src/cpu/x86/vm/x86_32.ad
Index Unified diffs Context diffs Sdiffs Patch New Old Previous File Next File hotspot Cdiff src/cpu/x86/vm/x86_32.ad

src/cpu/x86/vm/x86_32.ad

Print this page
rev 5902 : 8027754: Enable loop optimizations for loops with MathExact inside

*** 1540,1562 **** const RegMask Matcher::method_handle_invoke_SP_save_mask() { return EBP_REG_mask(); } - const RegMask Matcher::mathExactI_result_proj_mask() { - return EAX_REG_mask(); - } - - const RegMask Matcher::mathExactL_result_proj_mask() { - ShouldNotReachHere(); - return RegMask(); - } - - const RegMask Matcher::mathExactI_flags_proj_mask() { - return INT_FLAGS_mask(); - } - // Returns true if the high 32 bits of the value is known to be zero. bool is_operand_hi32_zero(Node* n) { int opc = n->Opcode(); if (opc == Op_AndL) { Node* o2 = n->in(2); --- 1540,1549 ----
*** 7543,7590 **** %} //----------Arithmetic Instructions-------------------------------------------- //----------Addition Instructions---------------------------------------------- - instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) - %{ - match(AddExactI dst src); - effect(DEF cr); - - format %{ "ADD $dst, $src\t# addExact int" %} - ins_encode %{ - __ addl($dst$$Register, $src$$Register); - %} - ins_pipe(ialu_reg_reg); - %} - - instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) - %{ - match(AddExactI dst src); - effect(DEF cr); - - format %{ "ADD $dst, $src\t# addExact int" %} - ins_encode %{ - __ addl($dst$$Register, $src$$constant); - %} - ins_pipe(ialu_reg_reg); - %} - - instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) - %{ - match(AddExactI dst (LoadI src)); - effect(DEF cr); - - ins_cost(125); - format %{ "ADD $dst,$src\t# addExact int" %} - ins_encode %{ - __ addl($dst$$Register, $src$$Address); - %} - ins_pipe( ialu_reg_mem ); - %} - - // Integer Addition Instructions instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (AddI dst src)); effect(KILL cr); --- 7530,7539 ----
*** 7890,7936 **** ins_pipe( pipe_cmpxchg ); %} //----------Subtraction Instructions------------------------------------------- - instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) - %{ - match(SubExactI dst src); - effect(DEF cr); - - format %{ "SUB $dst, $src\t# subExact int" %} - ins_encode %{ - __ subl($dst$$Register, $src$$Register); - %} - ins_pipe(ialu_reg_reg); - %} - - instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) - %{ - match(SubExactI dst src); - effect(DEF cr); - - format %{ "SUB $dst, $src\t# subExact int" %} - ins_encode %{ - __ subl($dst$$Register, $src$$constant); - %} - ins_pipe(ialu_reg_reg); - %} - - instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) - %{ - match(SubExactI dst (LoadI src)); - effect(DEF cr); - - ins_cost(125); - format %{ "SUB $dst,$src\t# subExact int" %} - ins_encode %{ - __ subl($dst$$Register, $src$$Address); - %} - ins_pipe( ialu_reg_mem ); - %} - // Integer Subtraction Instructions instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (SubI dst src)); effect(KILL cr); --- 7839,7848 ----
*** 7995,8015 **** opcode(0xF7,0x03); // Opcode F7 /3 ins_encode( OpcP, RegOpc( dst ) ); ins_pipe( ialu_reg ); %} - instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{ - match(NegExactI dst); - effect(DEF cr); - - format %{ "NEG $dst\t# negExact int"%} - ins_encode %{ - __ negl($dst$$Register); - %} - ins_pipe(ialu_reg); - %} - //----------Multiplication/Division Instructions------------------------------- // Integer Multiplication Instructions // Multiply Register instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (MulI dst src)); --- 7907,7916 ----
*** 8217,8266 **** "ADD EDX,$tmp" %} ins_encode( long_multiply_con( dst, src, tmp ) ); ins_pipe( pipe_slow ); %} - instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) - %{ - match(MulExactI dst src); - effect(DEF cr); - - ins_cost(300); - format %{ "IMUL $dst, $src\t# mulExact int" %} - ins_encode %{ - __ imull($dst$$Register, $src$$Register); - %} - ins_pipe(ialu_reg_reg_alu0); - %} - - instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr) - %{ - match(MulExactI src imm); - effect(DEF cr); - - ins_cost(300); - format %{ "IMUL $dst, $src, $imm\t# mulExact int" %} - ins_encode %{ - __ imull($dst$$Register, $src$$Register, $imm$$constant); - %} - ins_pipe(ialu_reg_reg_alu0); - %} - - instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) - %{ - match(MulExactI dst (LoadI src)); - effect(DEF cr); - - ins_cost(350); - format %{ "IMUL $dst, $src\t# mulExact int" %} - ins_encode %{ - __ imull($dst$$Register, $src$$Address); - %} - ins_pipe(ialu_reg_mem_alu0); - %} - - // Integer DIV with Register instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ match(Set rax (DivI rax div)); effect(KILL rdx, KILL cr); size(26); --- 8118,8127 ----
*** 9122,9131 **** --- 8983,9079 ---- /* If I enable this, I encourage spilling in the inner loop of compress. instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); */ + //----------Overflow Math Instructions----------------------------------------- + + instruct addofI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) + %{ + match(Set cr (OverflowAddI op1 op2)); + effect(DEF cr, USE_KILL op1, USE op2); + + format %{ "ADD $op1, $op2 #overflow check int" %} + + ins_encode %{ + __ addl($op1$$Register, $op2$$Register); + %} + ins_pipe(ialu_reg_reg); + %} + + instruct addofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) + %{ + match(Set cr (OverflowAddI op1 op2)); + effect(DEF cr, USE_KILL op1, USE op2); + + format %{ "ADD $op1, $op2 #overflow check int" %} + + ins_encode %{ + __ addl($op1$$Register, $op2$$constant); + %} + ins_pipe(ialu_reg_reg); + %} + + instruct subofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) + %{ + match(Set cr (OverflowSubI op1 op2)); + effect(DEF cr, USE op1, USE op2); + + format %{ "CMP $op1, $op2 #overflow check int" %} + ins_encode %{ + __ cmpl($op1$$Register, $op2$$Register); + %} + ins_pipe(ialu_reg_reg); + %} + + instruct subofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) + %{ + match(Set cr (OverflowSubI op1 op2)); + effect(DEF cr, USE op1, USE op2); + + format %{ "CMP $op1, $op2 #overflow check int" %} + ins_encode %{ + __ cmpl($op1$$Register, $op2$$constant); + %} + ins_pipe(ialu_reg_reg); + %} + + instruct negofI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) + %{ + match(Set cr (OverflowSubI zero op2)); + effect(DEF cr, USE_KILL op2); + + format %{ "NEG $op2 #overflow check int" %} + ins_encode %{ + __ negl($op2$$Register); + %} + ins_pipe(ialu_reg_reg); + %} + + instruct mulofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) + %{ + match(Set cr (OverflowMulI op1 op2)); + effect(DEF cr, USE_KILL op1, USE op2); + + format %{ "IMUL $op1, $op2 #overflow check int" %} + ins_encode %{ + __ imull($op1$$Register, $op2$$Register); + %} + ins_pipe(ialu_reg_reg_alu0); + %} + + instruct mulofI_rReg_imm(eFlagsReg cr, eAXRegI op1, rRegI op2, immI op3) + %{ + match(Set cr (OverflowMulI op2 op3)); + effect(DEF cr, KILL op1, USE op2, USE op3); + + format %{ "IMUL $op1, $op2, $op3 #overflow check int" %} + ins_encode %{ + __ imull($op1$$Register, $op2$$Register, $op3$$constant); + %} + ins_pipe(ialu_reg_reg_alu0); + %} //----------Long Instructions------------------------------------------------ // Add Long Register with Register instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ match(Set dst (AddL dst src));
src/cpu/x86/vm/x86_32.ad
Index Unified diffs Context diffs Sdiffs Patch New Old Previous File Next File