1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1275
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1290
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1297
1298
1299 //=============================================================================
1300 uint size_exception_handler() {
1301 // NativeCall instruction size is the same as NativeJump.
1302 // exception handler starts out as jump and can be patched to
1303 // a call be deoptimization. (4932387)
1304 // Note that this value is also credited (in output.cpp) to
1305 // the size of the code section.
1306 return NativeJump::instruction_size;
1307 }
1308
1309 // Emit exception handler code. Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1312
1313 // Note that the code buffer's insts_mark is always relative to insts.
1314 // That's why we must use the macroassembler to generate a handler.
1315 MacroAssembler _masm(&cbuf);
1316 address base =
1317 __ start_a_stub(size_exception_handler());
1318 if (base == NULL) return 0; // CodeBuffer::expand failed
1319 int offset = __ offset();
1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322 __ end_a_stub();
1323 return offset;
1324 }
1325
1326 uint size_deopt_handler() {
1327 // NativeCall instruction size is the same as NativeJump.
1328 // exception handler starts out as jump and can be patched to
1329 // a call be deoptimization. (4932387)
1330 // Note that this value is also credited (in output.cpp) to
1331 // the size of the code section.
1332 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1334
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1337
1338 // Note that the code buffer's insts_mark is always relative to insts.
1339 // That's why we must use the macroassembler to generate a handler.
1340 MacroAssembler _masm(&cbuf);
1341 address base =
1342 __ start_a_stub(size_exception_handler());
1343 if (base == NULL) return 0; // CodeBuffer::expand failed
1344 int offset = __ offset();
1345 InternalAddress here(__ pc());
1346 __ pushptr(here.addr());
1347
1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350 __ end_a_stub();
1351 return offset;
1352 }
1353
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355 return regnum - 32; // The FP registers are in the second chunk
1356 }
1357
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360 return true;
1361 }
1362
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 // this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368 // The passed offset is relative to address of the branch.
1369 // On 86 a branch displacement is calculated relative to address
1370 // of a next instruction.
1371 offset -= br_size;
1372
1373 // the short version of jmpConUCF2 contains multiple branches,
1374 // making the reach slightly less
1375 if (rule == jmpConUCF2_rule)
1376 return (-126 <= offset && offset <= 125);
1377 return (-128 <= offset && offset <= 127);
1378 }
1379
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382 return false;
1383 }
1384
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1387
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1390
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1393
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1396
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers? True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1404
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1408
1409 bool Matcher::narrow_oop_use_complex_address() {
1410 ShouldNotCallThis();
1411 return true;
1412 }
1413
1414 bool Matcher::narrow_klass_use_complex_address() {
1415 ShouldNotCallThis();
1416 return true;
1417 }
1418
1419
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers. Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1425
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed. Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece. Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1431
1432
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434 // Get the memory operand from the node
1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438 uint opcnt = 1; // First operand
1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440 while( idx >= skipped+num_edges ) {
1441 skipped += num_edges;
1442 opcnt++; // Bump operand count
1443 assert( opcnt < numopnds, "Accessing non-existent operand" );
1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445 }
1446
1447 MachOper *memory = node->_opnds[opcnt];
1448 MachOper *new_memory = NULL;
1449 switch (memory->opcode()) {
1450 case DIRECT:
1451 case INDOFFSET32X:
1452 // No transformation necessary.
1453 return;
1454 case INDIRECT:
1455 new_memory = new (C) indirect_win95_safeOper( );
1456 break;
1457 case INDOFFSET8:
1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDOFFSET32:
1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXOFFSET:
1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465 break;
1466 case INDINDEXSCALE:
1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468 break;
1469 case INDINDEXSCALEOFFSET:
1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471 break;
1472 case LOAD_LONG_INDIRECT:
1473 case LOAD_LONG_INDOFFSET32:
1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475 return;
1476 default:
1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478 return;
1479 }
1480 node->_opnds[opcnt] = new_memory;
1481 }
1482
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1486
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1490
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1493
1494 // Return whether or not this register is ever used as an argument. This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499 if( reg == ECX_num || reg == EDX_num ) return true;
1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502 return false;
1503 }
1504
1505 bool Matcher::is_spillable_arg( int reg ) {
1506 return can_be_java_arg(reg);
1507 }
1508
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510 // Use hardware integer DIV instruction when
1511 // it is faster than a code which use multiply.
1512 // Only when constant divisor fits into 32 bit
1513 // (min_jint is excluded to get only correct
1514 // positive 32 bit values from negative).
1515 return VM_Version::has_fast_idiv() &&
1516 (divisor == (int)divisor && divisor != min_jint);
1517 }
1518
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521 return EAX_REG_mask();
1522 }
1523
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 // Returns true if the high 32 bits of the value is known to be zero.
1546 bool is_operand_hi32_zero(Node* n) {
1547 int opc = n->Opcode();
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1559
1560 %}
1561
1562 //----------ENCODING BLOCK-----------------------------------------------------
1563 // This block specifies the encoding classes used by the compiler to output
1564 // byte streams. Encoding classes generate functions which are called by
1565 // Machine Instruction Nodes in order to generate the bit encoding of the
1566 // instruction. Operands specify their base encoding interface with the
1567 // interface keyword. There are currently supported four interfaces,
1568 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1569 // operand to generate a function which returns its register number when
1570 // queried. CONST_INTER causes an operand to generate a function which
1571 // returns the value of the constant when queried. MEMORY_INTER causes an
1572 // operand to generate four functions which return the Base Register, the
1573 // Index Register, the Scale Value, and the Offset Value of the operand when
1574 // queried. COND_INTER causes an operand to generate six functions which
1575 // return the encoding code (ie - encoding bits for the instruction)
1576 // associated with each basic boolean condition for a conditional instruction.
1577 // Instructions specify two basic values for encoding. They use the
1578 // ins_encode keyword to specify their encoding class (which must be one of
1579 // the class names specified in the encoding block), and they use the
1580 // opcode keyword to specify, in order, their primary, secondary, and
1581 // tertiary opcode. Only the opcode sections which a particular instruction
1582 // needs for encoding need to be specified.
1583 encode %{
1584 // Build emit functions for each basic byte or larger field in the intel
1585 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1586 // code in the enc_class source block. Emit functions will live in the
1587 // main source block for now. In future, we can generalize this by
1588 // adding a syntax that specifies the sizes of fields in an order,
1589 // so that the adlc can build the emit functions automagically
1590
1591 // Emit primary opcode
1592 enc_class OpcP %{
1593 emit_opcode(cbuf, $primary);
1594 %}
1595
1596 // Emit secondary opcode
1597 enc_class OpcS %{
1598 emit_opcode(cbuf, $secondary);
1599 %}
1600
1601 // Emit opcode directly
1602 enc_class Opcode(immI d8) %{
1603 emit_opcode(cbuf, $d8$$constant);
1604 %}
1605
1606 enc_class SizePrefix %{
1607 emit_opcode(cbuf,0x66);
1608 %}
1609
1610 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1611 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1612 %}
1613
1614 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1615 emit_opcode(cbuf,$opcode$$constant);
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1618
1619 enc_class mov_r32_imm0( rRegI dst ) %{
1620 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1621 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1622 %}
1623
1624 enc_class cdq_enc %{
1625 // Full implementation of Java idiv and irem; checks for
1626 // special case as described in JVM spec., p.243 & p.271.
1627 //
1628 // normal case special case
1629 //
1630 // input : rax,: dividend min_int
1631 // reg: divisor -1
1632 //
1633 // output: rax,: quotient (= rax, idiv reg) min_int
1634 // rdx: remainder (= rax, irem reg) 0
1635 //
1636 // Code sequnce:
1637 //
1638 // 81 F8 00 00 00 80 cmp rax,80000000h
1639 // 0F 85 0B 00 00 00 jne normal_case
1640 // 33 D2 xor rdx,edx
1641 // 83 F9 FF cmp rcx,0FFh
1642 // 0F 84 03 00 00 00 je done
1643 // normal_case:
1644 // 99 cdq
1645 // F7 F9 idiv rax,ecx
1646 // done:
1647 //
1648 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1649 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1651 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1652 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1653 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1654 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1655 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1657 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1659 // normal_case:
1660 emit_opcode(cbuf,0x99); // cdq
1661 // idiv (note: must be emitted by the user of this rule)
1662 // normal:
1663 %}
1664
1665 // Dense encoding for older common ops
1666 enc_class Opc_plus(immI opcode, rRegI reg) %{
1667 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1668 %}
1669
1670
1671 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1672 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1673 // Check for 8-bit immediate, and set sign extend bit in opcode
1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1675 emit_opcode(cbuf, $primary | 0x02);
1676 }
1677 else { // If 32-bit immediate
1678 emit_opcode(cbuf, $primary);
1679 }
1680 %}
1681
1682 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1683 // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02); }
1687 else { // If 32-bit immediate
1688 emit_opcode(cbuf, $primary);
1689 }
1690 // Emit r/m byte with secondary opcode, after primary opcode.
1691 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1692 %}
1693
1694 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 $$$emit8$imm$$constant;
1698 }
1699 else { // If 32-bit immediate
1700 // Output immediate
1701 $$$emit32$imm$$constant;
1702 }
1703 %}
1704
1705 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1706 // Emit primary opcode and set sign-extend bit
1707 // Check for 8-bit immediate, and set sign extend bit in opcode
1708 int con = (int)$imm$$constant; // Throw away top bits
1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1710 // Emit r/m byte with secondary opcode, after primary opcode.
1711 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1713 else emit_d32(cbuf,con);
1714 %}
1715
1716 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with tertiary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1726
1727 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1728 emit_cc(cbuf, $secondary, $dst$$reg );
1729 %}
1730
1731 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1732 int destlo = $dst$$reg;
1733 int desthi = HIGH_FROM_LOW(destlo);
1734 // bswap lo
1735 emit_opcode(cbuf, 0x0F);
1736 emit_cc(cbuf, 0xC8, destlo);
1737 // bswap hi
1738 emit_opcode(cbuf, 0x0F);
1739 emit_cc(cbuf, 0xC8, desthi);
1740 // xchg lo and hi
1741 emit_opcode(cbuf, 0x87);
1742 emit_rm(cbuf, 0x3, destlo, desthi);
1743 %}
1744
1745 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1746 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1747 %}
1748
1749 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1750 $$$emit8$primary;
1751 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1752 %}
1753
1754 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1755 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1756 emit_d8(cbuf, op >> 8 );
1757 emit_d8(cbuf, op & 255);
1758 %}
1759
1760 // emulate a CMOV with a conditional branch around a MOV
1761 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1762 // Invert sense of branch from sense of CMOV
1763 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1764 emit_d8( cbuf, $brOffs$$constant );
1765 %}
1766
1767 enc_class enc_PartialSubtypeCheck( ) %{
1768 Register Redi = as_Register(EDI_enc); // result register
1769 Register Reax = as_Register(EAX_enc); // super class
1770 Register Recx = as_Register(ECX_enc); // killed
1771 Register Resi = as_Register(ESI_enc); // sub class
1772 Label miss;
1773
1774 MacroAssembler _masm(&cbuf);
1775 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1776 NULL, &miss,
1777 /*set_cond_codes:*/ true);
1778 if ($primary) {
1779 __ xorptr(Redi, Redi);
1780 }
1781 __ bind(miss);
1782 %}
1783
1784 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1785 MacroAssembler masm(&cbuf);
1786 int start = masm.offset();
1787 if (UseSSE >= 2) {
1788 if (VerifyFPU) {
1789 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1790 }
1791 } else {
1792 // External c_calling_convention expects the FPU stack to be 'clean'.
1793 // Compiled code leaves it dirty. Do cleanup now.
1794 masm.empty_FPU_stack();
1795 }
1796 if (sizeof_FFree_Float_Stack_All == -1) {
1797 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1798 } else {
1799 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1800 }
1801 %}
1802
1803 enc_class Verify_FPU_For_Leaf %{
1804 if( VerifyFPU ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1807 }
1808 %}
1809
1810 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1811 // This is the instruction starting address for relocation info.
1812 cbuf.set_insts_mark();
1813 $$$emit8$primary;
1814 // CALL directly to the runtime
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1816 runtime_call_Relocation::spec(), RELOC_IMM32 );
1817
1818 if (UseSSE >= 2) {
1819 MacroAssembler _masm(&cbuf);
1820 BasicType rt = tf()->return_type();
1821
1822 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1823 // A C runtime call where the return value is unused. In SSE2+
1824 // mode the result needs to be removed from the FPU stack. It's
1825 // likely that this function call could be removed by the
1826 // optimizer if the C function is a pure function.
1827 __ ffree(0);
1828 } else if (rt == T_FLOAT) {
1829 __ lea(rsp, Address(rsp, -4));
1830 __ fstp_s(Address(rsp, 0));
1831 __ movflt(xmm0, Address(rsp, 0));
1832 __ lea(rsp, Address(rsp, 4));
1833 } else if (rt == T_DOUBLE) {
1834 __ lea(rsp, Address(rsp, -8));
1835 __ fstp_d(Address(rsp, 0));
1836 __ movdbl(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 8));
1838 }
1839 }
1840 %}
1841
1842
1843 enc_class pre_call_resets %{
1844 // If method sets FPU control word restore it here
1845 debug_only(int off0 = cbuf.insts_size());
1846 if (ra_->C->in_24_bit_fp_mode()) {
1847 MacroAssembler _masm(&cbuf);
1848 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1849 }
1850 if (ra_->C->max_vector_size() > 16) {
1851 // Clear upper bits of YMM registers when current compiled code uses
1852 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1853 MacroAssembler _masm(&cbuf);
1854 __ vzeroupper();
1855 }
1856 debug_only(int off1 = cbuf.insts_size());
1857 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1858 %}
1859
1860 enc_class post_call_FPU %{
1861 // If method sets FPU control word do it here also
1862 if (Compile::current()->in_24_bit_fp_mode()) {
1863 MacroAssembler masm(&cbuf);
1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1865 }
1866 %}
1867
1868 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1869 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1870 // who we intended to call.
1871 cbuf.set_insts_mark();
1872 $$$emit8$primary;
1873 if (!_method) {
1874 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1875 runtime_call_Relocation::spec(), RELOC_IMM32 );
1876 } else if (_optimized_virtual) {
1877 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1878 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1879 } else {
1880 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1881 static_call_Relocation::spec(), RELOC_IMM32 );
1882 }
1883 if (_method) { // Emit stub for static call.
1884 CompiledStaticCall::emit_to_interp_stub(cbuf);
1885 }
1886 %}
1887
1888 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1889 MacroAssembler _masm(&cbuf);
1890 __ ic_call((address)$meth$$method);
1891 %}
1892
1893 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1894 int disp = in_bytes(Method::from_compiled_offset());
1895 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1896
1897 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1898 cbuf.set_insts_mark();
1899 $$$emit8$primary;
1900 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1901 emit_d8(cbuf, disp); // Displacement
1902
1903 %}
1904
1905 // Following encoding is no longer used, but may be restored if calling
1906 // convention changes significantly.
1907 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1908 //
1909 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1910 // // int ic_reg = Matcher::inline_cache_reg();
1911 // // int ic_encode = Matcher::_regEncode[ic_reg];
1912 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1913 // // int imo_encode = Matcher::_regEncode[imo_reg];
1914 //
1915 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1916 // // // so we load it immediately before the call
1917 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1918 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1919 //
1920 // // xor rbp,ebp
1921 // emit_opcode(cbuf, 0x33);
1922 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1923 //
1924 // // CALL to interpreter.
1925 // cbuf.set_insts_mark();
1926 // $$$emit8$primary;
1927 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1928 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1929 // %}
1930
1931 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1932 $$$emit8$primary;
1933 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1934 $$$emit8$shift$$constant;
1935 %}
1936
1937 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1941 $$$emit32$src$$constant;
1942 %}
1943
1944 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 emit_opcode(cbuf, $primary + $dst$$reg);
1948 $$$emit32$src$$constant;
1949 %}
1950
1951 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1952 // Load immediate does not have a zero or sign extended version
1953 // for 8-bit immediates
1954 int dst_enc = $dst$$reg;
1955 int src_con = $src$$constant & 0x0FFFFFFFFL;
1956 if (src_con == 0) {
1957 // xor dst, dst
1958 emit_opcode(cbuf, 0x33);
1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1960 } else {
1961 emit_opcode(cbuf, $primary + dst_enc);
1962 emit_d32(cbuf, src_con);
1963 }
1964 %}
1965
1966 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1967 // Load immediate does not have a zero or sign extended version
1968 // for 8-bit immediates
1969 int dst_enc = $dst$$reg + 2;
1970 int src_con = ((julong)($src$$constant)) >> 32;
1971 if (src_con == 0) {
1972 // xor dst, dst
1973 emit_opcode(cbuf, 0x33);
1974 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1975 } else {
1976 emit_opcode(cbuf, $primary + dst_enc);
1977 emit_d32(cbuf, src_con);
1978 }
1979 %}
1980
1981
1982 // Encode a reg-reg copy. If it is useless, then empty encoding.
1983 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1984 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1985 %}
1986
1987 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1988 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1989 %}
1990
1991 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 %}
1994
1995 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1996 $$$emit8$primary;
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
1999
2000 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$secondary;
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2007 %}
2008
2009 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2010 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2011 %}
2012
2013 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2014 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2015 %}
2016
2017 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2018 // Output immediate
2019 $$$emit32$src$$constant;
2020 %}
2021
2022 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2023 // Output Float immediate bits
2024 jfloat jf = $src$$constant;
2025 int jf_as_bits = jint_cast( jf );
2026 emit_d32(cbuf, jf_as_bits);
2027 %}
2028
2029 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2030 // Output Float immediate bits
2031 jfloat jf = $src$$constant;
2032 int jf_as_bits = jint_cast( jf );
2033 emit_d32(cbuf, jf_as_bits);
2034 %}
2035
2036 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2037 // Output immediate
2038 $$$emit16$src$$constant;
2039 %}
2040
2041 enc_class Con_d32(immI src) %{
2042 emit_d32(cbuf,$src$$constant);
2043 %}
2044
2045 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2046 // Output immediate memory reference
2047 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2048 emit_d32(cbuf, 0x00);
2049 %}
2050
2051 enc_class lock_prefix( ) %{
2052 if( os::is_MP() )
2053 emit_opcode(cbuf,0xF0); // [Lock]
2054 %}
2055
2056 // Cmp-xchg long value.
2057 // Note: we need to swap rbx, and rcx before and after the
2058 // cmpxchg8 instruction because the instruction uses
2059 // rcx as the high order word of the new value to store but
2060 // our register encoding uses rbx,.
2061 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2062
2063 // XCHG rbx,ecx
2064 emit_opcode(cbuf,0x87);
2065 emit_opcode(cbuf,0xD9);
2066 // [Lock]
2067 if( os::is_MP() )
2068 emit_opcode(cbuf,0xF0);
2069 // CMPXCHG8 [Eptr]
2070 emit_opcode(cbuf,0x0F);
2071 emit_opcode(cbuf,0xC7);
2072 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2073 // XCHG rbx,ecx
2074 emit_opcode(cbuf,0x87);
2075 emit_opcode(cbuf,0xD9);
2076 %}
2077
2078 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082
2083 // CMPXCHG [Eptr]
2084 emit_opcode(cbuf,0x0F);
2085 emit_opcode(cbuf,0xB1);
2086 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2087 %}
2088
2089 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2090 int res_encoding = $res$$reg;
2091
2092 // MOV res,0
2093 emit_opcode( cbuf, 0xB8 + res_encoding);
2094 emit_d32( cbuf, 0 );
2095 // JNE,s fail
2096 emit_opcode(cbuf,0x75);
2097 emit_d8(cbuf, 5 );
2098 // MOV res,1
2099 emit_opcode( cbuf, 0xB8 + res_encoding);
2100 emit_d32( cbuf, 1 );
2101 // fail:
2102 %}
2103
2104 enc_class set_instruction_start( ) %{
2105 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2106 %}
2107
2108 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2109 int reg_encoding = $ereg$$reg;
2110 int base = $mem$$base;
2111 int index = $mem$$index;
2112 int scale = $mem$$scale;
2113 int displace = $mem$$disp;
2114 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2115 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2116 %}
2117
2118 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2119 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2120 int base = $mem$$base;
2121 int index = $mem$$index;
2122 int scale = $mem$$scale;
2123 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2124 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2125 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2126 %}
2127
2128 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2129 int r1, r2;
2130 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2131 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2132 emit_opcode(cbuf,0x0F);
2133 emit_opcode(cbuf,$tertiary);
2134 emit_rm(cbuf, 0x3, r1, r2);
2135 emit_d8(cbuf,$cnt$$constant);
2136 emit_d8(cbuf,$primary);
2137 emit_rm(cbuf, 0x3, $secondary, r1);
2138 emit_d8(cbuf,$cnt$$constant);
2139 %}
2140
2141 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2142 emit_opcode( cbuf, 0x8B ); // Move
2143 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2144 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2145 emit_d8(cbuf,$primary);
2146 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2147 emit_d8(cbuf,$cnt$$constant-32);
2148 }
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2151 emit_d8(cbuf,31);
2152 %}
2153
2154 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2155 int r1, r2;
2156 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2157 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2158
2159 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2160 emit_rm(cbuf, 0x3, r1, r2);
2161 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2162 emit_opcode(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, r1);
2164 emit_d8(cbuf,$cnt$$constant-32);
2165 }
2166 emit_opcode(cbuf,0x33); // XOR r2,r2
2167 emit_rm(cbuf, 0x3, r2, r2);
2168 %}
2169
2170 // Clone of RegMem but accepts an extra parameter to access each
2171 // half of a double in memory; it never needs relocation info.
2172 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2173 emit_opcode(cbuf,$opcode$$constant);
2174 int reg_encoding = $rm_reg$$reg;
2175 int base = $mem$$base;
2176 int index = $mem$$index;
2177 int scale = $mem$$scale;
2178 int displace = $mem$$disp + $disp_for_half$$constant;
2179 relocInfo::relocType disp_reloc = relocInfo::none;
2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2181 %}
2182
2183 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2184 //
2185 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2186 // and it never needs relocation information.
2187 // Frequently used to move data between FPU's Stack Top and memory.
2188 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2189 int rm_byte_opcode = $rm_opcode$$constant;
2190 int base = $mem$$base;
2191 int index = $mem$$index;
2192 int scale = $mem$$scale;
2193 int displace = $mem$$disp;
2194 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2195 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2196 %}
2197
2198 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2199 int rm_byte_opcode = $rm_opcode$$constant;
2200 int base = $mem$$base;
2201 int index = $mem$$index;
2202 int scale = $mem$$scale;
2203 int displace = $mem$$disp;
2204 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2205 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2206 %}
2207
2208 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2209 int reg_encoding = $dst$$reg;
2210 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2211 int index = 0x04; // 0x04 indicates no index
2212 int scale = 0x00; // 0x00 indicates no scale
2213 int displace = $src1$$constant; // 0x00 indicates no displacement
2214 relocInfo::relocType disp_reloc = relocInfo::none;
2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2216 %}
2217
2218 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2219 // Compare dst,src
2220 emit_opcode(cbuf,0x3B);
2221 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2222 // jmp dst < src around move
2223 emit_opcode(cbuf,0x7C);
2224 emit_d8(cbuf,2);
2225 // move dst,src
2226 emit_opcode(cbuf,0x8B);
2227 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2228 %}
2229
2230 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2231 // Compare dst,src
2232 emit_opcode(cbuf,0x3B);
2233 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2234 // jmp dst > src around move
2235 emit_opcode(cbuf,0x7F);
2236 emit_d8(cbuf,2);
2237 // move dst,src
2238 emit_opcode(cbuf,0x8B);
2239 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2240 %}
2241
2242 enc_class enc_FPR_store(memory mem, regDPR src) %{
2243 // If src is FPR1, we can just FST to store it.
2244 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2245 int reg_encoding = 0x2; // Just store
2246 int base = $mem$$base;
2247 int index = $mem$$index;
2248 int scale = $mem$$scale;
2249 int displace = $mem$$disp;
2250 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2251 if( $src$$reg != FPR1L_enc ) {
2252 reg_encoding = 0x3; // Store & pop
2253 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2254 emit_d8( cbuf, 0xC0-1+$src$$reg );
2255 }
2256 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2257 emit_opcode(cbuf,$primary);
2258 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2259 %}
2260
2261 enc_class neg_reg(rRegI dst) %{
2262 // NEG $dst
2263 emit_opcode(cbuf,0xF7);
2264 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2265 %}
2266
2267 enc_class setLT_reg(eCXRegI dst) %{
2268 // SETLT $dst
2269 emit_opcode(cbuf,0x0F);
2270 emit_opcode(cbuf,0x9C);
2271 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2272 %}
2273
2274 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2275 int tmpReg = $tmp$$reg;
2276
2277 // SUB $p,$q
2278 emit_opcode(cbuf,0x2B);
2279 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2280 // SBB $tmp,$tmp
2281 emit_opcode(cbuf,0x1B);
2282 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2283 // AND $tmp,$y
2284 emit_opcode(cbuf,0x23);
2285 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2286 // ADD $p,$tmp
2287 emit_opcode(cbuf,0x03);
2288 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2289 %}
2290
2291 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2292 // TEST shift,32
2293 emit_opcode(cbuf,0xF7);
2294 emit_rm(cbuf, 0x3, 0, ECX_enc);
2295 emit_d32(cbuf,0x20);
2296 // JEQ,s small
2297 emit_opcode(cbuf, 0x74);
2298 emit_d8(cbuf, 0x04);
2299 // MOV $dst.hi,$dst.lo
2300 emit_opcode( cbuf, 0x8B );
2301 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2302 // CLR $dst.lo
2303 emit_opcode(cbuf, 0x33);
2304 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2305 // small:
2306 // SHLD $dst.hi,$dst.lo,$shift
2307 emit_opcode(cbuf,0x0F);
2308 emit_opcode(cbuf,0xA5);
2309 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2310 // SHL $dst.lo,$shift"
2311 emit_opcode(cbuf,0xD3);
2312 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2313 %}
2314
2315 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2316 // TEST shift,32
2317 emit_opcode(cbuf,0xF7);
2318 emit_rm(cbuf, 0x3, 0, ECX_enc);
2319 emit_d32(cbuf,0x20);
2320 // JEQ,s small
2321 emit_opcode(cbuf, 0x74);
2322 emit_d8(cbuf, 0x04);
2323 // MOV $dst.lo,$dst.hi
2324 emit_opcode( cbuf, 0x8B );
2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2326 // CLR $dst.hi
2327 emit_opcode(cbuf, 0x33);
2328 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2329 // small:
2330 // SHRD $dst.lo,$dst.hi,$shift
2331 emit_opcode(cbuf,0x0F);
2332 emit_opcode(cbuf,0xAD);
2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2334 // SHR $dst.hi,$shift"
2335 emit_opcode(cbuf,0xD3);
2336 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2337 %}
2338
2339 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2340 // TEST shift,32
2341 emit_opcode(cbuf,0xF7);
2342 emit_rm(cbuf, 0x3, 0, ECX_enc);
2343 emit_d32(cbuf,0x20);
2344 // JEQ,s small
2345 emit_opcode(cbuf, 0x74);
2346 emit_d8(cbuf, 0x05);
2347 // MOV $dst.lo,$dst.hi
2348 emit_opcode( cbuf, 0x8B );
2349 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2350 // SAR $dst.hi,31
2351 emit_opcode(cbuf, 0xC1);
2352 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2353 emit_d8(cbuf, 0x1F );
2354 // small:
2355 // SHRD $dst.lo,$dst.hi,$shift
2356 emit_opcode(cbuf,0x0F);
2357 emit_opcode(cbuf,0xAD);
2358 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2359 // SAR $dst.hi,$shift"
2360 emit_opcode(cbuf,0xD3);
2361 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2362 %}
2363
2364
2365 // ----------------- Encodings for floating point unit -----------------
2366 // May leave result in FPU-TOS or FPU reg depending on opcodes
2367 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2368 $$$emit8$primary;
2369 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2370 %}
2371
2372 // Pop argument in FPR0 with FSTP ST(0)
2373 enc_class PopFPU() %{
2374 emit_opcode( cbuf, 0xDD );
2375 emit_d8( cbuf, 0xD8 );
2376 %}
2377
2378 // !!!!! equivalent to Pop_Reg_F
2379 enc_class Pop_Reg_DPR( regDPR dst ) %{
2380 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2381 emit_d8( cbuf, 0xD8+$dst$$reg );
2382 %}
2383
2384 enc_class Push_Reg_DPR( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xD9 );
2386 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2387 %}
2388
2389 enc_class strictfp_bias1( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xDB ); // FLD m80real
2391 emit_opcode( cbuf, 0x2D );
2392 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2393 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2394 emit_opcode( cbuf, 0xC8+$dst$$reg );
2395 %}
2396
2397 enc_class strictfp_bias2( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xDB ); // FLD m80real
2399 emit_opcode( cbuf, 0x2D );
2400 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2401 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2402 emit_opcode( cbuf, 0xC8+$dst$$reg );
2403 %}
2404
2405 // Special case for moving an integer register to a stack slot.
2406 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2407 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2408 %}
2409
2410 // Special case for moving a register to a stack slot.
2411 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2412 // Opcode already emitted
2413 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2414 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2415 emit_d32(cbuf, $dst$$disp); // Displacement
2416 %}
2417
2418 // Push the integer in stackSlot 'src' onto FP-stack
2419 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2420 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2421 %}
2422
2423 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2424 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2425 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2426 %}
2427
2428 // Same as Pop_Mem_F except for opcode
2429 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2430 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2431 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2432 %}
2433
2434 enc_class Pop_Reg_FPR( regFPR dst ) %{
2435 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2436 emit_d8( cbuf, 0xD8+$dst$$reg );
2437 %}
2438
2439 enc_class Push_Reg_FPR( regFPR dst ) %{
2440 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2441 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2442 %}
2443
2444 // Push FPU's float to a stack-slot, and pop FPU-stack
2445 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2446 int pop = 0x02;
2447 if ($src$$reg != FPR1L_enc) {
2448 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2449 emit_d8( cbuf, 0xC0-1+$src$$reg );
2450 pop = 0x03;
2451 }
2452 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2453 %}
2454
2455 // Push FPU's double to a stack-slot, and pop FPU-stack
2456 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2457 int pop = 0x02;
2458 if ($src$$reg != FPR1L_enc) {
2459 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2460 emit_d8( cbuf, 0xC0-1+$src$$reg );
2461 pop = 0x03;
2462 }
2463 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2464 %}
2465
2466 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2467 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2468 int pop = 0xD0 - 1; // -1 since we skip FLD
2469 if ($src$$reg != FPR1L_enc) {
2470 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2471 emit_d8( cbuf, 0xC0-1+$src$$reg );
2472 pop = 0xD8;
2473 }
2474 emit_opcode( cbuf, 0xDD );
2475 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2476 %}
2477
2478
2479 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2480 // load dst in FPR0
2481 emit_opcode( cbuf, 0xD9 );
2482 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2483 if ($src$$reg != FPR1L_enc) {
2484 // fincstp
2485 emit_opcode (cbuf, 0xD9);
2486 emit_opcode (cbuf, 0xF7);
2487 // swap src with FPR1:
2488 // FXCH FPR1 with src
2489 emit_opcode(cbuf, 0xD9);
2490 emit_d8(cbuf, 0xC8-1+$src$$reg );
2491 // fdecstp
2492 emit_opcode (cbuf, 0xD9);
2493 emit_opcode (cbuf, 0xF6);
2494 }
2495 %}
2496
2497 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2498 MacroAssembler _masm(&cbuf);
2499 __ subptr(rsp, 8);
2500 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2501 __ fld_d(Address(rsp, 0));
2502 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2503 __ fld_d(Address(rsp, 0));
2504 %}
2505
2506 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2507 MacroAssembler _masm(&cbuf);
2508 __ subptr(rsp, 4);
2509 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2510 __ fld_s(Address(rsp, 0));
2511 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2512 __ fld_s(Address(rsp, 0));
2513 %}
2514
2515 enc_class Push_ResultD(regD dst) %{
2516 MacroAssembler _masm(&cbuf);
2517 __ fstp_d(Address(rsp, 0));
2518 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2519 __ addptr(rsp, 8);
2520 %}
2521
2522 enc_class Push_ResultF(regF dst, immI d8) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ fstp_s(Address(rsp, 0));
2525 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2526 __ addptr(rsp, $d8$$constant);
2527 %}
2528
2529 enc_class Push_SrcD(regD src) %{
2530 MacroAssembler _masm(&cbuf);
2531 __ subptr(rsp, 8);
2532 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2533 __ fld_d(Address(rsp, 0));
2534 %}
2535
2536 enc_class push_stack_temp_qword() %{
2537 MacroAssembler _masm(&cbuf);
2538 __ subptr(rsp, 8);
2539 %}
2540
2541 enc_class pop_stack_temp_qword() %{
2542 MacroAssembler _masm(&cbuf);
2543 __ addptr(rsp, 8);
2544 %}
2545
2546 enc_class push_xmm_to_fpr1(regD src) %{
2547 MacroAssembler _masm(&cbuf);
2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2549 __ fld_d(Address(rsp, 0));
2550 %}
2551
2552 enc_class Push_Result_Mod_DPR( regDPR src) %{
2553 if ($src$$reg != FPR1L_enc) {
2554 // fincstp
2555 emit_opcode (cbuf, 0xD9);
2556 emit_opcode (cbuf, 0xF7);
2557 // FXCH FPR1 with src
2558 emit_opcode(cbuf, 0xD9);
2559 emit_d8(cbuf, 0xC8-1+$src$$reg );
2560 // fdecstp
2561 emit_opcode (cbuf, 0xD9);
2562 emit_opcode (cbuf, 0xF6);
2563 }
2564 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2565 // // FSTP FPR$dst$$reg
2566 // emit_opcode( cbuf, 0xDD );
2567 // emit_d8( cbuf, 0xD8+$dst$$reg );
2568 %}
2569
2570 enc_class fnstsw_sahf_skip_parity() %{
2571 // fnstsw ax
2572 emit_opcode( cbuf, 0xDF );
2573 emit_opcode( cbuf, 0xE0 );
2574 // sahf
2575 emit_opcode( cbuf, 0x9E );
2576 // jnp ::skip
2577 emit_opcode( cbuf, 0x7B );
2578 emit_opcode( cbuf, 0x05 );
2579 %}
2580
2581 enc_class emitModDPR() %{
2582 // fprem must be iterative
2583 // :: loop
2584 // fprem
2585 emit_opcode( cbuf, 0xD9 );
2586 emit_opcode( cbuf, 0xF8 );
2587 // wait
2588 emit_opcode( cbuf, 0x9b );
2589 // fnstsw ax
2590 emit_opcode( cbuf, 0xDF );
2591 emit_opcode( cbuf, 0xE0 );
2592 // sahf
2593 emit_opcode( cbuf, 0x9E );
2594 // jp ::loop
2595 emit_opcode( cbuf, 0x0F );
2596 emit_opcode( cbuf, 0x8A );
2597 emit_opcode( cbuf, 0xF4 );
2598 emit_opcode( cbuf, 0xFF );
2599 emit_opcode( cbuf, 0xFF );
2600 emit_opcode( cbuf, 0xFF );
2601 %}
2602
2603 enc_class fpu_flags() %{
2604 // fnstsw_ax
2605 emit_opcode( cbuf, 0xDF);
2606 emit_opcode( cbuf, 0xE0);
2607 // test ax,0x0400
2608 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2609 emit_opcode( cbuf, 0xA9 );
2610 emit_d16 ( cbuf, 0x0400 );
2611 // // // This sequence works, but stalls for 12-16 cycles on PPro
2612 // // test rax,0x0400
2613 // emit_opcode( cbuf, 0xA9 );
2614 // emit_d32 ( cbuf, 0x00000400 );
2615 //
2616 // jz exit (no unordered comparison)
2617 emit_opcode( cbuf, 0x74 );
2618 emit_d8 ( cbuf, 0x02 );
2619 // mov ah,1 - treat as LT case (set carry flag)
2620 emit_opcode( cbuf, 0xB4 );
2621 emit_d8 ( cbuf, 0x01 );
2622 // sahf
2623 emit_opcode( cbuf, 0x9E);
2624 %}
2625
2626 enc_class cmpF_P6_fixup() %{
2627 // Fixup the integer flags in case comparison involved a NaN
2628 //
2629 // JNP exit (no unordered comparison, P-flag is set by NaN)
2630 emit_opcode( cbuf, 0x7B );
2631 emit_d8 ( cbuf, 0x03 );
2632 // MOV AH,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // SAHF
2636 emit_opcode( cbuf, 0x9E);
2637 // NOP // target for branch to avoid branch to branch
2638 emit_opcode( cbuf, 0x90);
2639 %}
2640
2641 // fnstsw_ax();
2642 // sahf();
2643 // movl(dst, nan_result);
2644 // jcc(Assembler::parity, exit);
2645 // movl(dst, less_result);
2646 // jcc(Assembler::below, exit);
2647 // movl(dst, equal_result);
2648 // jcc(Assembler::equal, exit);
2649 // movl(dst, greater_result);
2650
2651 // less_result = 1;
2652 // greater_result = -1;
2653 // equal_result = 0;
2654 // nan_result = -1;
2655
2656 enc_class CmpF_Result(rRegI dst) %{
2657 // fnstsw_ax();
2658 emit_opcode( cbuf, 0xDF);
2659 emit_opcode( cbuf, 0xE0);
2660 // sahf
2661 emit_opcode( cbuf, 0x9E);
2662 // movl(dst, nan_result);
2663 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2664 emit_d32( cbuf, -1 );
2665 // jcc(Assembler::parity, exit);
2666 emit_opcode( cbuf, 0x7A );
2667 emit_d8 ( cbuf, 0x13 );
2668 // movl(dst, less_result);
2669 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2670 emit_d32( cbuf, -1 );
2671 // jcc(Assembler::below, exit);
2672 emit_opcode( cbuf, 0x72 );
2673 emit_d8 ( cbuf, 0x0C );
2674 // movl(dst, equal_result);
2675 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2676 emit_d32( cbuf, 0 );
2677 // jcc(Assembler::equal, exit);
2678 emit_opcode( cbuf, 0x74 );
2679 emit_d8 ( cbuf, 0x05 );
2680 // movl(dst, greater_result);
2681 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2682 emit_d32( cbuf, 1 );
2683 %}
2684
2685
2686 // Compare the longs and set flags
2687 // BROKEN! Do Not use as-is
2688 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2689 // CMP $src1.hi,$src2.hi
2690 emit_opcode( cbuf, 0x3B );
2691 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2692 // JNE,s done
2693 emit_opcode(cbuf,0x75);
2694 emit_d8(cbuf, 2 );
2695 // CMP $src1.lo,$src2.lo
2696 emit_opcode( cbuf, 0x3B );
2697 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2698 // done:
2699 %}
2700
2701 enc_class convert_int_long( regL dst, rRegI src ) %{
2702 // mov $dst.lo,$src
2703 int dst_encoding = $dst$$reg;
2704 int src_encoding = $src$$reg;
2705 encode_Copy( cbuf, dst_encoding , src_encoding );
2706 // mov $dst.hi,$src
2707 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2708 // sar $dst.hi,31
2709 emit_opcode( cbuf, 0xC1 );
2710 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2711 emit_d8(cbuf, 0x1F );
2712 %}
2713
2714 enc_class convert_long_double( eRegL src ) %{
2715 // push $src.hi
2716 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2717 // push $src.lo
2718 emit_opcode(cbuf, 0x50+$src$$reg );
2719 // fild 64-bits at [SP]
2720 emit_opcode(cbuf,0xdf);
2721 emit_d8(cbuf, 0x6C);
2722 emit_d8(cbuf, 0x24);
2723 emit_d8(cbuf, 0x00);
2724 // pop stack
2725 emit_opcode(cbuf, 0x83); // add SP, #8
2726 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2727 emit_d8(cbuf, 0x8);
2728 %}
2729
2730 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2731 // IMUL EDX:EAX,$src1
2732 emit_opcode( cbuf, 0xF7 );
2733 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2734 // SAR EDX,$cnt-32
2735 int shift_count = ((int)$cnt$$constant) - 32;
2736 if (shift_count > 0) {
2737 emit_opcode(cbuf, 0xC1);
2738 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2739 emit_d8(cbuf, shift_count);
2740 }
2741 %}
2742
2743 // this version doesn't have add sp, 8
2744 enc_class convert_long_double2( eRegL src ) %{
2745 // push $src.hi
2746 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2747 // push $src.lo
2748 emit_opcode(cbuf, 0x50+$src$$reg );
2749 // fild 64-bits at [SP]
2750 emit_opcode(cbuf,0xdf);
2751 emit_d8(cbuf, 0x6C);
2752 emit_d8(cbuf, 0x24);
2753 emit_d8(cbuf, 0x00);
2754 %}
2755
2756 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2757 // Basic idea: long = (long)int * (long)int
2758 // IMUL EDX:EAX, src
2759 emit_opcode( cbuf, 0xF7 );
2760 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2761 %}
2762
2763 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2764 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2765 // MUL EDX:EAX, src
2766 emit_opcode( cbuf, 0xF7 );
2767 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2768 %}
2769
2770 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2771 // Basic idea: lo(result) = lo(x_lo * y_lo)
2772 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2773 // MOV $tmp,$src.lo
2774 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2775 // IMUL $tmp,EDX
2776 emit_opcode( cbuf, 0x0F );
2777 emit_opcode( cbuf, 0xAF );
2778 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2779 // MOV EDX,$src.hi
2780 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2781 // IMUL EDX,EAX
2782 emit_opcode( cbuf, 0x0F );
2783 emit_opcode( cbuf, 0xAF );
2784 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2785 // ADD $tmp,EDX
2786 emit_opcode( cbuf, 0x03 );
2787 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2788 // MUL EDX:EAX,$src.lo
2789 emit_opcode( cbuf, 0xF7 );
2790 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2791 // ADD EDX,ESI
2792 emit_opcode( cbuf, 0x03 );
2793 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2794 %}
2795
2796 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2797 // Basic idea: lo(result) = lo(src * y_lo)
2798 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2799 // IMUL $tmp,EDX,$src
2800 emit_opcode( cbuf, 0x6B );
2801 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2802 emit_d8( cbuf, (int)$src$$constant );
2803 // MOV EDX,$src
2804 emit_opcode(cbuf, 0xB8 + EDX_enc);
2805 emit_d32( cbuf, (int)$src$$constant );
2806 // MUL EDX:EAX,EDX
2807 emit_opcode( cbuf, 0xF7 );
2808 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2809 // ADD EDX,ESI
2810 emit_opcode( cbuf, 0x03 );
2811 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2812 %}
2813
2814 enc_class long_div( eRegL src1, eRegL src2 ) %{
2815 // PUSH src1.hi
2816 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2817 // PUSH src1.lo
2818 emit_opcode(cbuf, 0x50+$src1$$reg );
2819 // PUSH src2.hi
2820 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2821 // PUSH src2.lo
2822 emit_opcode(cbuf, 0x50+$src2$$reg );
2823 // CALL directly to the runtime
2824 cbuf.set_insts_mark();
2825 emit_opcode(cbuf,0xE8); // Call into runtime
2826 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2827 // Restore stack
2828 emit_opcode(cbuf, 0x83); // add SP, #framesize
2829 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2830 emit_d8(cbuf, 4*4);
2831 %}
2832
2833 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2834 // PUSH src1.hi
2835 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2836 // PUSH src1.lo
2837 emit_opcode(cbuf, 0x50+$src1$$reg );
2838 // PUSH src2.hi
2839 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2840 // PUSH src2.lo
2841 emit_opcode(cbuf, 0x50+$src2$$reg );
2842 // CALL directly to the runtime
2843 cbuf.set_insts_mark();
2844 emit_opcode(cbuf,0xE8); // Call into runtime
2845 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2846 // Restore stack
2847 emit_opcode(cbuf, 0x83); // add SP, #framesize
2848 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2849 emit_d8(cbuf, 4*4);
2850 %}
2851
2852 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2853 // MOV $tmp,$src.lo
2854 emit_opcode(cbuf, 0x8B);
2855 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2856 // OR $tmp,$src.hi
2857 emit_opcode(cbuf, 0x0B);
2858 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2859 %}
2860
2861 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2862 // CMP $src1.lo,$src2.lo
2863 emit_opcode( cbuf, 0x3B );
2864 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2865 // JNE,s skip
2866 emit_cc(cbuf, 0x70, 0x5);
2867 emit_d8(cbuf,2);
2868 // CMP $src1.hi,$src2.hi
2869 emit_opcode( cbuf, 0x3B );
2870 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2871 %}
2872
2873 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2874 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2875 emit_opcode( cbuf, 0x3B );
2876 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2877 // MOV $tmp,$src1.hi
2878 emit_opcode( cbuf, 0x8B );
2879 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2880 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2881 emit_opcode( cbuf, 0x1B );
2882 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2883 %}
2884
2885 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2886 // XOR $tmp,$tmp
2887 emit_opcode(cbuf,0x33); // XOR
2888 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2889 // CMP $tmp,$src.lo
2890 emit_opcode( cbuf, 0x3B );
2891 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2892 // SBB $tmp,$src.hi
2893 emit_opcode( cbuf, 0x1B );
2894 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2895 %}
2896
2897 // Sniff, sniff... smells like Gnu Superoptimizer
2898 enc_class neg_long( eRegL dst ) %{
2899 emit_opcode(cbuf,0xF7); // NEG hi
2900 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2901 emit_opcode(cbuf,0xF7); // NEG lo
2902 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2903 emit_opcode(cbuf,0x83); // SBB hi,0
2904 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2905 emit_d8 (cbuf,0 );
2906 %}
2907
2908
2909 // Because the transitions from emitted code to the runtime
2910 // monitorenter/exit helper stubs are so slow it's critical that
2911 // we inline both the stack-locking fast-path and the inflated fast path.
2912 //
2913 // See also: cmpFastLock and cmpFastUnlock.
2914 //
2915 // What follows is a specialized inline transliteration of the code
2916 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2917 // another option would be to emit TrySlowEnter and TrySlowExit methods
2918 // at startup-time. These methods would accept arguments as
2919 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2920 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2921 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2922 // In practice, however, the # of lock sites is bounded and is usually small.
2923 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2924 // if the processor uses simple bimodal branch predictors keyed by EIP
2925 // Since the helper routines would be called from multiple synchronization
2926 // sites.
2927 //
2928 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2929 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2930 // to those specialized methods. That'd give us a mostly platform-independent
2931 // implementation that the JITs could optimize and inline at their pleasure.
2932 // Done correctly, the only time we'd need to cross to native could would be
2933 // to park() or unpark() threads. We'd also need a few more unsafe operators
2934 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2935 // (b) explicit barriers or fence operations.
2936 //
2937 // TODO:
2938 //
2939 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2940 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2941 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2942 // the lock operators would typically be faster than reifying Self.
2943 //
2944 // * Ideally I'd define the primitives as:
2945 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2946 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2947 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2948 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2949 // Furthermore the register assignments are overconstrained, possibly resulting in
2950 // sub-optimal code near the synchronization site.
2951 //
2952 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2953 // Alternately, use a better sp-proximity test.
2954 //
2955 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2956 // Either one is sufficient to uniquely identify a thread.
2957 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2958 //
2959 // * Intrinsify notify() and notifyAll() for the common cases where the
2960 // object is locked by the calling thread but the waitlist is empty.
2961 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2962 //
2963 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2964 // But beware of excessive branch density on AMD Opterons.
2965 //
2966 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2967 // or failure of the fast-path. If the fast-path fails then we pass
2968 // control to the slow-path, typically in C. In Fast_Lock and
2969 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2970 // will emit a conditional branch immediately after the node.
2971 // So we have branches to branches and lots of ICC.ZF games.
2972 // Instead, it might be better to have C2 pass a "FailureLabel"
2973 // into Fast_Lock and Fast_Unlock. In the case of success, control
2974 // will drop through the node. ICC.ZF is undefined at exit.
2975 // In the case of failure, the node will branch directly to the
2976 // FailureLabel
2977
2978
2979 // obj: object to lock
2980 // box: on-stack box address (displaced header location) - KILLED
2981 // rax,: tmp -- KILLED
2982 // scr: tmp -- KILLED
2983 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2984
2985 Register objReg = as_Register($obj$$reg);
2986 Register boxReg = as_Register($box$$reg);
2987 Register tmpReg = as_Register($tmp$$reg);
2988 Register scrReg = as_Register($scr$$reg);
2989
2990 // Ensure the register assignents are disjoint
2991 guarantee (objReg != boxReg, "") ;
2992 guarantee (objReg != tmpReg, "") ;
2993 guarantee (objReg != scrReg, "") ;
2994 guarantee (boxReg != tmpReg, "") ;
2995 guarantee (boxReg != scrReg, "") ;
2996 guarantee (tmpReg == as_Register(EAX_enc), "") ;
2997
2998 MacroAssembler masm(&cbuf);
2999
3000 if (_counters != NULL) {
3001 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3002 }
3003 if (EmitSync & 1) {
3004 // set box->dhw = unused_mark (3)
3005 // Force all sync thru slow-path: slow_enter() and slow_exit()
3006 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3007 masm.cmpptr (rsp, (int32_t)0) ;
3008 } else
3009 if (EmitSync & 2) {
3010 Label DONE_LABEL ;
3011 if (UseBiasedLocking) {
3012 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3013 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3014 }
3015
3016 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3017 masm.orptr (tmpReg, 0x1);
3018 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3019 if (os::is_MP()) { masm.lock(); }
3020 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3021 masm.jcc(Assembler::equal, DONE_LABEL);
3022 // Recursive locking
3023 masm.subptr(tmpReg, rsp);
3024 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3025 masm.movptr(Address(boxReg, 0), tmpReg);
3026 masm.bind(DONE_LABEL) ;
3027 } else {
3028 // Possible cases that we'll encounter in fast_lock
3029 // ------------------------------------------------
3030 // * Inflated
3031 // -- unlocked
3032 // -- Locked
3033 // = by self
3034 // = by other
3035 // * biased
3036 // -- by Self
3037 // -- by other
3038 // * neutral
3039 // * stack-locked
3040 // -- by self
3041 // = sp-proximity test hits
3042 // = sp-proximity test generates false-negative
3043 // -- by other
3044 //
3045
3046 Label IsInflated, DONE_LABEL, PopDone ;
3047
3048 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3049 // order to reduce the number of conditional branches in the most common cases.
3050 // Beware -- there's a subtle invariant that fetch of the markword
3051 // at [FETCH], below, will never observe a biased encoding (*101b).
3052 // If this invariant is not held we risk exclusion (safety) failure.
3053 if (UseBiasedLocking && !UseOptoBiasInlining) {
3054 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3055 }
3056
3057 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3058 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3059 masm.jccb (Assembler::notZero, IsInflated) ;
3060
3061 // Attempt stack-locking ...
3062 masm.orptr (tmpReg, 0x1);
3063 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3064 if (os::is_MP()) { masm.lock(); }
3065 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3066 if (_counters != NULL) {
3067 masm.cond_inc32(Assembler::equal,
3068 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3069 }
3070 masm.jccb (Assembler::equal, DONE_LABEL);
3071
3072 // Recursive locking
3073 masm.subptr(tmpReg, rsp);
3074 masm.andptr(tmpReg, 0xFFFFF003 );
3075 masm.movptr(Address(boxReg, 0), tmpReg);
3076 if (_counters != NULL) {
3077 masm.cond_inc32(Assembler::equal,
3078 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3079 }
3080 masm.jmp (DONE_LABEL) ;
3081
3082 masm.bind (IsInflated) ;
3083
3084 // The object is inflated.
3085 //
3086 // TODO-FIXME: eliminate the ugly use of manifest constants:
3087 // Use markOopDesc::monitor_value instead of "2".
3088 // use markOop::unused_mark() instead of "3".
3089 // The tmpReg value is an objectMonitor reference ORed with
3090 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3091 // objectmonitor pointer by masking off the "2" bit or we can just
3092 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3093 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3094 //
3095 // I use the latter as it avoids AGI stalls.
3096 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3097 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3098 //
3099 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3100
3101 // boxReg refers to the on-stack BasicLock in the current frame.
3102 // We'd like to write:
3103 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3104 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3105 // additional latency as we have another ST in the store buffer that must drain.
3106
3107 if (EmitSync & 8192) {
3108 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3109 masm.get_thread (scrReg) ;
3110 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3111 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3112 if (os::is_MP()) { masm.lock(); }
3113 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3114 } else
3115 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3116 masm.movptr(scrReg, boxReg) ;
3117 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3118
3119 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3120 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3121 // prefetchw [eax + Offset(_owner)-2]
3122 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3123 }
3124
3125 if ((EmitSync & 64) == 0) {
3126 // Optimistic form: consider XORL tmpReg,tmpReg
3127 masm.movptr(tmpReg, NULL_WORD) ;
3128 } else {
3129 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3130 // Test-And-CAS instead of CAS
3131 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3132 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3133 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3134 }
3135
3136 // Appears unlocked - try to swing _owner from null to non-null.
3137 // Ideally, I'd manifest "Self" with get_thread and then attempt
3138 // to CAS the register containing Self into m->Owner.
3139 // But we don't have enough registers, so instead we can either try to CAS
3140 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3141 // we later store "Self" into m->Owner. Transiently storing a stack address
3142 // (rsp or the address of the box) into m->owner is harmless.
3143 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3144 if (os::is_MP()) { masm.lock(); }
3145 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3146 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3147 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3148 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3149 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3150 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3151
3152 // If the CAS fails we can either retry or pass control to the slow-path.
3153 // We use the latter tactic.
3154 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3155 // If the CAS was successful ...
3156 // Self has acquired the lock
3157 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3158 // Intentional fall-through into DONE_LABEL ...
3159 } else {
3160 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3161 masm.movptr(boxReg, tmpReg) ;
3162
3163 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3164 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3165 // prefetchw [eax + Offset(_owner)-2]
3166 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3167 }
3168
3169 if ((EmitSync & 64) == 0) {
3170 // Optimistic form
3171 masm.xorptr (tmpReg, tmpReg) ;
3172 } else {
3173 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3174 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3175 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3176 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3177 }
3178
3179 // Appears unlocked - try to swing _owner from null to non-null.
3180 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3181 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3182 masm.get_thread (scrReg) ;
3183 if (os::is_MP()) { masm.lock(); }
3184 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3185
3186 // If the CAS fails we can either retry or pass control to the slow-path.
3187 // We use the latter tactic.
3188 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3189 // If the CAS was successful ...
3190 // Self has acquired the lock
3191 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3192 // Intentional fall-through into DONE_LABEL ...
3193 }
3194
3195 // DONE_LABEL is a hot target - we'd really like to place it at the
3196 // start of cache line by padding with NOPs.
3197 // See the AMD and Intel software optimization manuals for the
3198 // most efficient "long" NOP encodings.
3199 // Unfortunately none of our alignment mechanisms suffice.
3200 masm.bind(DONE_LABEL);
3201
3202 // Avoid branch-to-branch on AMD processors
3203 // This appears to be superstition.
3204 if (EmitSync & 32) masm.nop() ;
3205
3206
3207 // At DONE_LABEL the icc ZFlag is set as follows ...
3208 // Fast_Unlock uses the same protocol.
3209 // ZFlag == 1 -> Success
3210 // ZFlag == 0 -> Failure - force control through the slow-path
3211 }
3212 %}
3213
3214 // obj: object to unlock
3215 // box: box address (displaced header location), killed. Must be EAX.
3216 // rbx,: killed tmp; cannot be obj nor box.
3217 //
3218 // Some commentary on balanced locking:
3219 //
3220 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3221 // Methods that don't have provably balanced locking are forced to run in the
3222 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3223 // The interpreter provides two properties:
3224 // I1: At return-time the interpreter automatically and quietly unlocks any
3225 // objects acquired the current activation (frame). Recall that the
3226 // interpreter maintains an on-stack list of locks currently held by
3227 // a frame.
3228 // I2: If a method attempts to unlock an object that is not held by the
3229 // the frame the interpreter throws IMSX.
3230 //
3231 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3232 // B() doesn't have provably balanced locking so it runs in the interpreter.
3233 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3234 // is still locked by A().
3235 //
3236 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3237 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3238 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3239 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3240
3241 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3242
3243 Register objReg = as_Register($obj$$reg);
3244 Register boxReg = as_Register($box$$reg);
3245 Register tmpReg = as_Register($tmp$$reg);
3246
3247 guarantee (objReg != boxReg, "") ;
3248 guarantee (objReg != tmpReg, "") ;
3249 guarantee (boxReg != tmpReg, "") ;
3250 guarantee (boxReg == as_Register(EAX_enc), "") ;
3251 MacroAssembler masm(&cbuf);
3252
3253 if (EmitSync & 4) {
3254 // Disable - inhibit all inlining. Force control through the slow-path
3255 masm.cmpptr (rsp, 0) ;
3256 } else
3257 if (EmitSync & 8) {
3258 Label DONE_LABEL ;
3259 if (UseBiasedLocking) {
3260 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3261 }
3262 // classic stack-locking code ...
3263 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3264 masm.testptr(tmpReg, tmpReg) ;
3265 masm.jcc (Assembler::zero, DONE_LABEL) ;
3266 if (os::is_MP()) { masm.lock(); }
3267 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3268 masm.bind(DONE_LABEL);
3269 } else {
3270 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3271
3272 // Critically, the biased locking test must have precedence over
3273 // and appear before the (box->dhw == 0) recursive stack-lock test.
3274 if (UseBiasedLocking && !UseOptoBiasInlining) {
3275 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3276 }
3277
3278 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3279 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3280 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3281
3282 masm.testptr(tmpReg, 0x02) ; // Inflated?
3283 masm.jccb (Assembler::zero, Stacked) ;
3284
3285 masm.bind (Inflated) ;
3286 // It's inflated.
3287 // Despite our balanced locking property we still check that m->_owner == Self
3288 // as java routines or native JNI code called by this thread might
3289 // have released the lock.
3290 // Refer to the comments in synchronizer.cpp for how we might encode extra
3291 // state in _succ so we can avoid fetching EntryList|cxq.
3292 //
3293 // I'd like to add more cases in fast_lock() and fast_unlock() --
3294 // such as recursive enter and exit -- but we have to be wary of
3295 // I$ bloat, T$ effects and BP$ effects.
3296 //
3297 // If there's no contention try a 1-0 exit. That is, exit without
3298 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3299 // we detect and recover from the race that the 1-0 exit admits.
3300 //
3301 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3302 // before it STs null into _owner, releasing the lock. Updates
3303 // to data protected by the critical section must be visible before
3304 // we drop the lock (and thus before any other thread could acquire
3305 // the lock and observe the fields protected by the lock).
3306 // IA32's memory-model is SPO, so STs are ordered with respect to
3307 // each other and there's no need for an explicit barrier (fence).
3308 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3309
3310 masm.get_thread (boxReg) ;
3311 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3312 // prefetchw [ebx + Offset(_owner)-2]
3313 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3314 }
3315
3316 // Note that we could employ various encoding schemes to reduce
3317 // the number of loads below (currently 4) to just 2 or 3.
3318 // Refer to the comments in synchronizer.cpp.
3319 // In practice the chain of fetches doesn't seem to impact performance, however.
3320 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3321 // Attempt to reduce branch density - AMD's branch predictor.
3322 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3323 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3324 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3325 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3326 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3327 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3328 masm.jmpb (DONE_LABEL) ;
3329 } else {
3330 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3331 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3332 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3333 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3334 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3335 masm.jccb (Assembler::notZero, CheckSucc) ;
3336 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3337 masm.jmpb (DONE_LABEL) ;
3338 }
3339
3340 // The Following code fragment (EmitSync & 65536) improves the performance of
3341 // contended applications and contended synchronization microbenchmarks.
3342 // Unfortunately the emission of the code - even though not executed - causes regressions
3343 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3344 // with an equal number of never-executed NOPs results in the same regression.
3345 // We leave it off by default.
3346
3347 if ((EmitSync & 65536) != 0) {
3348 Label LSuccess, LGoSlowPath ;
3349
3350 masm.bind (CheckSucc) ;
3351
3352 // Optional pre-test ... it's safe to elide this
3353 if ((EmitSync & 16) == 0) {
3354 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3355 masm.jccb (Assembler::zero, LGoSlowPath) ;
3356 }
3357
3358 // We have a classic Dekker-style idiom:
3359 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3360 // There are a number of ways to implement the barrier:
3361 // (1) lock:andl &m->_owner, 0
3362 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3363 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3364 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3365 // (2) If supported, an explicit MFENCE is appealing.
3366 // In older IA32 processors MFENCE is slower than lock:add or xchg
3367 // particularly if the write-buffer is full as might be the case if
3368 // if stores closely precede the fence or fence-equivalent instruction.
3369 // In more modern implementations MFENCE appears faster, however.
3370 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3371 // The $lines underlying the top-of-stack should be in M-state.
3372 // The locked add instruction is serializing, of course.
3373 // (4) Use xchg, which is serializing
3374 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3375 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3376 // The integer condition codes will tell us if succ was 0.
3377 // Since _succ and _owner should reside in the same $line and
3378 // we just stored into _owner, it's likely that the $line
3379 // remains in M-state for the lock:orl.
3380 //
3381 // We currently use (3), although it's likely that switching to (2)
3382 // is correct for the future.
3383
3384 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3385 if (os::is_MP()) {
3386 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3387 masm.mfence();
3388 } else {
3389 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3390 }
3391 }
3392 // Ratify _succ remains non-null
3393 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3394 masm.jccb (Assembler::notZero, LSuccess) ;
3395
3396 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3397 if (os::is_MP()) { masm.lock(); }
3398 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3399 masm.jccb (Assembler::notEqual, LSuccess) ;
3400 // Since we're low on registers we installed rsp as a placeholding in _owner.
3401 // Now install Self over rsp. This is safe as we're transitioning from
3402 // non-null to non=null
3403 masm.get_thread (boxReg) ;
3404 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3405 // Intentional fall-through into LGoSlowPath ...
3406
3407 masm.bind (LGoSlowPath) ;
3408 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3409 masm.jmpb (DONE_LABEL) ;
3410
3411 masm.bind (LSuccess) ;
3412 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3413 masm.jmpb (DONE_LABEL) ;
3414 }
3415
3416 masm.bind (Stacked) ;
3417 // It's not inflated and it's not recursively stack-locked and it's not biased.
3418 // It must be stack-locked.
3419 // Try to reset the header to displaced header.
3420 // The "box" value on the stack is stable, so we can reload
3421 // and be assured we observe the same value as above.
3422 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3423 if (os::is_MP()) { masm.lock(); }
3424 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3425 // Intention fall-thru into DONE_LABEL
3426
3427
3428 // DONE_LABEL is a hot target - we'd really like to place it at the
3429 // start of cache line by padding with NOPs.
3430 // See the AMD and Intel software optimization manuals for the
3431 // most efficient "long" NOP encodings.
3432 // Unfortunately none of our alignment mechanisms suffice.
3433 if ((EmitSync & 65536) == 0) {
3434 masm.bind (CheckSucc) ;
3435 }
3436 masm.bind(DONE_LABEL);
3437
3438 // Avoid branch to branch on AMD processors
3439 if (EmitSync & 32768) { masm.nop() ; }
3440 }
3441 %}
3442
3443
3444 enc_class enc_pop_rdx() %{
3445 emit_opcode(cbuf,0x5A);
3446 %}
3447
3448 enc_class enc_rethrow() %{
3449 cbuf.set_insts_mark();
3450 emit_opcode(cbuf, 0xE9); // jmp entry
3451 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3452 runtime_call_Relocation::spec(), RELOC_IMM32 );
3453 %}
3454
3455
3456 // Convert a double to an int. Java semantics require we do complex
3457 // manglelations in the corner cases. So we set the rounding mode to
3458 // 'zero', store the darned double down as an int, and reset the
3459 // rounding mode to 'nearest'. The hardware throws an exception which
3460 // patches up the correct value directly to the stack.
3461 enc_class DPR2I_encoding( regDPR src ) %{
3462 // Flip to round-to-zero mode. We attempted to allow invalid-op
3463 // exceptions here, so that a NAN or other corner-case value will
3464 // thrown an exception (but normal values get converted at full speed).
3465 // However, I2C adapters and other float-stack manglers leave pending
3466 // invalid-op exceptions hanging. We would have to clear them before
3467 // enabling them and that is more expensive than just testing for the
3468 // invalid value Intel stores down in the corner cases.
3469 emit_opcode(cbuf,0xD9); // FLDCW trunc
3470 emit_opcode(cbuf,0x2D);
3471 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3472 // Allocate a word
3473 emit_opcode(cbuf,0x83); // SUB ESP,4
3474 emit_opcode(cbuf,0xEC);
3475 emit_d8(cbuf,0x04);
3476 // Encoding assumes a double has been pushed into FPR0.
3477 // Store down the double as an int, popping the FPU stack
3478 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3479 emit_opcode(cbuf,0x1C);
3480 emit_d8(cbuf,0x24);
3481 // Restore the rounding mode; mask the exception
3482 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3483 emit_opcode(cbuf,0x2D);
3484 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3485 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3486 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3487
3488 // Load the converted int; adjust CPU stack
3489 emit_opcode(cbuf,0x58); // POP EAX
3490 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3491 emit_d32 (cbuf,0x80000000); // 0x80000000
3492 emit_opcode(cbuf,0x75); // JNE around_slow_call
3493 emit_d8 (cbuf,0x07); // Size of slow_call
3494 // Push src onto stack slow-path
3495 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3496 emit_d8 (cbuf,0xC0-1+$src$$reg );
3497 // CALL directly to the runtime
3498 cbuf.set_insts_mark();
3499 emit_opcode(cbuf,0xE8); // Call into runtime
3500 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3501 // Carry on here...
3502 %}
3503
3504 enc_class DPR2L_encoding( regDPR src ) %{
3505 emit_opcode(cbuf,0xD9); // FLDCW trunc
3506 emit_opcode(cbuf,0x2D);
3507 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3508 // Allocate a word
3509 emit_opcode(cbuf,0x83); // SUB ESP,8
3510 emit_opcode(cbuf,0xEC);
3511 emit_d8(cbuf,0x08);
3512 // Encoding assumes a double has been pushed into FPR0.
3513 // Store down the double as a long, popping the FPU stack
3514 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3515 emit_opcode(cbuf,0x3C);
3516 emit_d8(cbuf,0x24);
3517 // Restore the rounding mode; mask the exception
3518 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3519 emit_opcode(cbuf,0x2D);
3520 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3521 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3522 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3523
3524 // Load the converted int; adjust CPU stack
3525 emit_opcode(cbuf,0x58); // POP EAX
3526 emit_opcode(cbuf,0x5A); // POP EDX
3527 emit_opcode(cbuf,0x81); // CMP EDX,imm
3528 emit_d8 (cbuf,0xFA); // rdx
3529 emit_d32 (cbuf,0x80000000); // 0x80000000
3530 emit_opcode(cbuf,0x75); // JNE around_slow_call
3531 emit_d8 (cbuf,0x07+4); // Size of slow_call
3532 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3533 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3534 emit_opcode(cbuf,0x75); // JNE around_slow_call
3535 emit_d8 (cbuf,0x07); // Size of slow_call
3536 // Push src onto stack slow-path
3537 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3538 emit_d8 (cbuf,0xC0-1+$src$$reg );
3539 // CALL directly to the runtime
3540 cbuf.set_insts_mark();
3541 emit_opcode(cbuf,0xE8); // Call into runtime
3542 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3543 // Carry on here...
3544 %}
3545
3546 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3547 // Operand was loaded from memory into fp ST (stack top)
3548 // FMUL ST,$src /* D8 C8+i */
3549 emit_opcode(cbuf, 0xD8);
3550 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3551 %}
3552
3553 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3554 // FADDP ST,src2 /* D8 C0+i */
3555 emit_opcode(cbuf, 0xD8);
3556 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3557 //could use FADDP src2,fpST /* DE C0+i */
3558 %}
3559
3560 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3561 // FADDP src2,ST /* DE C0+i */
3562 emit_opcode(cbuf, 0xDE);
3563 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3564 %}
3565
3566 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3567 // Operand has been loaded into fp ST (stack top)
3568 // FSUB ST,$src1
3569 emit_opcode(cbuf, 0xD8);
3570 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3571
3572 // FDIV
3573 emit_opcode(cbuf, 0xD8);
3574 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3575 %}
3576
3577 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3578 // Operand was loaded from memory into fp ST (stack top)
3579 // FADD ST,$src /* D8 C0+i */
3580 emit_opcode(cbuf, 0xD8);
3581 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3582
3583 // FMUL ST,src2 /* D8 C*+i */
3584 emit_opcode(cbuf, 0xD8);
3585 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3586 %}
3587
3588
3589 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3590 // Operand was loaded from memory into fp ST (stack top)
3591 // FADD ST,$src /* D8 C0+i */
3592 emit_opcode(cbuf, 0xD8);
3593 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3594
3595 // FMULP src2,ST /* DE C8+i */
3596 emit_opcode(cbuf, 0xDE);
3597 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3598 %}
3599
3600 // Atomically load the volatile long
3601 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3602 emit_opcode(cbuf,0xDF);
3603 int rm_byte_opcode = 0x05;
3604 int base = $mem$$base;
3605 int index = $mem$$index;
3606 int scale = $mem$$scale;
3607 int displace = $mem$$disp;
3608 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3609 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3610 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3611 %}
3612
3613 // Volatile Store Long. Must be atomic, so move it into
3614 // the FP TOS and then do a 64-bit FIST. Has to probe the
3615 // target address before the store (for null-ptr checks)
3616 // so the memory operand is used twice in the encoding.
3617 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3618 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3619 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3620 emit_opcode(cbuf,0xDF);
3621 int rm_byte_opcode = 0x07;
3622 int base = $mem$$base;
3623 int index = $mem$$index;
3624 int scale = $mem$$scale;
3625 int displace = $mem$$disp;
3626 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3627 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3628 %}
3629
3630 // Safepoint Poll. This polls the safepoint page, and causes an
3631 // exception if it is not readable. Unfortunately, it kills the condition code
3632 // in the process
3633 // We current use TESTL [spp],EDI
3634 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3635
3636 enc_class Safepoint_Poll() %{
3637 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3638 emit_opcode(cbuf,0x85);
3639 emit_rm (cbuf, 0x0, 0x7, 0x5);
3640 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3641 %}
3642 %}
3643
3644
3645 //----------FRAME--------------------------------------------------------------
3646 // Definition of frame structure and management information.
3647 //
3648 // S T A C K L A Y O U T Allocators stack-slot number
3649 // | (to get allocators register number
3650 // G Owned by | | v add OptoReg::stack0())
3651 // r CALLER | |
3652 // o | +--------+ pad to even-align allocators stack-slot
3653 // w V | pad0 | numbers; owned by CALLER
3654 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3655 // h ^ | in | 5
3656 // | | args | 4 Holes in incoming args owned by SELF
3657 // | | | | 3
3658 // | | +--------+
3659 // V | | old out| Empty on Intel, window on Sparc
3660 // | old |preserve| Must be even aligned.
3661 // | SP-+--------+----> Matcher::_old_SP, even aligned
3662 // | | in | 3 area for Intel ret address
3663 // Owned by |preserve| Empty on Sparc.
3664 // SELF +--------+
3665 // | | pad2 | 2 pad to align old SP
3666 // | +--------+ 1
3667 // | | locks | 0
3668 // | +--------+----> OptoReg::stack0(), even aligned
3669 // | | pad1 | 11 pad to align new SP
3670 // | +--------+
3671 // | | | 10
3672 // | | spills | 9 spills
3673 // V | | 8 (pad0 slot for callee)
3674 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3675 // ^ | out | 7
3676 // | | args | 6 Holes in outgoing args owned by CALLEE
3677 // Owned by +--------+
3678 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3679 // | new |preserve| Must be even-aligned.
3680 // | SP-+--------+----> Matcher::_new_SP, even aligned
3681 // | | |
3682 //
3683 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3684 // known from SELF's arguments and the Java calling convention.
3685 // Region 6-7 is determined per call site.
3686 // Note 2: If the calling convention leaves holes in the incoming argument
3687 // area, those holes are owned by SELF. Holes in the outgoing area
3688 // are owned by the CALLEE. Holes should not be nessecary in the
3689 // incoming area, as the Java calling convention is completely under
3690 // the control of the AD file. Doubles can be sorted and packed to
3691 // avoid holes. Holes in the outgoing arguments may be nessecary for
3692 // varargs C calling conventions.
3693 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3694 // even aligned with pad0 as needed.
3695 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3696 // region 6-11 is even aligned; it may be padded out more so that
3697 // the region from SP to FP meets the minimum stack alignment.
3698
3699 frame %{
3700 // What direction does stack grow in (assumed to be same for C & Java)
3701 stack_direction(TOWARDS_LOW);
3702
3703 // These three registers define part of the calling convention
3704 // between compiled code and the interpreter.
3705 inline_cache_reg(EAX); // Inline Cache Register
3706 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3707
3708 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3709 cisc_spilling_operand_name(indOffset32);
3710
3711 // Number of stack slots consumed by locking an object
3712 sync_stack_slots(1);
3713
3714 // Compiled code's Frame Pointer
3715 frame_pointer(ESP);
3716 // Interpreter stores its frame pointer in a register which is
3717 // stored to the stack by I2CAdaptors.
3718 // I2CAdaptors convert from interpreted java to compiled java.
3719 interpreter_frame_pointer(EBP);
3720
3721 // Stack alignment requirement
3722 // Alignment size in bytes (128-bit -> 16 bytes)
3723 stack_alignment(StackAlignmentInBytes);
3724
3725 // Number of stack slots between incoming argument block and the start of
3726 // a new frame. The PROLOG must add this many slots to the stack. The
3727 // EPILOG must remove this many slots. Intel needs one slot for
3728 // return address and one for rbp, (must save rbp)
3729 in_preserve_stack_slots(2+VerifyStackAtCalls);
3730
3731 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3732 // for calls to C. Supports the var-args backing area for register parms.
3733 varargs_C_out_slots_killed(0);
3734
3735 // The after-PROLOG location of the return address. Location of
3736 // return address specifies a type (REG or STACK) and a number
3737 // representing the register number (i.e. - use a register name) or
3738 // stack slot.
3739 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3740 // Otherwise, it is above the locks and verification slot and alignment word
3741 return_addr(STACK - 1 +
3742 round_to((Compile::current()->in_preserve_stack_slots() +
3743 Compile::current()->fixed_slots()),
3744 stack_alignment_in_slots()));
3745
3746 // Body of function which returns an integer array locating
3747 // arguments either in registers or in stack slots. Passed an array
3748 // of ideal registers called "sig" and a "length" count. Stack-slot
3749 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3750 // arguments for a CALLEE. Incoming stack arguments are
3751 // automatically biased by the preserve_stack_slots field above.
3752 calling_convention %{
3753 // No difference between ingoing/outgoing just pass false
3754 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3755 %}
3756
3757
3758 // Body of function which returns an integer array locating
3759 // arguments either in registers or in stack slots. Passed an array
3760 // of ideal registers called "sig" and a "length" count. Stack-slot
3761 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3762 // arguments for a CALLEE. Incoming stack arguments are
3763 // automatically biased by the preserve_stack_slots field above.
3764 c_calling_convention %{
3765 // This is obviously always outgoing
3766 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3767 %}
3768
3769 // Location of C & interpreter return values
3770 c_return_value %{
3771 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3772 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3773 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3774
3775 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3776 // that C functions return float and double results in XMM0.
3777 if( ideal_reg == Op_RegD && UseSSE>=2 )
3778 return OptoRegPair(XMM0b_num,XMM0_num);
3779 if( ideal_reg == Op_RegF && UseSSE>=2 )
3780 return OptoRegPair(OptoReg::Bad,XMM0_num);
3781
3782 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3783 %}
3784
3785 // Location of return values
3786 return_value %{
3787 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3788 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3789 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3790 if( ideal_reg == Op_RegD && UseSSE>=2 )
3791 return OptoRegPair(XMM0b_num,XMM0_num);
3792 if( ideal_reg == Op_RegF && UseSSE>=1 )
3793 return OptoRegPair(OptoReg::Bad,XMM0_num);
3794 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3795 %}
3796
3797 %}
3798
3799 //----------ATTRIBUTES---------------------------------------------------------
3800 //----------Operand Attributes-------------------------------------------------
3801 op_attrib op_cost(0); // Required cost attribute
3802
3803 //----------Instruction Attributes---------------------------------------------
3804 ins_attrib ins_cost(100); // Required cost attribute
3805 ins_attrib ins_size(8); // Required size attribute (in bits)
3806 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3807 // non-matching short branch variant of some
3808 // long branch?
3809 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3810 // specifies the alignment that some part of the instruction (not
3811 // necessarily the start) requires. If > 1, a compute_padding()
3812 // function must be provided for the instruction
3813
3814 //----------OPERANDS-----------------------------------------------------------
3815 // Operand definitions must precede instruction definitions for correct parsing
3816 // in the ADLC because operands constitute user defined types which are used in
3817 // instruction definitions.
3818
3819 //----------Simple Operands----------------------------------------------------
3820 // Immediate Operands
3821 // Integer Immediate
3822 operand immI() %{
3823 match(ConI);
3824
3825 op_cost(10);
3826 format %{ %}
3827 interface(CONST_INTER);
3828 %}
3829
3830 // Constant for test vs zero
3831 operand immI0() %{
3832 predicate(n->get_int() == 0);
3833 match(ConI);
3834
3835 op_cost(0);
3836 format %{ %}
3837 interface(CONST_INTER);
3838 %}
3839
3840 // Constant for increment
3841 operand immI1() %{
3842 predicate(n->get_int() == 1);
3843 match(ConI);
3844
3845 op_cost(0);
3846 format %{ %}
3847 interface(CONST_INTER);
3848 %}
3849
3850 // Constant for decrement
3851 operand immI_M1() %{
3852 predicate(n->get_int() == -1);
3853 match(ConI);
3854
3855 op_cost(0);
3856 format %{ %}
3857 interface(CONST_INTER);
3858 %}
3859
3860 // Valid scale values for addressing modes
3861 operand immI2() %{
3862 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3863 match(ConI);
3864
3865 format %{ %}
3866 interface(CONST_INTER);
3867 %}
3868
3869 operand immI8() %{
3870 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3871 match(ConI);
3872
3873 op_cost(5);
3874 format %{ %}
3875 interface(CONST_INTER);
3876 %}
3877
3878 operand immI16() %{
3879 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3880 match(ConI);
3881
3882 op_cost(10);
3883 format %{ %}
3884 interface(CONST_INTER);
3885 %}
3886
3887 // Int Immediate non-negative
3888 operand immU31()
3889 %{
3890 predicate(n->get_int() >= 0);
3891 match(ConI);
3892
3893 op_cost(0);
3894 format %{ %}
3895 interface(CONST_INTER);
3896 %}
3897
3898 // Constant for long shifts
3899 operand immI_32() %{
3900 predicate( n->get_int() == 32 );
3901 match(ConI);
3902
3903 op_cost(0);
3904 format %{ %}
3905 interface(CONST_INTER);
3906 %}
3907
3908 operand immI_1_31() %{
3909 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3910 match(ConI);
3911
3912 op_cost(0);
3913 format %{ %}
3914 interface(CONST_INTER);
3915 %}
3916
3917 operand immI_32_63() %{
3918 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3919 match(ConI);
3920 op_cost(0);
3921
3922 format %{ %}
3923 interface(CONST_INTER);
3924 %}
3925
3926 operand immI_1() %{
3927 predicate( n->get_int() == 1 );
3928 match(ConI);
3929
3930 op_cost(0);
3931 format %{ %}
3932 interface(CONST_INTER);
3933 %}
3934
3935 operand immI_2() %{
3936 predicate( n->get_int() == 2 );
3937 match(ConI);
3938
3939 op_cost(0);
3940 format %{ %}
3941 interface(CONST_INTER);
3942 %}
3943
3944 operand immI_3() %{
3945 predicate( n->get_int() == 3 );
3946 match(ConI);
3947
3948 op_cost(0);
3949 format %{ %}
3950 interface(CONST_INTER);
3951 %}
3952
3953 // Pointer Immediate
3954 operand immP() %{
3955 match(ConP);
3956
3957 op_cost(10);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3961
3962 // NULL Pointer Immediate
3963 operand immP0() %{
3964 predicate( n->get_ptr() == 0 );
3965 match(ConP);
3966 op_cost(0);
3967
3968 format %{ %}
3969 interface(CONST_INTER);
3970 %}
3971
3972 // Long Immediate
3973 operand immL() %{
3974 match(ConL);
3975
3976 op_cost(20);
3977 format %{ %}
3978 interface(CONST_INTER);
3979 %}
3980
3981 // Long Immediate zero
3982 operand immL0() %{
3983 predicate( n->get_long() == 0L );
3984 match(ConL);
3985 op_cost(0);
3986
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3990
3991 // Long Immediate zero
3992 operand immL_M1() %{
3993 predicate( n->get_long() == -1L );
3994 match(ConL);
3995 op_cost(0);
3996
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4000
4001 // Long immediate from 0 to 127.
4002 // Used for a shorter form of long mul by 10.
4003 operand immL_127() %{
4004 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4005 match(ConL);
4006 op_cost(0);
4007
4008 format %{ %}
4009 interface(CONST_INTER);
4010 %}
4011
4012 // Long Immediate: low 32-bit mask
4013 operand immL_32bits() %{
4014 predicate(n->get_long() == 0xFFFFFFFFL);
4015 match(ConL);
4016 op_cost(0);
4017
4018 format %{ %}
4019 interface(CONST_INTER);
4020 %}
4021
4022 // Long Immediate: low 32-bit mask
4023 operand immL32() %{
4024 predicate(n->get_long() == (int)(n->get_long()));
4025 match(ConL);
4026 op_cost(20);
4027
4028 format %{ %}
4029 interface(CONST_INTER);
4030 %}
4031
4032 //Double Immediate zero
4033 operand immDPR0() %{
4034 // Do additional (and counter-intuitive) test against NaN to work around VC++
4035 // bug that generates code such that NaNs compare equal to 0.0
4036 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4037 match(ConD);
4038
4039 op_cost(5);
4040 format %{ %}
4041 interface(CONST_INTER);
4042 %}
4043
4044 // Double Immediate one
4045 operand immDPR1() %{
4046 predicate( UseSSE<=1 && n->getd() == 1.0 );
4047 match(ConD);
4048
4049 op_cost(5);
4050 format %{ %}
4051 interface(CONST_INTER);
4052 %}
4053
4054 // Double Immediate
4055 operand immDPR() %{
4056 predicate(UseSSE<=1);
4057 match(ConD);
4058
4059 op_cost(5);
4060 format %{ %}
4061 interface(CONST_INTER);
4062 %}
4063
4064 operand immD() %{
4065 predicate(UseSSE>=2);
4066 match(ConD);
4067
4068 op_cost(5);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4072
4073 // Double Immediate zero
4074 operand immD0() %{
4075 // Do additional (and counter-intuitive) test against NaN to work around VC++
4076 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4077 // compare equal to -0.0.
4078 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4079 match(ConD);
4080
4081 format %{ %}
4082 interface(CONST_INTER);
4083 %}
4084
4085 // Float Immediate zero
4086 operand immFPR0() %{
4087 predicate(UseSSE == 0 && n->getf() == 0.0F);
4088 match(ConF);
4089
4090 op_cost(5);
4091 format %{ %}
4092 interface(CONST_INTER);
4093 %}
4094
4095 // Float Immediate one
4096 operand immFPR1() %{
4097 predicate(UseSSE == 0 && n->getf() == 1.0F);
4098 match(ConF);
4099
4100 op_cost(5);
4101 format %{ %}
4102 interface(CONST_INTER);
4103 %}
4104
4105 // Float Immediate
4106 operand immFPR() %{
4107 predicate( UseSSE == 0 );
4108 match(ConF);
4109
4110 op_cost(5);
4111 format %{ %}
4112 interface(CONST_INTER);
4113 %}
4114
4115 // Float Immediate
4116 operand immF() %{
4117 predicate(UseSSE >= 1);
4118 match(ConF);
4119
4120 op_cost(5);
4121 format %{ %}
4122 interface(CONST_INTER);
4123 %}
4124
4125 // Float Immediate zero. Zero and not -0.0
4126 operand immF0() %{
4127 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4128 match(ConF);
4129
4130 op_cost(5);
4131 format %{ %}
4132 interface(CONST_INTER);
4133 %}
4134
4135 // Immediates for special shifts (sign extend)
4136
4137 // Constants for increment
4138 operand immI_16() %{
4139 predicate( n->get_int() == 16 );
4140 match(ConI);
4141
4142 format %{ %}
4143 interface(CONST_INTER);
4144 %}
4145
4146 operand immI_24() %{
4147 predicate( n->get_int() == 24 );
4148 match(ConI);
4149
4150 format %{ %}
4151 interface(CONST_INTER);
4152 %}
4153
4154 // Constant for byte-wide masking
4155 operand immI_255() %{
4156 predicate( n->get_int() == 255 );
4157 match(ConI);
4158
4159 format %{ %}
4160 interface(CONST_INTER);
4161 %}
4162
4163 // Constant for short-wide masking
4164 operand immI_65535() %{
4165 predicate(n->get_int() == 65535);
4166 match(ConI);
4167
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4171
4172 // Register Operands
4173 // Integer Register
4174 operand rRegI() %{
4175 constraint(ALLOC_IN_RC(int_reg));
4176 match(RegI);
4177 match(xRegI);
4178 match(eAXRegI);
4179 match(eBXRegI);
4180 match(eCXRegI);
4181 match(eDXRegI);
4182 match(eDIRegI);
4183 match(eSIRegI);
4184
4185 format %{ %}
4186 interface(REG_INTER);
4187 %}
4188
4189 // Subset of Integer Register
4190 operand xRegI(rRegI reg) %{
4191 constraint(ALLOC_IN_RC(int_x_reg));
4192 match(reg);
4193 match(eAXRegI);
4194 match(eBXRegI);
4195 match(eCXRegI);
4196 match(eDXRegI);
4197
4198 format %{ %}
4199 interface(REG_INTER);
4200 %}
4201
4202 // Special Registers
4203 operand eAXRegI(xRegI reg) %{
4204 constraint(ALLOC_IN_RC(eax_reg));
4205 match(reg);
4206 match(rRegI);
4207
4208 format %{ "EAX" %}
4209 interface(REG_INTER);
4210 %}
4211
4212 // Special Registers
4213 operand eBXRegI(xRegI reg) %{
4214 constraint(ALLOC_IN_RC(ebx_reg));
4215 match(reg);
4216 match(rRegI);
4217
4218 format %{ "EBX" %}
4219 interface(REG_INTER);
4220 %}
4221
4222 operand eCXRegI(xRegI reg) %{
4223 constraint(ALLOC_IN_RC(ecx_reg));
4224 match(reg);
4225 match(rRegI);
4226
4227 format %{ "ECX" %}
4228 interface(REG_INTER);
4229 %}
4230
4231 operand eDXRegI(xRegI reg) %{
4232 constraint(ALLOC_IN_RC(edx_reg));
4233 match(reg);
4234 match(rRegI);
4235
4236 format %{ "EDX" %}
4237 interface(REG_INTER);
4238 %}
4239
4240 operand eDIRegI(xRegI reg) %{
4241 constraint(ALLOC_IN_RC(edi_reg));
4242 match(reg);
4243 match(rRegI);
4244
4245 format %{ "EDI" %}
4246 interface(REG_INTER);
4247 %}
4248
4249 operand naxRegI() %{
4250 constraint(ALLOC_IN_RC(nax_reg));
4251 match(RegI);
4252 match(eCXRegI);
4253 match(eDXRegI);
4254 match(eSIRegI);
4255 match(eDIRegI);
4256
4257 format %{ %}
4258 interface(REG_INTER);
4259 %}
4260
4261 operand nadxRegI() %{
4262 constraint(ALLOC_IN_RC(nadx_reg));
4263 match(RegI);
4264 match(eBXRegI);
4265 match(eCXRegI);
4266 match(eSIRegI);
4267 match(eDIRegI);
4268
4269 format %{ %}
4270 interface(REG_INTER);
4271 %}
4272
4273 operand ncxRegI() %{
4274 constraint(ALLOC_IN_RC(ncx_reg));
4275 match(RegI);
4276 match(eAXRegI);
4277 match(eDXRegI);
4278 match(eSIRegI);
4279 match(eDIRegI);
4280
4281 format %{ %}
4282 interface(REG_INTER);
4283 %}
4284
4285 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4286 // //
4287 operand eSIRegI(xRegI reg) %{
4288 constraint(ALLOC_IN_RC(esi_reg));
4289 match(reg);
4290 match(rRegI);
4291
4292 format %{ "ESI" %}
4293 interface(REG_INTER);
4294 %}
4295
4296 // Pointer Register
4297 operand anyRegP() %{
4298 constraint(ALLOC_IN_RC(any_reg));
4299 match(RegP);
4300 match(eAXRegP);
4301 match(eBXRegP);
4302 match(eCXRegP);
4303 match(eDIRegP);
4304 match(eRegP);
4305
4306 format %{ %}
4307 interface(REG_INTER);
4308 %}
4309
4310 operand eRegP() %{
4311 constraint(ALLOC_IN_RC(int_reg));
4312 match(RegP);
4313 match(eAXRegP);
4314 match(eBXRegP);
4315 match(eCXRegP);
4316 match(eDIRegP);
4317
4318 format %{ %}
4319 interface(REG_INTER);
4320 %}
4321
4322 // On windows95, EBP is not safe to use for implicit null tests.
4323 operand eRegP_no_EBP() %{
4324 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4325 match(RegP);
4326 match(eAXRegP);
4327 match(eBXRegP);
4328 match(eCXRegP);
4329 match(eDIRegP);
4330
4331 op_cost(100);
4332 format %{ %}
4333 interface(REG_INTER);
4334 %}
4335
4336 operand naxRegP() %{
4337 constraint(ALLOC_IN_RC(nax_reg));
4338 match(RegP);
4339 match(eBXRegP);
4340 match(eDXRegP);
4341 match(eCXRegP);
4342 match(eSIRegP);
4343 match(eDIRegP);
4344
4345 format %{ %}
4346 interface(REG_INTER);
4347 %}
4348
4349 operand nabxRegP() %{
4350 constraint(ALLOC_IN_RC(nabx_reg));
4351 match(RegP);
4352 match(eCXRegP);
4353 match(eDXRegP);
4354 match(eSIRegP);
4355 match(eDIRegP);
4356
4357 format %{ %}
4358 interface(REG_INTER);
4359 %}
4360
4361 operand pRegP() %{
4362 constraint(ALLOC_IN_RC(p_reg));
4363 match(RegP);
4364 match(eBXRegP);
4365 match(eDXRegP);
4366 match(eSIRegP);
4367 match(eDIRegP);
4368
4369 format %{ %}
4370 interface(REG_INTER);
4371 %}
4372
4373 // Special Registers
4374 // Return a pointer value
4375 operand eAXRegP(eRegP reg) %{
4376 constraint(ALLOC_IN_RC(eax_reg));
4377 match(reg);
4378 format %{ "EAX" %}
4379 interface(REG_INTER);
4380 %}
4381
4382 // Used in AtomicAdd
4383 operand eBXRegP(eRegP reg) %{
4384 constraint(ALLOC_IN_RC(ebx_reg));
4385 match(reg);
4386 format %{ "EBX" %}
4387 interface(REG_INTER);
4388 %}
4389
4390 // Tail-call (interprocedural jump) to interpreter
4391 operand eCXRegP(eRegP reg) %{
4392 constraint(ALLOC_IN_RC(ecx_reg));
4393 match(reg);
4394 format %{ "ECX" %}
4395 interface(REG_INTER);
4396 %}
4397
4398 operand eSIRegP(eRegP reg) %{
4399 constraint(ALLOC_IN_RC(esi_reg));
4400 match(reg);
4401 format %{ "ESI" %}
4402 interface(REG_INTER);
4403 %}
4404
4405 // Used in rep stosw
4406 operand eDIRegP(eRegP reg) %{
4407 constraint(ALLOC_IN_RC(edi_reg));
4408 match(reg);
4409 format %{ "EDI" %}
4410 interface(REG_INTER);
4411 %}
4412
4413 operand eBPRegP() %{
4414 constraint(ALLOC_IN_RC(ebp_reg));
4415 match(RegP);
4416 format %{ "EBP" %}
4417 interface(REG_INTER);
4418 %}
4419
4420 operand eRegL() %{
4421 constraint(ALLOC_IN_RC(long_reg));
4422 match(RegL);
4423 match(eADXRegL);
4424
4425 format %{ %}
4426 interface(REG_INTER);
4427 %}
4428
4429 operand eADXRegL( eRegL reg ) %{
4430 constraint(ALLOC_IN_RC(eadx_reg));
4431 match(reg);
4432
4433 format %{ "EDX:EAX" %}
4434 interface(REG_INTER);
4435 %}
4436
4437 operand eBCXRegL( eRegL reg ) %{
4438 constraint(ALLOC_IN_RC(ebcx_reg));
4439 match(reg);
4440
4441 format %{ "EBX:ECX" %}
4442 interface(REG_INTER);
4443 %}
4444
4445 // Special case for integer high multiply
4446 operand eADXRegL_low_only() %{
4447 constraint(ALLOC_IN_RC(eadx_reg));
4448 match(RegL);
4449
4450 format %{ "EAX" %}
4451 interface(REG_INTER);
4452 %}
4453
4454 // Flags register, used as output of compare instructions
4455 operand eFlagsReg() %{
4456 constraint(ALLOC_IN_RC(int_flags));
4457 match(RegFlags);
4458
4459 format %{ "EFLAGS" %}
4460 interface(REG_INTER);
4461 %}
4462
4463 // Flags register, used as output of FLOATING POINT compare instructions
4464 operand eFlagsRegU() %{
4465 constraint(ALLOC_IN_RC(int_flags));
4466 match(RegFlags);
4467
4468 format %{ "EFLAGS_U" %}
4469 interface(REG_INTER);
4470 %}
4471
4472 operand eFlagsRegUCF() %{
4473 constraint(ALLOC_IN_RC(int_flags));
4474 match(RegFlags);
4475 predicate(false);
4476
4477 format %{ "EFLAGS_U_CF" %}
4478 interface(REG_INTER);
4479 %}
4480
4481 // Condition Code Register used by long compare
4482 operand flagsReg_long_LTGE() %{
4483 constraint(ALLOC_IN_RC(int_flags));
4484 match(RegFlags);
4485 format %{ "FLAGS_LTGE" %}
4486 interface(REG_INTER);
4487 %}
4488 operand flagsReg_long_EQNE() %{
4489 constraint(ALLOC_IN_RC(int_flags));
4490 match(RegFlags);
4491 format %{ "FLAGS_EQNE" %}
4492 interface(REG_INTER);
4493 %}
4494 operand flagsReg_long_LEGT() %{
4495 constraint(ALLOC_IN_RC(int_flags));
4496 match(RegFlags);
4497 format %{ "FLAGS_LEGT" %}
4498 interface(REG_INTER);
4499 %}
4500
4501 // Float register operands
4502 operand regDPR() %{
4503 predicate( UseSSE < 2 );
4504 constraint(ALLOC_IN_RC(fp_dbl_reg));
4505 match(RegD);
4506 match(regDPR1);
4507 match(regDPR2);
4508 format %{ %}
4509 interface(REG_INTER);
4510 %}
4511
4512 operand regDPR1(regDPR reg) %{
4513 predicate( UseSSE < 2 );
4514 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4515 match(reg);
4516 format %{ "FPR1" %}
4517 interface(REG_INTER);
4518 %}
4519
4520 operand regDPR2(regDPR reg) %{
4521 predicate( UseSSE < 2 );
4522 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4523 match(reg);
4524 format %{ "FPR2" %}
4525 interface(REG_INTER);
4526 %}
4527
4528 operand regnotDPR1(regDPR reg) %{
4529 predicate( UseSSE < 2 );
4530 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4531 match(reg);
4532 format %{ %}
4533 interface(REG_INTER);
4534 %}
4535
4536 // Float register operands
4537 operand regFPR() %{
4538 predicate( UseSSE < 2 );
4539 constraint(ALLOC_IN_RC(fp_flt_reg));
4540 match(RegF);
4541 match(regFPR1);
4542 format %{ %}
4543 interface(REG_INTER);
4544 %}
4545
4546 // Float register operands
4547 operand regFPR1(regFPR reg) %{
4548 predicate( UseSSE < 2 );
4549 constraint(ALLOC_IN_RC(fp_flt_reg0));
4550 match(reg);
4551 format %{ "FPR1" %}
4552 interface(REG_INTER);
4553 %}
4554
4555 // XMM Float register operands
4556 operand regF() %{
4557 predicate( UseSSE>=1 );
4558 constraint(ALLOC_IN_RC(float_reg));
4559 match(RegF);
4560 format %{ %}
4561 interface(REG_INTER);
4562 %}
4563
4564 // XMM Double register operands
4565 operand regD() %{
4566 predicate( UseSSE>=2 );
4567 constraint(ALLOC_IN_RC(double_reg));
4568 match(RegD);
4569 format %{ %}
4570 interface(REG_INTER);
4571 %}
4572
4573
4574 //----------Memory Operands----------------------------------------------------
4575 // Direct Memory Operand
4576 operand direct(immP addr) %{
4577 match(addr);
4578
4579 format %{ "[$addr]" %}
4580 interface(MEMORY_INTER) %{
4581 base(0xFFFFFFFF);
4582 index(0x4);
4583 scale(0x0);
4584 disp($addr);
4585 %}
4586 %}
4587
4588 // Indirect Memory Operand
4589 operand indirect(eRegP reg) %{
4590 constraint(ALLOC_IN_RC(int_reg));
4591 match(reg);
4592
4593 format %{ "[$reg]" %}
4594 interface(MEMORY_INTER) %{
4595 base($reg);
4596 index(0x4);
4597 scale(0x0);
4598 disp(0x0);
4599 %}
4600 %}
4601
4602 // Indirect Memory Plus Short Offset Operand
4603 operand indOffset8(eRegP reg, immI8 off) %{
4604 match(AddP reg off);
4605
4606 format %{ "[$reg + $off]" %}
4607 interface(MEMORY_INTER) %{
4608 base($reg);
4609 index(0x4);
4610 scale(0x0);
4611 disp($off);
4612 %}
4613 %}
4614
4615 // Indirect Memory Plus Long Offset Operand
4616 operand indOffset32(eRegP reg, immI off) %{
4617 match(AddP reg off);
4618
4619 format %{ "[$reg + $off]" %}
4620 interface(MEMORY_INTER) %{
4621 base($reg);
4622 index(0x4);
4623 scale(0x0);
4624 disp($off);
4625 %}
4626 %}
4627
4628 // Indirect Memory Plus Long Offset Operand
4629 operand indOffset32X(rRegI reg, immP off) %{
4630 match(AddP off reg);
4631
4632 format %{ "[$reg + $off]" %}
4633 interface(MEMORY_INTER) %{
4634 base($reg);
4635 index(0x4);
4636 scale(0x0);
4637 disp($off);
4638 %}
4639 %}
4640
4641 // Indirect Memory Plus Index Register Plus Offset Operand
4642 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4643 match(AddP (AddP reg ireg) off);
4644
4645 op_cost(10);
4646 format %{"[$reg + $off + $ireg]" %}
4647 interface(MEMORY_INTER) %{
4648 base($reg);
4649 index($ireg);
4650 scale(0x0);
4651 disp($off);
4652 %}
4653 %}
4654
4655 // Indirect Memory Plus Index Register Plus Offset Operand
4656 operand indIndex(eRegP reg, rRegI ireg) %{
4657 match(AddP reg ireg);
4658
4659 op_cost(10);
4660 format %{"[$reg + $ireg]" %}
4661 interface(MEMORY_INTER) %{
4662 base($reg);
4663 index($ireg);
4664 scale(0x0);
4665 disp(0x0);
4666 %}
4667 %}
4668
4669 // // -------------------------------------------------------------------------
4670 // // 486 architecture doesn't support "scale * index + offset" with out a base
4671 // // -------------------------------------------------------------------------
4672 // // Scaled Memory Operands
4673 // // Indirect Memory Times Scale Plus Offset Operand
4674 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4675 // match(AddP off (LShiftI ireg scale));
4676 //
4677 // op_cost(10);
4678 // format %{"[$off + $ireg << $scale]" %}
4679 // interface(MEMORY_INTER) %{
4680 // base(0x4);
4681 // index($ireg);
4682 // scale($scale);
4683 // disp($off);
4684 // %}
4685 // %}
4686
4687 // Indirect Memory Times Scale Plus Index Register
4688 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4689 match(AddP reg (LShiftI ireg scale));
4690
4691 op_cost(10);
4692 format %{"[$reg + $ireg << $scale]" %}
4693 interface(MEMORY_INTER) %{
4694 base($reg);
4695 index($ireg);
4696 scale($scale);
4697 disp(0x0);
4698 %}
4699 %}
4700
4701 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4702 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4703 match(AddP (AddP reg (LShiftI ireg scale)) off);
4704
4705 op_cost(10);
4706 format %{"[$reg + $off + $ireg << $scale]" %}
4707 interface(MEMORY_INTER) %{
4708 base($reg);
4709 index($ireg);
4710 scale($scale);
4711 disp($off);
4712 %}
4713 %}
4714
4715 //----------Load Long Memory Operands------------------------------------------
4716 // The load-long idiom will use it's address expression again after loading
4717 // the first word of the long. If the load-long destination overlaps with
4718 // registers used in the addressing expression, the 2nd half will be loaded
4719 // from a clobbered address. Fix this by requiring that load-long use
4720 // address registers that do not overlap with the load-long target.
4721
4722 // load-long support
4723 operand load_long_RegP() %{
4724 constraint(ALLOC_IN_RC(esi_reg));
4725 match(RegP);
4726 match(eSIRegP);
4727 op_cost(100);
4728 format %{ %}
4729 interface(REG_INTER);
4730 %}
4731
4732 // Indirect Memory Operand Long
4733 operand load_long_indirect(load_long_RegP reg) %{
4734 constraint(ALLOC_IN_RC(esi_reg));
4735 match(reg);
4736
4737 format %{ "[$reg]" %}
4738 interface(MEMORY_INTER) %{
4739 base($reg);
4740 index(0x4);
4741 scale(0x0);
4742 disp(0x0);
4743 %}
4744 %}
4745
4746 // Indirect Memory Plus Long Offset Operand
4747 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4748 match(AddP reg off);
4749
4750 format %{ "[$reg + $off]" %}
4751 interface(MEMORY_INTER) %{
4752 base($reg);
4753 index(0x4);
4754 scale(0x0);
4755 disp($off);
4756 %}
4757 %}
4758
4759 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4760
4761
4762 //----------Special Memory Operands--------------------------------------------
4763 // Stack Slot Operand - This operand is used for loading and storing temporary
4764 // values on the stack where a match requires a value to
4765 // flow through memory.
4766 operand stackSlotP(sRegP reg) %{
4767 constraint(ALLOC_IN_RC(stack_slots));
4768 // No match rule because this operand is only generated in matching
4769 format %{ "[$reg]" %}
4770 interface(MEMORY_INTER) %{
4771 base(0x4); // ESP
4772 index(0x4); // No Index
4773 scale(0x0); // No Scale
4774 disp($reg); // Stack Offset
4775 %}
4776 %}
4777
4778 operand stackSlotI(sRegI reg) %{
4779 constraint(ALLOC_IN_RC(stack_slots));
4780 // No match rule because this operand is only generated in matching
4781 format %{ "[$reg]" %}
4782 interface(MEMORY_INTER) %{
4783 base(0x4); // ESP
4784 index(0x4); // No Index
4785 scale(0x0); // No Scale
4786 disp($reg); // Stack Offset
4787 %}
4788 %}
4789
4790 operand stackSlotF(sRegF reg) %{
4791 constraint(ALLOC_IN_RC(stack_slots));
4792 // No match rule because this operand is only generated in matching
4793 format %{ "[$reg]" %}
4794 interface(MEMORY_INTER) %{
4795 base(0x4); // ESP
4796 index(0x4); // No Index
4797 scale(0x0); // No Scale
4798 disp($reg); // Stack Offset
4799 %}
4800 %}
4801
4802 operand stackSlotD(sRegD reg) %{
4803 constraint(ALLOC_IN_RC(stack_slots));
4804 // No match rule because this operand is only generated in matching
4805 format %{ "[$reg]" %}
4806 interface(MEMORY_INTER) %{
4807 base(0x4); // ESP
4808 index(0x4); // No Index
4809 scale(0x0); // No Scale
4810 disp($reg); // Stack Offset
4811 %}
4812 %}
4813
4814 operand stackSlotL(sRegL reg) %{
4815 constraint(ALLOC_IN_RC(stack_slots));
4816 // No match rule because this operand is only generated in matching
4817 format %{ "[$reg]" %}
4818 interface(MEMORY_INTER) %{
4819 base(0x4); // ESP
4820 index(0x4); // No Index
4821 scale(0x0); // No Scale
4822 disp($reg); // Stack Offset
4823 %}
4824 %}
4825
4826 //----------Memory Operands - Win95 Implicit Null Variants----------------
4827 // Indirect Memory Operand
4828 operand indirect_win95_safe(eRegP_no_EBP reg)
4829 %{
4830 constraint(ALLOC_IN_RC(int_reg));
4831 match(reg);
4832
4833 op_cost(100);
4834 format %{ "[$reg]" %}
4835 interface(MEMORY_INTER) %{
4836 base($reg);
4837 index(0x4);
4838 scale(0x0);
4839 disp(0x0);
4840 %}
4841 %}
4842
4843 // Indirect Memory Plus Short Offset Operand
4844 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4845 %{
4846 match(AddP reg off);
4847
4848 op_cost(100);
4849 format %{ "[$reg + $off]" %}
4850 interface(MEMORY_INTER) %{
4851 base($reg);
4852 index(0x4);
4853 scale(0x0);
4854 disp($off);
4855 %}
4856 %}
4857
4858 // Indirect Memory Plus Long Offset Operand
4859 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4860 %{
4861 match(AddP reg off);
4862
4863 op_cost(100);
4864 format %{ "[$reg + $off]" %}
4865 interface(MEMORY_INTER) %{
4866 base($reg);
4867 index(0x4);
4868 scale(0x0);
4869 disp($off);
4870 %}
4871 %}
4872
4873 // Indirect Memory Plus Index Register Plus Offset Operand
4874 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4875 %{
4876 match(AddP (AddP reg ireg) off);
4877
4878 op_cost(100);
4879 format %{"[$reg + $off + $ireg]" %}
4880 interface(MEMORY_INTER) %{
4881 base($reg);
4882 index($ireg);
4883 scale(0x0);
4884 disp($off);
4885 %}
4886 %}
4887
4888 // Indirect Memory Times Scale Plus Index Register
4889 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4890 %{
4891 match(AddP reg (LShiftI ireg scale));
4892
4893 op_cost(100);
4894 format %{"[$reg + $ireg << $scale]" %}
4895 interface(MEMORY_INTER) %{
4896 base($reg);
4897 index($ireg);
4898 scale($scale);
4899 disp(0x0);
4900 %}
4901 %}
4902
4903 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4904 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4905 %{
4906 match(AddP (AddP reg (LShiftI ireg scale)) off);
4907
4908 op_cost(100);
4909 format %{"[$reg + $off + $ireg << $scale]" %}
4910 interface(MEMORY_INTER) %{
4911 base($reg);
4912 index($ireg);
4913 scale($scale);
4914 disp($off);
4915 %}
4916 %}
4917
4918 //----------Conditional Branch Operands----------------------------------------
4919 // Comparison Op - This is the operation of the comparison, and is limited to
4920 // the following set of codes:
4921 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4922 //
4923 // Other attributes of the comparison, such as unsignedness, are specified
4924 // by the comparison instruction that sets a condition code flags register.
4925 // That result is represented by a flags operand whose subtype is appropriate
4926 // to the unsignedness (etc.) of the comparison.
4927 //
4928 // Later, the instruction which matches both the Comparison Op (a Bool) and
4929 // the flags (produced by the Cmp) specifies the coding of the comparison op
4930 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4931
4932 // Comparision Code
4933 operand cmpOp() %{
4934 match(Bool);
4935
4936 format %{ "" %}
4937 interface(COND_INTER) %{
4938 equal(0x4, "e");
4939 not_equal(0x5, "ne");
4940 less(0xC, "l");
4941 greater_equal(0xD, "ge");
4942 less_equal(0xE, "le");
4943 greater(0xF, "g");
4944 overflow(0x0, "o");
4945 no_overflow(0x1, "no");
4946 %}
4947 %}
4948
4949 // Comparison Code, unsigned compare. Used by FP also, with
4950 // C2 (unordered) turned into GT or LT already. The other bits
4951 // C0 and C3 are turned into Carry & Zero flags.
4952 operand cmpOpU() %{
4953 match(Bool);
4954
4955 format %{ "" %}
4956 interface(COND_INTER) %{
4957 equal(0x4, "e");
4958 not_equal(0x5, "ne");
4959 less(0x2, "b");
4960 greater_equal(0x3, "nb");
4961 less_equal(0x6, "be");
4962 greater(0x7, "nbe");
4963 overflow(0x0, "o");
4964 no_overflow(0x1, "no");
4965 %}
4966 %}
4967
4968 // Floating comparisons that don't require any fixup for the unordered case
4969 operand cmpOpUCF() %{
4970 match(Bool);
4971 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4972 n->as_Bool()->_test._test == BoolTest::ge ||
4973 n->as_Bool()->_test._test == BoolTest::le ||
4974 n->as_Bool()->_test._test == BoolTest::gt);
4975 format %{ "" %}
4976 interface(COND_INTER) %{
4977 equal(0x4, "e");
4978 not_equal(0x5, "ne");
4979 less(0x2, "b");
4980 greater_equal(0x3, "nb");
4981 less_equal(0x6, "be");
4982 greater(0x7, "nbe");
4983 overflow(0x0, "o");
4984 no_overflow(0x1, "no");
4985 %}
4986 %}
4987
4988
4989 // Floating comparisons that can be fixed up with extra conditional jumps
4990 operand cmpOpUCF2() %{
4991 match(Bool);
4992 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4993 n->as_Bool()->_test._test == BoolTest::eq);
4994 format %{ "" %}
4995 interface(COND_INTER) %{
4996 equal(0x4, "e");
4997 not_equal(0x5, "ne");
4998 less(0x2, "b");
4999 greater_equal(0x3, "nb");
5000 less_equal(0x6, "be");
5001 greater(0x7, "nbe");
5002 overflow(0x0, "o");
5003 no_overflow(0x1, "no");
5004 %}
5005 %}
5006
5007 // Comparison Code for FP conditional move
5008 operand cmpOp_fcmov() %{
5009 match(Bool);
5010
5011 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5012 n->as_Bool()->_test._test != BoolTest::no_overflow);
5013 format %{ "" %}
5014 interface(COND_INTER) %{
5015 equal (0x0C8);
5016 not_equal (0x1C8);
5017 less (0x0C0);
5018 greater_equal(0x1C0);
5019 less_equal (0x0D0);
5020 greater (0x1D0);
5021 overflow(0x0, "o"); // not really supported by the instruction
5022 no_overflow(0x1, "no"); // not really supported by the instruction
5023 %}
5024 %}
5025
5026 // Comparision Code used in long compares
5027 operand cmpOp_commute() %{
5028 match(Bool);
5029
5030 format %{ "" %}
5031 interface(COND_INTER) %{
5032 equal(0x4, "e");
5033 not_equal(0x5, "ne");
5034 less(0xF, "g");
5035 greater_equal(0xE, "le");
5036 less_equal(0xD, "ge");
5037 greater(0xC, "l");
5038 overflow(0x0, "o");
5039 no_overflow(0x1, "no");
5040 %}
5041 %}
5042
5043 //----------OPERAND CLASSES----------------------------------------------------
5044 // Operand Classes are groups of operands that are used as to simplify
5045 // instruction definitions by not requiring the AD writer to specify separate
5046 // instructions for every form of operand when the instruction accepts
5047 // multiple operand types with the same basic encoding and format. The classic
5048 // case of this is memory operands.
5049
5050 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5051 indIndex, indIndexScale, indIndexScaleOffset);
5052
5053 // Long memory operations are encoded in 2 instructions and a +4 offset.
5054 // This means some kind of offset is always required and you cannot use
5055 // an oop as the offset (done when working on static globals).
5056 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5057 indIndex, indIndexScale, indIndexScaleOffset);
5058
5059
5060 //----------PIPELINE-----------------------------------------------------------
5061 // Rules which define the behavior of the target architectures pipeline.
5062 pipeline %{
5063
5064 //----------ATTRIBUTES---------------------------------------------------------
5065 attributes %{
5066 variable_size_instructions; // Fixed size instructions
5067 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5068 instruction_unit_size = 1; // An instruction is 1 bytes long
5069 instruction_fetch_unit_size = 16; // The processor fetches one line
5070 instruction_fetch_units = 1; // of 16 bytes
5071
5072 // List of nop instructions
5073 nops( MachNop );
5074 %}
5075
5076 //----------RESOURCES----------------------------------------------------------
5077 // Resources are the functional units available to the machine
5078
5079 // Generic P2/P3 pipeline
5080 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5081 // 3 instructions decoded per cycle.
5082 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5083 // 2 ALU op, only ALU0 handles mul/div instructions.
5084 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5085 MS0, MS1, MEM = MS0 | MS1,
5086 BR, FPU,
5087 ALU0, ALU1, ALU = ALU0 | ALU1 );
5088
5089 //----------PIPELINE DESCRIPTION-----------------------------------------------
5090 // Pipeline Description specifies the stages in the machine's pipeline
5091
5092 // Generic P2/P3 pipeline
5093 pipe_desc(S0, S1, S2, S3, S4, S5);
5094
5095 //----------PIPELINE CLASSES---------------------------------------------------
5096 // Pipeline Classes describe the stages in which input and output are
5097 // referenced by the hardware pipeline.
5098
5099 // Naming convention: ialu or fpu
5100 // Then: _reg
5101 // Then: _reg if there is a 2nd register
5102 // Then: _long if it's a pair of instructions implementing a long
5103 // Then: _fat if it requires the big decoder
5104 // Or: _mem if it requires the big decoder and a memory unit.
5105
5106 // Integer ALU reg operation
5107 pipe_class ialu_reg(rRegI dst) %{
5108 single_instruction;
5109 dst : S4(write);
5110 dst : S3(read);
5111 DECODE : S0; // any decoder
5112 ALU : S3; // any alu
5113 %}
5114
5115 // Long ALU reg operation
5116 pipe_class ialu_reg_long(eRegL dst) %{
5117 instruction_count(2);
5118 dst : S4(write);
5119 dst : S3(read);
5120 DECODE : S0(2); // any 2 decoders
5121 ALU : S3(2); // both alus
5122 %}
5123
5124 // Integer ALU reg operation using big decoder
5125 pipe_class ialu_reg_fat(rRegI dst) %{
5126 single_instruction;
5127 dst : S4(write);
5128 dst : S3(read);
5129 D0 : S0; // big decoder only
5130 ALU : S3; // any alu
5131 %}
5132
5133 // Long ALU reg operation using big decoder
5134 pipe_class ialu_reg_long_fat(eRegL dst) %{
5135 instruction_count(2);
5136 dst : S4(write);
5137 dst : S3(read);
5138 D0 : S0(2); // big decoder only; twice
5139 ALU : S3(2); // any 2 alus
5140 %}
5141
5142 // Integer ALU reg-reg operation
5143 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5144 single_instruction;
5145 dst : S4(write);
5146 src : S3(read);
5147 DECODE : S0; // any decoder
5148 ALU : S3; // any alu
5149 %}
5150
5151 // Long ALU reg-reg operation
5152 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5153 instruction_count(2);
5154 dst : S4(write);
5155 src : S3(read);
5156 DECODE : S0(2); // any 2 decoders
5157 ALU : S3(2); // both alus
5158 %}
5159
5160 // Integer ALU reg-reg operation
5161 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5162 single_instruction;
5163 dst : S4(write);
5164 src : S3(read);
5165 D0 : S0; // big decoder only
5166 ALU : S3; // any alu
5167 %}
5168
5169 // Long ALU reg-reg operation
5170 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5171 instruction_count(2);
5172 dst : S4(write);
5173 src : S3(read);
5174 D0 : S0(2); // big decoder only; twice
5175 ALU : S3(2); // both alus
5176 %}
5177
5178 // Integer ALU reg-mem operation
5179 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5180 single_instruction;
5181 dst : S5(write);
5182 mem : S3(read);
5183 D0 : S0; // big decoder only
5184 ALU : S4; // any alu
5185 MEM : S3; // any mem
5186 %}
5187
5188 // Long ALU reg-mem operation
5189 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5190 instruction_count(2);
5191 dst : S5(write);
5192 mem : S3(read);
5193 D0 : S0(2); // big decoder only; twice
5194 ALU : S4(2); // any 2 alus
5195 MEM : S3(2); // both mems
5196 %}
5197
5198 // Integer mem operation (prefetch)
5199 pipe_class ialu_mem(memory mem)
5200 %{
5201 single_instruction;
5202 mem : S3(read);
5203 D0 : S0; // big decoder only
5204 MEM : S3; // any mem
5205 %}
5206
5207 // Integer Store to Memory
5208 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5209 single_instruction;
5210 mem : S3(read);
5211 src : S5(read);
5212 D0 : S0; // big decoder only
5213 ALU : S4; // any alu
5214 MEM : S3;
5215 %}
5216
5217 // Long Store to Memory
5218 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5219 instruction_count(2);
5220 mem : S3(read);
5221 src : S5(read);
5222 D0 : S0(2); // big decoder only; twice
5223 ALU : S4(2); // any 2 alus
5224 MEM : S3(2); // Both mems
5225 %}
5226
5227 // Integer Store to Memory
5228 pipe_class ialu_mem_imm(memory mem) %{
5229 single_instruction;
5230 mem : S3(read);
5231 D0 : S0; // big decoder only
5232 ALU : S4; // any alu
5233 MEM : S3;
5234 %}
5235
5236 // Integer ALU0 reg-reg operation
5237 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5238 single_instruction;
5239 dst : S4(write);
5240 src : S3(read);
5241 D0 : S0; // Big decoder only
5242 ALU0 : S3; // only alu0
5243 %}
5244
5245 // Integer ALU0 reg-mem operation
5246 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5247 single_instruction;
5248 dst : S5(write);
5249 mem : S3(read);
5250 D0 : S0; // big decoder only
5251 ALU0 : S4; // ALU0 only
5252 MEM : S3; // any mem
5253 %}
5254
5255 // Integer ALU reg-reg operation
5256 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5257 single_instruction;
5258 cr : S4(write);
5259 src1 : S3(read);
5260 src2 : S3(read);
5261 DECODE : S0; // any decoder
5262 ALU : S3; // any alu
5263 %}
5264
5265 // Integer ALU reg-imm operation
5266 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5267 single_instruction;
5268 cr : S4(write);
5269 src1 : S3(read);
5270 DECODE : S0; // any decoder
5271 ALU : S3; // any alu
5272 %}
5273
5274 // Integer ALU reg-mem operation
5275 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5276 single_instruction;
5277 cr : S4(write);
5278 src1 : S3(read);
5279 src2 : S3(read);
5280 D0 : S0; // big decoder only
5281 ALU : S4; // any alu
5282 MEM : S3;
5283 %}
5284
5285 // Conditional move reg-reg
5286 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5287 instruction_count(4);
5288 y : S4(read);
5289 q : S3(read);
5290 p : S3(read);
5291 DECODE : S0(4); // any decoder
5292 %}
5293
5294 // Conditional move reg-reg
5295 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5296 single_instruction;
5297 dst : S4(write);
5298 src : S3(read);
5299 cr : S3(read);
5300 DECODE : S0; // any decoder
5301 %}
5302
5303 // Conditional move reg-mem
5304 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5305 single_instruction;
5306 dst : S4(write);
5307 src : S3(read);
5308 cr : S3(read);
5309 DECODE : S0; // any decoder
5310 MEM : S3;
5311 %}
5312
5313 // Conditional move reg-reg long
5314 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5315 single_instruction;
5316 dst : S4(write);
5317 src : S3(read);
5318 cr : S3(read);
5319 DECODE : S0(2); // any 2 decoders
5320 %}
5321
5322 // Conditional move double reg-reg
5323 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5324 single_instruction;
5325 dst : S4(write);
5326 src : S3(read);
5327 cr : S3(read);
5328 DECODE : S0; // any decoder
5329 %}
5330
5331 // Float reg-reg operation
5332 pipe_class fpu_reg(regDPR dst) %{
5333 instruction_count(2);
5334 dst : S3(read);
5335 DECODE : S0(2); // any 2 decoders
5336 FPU : S3;
5337 %}
5338
5339 // Float reg-reg operation
5340 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5341 instruction_count(2);
5342 dst : S4(write);
5343 src : S3(read);
5344 DECODE : S0(2); // any 2 decoders
5345 FPU : S3;
5346 %}
5347
5348 // Float reg-reg operation
5349 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5350 instruction_count(3);
5351 dst : S4(write);
5352 src1 : S3(read);
5353 src2 : S3(read);
5354 DECODE : S0(3); // any 3 decoders
5355 FPU : S3(2);
5356 %}
5357
5358 // Float reg-reg operation
5359 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5360 instruction_count(4);
5361 dst : S4(write);
5362 src1 : S3(read);
5363 src2 : S3(read);
5364 src3 : S3(read);
5365 DECODE : S0(4); // any 3 decoders
5366 FPU : S3(2);
5367 %}
5368
5369 // Float reg-reg operation
5370 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5371 instruction_count(4);
5372 dst : S4(write);
5373 src1 : S3(read);
5374 src2 : S3(read);
5375 src3 : S3(read);
5376 DECODE : S1(3); // any 3 decoders
5377 D0 : S0; // Big decoder only
5378 FPU : S3(2);
5379 MEM : S3;
5380 %}
5381
5382 // Float reg-mem operation
5383 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5384 instruction_count(2);
5385 dst : S5(write);
5386 mem : S3(read);
5387 D0 : S0; // big decoder only
5388 DECODE : S1; // any decoder for FPU POP
5389 FPU : S4;
5390 MEM : S3; // any mem
5391 %}
5392
5393 // Float reg-mem operation
5394 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5395 instruction_count(3);
5396 dst : S5(write);
5397 src1 : S3(read);
5398 mem : S3(read);
5399 D0 : S0; // big decoder only
5400 DECODE : S1(2); // any decoder for FPU POP
5401 FPU : S4;
5402 MEM : S3; // any mem
5403 %}
5404
5405 // Float mem-reg operation
5406 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5407 instruction_count(2);
5408 src : S5(read);
5409 mem : S3(read);
5410 DECODE : S0; // any decoder for FPU PUSH
5411 D0 : S1; // big decoder only
5412 FPU : S4;
5413 MEM : S3; // any mem
5414 %}
5415
5416 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5417 instruction_count(3);
5418 src1 : S3(read);
5419 src2 : S3(read);
5420 mem : S3(read);
5421 DECODE : S0(2); // any decoder for FPU PUSH
5422 D0 : S1; // big decoder only
5423 FPU : S4;
5424 MEM : S3; // any mem
5425 %}
5426
5427 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5428 instruction_count(3);
5429 src1 : S3(read);
5430 src2 : S3(read);
5431 mem : S4(read);
5432 DECODE : S0; // any decoder for FPU PUSH
5433 D0 : S0(2); // big decoder only
5434 FPU : S4;
5435 MEM : S3(2); // any mem
5436 %}
5437
5438 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5439 instruction_count(2);
5440 src1 : S3(read);
5441 dst : S4(read);
5442 D0 : S0(2); // big decoder only
5443 MEM : S3(2); // any mem
5444 %}
5445
5446 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5447 instruction_count(3);
5448 src1 : S3(read);
5449 src2 : S3(read);
5450 dst : S4(read);
5451 D0 : S0(3); // big decoder only
5452 FPU : S4;
5453 MEM : S3(3); // any mem
5454 %}
5455
5456 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5457 instruction_count(3);
5458 src1 : S4(read);
5459 mem : S4(read);
5460 DECODE : S0; // any decoder for FPU PUSH
5461 D0 : S0(2); // big decoder only
5462 FPU : S4;
5463 MEM : S3(2); // any mem
5464 %}
5465
5466 // Float load constant
5467 pipe_class fpu_reg_con(regDPR dst) %{
5468 instruction_count(2);
5469 dst : S5(write);
5470 D0 : S0; // big decoder only for the load
5471 DECODE : S1; // any decoder for FPU POP
5472 FPU : S4;
5473 MEM : S3; // any mem
5474 %}
5475
5476 // Float load constant
5477 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5478 instruction_count(3);
5479 dst : S5(write);
5480 src : S3(read);
5481 D0 : S0; // big decoder only for the load
5482 DECODE : S1(2); // any decoder for FPU POP
5483 FPU : S4;
5484 MEM : S3; // any mem
5485 %}
5486
5487 // UnConditional branch
5488 pipe_class pipe_jmp( label labl ) %{
5489 single_instruction;
5490 BR : S3;
5491 %}
5492
5493 // Conditional branch
5494 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5495 single_instruction;
5496 cr : S1(read);
5497 BR : S3;
5498 %}
5499
5500 // Allocation idiom
5501 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5502 instruction_count(1); force_serialization;
5503 fixed_latency(6);
5504 heap_ptr : S3(read);
5505 DECODE : S0(3);
5506 D0 : S2;
5507 MEM : S3;
5508 ALU : S3(2);
5509 dst : S5(write);
5510 BR : S5;
5511 %}
5512
5513 // Generic big/slow expanded idiom
5514 pipe_class pipe_slow( ) %{
5515 instruction_count(10); multiple_bundles; force_serialization;
5516 fixed_latency(100);
5517 D0 : S0(2);
5518 MEM : S3(2);
5519 %}
5520
5521 // The real do-nothing guy
5522 pipe_class empty( ) %{
5523 instruction_count(0);
5524 %}
5525
5526 // Define the class for the Nop node
5527 define %{
5528 MachNop = empty;
5529 %}
5530
5531 %}
5532
5533 //----------INSTRUCTIONS-------------------------------------------------------
5534 //
5535 // match -- States which machine-independent subtree may be replaced
5536 // by this instruction.
5537 // ins_cost -- The estimated cost of this instruction is used by instruction
5538 // selection to identify a minimum cost tree of machine
5539 // instructions that matches a tree of machine-independent
5540 // instructions.
5541 // format -- A string providing the disassembly for this instruction.
5542 // The value of an instruction's operand may be inserted
5543 // by referring to it with a '$' prefix.
5544 // opcode -- Three instruction opcodes may be provided. These are referred
5545 // to within an encode class as $primary, $secondary, and $tertiary
5546 // respectively. The primary opcode is commonly used to
5547 // indicate the type of machine instruction, while secondary
5548 // and tertiary are often used for prefix options or addressing
5549 // modes.
5550 // ins_encode -- A list of encode classes with parameters. The encode class
5551 // name must have been defined in an 'enc_class' specification
5552 // in the encode section of the architecture description.
5553
5554 //----------BSWAP-Instruction--------------------------------------------------
5555 instruct bytes_reverse_int(rRegI dst) %{
5556 match(Set dst (ReverseBytesI dst));
5557
5558 format %{ "BSWAP $dst" %}
5559 opcode(0x0F, 0xC8);
5560 ins_encode( OpcP, OpcSReg(dst) );
5561 ins_pipe( ialu_reg );
5562 %}
5563
5564 instruct bytes_reverse_long(eRegL dst) %{
5565 match(Set dst (ReverseBytesL dst));
5566
5567 format %{ "BSWAP $dst.lo\n\t"
5568 "BSWAP $dst.hi\n\t"
5569 "XCHG $dst.lo $dst.hi" %}
5570
5571 ins_cost(125);
5572 ins_encode( bswap_long_bytes(dst) );
5573 ins_pipe( ialu_reg_reg);
5574 %}
5575
5576 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5577 match(Set dst (ReverseBytesUS dst));
5578 effect(KILL cr);
5579
5580 format %{ "BSWAP $dst\n\t"
5581 "SHR $dst,16\n\t" %}
5582 ins_encode %{
5583 __ bswapl($dst$$Register);
5584 __ shrl($dst$$Register, 16);
5585 %}
5586 ins_pipe( ialu_reg );
5587 %}
5588
5589 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5590 match(Set dst (ReverseBytesS dst));
5591 effect(KILL cr);
5592
5593 format %{ "BSWAP $dst\n\t"
5594 "SAR $dst,16\n\t" %}
5595 ins_encode %{
5596 __ bswapl($dst$$Register);
5597 __ sarl($dst$$Register, 16);
5598 %}
5599 ins_pipe( ialu_reg );
5600 %}
5601
5602
5603 //---------- Zeros Count Instructions ------------------------------------------
5604
5605 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5606 predicate(UseCountLeadingZerosInstruction);
5607 match(Set dst (CountLeadingZerosI src));
5608 effect(KILL cr);
5609
5610 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5611 ins_encode %{
5612 __ lzcntl($dst$$Register, $src$$Register);
5613 %}
5614 ins_pipe(ialu_reg);
5615 %}
5616
5617 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5618 predicate(!UseCountLeadingZerosInstruction);
5619 match(Set dst (CountLeadingZerosI src));
5620 effect(KILL cr);
5621
5622 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5623 "JNZ skip\n\t"
5624 "MOV $dst, -1\n"
5625 "skip:\n\t"
5626 "NEG $dst\n\t"
5627 "ADD $dst, 31" %}
5628 ins_encode %{
5629 Register Rdst = $dst$$Register;
5630 Register Rsrc = $src$$Register;
5631 Label skip;
5632 __ bsrl(Rdst, Rsrc);
5633 __ jccb(Assembler::notZero, skip);
5634 __ movl(Rdst, -1);
5635 __ bind(skip);
5636 __ negl(Rdst);
5637 __ addl(Rdst, BitsPerInt - 1);
5638 %}
5639 ins_pipe(ialu_reg);
5640 %}
5641
5642 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5643 predicate(UseCountLeadingZerosInstruction);
5644 match(Set dst (CountLeadingZerosL src));
5645 effect(TEMP dst, KILL cr);
5646
5647 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5648 "JNC done\n\t"
5649 "LZCNT $dst, $src.lo\n\t"
5650 "ADD $dst, 32\n"
5651 "done:" %}
5652 ins_encode %{
5653 Register Rdst = $dst$$Register;
5654 Register Rsrc = $src$$Register;
5655 Label done;
5656 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5657 __ jccb(Assembler::carryClear, done);
5658 __ lzcntl(Rdst, Rsrc);
5659 __ addl(Rdst, BitsPerInt);
5660 __ bind(done);
5661 %}
5662 ins_pipe(ialu_reg);
5663 %}
5664
5665 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5666 predicate(!UseCountLeadingZerosInstruction);
5667 match(Set dst (CountLeadingZerosL src));
5668 effect(TEMP dst, KILL cr);
5669
5670 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5671 "JZ msw_is_zero\n\t"
5672 "ADD $dst, 32\n\t"
5673 "JMP not_zero\n"
5674 "msw_is_zero:\n\t"
5675 "BSR $dst, $src.lo\n\t"
5676 "JNZ not_zero\n\t"
5677 "MOV $dst, -1\n"
5678 "not_zero:\n\t"
5679 "NEG $dst\n\t"
5680 "ADD $dst, 63\n" %}
5681 ins_encode %{
5682 Register Rdst = $dst$$Register;
5683 Register Rsrc = $src$$Register;
5684 Label msw_is_zero;
5685 Label not_zero;
5686 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5687 __ jccb(Assembler::zero, msw_is_zero);
5688 __ addl(Rdst, BitsPerInt);
5689 __ jmpb(not_zero);
5690 __ bind(msw_is_zero);
5691 __ bsrl(Rdst, Rsrc);
5692 __ jccb(Assembler::notZero, not_zero);
5693 __ movl(Rdst, -1);
5694 __ bind(not_zero);
5695 __ negl(Rdst);
5696 __ addl(Rdst, BitsPerLong - 1);
5697 %}
5698 ins_pipe(ialu_reg);
5699 %}
5700
5701 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5702 match(Set dst (CountTrailingZerosI src));
5703 effect(KILL cr);
5704
5705 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5706 "JNZ done\n\t"
5707 "MOV $dst, 32\n"
5708 "done:" %}
5709 ins_encode %{
5710 Register Rdst = $dst$$Register;
5711 Label done;
5712 __ bsfl(Rdst, $src$$Register);
5713 __ jccb(Assembler::notZero, done);
5714 __ movl(Rdst, BitsPerInt);
5715 __ bind(done);
5716 %}
5717 ins_pipe(ialu_reg);
5718 %}
5719
5720 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5721 match(Set dst (CountTrailingZerosL src));
5722 effect(TEMP dst, KILL cr);
5723
5724 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5725 "JNZ done\n\t"
5726 "BSF $dst, $src.hi\n\t"
5727 "JNZ msw_not_zero\n\t"
5728 "MOV $dst, 32\n"
5729 "msw_not_zero:\n\t"
5730 "ADD $dst, 32\n"
5731 "done:" %}
5732 ins_encode %{
5733 Register Rdst = $dst$$Register;
5734 Register Rsrc = $src$$Register;
5735 Label msw_not_zero;
5736 Label done;
5737 __ bsfl(Rdst, Rsrc);
5738 __ jccb(Assembler::notZero, done);
5739 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5740 __ jccb(Assembler::notZero, msw_not_zero);
5741 __ movl(Rdst, BitsPerInt);
5742 __ bind(msw_not_zero);
5743 __ addl(Rdst, BitsPerInt);
5744 __ bind(done);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749
5750 //---------- Population Count Instructions -------------------------------------
5751
5752 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5753 predicate(UsePopCountInstruction);
5754 match(Set dst (PopCountI src));
5755 effect(KILL cr);
5756
5757 format %{ "POPCNT $dst, $src" %}
5758 ins_encode %{
5759 __ popcntl($dst$$Register, $src$$Register);
5760 %}
5761 ins_pipe(ialu_reg);
5762 %}
5763
5764 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5765 predicate(UsePopCountInstruction);
5766 match(Set dst (PopCountI (LoadI mem)));
5767 effect(KILL cr);
5768
5769 format %{ "POPCNT $dst, $mem" %}
5770 ins_encode %{
5771 __ popcntl($dst$$Register, $mem$$Address);
5772 %}
5773 ins_pipe(ialu_reg);
5774 %}
5775
5776 // Note: Long.bitCount(long) returns an int.
5777 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5778 predicate(UsePopCountInstruction);
5779 match(Set dst (PopCountL src));
5780 effect(KILL cr, TEMP tmp, TEMP dst);
5781
5782 format %{ "POPCNT $dst, $src.lo\n\t"
5783 "POPCNT $tmp, $src.hi\n\t"
5784 "ADD $dst, $tmp" %}
5785 ins_encode %{
5786 __ popcntl($dst$$Register, $src$$Register);
5787 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5788 __ addl($dst$$Register, $tmp$$Register);
5789 %}
5790 ins_pipe(ialu_reg);
5791 %}
5792
5793 // Note: Long.bitCount(long) returns an int.
5794 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5795 predicate(UsePopCountInstruction);
5796 match(Set dst (PopCountL (LoadL mem)));
5797 effect(KILL cr, TEMP tmp, TEMP dst);
5798
5799 format %{ "POPCNT $dst, $mem\n\t"
5800 "POPCNT $tmp, $mem+4\n\t"
5801 "ADD $dst, $tmp" %}
5802 ins_encode %{
5803 //__ popcntl($dst$$Register, $mem$$Address$$first);
5804 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5805 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5806 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5807 __ addl($dst$$Register, $tmp$$Register);
5808 %}
5809 ins_pipe(ialu_reg);
5810 %}
5811
5812
5813 //----------Load/Store/Move Instructions---------------------------------------
5814 //----------Load Instructions--------------------------------------------------
5815 // Load Byte (8bit signed)
5816 instruct loadB(xRegI dst, memory mem) %{
5817 match(Set dst (LoadB mem));
5818
5819 ins_cost(125);
5820 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5821
5822 ins_encode %{
5823 __ movsbl($dst$$Register, $mem$$Address);
5824 %}
5825
5826 ins_pipe(ialu_reg_mem);
5827 %}
5828
5829 // Load Byte (8bit signed) into Long Register
5830 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5831 match(Set dst (ConvI2L (LoadB mem)));
5832 effect(KILL cr);
5833
5834 ins_cost(375);
5835 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5836 "MOV $dst.hi,$dst.lo\n\t"
5837 "SAR $dst.hi,7" %}
5838
5839 ins_encode %{
5840 __ movsbl($dst$$Register, $mem$$Address);
5841 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5842 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5843 %}
5844
5845 ins_pipe(ialu_reg_mem);
5846 %}
5847
5848 // Load Unsigned Byte (8bit UNsigned)
5849 instruct loadUB(xRegI dst, memory mem) %{
5850 match(Set dst (LoadUB mem));
5851
5852 ins_cost(125);
5853 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5854
5855 ins_encode %{
5856 __ movzbl($dst$$Register, $mem$$Address);
5857 %}
5858
5859 ins_pipe(ialu_reg_mem);
5860 %}
5861
5862 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5863 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5864 match(Set dst (ConvI2L (LoadUB mem)));
5865 effect(KILL cr);
5866
5867 ins_cost(250);
5868 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5869 "XOR $dst.hi,$dst.hi" %}
5870
5871 ins_encode %{
5872 Register Rdst = $dst$$Register;
5873 __ movzbl(Rdst, $mem$$Address);
5874 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5875 %}
5876
5877 ins_pipe(ialu_reg_mem);
5878 %}
5879
5880 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5881 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5882 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5883 effect(KILL cr);
5884
5885 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5886 "XOR $dst.hi,$dst.hi\n\t"
5887 "AND $dst.lo,$mask" %}
5888 ins_encode %{
5889 Register Rdst = $dst$$Register;
5890 __ movzbl(Rdst, $mem$$Address);
5891 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5892 __ andl(Rdst, $mask$$constant);
5893 %}
5894 ins_pipe(ialu_reg_mem);
5895 %}
5896
5897 // Load Short (16bit signed)
5898 instruct loadS(rRegI dst, memory mem) %{
5899 match(Set dst (LoadS mem));
5900
5901 ins_cost(125);
5902 format %{ "MOVSX $dst,$mem\t# short" %}
5903
5904 ins_encode %{
5905 __ movswl($dst$$Register, $mem$$Address);
5906 %}
5907
5908 ins_pipe(ialu_reg_mem);
5909 %}
5910
5911 // Load Short (16 bit signed) to Byte (8 bit signed)
5912 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5913 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5914
5915 ins_cost(125);
5916 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5917 ins_encode %{
5918 __ movsbl($dst$$Register, $mem$$Address);
5919 %}
5920 ins_pipe(ialu_reg_mem);
5921 %}
5922
5923 // Load Short (16bit signed) into Long Register
5924 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5925 match(Set dst (ConvI2L (LoadS mem)));
5926 effect(KILL cr);
5927
5928 ins_cost(375);
5929 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5930 "MOV $dst.hi,$dst.lo\n\t"
5931 "SAR $dst.hi,15" %}
5932
5933 ins_encode %{
5934 __ movswl($dst$$Register, $mem$$Address);
5935 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5936 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5937 %}
5938
5939 ins_pipe(ialu_reg_mem);
5940 %}
5941
5942 // Load Unsigned Short/Char (16bit unsigned)
5943 instruct loadUS(rRegI dst, memory mem) %{
5944 match(Set dst (LoadUS mem));
5945
5946 ins_cost(125);
5947 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5948
5949 ins_encode %{
5950 __ movzwl($dst$$Register, $mem$$Address);
5951 %}
5952
5953 ins_pipe(ialu_reg_mem);
5954 %}
5955
5956 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5957 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5958 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5959
5960 ins_cost(125);
5961 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5962 ins_encode %{
5963 __ movsbl($dst$$Register, $mem$$Address);
5964 %}
5965 ins_pipe(ialu_reg_mem);
5966 %}
5967
5968 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5969 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5970 match(Set dst (ConvI2L (LoadUS mem)));
5971 effect(KILL cr);
5972
5973 ins_cost(250);
5974 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5975 "XOR $dst.hi,$dst.hi" %}
5976
5977 ins_encode %{
5978 __ movzwl($dst$$Register, $mem$$Address);
5979 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5980 %}
5981
5982 ins_pipe(ialu_reg_mem);
5983 %}
5984
5985 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5986 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5987 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5988 effect(KILL cr);
5989
5990 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5991 "XOR $dst.hi,$dst.hi" %}
5992 ins_encode %{
5993 Register Rdst = $dst$$Register;
5994 __ movzbl(Rdst, $mem$$Address);
5995 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5996 %}
5997 ins_pipe(ialu_reg_mem);
5998 %}
5999
6000 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6001 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6002 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6003 effect(KILL cr);
6004
6005 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6006 "XOR $dst.hi,$dst.hi\n\t"
6007 "AND $dst.lo,$mask" %}
6008 ins_encode %{
6009 Register Rdst = $dst$$Register;
6010 __ movzwl(Rdst, $mem$$Address);
6011 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6012 __ andl(Rdst, $mask$$constant);
6013 %}
6014 ins_pipe(ialu_reg_mem);
6015 %}
6016
6017 // Load Integer
6018 instruct loadI(rRegI dst, memory mem) %{
6019 match(Set dst (LoadI mem));
6020
6021 ins_cost(125);
6022 format %{ "MOV $dst,$mem\t# int" %}
6023
6024 ins_encode %{
6025 __ movl($dst$$Register, $mem$$Address);
6026 %}
6027
6028 ins_pipe(ialu_reg_mem);
6029 %}
6030
6031 // Load Integer (32 bit signed) to Byte (8 bit signed)
6032 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6033 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6034
6035 ins_cost(125);
6036 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6037 ins_encode %{
6038 __ movsbl($dst$$Register, $mem$$Address);
6039 %}
6040 ins_pipe(ialu_reg_mem);
6041 %}
6042
6043 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6044 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6045 match(Set dst (AndI (LoadI mem) mask));
6046
6047 ins_cost(125);
6048 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6049 ins_encode %{
6050 __ movzbl($dst$$Register, $mem$$Address);
6051 %}
6052 ins_pipe(ialu_reg_mem);
6053 %}
6054
6055 // Load Integer (32 bit signed) to Short (16 bit signed)
6056 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6057 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6058
6059 ins_cost(125);
6060 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6061 ins_encode %{
6062 __ movswl($dst$$Register, $mem$$Address);
6063 %}
6064 ins_pipe(ialu_reg_mem);
6065 %}
6066
6067 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6068 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6069 match(Set dst (AndI (LoadI mem) mask));
6070
6071 ins_cost(125);
6072 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6073 ins_encode %{
6074 __ movzwl($dst$$Register, $mem$$Address);
6075 %}
6076 ins_pipe(ialu_reg_mem);
6077 %}
6078
6079 // Load Integer into Long Register
6080 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6081 match(Set dst (ConvI2L (LoadI mem)));
6082 effect(KILL cr);
6083
6084 ins_cost(375);
6085 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6086 "MOV $dst.hi,$dst.lo\n\t"
6087 "SAR $dst.hi,31" %}
6088
6089 ins_encode %{
6090 __ movl($dst$$Register, $mem$$Address);
6091 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6092 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6093 %}
6094
6095 ins_pipe(ialu_reg_mem);
6096 %}
6097
6098 // Load Integer with mask 0xFF into Long Register
6099 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6100 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6101 effect(KILL cr);
6102
6103 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6104 "XOR $dst.hi,$dst.hi" %}
6105 ins_encode %{
6106 Register Rdst = $dst$$Register;
6107 __ movzbl(Rdst, $mem$$Address);
6108 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6109 %}
6110 ins_pipe(ialu_reg_mem);
6111 %}
6112
6113 // Load Integer with mask 0xFFFF into Long Register
6114 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6115 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6116 effect(KILL cr);
6117
6118 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6119 "XOR $dst.hi,$dst.hi" %}
6120 ins_encode %{
6121 Register Rdst = $dst$$Register;
6122 __ movzwl(Rdst, $mem$$Address);
6123 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6124 %}
6125 ins_pipe(ialu_reg_mem);
6126 %}
6127
6128 // Load Integer with 31-bit mask into Long Register
6129 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6130 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6131 effect(KILL cr);
6132
6133 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6134 "XOR $dst.hi,$dst.hi\n\t"
6135 "AND $dst.lo,$mask" %}
6136 ins_encode %{
6137 Register Rdst = $dst$$Register;
6138 __ movl(Rdst, $mem$$Address);
6139 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6140 __ andl(Rdst, $mask$$constant);
6141 %}
6142 ins_pipe(ialu_reg_mem);
6143 %}
6144
6145 // Load Unsigned Integer into Long Register
6146 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6147 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6148 effect(KILL cr);
6149
6150 ins_cost(250);
6151 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6152 "XOR $dst.hi,$dst.hi" %}
6153
6154 ins_encode %{
6155 __ movl($dst$$Register, $mem$$Address);
6156 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6157 %}
6158
6159 ins_pipe(ialu_reg_mem);
6160 %}
6161
6162 // Load Long. Cannot clobber address while loading, so restrict address
6163 // register to ESI
6164 instruct loadL(eRegL dst, load_long_memory mem) %{
6165 predicate(!((LoadLNode*)n)->require_atomic_access());
6166 match(Set dst (LoadL mem));
6167
6168 ins_cost(250);
6169 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6170 "MOV $dst.hi,$mem+4" %}
6171
6172 ins_encode %{
6173 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6174 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6175 __ movl($dst$$Register, Amemlo);
6176 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6177 %}
6178
6179 ins_pipe(ialu_reg_long_mem);
6180 %}
6181
6182 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6183 // then store it down to the stack and reload on the int
6184 // side.
6185 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6186 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6187 match(Set dst (LoadL mem));
6188
6189 ins_cost(200);
6190 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6191 "FISTp $dst" %}
6192 ins_encode(enc_loadL_volatile(mem,dst));
6193 ins_pipe( fpu_reg_mem );
6194 %}
6195
6196 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6197 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6198 match(Set dst (LoadL mem));
6199 effect(TEMP tmp);
6200 ins_cost(180);
6201 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6202 "MOVSD $dst,$tmp" %}
6203 ins_encode %{
6204 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6205 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6206 %}
6207 ins_pipe( pipe_slow );
6208 %}
6209
6210 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6211 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6212 match(Set dst (LoadL mem));
6213 effect(TEMP tmp);
6214 ins_cost(160);
6215 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6216 "MOVD $dst.lo,$tmp\n\t"
6217 "PSRLQ $tmp,32\n\t"
6218 "MOVD $dst.hi,$tmp" %}
6219 ins_encode %{
6220 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6221 __ movdl($dst$$Register, $tmp$$XMMRegister);
6222 __ psrlq($tmp$$XMMRegister, 32);
6223 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6224 %}
6225 ins_pipe( pipe_slow );
6226 %}
6227
6228 // Load Range
6229 instruct loadRange(rRegI dst, memory mem) %{
6230 match(Set dst (LoadRange mem));
6231
6232 ins_cost(125);
6233 format %{ "MOV $dst,$mem" %}
6234 opcode(0x8B);
6235 ins_encode( OpcP, RegMem(dst,mem));
6236 ins_pipe( ialu_reg_mem );
6237 %}
6238
6239
6240 // Load Pointer
6241 instruct loadP(eRegP dst, memory mem) %{
6242 match(Set dst (LoadP mem));
6243
6244 ins_cost(125);
6245 format %{ "MOV $dst,$mem" %}
6246 opcode(0x8B);
6247 ins_encode( OpcP, RegMem(dst,mem));
6248 ins_pipe( ialu_reg_mem );
6249 %}
6250
6251 // Load Klass Pointer
6252 instruct loadKlass(eRegP dst, memory mem) %{
6253 match(Set dst (LoadKlass mem));
6254
6255 ins_cost(125);
6256 format %{ "MOV $dst,$mem" %}
6257 opcode(0x8B);
6258 ins_encode( OpcP, RegMem(dst,mem));
6259 ins_pipe( ialu_reg_mem );
6260 %}
6261
6262 // Load Double
6263 instruct loadDPR(regDPR dst, memory mem) %{
6264 predicate(UseSSE<=1);
6265 match(Set dst (LoadD mem));
6266
6267 ins_cost(150);
6268 format %{ "FLD_D ST,$mem\n\t"
6269 "FSTP $dst" %}
6270 opcode(0xDD); /* DD /0 */
6271 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6272 Pop_Reg_DPR(dst) );
6273 ins_pipe( fpu_reg_mem );
6274 %}
6275
6276 // Load Double to XMM
6277 instruct loadD(regD dst, memory mem) %{
6278 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6279 match(Set dst (LoadD mem));
6280 ins_cost(145);
6281 format %{ "MOVSD $dst,$mem" %}
6282 ins_encode %{
6283 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6284 %}
6285 ins_pipe( pipe_slow );
6286 %}
6287
6288 instruct loadD_partial(regD dst, memory mem) %{
6289 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6290 match(Set dst (LoadD mem));
6291 ins_cost(145);
6292 format %{ "MOVLPD $dst,$mem" %}
6293 ins_encode %{
6294 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6295 %}
6296 ins_pipe( pipe_slow );
6297 %}
6298
6299 // Load to XMM register (single-precision floating point)
6300 // MOVSS instruction
6301 instruct loadF(regF dst, memory mem) %{
6302 predicate(UseSSE>=1);
6303 match(Set dst (LoadF mem));
6304 ins_cost(145);
6305 format %{ "MOVSS $dst,$mem" %}
6306 ins_encode %{
6307 __ movflt ($dst$$XMMRegister, $mem$$Address);
6308 %}
6309 ins_pipe( pipe_slow );
6310 %}
6311
6312 // Load Float
6313 instruct loadFPR(regFPR dst, memory mem) %{
6314 predicate(UseSSE==0);
6315 match(Set dst (LoadF mem));
6316
6317 ins_cost(150);
6318 format %{ "FLD_S ST,$mem\n\t"
6319 "FSTP $dst" %}
6320 opcode(0xD9); /* D9 /0 */
6321 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6322 Pop_Reg_FPR(dst) );
6323 ins_pipe( fpu_reg_mem );
6324 %}
6325
6326 // Load Effective Address
6327 instruct leaP8(eRegP dst, indOffset8 mem) %{
6328 match(Set dst mem);
6329
6330 ins_cost(110);
6331 format %{ "LEA $dst,$mem" %}
6332 opcode(0x8D);
6333 ins_encode( OpcP, RegMem(dst,mem));
6334 ins_pipe( ialu_reg_reg_fat );
6335 %}
6336
6337 instruct leaP32(eRegP dst, indOffset32 mem) %{
6338 match(Set dst mem);
6339
6340 ins_cost(110);
6341 format %{ "LEA $dst,$mem" %}
6342 opcode(0x8D);
6343 ins_encode( OpcP, RegMem(dst,mem));
6344 ins_pipe( ialu_reg_reg_fat );
6345 %}
6346
6347 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6348 match(Set dst mem);
6349
6350 ins_cost(110);
6351 format %{ "LEA $dst,$mem" %}
6352 opcode(0x8D);
6353 ins_encode( OpcP, RegMem(dst,mem));
6354 ins_pipe( ialu_reg_reg_fat );
6355 %}
6356
6357 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6358 match(Set dst mem);
6359
6360 ins_cost(110);
6361 format %{ "LEA $dst,$mem" %}
6362 opcode(0x8D);
6363 ins_encode( OpcP, RegMem(dst,mem));
6364 ins_pipe( ialu_reg_reg_fat );
6365 %}
6366
6367 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6368 match(Set dst mem);
6369
6370 ins_cost(110);
6371 format %{ "LEA $dst,$mem" %}
6372 opcode(0x8D);
6373 ins_encode( OpcP, RegMem(dst,mem));
6374 ins_pipe( ialu_reg_reg_fat );
6375 %}
6376
6377 // Load Constant
6378 instruct loadConI(rRegI dst, immI src) %{
6379 match(Set dst src);
6380
6381 format %{ "MOV $dst,$src" %}
6382 ins_encode( LdImmI(dst, src) );
6383 ins_pipe( ialu_reg_fat );
6384 %}
6385
6386 // Load Constant zero
6387 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6388 match(Set dst src);
6389 effect(KILL cr);
6390
6391 ins_cost(50);
6392 format %{ "XOR $dst,$dst" %}
6393 opcode(0x33); /* + rd */
6394 ins_encode( OpcP, RegReg( dst, dst ) );
6395 ins_pipe( ialu_reg );
6396 %}
6397
6398 instruct loadConP(eRegP dst, immP src) %{
6399 match(Set dst src);
6400
6401 format %{ "MOV $dst,$src" %}
6402 opcode(0xB8); /* + rd */
6403 ins_encode( LdImmP(dst, src) );
6404 ins_pipe( ialu_reg_fat );
6405 %}
6406
6407 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6408 match(Set dst src);
6409 effect(KILL cr);
6410 ins_cost(200);
6411 format %{ "MOV $dst.lo,$src.lo\n\t"
6412 "MOV $dst.hi,$src.hi" %}
6413 opcode(0xB8);
6414 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6415 ins_pipe( ialu_reg_long_fat );
6416 %}
6417
6418 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6419 match(Set dst src);
6420 effect(KILL cr);
6421 ins_cost(150);
6422 format %{ "XOR $dst.lo,$dst.lo\n\t"
6423 "XOR $dst.hi,$dst.hi" %}
6424 opcode(0x33,0x33);
6425 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6426 ins_pipe( ialu_reg_long );
6427 %}
6428
6429 // The instruction usage is guarded by predicate in operand immFPR().
6430 instruct loadConFPR(regFPR dst, immFPR con) %{
6431 match(Set dst con);
6432 ins_cost(125);
6433 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6434 "FSTP $dst" %}
6435 ins_encode %{
6436 __ fld_s($constantaddress($con));
6437 __ fstp_d($dst$$reg);
6438 %}
6439 ins_pipe(fpu_reg_con);
6440 %}
6441
6442 // The instruction usage is guarded by predicate in operand immFPR0().
6443 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6444 match(Set dst con);
6445 ins_cost(125);
6446 format %{ "FLDZ ST\n\t"
6447 "FSTP $dst" %}
6448 ins_encode %{
6449 __ fldz();
6450 __ fstp_d($dst$$reg);
6451 %}
6452 ins_pipe(fpu_reg_con);
6453 %}
6454
6455 // The instruction usage is guarded by predicate in operand immFPR1().
6456 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6457 match(Set dst con);
6458 ins_cost(125);
6459 format %{ "FLD1 ST\n\t"
6460 "FSTP $dst" %}
6461 ins_encode %{
6462 __ fld1();
6463 __ fstp_d($dst$$reg);
6464 %}
6465 ins_pipe(fpu_reg_con);
6466 %}
6467
6468 // The instruction usage is guarded by predicate in operand immF().
6469 instruct loadConF(regF dst, immF con) %{
6470 match(Set dst con);
6471 ins_cost(125);
6472 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6473 ins_encode %{
6474 __ movflt($dst$$XMMRegister, $constantaddress($con));
6475 %}
6476 ins_pipe(pipe_slow);
6477 %}
6478
6479 // The instruction usage is guarded by predicate in operand immF0().
6480 instruct loadConF0(regF dst, immF0 src) %{
6481 match(Set dst src);
6482 ins_cost(100);
6483 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6484 ins_encode %{
6485 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6486 %}
6487 ins_pipe(pipe_slow);
6488 %}
6489
6490 // The instruction usage is guarded by predicate in operand immDPR().
6491 instruct loadConDPR(regDPR dst, immDPR con) %{
6492 match(Set dst con);
6493 ins_cost(125);
6494
6495 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6496 "FSTP $dst" %}
6497 ins_encode %{
6498 __ fld_d($constantaddress($con));
6499 __ fstp_d($dst$$reg);
6500 %}
6501 ins_pipe(fpu_reg_con);
6502 %}
6503
6504 // The instruction usage is guarded by predicate in operand immDPR0().
6505 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6506 match(Set dst con);
6507 ins_cost(125);
6508
6509 format %{ "FLDZ ST\n\t"
6510 "FSTP $dst" %}
6511 ins_encode %{
6512 __ fldz();
6513 __ fstp_d($dst$$reg);
6514 %}
6515 ins_pipe(fpu_reg_con);
6516 %}
6517
6518 // The instruction usage is guarded by predicate in operand immDPR1().
6519 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6520 match(Set dst con);
6521 ins_cost(125);
6522
6523 format %{ "FLD1 ST\n\t"
6524 "FSTP $dst" %}
6525 ins_encode %{
6526 __ fld1();
6527 __ fstp_d($dst$$reg);
6528 %}
6529 ins_pipe(fpu_reg_con);
6530 %}
6531
6532 // The instruction usage is guarded by predicate in operand immD().
6533 instruct loadConD(regD dst, immD con) %{
6534 match(Set dst con);
6535 ins_cost(125);
6536 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6537 ins_encode %{
6538 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6539 %}
6540 ins_pipe(pipe_slow);
6541 %}
6542
6543 // The instruction usage is guarded by predicate in operand immD0().
6544 instruct loadConD0(regD dst, immD0 src) %{
6545 match(Set dst src);
6546 ins_cost(100);
6547 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6548 ins_encode %{
6549 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6550 %}
6551 ins_pipe( pipe_slow );
6552 %}
6553
6554 // Load Stack Slot
6555 instruct loadSSI(rRegI dst, stackSlotI src) %{
6556 match(Set dst src);
6557 ins_cost(125);
6558
6559 format %{ "MOV $dst,$src" %}
6560 opcode(0x8B);
6561 ins_encode( OpcP, RegMem(dst,src));
6562 ins_pipe( ialu_reg_mem );
6563 %}
6564
6565 instruct loadSSL(eRegL dst, stackSlotL src) %{
6566 match(Set dst src);
6567
6568 ins_cost(200);
6569 format %{ "MOV $dst,$src.lo\n\t"
6570 "MOV $dst+4,$src.hi" %}
6571 opcode(0x8B, 0x8B);
6572 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6573 ins_pipe( ialu_mem_long_reg );
6574 %}
6575
6576 // Load Stack Slot
6577 instruct loadSSP(eRegP dst, stackSlotP src) %{
6578 match(Set dst src);
6579 ins_cost(125);
6580
6581 format %{ "MOV $dst,$src" %}
6582 opcode(0x8B);
6583 ins_encode( OpcP, RegMem(dst,src));
6584 ins_pipe( ialu_reg_mem );
6585 %}
6586
6587 // Load Stack Slot
6588 instruct loadSSF(regFPR dst, stackSlotF src) %{
6589 match(Set dst src);
6590 ins_cost(125);
6591
6592 format %{ "FLD_S $src\n\t"
6593 "FSTP $dst" %}
6594 opcode(0xD9); /* D9 /0, FLD m32real */
6595 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6596 Pop_Reg_FPR(dst) );
6597 ins_pipe( fpu_reg_mem );
6598 %}
6599
6600 // Load Stack Slot
6601 instruct loadSSD(regDPR dst, stackSlotD src) %{
6602 match(Set dst src);
6603 ins_cost(125);
6604
6605 format %{ "FLD_D $src\n\t"
6606 "FSTP $dst" %}
6607 opcode(0xDD); /* DD /0, FLD m64real */
6608 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6609 Pop_Reg_DPR(dst) );
6610 ins_pipe( fpu_reg_mem );
6611 %}
6612
6613 // Prefetch instructions.
6614 // Must be safe to execute with invalid address (cannot fault).
6615
6616 instruct prefetchr0( memory mem ) %{
6617 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6618 match(PrefetchRead mem);
6619 ins_cost(0);
6620 size(0);
6621 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6622 ins_encode();
6623 ins_pipe(empty);
6624 %}
6625
6626 instruct prefetchr( memory mem ) %{
6627 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6628 match(PrefetchRead mem);
6629 ins_cost(100);
6630
6631 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6632 ins_encode %{
6633 __ prefetchr($mem$$Address);
6634 %}
6635 ins_pipe(ialu_mem);
6636 %}
6637
6638 instruct prefetchrNTA( memory mem ) %{
6639 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6640 match(PrefetchRead mem);
6641 ins_cost(100);
6642
6643 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6644 ins_encode %{
6645 __ prefetchnta($mem$$Address);
6646 %}
6647 ins_pipe(ialu_mem);
6648 %}
6649
6650 instruct prefetchrT0( memory mem ) %{
6651 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6652 match(PrefetchRead mem);
6653 ins_cost(100);
6654
6655 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6656 ins_encode %{
6657 __ prefetcht0($mem$$Address);
6658 %}
6659 ins_pipe(ialu_mem);
6660 %}
6661
6662 instruct prefetchrT2( memory mem ) %{
6663 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6664 match(PrefetchRead mem);
6665 ins_cost(100);
6666
6667 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6668 ins_encode %{
6669 __ prefetcht2($mem$$Address);
6670 %}
6671 ins_pipe(ialu_mem);
6672 %}
6673
6674 instruct prefetchw0( memory mem ) %{
6675 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6676 match(PrefetchWrite mem);
6677 ins_cost(0);
6678 size(0);
6679 format %{ "Prefetch (non-SSE is empty encoding)" %}
6680 ins_encode();
6681 ins_pipe(empty);
6682 %}
6683
6684 instruct prefetchw( memory mem ) %{
6685 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6686 match( PrefetchWrite mem );
6687 ins_cost(100);
6688
6689 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6690 ins_encode %{
6691 __ prefetchw($mem$$Address);
6692 %}
6693 ins_pipe(ialu_mem);
6694 %}
6695
6696 instruct prefetchwNTA( memory mem ) %{
6697 predicate(UseSSE>=1);
6698 match(PrefetchWrite mem);
6699 ins_cost(100);
6700
6701 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6702 ins_encode %{
6703 __ prefetchnta($mem$$Address);
6704 %}
6705 ins_pipe(ialu_mem);
6706 %}
6707
6708 // Prefetch instructions for allocation.
6709
6710 instruct prefetchAlloc0( memory mem ) %{
6711 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6712 match(PrefetchAllocation mem);
6713 ins_cost(0);
6714 size(0);
6715 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6716 ins_encode();
6717 ins_pipe(empty);
6718 %}
6719
6720 instruct prefetchAlloc( memory mem ) %{
6721 predicate(AllocatePrefetchInstr==3);
6722 match( PrefetchAllocation mem );
6723 ins_cost(100);
6724
6725 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6726 ins_encode %{
6727 __ prefetchw($mem$$Address);
6728 %}
6729 ins_pipe(ialu_mem);
6730 %}
6731
6732 instruct prefetchAllocNTA( memory mem ) %{
6733 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6734 match(PrefetchAllocation mem);
6735 ins_cost(100);
6736
6737 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6738 ins_encode %{
6739 __ prefetchnta($mem$$Address);
6740 %}
6741 ins_pipe(ialu_mem);
6742 %}
6743
6744 instruct prefetchAllocT0( memory mem ) %{
6745 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6746 match(PrefetchAllocation mem);
6747 ins_cost(100);
6748
6749 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6750 ins_encode %{
6751 __ prefetcht0($mem$$Address);
6752 %}
6753 ins_pipe(ialu_mem);
6754 %}
6755
6756 instruct prefetchAllocT2( memory mem ) %{
6757 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6758 match(PrefetchAllocation mem);
6759 ins_cost(100);
6760
6761 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6762 ins_encode %{
6763 __ prefetcht2($mem$$Address);
6764 %}
6765 ins_pipe(ialu_mem);
6766 %}
6767
6768 //----------Store Instructions-------------------------------------------------
6769
6770 // Store Byte
6771 instruct storeB(memory mem, xRegI src) %{
6772 match(Set mem (StoreB mem src));
6773
6774 ins_cost(125);
6775 format %{ "MOV8 $mem,$src" %}
6776 opcode(0x88);
6777 ins_encode( OpcP, RegMem( src, mem ) );
6778 ins_pipe( ialu_mem_reg );
6779 %}
6780
6781 // Store Char/Short
6782 instruct storeC(memory mem, rRegI src) %{
6783 match(Set mem (StoreC mem src));
6784
6785 ins_cost(125);
6786 format %{ "MOV16 $mem,$src" %}
6787 opcode(0x89, 0x66);
6788 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6789 ins_pipe( ialu_mem_reg );
6790 %}
6791
6792 // Store Integer
6793 instruct storeI(memory mem, rRegI src) %{
6794 match(Set mem (StoreI mem src));
6795
6796 ins_cost(125);
6797 format %{ "MOV $mem,$src" %}
6798 opcode(0x89);
6799 ins_encode( OpcP, RegMem( src, mem ) );
6800 ins_pipe( ialu_mem_reg );
6801 %}
6802
6803 // Store Long
6804 instruct storeL(long_memory mem, eRegL src) %{
6805 predicate(!((StoreLNode*)n)->require_atomic_access());
6806 match(Set mem (StoreL mem src));
6807
6808 ins_cost(200);
6809 format %{ "MOV $mem,$src.lo\n\t"
6810 "MOV $mem+4,$src.hi" %}
6811 opcode(0x89, 0x89);
6812 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6813 ins_pipe( ialu_mem_long_reg );
6814 %}
6815
6816 // Store Long to Integer
6817 instruct storeL2I(memory mem, eRegL src) %{
6818 match(Set mem (StoreI mem (ConvL2I src)));
6819
6820 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6821 ins_encode %{
6822 __ movl($mem$$Address, $src$$Register);
6823 %}
6824 ins_pipe(ialu_mem_reg);
6825 %}
6826
6827 // Volatile Store Long. Must be atomic, so move it into
6828 // the FP TOS and then do a 64-bit FIST. Has to probe the
6829 // target address before the store (for null-ptr checks)
6830 // so the memory operand is used twice in the encoding.
6831 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6832 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6833 match(Set mem (StoreL mem src));
6834 effect( KILL cr );
6835 ins_cost(400);
6836 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6837 "FILD $src\n\t"
6838 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6839 opcode(0x3B);
6840 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6841 ins_pipe( fpu_reg_mem );
6842 %}
6843
6844 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6845 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6846 match(Set mem (StoreL mem src));
6847 effect( TEMP tmp, KILL cr );
6848 ins_cost(380);
6849 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6850 "MOVSD $tmp,$src\n\t"
6851 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6852 ins_encode %{
6853 __ cmpl(rax, $mem$$Address);
6854 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6855 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6856 %}
6857 ins_pipe( pipe_slow );
6858 %}
6859
6860 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6861 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6862 match(Set mem (StoreL mem src));
6863 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6864 ins_cost(360);
6865 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6866 "MOVD $tmp,$src.lo\n\t"
6867 "MOVD $tmp2,$src.hi\n\t"
6868 "PUNPCKLDQ $tmp,$tmp2\n\t"
6869 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6870 ins_encode %{
6871 __ cmpl(rax, $mem$$Address);
6872 __ movdl($tmp$$XMMRegister, $src$$Register);
6873 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6874 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6875 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6876 %}
6877 ins_pipe( pipe_slow );
6878 %}
6879
6880 // Store Pointer; for storing unknown oops and raw pointers
6881 instruct storeP(memory mem, anyRegP src) %{
6882 match(Set mem (StoreP mem src));
6883
6884 ins_cost(125);
6885 format %{ "MOV $mem,$src" %}
6886 opcode(0x89);
6887 ins_encode( OpcP, RegMem( src, mem ) );
6888 ins_pipe( ialu_mem_reg );
6889 %}
6890
6891 // Store Integer Immediate
6892 instruct storeImmI(memory mem, immI src) %{
6893 match(Set mem (StoreI mem src));
6894
6895 ins_cost(150);
6896 format %{ "MOV $mem,$src" %}
6897 opcode(0xC7); /* C7 /0 */
6898 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6899 ins_pipe( ialu_mem_imm );
6900 %}
6901
6902 // Store Short/Char Immediate
6903 instruct storeImmI16(memory mem, immI16 src) %{
6904 predicate(UseStoreImmI16);
6905 match(Set mem (StoreC mem src));
6906
6907 ins_cost(150);
6908 format %{ "MOV16 $mem,$src" %}
6909 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6910 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6911 ins_pipe( ialu_mem_imm );
6912 %}
6913
6914 // Store Pointer Immediate; null pointers or constant oops that do not
6915 // need card-mark barriers.
6916 instruct storeImmP(memory mem, immP src) %{
6917 match(Set mem (StoreP mem src));
6918
6919 ins_cost(150);
6920 format %{ "MOV $mem,$src" %}
6921 opcode(0xC7); /* C7 /0 */
6922 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6923 ins_pipe( ialu_mem_imm );
6924 %}
6925
6926 // Store Byte Immediate
6927 instruct storeImmB(memory mem, immI8 src) %{
6928 match(Set mem (StoreB mem src));
6929
6930 ins_cost(150);
6931 format %{ "MOV8 $mem,$src" %}
6932 opcode(0xC6); /* C6 /0 */
6933 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6934 ins_pipe( ialu_mem_imm );
6935 %}
6936
6937 // Store CMS card-mark Immediate
6938 instruct storeImmCM(memory mem, immI8 src) %{
6939 match(Set mem (StoreCM mem src));
6940
6941 ins_cost(150);
6942 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6943 opcode(0xC6); /* C6 /0 */
6944 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6945 ins_pipe( ialu_mem_imm );
6946 %}
6947
6948 // Store Double
6949 instruct storeDPR( memory mem, regDPR1 src) %{
6950 predicate(UseSSE<=1);
6951 match(Set mem (StoreD mem src));
6952
6953 ins_cost(100);
6954 format %{ "FST_D $mem,$src" %}
6955 opcode(0xDD); /* DD /2 */
6956 ins_encode( enc_FPR_store(mem,src) );
6957 ins_pipe( fpu_mem_reg );
6958 %}
6959
6960 // Store double does rounding on x86
6961 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6962 predicate(UseSSE<=1);
6963 match(Set mem (StoreD mem (RoundDouble src)));
6964
6965 ins_cost(100);
6966 format %{ "FST_D $mem,$src\t# round" %}
6967 opcode(0xDD); /* DD /2 */
6968 ins_encode( enc_FPR_store(mem,src) );
6969 ins_pipe( fpu_mem_reg );
6970 %}
6971
6972 // Store XMM register to memory (double-precision floating points)
6973 // MOVSD instruction
6974 instruct storeD(memory mem, regD src) %{
6975 predicate(UseSSE>=2);
6976 match(Set mem (StoreD mem src));
6977 ins_cost(95);
6978 format %{ "MOVSD $mem,$src" %}
6979 ins_encode %{
6980 __ movdbl($mem$$Address, $src$$XMMRegister);
6981 %}
6982 ins_pipe( pipe_slow );
6983 %}
6984
6985 // Store XMM register to memory (single-precision floating point)
6986 // MOVSS instruction
6987 instruct storeF(memory mem, regF src) %{
6988 predicate(UseSSE>=1);
6989 match(Set mem (StoreF mem src));
6990 ins_cost(95);
6991 format %{ "MOVSS $mem,$src" %}
6992 ins_encode %{
6993 __ movflt($mem$$Address, $src$$XMMRegister);
6994 %}
6995 ins_pipe( pipe_slow );
6996 %}
6997
6998 // Store Float
6999 instruct storeFPR( memory mem, regFPR1 src) %{
7000 predicate(UseSSE==0);
7001 match(Set mem (StoreF mem src));
7002
7003 ins_cost(100);
7004 format %{ "FST_S $mem,$src" %}
7005 opcode(0xD9); /* D9 /2 */
7006 ins_encode( enc_FPR_store(mem,src) );
7007 ins_pipe( fpu_mem_reg );
7008 %}
7009
7010 // Store Float does rounding on x86
7011 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7012 predicate(UseSSE==0);
7013 match(Set mem (StoreF mem (RoundFloat src)));
7014
7015 ins_cost(100);
7016 format %{ "FST_S $mem,$src\t# round" %}
7017 opcode(0xD9); /* D9 /2 */
7018 ins_encode( enc_FPR_store(mem,src) );
7019 ins_pipe( fpu_mem_reg );
7020 %}
7021
7022 // Store Float does rounding on x86
7023 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7024 predicate(UseSSE<=1);
7025 match(Set mem (StoreF mem (ConvD2F src)));
7026
7027 ins_cost(100);
7028 format %{ "FST_S $mem,$src\t# D-round" %}
7029 opcode(0xD9); /* D9 /2 */
7030 ins_encode( enc_FPR_store(mem,src) );
7031 ins_pipe( fpu_mem_reg );
7032 %}
7033
7034 // Store immediate Float value (it is faster than store from FPU register)
7035 // The instruction usage is guarded by predicate in operand immFPR().
7036 instruct storeFPR_imm( memory mem, immFPR src) %{
7037 match(Set mem (StoreF mem src));
7038
7039 ins_cost(50);
7040 format %{ "MOV $mem,$src\t# store float" %}
7041 opcode(0xC7); /* C7 /0 */
7042 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7043 ins_pipe( ialu_mem_imm );
7044 %}
7045
7046 // Store immediate Float value (it is faster than store from XMM register)
7047 // The instruction usage is guarded by predicate in operand immF().
7048 instruct storeF_imm( memory mem, immF src) %{
7049 match(Set mem (StoreF mem src));
7050
7051 ins_cost(50);
7052 format %{ "MOV $mem,$src\t# store float" %}
7053 opcode(0xC7); /* C7 /0 */
7054 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7055 ins_pipe( ialu_mem_imm );
7056 %}
7057
7058 // Store Integer to stack slot
7059 instruct storeSSI(stackSlotI dst, rRegI src) %{
7060 match(Set dst src);
7061
7062 ins_cost(100);
7063 format %{ "MOV $dst,$src" %}
7064 opcode(0x89);
7065 ins_encode( OpcPRegSS( dst, src ) );
7066 ins_pipe( ialu_mem_reg );
7067 %}
7068
7069 // Store Integer to stack slot
7070 instruct storeSSP(stackSlotP dst, eRegP src) %{
7071 match(Set dst src);
7072
7073 ins_cost(100);
7074 format %{ "MOV $dst,$src" %}
7075 opcode(0x89);
7076 ins_encode( OpcPRegSS( dst, src ) );
7077 ins_pipe( ialu_mem_reg );
7078 %}
7079
7080 // Store Long to stack slot
7081 instruct storeSSL(stackSlotL dst, eRegL src) %{
7082 match(Set dst src);
7083
7084 ins_cost(200);
7085 format %{ "MOV $dst,$src.lo\n\t"
7086 "MOV $dst+4,$src.hi" %}
7087 opcode(0x89, 0x89);
7088 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7089 ins_pipe( ialu_mem_long_reg );
7090 %}
7091
7092 //----------MemBar Instructions-----------------------------------------------
7093 // Memory barrier flavors
7094
7095 instruct membar_acquire() %{
7096 match(MemBarAcquire);
7097 match(LoadFence);
7098 ins_cost(400);
7099
7100 size(0);
7101 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7102 ins_encode();
7103 ins_pipe(empty);
7104 %}
7105
7106 instruct membar_acquire_lock() %{
7107 match(MemBarAcquireLock);
7108 ins_cost(0);
7109
7110 size(0);
7111 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7112 ins_encode( );
7113 ins_pipe(empty);
7114 %}
7115
7116 instruct membar_release() %{
7117 match(MemBarRelease);
7118 match(StoreFence);
7119 ins_cost(400);
7120
7121 size(0);
7122 format %{ "MEMBAR-release ! (empty encoding)" %}
7123 ins_encode( );
7124 ins_pipe(empty);
7125 %}
7126
7127 instruct membar_release_lock() %{
7128 match(MemBarReleaseLock);
7129 ins_cost(0);
7130
7131 size(0);
7132 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7133 ins_encode( );
7134 ins_pipe(empty);
7135 %}
7136
7137 instruct membar_volatile(eFlagsReg cr) %{
7138 match(MemBarVolatile);
7139 effect(KILL cr);
7140 ins_cost(400);
7141
7142 format %{
7143 $$template
7144 if (os::is_MP()) {
7145 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7146 } else {
7147 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7148 }
7149 %}
7150 ins_encode %{
7151 __ membar(Assembler::StoreLoad);
7152 %}
7153 ins_pipe(pipe_slow);
7154 %}
7155
7156 instruct unnecessary_membar_volatile() %{
7157 match(MemBarVolatile);
7158 predicate(Matcher::post_store_load_barrier(n));
7159 ins_cost(0);
7160
7161 size(0);
7162 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7163 ins_encode( );
7164 ins_pipe(empty);
7165 %}
7166
7167 instruct membar_storestore() %{
7168 match(MemBarStoreStore);
7169 ins_cost(0);
7170
7171 size(0);
7172 format %{ "MEMBAR-storestore (empty encoding)" %}
7173 ins_encode( );
7174 ins_pipe(empty);
7175 %}
7176
7177 //----------Move Instructions--------------------------------------------------
7178 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7179 match(Set dst (CastX2P src));
7180 format %{ "# X2P $dst, $src" %}
7181 ins_encode( /*empty encoding*/ );
7182 ins_cost(0);
7183 ins_pipe(empty);
7184 %}
7185
7186 instruct castP2X(rRegI dst, eRegP src ) %{
7187 match(Set dst (CastP2X src));
7188 ins_cost(50);
7189 format %{ "MOV $dst, $src\t# CastP2X" %}
7190 ins_encode( enc_Copy( dst, src) );
7191 ins_pipe( ialu_reg_reg );
7192 %}
7193
7194 //----------Conditional Move---------------------------------------------------
7195 // Conditional move
7196 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7197 predicate(!VM_Version::supports_cmov() );
7198 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7199 ins_cost(200);
7200 format %{ "J$cop,us skip\t# signed cmove\n\t"
7201 "MOV $dst,$src\n"
7202 "skip:" %}
7203 ins_encode %{
7204 Label Lskip;
7205 // Invert sense of branch from sense of CMOV
7206 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7207 __ movl($dst$$Register, $src$$Register);
7208 __ bind(Lskip);
7209 %}
7210 ins_pipe( pipe_cmov_reg );
7211 %}
7212
7213 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7214 predicate(!VM_Version::supports_cmov() );
7215 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7216 ins_cost(200);
7217 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7218 "MOV $dst,$src\n"
7219 "skip:" %}
7220 ins_encode %{
7221 Label Lskip;
7222 // Invert sense of branch from sense of CMOV
7223 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7224 __ movl($dst$$Register, $src$$Register);
7225 __ bind(Lskip);
7226 %}
7227 ins_pipe( pipe_cmov_reg );
7228 %}
7229
7230 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7231 predicate(VM_Version::supports_cmov() );
7232 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7233 ins_cost(200);
7234 format %{ "CMOV$cop $dst,$src" %}
7235 opcode(0x0F,0x40);
7236 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7237 ins_pipe( pipe_cmov_reg );
7238 %}
7239
7240 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7241 predicate(VM_Version::supports_cmov() );
7242 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7243 ins_cost(200);
7244 format %{ "CMOV$cop $dst,$src" %}
7245 opcode(0x0F,0x40);
7246 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7247 ins_pipe( pipe_cmov_reg );
7248 %}
7249
7250 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7251 predicate(VM_Version::supports_cmov() );
7252 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7253 ins_cost(200);
7254 expand %{
7255 cmovI_regU(cop, cr, dst, src);
7256 %}
7257 %}
7258
7259 // Conditional move
7260 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7261 predicate(VM_Version::supports_cmov() );
7262 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7263 ins_cost(250);
7264 format %{ "CMOV$cop $dst,$src" %}
7265 opcode(0x0F,0x40);
7266 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7267 ins_pipe( pipe_cmov_mem );
7268 %}
7269
7270 // Conditional move
7271 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7272 predicate(VM_Version::supports_cmov() );
7273 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7274 ins_cost(250);
7275 format %{ "CMOV$cop $dst,$src" %}
7276 opcode(0x0F,0x40);
7277 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7278 ins_pipe( pipe_cmov_mem );
7279 %}
7280
7281 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7282 predicate(VM_Version::supports_cmov() );
7283 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7284 ins_cost(250);
7285 expand %{
7286 cmovI_memU(cop, cr, dst, src);
7287 %}
7288 %}
7289
7290 // Conditional move
7291 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7292 predicate(VM_Version::supports_cmov() );
7293 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7294 ins_cost(200);
7295 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7296 opcode(0x0F,0x40);
7297 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7298 ins_pipe( pipe_cmov_reg );
7299 %}
7300
7301 // Conditional move (non-P6 version)
7302 // Note: a CMoveP is generated for stubs and native wrappers
7303 // regardless of whether we are on a P6, so we
7304 // emulate a cmov here
7305 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7306 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7307 ins_cost(300);
7308 format %{ "Jn$cop skip\n\t"
7309 "MOV $dst,$src\t# pointer\n"
7310 "skip:" %}
7311 opcode(0x8b);
7312 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7313 ins_pipe( pipe_cmov_reg );
7314 %}
7315
7316 // Conditional move
7317 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7318 predicate(VM_Version::supports_cmov() );
7319 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7320 ins_cost(200);
7321 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7322 opcode(0x0F,0x40);
7323 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7324 ins_pipe( pipe_cmov_reg );
7325 %}
7326
7327 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7328 predicate(VM_Version::supports_cmov() );
7329 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7330 ins_cost(200);
7331 expand %{
7332 cmovP_regU(cop, cr, dst, src);
7333 %}
7334 %}
7335
7336 // DISABLED: Requires the ADLC to emit a bottom_type call that
7337 // correctly meets the two pointer arguments; one is an incoming
7338 // register but the other is a memory operand. ALSO appears to
7339 // be buggy with implicit null checks.
7340 //
7341 //// Conditional move
7342 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7343 // predicate(VM_Version::supports_cmov() );
7344 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7345 // ins_cost(250);
7346 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7347 // opcode(0x0F,0x40);
7348 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7349 // ins_pipe( pipe_cmov_mem );
7350 //%}
7351 //
7352 //// Conditional move
7353 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7354 // predicate(VM_Version::supports_cmov() );
7355 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7356 // ins_cost(250);
7357 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7358 // opcode(0x0F,0x40);
7359 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7360 // ins_pipe( pipe_cmov_mem );
7361 //%}
7362
7363 // Conditional move
7364 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7365 predicate(UseSSE<=1);
7366 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7367 ins_cost(200);
7368 format %{ "FCMOV$cop $dst,$src\t# double" %}
7369 opcode(0xDA);
7370 ins_encode( enc_cmov_dpr(cop,src) );
7371 ins_pipe( pipe_cmovDPR_reg );
7372 %}
7373
7374 // Conditional move
7375 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7376 predicate(UseSSE==0);
7377 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7378 ins_cost(200);
7379 format %{ "FCMOV$cop $dst,$src\t# float" %}
7380 opcode(0xDA);
7381 ins_encode( enc_cmov_dpr(cop,src) );
7382 ins_pipe( pipe_cmovDPR_reg );
7383 %}
7384
7385 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7386 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7387 predicate(UseSSE<=1);
7388 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7389 ins_cost(200);
7390 format %{ "Jn$cop skip\n\t"
7391 "MOV $dst,$src\t# double\n"
7392 "skip:" %}
7393 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7394 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7395 ins_pipe( pipe_cmovDPR_reg );
7396 %}
7397
7398 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7399 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7400 predicate(UseSSE==0);
7401 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7402 ins_cost(200);
7403 format %{ "Jn$cop skip\n\t"
7404 "MOV $dst,$src\t# float\n"
7405 "skip:" %}
7406 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7407 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7408 ins_pipe( pipe_cmovDPR_reg );
7409 %}
7410
7411 // No CMOVE with SSE/SSE2
7412 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7413 predicate (UseSSE>=1);
7414 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7415 ins_cost(200);
7416 format %{ "Jn$cop skip\n\t"
7417 "MOVSS $dst,$src\t# float\n"
7418 "skip:" %}
7419 ins_encode %{
7420 Label skip;
7421 // Invert sense of branch from sense of CMOV
7422 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7423 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7424 __ bind(skip);
7425 %}
7426 ins_pipe( pipe_slow );
7427 %}
7428
7429 // No CMOVE with SSE/SSE2
7430 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7431 predicate (UseSSE>=2);
7432 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7433 ins_cost(200);
7434 format %{ "Jn$cop skip\n\t"
7435 "MOVSD $dst,$src\t# float\n"
7436 "skip:" %}
7437 ins_encode %{
7438 Label skip;
7439 // Invert sense of branch from sense of CMOV
7440 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7441 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7442 __ bind(skip);
7443 %}
7444 ins_pipe( pipe_slow );
7445 %}
7446
7447 // unsigned version
7448 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7449 predicate (UseSSE>=1);
7450 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7451 ins_cost(200);
7452 format %{ "Jn$cop skip\n\t"
7453 "MOVSS $dst,$src\t# float\n"
7454 "skip:" %}
7455 ins_encode %{
7456 Label skip;
7457 // Invert sense of branch from sense of CMOV
7458 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7459 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7460 __ bind(skip);
7461 %}
7462 ins_pipe( pipe_slow );
7463 %}
7464
7465 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7466 predicate (UseSSE>=1);
7467 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7468 ins_cost(200);
7469 expand %{
7470 fcmovF_regU(cop, cr, dst, src);
7471 %}
7472 %}
7473
7474 // unsigned version
7475 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7476 predicate (UseSSE>=2);
7477 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7478 ins_cost(200);
7479 format %{ "Jn$cop skip\n\t"
7480 "MOVSD $dst,$src\t# float\n"
7481 "skip:" %}
7482 ins_encode %{
7483 Label skip;
7484 // Invert sense of branch from sense of CMOV
7485 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7486 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7487 __ bind(skip);
7488 %}
7489 ins_pipe( pipe_slow );
7490 %}
7491
7492 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7493 predicate (UseSSE>=2);
7494 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7495 ins_cost(200);
7496 expand %{
7497 fcmovD_regU(cop, cr, dst, src);
7498 %}
7499 %}
7500
7501 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7502 predicate(VM_Version::supports_cmov() );
7503 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7504 ins_cost(200);
7505 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7506 "CMOV$cop $dst.hi,$src.hi" %}
7507 opcode(0x0F,0x40);
7508 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7509 ins_pipe( pipe_cmov_reg_long );
7510 %}
7511
7512 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7513 predicate(VM_Version::supports_cmov() );
7514 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7515 ins_cost(200);
7516 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7517 "CMOV$cop $dst.hi,$src.hi" %}
7518 opcode(0x0F,0x40);
7519 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7520 ins_pipe( pipe_cmov_reg_long );
7521 %}
7522
7523 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7524 predicate(VM_Version::supports_cmov() );
7525 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7526 ins_cost(200);
7527 expand %{
7528 cmovL_regU(cop, cr, dst, src);
7529 %}
7530 %}
7531
7532 //----------Arithmetic Instructions--------------------------------------------
7533 //----------Addition Instructions----------------------------------------------
7534
7535 // Integer Addition Instructions
7536 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7537 match(Set dst (AddI dst src));
7538 effect(KILL cr);
7539
7540 size(2);
7541 format %{ "ADD $dst,$src" %}
7542 opcode(0x03);
7543 ins_encode( OpcP, RegReg( dst, src) );
7544 ins_pipe( ialu_reg_reg );
7545 %}
7546
7547 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7548 match(Set dst (AddI dst src));
7549 effect(KILL cr);
7550
7551 format %{ "ADD $dst,$src" %}
7552 opcode(0x81, 0x00); /* /0 id */
7553 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7554 ins_pipe( ialu_reg );
7555 %}
7556
7557 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7558 predicate(UseIncDec);
7559 match(Set dst (AddI dst src));
7560 effect(KILL cr);
7561
7562 size(1);
7563 format %{ "INC $dst" %}
7564 opcode(0x40); /* */
7565 ins_encode( Opc_plus( primary, dst ) );
7566 ins_pipe( ialu_reg );
7567 %}
7568
7569 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7570 match(Set dst (AddI src0 src1));
7571 ins_cost(110);
7572
7573 format %{ "LEA $dst,[$src0 + $src1]" %}
7574 opcode(0x8D); /* 0x8D /r */
7575 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7576 ins_pipe( ialu_reg_reg );
7577 %}
7578
7579 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7580 match(Set dst (AddP src0 src1));
7581 ins_cost(110);
7582
7583 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7584 opcode(0x8D); /* 0x8D /r */
7585 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7586 ins_pipe( ialu_reg_reg );
7587 %}
7588
7589 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7590 predicate(UseIncDec);
7591 match(Set dst (AddI dst src));
7592 effect(KILL cr);
7593
7594 size(1);
7595 format %{ "DEC $dst" %}
7596 opcode(0x48); /* */
7597 ins_encode( Opc_plus( primary, dst ) );
7598 ins_pipe( ialu_reg );
7599 %}
7600
7601 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7602 match(Set dst (AddP dst src));
7603 effect(KILL cr);
7604
7605 size(2);
7606 format %{ "ADD $dst,$src" %}
7607 opcode(0x03);
7608 ins_encode( OpcP, RegReg( dst, src) );
7609 ins_pipe( ialu_reg_reg );
7610 %}
7611
7612 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7613 match(Set dst (AddP dst src));
7614 effect(KILL cr);
7615
7616 format %{ "ADD $dst,$src" %}
7617 opcode(0x81,0x00); /* Opcode 81 /0 id */
7618 // ins_encode( RegImm( dst, src) );
7619 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7620 ins_pipe( ialu_reg );
7621 %}
7622
7623 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7624 match(Set dst (AddI dst (LoadI src)));
7625 effect(KILL cr);
7626
7627 ins_cost(125);
7628 format %{ "ADD $dst,$src" %}
7629 opcode(0x03);
7630 ins_encode( OpcP, RegMem( dst, src) );
7631 ins_pipe( ialu_reg_mem );
7632 %}
7633
7634 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7635 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7636 effect(KILL cr);
7637
7638 ins_cost(150);
7639 format %{ "ADD $dst,$src" %}
7640 opcode(0x01); /* Opcode 01 /r */
7641 ins_encode( OpcP, RegMem( src, dst ) );
7642 ins_pipe( ialu_mem_reg );
7643 %}
7644
7645 // Add Memory with Immediate
7646 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7647 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7648 effect(KILL cr);
7649
7650 ins_cost(125);
7651 format %{ "ADD $dst,$src" %}
7652 opcode(0x81); /* Opcode 81 /0 id */
7653 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7654 ins_pipe( ialu_mem_imm );
7655 %}
7656
7657 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7658 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7659 effect(KILL cr);
7660
7661 ins_cost(125);
7662 format %{ "INC $dst" %}
7663 opcode(0xFF); /* Opcode FF /0 */
7664 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7665 ins_pipe( ialu_mem_imm );
7666 %}
7667
7668 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7669 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7670 effect(KILL cr);
7671
7672 ins_cost(125);
7673 format %{ "DEC $dst" %}
7674 opcode(0xFF); /* Opcode FF /1 */
7675 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7676 ins_pipe( ialu_mem_imm );
7677 %}
7678
7679
7680 instruct checkCastPP( eRegP dst ) %{
7681 match(Set dst (CheckCastPP dst));
7682
7683 size(0);
7684 format %{ "#checkcastPP of $dst" %}
7685 ins_encode( /*empty encoding*/ );
7686 ins_pipe( empty );
7687 %}
7688
7689 instruct castPP( eRegP dst ) %{
7690 match(Set dst (CastPP dst));
7691 format %{ "#castPP of $dst" %}
7692 ins_encode( /*empty encoding*/ );
7693 ins_pipe( empty );
7694 %}
7695
7696 instruct castII( rRegI dst ) %{
7697 match(Set dst (CastII dst));
7698 format %{ "#castII of $dst" %}
7699 ins_encode( /*empty encoding*/ );
7700 ins_cost(0);
7701 ins_pipe( empty );
7702 %}
7703
7704
7705 // Load-locked - same as a regular pointer load when used with compare-swap
7706 instruct loadPLocked(eRegP dst, memory mem) %{
7707 match(Set dst (LoadPLocked mem));
7708
7709 ins_cost(125);
7710 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7711 opcode(0x8B);
7712 ins_encode( OpcP, RegMem(dst,mem));
7713 ins_pipe( ialu_reg_mem );
7714 %}
7715
7716 // Conditional-store of the updated heap-top.
7717 // Used during allocation of the shared heap.
7718 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7719 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7720 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7721 // EAX is killed if there is contention, but then it's also unused.
7722 // In the common case of no contention, EAX holds the new oop address.
7723 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7724 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7725 ins_pipe( pipe_cmpxchg );
7726 %}
7727
7728 // Conditional-store of an int value.
7729 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7730 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7731 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7732 effect(KILL oldval);
7733 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7734 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7735 ins_pipe( pipe_cmpxchg );
7736 %}
7737
7738 // Conditional-store of a long value.
7739 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7740 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7741 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7742 effect(KILL oldval);
7743 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7744 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7745 "XCHG EBX,ECX"
7746 %}
7747 ins_encode %{
7748 // Note: we need to swap rbx, and rcx before and after the
7749 // cmpxchg8 instruction because the instruction uses
7750 // rcx as the high order word of the new value to store but
7751 // our register encoding uses rbx.
7752 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7753 if( os::is_MP() )
7754 __ lock();
7755 __ cmpxchg8($mem$$Address);
7756 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7757 %}
7758 ins_pipe( pipe_cmpxchg );
7759 %}
7760
7761 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7762
7763 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7764 predicate(VM_Version::supports_cx8());
7765 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7766 effect(KILL cr, KILL oldval);
7767 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7768 "MOV $res,0\n\t"
7769 "JNE,s fail\n\t"
7770 "MOV $res,1\n"
7771 "fail:" %}
7772 ins_encode( enc_cmpxchg8(mem_ptr),
7773 enc_flags_ne_to_boolean(res) );
7774 ins_pipe( pipe_cmpxchg );
7775 %}
7776
7777 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7778 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7779 effect(KILL cr, KILL oldval);
7780 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7781 "MOV $res,0\n\t"
7782 "JNE,s fail\n\t"
7783 "MOV $res,1\n"
7784 "fail:" %}
7785 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7786 ins_pipe( pipe_cmpxchg );
7787 %}
7788
7789 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7790 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7791 effect(KILL cr, KILL oldval);
7792 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7793 "MOV $res,0\n\t"
7794 "JNE,s fail\n\t"
7795 "MOV $res,1\n"
7796 "fail:" %}
7797 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7800
7801 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7802 predicate(n->as_LoadStore()->result_not_used());
7803 match(Set dummy (GetAndAddI mem add));
7804 effect(KILL cr);
7805 format %{ "ADDL [$mem],$add" %}
7806 ins_encode %{
7807 if (os::is_MP()) { __ lock(); }
7808 __ addl($mem$$Address, $add$$constant);
7809 %}
7810 ins_pipe( pipe_cmpxchg );
7811 %}
7812
7813 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7814 match(Set newval (GetAndAddI mem newval));
7815 effect(KILL cr);
7816 format %{ "XADDL [$mem],$newval" %}
7817 ins_encode %{
7818 if (os::is_MP()) { __ lock(); }
7819 __ xaddl($mem$$Address, $newval$$Register);
7820 %}
7821 ins_pipe( pipe_cmpxchg );
7822 %}
7823
7824 instruct xchgI( memory mem, rRegI newval) %{
7825 match(Set newval (GetAndSetI mem newval));
7826 format %{ "XCHGL $newval,[$mem]" %}
7827 ins_encode %{
7828 __ xchgl($newval$$Register, $mem$$Address);
7829 %}
7830 ins_pipe( pipe_cmpxchg );
7831 %}
7832
7833 instruct xchgP( memory mem, pRegP newval) %{
7834 match(Set newval (GetAndSetP mem newval));
7835 format %{ "XCHGL $newval,[$mem]" %}
7836 ins_encode %{
7837 __ xchgl($newval$$Register, $mem$$Address);
7838 %}
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 //----------Subtraction Instructions-------------------------------------------
7843
7844 // Integer Subtraction Instructions
7845 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7846 match(Set dst (SubI dst src));
7847 effect(KILL cr);
7848
7849 size(2);
7850 format %{ "SUB $dst,$src" %}
7851 opcode(0x2B);
7852 ins_encode( OpcP, RegReg( dst, src) );
7853 ins_pipe( ialu_reg_reg );
7854 %}
7855
7856 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7857 match(Set dst (SubI dst src));
7858 effect(KILL cr);
7859
7860 format %{ "SUB $dst,$src" %}
7861 opcode(0x81,0x05); /* Opcode 81 /5 */
7862 // ins_encode( RegImm( dst, src) );
7863 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7864 ins_pipe( ialu_reg );
7865 %}
7866
7867 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7868 match(Set dst (SubI dst (LoadI src)));
7869 effect(KILL cr);
7870
7871 ins_cost(125);
7872 format %{ "SUB $dst,$src" %}
7873 opcode(0x2B);
7874 ins_encode( OpcP, RegMem( dst, src) );
7875 ins_pipe( ialu_reg_mem );
7876 %}
7877
7878 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7879 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7880 effect(KILL cr);
7881
7882 ins_cost(150);
7883 format %{ "SUB $dst,$src" %}
7884 opcode(0x29); /* Opcode 29 /r */
7885 ins_encode( OpcP, RegMem( src, dst ) );
7886 ins_pipe( ialu_mem_reg );
7887 %}
7888
7889 // Subtract from a pointer
7890 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7891 match(Set dst (AddP dst (SubI zero src)));
7892 effect(KILL cr);
7893
7894 size(2);
7895 format %{ "SUB $dst,$src" %}
7896 opcode(0x2B);
7897 ins_encode( OpcP, RegReg( dst, src) );
7898 ins_pipe( ialu_reg_reg );
7899 %}
7900
7901 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7902 match(Set dst (SubI zero dst));
7903 effect(KILL cr);
7904
7905 size(2);
7906 format %{ "NEG $dst" %}
7907 opcode(0xF7,0x03); // Opcode F7 /3
7908 ins_encode( OpcP, RegOpc( dst ) );
7909 ins_pipe( ialu_reg );
7910 %}
7911
7912 //----------Multiplication/Division Instructions-------------------------------
7913 // Integer Multiplication Instructions
7914 // Multiply Register
7915 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7916 match(Set dst (MulI dst src));
7917 effect(KILL cr);
7918
7919 size(3);
7920 ins_cost(300);
7921 format %{ "IMUL $dst,$src" %}
7922 opcode(0xAF, 0x0F);
7923 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7924 ins_pipe( ialu_reg_reg_alu0 );
7925 %}
7926
7927 // Multiply 32-bit Immediate
7928 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7929 match(Set dst (MulI src imm));
7930 effect(KILL cr);
7931
7932 ins_cost(300);
7933 format %{ "IMUL $dst,$src,$imm" %}
7934 opcode(0x69); /* 69 /r id */
7935 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7936 ins_pipe( ialu_reg_reg_alu0 );
7937 %}
7938
7939 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7940 match(Set dst src);
7941 effect(KILL cr);
7942
7943 // Note that this is artificially increased to make it more expensive than loadConL
7944 ins_cost(250);
7945 format %{ "MOV EAX,$src\t// low word only" %}
7946 opcode(0xB8);
7947 ins_encode( LdImmL_Lo(dst, src) );
7948 ins_pipe( ialu_reg_fat );
7949 %}
7950
7951 // Multiply by 32-bit Immediate, taking the shifted high order results
7952 // (special case for shift by 32)
7953 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7954 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7955 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7956 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7957 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7958 effect(USE src1, KILL cr);
7959
7960 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7961 ins_cost(0*100 + 1*400 - 150);
7962 format %{ "IMUL EDX:EAX,$src1" %}
7963 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7964 ins_pipe( pipe_slow );
7965 %}
7966
7967 // Multiply by 32-bit Immediate, taking the shifted high order results
7968 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7969 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7970 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7971 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7972 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7973 effect(USE src1, KILL cr);
7974
7975 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7976 ins_cost(1*100 + 1*400 - 150);
7977 format %{ "IMUL EDX:EAX,$src1\n\t"
7978 "SAR EDX,$cnt-32" %}
7979 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7980 ins_pipe( pipe_slow );
7981 %}
7982
7983 // Multiply Memory 32-bit Immediate
7984 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7985 match(Set dst (MulI (LoadI src) imm));
7986 effect(KILL cr);
7987
7988 ins_cost(300);
7989 format %{ "IMUL $dst,$src,$imm" %}
7990 opcode(0x69); /* 69 /r id */
7991 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7992 ins_pipe( ialu_reg_mem_alu0 );
7993 %}
7994
7995 // Multiply Memory
7996 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7997 match(Set dst (MulI dst (LoadI src)));
7998 effect(KILL cr);
7999
8000 ins_cost(350);
8001 format %{ "IMUL $dst,$src" %}
8002 opcode(0xAF, 0x0F);
8003 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8004 ins_pipe( ialu_reg_mem_alu0 );
8005 %}
8006
8007 // Multiply Register Int to Long
8008 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8009 // Basic Idea: long = (long)int * (long)int
8010 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8011 effect(DEF dst, USE src, USE src1, KILL flags);
8012
8013 ins_cost(300);
8014 format %{ "IMUL $dst,$src1" %}
8015
8016 ins_encode( long_int_multiply( dst, src1 ) );
8017 ins_pipe( ialu_reg_reg_alu0 );
8018 %}
8019
8020 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8021 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8022 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8023 effect(KILL flags);
8024
8025 ins_cost(300);
8026 format %{ "MUL $dst,$src1" %}
8027
8028 ins_encode( long_uint_multiply(dst, src1) );
8029 ins_pipe( ialu_reg_reg_alu0 );
8030 %}
8031
8032 // Multiply Register Long
8033 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8034 match(Set dst (MulL dst src));
8035 effect(KILL cr, TEMP tmp);
8036 ins_cost(4*100+3*400);
8037 // Basic idea: lo(result) = lo(x_lo * y_lo)
8038 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8039 format %{ "MOV $tmp,$src.lo\n\t"
8040 "IMUL $tmp,EDX\n\t"
8041 "MOV EDX,$src.hi\n\t"
8042 "IMUL EDX,EAX\n\t"
8043 "ADD $tmp,EDX\n\t"
8044 "MUL EDX:EAX,$src.lo\n\t"
8045 "ADD EDX,$tmp" %}
8046 ins_encode( long_multiply( dst, src, tmp ) );
8047 ins_pipe( pipe_slow );
8048 %}
8049
8050 // Multiply Register Long where the left operand's high 32 bits are zero
8051 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8052 predicate(is_operand_hi32_zero(n->in(1)));
8053 match(Set dst (MulL dst src));
8054 effect(KILL cr, TEMP tmp);
8055 ins_cost(2*100+2*400);
8056 // Basic idea: lo(result) = lo(x_lo * y_lo)
8057 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8058 format %{ "MOV $tmp,$src.hi\n\t"
8059 "IMUL $tmp,EAX\n\t"
8060 "MUL EDX:EAX,$src.lo\n\t"
8061 "ADD EDX,$tmp" %}
8062 ins_encode %{
8063 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8064 __ imull($tmp$$Register, rax);
8065 __ mull($src$$Register);
8066 __ addl(rdx, $tmp$$Register);
8067 %}
8068 ins_pipe( pipe_slow );
8069 %}
8070
8071 // Multiply Register Long where the right operand's high 32 bits are zero
8072 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8073 predicate(is_operand_hi32_zero(n->in(2)));
8074 match(Set dst (MulL dst src));
8075 effect(KILL cr, TEMP tmp);
8076 ins_cost(2*100+2*400);
8077 // Basic idea: lo(result) = lo(x_lo * y_lo)
8078 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8079 format %{ "MOV $tmp,$src.lo\n\t"
8080 "IMUL $tmp,EDX\n\t"
8081 "MUL EDX:EAX,$src.lo\n\t"
8082 "ADD EDX,$tmp" %}
8083 ins_encode %{
8084 __ movl($tmp$$Register, $src$$Register);
8085 __ imull($tmp$$Register, rdx);
8086 __ mull($src$$Register);
8087 __ addl(rdx, $tmp$$Register);
8088 %}
8089 ins_pipe( pipe_slow );
8090 %}
8091
8092 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8093 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8094 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8095 match(Set dst (MulL dst src));
8096 effect(KILL cr);
8097 ins_cost(1*400);
8098 // Basic idea: lo(result) = lo(x_lo * y_lo)
8099 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8100 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8101 ins_encode %{
8102 __ mull($src$$Register);
8103 %}
8104 ins_pipe( pipe_slow );
8105 %}
8106
8107 // Multiply Register Long by small constant
8108 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8109 match(Set dst (MulL dst src));
8110 effect(KILL cr, TEMP tmp);
8111 ins_cost(2*100+2*400);
8112 size(12);
8113 // Basic idea: lo(result) = lo(src * EAX)
8114 // hi(result) = hi(src * EAX) + lo(src * EDX)
8115 format %{ "IMUL $tmp,EDX,$src\n\t"
8116 "MOV EDX,$src\n\t"
8117 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8118 "ADD EDX,$tmp" %}
8119 ins_encode( long_multiply_con( dst, src, tmp ) );
8120 ins_pipe( pipe_slow );
8121 %}
8122
8123 // Integer DIV with Register
8124 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8125 match(Set rax (DivI rax div));
8126 effect(KILL rdx, KILL cr);
8127 size(26);
8128 ins_cost(30*100+10*100);
8129 format %{ "CMP EAX,0x80000000\n\t"
8130 "JNE,s normal\n\t"
8131 "XOR EDX,EDX\n\t"
8132 "CMP ECX,-1\n\t"
8133 "JE,s done\n"
8134 "normal: CDQ\n\t"
8135 "IDIV $div\n\t"
8136 "done:" %}
8137 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8138 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8139 ins_pipe( ialu_reg_reg_alu0 );
8140 %}
8141
8142 // Divide Register Long
8143 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8144 match(Set dst (DivL src1 src2));
8145 effect( KILL cr, KILL cx, KILL bx );
8146 ins_cost(10000);
8147 format %{ "PUSH $src1.hi\n\t"
8148 "PUSH $src1.lo\n\t"
8149 "PUSH $src2.hi\n\t"
8150 "PUSH $src2.lo\n\t"
8151 "CALL SharedRuntime::ldiv\n\t"
8152 "ADD ESP,16" %}
8153 ins_encode( long_div(src1,src2) );
8154 ins_pipe( pipe_slow );
8155 %}
8156
8157 // Integer DIVMOD with Register, both quotient and mod results
8158 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8159 match(DivModI rax div);
8160 effect(KILL cr);
8161 size(26);
8162 ins_cost(30*100+10*100);
8163 format %{ "CMP EAX,0x80000000\n\t"
8164 "JNE,s normal\n\t"
8165 "XOR EDX,EDX\n\t"
8166 "CMP ECX,-1\n\t"
8167 "JE,s done\n"
8168 "normal: CDQ\n\t"
8169 "IDIV $div\n\t"
8170 "done:" %}
8171 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8172 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8173 ins_pipe( pipe_slow );
8174 %}
8175
8176 // Integer MOD with Register
8177 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8178 match(Set rdx (ModI rax div));
8179 effect(KILL rax, KILL cr);
8180
8181 size(26);
8182 ins_cost(300);
8183 format %{ "CDQ\n\t"
8184 "IDIV $div" %}
8185 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8186 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8187 ins_pipe( ialu_reg_reg_alu0 );
8188 %}
8189
8190 // Remainder Register Long
8191 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8192 match(Set dst (ModL src1 src2));
8193 effect( KILL cr, KILL cx, KILL bx );
8194 ins_cost(10000);
8195 format %{ "PUSH $src1.hi\n\t"
8196 "PUSH $src1.lo\n\t"
8197 "PUSH $src2.hi\n\t"
8198 "PUSH $src2.lo\n\t"
8199 "CALL SharedRuntime::lrem\n\t"
8200 "ADD ESP,16" %}
8201 ins_encode( long_mod(src1,src2) );
8202 ins_pipe( pipe_slow );
8203 %}
8204
8205 // Divide Register Long (no special case since divisor != -1)
8206 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8207 match(Set dst (DivL dst imm));
8208 effect( TEMP tmp, TEMP tmp2, KILL cr );
8209 ins_cost(1000);
8210 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8211 "XOR $tmp2,$tmp2\n\t"
8212 "CMP $tmp,EDX\n\t"
8213 "JA,s fast\n\t"
8214 "MOV $tmp2,EAX\n\t"
8215 "MOV EAX,EDX\n\t"
8216 "MOV EDX,0\n\t"
8217 "JLE,s pos\n\t"
8218 "LNEG EAX : $tmp2\n\t"
8219 "DIV $tmp # unsigned division\n\t"
8220 "XCHG EAX,$tmp2\n\t"
8221 "DIV $tmp\n\t"
8222 "LNEG $tmp2 : EAX\n\t"
8223 "JMP,s done\n"
8224 "pos:\n\t"
8225 "DIV $tmp\n\t"
8226 "XCHG EAX,$tmp2\n"
8227 "fast:\n\t"
8228 "DIV $tmp\n"
8229 "done:\n\t"
8230 "MOV EDX,$tmp2\n\t"
8231 "NEG EDX:EAX # if $imm < 0" %}
8232 ins_encode %{
8233 int con = (int)$imm$$constant;
8234 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8235 int pcon = (con > 0) ? con : -con;
8236 Label Lfast, Lpos, Ldone;
8237
8238 __ movl($tmp$$Register, pcon);
8239 __ xorl($tmp2$$Register,$tmp2$$Register);
8240 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8241 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8242
8243 __ movl($tmp2$$Register, $dst$$Register); // save
8244 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8245 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8246 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8247
8248 // Negative dividend.
8249 // convert value to positive to use unsigned division
8250 __ lneg($dst$$Register, $tmp2$$Register);
8251 __ divl($tmp$$Register);
8252 __ xchgl($dst$$Register, $tmp2$$Register);
8253 __ divl($tmp$$Register);
8254 // revert result back to negative
8255 __ lneg($tmp2$$Register, $dst$$Register);
8256 __ jmpb(Ldone);
8257
8258 __ bind(Lpos);
8259 __ divl($tmp$$Register); // Use unsigned division
8260 __ xchgl($dst$$Register, $tmp2$$Register);
8261 // Fallthrow for final divide, tmp2 has 32 bit hi result
8262
8263 __ bind(Lfast);
8264 // fast path: src is positive
8265 __ divl($tmp$$Register); // Use unsigned division
8266
8267 __ bind(Ldone);
8268 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8269 if (con < 0) {
8270 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8271 }
8272 %}
8273 ins_pipe( pipe_slow );
8274 %}
8275
8276 // Remainder Register Long (remainder fit into 32 bits)
8277 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8278 match(Set dst (ModL dst imm));
8279 effect( TEMP tmp, TEMP tmp2, KILL cr );
8280 ins_cost(1000);
8281 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8282 "CMP $tmp,EDX\n\t"
8283 "JA,s fast\n\t"
8284 "MOV $tmp2,EAX\n\t"
8285 "MOV EAX,EDX\n\t"
8286 "MOV EDX,0\n\t"
8287 "JLE,s pos\n\t"
8288 "LNEG EAX : $tmp2\n\t"
8289 "DIV $tmp # unsigned division\n\t"
8290 "MOV EAX,$tmp2\n\t"
8291 "DIV $tmp\n\t"
8292 "NEG EDX\n\t"
8293 "JMP,s done\n"
8294 "pos:\n\t"
8295 "DIV $tmp\n\t"
8296 "MOV EAX,$tmp2\n"
8297 "fast:\n\t"
8298 "DIV $tmp\n"
8299 "done:\n\t"
8300 "MOV EAX,EDX\n\t"
8301 "SAR EDX,31\n\t" %}
8302 ins_encode %{
8303 int con = (int)$imm$$constant;
8304 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8305 int pcon = (con > 0) ? con : -con;
8306 Label Lfast, Lpos, Ldone;
8307
8308 __ movl($tmp$$Register, pcon);
8309 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8310 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8311
8312 __ movl($tmp2$$Register, $dst$$Register); // save
8313 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8314 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8315 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8316
8317 // Negative dividend.
8318 // convert value to positive to use unsigned division
8319 __ lneg($dst$$Register, $tmp2$$Register);
8320 __ divl($tmp$$Register);
8321 __ movl($dst$$Register, $tmp2$$Register);
8322 __ divl($tmp$$Register);
8323 // revert remainder back to negative
8324 __ negl(HIGH_FROM_LOW($dst$$Register));
8325 __ jmpb(Ldone);
8326
8327 __ bind(Lpos);
8328 __ divl($tmp$$Register);
8329 __ movl($dst$$Register, $tmp2$$Register);
8330
8331 __ bind(Lfast);
8332 // fast path: src is positive
8333 __ divl($tmp$$Register);
8334
8335 __ bind(Ldone);
8336 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8337 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8338
8339 %}
8340 ins_pipe( pipe_slow );
8341 %}
8342
8343 // Integer Shift Instructions
8344 // Shift Left by one
8345 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8346 match(Set dst (LShiftI dst shift));
8347 effect(KILL cr);
8348
8349 size(2);
8350 format %{ "SHL $dst,$shift" %}
8351 opcode(0xD1, 0x4); /* D1 /4 */
8352 ins_encode( OpcP, RegOpc( dst ) );
8353 ins_pipe( ialu_reg );
8354 %}
8355
8356 // Shift Left by 8-bit immediate
8357 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8358 match(Set dst (LShiftI dst shift));
8359 effect(KILL cr);
8360
8361 size(3);
8362 format %{ "SHL $dst,$shift" %}
8363 opcode(0xC1, 0x4); /* C1 /4 ib */
8364 ins_encode( RegOpcImm( dst, shift) );
8365 ins_pipe( ialu_reg );
8366 %}
8367
8368 // Shift Left by variable
8369 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8370 match(Set dst (LShiftI dst shift));
8371 effect(KILL cr);
8372
8373 size(2);
8374 format %{ "SHL $dst,$shift" %}
8375 opcode(0xD3, 0x4); /* D3 /4 */
8376 ins_encode( OpcP, RegOpc( dst ) );
8377 ins_pipe( ialu_reg_reg );
8378 %}
8379
8380 // Arithmetic shift right by one
8381 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8382 match(Set dst (RShiftI dst shift));
8383 effect(KILL cr);
8384
8385 size(2);
8386 format %{ "SAR $dst,$shift" %}
8387 opcode(0xD1, 0x7); /* D1 /7 */
8388 ins_encode( OpcP, RegOpc( dst ) );
8389 ins_pipe( ialu_reg );
8390 %}
8391
8392 // Arithmetic shift right by one
8393 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8394 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8395 effect(KILL cr);
8396 format %{ "SAR $dst,$shift" %}
8397 opcode(0xD1, 0x7); /* D1 /7 */
8398 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8399 ins_pipe( ialu_mem_imm );
8400 %}
8401
8402 // Arithmetic Shift Right by 8-bit immediate
8403 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8404 match(Set dst (RShiftI dst shift));
8405 effect(KILL cr);
8406
8407 size(3);
8408 format %{ "SAR $dst,$shift" %}
8409 opcode(0xC1, 0x7); /* C1 /7 ib */
8410 ins_encode( RegOpcImm( dst, shift ) );
8411 ins_pipe( ialu_mem_imm );
8412 %}
8413
8414 // Arithmetic Shift Right by 8-bit immediate
8415 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8416 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8417 effect(KILL cr);
8418
8419 format %{ "SAR $dst,$shift" %}
8420 opcode(0xC1, 0x7); /* C1 /7 ib */
8421 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8422 ins_pipe( ialu_mem_imm );
8423 %}
8424
8425 // Arithmetic Shift Right by variable
8426 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8427 match(Set dst (RShiftI dst shift));
8428 effect(KILL cr);
8429
8430 size(2);
8431 format %{ "SAR $dst,$shift" %}
8432 opcode(0xD3, 0x7); /* D3 /7 */
8433 ins_encode( OpcP, RegOpc( dst ) );
8434 ins_pipe( ialu_reg_reg );
8435 %}
8436
8437 // Logical shift right by one
8438 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8439 match(Set dst (URShiftI dst shift));
8440 effect(KILL cr);
8441
8442 size(2);
8443 format %{ "SHR $dst,$shift" %}
8444 opcode(0xD1, 0x5); /* D1 /5 */
8445 ins_encode( OpcP, RegOpc( dst ) );
8446 ins_pipe( ialu_reg );
8447 %}
8448
8449 // Logical Shift Right by 8-bit immediate
8450 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8451 match(Set dst (URShiftI dst shift));
8452 effect(KILL cr);
8453
8454 size(3);
8455 format %{ "SHR $dst,$shift" %}
8456 opcode(0xC1, 0x5); /* C1 /5 ib */
8457 ins_encode( RegOpcImm( dst, shift) );
8458 ins_pipe( ialu_reg );
8459 %}
8460
8461
8462 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8463 // This idiom is used by the compiler for the i2b bytecode.
8464 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8465 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8466
8467 size(3);
8468 format %{ "MOVSX $dst,$src :8" %}
8469 ins_encode %{
8470 __ movsbl($dst$$Register, $src$$Register);
8471 %}
8472 ins_pipe(ialu_reg_reg);
8473 %}
8474
8475 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8476 // This idiom is used by the compiler the i2s bytecode.
8477 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8478 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8479
8480 size(3);
8481 format %{ "MOVSX $dst,$src :16" %}
8482 ins_encode %{
8483 __ movswl($dst$$Register, $src$$Register);
8484 %}
8485 ins_pipe(ialu_reg_reg);
8486 %}
8487
8488
8489 // Logical Shift Right by variable
8490 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8491 match(Set dst (URShiftI dst shift));
8492 effect(KILL cr);
8493
8494 size(2);
8495 format %{ "SHR $dst,$shift" %}
8496 opcode(0xD3, 0x5); /* D3 /5 */
8497 ins_encode( OpcP, RegOpc( dst ) );
8498 ins_pipe( ialu_reg_reg );
8499 %}
8500
8501
8502 //----------Logical Instructions-----------------------------------------------
8503 //----------Integer Logical Instructions---------------------------------------
8504 // And Instructions
8505 // And Register with Register
8506 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8507 match(Set dst (AndI dst src));
8508 effect(KILL cr);
8509
8510 size(2);
8511 format %{ "AND $dst,$src" %}
8512 opcode(0x23);
8513 ins_encode( OpcP, RegReg( dst, src) );
8514 ins_pipe( ialu_reg_reg );
8515 %}
8516
8517 // And Register with Immediate
8518 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8519 match(Set dst (AndI dst src));
8520 effect(KILL cr);
8521
8522 format %{ "AND $dst,$src" %}
8523 opcode(0x81,0x04); /* Opcode 81 /4 */
8524 // ins_encode( RegImm( dst, src) );
8525 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8526 ins_pipe( ialu_reg );
8527 %}
8528
8529 // And Register with Memory
8530 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8531 match(Set dst (AndI dst (LoadI src)));
8532 effect(KILL cr);
8533
8534 ins_cost(125);
8535 format %{ "AND $dst,$src" %}
8536 opcode(0x23);
8537 ins_encode( OpcP, RegMem( dst, src) );
8538 ins_pipe( ialu_reg_mem );
8539 %}
8540
8541 // And Memory with Register
8542 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8543 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8544 effect(KILL cr);
8545
8546 ins_cost(150);
8547 format %{ "AND $dst,$src" %}
8548 opcode(0x21); /* Opcode 21 /r */
8549 ins_encode( OpcP, RegMem( src, dst ) );
8550 ins_pipe( ialu_mem_reg );
8551 %}
8552
8553 // And Memory with Immediate
8554 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8555 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8556 effect(KILL cr);
8557
8558 ins_cost(125);
8559 format %{ "AND $dst,$src" %}
8560 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8561 // ins_encode( MemImm( dst, src) );
8562 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8563 ins_pipe( ialu_mem_imm );
8564 %}
8565
8566 // Or Instructions
8567 // Or Register with Register
8568 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8569 match(Set dst (OrI dst src));
8570 effect(KILL cr);
8571
8572 size(2);
8573 format %{ "OR $dst,$src" %}
8574 opcode(0x0B);
8575 ins_encode( OpcP, RegReg( dst, src) );
8576 ins_pipe( ialu_reg_reg );
8577 %}
8578
8579 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8580 match(Set dst (OrI dst (CastP2X src)));
8581 effect(KILL cr);
8582
8583 size(2);
8584 format %{ "OR $dst,$src" %}
8585 opcode(0x0B);
8586 ins_encode( OpcP, RegReg( dst, src) );
8587 ins_pipe( ialu_reg_reg );
8588 %}
8589
8590
8591 // Or Register with Immediate
8592 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8593 match(Set dst (OrI dst src));
8594 effect(KILL cr);
8595
8596 format %{ "OR $dst,$src" %}
8597 opcode(0x81,0x01); /* Opcode 81 /1 id */
8598 // ins_encode( RegImm( dst, src) );
8599 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8600 ins_pipe( ialu_reg );
8601 %}
8602
8603 // Or Register with Memory
8604 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8605 match(Set dst (OrI dst (LoadI src)));
8606 effect(KILL cr);
8607
8608 ins_cost(125);
8609 format %{ "OR $dst,$src" %}
8610 opcode(0x0B);
8611 ins_encode( OpcP, RegMem( dst, src) );
8612 ins_pipe( ialu_reg_mem );
8613 %}
8614
8615 // Or Memory with Register
8616 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8617 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8618 effect(KILL cr);
8619
8620 ins_cost(150);
8621 format %{ "OR $dst,$src" %}
8622 opcode(0x09); /* Opcode 09 /r */
8623 ins_encode( OpcP, RegMem( src, dst ) );
8624 ins_pipe( ialu_mem_reg );
8625 %}
8626
8627 // Or Memory with Immediate
8628 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8629 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8630 effect(KILL cr);
8631
8632 ins_cost(125);
8633 format %{ "OR $dst,$src" %}
8634 opcode(0x81,0x1); /* Opcode 81 /1 id */
8635 // ins_encode( MemImm( dst, src) );
8636 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8637 ins_pipe( ialu_mem_imm );
8638 %}
8639
8640 // ROL/ROR
8641 // ROL expand
8642 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8643 effect(USE_DEF dst, USE shift, KILL cr);
8644
8645 format %{ "ROL $dst, $shift" %}
8646 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8647 ins_encode( OpcP, RegOpc( dst ));
8648 ins_pipe( ialu_reg );
8649 %}
8650
8651 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8652 effect(USE_DEF dst, USE shift, KILL cr);
8653
8654 format %{ "ROL $dst, $shift" %}
8655 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8656 ins_encode( RegOpcImm(dst, shift) );
8657 ins_pipe(ialu_reg);
8658 %}
8659
8660 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8661 effect(USE_DEF dst, USE shift, KILL cr);
8662
8663 format %{ "ROL $dst, $shift" %}
8664 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8665 ins_encode(OpcP, RegOpc(dst));
8666 ins_pipe( ialu_reg_reg );
8667 %}
8668 // end of ROL expand
8669
8670 // ROL 32bit by one once
8671 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8672 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8673
8674 expand %{
8675 rolI_eReg_imm1(dst, lshift, cr);
8676 %}
8677 %}
8678
8679 // ROL 32bit var by imm8 once
8680 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8681 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8682 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8683
8684 expand %{
8685 rolI_eReg_imm8(dst, lshift, cr);
8686 %}
8687 %}
8688
8689 // ROL 32bit var by var once
8690 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8691 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8692
8693 expand %{
8694 rolI_eReg_CL(dst, shift, cr);
8695 %}
8696 %}
8697
8698 // ROL 32bit var by var once
8699 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8700 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8701
8702 expand %{
8703 rolI_eReg_CL(dst, shift, cr);
8704 %}
8705 %}
8706
8707 // ROR expand
8708 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8709 effect(USE_DEF dst, USE shift, KILL cr);
8710
8711 format %{ "ROR $dst, $shift" %}
8712 opcode(0xD1,0x1); /* Opcode D1 /1 */
8713 ins_encode( OpcP, RegOpc( dst ) );
8714 ins_pipe( ialu_reg );
8715 %}
8716
8717 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8718 effect (USE_DEF dst, USE shift, KILL cr);
8719
8720 format %{ "ROR $dst, $shift" %}
8721 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8722 ins_encode( RegOpcImm(dst, shift) );
8723 ins_pipe( ialu_reg );
8724 %}
8725
8726 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8727 effect(USE_DEF dst, USE shift, KILL cr);
8728
8729 format %{ "ROR $dst, $shift" %}
8730 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8731 ins_encode(OpcP, RegOpc(dst));
8732 ins_pipe( ialu_reg_reg );
8733 %}
8734 // end of ROR expand
8735
8736 // ROR right once
8737 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8738 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8739
8740 expand %{
8741 rorI_eReg_imm1(dst, rshift, cr);
8742 %}
8743 %}
8744
8745 // ROR 32bit by immI8 once
8746 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8747 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8748 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8749
8750 expand %{
8751 rorI_eReg_imm8(dst, rshift, cr);
8752 %}
8753 %}
8754
8755 // ROR 32bit var by var once
8756 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8757 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8758
8759 expand %{
8760 rorI_eReg_CL(dst, shift, cr);
8761 %}
8762 %}
8763
8764 // ROR 32bit var by var once
8765 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8766 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8767
8768 expand %{
8769 rorI_eReg_CL(dst, shift, cr);
8770 %}
8771 %}
8772
8773 // Xor Instructions
8774 // Xor Register with Register
8775 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8776 match(Set dst (XorI dst src));
8777 effect(KILL cr);
8778
8779 size(2);
8780 format %{ "XOR $dst,$src" %}
8781 opcode(0x33);
8782 ins_encode( OpcP, RegReg( dst, src) );
8783 ins_pipe( ialu_reg_reg );
8784 %}
8785
8786 // Xor Register with Immediate -1
8787 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8788 match(Set dst (XorI dst imm));
8789
8790 size(2);
8791 format %{ "NOT $dst" %}
8792 ins_encode %{
8793 __ notl($dst$$Register);
8794 %}
8795 ins_pipe( ialu_reg );
8796 %}
8797
8798 // Xor Register with Immediate
8799 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8800 match(Set dst (XorI dst src));
8801 effect(KILL cr);
8802
8803 format %{ "XOR $dst,$src" %}
8804 opcode(0x81,0x06); /* Opcode 81 /6 id */
8805 // ins_encode( RegImm( dst, src) );
8806 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8807 ins_pipe( ialu_reg );
8808 %}
8809
8810 // Xor Register with Memory
8811 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8812 match(Set dst (XorI dst (LoadI src)));
8813 effect(KILL cr);
8814
8815 ins_cost(125);
8816 format %{ "XOR $dst,$src" %}
8817 opcode(0x33);
8818 ins_encode( OpcP, RegMem(dst, src) );
8819 ins_pipe( ialu_reg_mem );
8820 %}
8821
8822 // Xor Memory with Register
8823 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8824 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8825 effect(KILL cr);
8826
8827 ins_cost(150);
8828 format %{ "XOR $dst,$src" %}
8829 opcode(0x31); /* Opcode 31 /r */
8830 ins_encode( OpcP, RegMem( src, dst ) );
8831 ins_pipe( ialu_mem_reg );
8832 %}
8833
8834 // Xor Memory with Immediate
8835 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8836 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8837 effect(KILL cr);
8838
8839 ins_cost(125);
8840 format %{ "XOR $dst,$src" %}
8841 opcode(0x81,0x6); /* Opcode 81 /6 id */
8842 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8843 ins_pipe( ialu_mem_imm );
8844 %}
8845
8846 //----------Convert Int to Boolean---------------------------------------------
8847
8848 instruct movI_nocopy(rRegI dst, rRegI src) %{
8849 effect( DEF dst, USE src );
8850 format %{ "MOV $dst,$src" %}
8851 ins_encode( enc_Copy( dst, src) );
8852 ins_pipe( ialu_reg_reg );
8853 %}
8854
8855 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8856 effect( USE_DEF dst, USE src, KILL cr );
8857
8858 size(4);
8859 format %{ "NEG $dst\n\t"
8860 "ADC $dst,$src" %}
8861 ins_encode( neg_reg(dst),
8862 OpcRegReg(0x13,dst,src) );
8863 ins_pipe( ialu_reg_reg_long );
8864 %}
8865
8866 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8867 match(Set dst (Conv2B src));
8868
8869 expand %{
8870 movI_nocopy(dst,src);
8871 ci2b(dst,src,cr);
8872 %}
8873 %}
8874
8875 instruct movP_nocopy(rRegI dst, eRegP src) %{
8876 effect( DEF dst, USE src );
8877 format %{ "MOV $dst,$src" %}
8878 ins_encode( enc_Copy( dst, src) );
8879 ins_pipe( ialu_reg_reg );
8880 %}
8881
8882 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8883 effect( USE_DEF dst, USE src, KILL cr );
8884 format %{ "NEG $dst\n\t"
8885 "ADC $dst,$src" %}
8886 ins_encode( neg_reg(dst),
8887 OpcRegReg(0x13,dst,src) );
8888 ins_pipe( ialu_reg_reg_long );
8889 %}
8890
8891 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8892 match(Set dst (Conv2B src));
8893
8894 expand %{
8895 movP_nocopy(dst,src);
8896 cp2b(dst,src,cr);
8897 %}
8898 %}
8899
8900 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8901 match(Set dst (CmpLTMask p q));
8902 effect(KILL cr);
8903 ins_cost(400);
8904
8905 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8906 format %{ "XOR $dst,$dst\n\t"
8907 "CMP $p,$q\n\t"
8908 "SETlt $dst\n\t"
8909 "NEG $dst" %}
8910 ins_encode %{
8911 Register Rp = $p$$Register;
8912 Register Rq = $q$$Register;
8913 Register Rd = $dst$$Register;
8914 Label done;
8915 __ xorl(Rd, Rd);
8916 __ cmpl(Rp, Rq);
8917 __ setb(Assembler::less, Rd);
8918 __ negl(Rd);
8919 %}
8920
8921 ins_pipe(pipe_slow);
8922 %}
8923
8924 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8925 match(Set dst (CmpLTMask dst zero));
8926 effect(DEF dst, KILL cr);
8927 ins_cost(100);
8928
8929 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8930 ins_encode %{
8931 __ sarl($dst$$Register, 31);
8932 %}
8933 ins_pipe(ialu_reg);
8934 %}
8935
8936 /* better to save a register than avoid a branch */
8937 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8938 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8939 effect(KILL cr);
8940 ins_cost(400);
8941 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8942 "JGE done\n\t"
8943 "ADD $p,$y\n"
8944 "done: " %}
8945 ins_encode %{
8946 Register Rp = $p$$Register;
8947 Register Rq = $q$$Register;
8948 Register Ry = $y$$Register;
8949 Label done;
8950 __ subl(Rp, Rq);
8951 __ jccb(Assembler::greaterEqual, done);
8952 __ addl(Rp, Ry);
8953 __ bind(done);
8954 %}
8955
8956 ins_pipe(pipe_cmplt);
8957 %}
8958
8959 /* better to save a register than avoid a branch */
8960 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8961 match(Set y (AndI (CmpLTMask p q) y));
8962 effect(KILL cr);
8963
8964 ins_cost(300);
8965
8966 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8967 "JLT done\n\t"
8968 "XORL $y, $y\n"
8969 "done: " %}
8970 ins_encode %{
8971 Register Rp = $p$$Register;
8972 Register Rq = $q$$Register;
8973 Register Ry = $y$$Register;
8974 Label done;
8975 __ cmpl(Rp, Rq);
8976 __ jccb(Assembler::less, done);
8977 __ xorl(Ry, Ry);
8978 __ bind(done);
8979 %}
8980
8981 ins_pipe(pipe_cmplt);
8982 %}
8983
8984 /* If I enable this, I encourage spilling in the inner loop of compress.
8985 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8986 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8987 */
8988 //----------Overflow Math Instructions-----------------------------------------
8989
8990 instruct addofI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8991 %{
8992 match(Set cr (OverflowAddI op1 op2));
8993 effect(DEF cr, USE_KILL op1, USE op2);
8994
8995 format %{ "ADD $op1, $op2 #overflow check int" %}
8996
8997 ins_encode %{
8998 __ addl($op1$$Register, $op2$$Register);
8999 %}
9000 ins_pipe(ialu_reg_reg);
9001 %}
9002
9003 instruct addofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
9004 %{
9005 match(Set cr (OverflowAddI op1 op2));
9006 effect(DEF cr, USE_KILL op1, USE op2);
9007
9008 format %{ "ADD $op1, $op2 #overflow check int" %}
9009
9010 ins_encode %{
9011 __ addl($op1$$Register, $op2$$constant);
9012 %}
9013 ins_pipe(ialu_reg_reg);
9014 %}
9015
9016 instruct subofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9017 %{
9018 match(Set cr (OverflowSubI op1 op2));
9019 effect(DEF cr, USE op1, USE op2);
9020
9021 format %{ "CMP $op1, $op2 #overflow check int" %}
9022 ins_encode %{
9023 __ cmpl($op1$$Register, $op2$$Register);
9024 %}
9025 ins_pipe(ialu_reg_reg);
9026 %}
9027
9028 instruct subofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
9029 %{
9030 match(Set cr (OverflowSubI op1 op2));
9031 effect(DEF cr, USE op1, USE op2);
9032
9033 format %{ "CMP $op1, $op2 #overflow check int" %}
9034 ins_encode %{
9035 __ cmpl($op1$$Register, $op2$$constant);
9036 %}
9037 ins_pipe(ialu_reg_reg);
9038 %}
9039
9040 instruct negofI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
9041 %{
9042 match(Set cr (OverflowSubI zero op2));
9043 effect(DEF cr, USE_KILL op2);
9044
9045 format %{ "NEG $op2 #overflow check int" %}
9046 ins_encode %{
9047 __ negl($op2$$Register);
9048 %}
9049 ins_pipe(ialu_reg_reg);
9050 %}
9051
9052 instruct mulofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9053 %{
9054 match(Set cr (OverflowMulI op1 op2));
9055 effect(DEF cr, USE_KILL op1, USE op2);
9056
9057 format %{ "IMUL $op1, $op2 #overflow check int" %}
9058 ins_encode %{
9059 __ imull($op1$$Register, $op2$$Register);
9060 %}
9061 ins_pipe(ialu_reg_reg_alu0);
9062 %}
9063
9064 instruct mulofI_rReg_imm(eFlagsReg cr, eAXRegI op1, rRegI op2, immI op3)
9065 %{
9066 match(Set cr (OverflowMulI op2 op3));
9067 effect(DEF cr, KILL op1, USE op2, USE op3);
9068
9069 format %{ "IMUL $op1, $op2, $op3 #overflow check int" %}
9070 ins_encode %{
9071 __ imull($op1$$Register, $op2$$Register, $op3$$constant);
9072 %}
9073 ins_pipe(ialu_reg_reg_alu0);
9074 %}
9075
9076 //----------Long Instructions------------------------------------------------
9077 // Add Long Register with Register
9078 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9079 match(Set dst (AddL dst src));
9080 effect(KILL cr);
9081 ins_cost(200);
9082 format %{ "ADD $dst.lo,$src.lo\n\t"
9083 "ADC $dst.hi,$src.hi" %}
9084 opcode(0x03, 0x13);
9085 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9086 ins_pipe( ialu_reg_reg_long );
9087 %}
9088
9089 // Add Long Register with Immediate
9090 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9091 match(Set dst (AddL dst src));
9092 effect(KILL cr);
9093 format %{ "ADD $dst.lo,$src.lo\n\t"
9094 "ADC $dst.hi,$src.hi" %}
9095 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9096 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9097 ins_pipe( ialu_reg_long );
9098 %}
9099
9100 // Add Long Register with Memory
9101 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9102 match(Set dst (AddL dst (LoadL mem)));
9103 effect(KILL cr);
9104 ins_cost(125);
9105 format %{ "ADD $dst.lo,$mem\n\t"
9106 "ADC $dst.hi,$mem+4" %}
9107 opcode(0x03, 0x13);
9108 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9109 ins_pipe( ialu_reg_long_mem );
9110 %}
9111
9112 // Subtract Long Register with Register.
9113 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9114 match(Set dst (SubL dst src));
9115 effect(KILL cr);
9116 ins_cost(200);
9117 format %{ "SUB $dst.lo,$src.lo\n\t"
9118 "SBB $dst.hi,$src.hi" %}
9119 opcode(0x2B, 0x1B);
9120 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9121 ins_pipe( ialu_reg_reg_long );
9122 %}
9123
9124 // Subtract Long Register with Immediate
9125 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9126 match(Set dst (SubL dst src));
9127 effect(KILL cr);
9128 format %{ "SUB $dst.lo,$src.lo\n\t"
9129 "SBB $dst.hi,$src.hi" %}
9130 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9131 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9132 ins_pipe( ialu_reg_long );
9133 %}
9134
9135 // Subtract Long Register with Memory
9136 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9137 match(Set dst (SubL dst (LoadL mem)));
9138 effect(KILL cr);
9139 ins_cost(125);
9140 format %{ "SUB $dst.lo,$mem\n\t"
9141 "SBB $dst.hi,$mem+4" %}
9142 opcode(0x2B, 0x1B);
9143 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9144 ins_pipe( ialu_reg_long_mem );
9145 %}
9146
9147 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9148 match(Set dst (SubL zero dst));
9149 effect(KILL cr);
9150 ins_cost(300);
9151 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9152 ins_encode( neg_long(dst) );
9153 ins_pipe( ialu_reg_reg_long );
9154 %}
9155
9156 // And Long Register with Register
9157 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9158 match(Set dst (AndL dst src));
9159 effect(KILL cr);
9160 format %{ "AND $dst.lo,$src.lo\n\t"
9161 "AND $dst.hi,$src.hi" %}
9162 opcode(0x23,0x23);
9163 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9164 ins_pipe( ialu_reg_reg_long );
9165 %}
9166
9167 // And Long Register with Immediate
9168 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9169 match(Set dst (AndL dst src));
9170 effect(KILL cr);
9171 format %{ "AND $dst.lo,$src.lo\n\t"
9172 "AND $dst.hi,$src.hi" %}
9173 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9174 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9175 ins_pipe( ialu_reg_long );
9176 %}
9177
9178 // And Long Register with Memory
9179 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9180 match(Set dst (AndL dst (LoadL mem)));
9181 effect(KILL cr);
9182 ins_cost(125);
9183 format %{ "AND $dst.lo,$mem\n\t"
9184 "AND $dst.hi,$mem+4" %}
9185 opcode(0x23, 0x23);
9186 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9187 ins_pipe( ialu_reg_long_mem );
9188 %}
9189
9190 // Or Long Register with Register
9191 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9192 match(Set dst (OrL dst src));
9193 effect(KILL cr);
9194 format %{ "OR $dst.lo,$src.lo\n\t"
9195 "OR $dst.hi,$src.hi" %}
9196 opcode(0x0B,0x0B);
9197 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9198 ins_pipe( ialu_reg_reg_long );
9199 %}
9200
9201 // Or Long Register with Immediate
9202 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9203 match(Set dst (OrL dst src));
9204 effect(KILL cr);
9205 format %{ "OR $dst.lo,$src.lo\n\t"
9206 "OR $dst.hi,$src.hi" %}
9207 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9208 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9209 ins_pipe( ialu_reg_long );
9210 %}
9211
9212 // Or Long Register with Memory
9213 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9214 match(Set dst (OrL dst (LoadL mem)));
9215 effect(KILL cr);
9216 ins_cost(125);
9217 format %{ "OR $dst.lo,$mem\n\t"
9218 "OR $dst.hi,$mem+4" %}
9219 opcode(0x0B,0x0B);
9220 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9221 ins_pipe( ialu_reg_long_mem );
9222 %}
9223
9224 // Xor Long Register with Register
9225 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9226 match(Set dst (XorL dst src));
9227 effect(KILL cr);
9228 format %{ "XOR $dst.lo,$src.lo\n\t"
9229 "XOR $dst.hi,$src.hi" %}
9230 opcode(0x33,0x33);
9231 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9232 ins_pipe( ialu_reg_reg_long );
9233 %}
9234
9235 // Xor Long Register with Immediate -1
9236 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9237 match(Set dst (XorL dst imm));
9238 format %{ "NOT $dst.lo\n\t"
9239 "NOT $dst.hi" %}
9240 ins_encode %{
9241 __ notl($dst$$Register);
9242 __ notl(HIGH_FROM_LOW($dst$$Register));
9243 %}
9244 ins_pipe( ialu_reg_long );
9245 %}
9246
9247 // Xor Long Register with Immediate
9248 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9249 match(Set dst (XorL dst src));
9250 effect(KILL cr);
9251 format %{ "XOR $dst.lo,$src.lo\n\t"
9252 "XOR $dst.hi,$src.hi" %}
9253 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9254 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9255 ins_pipe( ialu_reg_long );
9256 %}
9257
9258 // Xor Long Register with Memory
9259 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9260 match(Set dst (XorL dst (LoadL mem)));
9261 effect(KILL cr);
9262 ins_cost(125);
9263 format %{ "XOR $dst.lo,$mem\n\t"
9264 "XOR $dst.hi,$mem+4" %}
9265 opcode(0x33,0x33);
9266 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9267 ins_pipe( ialu_reg_long_mem );
9268 %}
9269
9270 // Shift Left Long by 1
9271 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9272 predicate(UseNewLongLShift);
9273 match(Set dst (LShiftL dst cnt));
9274 effect(KILL cr);
9275 ins_cost(100);
9276 format %{ "ADD $dst.lo,$dst.lo\n\t"
9277 "ADC $dst.hi,$dst.hi" %}
9278 ins_encode %{
9279 __ addl($dst$$Register,$dst$$Register);
9280 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9281 %}
9282 ins_pipe( ialu_reg_long );
9283 %}
9284
9285 // Shift Left Long by 2
9286 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9287 predicate(UseNewLongLShift);
9288 match(Set dst (LShiftL dst cnt));
9289 effect(KILL cr);
9290 ins_cost(100);
9291 format %{ "ADD $dst.lo,$dst.lo\n\t"
9292 "ADC $dst.hi,$dst.hi\n\t"
9293 "ADD $dst.lo,$dst.lo\n\t"
9294 "ADC $dst.hi,$dst.hi" %}
9295 ins_encode %{
9296 __ addl($dst$$Register,$dst$$Register);
9297 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9298 __ addl($dst$$Register,$dst$$Register);
9299 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9300 %}
9301 ins_pipe( ialu_reg_long );
9302 %}
9303
9304 // Shift Left Long by 3
9305 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9306 predicate(UseNewLongLShift);
9307 match(Set dst (LShiftL dst cnt));
9308 effect(KILL cr);
9309 ins_cost(100);
9310 format %{ "ADD $dst.lo,$dst.lo\n\t"
9311 "ADC $dst.hi,$dst.hi\n\t"
9312 "ADD $dst.lo,$dst.lo\n\t"
9313 "ADC $dst.hi,$dst.hi\n\t"
9314 "ADD $dst.lo,$dst.lo\n\t"
9315 "ADC $dst.hi,$dst.hi" %}
9316 ins_encode %{
9317 __ addl($dst$$Register,$dst$$Register);
9318 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9319 __ addl($dst$$Register,$dst$$Register);
9320 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9321 __ addl($dst$$Register,$dst$$Register);
9322 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9323 %}
9324 ins_pipe( ialu_reg_long );
9325 %}
9326
9327 // Shift Left Long by 1-31
9328 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9329 match(Set dst (LShiftL dst cnt));
9330 effect(KILL cr);
9331 ins_cost(200);
9332 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9333 "SHL $dst.lo,$cnt" %}
9334 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9335 ins_encode( move_long_small_shift(dst,cnt) );
9336 ins_pipe( ialu_reg_long );
9337 %}
9338
9339 // Shift Left Long by 32-63
9340 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9341 match(Set dst (LShiftL dst cnt));
9342 effect(KILL cr);
9343 ins_cost(300);
9344 format %{ "MOV $dst.hi,$dst.lo\n"
9345 "\tSHL $dst.hi,$cnt-32\n"
9346 "\tXOR $dst.lo,$dst.lo" %}
9347 opcode(0xC1, 0x4); /* C1 /4 ib */
9348 ins_encode( move_long_big_shift_clr(dst,cnt) );
9349 ins_pipe( ialu_reg_long );
9350 %}
9351
9352 // Shift Left Long by variable
9353 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9354 match(Set dst (LShiftL dst shift));
9355 effect(KILL cr);
9356 ins_cost(500+200);
9357 size(17);
9358 format %{ "TEST $shift,32\n\t"
9359 "JEQ,s small\n\t"
9360 "MOV $dst.hi,$dst.lo\n\t"
9361 "XOR $dst.lo,$dst.lo\n"
9362 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9363 "SHL $dst.lo,$shift" %}
9364 ins_encode( shift_left_long( dst, shift ) );
9365 ins_pipe( pipe_slow );
9366 %}
9367
9368 // Shift Right Long by 1-31
9369 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9370 match(Set dst (URShiftL dst cnt));
9371 effect(KILL cr);
9372 ins_cost(200);
9373 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9374 "SHR $dst.hi,$cnt" %}
9375 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9376 ins_encode( move_long_small_shift(dst,cnt) );
9377 ins_pipe( ialu_reg_long );
9378 %}
9379
9380 // Shift Right Long by 32-63
9381 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9382 match(Set dst (URShiftL dst cnt));
9383 effect(KILL cr);
9384 ins_cost(300);
9385 format %{ "MOV $dst.lo,$dst.hi\n"
9386 "\tSHR $dst.lo,$cnt-32\n"
9387 "\tXOR $dst.hi,$dst.hi" %}
9388 opcode(0xC1, 0x5); /* C1 /5 ib */
9389 ins_encode( move_long_big_shift_clr(dst,cnt) );
9390 ins_pipe( ialu_reg_long );
9391 %}
9392
9393 // Shift Right Long by variable
9394 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9395 match(Set dst (URShiftL dst shift));
9396 effect(KILL cr);
9397 ins_cost(600);
9398 size(17);
9399 format %{ "TEST $shift,32\n\t"
9400 "JEQ,s small\n\t"
9401 "MOV $dst.lo,$dst.hi\n\t"
9402 "XOR $dst.hi,$dst.hi\n"
9403 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9404 "SHR $dst.hi,$shift" %}
9405 ins_encode( shift_right_long( dst, shift ) );
9406 ins_pipe( pipe_slow );
9407 %}
9408
9409 // Shift Right Long by 1-31
9410 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9411 match(Set dst (RShiftL dst cnt));
9412 effect(KILL cr);
9413 ins_cost(200);
9414 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9415 "SAR $dst.hi,$cnt" %}
9416 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9417 ins_encode( move_long_small_shift(dst,cnt) );
9418 ins_pipe( ialu_reg_long );
9419 %}
9420
9421 // Shift Right Long by 32-63
9422 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9423 match(Set dst (RShiftL dst cnt));
9424 effect(KILL cr);
9425 ins_cost(300);
9426 format %{ "MOV $dst.lo,$dst.hi\n"
9427 "\tSAR $dst.lo,$cnt-32\n"
9428 "\tSAR $dst.hi,31" %}
9429 opcode(0xC1, 0x7); /* C1 /7 ib */
9430 ins_encode( move_long_big_shift_sign(dst,cnt) );
9431 ins_pipe( ialu_reg_long );
9432 %}
9433
9434 // Shift Right arithmetic Long by variable
9435 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9436 match(Set dst (RShiftL dst shift));
9437 effect(KILL cr);
9438 ins_cost(600);
9439 size(18);
9440 format %{ "TEST $shift,32\n\t"
9441 "JEQ,s small\n\t"
9442 "MOV $dst.lo,$dst.hi\n\t"
9443 "SAR $dst.hi,31\n"
9444 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9445 "SAR $dst.hi,$shift" %}
9446 ins_encode( shift_right_arith_long( dst, shift ) );
9447 ins_pipe( pipe_slow );
9448 %}
9449
9450
9451 //----------Double Instructions------------------------------------------------
9452 // Double Math
9453
9454 // Compare & branch
9455
9456 // P6 version of float compare, sets condition codes in EFLAGS
9457 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9458 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9459 match(Set cr (CmpD src1 src2));
9460 effect(KILL rax);
9461 ins_cost(150);
9462 format %{ "FLD $src1\n\t"
9463 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9464 "JNP exit\n\t"
9465 "MOV ah,1 // saw a NaN, set CF\n\t"
9466 "SAHF\n"
9467 "exit:\tNOP // avoid branch to branch" %}
9468 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9469 ins_encode( Push_Reg_DPR(src1),
9470 OpcP, RegOpc(src2),
9471 cmpF_P6_fixup );
9472 ins_pipe( pipe_slow );
9473 %}
9474
9475 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9476 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9477 match(Set cr (CmpD src1 src2));
9478 ins_cost(150);
9479 format %{ "FLD $src1\n\t"
9480 "FUCOMIP ST,$src2 // P6 instruction" %}
9481 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9482 ins_encode( Push_Reg_DPR(src1),
9483 OpcP, RegOpc(src2));
9484 ins_pipe( pipe_slow );
9485 %}
9486
9487 // Compare & branch
9488 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9489 predicate(UseSSE<=1);
9490 match(Set cr (CmpD src1 src2));
9491 effect(KILL rax);
9492 ins_cost(200);
9493 format %{ "FLD $src1\n\t"
9494 "FCOMp $src2\n\t"
9495 "FNSTSW AX\n\t"
9496 "TEST AX,0x400\n\t"
9497 "JZ,s flags\n\t"
9498 "MOV AH,1\t# unordered treat as LT\n"
9499 "flags:\tSAHF" %}
9500 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9501 ins_encode( Push_Reg_DPR(src1),
9502 OpcP, RegOpc(src2),
9503 fpu_flags);
9504 ins_pipe( pipe_slow );
9505 %}
9506
9507 // Compare vs zero into -1,0,1
9508 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9509 predicate(UseSSE<=1);
9510 match(Set dst (CmpD3 src1 zero));
9511 effect(KILL cr, KILL rax);
9512 ins_cost(280);
9513 format %{ "FTSTD $dst,$src1" %}
9514 opcode(0xE4, 0xD9);
9515 ins_encode( Push_Reg_DPR(src1),
9516 OpcS, OpcP, PopFPU,
9517 CmpF_Result(dst));
9518 ins_pipe( pipe_slow );
9519 %}
9520
9521 // Compare into -1,0,1
9522 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9523 predicate(UseSSE<=1);
9524 match(Set dst (CmpD3 src1 src2));
9525 effect(KILL cr, KILL rax);
9526 ins_cost(300);
9527 format %{ "FCMPD $dst,$src1,$src2" %}
9528 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9529 ins_encode( Push_Reg_DPR(src1),
9530 OpcP, RegOpc(src2),
9531 CmpF_Result(dst));
9532 ins_pipe( pipe_slow );
9533 %}
9534
9535 // float compare and set condition codes in EFLAGS by XMM regs
9536 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9537 predicate(UseSSE>=2);
9538 match(Set cr (CmpD src1 src2));
9539 ins_cost(145);
9540 format %{ "UCOMISD $src1,$src2\n\t"
9541 "JNP,s exit\n\t"
9542 "PUSHF\t# saw NaN, set CF\n\t"
9543 "AND [rsp], #0xffffff2b\n\t"
9544 "POPF\n"
9545 "exit:" %}
9546 ins_encode %{
9547 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9548 emit_cmpfp_fixup(_masm);
9549 %}
9550 ins_pipe( pipe_slow );
9551 %}
9552
9553 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9554 predicate(UseSSE>=2);
9555 match(Set cr (CmpD src1 src2));
9556 ins_cost(100);
9557 format %{ "UCOMISD $src1,$src2" %}
9558 ins_encode %{
9559 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9560 %}
9561 ins_pipe( pipe_slow );
9562 %}
9563
9564 // float compare and set condition codes in EFLAGS by XMM regs
9565 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9566 predicate(UseSSE>=2);
9567 match(Set cr (CmpD src1 (LoadD src2)));
9568 ins_cost(145);
9569 format %{ "UCOMISD $src1,$src2\n\t"
9570 "JNP,s exit\n\t"
9571 "PUSHF\t# saw NaN, set CF\n\t"
9572 "AND [rsp], #0xffffff2b\n\t"
9573 "POPF\n"
9574 "exit:" %}
9575 ins_encode %{
9576 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9577 emit_cmpfp_fixup(_masm);
9578 %}
9579 ins_pipe( pipe_slow );
9580 %}
9581
9582 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9583 predicate(UseSSE>=2);
9584 match(Set cr (CmpD src1 (LoadD src2)));
9585 ins_cost(100);
9586 format %{ "UCOMISD $src1,$src2" %}
9587 ins_encode %{
9588 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9589 %}
9590 ins_pipe( pipe_slow );
9591 %}
9592
9593 // Compare into -1,0,1 in XMM
9594 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9595 predicate(UseSSE>=2);
9596 match(Set dst (CmpD3 src1 src2));
9597 effect(KILL cr);
9598 ins_cost(255);
9599 format %{ "UCOMISD $src1, $src2\n\t"
9600 "MOV $dst, #-1\n\t"
9601 "JP,s done\n\t"
9602 "JB,s done\n\t"
9603 "SETNE $dst\n\t"
9604 "MOVZB $dst, $dst\n"
9605 "done:" %}
9606 ins_encode %{
9607 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9608 emit_cmpfp3(_masm, $dst$$Register);
9609 %}
9610 ins_pipe( pipe_slow );
9611 %}
9612
9613 // Compare into -1,0,1 in XMM and memory
9614 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9615 predicate(UseSSE>=2);
9616 match(Set dst (CmpD3 src1 (LoadD src2)));
9617 effect(KILL cr);
9618 ins_cost(275);
9619 format %{ "UCOMISD $src1, $src2\n\t"
9620 "MOV $dst, #-1\n\t"
9621 "JP,s done\n\t"
9622 "JB,s done\n\t"
9623 "SETNE $dst\n\t"
9624 "MOVZB $dst, $dst\n"
9625 "done:" %}
9626 ins_encode %{
9627 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9628 emit_cmpfp3(_masm, $dst$$Register);
9629 %}
9630 ins_pipe( pipe_slow );
9631 %}
9632
9633
9634 instruct subDPR_reg(regDPR dst, regDPR src) %{
9635 predicate (UseSSE <=1);
9636 match(Set dst (SubD dst src));
9637
9638 format %{ "FLD $src\n\t"
9639 "DSUBp $dst,ST" %}
9640 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9641 ins_cost(150);
9642 ins_encode( Push_Reg_DPR(src),
9643 OpcP, RegOpc(dst) );
9644 ins_pipe( fpu_reg_reg );
9645 %}
9646
9647 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9648 predicate (UseSSE <=1);
9649 match(Set dst (RoundDouble (SubD src1 src2)));
9650 ins_cost(250);
9651
9652 format %{ "FLD $src2\n\t"
9653 "DSUB ST,$src1\n\t"
9654 "FSTP_D $dst\t# D-round" %}
9655 opcode(0xD8, 0x5);
9656 ins_encode( Push_Reg_DPR(src2),
9657 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9658 ins_pipe( fpu_mem_reg_reg );
9659 %}
9660
9661
9662 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9663 predicate (UseSSE <=1);
9664 match(Set dst (SubD dst (LoadD src)));
9665 ins_cost(150);
9666
9667 format %{ "FLD $src\n\t"
9668 "DSUBp $dst,ST" %}
9669 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9670 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9671 OpcP, RegOpc(dst) );
9672 ins_pipe( fpu_reg_mem );
9673 %}
9674
9675 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9676 predicate (UseSSE<=1);
9677 match(Set dst (AbsD src));
9678 ins_cost(100);
9679 format %{ "FABS" %}
9680 opcode(0xE1, 0xD9);
9681 ins_encode( OpcS, OpcP );
9682 ins_pipe( fpu_reg_reg );
9683 %}
9684
9685 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9686 predicate(UseSSE<=1);
9687 match(Set dst (NegD src));
9688 ins_cost(100);
9689 format %{ "FCHS" %}
9690 opcode(0xE0, 0xD9);
9691 ins_encode( OpcS, OpcP );
9692 ins_pipe( fpu_reg_reg );
9693 %}
9694
9695 instruct addDPR_reg(regDPR dst, regDPR src) %{
9696 predicate(UseSSE<=1);
9697 match(Set dst (AddD dst src));
9698 format %{ "FLD $src\n\t"
9699 "DADD $dst,ST" %}
9700 size(4);
9701 ins_cost(150);
9702 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9703 ins_encode( Push_Reg_DPR(src),
9704 OpcP, RegOpc(dst) );
9705 ins_pipe( fpu_reg_reg );
9706 %}
9707
9708
9709 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9710 predicate(UseSSE<=1);
9711 match(Set dst (RoundDouble (AddD src1 src2)));
9712 ins_cost(250);
9713
9714 format %{ "FLD $src2\n\t"
9715 "DADD ST,$src1\n\t"
9716 "FSTP_D $dst\t# D-round" %}
9717 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9718 ins_encode( Push_Reg_DPR(src2),
9719 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9720 ins_pipe( fpu_mem_reg_reg );
9721 %}
9722
9723
9724 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9725 predicate(UseSSE<=1);
9726 match(Set dst (AddD dst (LoadD src)));
9727 ins_cost(150);
9728
9729 format %{ "FLD $src\n\t"
9730 "DADDp $dst,ST" %}
9731 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9732 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9733 OpcP, RegOpc(dst) );
9734 ins_pipe( fpu_reg_mem );
9735 %}
9736
9737 // add-to-memory
9738 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9739 predicate(UseSSE<=1);
9740 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9741 ins_cost(150);
9742
9743 format %{ "FLD_D $dst\n\t"
9744 "DADD ST,$src\n\t"
9745 "FST_D $dst" %}
9746 opcode(0xDD, 0x0);
9747 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9748 Opcode(0xD8), RegOpc(src),
9749 set_instruction_start,
9750 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9751 ins_pipe( fpu_reg_mem );
9752 %}
9753
9754 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9755 predicate(UseSSE<=1);
9756 match(Set dst (AddD dst con));
9757 ins_cost(125);
9758 format %{ "FLD1\n\t"
9759 "DADDp $dst,ST" %}
9760 ins_encode %{
9761 __ fld1();
9762 __ faddp($dst$$reg);
9763 %}
9764 ins_pipe(fpu_reg);
9765 %}
9766
9767 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9768 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9769 match(Set dst (AddD dst con));
9770 ins_cost(200);
9771 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9772 "DADDp $dst,ST" %}
9773 ins_encode %{
9774 __ fld_d($constantaddress($con));
9775 __ faddp($dst$$reg);
9776 %}
9777 ins_pipe(fpu_reg_mem);
9778 %}
9779
9780 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9781 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9782 match(Set dst (RoundDouble (AddD src con)));
9783 ins_cost(200);
9784 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9785 "DADD ST,$src\n\t"
9786 "FSTP_D $dst\t# D-round" %}
9787 ins_encode %{
9788 __ fld_d($constantaddress($con));
9789 __ fadd($src$$reg);
9790 __ fstp_d(Address(rsp, $dst$$disp));
9791 %}
9792 ins_pipe(fpu_mem_reg_con);
9793 %}
9794
9795 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9796 predicate(UseSSE<=1);
9797 match(Set dst (MulD dst src));
9798 format %{ "FLD $src\n\t"
9799 "DMULp $dst,ST" %}
9800 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9801 ins_cost(150);
9802 ins_encode( Push_Reg_DPR(src),
9803 OpcP, RegOpc(dst) );
9804 ins_pipe( fpu_reg_reg );
9805 %}
9806
9807 // Strict FP instruction biases argument before multiply then
9808 // biases result to avoid double rounding of subnormals.
9809 //
9810 // scale arg1 by multiplying arg1 by 2^(-15360)
9811 // load arg2
9812 // multiply scaled arg1 by arg2
9813 // rescale product by 2^(15360)
9814 //
9815 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9816 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9817 match(Set dst (MulD dst src));
9818 ins_cost(1); // Select this instruction for all strict FP double multiplies
9819
9820 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9821 "DMULp $dst,ST\n\t"
9822 "FLD $src\n\t"
9823 "DMULp $dst,ST\n\t"
9824 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9825 "DMULp $dst,ST\n\t" %}
9826 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9827 ins_encode( strictfp_bias1(dst),
9828 Push_Reg_DPR(src),
9829 OpcP, RegOpc(dst),
9830 strictfp_bias2(dst) );
9831 ins_pipe( fpu_reg_reg );
9832 %}
9833
9834 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9835 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9836 match(Set dst (MulD dst con));
9837 ins_cost(200);
9838 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9839 "DMULp $dst,ST" %}
9840 ins_encode %{
9841 __ fld_d($constantaddress($con));
9842 __ fmulp($dst$$reg);
9843 %}
9844 ins_pipe(fpu_reg_mem);
9845 %}
9846
9847
9848 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9849 predicate( UseSSE<=1 );
9850 match(Set dst (MulD dst (LoadD src)));
9851 ins_cost(200);
9852 format %{ "FLD_D $src\n\t"
9853 "DMULp $dst,ST" %}
9854 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9855 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9856 OpcP, RegOpc(dst) );
9857 ins_pipe( fpu_reg_mem );
9858 %}
9859
9860 //
9861 // Cisc-alternate to reg-reg multiply
9862 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9863 predicate( UseSSE<=1 );
9864 match(Set dst (MulD src (LoadD mem)));
9865 ins_cost(250);
9866 format %{ "FLD_D $mem\n\t"
9867 "DMUL ST,$src\n\t"
9868 "FSTP_D $dst" %}
9869 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9870 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9871 OpcReg_FPR(src),
9872 Pop_Reg_DPR(dst) );
9873 ins_pipe( fpu_reg_reg_mem );
9874 %}
9875
9876
9877 // MACRO3 -- addDPR a mulDPR
9878 // This instruction is a '2-address' instruction in that the result goes
9879 // back to src2. This eliminates a move from the macro; possibly the
9880 // register allocator will have to add it back (and maybe not).
9881 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9882 predicate( UseSSE<=1 );
9883 match(Set src2 (AddD (MulD src0 src1) src2));
9884 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9885 "DMUL ST,$src1\n\t"
9886 "DADDp $src2,ST" %}
9887 ins_cost(250);
9888 opcode(0xDD); /* LoadD DD /0 */
9889 ins_encode( Push_Reg_FPR(src0),
9890 FMul_ST_reg(src1),
9891 FAddP_reg_ST(src2) );
9892 ins_pipe( fpu_reg_reg_reg );
9893 %}
9894
9895
9896 // MACRO3 -- subDPR a mulDPR
9897 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9898 predicate( UseSSE<=1 );
9899 match(Set src2 (SubD (MulD src0 src1) src2));
9900 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9901 "DMUL ST,$src1\n\t"
9902 "DSUBRp $src2,ST" %}
9903 ins_cost(250);
9904 ins_encode( Push_Reg_FPR(src0),
9905 FMul_ST_reg(src1),
9906 Opcode(0xDE), Opc_plus(0xE0,src2));
9907 ins_pipe( fpu_reg_reg_reg );
9908 %}
9909
9910
9911 instruct divDPR_reg(regDPR dst, regDPR src) %{
9912 predicate( UseSSE<=1 );
9913 match(Set dst (DivD dst src));
9914
9915 format %{ "FLD $src\n\t"
9916 "FDIVp $dst,ST" %}
9917 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9918 ins_cost(150);
9919 ins_encode( Push_Reg_DPR(src),
9920 OpcP, RegOpc(dst) );
9921 ins_pipe( fpu_reg_reg );
9922 %}
9923
9924 // Strict FP instruction biases argument before division then
9925 // biases result, to avoid double rounding of subnormals.
9926 //
9927 // scale dividend by multiplying dividend by 2^(-15360)
9928 // load divisor
9929 // divide scaled dividend by divisor
9930 // rescale quotient by 2^(15360)
9931 //
9932 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9933 predicate (UseSSE<=1);
9934 match(Set dst (DivD dst src));
9935 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9936 ins_cost(01);
9937
9938 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9939 "DMULp $dst,ST\n\t"
9940 "FLD $src\n\t"
9941 "FDIVp $dst,ST\n\t"
9942 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9943 "DMULp $dst,ST\n\t" %}
9944 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9945 ins_encode( strictfp_bias1(dst),
9946 Push_Reg_DPR(src),
9947 OpcP, RegOpc(dst),
9948 strictfp_bias2(dst) );
9949 ins_pipe( fpu_reg_reg );
9950 %}
9951
9952 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9953 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9954 match(Set dst (RoundDouble (DivD src1 src2)));
9955
9956 format %{ "FLD $src1\n\t"
9957 "FDIV ST,$src2\n\t"
9958 "FSTP_D $dst\t# D-round" %}
9959 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9960 ins_encode( Push_Reg_DPR(src1),
9961 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9962 ins_pipe( fpu_mem_reg_reg );
9963 %}
9964
9965
9966 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9967 predicate(UseSSE<=1);
9968 match(Set dst (ModD dst src));
9969 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9970
9971 format %{ "DMOD $dst,$src" %}
9972 ins_cost(250);
9973 ins_encode(Push_Reg_Mod_DPR(dst, src),
9974 emitModDPR(),
9975 Push_Result_Mod_DPR(src),
9976 Pop_Reg_DPR(dst));
9977 ins_pipe( pipe_slow );
9978 %}
9979
9980 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9981 predicate(UseSSE>=2);
9982 match(Set dst (ModD src0 src1));
9983 effect(KILL rax, KILL cr);
9984
9985 format %{ "SUB ESP,8\t # DMOD\n"
9986 "\tMOVSD [ESP+0],$src1\n"
9987 "\tFLD_D [ESP+0]\n"
9988 "\tMOVSD [ESP+0],$src0\n"
9989 "\tFLD_D [ESP+0]\n"
9990 "loop:\tFPREM\n"
9991 "\tFWAIT\n"
9992 "\tFNSTSW AX\n"
9993 "\tSAHF\n"
9994 "\tJP loop\n"
9995 "\tFSTP_D [ESP+0]\n"
9996 "\tMOVSD $dst,[ESP+0]\n"
9997 "\tADD ESP,8\n"
9998 "\tFSTP ST0\t # Restore FPU Stack"
9999 %}
10000 ins_cost(250);
10001 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10002 ins_pipe( pipe_slow );
10003 %}
10004
10005 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10006 predicate (UseSSE<=1);
10007 match(Set dst (SinD src));
10008 ins_cost(1800);
10009 format %{ "DSIN $dst" %}
10010 opcode(0xD9, 0xFE);
10011 ins_encode( OpcP, OpcS );
10012 ins_pipe( pipe_slow );
10013 %}
10014
10015 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10016 predicate (UseSSE>=2);
10017 match(Set dst (SinD dst));
10018 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10019 ins_cost(1800);
10020 format %{ "DSIN $dst" %}
10021 opcode(0xD9, 0xFE);
10022 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10023 ins_pipe( pipe_slow );
10024 %}
10025
10026 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10027 predicate (UseSSE<=1);
10028 match(Set dst (CosD src));
10029 ins_cost(1800);
10030 format %{ "DCOS $dst" %}
10031 opcode(0xD9, 0xFF);
10032 ins_encode( OpcP, OpcS );
10033 ins_pipe( pipe_slow );
10034 %}
10035
10036 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10037 predicate (UseSSE>=2);
10038 match(Set dst (CosD dst));
10039 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10040 ins_cost(1800);
10041 format %{ "DCOS $dst" %}
10042 opcode(0xD9, 0xFF);
10043 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10044 ins_pipe( pipe_slow );
10045 %}
10046
10047 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10048 predicate (UseSSE<=1);
10049 match(Set dst(TanD src));
10050 format %{ "DTAN $dst" %}
10051 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10052 Opcode(0xDD), Opcode(0xD8)); // fstp st
10053 ins_pipe( pipe_slow );
10054 %}
10055
10056 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10057 predicate (UseSSE>=2);
10058 match(Set dst(TanD dst));
10059 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10060 format %{ "DTAN $dst" %}
10061 ins_encode( Push_SrcD(dst),
10062 Opcode(0xD9), Opcode(0xF2), // fptan
10063 Opcode(0xDD), Opcode(0xD8), // fstp st
10064 Push_ResultD(dst) );
10065 ins_pipe( pipe_slow );
10066 %}
10067
10068 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10069 predicate (UseSSE<=1);
10070 match(Set dst(AtanD dst src));
10071 format %{ "DATA $dst,$src" %}
10072 opcode(0xD9, 0xF3);
10073 ins_encode( Push_Reg_DPR(src),
10074 OpcP, OpcS, RegOpc(dst) );
10075 ins_pipe( pipe_slow );
10076 %}
10077
10078 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10079 predicate (UseSSE>=2);
10080 match(Set dst(AtanD dst src));
10081 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10082 format %{ "DATA $dst,$src" %}
10083 opcode(0xD9, 0xF3);
10084 ins_encode( Push_SrcD(src),
10085 OpcP, OpcS, Push_ResultD(dst) );
10086 ins_pipe( pipe_slow );
10087 %}
10088
10089 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10090 predicate (UseSSE<=1);
10091 match(Set dst (SqrtD src));
10092 format %{ "DSQRT $dst,$src" %}
10093 opcode(0xFA, 0xD9);
10094 ins_encode( Push_Reg_DPR(src),
10095 OpcS, OpcP, Pop_Reg_DPR(dst) );
10096 ins_pipe( pipe_slow );
10097 %}
10098
10099 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10100 predicate (UseSSE<=1);
10101 match(Set Y (PowD X Y)); // Raise X to the Yth power
10102 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10103 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10104 ins_encode %{
10105 __ subptr(rsp, 8);
10106 __ fld_s($X$$reg - 1);
10107 __ fast_pow();
10108 __ addptr(rsp, 8);
10109 %}
10110 ins_pipe( pipe_slow );
10111 %}
10112
10113 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10114 predicate (UseSSE>=2);
10115 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10116 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10117 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10118 ins_encode %{
10119 __ subptr(rsp, 8);
10120 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10121 __ fld_d(Address(rsp, 0));
10122 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10123 __ fld_d(Address(rsp, 0));
10124 __ fast_pow();
10125 __ fstp_d(Address(rsp, 0));
10126 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10127 __ addptr(rsp, 8);
10128 %}
10129 ins_pipe( pipe_slow );
10130 %}
10131
10132
10133 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10134 predicate (UseSSE<=1);
10135 match(Set dpr1 (ExpD dpr1));
10136 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10137 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10138 ins_encode %{
10139 __ fast_exp();
10140 %}
10141 ins_pipe( pipe_slow );
10142 %}
10143
10144 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10145 predicate (UseSSE>=2);
10146 match(Set dst (ExpD src));
10147 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10148 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10149 ins_encode %{
10150 __ subptr(rsp, 8);
10151 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10152 __ fld_d(Address(rsp, 0));
10153 __ fast_exp();
10154 __ fstp_d(Address(rsp, 0));
10155 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10156 __ addptr(rsp, 8);
10157 %}
10158 ins_pipe( pipe_slow );
10159 %}
10160
10161 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10162 predicate (UseSSE<=1);
10163 // The source Double operand on FPU stack
10164 match(Set dst (Log10D src));
10165 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10166 // fxch ; swap ST(0) with ST(1)
10167 // fyl2x ; compute log_10(2) * log_2(x)
10168 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10169 "FXCH \n\t"
10170 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10171 %}
10172 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10173 Opcode(0xD9), Opcode(0xC9), // fxch
10174 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10175
10176 ins_pipe( pipe_slow );
10177 %}
10178
10179 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10180 predicate (UseSSE>=2);
10181 effect(KILL cr);
10182 match(Set dst (Log10D src));
10183 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10184 // fyl2x ; compute log_10(2) * log_2(x)
10185 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10186 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10187 %}
10188 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10189 Push_SrcD(src),
10190 Opcode(0xD9), Opcode(0xF1), // fyl2x
10191 Push_ResultD(dst));
10192
10193 ins_pipe( pipe_slow );
10194 %}
10195
10196 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10197 predicate (UseSSE<=1);
10198 // The source Double operand on FPU stack
10199 match(Set dst (LogD src));
10200 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10201 // fxch ; swap ST(0) with ST(1)
10202 // fyl2x ; compute log_e(2) * log_2(x)
10203 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10204 "FXCH \n\t"
10205 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10206 %}
10207 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10208 Opcode(0xD9), Opcode(0xC9), // fxch
10209 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10210
10211 ins_pipe( pipe_slow );
10212 %}
10213
10214 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10215 predicate (UseSSE>=2);
10216 effect(KILL cr);
10217 // The source and result Double operands in XMM registers
10218 match(Set dst (LogD src));
10219 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10220 // fyl2x ; compute log_e(2) * log_2(x)
10221 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10222 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10223 %}
10224 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10225 Push_SrcD(src),
10226 Opcode(0xD9), Opcode(0xF1), // fyl2x
10227 Push_ResultD(dst));
10228 ins_pipe( pipe_slow );
10229 %}
10230
10231 //-------------Float Instructions-------------------------------
10232 // Float Math
10233
10234 // Code for float compare:
10235 // fcompp();
10236 // fwait(); fnstsw_ax();
10237 // sahf();
10238 // movl(dst, unordered_result);
10239 // jcc(Assembler::parity, exit);
10240 // movl(dst, less_result);
10241 // jcc(Assembler::below, exit);
10242 // movl(dst, equal_result);
10243 // jcc(Assembler::equal, exit);
10244 // movl(dst, greater_result);
10245 // exit:
10246
10247 // P6 version of float compare, sets condition codes in EFLAGS
10248 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10249 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10250 match(Set cr (CmpF src1 src2));
10251 effect(KILL rax);
10252 ins_cost(150);
10253 format %{ "FLD $src1\n\t"
10254 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10255 "JNP exit\n\t"
10256 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10257 "SAHF\n"
10258 "exit:\tNOP // avoid branch to branch" %}
10259 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10260 ins_encode( Push_Reg_DPR(src1),
10261 OpcP, RegOpc(src2),
10262 cmpF_P6_fixup );
10263 ins_pipe( pipe_slow );
10264 %}
10265
10266 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10267 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10268 match(Set cr (CmpF src1 src2));
10269 ins_cost(100);
10270 format %{ "FLD $src1\n\t"
10271 "FUCOMIP ST,$src2 // P6 instruction" %}
10272 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10273 ins_encode( Push_Reg_DPR(src1),
10274 OpcP, RegOpc(src2));
10275 ins_pipe( pipe_slow );
10276 %}
10277
10278
10279 // Compare & branch
10280 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10281 predicate(UseSSE == 0);
10282 match(Set cr (CmpF src1 src2));
10283 effect(KILL rax);
10284 ins_cost(200);
10285 format %{ "FLD $src1\n\t"
10286 "FCOMp $src2\n\t"
10287 "FNSTSW AX\n\t"
10288 "TEST AX,0x400\n\t"
10289 "JZ,s flags\n\t"
10290 "MOV AH,1\t# unordered treat as LT\n"
10291 "flags:\tSAHF" %}
10292 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10293 ins_encode( Push_Reg_DPR(src1),
10294 OpcP, RegOpc(src2),
10295 fpu_flags);
10296 ins_pipe( pipe_slow );
10297 %}
10298
10299 // Compare vs zero into -1,0,1
10300 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10301 predicate(UseSSE == 0);
10302 match(Set dst (CmpF3 src1 zero));
10303 effect(KILL cr, KILL rax);
10304 ins_cost(280);
10305 format %{ "FTSTF $dst,$src1" %}
10306 opcode(0xE4, 0xD9);
10307 ins_encode( Push_Reg_DPR(src1),
10308 OpcS, OpcP, PopFPU,
10309 CmpF_Result(dst));
10310 ins_pipe( pipe_slow );
10311 %}
10312
10313 // Compare into -1,0,1
10314 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10315 predicate(UseSSE == 0);
10316 match(Set dst (CmpF3 src1 src2));
10317 effect(KILL cr, KILL rax);
10318 ins_cost(300);
10319 format %{ "FCMPF $dst,$src1,$src2" %}
10320 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10321 ins_encode( Push_Reg_DPR(src1),
10322 OpcP, RegOpc(src2),
10323 CmpF_Result(dst));
10324 ins_pipe( pipe_slow );
10325 %}
10326
10327 // float compare and set condition codes in EFLAGS by XMM regs
10328 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10329 predicate(UseSSE>=1);
10330 match(Set cr (CmpF src1 src2));
10331 ins_cost(145);
10332 format %{ "UCOMISS $src1,$src2\n\t"
10333 "JNP,s exit\n\t"
10334 "PUSHF\t# saw NaN, set CF\n\t"
10335 "AND [rsp], #0xffffff2b\n\t"
10336 "POPF\n"
10337 "exit:" %}
10338 ins_encode %{
10339 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10340 emit_cmpfp_fixup(_masm);
10341 %}
10342 ins_pipe( pipe_slow );
10343 %}
10344
10345 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10346 predicate(UseSSE>=1);
10347 match(Set cr (CmpF src1 src2));
10348 ins_cost(100);
10349 format %{ "UCOMISS $src1,$src2" %}
10350 ins_encode %{
10351 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10352 %}
10353 ins_pipe( pipe_slow );
10354 %}
10355
10356 // float compare and set condition codes in EFLAGS by XMM regs
10357 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10358 predicate(UseSSE>=1);
10359 match(Set cr (CmpF src1 (LoadF src2)));
10360 ins_cost(165);
10361 format %{ "UCOMISS $src1,$src2\n\t"
10362 "JNP,s exit\n\t"
10363 "PUSHF\t# saw NaN, set CF\n\t"
10364 "AND [rsp], #0xffffff2b\n\t"
10365 "POPF\n"
10366 "exit:" %}
10367 ins_encode %{
10368 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10369 emit_cmpfp_fixup(_masm);
10370 %}
10371 ins_pipe( pipe_slow );
10372 %}
10373
10374 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10375 predicate(UseSSE>=1);
10376 match(Set cr (CmpF src1 (LoadF src2)));
10377 ins_cost(100);
10378 format %{ "UCOMISS $src1,$src2" %}
10379 ins_encode %{
10380 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10381 %}
10382 ins_pipe( pipe_slow );
10383 %}
10384
10385 // Compare into -1,0,1 in XMM
10386 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10387 predicate(UseSSE>=1);
10388 match(Set dst (CmpF3 src1 src2));
10389 effect(KILL cr);
10390 ins_cost(255);
10391 format %{ "UCOMISS $src1, $src2\n\t"
10392 "MOV $dst, #-1\n\t"
10393 "JP,s done\n\t"
10394 "JB,s done\n\t"
10395 "SETNE $dst\n\t"
10396 "MOVZB $dst, $dst\n"
10397 "done:" %}
10398 ins_encode %{
10399 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10400 emit_cmpfp3(_masm, $dst$$Register);
10401 %}
10402 ins_pipe( pipe_slow );
10403 %}
10404
10405 // Compare into -1,0,1 in XMM and memory
10406 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10407 predicate(UseSSE>=1);
10408 match(Set dst (CmpF3 src1 (LoadF src2)));
10409 effect(KILL cr);
10410 ins_cost(275);
10411 format %{ "UCOMISS $src1, $src2\n\t"
10412 "MOV $dst, #-1\n\t"
10413 "JP,s done\n\t"
10414 "JB,s done\n\t"
10415 "SETNE $dst\n\t"
10416 "MOVZB $dst, $dst\n"
10417 "done:" %}
10418 ins_encode %{
10419 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10420 emit_cmpfp3(_masm, $dst$$Register);
10421 %}
10422 ins_pipe( pipe_slow );
10423 %}
10424
10425 // Spill to obtain 24-bit precision
10426 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10427 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10428 match(Set dst (SubF src1 src2));
10429
10430 format %{ "FSUB $dst,$src1 - $src2" %}
10431 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10432 ins_encode( Push_Reg_FPR(src1),
10433 OpcReg_FPR(src2),
10434 Pop_Mem_FPR(dst) );
10435 ins_pipe( fpu_mem_reg_reg );
10436 %}
10437 //
10438 // This instruction does not round to 24-bits
10439 instruct subFPR_reg(regFPR dst, regFPR src) %{
10440 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10441 match(Set dst (SubF dst src));
10442
10443 format %{ "FSUB $dst,$src" %}
10444 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10445 ins_encode( Push_Reg_FPR(src),
10446 OpcP, RegOpc(dst) );
10447 ins_pipe( fpu_reg_reg );
10448 %}
10449
10450 // Spill to obtain 24-bit precision
10451 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10452 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10453 match(Set dst (AddF src1 src2));
10454
10455 format %{ "FADD $dst,$src1,$src2" %}
10456 opcode(0xD8, 0x0); /* D8 C0+i */
10457 ins_encode( Push_Reg_FPR(src2),
10458 OpcReg_FPR(src1),
10459 Pop_Mem_FPR(dst) );
10460 ins_pipe( fpu_mem_reg_reg );
10461 %}
10462 //
10463 // This instruction does not round to 24-bits
10464 instruct addFPR_reg(regFPR dst, regFPR src) %{
10465 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10466 match(Set dst (AddF dst src));
10467
10468 format %{ "FLD $src\n\t"
10469 "FADDp $dst,ST" %}
10470 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10471 ins_encode( Push_Reg_FPR(src),
10472 OpcP, RegOpc(dst) );
10473 ins_pipe( fpu_reg_reg );
10474 %}
10475
10476 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10477 predicate(UseSSE==0);
10478 match(Set dst (AbsF src));
10479 ins_cost(100);
10480 format %{ "FABS" %}
10481 opcode(0xE1, 0xD9);
10482 ins_encode( OpcS, OpcP );
10483 ins_pipe( fpu_reg_reg );
10484 %}
10485
10486 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10487 predicate(UseSSE==0);
10488 match(Set dst (NegF src));
10489 ins_cost(100);
10490 format %{ "FCHS" %}
10491 opcode(0xE0, 0xD9);
10492 ins_encode( OpcS, OpcP );
10493 ins_pipe( fpu_reg_reg );
10494 %}
10495
10496 // Cisc-alternate to addFPR_reg
10497 // Spill to obtain 24-bit precision
10498 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10499 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10500 match(Set dst (AddF src1 (LoadF src2)));
10501
10502 format %{ "FLD $src2\n\t"
10503 "FADD ST,$src1\n\t"
10504 "FSTP_S $dst" %}
10505 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10506 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10507 OpcReg_FPR(src1),
10508 Pop_Mem_FPR(dst) );
10509 ins_pipe( fpu_mem_reg_mem );
10510 %}
10511 //
10512 // Cisc-alternate to addFPR_reg
10513 // This instruction does not round to 24-bits
10514 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10515 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10516 match(Set dst (AddF dst (LoadF src)));
10517
10518 format %{ "FADD $dst,$src" %}
10519 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10521 OpcP, RegOpc(dst) );
10522 ins_pipe( fpu_reg_mem );
10523 %}
10524
10525 // // Following two instructions for _222_mpegaudio
10526 // Spill to obtain 24-bit precision
10527 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10528 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10529 match(Set dst (AddF src1 src2));
10530
10531 format %{ "FADD $dst,$src1,$src2" %}
10532 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10533 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10534 OpcReg_FPR(src2),
10535 Pop_Mem_FPR(dst) );
10536 ins_pipe( fpu_mem_reg_mem );
10537 %}
10538
10539 // Cisc-spill variant
10540 // Spill to obtain 24-bit precision
10541 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10542 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10543 match(Set dst (AddF src1 (LoadF src2)));
10544
10545 format %{ "FADD $dst,$src1,$src2 cisc" %}
10546 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10547 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10548 set_instruction_start,
10549 OpcP, RMopc_Mem(secondary,src1),
10550 Pop_Mem_FPR(dst) );
10551 ins_pipe( fpu_mem_mem_mem );
10552 %}
10553
10554 // Spill to obtain 24-bit precision
10555 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10556 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10557 match(Set dst (AddF src1 src2));
10558
10559 format %{ "FADD $dst,$src1,$src2" %}
10560 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10561 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10562 set_instruction_start,
10563 OpcP, RMopc_Mem(secondary,src1),
10564 Pop_Mem_FPR(dst) );
10565 ins_pipe( fpu_mem_mem_mem );
10566 %}
10567
10568
10569 // Spill to obtain 24-bit precision
10570 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10571 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10572 match(Set dst (AddF src con));
10573 format %{ "FLD $src\n\t"
10574 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10575 "FSTP_S $dst" %}
10576 ins_encode %{
10577 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10578 __ fadd_s($constantaddress($con));
10579 __ fstp_s(Address(rsp, $dst$$disp));
10580 %}
10581 ins_pipe(fpu_mem_reg_con);
10582 %}
10583 //
10584 // This instruction does not round to 24-bits
10585 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10586 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10587 match(Set dst (AddF src con));
10588 format %{ "FLD $src\n\t"
10589 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10590 "FSTP $dst" %}
10591 ins_encode %{
10592 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10593 __ fadd_s($constantaddress($con));
10594 __ fstp_d($dst$$reg);
10595 %}
10596 ins_pipe(fpu_reg_reg_con);
10597 %}
10598
10599 // Spill to obtain 24-bit precision
10600 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10601 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10602 match(Set dst (MulF src1 src2));
10603
10604 format %{ "FLD $src1\n\t"
10605 "FMUL $src2\n\t"
10606 "FSTP_S $dst" %}
10607 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10608 ins_encode( Push_Reg_FPR(src1),
10609 OpcReg_FPR(src2),
10610 Pop_Mem_FPR(dst) );
10611 ins_pipe( fpu_mem_reg_reg );
10612 %}
10613 //
10614 // This instruction does not round to 24-bits
10615 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10616 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10617 match(Set dst (MulF src1 src2));
10618
10619 format %{ "FLD $src1\n\t"
10620 "FMUL $src2\n\t"
10621 "FSTP_S $dst" %}
10622 opcode(0xD8, 0x1); /* D8 C8+i */
10623 ins_encode( Push_Reg_FPR(src2),
10624 OpcReg_FPR(src1),
10625 Pop_Reg_FPR(dst) );
10626 ins_pipe( fpu_reg_reg_reg );
10627 %}
10628
10629
10630 // Spill to obtain 24-bit precision
10631 // Cisc-alternate to reg-reg multiply
10632 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10633 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10634 match(Set dst (MulF src1 (LoadF src2)));
10635
10636 format %{ "FLD_S $src2\n\t"
10637 "FMUL $src1\n\t"
10638 "FSTP_S $dst" %}
10639 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10640 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10641 OpcReg_FPR(src1),
10642 Pop_Mem_FPR(dst) );
10643 ins_pipe( fpu_mem_reg_mem );
10644 %}
10645 //
10646 // This instruction does not round to 24-bits
10647 // Cisc-alternate to reg-reg multiply
10648 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10649 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10650 match(Set dst (MulF src1 (LoadF src2)));
10651
10652 format %{ "FMUL $dst,$src1,$src2" %}
10653 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10654 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10655 OpcReg_FPR(src1),
10656 Pop_Reg_FPR(dst) );
10657 ins_pipe( fpu_reg_reg_mem );
10658 %}
10659
10660 // Spill to obtain 24-bit precision
10661 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10662 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10663 match(Set dst (MulF src1 src2));
10664
10665 format %{ "FMUL $dst,$src1,$src2" %}
10666 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10667 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10668 set_instruction_start,
10669 OpcP, RMopc_Mem(secondary,src1),
10670 Pop_Mem_FPR(dst) );
10671 ins_pipe( fpu_mem_mem_mem );
10672 %}
10673
10674 // Spill to obtain 24-bit precision
10675 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10676 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10677 match(Set dst (MulF src con));
10678
10679 format %{ "FLD $src\n\t"
10680 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10681 "FSTP_S $dst" %}
10682 ins_encode %{
10683 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10684 __ fmul_s($constantaddress($con));
10685 __ fstp_s(Address(rsp, $dst$$disp));
10686 %}
10687 ins_pipe(fpu_mem_reg_con);
10688 %}
10689 //
10690 // This instruction does not round to 24-bits
10691 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10692 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10693 match(Set dst (MulF src con));
10694
10695 format %{ "FLD $src\n\t"
10696 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10697 "FSTP $dst" %}
10698 ins_encode %{
10699 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10700 __ fmul_s($constantaddress($con));
10701 __ fstp_d($dst$$reg);
10702 %}
10703 ins_pipe(fpu_reg_reg_con);
10704 %}
10705
10706
10707 //
10708 // MACRO1 -- subsume unshared load into mulFPR
10709 // This instruction does not round to 24-bits
10710 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10711 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10712 match(Set dst (MulF (LoadF mem1) src));
10713
10714 format %{ "FLD $mem1 ===MACRO1===\n\t"
10715 "FMUL ST,$src\n\t"
10716 "FSTP $dst" %}
10717 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10718 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10719 OpcReg_FPR(src),
10720 Pop_Reg_FPR(dst) );
10721 ins_pipe( fpu_reg_reg_mem );
10722 %}
10723 //
10724 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10725 // This instruction does not round to 24-bits
10726 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10727 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10728 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10729 ins_cost(95);
10730
10731 format %{ "FLD $mem1 ===MACRO2===\n\t"
10732 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10733 "FADD ST,$src2\n\t"
10734 "FSTP $dst" %}
10735 opcode(0xD9); /* LoadF D9 /0 */
10736 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10737 FMul_ST_reg(src1),
10738 FAdd_ST_reg(src2),
10739 Pop_Reg_FPR(dst) );
10740 ins_pipe( fpu_reg_mem_reg_reg );
10741 %}
10742
10743 // MACRO3 -- addFPR a mulFPR
10744 // This instruction does not round to 24-bits. It is a '2-address'
10745 // instruction in that the result goes back to src2. This eliminates
10746 // a move from the macro; possibly the register allocator will have
10747 // to add it back (and maybe not).
10748 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10749 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10750 match(Set src2 (AddF (MulF src0 src1) src2));
10751
10752 format %{ "FLD $src0 ===MACRO3===\n\t"
10753 "FMUL ST,$src1\n\t"
10754 "FADDP $src2,ST" %}
10755 opcode(0xD9); /* LoadF D9 /0 */
10756 ins_encode( Push_Reg_FPR(src0),
10757 FMul_ST_reg(src1),
10758 FAddP_reg_ST(src2) );
10759 ins_pipe( fpu_reg_reg_reg );
10760 %}
10761
10762 // MACRO4 -- divFPR subFPR
10763 // This instruction does not round to 24-bits
10764 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10765 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10766 match(Set dst (DivF (SubF src2 src1) src3));
10767
10768 format %{ "FLD $src2 ===MACRO4===\n\t"
10769 "FSUB ST,$src1\n\t"
10770 "FDIV ST,$src3\n\t"
10771 "FSTP $dst" %}
10772 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10773 ins_encode( Push_Reg_FPR(src2),
10774 subFPR_divFPR_encode(src1,src3),
10775 Pop_Reg_FPR(dst) );
10776 ins_pipe( fpu_reg_reg_reg_reg );
10777 %}
10778
10779 // Spill to obtain 24-bit precision
10780 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10781 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10782 match(Set dst (DivF src1 src2));
10783
10784 format %{ "FDIV $dst,$src1,$src2" %}
10785 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10786 ins_encode( Push_Reg_FPR(src1),
10787 OpcReg_FPR(src2),
10788 Pop_Mem_FPR(dst) );
10789 ins_pipe( fpu_mem_reg_reg );
10790 %}
10791 //
10792 // This instruction does not round to 24-bits
10793 instruct divFPR_reg(regFPR dst, regFPR src) %{
10794 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10795 match(Set dst (DivF dst src));
10796
10797 format %{ "FDIV $dst,$src" %}
10798 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10799 ins_encode( Push_Reg_FPR(src),
10800 OpcP, RegOpc(dst) );
10801 ins_pipe( fpu_reg_reg );
10802 %}
10803
10804
10805 // Spill to obtain 24-bit precision
10806 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10807 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10808 match(Set dst (ModF src1 src2));
10809 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10810
10811 format %{ "FMOD $dst,$src1,$src2" %}
10812 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10813 emitModDPR(),
10814 Push_Result_Mod_DPR(src2),
10815 Pop_Mem_FPR(dst));
10816 ins_pipe( pipe_slow );
10817 %}
10818 //
10819 // This instruction does not round to 24-bits
10820 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10821 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10822 match(Set dst (ModF dst src));
10823 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10824
10825 format %{ "FMOD $dst,$src" %}
10826 ins_encode(Push_Reg_Mod_DPR(dst, src),
10827 emitModDPR(),
10828 Push_Result_Mod_DPR(src),
10829 Pop_Reg_FPR(dst));
10830 ins_pipe( pipe_slow );
10831 %}
10832
10833 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10834 predicate(UseSSE>=1);
10835 match(Set dst (ModF src0 src1));
10836 effect(KILL rax, KILL cr);
10837 format %{ "SUB ESP,4\t # FMOD\n"
10838 "\tMOVSS [ESP+0],$src1\n"
10839 "\tFLD_S [ESP+0]\n"
10840 "\tMOVSS [ESP+0],$src0\n"
10841 "\tFLD_S [ESP+0]\n"
10842 "loop:\tFPREM\n"
10843 "\tFWAIT\n"
10844 "\tFNSTSW AX\n"
10845 "\tSAHF\n"
10846 "\tJP loop\n"
10847 "\tFSTP_S [ESP+0]\n"
10848 "\tMOVSS $dst,[ESP+0]\n"
10849 "\tADD ESP,4\n"
10850 "\tFSTP ST0\t # Restore FPU Stack"
10851 %}
10852 ins_cost(250);
10853 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10854 ins_pipe( pipe_slow );
10855 %}
10856
10857
10858 //----------Arithmetic Conversion Instructions---------------------------------
10859 // The conversions operations are all Alpha sorted. Please keep it that way!
10860
10861 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10862 predicate(UseSSE==0);
10863 match(Set dst (RoundFloat src));
10864 ins_cost(125);
10865 format %{ "FST_S $dst,$src\t# F-round" %}
10866 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10867 ins_pipe( fpu_mem_reg );
10868 %}
10869
10870 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10871 predicate(UseSSE<=1);
10872 match(Set dst (RoundDouble src));
10873 ins_cost(125);
10874 format %{ "FST_D $dst,$src\t# D-round" %}
10875 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10876 ins_pipe( fpu_mem_reg );
10877 %}
10878
10879 // Force rounding to 24-bit precision and 6-bit exponent
10880 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10881 predicate(UseSSE==0);
10882 match(Set dst (ConvD2F src));
10883 format %{ "FST_S $dst,$src\t# F-round" %}
10884 expand %{
10885 roundFloat_mem_reg(dst,src);
10886 %}
10887 %}
10888
10889 // Force rounding to 24-bit precision and 6-bit exponent
10890 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10891 predicate(UseSSE==1);
10892 match(Set dst (ConvD2F src));
10893 effect( KILL cr );
10894 format %{ "SUB ESP,4\n\t"
10895 "FST_S [ESP],$src\t# F-round\n\t"
10896 "MOVSS $dst,[ESP]\n\t"
10897 "ADD ESP,4" %}
10898 ins_encode %{
10899 __ subptr(rsp, 4);
10900 if ($src$$reg != FPR1L_enc) {
10901 __ fld_s($src$$reg-1);
10902 __ fstp_s(Address(rsp, 0));
10903 } else {
10904 __ fst_s(Address(rsp, 0));
10905 }
10906 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10907 __ addptr(rsp, 4);
10908 %}
10909 ins_pipe( pipe_slow );
10910 %}
10911
10912 // Force rounding double precision to single precision
10913 instruct convD2F_reg(regF dst, regD src) %{
10914 predicate(UseSSE>=2);
10915 match(Set dst (ConvD2F src));
10916 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10917 ins_encode %{
10918 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10919 %}
10920 ins_pipe( pipe_slow );
10921 %}
10922
10923 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10924 predicate(UseSSE==0);
10925 match(Set dst (ConvF2D src));
10926 format %{ "FST_S $dst,$src\t# D-round" %}
10927 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10928 ins_pipe( fpu_reg_reg );
10929 %}
10930
10931 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10932 predicate(UseSSE==1);
10933 match(Set dst (ConvF2D src));
10934 format %{ "FST_D $dst,$src\t# D-round" %}
10935 expand %{
10936 roundDouble_mem_reg(dst,src);
10937 %}
10938 %}
10939
10940 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10941 predicate(UseSSE==1);
10942 match(Set dst (ConvF2D src));
10943 effect( KILL cr );
10944 format %{ "SUB ESP,4\n\t"
10945 "MOVSS [ESP] $src\n\t"
10946 "FLD_S [ESP]\n\t"
10947 "ADD ESP,4\n\t"
10948 "FSTP $dst\t# D-round" %}
10949 ins_encode %{
10950 __ subptr(rsp, 4);
10951 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10952 __ fld_s(Address(rsp, 0));
10953 __ addptr(rsp, 4);
10954 __ fstp_d($dst$$reg);
10955 %}
10956 ins_pipe( pipe_slow );
10957 %}
10958
10959 instruct convF2D_reg(regD dst, regF src) %{
10960 predicate(UseSSE>=2);
10961 match(Set dst (ConvF2D src));
10962 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10963 ins_encode %{
10964 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10965 %}
10966 ins_pipe( pipe_slow );
10967 %}
10968
10969 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10970 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10971 predicate(UseSSE<=1);
10972 match(Set dst (ConvD2I src));
10973 effect( KILL tmp, KILL cr );
10974 format %{ "FLD $src\t# Convert double to int \n\t"
10975 "FLDCW trunc mode\n\t"
10976 "SUB ESP,4\n\t"
10977 "FISTp [ESP + #0]\n\t"
10978 "FLDCW std/24-bit mode\n\t"
10979 "POP EAX\n\t"
10980 "CMP EAX,0x80000000\n\t"
10981 "JNE,s fast\n\t"
10982 "FLD_D $src\n\t"
10983 "CALL d2i_wrapper\n"
10984 "fast:" %}
10985 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10986 ins_pipe( pipe_slow );
10987 %}
10988
10989 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10990 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10991 predicate(UseSSE>=2);
10992 match(Set dst (ConvD2I src));
10993 effect( KILL tmp, KILL cr );
10994 format %{ "CVTTSD2SI $dst, $src\n\t"
10995 "CMP $dst,0x80000000\n\t"
10996 "JNE,s fast\n\t"
10997 "SUB ESP, 8\n\t"
10998 "MOVSD [ESP], $src\n\t"
10999 "FLD_D [ESP]\n\t"
11000 "ADD ESP, 8\n\t"
11001 "CALL d2i_wrapper\n"
11002 "fast:" %}
11003 ins_encode %{
11004 Label fast;
11005 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11006 __ cmpl($dst$$Register, 0x80000000);
11007 __ jccb(Assembler::notEqual, fast);
11008 __ subptr(rsp, 8);
11009 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11010 __ fld_d(Address(rsp, 0));
11011 __ addptr(rsp, 8);
11012 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11013 __ bind(fast);
11014 %}
11015 ins_pipe( pipe_slow );
11016 %}
11017
11018 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11019 predicate(UseSSE<=1);
11020 match(Set dst (ConvD2L src));
11021 effect( KILL cr );
11022 format %{ "FLD $src\t# Convert double to long\n\t"
11023 "FLDCW trunc mode\n\t"
11024 "SUB ESP,8\n\t"
11025 "FISTp [ESP + #0]\n\t"
11026 "FLDCW std/24-bit mode\n\t"
11027 "POP EAX\n\t"
11028 "POP EDX\n\t"
11029 "CMP EDX,0x80000000\n\t"
11030 "JNE,s fast\n\t"
11031 "TEST EAX,EAX\n\t"
11032 "JNE,s fast\n\t"
11033 "FLD $src\n\t"
11034 "CALL d2l_wrapper\n"
11035 "fast:" %}
11036 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11037 ins_pipe( pipe_slow );
11038 %}
11039
11040 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11041 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11042 predicate (UseSSE>=2);
11043 match(Set dst (ConvD2L src));
11044 effect( KILL cr );
11045 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11046 "MOVSD [ESP],$src\n\t"
11047 "FLD_D [ESP]\n\t"
11048 "FLDCW trunc mode\n\t"
11049 "FISTp [ESP + #0]\n\t"
11050 "FLDCW std/24-bit mode\n\t"
11051 "POP EAX\n\t"
11052 "POP EDX\n\t"
11053 "CMP EDX,0x80000000\n\t"
11054 "JNE,s fast\n\t"
11055 "TEST EAX,EAX\n\t"
11056 "JNE,s fast\n\t"
11057 "SUB ESP,8\n\t"
11058 "MOVSD [ESP],$src\n\t"
11059 "FLD_D [ESP]\n\t"
11060 "ADD ESP,8\n\t"
11061 "CALL d2l_wrapper\n"
11062 "fast:" %}
11063 ins_encode %{
11064 Label fast;
11065 __ subptr(rsp, 8);
11066 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11067 __ fld_d(Address(rsp, 0));
11068 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11069 __ fistp_d(Address(rsp, 0));
11070 // Restore the rounding mode, mask the exception
11071 if (Compile::current()->in_24_bit_fp_mode()) {
11072 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11073 } else {
11074 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11075 }
11076 // Load the converted long, adjust CPU stack
11077 __ pop(rax);
11078 __ pop(rdx);
11079 __ cmpl(rdx, 0x80000000);
11080 __ jccb(Assembler::notEqual, fast);
11081 __ testl(rax, rax);
11082 __ jccb(Assembler::notEqual, fast);
11083 __ subptr(rsp, 8);
11084 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11085 __ fld_d(Address(rsp, 0));
11086 __ addptr(rsp, 8);
11087 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11088 __ bind(fast);
11089 %}
11090 ins_pipe( pipe_slow );
11091 %}
11092
11093 // Convert a double to an int. Java semantics require we do complex
11094 // manglations in the corner cases. So we set the rounding mode to
11095 // 'zero', store the darned double down as an int, and reset the
11096 // rounding mode to 'nearest'. The hardware stores a flag value down
11097 // if we would overflow or converted a NAN; we check for this and
11098 // and go the slow path if needed.
11099 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11100 predicate(UseSSE==0);
11101 match(Set dst (ConvF2I src));
11102 effect( KILL tmp, KILL cr );
11103 format %{ "FLD $src\t# Convert float to int \n\t"
11104 "FLDCW trunc mode\n\t"
11105 "SUB ESP,4\n\t"
11106 "FISTp [ESP + #0]\n\t"
11107 "FLDCW std/24-bit mode\n\t"
11108 "POP EAX\n\t"
11109 "CMP EAX,0x80000000\n\t"
11110 "JNE,s fast\n\t"
11111 "FLD $src\n\t"
11112 "CALL d2i_wrapper\n"
11113 "fast:" %}
11114 // DPR2I_encoding works for FPR2I
11115 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11116 ins_pipe( pipe_slow );
11117 %}
11118
11119 // Convert a float in xmm to an int reg.
11120 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11121 predicate(UseSSE>=1);
11122 match(Set dst (ConvF2I src));
11123 effect( KILL tmp, KILL cr );
11124 format %{ "CVTTSS2SI $dst, $src\n\t"
11125 "CMP $dst,0x80000000\n\t"
11126 "JNE,s fast\n\t"
11127 "SUB ESP, 4\n\t"
11128 "MOVSS [ESP], $src\n\t"
11129 "FLD [ESP]\n\t"
11130 "ADD ESP, 4\n\t"
11131 "CALL d2i_wrapper\n"
11132 "fast:" %}
11133 ins_encode %{
11134 Label fast;
11135 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11136 __ cmpl($dst$$Register, 0x80000000);
11137 __ jccb(Assembler::notEqual, fast);
11138 __ subptr(rsp, 4);
11139 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11140 __ fld_s(Address(rsp, 0));
11141 __ addptr(rsp, 4);
11142 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11143 __ bind(fast);
11144 %}
11145 ins_pipe( pipe_slow );
11146 %}
11147
11148 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11149 predicate(UseSSE==0);
11150 match(Set dst (ConvF2L src));
11151 effect( KILL cr );
11152 format %{ "FLD $src\t# Convert float to long\n\t"
11153 "FLDCW trunc mode\n\t"
11154 "SUB ESP,8\n\t"
11155 "FISTp [ESP + #0]\n\t"
11156 "FLDCW std/24-bit mode\n\t"
11157 "POP EAX\n\t"
11158 "POP EDX\n\t"
11159 "CMP EDX,0x80000000\n\t"
11160 "JNE,s fast\n\t"
11161 "TEST EAX,EAX\n\t"
11162 "JNE,s fast\n\t"
11163 "FLD $src\n\t"
11164 "CALL d2l_wrapper\n"
11165 "fast:" %}
11166 // DPR2L_encoding works for FPR2L
11167 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11168 ins_pipe( pipe_slow );
11169 %}
11170
11171 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11172 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11173 predicate (UseSSE>=1);
11174 match(Set dst (ConvF2L src));
11175 effect( KILL cr );
11176 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11177 "MOVSS [ESP],$src\n\t"
11178 "FLD_S [ESP]\n\t"
11179 "FLDCW trunc mode\n\t"
11180 "FISTp [ESP + #0]\n\t"
11181 "FLDCW std/24-bit mode\n\t"
11182 "POP EAX\n\t"
11183 "POP EDX\n\t"
11184 "CMP EDX,0x80000000\n\t"
11185 "JNE,s fast\n\t"
11186 "TEST EAX,EAX\n\t"
11187 "JNE,s fast\n\t"
11188 "SUB ESP,4\t# Convert float to long\n\t"
11189 "MOVSS [ESP],$src\n\t"
11190 "FLD_S [ESP]\n\t"
11191 "ADD ESP,4\n\t"
11192 "CALL d2l_wrapper\n"
11193 "fast:" %}
11194 ins_encode %{
11195 Label fast;
11196 __ subptr(rsp, 8);
11197 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11198 __ fld_s(Address(rsp, 0));
11199 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11200 __ fistp_d(Address(rsp, 0));
11201 // Restore the rounding mode, mask the exception
11202 if (Compile::current()->in_24_bit_fp_mode()) {
11203 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11204 } else {
11205 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11206 }
11207 // Load the converted long, adjust CPU stack
11208 __ pop(rax);
11209 __ pop(rdx);
11210 __ cmpl(rdx, 0x80000000);
11211 __ jccb(Assembler::notEqual, fast);
11212 __ testl(rax, rax);
11213 __ jccb(Assembler::notEqual, fast);
11214 __ subptr(rsp, 4);
11215 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11216 __ fld_s(Address(rsp, 0));
11217 __ addptr(rsp, 4);
11218 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11219 __ bind(fast);
11220 %}
11221 ins_pipe( pipe_slow );
11222 %}
11223
11224 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11225 predicate( UseSSE<=1 );
11226 match(Set dst (ConvI2D src));
11227 format %{ "FILD $src\n\t"
11228 "FSTP $dst" %}
11229 opcode(0xDB, 0x0); /* DB /0 */
11230 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11231 ins_pipe( fpu_reg_mem );
11232 %}
11233
11234 instruct convI2D_reg(regD dst, rRegI src) %{
11235 predicate( UseSSE>=2 && !UseXmmI2D );
11236 match(Set dst (ConvI2D src));
11237 format %{ "CVTSI2SD $dst,$src" %}
11238 ins_encode %{
11239 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11240 %}
11241 ins_pipe( pipe_slow );
11242 %}
11243
11244 instruct convI2D_mem(regD dst, memory mem) %{
11245 predicate( UseSSE>=2 );
11246 match(Set dst (ConvI2D (LoadI mem)));
11247 format %{ "CVTSI2SD $dst,$mem" %}
11248 ins_encode %{
11249 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11250 %}
11251 ins_pipe( pipe_slow );
11252 %}
11253
11254 instruct convXI2D_reg(regD dst, rRegI src)
11255 %{
11256 predicate( UseSSE>=2 && UseXmmI2D );
11257 match(Set dst (ConvI2D src));
11258
11259 format %{ "MOVD $dst,$src\n\t"
11260 "CVTDQ2PD $dst,$dst\t# i2d" %}
11261 ins_encode %{
11262 __ movdl($dst$$XMMRegister, $src$$Register);
11263 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11264 %}
11265 ins_pipe(pipe_slow); // XXX
11266 %}
11267
11268 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11269 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11270 match(Set dst (ConvI2D (LoadI mem)));
11271 format %{ "FILD $mem\n\t"
11272 "FSTP $dst" %}
11273 opcode(0xDB); /* DB /0 */
11274 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11275 Pop_Reg_DPR(dst));
11276 ins_pipe( fpu_reg_mem );
11277 %}
11278
11279 // Convert a byte to a float; no rounding step needed.
11280 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11281 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11282 match(Set dst (ConvI2F src));
11283 format %{ "FILD $src\n\t"
11284 "FSTP $dst" %}
11285
11286 opcode(0xDB, 0x0); /* DB /0 */
11287 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11288 ins_pipe( fpu_reg_mem );
11289 %}
11290
11291 // In 24-bit mode, force exponent rounding by storing back out
11292 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11293 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11294 match(Set dst (ConvI2F src));
11295 ins_cost(200);
11296 format %{ "FILD $src\n\t"
11297 "FSTP_S $dst" %}
11298 opcode(0xDB, 0x0); /* DB /0 */
11299 ins_encode( Push_Mem_I(src),
11300 Pop_Mem_FPR(dst));
11301 ins_pipe( fpu_mem_mem );
11302 %}
11303
11304 // In 24-bit mode, force exponent rounding by storing back out
11305 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11306 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11307 match(Set dst (ConvI2F (LoadI mem)));
11308 ins_cost(200);
11309 format %{ "FILD $mem\n\t"
11310 "FSTP_S $dst" %}
11311 opcode(0xDB); /* DB /0 */
11312 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11313 Pop_Mem_FPR(dst));
11314 ins_pipe( fpu_mem_mem );
11315 %}
11316
11317 // This instruction does not round to 24-bits
11318 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11319 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11320 match(Set dst (ConvI2F src));
11321 format %{ "FILD $src\n\t"
11322 "FSTP $dst" %}
11323 opcode(0xDB, 0x0); /* DB /0 */
11324 ins_encode( Push_Mem_I(src),
11325 Pop_Reg_FPR(dst));
11326 ins_pipe( fpu_reg_mem );
11327 %}
11328
11329 // This instruction does not round to 24-bits
11330 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11331 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11332 match(Set dst (ConvI2F (LoadI mem)));
11333 format %{ "FILD $mem\n\t"
11334 "FSTP $dst" %}
11335 opcode(0xDB); /* DB /0 */
11336 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11337 Pop_Reg_FPR(dst));
11338 ins_pipe( fpu_reg_mem );
11339 %}
11340
11341 // Convert an int to a float in xmm; no rounding step needed.
11342 instruct convI2F_reg(regF dst, rRegI src) %{
11343 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11344 match(Set dst (ConvI2F src));
11345 format %{ "CVTSI2SS $dst, $src" %}
11346 ins_encode %{
11347 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11348 %}
11349 ins_pipe( pipe_slow );
11350 %}
11351
11352 instruct convXI2F_reg(regF dst, rRegI src)
11353 %{
11354 predicate( UseSSE>=2 && UseXmmI2F );
11355 match(Set dst (ConvI2F src));
11356
11357 format %{ "MOVD $dst,$src\n\t"
11358 "CVTDQ2PS $dst,$dst\t# i2f" %}
11359 ins_encode %{
11360 __ movdl($dst$$XMMRegister, $src$$Register);
11361 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11362 %}
11363 ins_pipe(pipe_slow); // XXX
11364 %}
11365
11366 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11367 match(Set dst (ConvI2L src));
11368 effect(KILL cr);
11369 ins_cost(375);
11370 format %{ "MOV $dst.lo,$src\n\t"
11371 "MOV $dst.hi,$src\n\t"
11372 "SAR $dst.hi,31" %}
11373 ins_encode(convert_int_long(dst,src));
11374 ins_pipe( ialu_reg_reg_long );
11375 %}
11376
11377 // Zero-extend convert int to long
11378 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11379 match(Set dst (AndL (ConvI2L src) mask) );
11380 effect( KILL flags );
11381 ins_cost(250);
11382 format %{ "MOV $dst.lo,$src\n\t"
11383 "XOR $dst.hi,$dst.hi" %}
11384 opcode(0x33); // XOR
11385 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11386 ins_pipe( ialu_reg_reg_long );
11387 %}
11388
11389 // Zero-extend long
11390 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11391 match(Set dst (AndL src mask) );
11392 effect( KILL flags );
11393 ins_cost(250);
11394 format %{ "MOV $dst.lo,$src.lo\n\t"
11395 "XOR $dst.hi,$dst.hi\n\t" %}
11396 opcode(0x33); // XOR
11397 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11398 ins_pipe( ialu_reg_reg_long );
11399 %}
11400
11401 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11402 predicate (UseSSE<=1);
11403 match(Set dst (ConvL2D src));
11404 effect( KILL cr );
11405 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11406 "PUSH $src.lo\n\t"
11407 "FILD ST,[ESP + #0]\n\t"
11408 "ADD ESP,8\n\t"
11409 "FSTP_D $dst\t# D-round" %}
11410 opcode(0xDF, 0x5); /* DF /5 */
11411 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11412 ins_pipe( pipe_slow );
11413 %}
11414
11415 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11416 predicate (UseSSE>=2);
11417 match(Set dst (ConvL2D src));
11418 effect( KILL cr );
11419 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11420 "PUSH $src.lo\n\t"
11421 "FILD_D [ESP]\n\t"
11422 "FSTP_D [ESP]\n\t"
11423 "MOVSD $dst,[ESP]\n\t"
11424 "ADD ESP,8" %}
11425 opcode(0xDF, 0x5); /* DF /5 */
11426 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11427 ins_pipe( pipe_slow );
11428 %}
11429
11430 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11431 predicate (UseSSE>=1);
11432 match(Set dst (ConvL2F src));
11433 effect( KILL cr );
11434 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11435 "PUSH $src.lo\n\t"
11436 "FILD_D [ESP]\n\t"
11437 "FSTP_S [ESP]\n\t"
11438 "MOVSS $dst,[ESP]\n\t"
11439 "ADD ESP,8" %}
11440 opcode(0xDF, 0x5); /* DF /5 */
11441 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11442 ins_pipe( pipe_slow );
11443 %}
11444
11445 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11446 match(Set dst (ConvL2F src));
11447 effect( KILL cr );
11448 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11449 "PUSH $src.lo\n\t"
11450 "FILD ST,[ESP + #0]\n\t"
11451 "ADD ESP,8\n\t"
11452 "FSTP_S $dst\t# F-round" %}
11453 opcode(0xDF, 0x5); /* DF /5 */
11454 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11455 ins_pipe( pipe_slow );
11456 %}
11457
11458 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11459 match(Set dst (ConvL2I src));
11460 effect( DEF dst, USE src );
11461 format %{ "MOV $dst,$src.lo" %}
11462 ins_encode(enc_CopyL_Lo(dst,src));
11463 ins_pipe( ialu_reg_reg );
11464 %}
11465
11466
11467 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11468 match(Set dst (MoveF2I src));
11469 effect( DEF dst, USE src );
11470 ins_cost(100);
11471 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11472 ins_encode %{
11473 __ movl($dst$$Register, Address(rsp, $src$$disp));
11474 %}
11475 ins_pipe( ialu_reg_mem );
11476 %}
11477
11478 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11479 predicate(UseSSE==0);
11480 match(Set dst (MoveF2I src));
11481 effect( DEF dst, USE src );
11482
11483 ins_cost(125);
11484 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11485 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11486 ins_pipe( fpu_mem_reg );
11487 %}
11488
11489 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11490 predicate(UseSSE>=1);
11491 match(Set dst (MoveF2I src));
11492 effect( DEF dst, USE src );
11493
11494 ins_cost(95);
11495 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11496 ins_encode %{
11497 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11498 %}
11499 ins_pipe( pipe_slow );
11500 %}
11501
11502 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11503 predicate(UseSSE>=2);
11504 match(Set dst (MoveF2I src));
11505 effect( DEF dst, USE src );
11506 ins_cost(85);
11507 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11508 ins_encode %{
11509 __ movdl($dst$$Register, $src$$XMMRegister);
11510 %}
11511 ins_pipe( pipe_slow );
11512 %}
11513
11514 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11515 match(Set dst (MoveI2F src));
11516 effect( DEF dst, USE src );
11517
11518 ins_cost(100);
11519 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11520 ins_encode %{
11521 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11522 %}
11523 ins_pipe( ialu_mem_reg );
11524 %}
11525
11526
11527 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11528 predicate(UseSSE==0);
11529 match(Set dst (MoveI2F src));
11530 effect(DEF dst, USE src);
11531
11532 ins_cost(125);
11533 format %{ "FLD_S $src\n\t"
11534 "FSTP $dst\t# MoveI2F_stack_reg" %}
11535 opcode(0xD9); /* D9 /0, FLD m32real */
11536 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11537 Pop_Reg_FPR(dst) );
11538 ins_pipe( fpu_reg_mem );
11539 %}
11540
11541 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11542 predicate(UseSSE>=1);
11543 match(Set dst (MoveI2F src));
11544 effect( DEF dst, USE src );
11545
11546 ins_cost(95);
11547 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11548 ins_encode %{
11549 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11550 %}
11551 ins_pipe( pipe_slow );
11552 %}
11553
11554 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11555 predicate(UseSSE>=2);
11556 match(Set dst (MoveI2F src));
11557 effect( DEF dst, USE src );
11558
11559 ins_cost(85);
11560 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11561 ins_encode %{
11562 __ movdl($dst$$XMMRegister, $src$$Register);
11563 %}
11564 ins_pipe( pipe_slow );
11565 %}
11566
11567 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11568 match(Set dst (MoveD2L src));
11569 effect(DEF dst, USE src);
11570
11571 ins_cost(250);
11572 format %{ "MOV $dst.lo,$src\n\t"
11573 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11574 opcode(0x8B, 0x8B);
11575 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11576 ins_pipe( ialu_mem_long_reg );
11577 %}
11578
11579 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11580 predicate(UseSSE<=1);
11581 match(Set dst (MoveD2L src));
11582 effect(DEF dst, USE src);
11583
11584 ins_cost(125);
11585 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11586 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11587 ins_pipe( fpu_mem_reg );
11588 %}
11589
11590 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11591 predicate(UseSSE>=2);
11592 match(Set dst (MoveD2L src));
11593 effect(DEF dst, USE src);
11594 ins_cost(95);
11595 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11596 ins_encode %{
11597 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11598 %}
11599 ins_pipe( pipe_slow );
11600 %}
11601
11602 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11603 predicate(UseSSE>=2);
11604 match(Set dst (MoveD2L src));
11605 effect(DEF dst, USE src, TEMP tmp);
11606 ins_cost(85);
11607 format %{ "MOVD $dst.lo,$src\n\t"
11608 "PSHUFLW $tmp,$src,0x4E\n\t"
11609 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11610 ins_encode %{
11611 __ movdl($dst$$Register, $src$$XMMRegister);
11612 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11613 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11614 %}
11615 ins_pipe( pipe_slow );
11616 %}
11617
11618 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11619 match(Set dst (MoveL2D src));
11620 effect(DEF dst, USE src);
11621
11622 ins_cost(200);
11623 format %{ "MOV $dst,$src.lo\n\t"
11624 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11625 opcode(0x89, 0x89);
11626 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11627 ins_pipe( ialu_mem_long_reg );
11628 %}
11629
11630
11631 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11632 predicate(UseSSE<=1);
11633 match(Set dst (MoveL2D src));
11634 effect(DEF dst, USE src);
11635 ins_cost(125);
11636
11637 format %{ "FLD_D $src\n\t"
11638 "FSTP $dst\t# MoveL2D_stack_reg" %}
11639 opcode(0xDD); /* DD /0, FLD m64real */
11640 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11641 Pop_Reg_DPR(dst) );
11642 ins_pipe( fpu_reg_mem );
11643 %}
11644
11645
11646 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11647 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11648 match(Set dst (MoveL2D src));
11649 effect(DEF dst, USE src);
11650
11651 ins_cost(95);
11652 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11653 ins_encode %{
11654 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11655 %}
11656 ins_pipe( pipe_slow );
11657 %}
11658
11659 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11660 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11661 match(Set dst (MoveL2D src));
11662 effect(DEF dst, USE src);
11663
11664 ins_cost(95);
11665 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11666 ins_encode %{
11667 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11668 %}
11669 ins_pipe( pipe_slow );
11670 %}
11671
11672 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11673 predicate(UseSSE>=2);
11674 match(Set dst (MoveL2D src));
11675 effect(TEMP dst, USE src, TEMP tmp);
11676 ins_cost(85);
11677 format %{ "MOVD $dst,$src.lo\n\t"
11678 "MOVD $tmp,$src.hi\n\t"
11679 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11680 ins_encode %{
11681 __ movdl($dst$$XMMRegister, $src$$Register);
11682 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11683 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11684 %}
11685 ins_pipe( pipe_slow );
11686 %}
11687
11688
11689 // =======================================================================
11690 // fast clearing of an array
11691 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11692 predicate(!UseFastStosb);
11693 match(Set dummy (ClearArray cnt base));
11694 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11695 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11696 "SHL ECX,1\t# Convert doublewords to words\n\t"
11697 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11698 ins_encode %{
11699 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11700 %}
11701 ins_pipe( pipe_slow );
11702 %}
11703
11704 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11705 predicate(UseFastStosb);
11706 match(Set dummy (ClearArray cnt base));
11707 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11708 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11709 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11710 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11711 ins_encode %{
11712 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11713 %}
11714 ins_pipe( pipe_slow );
11715 %}
11716
11717 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11718 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11719 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11720 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11721
11722 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11723 ins_encode %{
11724 __ string_compare($str1$$Register, $str2$$Register,
11725 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11726 $tmp1$$XMMRegister);
11727 %}
11728 ins_pipe( pipe_slow );
11729 %}
11730
11731 // fast string equals
11732 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11733 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11734 match(Set result (StrEquals (Binary str1 str2) cnt));
11735 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11736
11737 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11738 ins_encode %{
11739 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11740 $cnt$$Register, $result$$Register, $tmp3$$Register,
11741 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11742 %}
11743 ins_pipe( pipe_slow );
11744 %}
11745
11746 // fast search of substring with known size.
11747 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11748 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11749 predicate(UseSSE42Intrinsics);
11750 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11751 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11752
11753 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11754 ins_encode %{
11755 int icnt2 = (int)$int_cnt2$$constant;
11756 if (icnt2 >= 8) {
11757 // IndexOf for constant substrings with size >= 8 elements
11758 // which don't need to be loaded through stack.
11759 __ string_indexofC8($str1$$Register, $str2$$Register,
11760 $cnt1$$Register, $cnt2$$Register,
11761 icnt2, $result$$Register,
11762 $vec$$XMMRegister, $tmp$$Register);
11763 } else {
11764 // Small strings are loaded through stack if they cross page boundary.
11765 __ string_indexof($str1$$Register, $str2$$Register,
11766 $cnt1$$Register, $cnt2$$Register,
11767 icnt2, $result$$Register,
11768 $vec$$XMMRegister, $tmp$$Register);
11769 }
11770 %}
11771 ins_pipe( pipe_slow );
11772 %}
11773
11774 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11775 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11776 predicate(UseSSE42Intrinsics);
11777 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11778 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11779
11780 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11781 ins_encode %{
11782 __ string_indexof($str1$$Register, $str2$$Register,
11783 $cnt1$$Register, $cnt2$$Register,
11784 (-1), $result$$Register,
11785 $vec$$XMMRegister, $tmp$$Register);
11786 %}
11787 ins_pipe( pipe_slow );
11788 %}
11789
11790 // fast array equals
11791 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11792 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11793 %{
11794 match(Set result (AryEq ary1 ary2));
11795 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11796 //ins_cost(300);
11797
11798 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11799 ins_encode %{
11800 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11801 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11802 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11803 %}
11804 ins_pipe( pipe_slow );
11805 %}
11806
11807 // encode char[] to byte[] in ISO_8859_1
11808 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11809 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11810 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11811 match(Set result (EncodeISOArray src (Binary dst len)));
11812 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11813
11814 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11815 ins_encode %{
11816 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11817 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11818 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11819 %}
11820 ins_pipe( pipe_slow );
11821 %}
11822
11823
11824 //----------Control Flow Instructions------------------------------------------
11825 // Signed compare Instructions
11826 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11827 match(Set cr (CmpI op1 op2));
11828 effect( DEF cr, USE op1, USE op2 );
11829 format %{ "CMP $op1,$op2" %}
11830 opcode(0x3B); /* Opcode 3B /r */
11831 ins_encode( OpcP, RegReg( op1, op2) );
11832 ins_pipe( ialu_cr_reg_reg );
11833 %}
11834
11835 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11836 match(Set cr (CmpI op1 op2));
11837 effect( DEF cr, USE op1 );
11838 format %{ "CMP $op1,$op2" %}
11839 opcode(0x81,0x07); /* Opcode 81 /7 */
11840 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11841 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11842 ins_pipe( ialu_cr_reg_imm );
11843 %}
11844
11845 // Cisc-spilled version of cmpI_eReg
11846 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11847 match(Set cr (CmpI op1 (LoadI op2)));
11848
11849 format %{ "CMP $op1,$op2" %}
11850 ins_cost(500);
11851 opcode(0x3B); /* Opcode 3B /r */
11852 ins_encode( OpcP, RegMem( op1, op2) );
11853 ins_pipe( ialu_cr_reg_mem );
11854 %}
11855
11856 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11857 match(Set cr (CmpI src zero));
11858 effect( DEF cr, USE src );
11859
11860 format %{ "TEST $src,$src" %}
11861 opcode(0x85);
11862 ins_encode( OpcP, RegReg( src, src ) );
11863 ins_pipe( ialu_cr_reg_imm );
11864 %}
11865
11866 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11867 match(Set cr (CmpI (AndI src con) zero));
11868
11869 format %{ "TEST $src,$con" %}
11870 opcode(0xF7,0x00);
11871 ins_encode( OpcP, RegOpc(src), Con32(con) );
11872 ins_pipe( ialu_cr_reg_imm );
11873 %}
11874
11875 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11876 match(Set cr (CmpI (AndI src mem) zero));
11877
11878 format %{ "TEST $src,$mem" %}
11879 opcode(0x85);
11880 ins_encode( OpcP, RegMem( src, mem ) );
11881 ins_pipe( ialu_cr_reg_mem );
11882 %}
11883
11884 // Unsigned compare Instructions; really, same as signed except they
11885 // produce an eFlagsRegU instead of eFlagsReg.
11886 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11887 match(Set cr (CmpU op1 op2));
11888
11889 format %{ "CMPu $op1,$op2" %}
11890 opcode(0x3B); /* Opcode 3B /r */
11891 ins_encode( OpcP, RegReg( op1, op2) );
11892 ins_pipe( ialu_cr_reg_reg );
11893 %}
11894
11895 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11896 match(Set cr (CmpU op1 op2));
11897
11898 format %{ "CMPu $op1,$op2" %}
11899 opcode(0x81,0x07); /* Opcode 81 /7 */
11900 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11901 ins_pipe( ialu_cr_reg_imm );
11902 %}
11903
11904 // // Cisc-spilled version of cmpU_eReg
11905 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11906 match(Set cr (CmpU op1 (LoadI op2)));
11907
11908 format %{ "CMPu $op1,$op2" %}
11909 ins_cost(500);
11910 opcode(0x3B); /* Opcode 3B /r */
11911 ins_encode( OpcP, RegMem( op1, op2) );
11912 ins_pipe( ialu_cr_reg_mem );
11913 %}
11914
11915 // // Cisc-spilled version of cmpU_eReg
11916 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11917 // match(Set cr (CmpU (LoadI op1) op2));
11918 //
11919 // format %{ "CMPu $op1,$op2" %}
11920 // ins_cost(500);
11921 // opcode(0x39); /* Opcode 39 /r */
11922 // ins_encode( OpcP, RegMem( op1, op2) );
11923 //%}
11924
11925 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11926 match(Set cr (CmpU src zero));
11927
11928 format %{ "TESTu $src,$src" %}
11929 opcode(0x85);
11930 ins_encode( OpcP, RegReg( src, src ) );
11931 ins_pipe( ialu_cr_reg_imm );
11932 %}
11933
11934 // Unsigned pointer compare Instructions
11935 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11936 match(Set cr (CmpP op1 op2));
11937
11938 format %{ "CMPu $op1,$op2" %}
11939 opcode(0x3B); /* Opcode 3B /r */
11940 ins_encode( OpcP, RegReg( op1, op2) );
11941 ins_pipe( ialu_cr_reg_reg );
11942 %}
11943
11944 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11945 match(Set cr (CmpP op1 op2));
11946
11947 format %{ "CMPu $op1,$op2" %}
11948 opcode(0x81,0x07); /* Opcode 81 /7 */
11949 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11950 ins_pipe( ialu_cr_reg_imm );
11951 %}
11952
11953 // // Cisc-spilled version of cmpP_eReg
11954 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11955 match(Set cr (CmpP op1 (LoadP op2)));
11956
11957 format %{ "CMPu $op1,$op2" %}
11958 ins_cost(500);
11959 opcode(0x3B); /* Opcode 3B /r */
11960 ins_encode( OpcP, RegMem( op1, op2) );
11961 ins_pipe( ialu_cr_reg_mem );
11962 %}
11963
11964 // // Cisc-spilled version of cmpP_eReg
11965 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11966 // match(Set cr (CmpP (LoadP op1) op2));
11967 //
11968 // format %{ "CMPu $op1,$op2" %}
11969 // ins_cost(500);
11970 // opcode(0x39); /* Opcode 39 /r */
11971 // ins_encode( OpcP, RegMem( op1, op2) );
11972 //%}
11973
11974 // Compare raw pointer (used in out-of-heap check).
11975 // Only works because non-oop pointers must be raw pointers
11976 // and raw pointers have no anti-dependencies.
11977 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11978 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11979 match(Set cr (CmpP op1 (LoadP op2)));
11980
11981 format %{ "CMPu $op1,$op2" %}
11982 opcode(0x3B); /* Opcode 3B /r */
11983 ins_encode( OpcP, RegMem( op1, op2) );
11984 ins_pipe( ialu_cr_reg_mem );
11985 %}
11986
11987 //
11988 // This will generate a signed flags result. This should be ok
11989 // since any compare to a zero should be eq/neq.
11990 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11991 match(Set cr (CmpP src zero));
11992
11993 format %{ "TEST $src,$src" %}
11994 opcode(0x85);
11995 ins_encode( OpcP, RegReg( src, src ) );
11996 ins_pipe( ialu_cr_reg_imm );
11997 %}
11998
11999 // Cisc-spilled version of testP_reg
12000 // This will generate a signed flags result. This should be ok
12001 // since any compare to a zero should be eq/neq.
12002 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12003 match(Set cr (CmpP (LoadP op) zero));
12004
12005 format %{ "TEST $op,0xFFFFFFFF" %}
12006 ins_cost(500);
12007 opcode(0xF7); /* Opcode F7 /0 */
12008 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12009 ins_pipe( ialu_cr_reg_imm );
12010 %}
12011
12012 // Yanked all unsigned pointer compare operations.
12013 // Pointer compares are done with CmpP which is already unsigned.
12014
12015 //----------Max and Min--------------------------------------------------------
12016 // Min Instructions
12017 ////
12018 // *** Min and Max using the conditional move are slower than the
12019 // *** branch version on a Pentium III.
12020 // // Conditional move for min
12021 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12022 // effect( USE_DEF op2, USE op1, USE cr );
12023 // format %{ "CMOVlt $op2,$op1\t! min" %}
12024 // opcode(0x4C,0x0F);
12025 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12026 // ins_pipe( pipe_cmov_reg );
12027 //%}
12028 //
12029 //// Min Register with Register (P6 version)
12030 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12031 // predicate(VM_Version::supports_cmov() );
12032 // match(Set op2 (MinI op1 op2));
12033 // ins_cost(200);
12034 // expand %{
12035 // eFlagsReg cr;
12036 // compI_eReg(cr,op1,op2);
12037 // cmovI_reg_lt(op2,op1,cr);
12038 // %}
12039 //%}
12040
12041 // Min Register with Register (generic version)
12042 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12043 match(Set dst (MinI dst src));
12044 effect(KILL flags);
12045 ins_cost(300);
12046
12047 format %{ "MIN $dst,$src" %}
12048 opcode(0xCC);
12049 ins_encode( min_enc(dst,src) );
12050 ins_pipe( pipe_slow );
12051 %}
12052
12053 // Max Register with Register
12054 // *** Min and Max using the conditional move are slower than the
12055 // *** branch version on a Pentium III.
12056 // // Conditional move for max
12057 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12058 // effect( USE_DEF op2, USE op1, USE cr );
12059 // format %{ "CMOVgt $op2,$op1\t! max" %}
12060 // opcode(0x4F,0x0F);
12061 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12062 // ins_pipe( pipe_cmov_reg );
12063 //%}
12064 //
12065 // // Max Register with Register (P6 version)
12066 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12067 // predicate(VM_Version::supports_cmov() );
12068 // match(Set op2 (MaxI op1 op2));
12069 // ins_cost(200);
12070 // expand %{
12071 // eFlagsReg cr;
12072 // compI_eReg(cr,op1,op2);
12073 // cmovI_reg_gt(op2,op1,cr);
12074 // %}
12075 //%}
12076
12077 // Max Register with Register (generic version)
12078 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12079 match(Set dst (MaxI dst src));
12080 effect(KILL flags);
12081 ins_cost(300);
12082
12083 format %{ "MAX $dst,$src" %}
12084 opcode(0xCC);
12085 ins_encode( max_enc(dst,src) );
12086 ins_pipe( pipe_slow );
12087 %}
12088
12089 // ============================================================================
12090 // Counted Loop limit node which represents exact final iterator value.
12091 // Note: the resulting value should fit into integer range since
12092 // counted loops have limit check on overflow.
12093 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12094 match(Set limit (LoopLimit (Binary init limit) stride));
12095 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12096 ins_cost(300);
12097
12098 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12099 ins_encode %{
12100 int strd = (int)$stride$$constant;
12101 assert(strd != 1 && strd != -1, "sanity");
12102 int m1 = (strd > 0) ? 1 : -1;
12103 // Convert limit to long (EAX:EDX)
12104 __ cdql();
12105 // Convert init to long (init:tmp)
12106 __ movl($tmp$$Register, $init$$Register);
12107 __ sarl($tmp$$Register, 31);
12108 // $limit - $init
12109 __ subl($limit$$Register, $init$$Register);
12110 __ sbbl($limit_hi$$Register, $tmp$$Register);
12111 // + ($stride - 1)
12112 if (strd > 0) {
12113 __ addl($limit$$Register, (strd - 1));
12114 __ adcl($limit_hi$$Register, 0);
12115 __ movl($tmp$$Register, strd);
12116 } else {
12117 __ addl($limit$$Register, (strd + 1));
12118 __ adcl($limit_hi$$Register, -1);
12119 __ lneg($limit_hi$$Register, $limit$$Register);
12120 __ movl($tmp$$Register, -strd);
12121 }
12122 // signed devision: (EAX:EDX) / pos_stride
12123 __ idivl($tmp$$Register);
12124 if (strd < 0) {
12125 // restore sign
12126 __ negl($tmp$$Register);
12127 }
12128 // (EAX) * stride
12129 __ mull($tmp$$Register);
12130 // + init (ignore upper bits)
12131 __ addl($limit$$Register, $init$$Register);
12132 %}
12133 ins_pipe( pipe_slow );
12134 %}
12135
12136 // ============================================================================
12137 // Branch Instructions
12138 // Jump Table
12139 instruct jumpXtnd(rRegI switch_val) %{
12140 match(Jump switch_val);
12141 ins_cost(350);
12142 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12143 ins_encode %{
12144 // Jump to Address(table_base + switch_reg)
12145 Address index(noreg, $switch_val$$Register, Address::times_1);
12146 __ jump(ArrayAddress($constantaddress, index));
12147 %}
12148 ins_pipe(pipe_jmp);
12149 %}
12150
12151 // Jump Direct - Label defines a relative address from JMP+1
12152 instruct jmpDir(label labl) %{
12153 match(Goto);
12154 effect(USE labl);
12155
12156 ins_cost(300);
12157 format %{ "JMP $labl" %}
12158 size(5);
12159 ins_encode %{
12160 Label* L = $labl$$label;
12161 __ jmp(*L, false); // Always long jump
12162 %}
12163 ins_pipe( pipe_jmp );
12164 %}
12165
12166 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12167 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12168 match(If cop cr);
12169 effect(USE labl);
12170
12171 ins_cost(300);
12172 format %{ "J$cop $labl" %}
12173 size(6);
12174 ins_encode %{
12175 Label* L = $labl$$label;
12176 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12177 %}
12178 ins_pipe( pipe_jcc );
12179 %}
12180
12181 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12182 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12183 match(CountedLoopEnd cop cr);
12184 effect(USE labl);
12185
12186 ins_cost(300);
12187 format %{ "J$cop $labl\t# Loop end" %}
12188 size(6);
12189 ins_encode %{
12190 Label* L = $labl$$label;
12191 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12192 %}
12193 ins_pipe( pipe_jcc );
12194 %}
12195
12196 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12197 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12198 match(CountedLoopEnd cop cmp);
12199 effect(USE labl);
12200
12201 ins_cost(300);
12202 format %{ "J$cop,u $labl\t# Loop end" %}
12203 size(6);
12204 ins_encode %{
12205 Label* L = $labl$$label;
12206 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12207 %}
12208 ins_pipe( pipe_jcc );
12209 %}
12210
12211 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12212 match(CountedLoopEnd cop cmp);
12213 effect(USE labl);
12214
12215 ins_cost(200);
12216 format %{ "J$cop,u $labl\t# Loop end" %}
12217 size(6);
12218 ins_encode %{
12219 Label* L = $labl$$label;
12220 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12221 %}
12222 ins_pipe( pipe_jcc );
12223 %}
12224
12225 // Jump Direct Conditional - using unsigned comparison
12226 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12227 match(If cop cmp);
12228 effect(USE labl);
12229
12230 ins_cost(300);
12231 format %{ "J$cop,u $labl" %}
12232 size(6);
12233 ins_encode %{
12234 Label* L = $labl$$label;
12235 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12236 %}
12237 ins_pipe(pipe_jcc);
12238 %}
12239
12240 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12241 match(If cop cmp);
12242 effect(USE labl);
12243
12244 ins_cost(200);
12245 format %{ "J$cop,u $labl" %}
12246 size(6);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12250 %}
12251 ins_pipe(pipe_jcc);
12252 %}
12253
12254 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12255 match(If cop cmp);
12256 effect(USE labl);
12257
12258 ins_cost(200);
12259 format %{ $$template
12260 if ($cop$$cmpcode == Assembler::notEqual) {
12261 $$emit$$"JP,u $labl\n\t"
12262 $$emit$$"J$cop,u $labl"
12263 } else {
12264 $$emit$$"JP,u done\n\t"
12265 $$emit$$"J$cop,u $labl\n\t"
12266 $$emit$$"done:"
12267 }
12268 %}
12269 ins_encode %{
12270 Label* l = $labl$$label;
12271 if ($cop$$cmpcode == Assembler::notEqual) {
12272 __ jcc(Assembler::parity, *l, false);
12273 __ jcc(Assembler::notEqual, *l, false);
12274 } else if ($cop$$cmpcode == Assembler::equal) {
12275 Label done;
12276 __ jccb(Assembler::parity, done);
12277 __ jcc(Assembler::equal, *l, false);
12278 __ bind(done);
12279 } else {
12280 ShouldNotReachHere();
12281 }
12282 %}
12283 ins_pipe(pipe_jcc);
12284 %}
12285
12286 // ============================================================================
12287 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12288 // array for an instance of the superklass. Set a hidden internal cache on a
12289 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12290 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12291 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12292 match(Set result (PartialSubtypeCheck sub super));
12293 effect( KILL rcx, KILL cr );
12294
12295 ins_cost(1100); // slightly larger than the next version
12296 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12297 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12298 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12299 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12300 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12301 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12302 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12303 "miss:\t" %}
12304
12305 opcode(0x1); // Force a XOR of EDI
12306 ins_encode( enc_PartialSubtypeCheck() );
12307 ins_pipe( pipe_slow );
12308 %}
12309
12310 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12311 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12312 effect( KILL rcx, KILL result );
12313
12314 ins_cost(1000);
12315 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12316 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12317 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12318 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12319 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12320 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12321 "miss:\t" %}
12322
12323 opcode(0x0); // No need to XOR EDI
12324 ins_encode( enc_PartialSubtypeCheck() );
12325 ins_pipe( pipe_slow );
12326 %}
12327
12328 // ============================================================================
12329 // Branch Instructions -- short offset versions
12330 //
12331 // These instructions are used to replace jumps of a long offset (the default
12332 // match) with jumps of a shorter offset. These instructions are all tagged
12333 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12334 // match rules in general matching. Instead, the ADLC generates a conversion
12335 // method in the MachNode which can be used to do in-place replacement of the
12336 // long variant with the shorter variant. The compiler will determine if a
12337 // branch can be taken by the is_short_branch_offset() predicate in the machine
12338 // specific code section of the file.
12339
12340 // Jump Direct - Label defines a relative address from JMP+1
12341 instruct jmpDir_short(label labl) %{
12342 match(Goto);
12343 effect(USE labl);
12344
12345 ins_cost(300);
12346 format %{ "JMP,s $labl" %}
12347 size(2);
12348 ins_encode %{
12349 Label* L = $labl$$label;
12350 __ jmpb(*L);
12351 %}
12352 ins_pipe( pipe_jmp );
12353 ins_short_branch(1);
12354 %}
12355
12356 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12357 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12358 match(If cop cr);
12359 effect(USE labl);
12360
12361 ins_cost(300);
12362 format %{ "J$cop,s $labl" %}
12363 size(2);
12364 ins_encode %{
12365 Label* L = $labl$$label;
12366 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12367 %}
12368 ins_pipe( pipe_jcc );
12369 ins_short_branch(1);
12370 %}
12371
12372 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12373 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12374 match(CountedLoopEnd cop cr);
12375 effect(USE labl);
12376
12377 ins_cost(300);
12378 format %{ "J$cop,s $labl\t# Loop end" %}
12379 size(2);
12380 ins_encode %{
12381 Label* L = $labl$$label;
12382 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12383 %}
12384 ins_pipe( pipe_jcc );
12385 ins_short_branch(1);
12386 %}
12387
12388 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12389 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12390 match(CountedLoopEnd cop cmp);
12391 effect(USE labl);
12392
12393 ins_cost(300);
12394 format %{ "J$cop,us $labl\t# Loop end" %}
12395 size(2);
12396 ins_encode %{
12397 Label* L = $labl$$label;
12398 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12399 %}
12400 ins_pipe( pipe_jcc );
12401 ins_short_branch(1);
12402 %}
12403
12404 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12405 match(CountedLoopEnd cop cmp);
12406 effect(USE labl);
12407
12408 ins_cost(300);
12409 format %{ "J$cop,us $labl\t# Loop end" %}
12410 size(2);
12411 ins_encode %{
12412 Label* L = $labl$$label;
12413 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12414 %}
12415 ins_pipe( pipe_jcc );
12416 ins_short_branch(1);
12417 %}
12418
12419 // Jump Direct Conditional - using unsigned comparison
12420 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12421 match(If cop cmp);
12422 effect(USE labl);
12423
12424 ins_cost(300);
12425 format %{ "J$cop,us $labl" %}
12426 size(2);
12427 ins_encode %{
12428 Label* L = $labl$$label;
12429 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12430 %}
12431 ins_pipe( pipe_jcc );
12432 ins_short_branch(1);
12433 %}
12434
12435 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12436 match(If cop cmp);
12437 effect(USE labl);
12438
12439 ins_cost(300);
12440 format %{ "J$cop,us $labl" %}
12441 size(2);
12442 ins_encode %{
12443 Label* L = $labl$$label;
12444 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12445 %}
12446 ins_pipe( pipe_jcc );
12447 ins_short_branch(1);
12448 %}
12449
12450 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12451 match(If cop cmp);
12452 effect(USE labl);
12453
12454 ins_cost(300);
12455 format %{ $$template
12456 if ($cop$$cmpcode == Assembler::notEqual) {
12457 $$emit$$"JP,u,s $labl\n\t"
12458 $$emit$$"J$cop,u,s $labl"
12459 } else {
12460 $$emit$$"JP,u,s done\n\t"
12461 $$emit$$"J$cop,u,s $labl\n\t"
12462 $$emit$$"done:"
12463 }
12464 %}
12465 size(4);
12466 ins_encode %{
12467 Label* l = $labl$$label;
12468 if ($cop$$cmpcode == Assembler::notEqual) {
12469 __ jccb(Assembler::parity, *l);
12470 __ jccb(Assembler::notEqual, *l);
12471 } else if ($cop$$cmpcode == Assembler::equal) {
12472 Label done;
12473 __ jccb(Assembler::parity, done);
12474 __ jccb(Assembler::equal, *l);
12475 __ bind(done);
12476 } else {
12477 ShouldNotReachHere();
12478 }
12479 %}
12480 ins_pipe(pipe_jcc);
12481 ins_short_branch(1);
12482 %}
12483
12484 // ============================================================================
12485 // Long Compare
12486 //
12487 // Currently we hold longs in 2 registers. Comparing such values efficiently
12488 // is tricky. The flavor of compare used depends on whether we are testing
12489 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12490 // The GE test is the negated LT test. The LE test can be had by commuting
12491 // the operands (yielding a GE test) and then negating; negate again for the
12492 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12493 // NE test is negated from that.
12494
12495 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12496 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12497 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12498 // are collapsed internally in the ADLC's dfa-gen code. The match for
12499 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12500 // foo match ends up with the wrong leaf. One fix is to not match both
12501 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12502 // both forms beat the trinary form of long-compare and both are very useful
12503 // on Intel which has so few registers.
12504
12505 // Manifest a CmpL result in an integer register. Very painful.
12506 // This is the test to avoid.
12507 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12508 match(Set dst (CmpL3 src1 src2));
12509 effect( KILL flags );
12510 ins_cost(1000);
12511 format %{ "XOR $dst,$dst\n\t"
12512 "CMP $src1.hi,$src2.hi\n\t"
12513 "JLT,s m_one\n\t"
12514 "JGT,s p_one\n\t"
12515 "CMP $src1.lo,$src2.lo\n\t"
12516 "JB,s m_one\n\t"
12517 "JEQ,s done\n"
12518 "p_one:\tINC $dst\n\t"
12519 "JMP,s done\n"
12520 "m_one:\tDEC $dst\n"
12521 "done:" %}
12522 ins_encode %{
12523 Label p_one, m_one, done;
12524 __ xorptr($dst$$Register, $dst$$Register);
12525 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12526 __ jccb(Assembler::less, m_one);
12527 __ jccb(Assembler::greater, p_one);
12528 __ cmpl($src1$$Register, $src2$$Register);
12529 __ jccb(Assembler::below, m_one);
12530 __ jccb(Assembler::equal, done);
12531 __ bind(p_one);
12532 __ incrementl($dst$$Register);
12533 __ jmpb(done);
12534 __ bind(m_one);
12535 __ decrementl($dst$$Register);
12536 __ bind(done);
12537 %}
12538 ins_pipe( pipe_slow );
12539 %}
12540
12541 //======
12542 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12543 // compares. Can be used for LE or GT compares by reversing arguments.
12544 // NOT GOOD FOR EQ/NE tests.
12545 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12546 match( Set flags (CmpL src zero ));
12547 ins_cost(100);
12548 format %{ "TEST $src.hi,$src.hi" %}
12549 opcode(0x85);
12550 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12551 ins_pipe( ialu_cr_reg_reg );
12552 %}
12553
12554 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12555 // compares. Can be used for LE or GT compares by reversing arguments.
12556 // NOT GOOD FOR EQ/NE tests.
12557 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12558 match( Set flags (CmpL src1 src2 ));
12559 effect( TEMP tmp );
12560 ins_cost(300);
12561 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12562 "MOV $tmp,$src1.hi\n\t"
12563 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12564 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12565 ins_pipe( ialu_cr_reg_reg );
12566 %}
12567
12568 // Long compares reg < zero/req OR reg >= zero/req.
12569 // Just a wrapper for a normal branch, plus the predicate test.
12570 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12571 match(If cmp flags);
12572 effect(USE labl);
12573 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12574 expand %{
12575 jmpCon(cmp,flags,labl); // JLT or JGE...
12576 %}
12577 %}
12578
12579 // Compare 2 longs and CMOVE longs.
12580 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12581 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12582 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12583 ins_cost(400);
12584 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12585 "CMOV$cmp $dst.hi,$src.hi" %}
12586 opcode(0x0F,0x40);
12587 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12588 ins_pipe( pipe_cmov_reg_long );
12589 %}
12590
12591 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12592 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12593 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12594 ins_cost(500);
12595 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12596 "CMOV$cmp $dst.hi,$src.hi" %}
12597 opcode(0x0F,0x40);
12598 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12599 ins_pipe( pipe_cmov_reg_long );
12600 %}
12601
12602 // Compare 2 longs and CMOVE ints.
12603 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12604 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12605 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12606 ins_cost(200);
12607 format %{ "CMOV$cmp $dst,$src" %}
12608 opcode(0x0F,0x40);
12609 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12610 ins_pipe( pipe_cmov_reg );
12611 %}
12612
12613 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12614 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12615 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12616 ins_cost(250);
12617 format %{ "CMOV$cmp $dst,$src" %}
12618 opcode(0x0F,0x40);
12619 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12620 ins_pipe( pipe_cmov_mem );
12621 %}
12622
12623 // Compare 2 longs and CMOVE ints.
12624 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12625 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12626 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12627 ins_cost(200);
12628 format %{ "CMOV$cmp $dst,$src" %}
12629 opcode(0x0F,0x40);
12630 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12631 ins_pipe( pipe_cmov_reg );
12632 %}
12633
12634 // Compare 2 longs and CMOVE doubles
12635 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12636 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12637 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12638 ins_cost(200);
12639 expand %{
12640 fcmovDPR_regS(cmp,flags,dst,src);
12641 %}
12642 %}
12643
12644 // Compare 2 longs and CMOVE doubles
12645 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12646 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12647 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12648 ins_cost(200);
12649 expand %{
12650 fcmovD_regS(cmp,flags,dst,src);
12651 %}
12652 %}
12653
12654 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12655 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12656 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12657 ins_cost(200);
12658 expand %{
12659 fcmovFPR_regS(cmp,flags,dst,src);
12660 %}
12661 %}
12662
12663 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12664 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12665 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12666 ins_cost(200);
12667 expand %{
12668 fcmovF_regS(cmp,flags,dst,src);
12669 %}
12670 %}
12671
12672 //======
12673 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12674 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12675 match( Set flags (CmpL src zero ));
12676 effect(TEMP tmp);
12677 ins_cost(200);
12678 format %{ "MOV $tmp,$src.lo\n\t"
12679 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12680 ins_encode( long_cmp_flags0( src, tmp ) );
12681 ins_pipe( ialu_reg_reg_long );
12682 %}
12683
12684 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12685 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12686 match( Set flags (CmpL src1 src2 ));
12687 ins_cost(200+300);
12688 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12689 "JNE,s skip\n\t"
12690 "CMP $src1.hi,$src2.hi\n\t"
12691 "skip:\t" %}
12692 ins_encode( long_cmp_flags1( src1, src2 ) );
12693 ins_pipe( ialu_cr_reg_reg );
12694 %}
12695
12696 // Long compare reg == zero/reg OR reg != zero/reg
12697 // Just a wrapper for a normal branch, plus the predicate test.
12698 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12699 match(If cmp flags);
12700 effect(USE labl);
12701 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12702 expand %{
12703 jmpCon(cmp,flags,labl); // JEQ or JNE...
12704 %}
12705 %}
12706
12707 // Compare 2 longs and CMOVE longs.
12708 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12709 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12710 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12711 ins_cost(400);
12712 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12713 "CMOV$cmp $dst.hi,$src.hi" %}
12714 opcode(0x0F,0x40);
12715 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12716 ins_pipe( pipe_cmov_reg_long );
12717 %}
12718
12719 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12720 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12721 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12722 ins_cost(500);
12723 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12724 "CMOV$cmp $dst.hi,$src.hi" %}
12725 opcode(0x0F,0x40);
12726 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12727 ins_pipe( pipe_cmov_reg_long );
12728 %}
12729
12730 // Compare 2 longs and CMOVE ints.
12731 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12732 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12733 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12734 ins_cost(200);
12735 format %{ "CMOV$cmp $dst,$src" %}
12736 opcode(0x0F,0x40);
12737 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12738 ins_pipe( pipe_cmov_reg );
12739 %}
12740
12741 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12742 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12743 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12744 ins_cost(250);
12745 format %{ "CMOV$cmp $dst,$src" %}
12746 opcode(0x0F,0x40);
12747 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12748 ins_pipe( pipe_cmov_mem );
12749 %}
12750
12751 // Compare 2 longs and CMOVE ints.
12752 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12753 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12754 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12755 ins_cost(200);
12756 format %{ "CMOV$cmp $dst,$src" %}
12757 opcode(0x0F,0x40);
12758 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12759 ins_pipe( pipe_cmov_reg );
12760 %}
12761
12762 // Compare 2 longs and CMOVE doubles
12763 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12764 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12765 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12766 ins_cost(200);
12767 expand %{
12768 fcmovDPR_regS(cmp,flags,dst,src);
12769 %}
12770 %}
12771
12772 // Compare 2 longs and CMOVE doubles
12773 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12774 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12775 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12776 ins_cost(200);
12777 expand %{
12778 fcmovD_regS(cmp,flags,dst,src);
12779 %}
12780 %}
12781
12782 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12783 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12784 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12785 ins_cost(200);
12786 expand %{
12787 fcmovFPR_regS(cmp,flags,dst,src);
12788 %}
12789 %}
12790
12791 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12792 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12793 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12794 ins_cost(200);
12795 expand %{
12796 fcmovF_regS(cmp,flags,dst,src);
12797 %}
12798 %}
12799
12800 //======
12801 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12802 // Same as cmpL_reg_flags_LEGT except must negate src
12803 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12804 match( Set flags (CmpL src zero ));
12805 effect( TEMP tmp );
12806 ins_cost(300);
12807 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12808 "CMP $tmp,$src.lo\n\t"
12809 "SBB $tmp,$src.hi\n\t" %}
12810 ins_encode( long_cmp_flags3(src, tmp) );
12811 ins_pipe( ialu_reg_reg_long );
12812 %}
12813
12814 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12815 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12816 // requires a commuted test to get the same result.
12817 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12818 match( Set flags (CmpL src1 src2 ));
12819 effect( TEMP tmp );
12820 ins_cost(300);
12821 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12822 "MOV $tmp,$src2.hi\n\t"
12823 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12824 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12825 ins_pipe( ialu_cr_reg_reg );
12826 %}
12827
12828 // Long compares reg < zero/req OR reg >= zero/req.
12829 // Just a wrapper for a normal branch, plus the predicate test
12830 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12831 match(If cmp flags);
12832 effect(USE labl);
12833 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12834 ins_cost(300);
12835 expand %{
12836 jmpCon(cmp,flags,labl); // JGT or JLE...
12837 %}
12838 %}
12839
12840 // Compare 2 longs and CMOVE longs.
12841 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12842 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12843 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12844 ins_cost(400);
12845 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12846 "CMOV$cmp $dst.hi,$src.hi" %}
12847 opcode(0x0F,0x40);
12848 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12849 ins_pipe( pipe_cmov_reg_long );
12850 %}
12851
12852 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12853 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12854 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12855 ins_cost(500);
12856 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12857 "CMOV$cmp $dst.hi,$src.hi+4" %}
12858 opcode(0x0F,0x40);
12859 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12860 ins_pipe( pipe_cmov_reg_long );
12861 %}
12862
12863 // Compare 2 longs and CMOVE ints.
12864 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12865 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12866 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12867 ins_cost(200);
12868 format %{ "CMOV$cmp $dst,$src" %}
12869 opcode(0x0F,0x40);
12870 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12871 ins_pipe( pipe_cmov_reg );
12872 %}
12873
12874 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12875 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12876 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12877 ins_cost(250);
12878 format %{ "CMOV$cmp $dst,$src" %}
12879 opcode(0x0F,0x40);
12880 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12881 ins_pipe( pipe_cmov_mem );
12882 %}
12883
12884 // Compare 2 longs and CMOVE ptrs.
12885 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12886 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12887 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12888 ins_cost(200);
12889 format %{ "CMOV$cmp $dst,$src" %}
12890 opcode(0x0F,0x40);
12891 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12892 ins_pipe( pipe_cmov_reg );
12893 %}
12894
12895 // Compare 2 longs and CMOVE doubles
12896 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12897 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12898 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12899 ins_cost(200);
12900 expand %{
12901 fcmovDPR_regS(cmp,flags,dst,src);
12902 %}
12903 %}
12904
12905 // Compare 2 longs and CMOVE doubles
12906 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12907 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12908 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12909 ins_cost(200);
12910 expand %{
12911 fcmovD_regS(cmp,flags,dst,src);
12912 %}
12913 %}
12914
12915 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12916 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12917 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12918 ins_cost(200);
12919 expand %{
12920 fcmovFPR_regS(cmp,flags,dst,src);
12921 %}
12922 %}
12923
12924
12925 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12926 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12927 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12928 ins_cost(200);
12929 expand %{
12930 fcmovF_regS(cmp,flags,dst,src);
12931 %}
12932 %}
12933
12934
12935 // ============================================================================
12936 // Procedure Call/Return Instructions
12937 // Call Java Static Instruction
12938 // Note: If this code changes, the corresponding ret_addr_offset() and
12939 // compute_padding() functions will have to be adjusted.
12940 instruct CallStaticJavaDirect(method meth) %{
12941 match(CallStaticJava);
12942 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12943 effect(USE meth);
12944
12945 ins_cost(300);
12946 format %{ "CALL,static " %}
12947 opcode(0xE8); /* E8 cd */
12948 ins_encode( pre_call_resets,
12949 Java_Static_Call( meth ),
12950 call_epilog,
12951 post_call_FPU );
12952 ins_pipe( pipe_slow );
12953 ins_alignment(4);
12954 %}
12955
12956 // Call Java Static Instruction (method handle version)
12957 // Note: If this code changes, the corresponding ret_addr_offset() and
12958 // compute_padding() functions will have to be adjusted.
12959 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12960 match(CallStaticJava);
12961 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12962 effect(USE meth);
12963 // EBP is saved by all callees (for interpreter stack correction).
12964 // We use it here for a similar purpose, in {preserve,restore}_SP.
12965
12966 ins_cost(300);
12967 format %{ "CALL,static/MethodHandle " %}
12968 opcode(0xE8); /* E8 cd */
12969 ins_encode( pre_call_resets,
12970 preserve_SP,
12971 Java_Static_Call( meth ),
12972 restore_SP,
12973 call_epilog,
12974 post_call_FPU );
12975 ins_pipe( pipe_slow );
12976 ins_alignment(4);
12977 %}
12978
12979 // Call Java Dynamic Instruction
12980 // Note: If this code changes, the corresponding ret_addr_offset() and
12981 // compute_padding() functions will have to be adjusted.
12982 instruct CallDynamicJavaDirect(method meth) %{
12983 match(CallDynamicJava);
12984 effect(USE meth);
12985
12986 ins_cost(300);
12987 format %{ "MOV EAX,(oop)-1\n\t"
12988 "CALL,dynamic" %}
12989 opcode(0xE8); /* E8 cd */
12990 ins_encode( pre_call_resets,
12991 Java_Dynamic_Call( meth ),
12992 call_epilog,
12993 post_call_FPU );
12994 ins_pipe( pipe_slow );
12995 ins_alignment(4);
12996 %}
12997
12998 // Call Runtime Instruction
12999 instruct CallRuntimeDirect(method meth) %{
13000 match(CallRuntime );
13001 effect(USE meth);
13002
13003 ins_cost(300);
13004 format %{ "CALL,runtime " %}
13005 opcode(0xE8); /* E8 cd */
13006 // Use FFREEs to clear entries in float stack
13007 ins_encode( pre_call_resets,
13008 FFree_Float_Stack_All,
13009 Java_To_Runtime( meth ),
13010 post_call_FPU );
13011 ins_pipe( pipe_slow );
13012 %}
13013
13014 // Call runtime without safepoint
13015 instruct CallLeafDirect(method meth) %{
13016 match(CallLeaf);
13017 effect(USE meth);
13018
13019 ins_cost(300);
13020 format %{ "CALL_LEAF,runtime " %}
13021 opcode(0xE8); /* E8 cd */
13022 ins_encode( pre_call_resets,
13023 FFree_Float_Stack_All,
13024 Java_To_Runtime( meth ),
13025 Verify_FPU_For_Leaf, post_call_FPU );
13026 ins_pipe( pipe_slow );
13027 %}
13028
13029 instruct CallLeafNoFPDirect(method meth) %{
13030 match(CallLeafNoFP);
13031 effect(USE meth);
13032
13033 ins_cost(300);
13034 format %{ "CALL_LEAF_NOFP,runtime " %}
13035 opcode(0xE8); /* E8 cd */
13036 ins_encode(Java_To_Runtime(meth));
13037 ins_pipe( pipe_slow );
13038 %}
13039
13040
13041 // Return Instruction
13042 // Remove the return address & jump to it.
13043 instruct Ret() %{
13044 match(Return);
13045 format %{ "RET" %}
13046 opcode(0xC3);
13047 ins_encode(OpcP);
13048 ins_pipe( pipe_jmp );
13049 %}
13050
13051 // Tail Call; Jump from runtime stub to Java code.
13052 // Also known as an 'interprocedural jump'.
13053 // Target of jump will eventually return to caller.
13054 // TailJump below removes the return address.
13055 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13056 match(TailCall jump_target method_oop );
13057 ins_cost(300);
13058 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13059 opcode(0xFF, 0x4); /* Opcode FF /4 */
13060 ins_encode( OpcP, RegOpc(jump_target) );
13061 ins_pipe( pipe_jmp );
13062 %}
13063
13064
13065 // Tail Jump; remove the return address; jump to target.
13066 // TailCall above leaves the return address around.
13067 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13068 match( TailJump jump_target ex_oop );
13069 ins_cost(300);
13070 format %{ "POP EDX\t# pop return address into dummy\n\t"
13071 "JMP $jump_target " %}
13072 opcode(0xFF, 0x4); /* Opcode FF /4 */
13073 ins_encode( enc_pop_rdx,
13074 OpcP, RegOpc(jump_target) );
13075 ins_pipe( pipe_jmp );
13076 %}
13077
13078 // Create exception oop: created by stack-crawling runtime code.
13079 // Created exception is now available to this handler, and is setup
13080 // just prior to jumping to this handler. No code emitted.
13081 instruct CreateException( eAXRegP ex_oop )
13082 %{
13083 match(Set ex_oop (CreateEx));
13084
13085 size(0);
13086 // use the following format syntax
13087 format %{ "# exception oop is in EAX; no code emitted" %}
13088 ins_encode();
13089 ins_pipe( empty );
13090 %}
13091
13092
13093 // Rethrow exception:
13094 // The exception oop will come in the first argument position.
13095 // Then JUMP (not call) to the rethrow stub code.
13096 instruct RethrowException()
13097 %{
13098 match(Rethrow);
13099
13100 // use the following format syntax
13101 format %{ "JMP rethrow_stub" %}
13102 ins_encode(enc_rethrow);
13103 ins_pipe( pipe_jmp );
13104 %}
13105
13106 // inlined locking and unlocking
13107
13108
13109 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13110 match( Set cr (FastLock object box) );
13111 effect( TEMP tmp, TEMP scr, USE_KILL box );
13112 ins_cost(300);
13113 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13114 ins_encode( Fast_Lock(object,box,tmp,scr) );
13115 ins_pipe( pipe_slow );
13116 %}
13117
13118 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13119 match( Set cr (FastUnlock object box) );
13120 effect( TEMP tmp, USE_KILL box );
13121 ins_cost(300);
13122 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13123 ins_encode( Fast_Unlock(object,box,tmp) );
13124 ins_pipe( pipe_slow );
13125 %}
13126
13127
13128
13129 // ============================================================================
13130 // Safepoint Instruction
13131 instruct safePoint_poll(eFlagsReg cr) %{
13132 match(SafePoint);
13133 effect(KILL cr);
13134
13135 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13136 // On SPARC that might be acceptable as we can generate the address with
13137 // just a sethi, saving an or. By polling at offset 0 we can end up
13138 // putting additional pressure on the index-0 in the D$. Because of
13139 // alignment (just like the situation at hand) the lower indices tend
13140 // to see more traffic. It'd be better to change the polling address
13141 // to offset 0 of the last $line in the polling page.
13142
13143 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13144 ins_cost(125);
13145 size(6) ;
13146 ins_encode( Safepoint_Poll() );
13147 ins_pipe( ialu_reg_mem );
13148 %}
13149
13150
13151 // ============================================================================
13152 // This name is KNOWN by the ADLC and cannot be changed.
13153 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13154 // for this guy.
13155 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13156 match(Set dst (ThreadLocal));
13157 effect(DEF dst, KILL cr);
13158
13159 format %{ "MOV $dst, Thread::current()" %}
13160 ins_encode %{
13161 Register dstReg = as_Register($dst$$reg);
13162 __ get_thread(dstReg);
13163 %}
13164 ins_pipe( ialu_reg_fat );
13165 %}
13166
13167
13168
13169 //----------PEEPHOLE RULES-----------------------------------------------------
13170 // These must follow all instruction definitions as they use the names
13171 // defined in the instructions definitions.
13172 //
13173 // peepmatch ( root_instr_name [preceding_instruction]* );
13174 //
13175 // peepconstraint %{
13176 // (instruction_number.operand_name relational_op instruction_number.operand_name
13177 // [, ...] );
13178 // // instruction numbers are zero-based using left to right order in peepmatch
13179 //
13180 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13181 // // provide an instruction_number.operand_name for each operand that appears
13182 // // in the replacement instruction's match rule
13183 //
13184 // ---------VM FLAGS---------------------------------------------------------
13185 //
13186 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13187 //
13188 // Each peephole rule is given an identifying number starting with zero and
13189 // increasing by one in the order seen by the parser. An individual peephole
13190 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13191 // on the command-line.
13192 //
13193 // ---------CURRENT LIMITATIONS----------------------------------------------
13194 //
13195 // Only match adjacent instructions in same basic block
13196 // Only equality constraints
13197 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13198 // Only one replacement instruction
13199 //
13200 // ---------EXAMPLE----------------------------------------------------------
13201 //
13202 // // pertinent parts of existing instructions in architecture description
13203 // instruct movI(rRegI dst, rRegI src) %{
13204 // match(Set dst (CopyI src));
13205 // %}
13206 //
13207 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13208 // match(Set dst (AddI dst src));
13209 // effect(KILL cr);
13210 // %}
13211 //
13212 // // Change (inc mov) to lea
13213 // peephole %{
13214 // // increment preceeded by register-register move
13215 // peepmatch ( incI_eReg movI );
13216 // // require that the destination register of the increment
13217 // // match the destination register of the move
13218 // peepconstraint ( 0.dst == 1.dst );
13219 // // construct a replacement instruction that sets
13220 // // the destination to ( move's source register + one )
13221 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13222 // %}
13223 //
13224 // Implementation no longer uses movX instructions since
13225 // machine-independent system no longer uses CopyX nodes.
13226 //
13227 // peephole %{
13228 // peepmatch ( incI_eReg movI );
13229 // peepconstraint ( 0.dst == 1.dst );
13230 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13231 // %}
13232 //
13233 // peephole %{
13234 // peepmatch ( decI_eReg movI );
13235 // peepconstraint ( 0.dst == 1.dst );
13236 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13237 // %}
13238 //
13239 // peephole %{
13240 // peepmatch ( addI_eReg_imm movI );
13241 // peepconstraint ( 0.dst == 1.dst );
13242 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13243 // %}
13244 //
13245 // peephole %{
13246 // peepmatch ( addP_eReg_imm movP );
13247 // peepconstraint ( 0.dst == 1.dst );
13248 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13249 // %}
13250
13251 // // Change load of spilled value to only a spill
13252 // instruct storeI(memory mem, rRegI src) %{
13253 // match(Set mem (StoreI mem src));
13254 // %}
13255 //
13256 // instruct loadI(rRegI dst, memory mem) %{
13257 // match(Set dst (LoadI mem));
13258 // %}
13259 //
13260 peephole %{
13261 peepmatch ( loadI storeI );
13262 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13263 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13264 %}
13265
13266 //----------SMARTSPILL RULES---------------------------------------------------
13267 // These must follow all instruction definitions as they use the names
13268 // defined in the instructions definitions.