src/cpu/x86/vm/x86_64.ad
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hotspot Cdiff src/cpu/x86/vm/x86_64.ad
src/cpu/x86/vm/x86_64.ad
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rev 5902 : 8027754: Enable loop optimizations for loops with MathExact inside
*** 1655,1676 ****
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
return PTR_RBP_REG_mask();
}
- const RegMask Matcher::mathExactI_result_proj_mask() {
- return INT_RAX_REG_mask();
- }
-
- const RegMask Matcher::mathExactL_result_proj_mask() {
- return LONG_RAX_REG_mask();
- }
-
- const RegMask Matcher::mathExactI_flags_proj_mask() {
- return INT_FLAGS_mask();
- }
-
%}
//----------ENCODING BLOCK-----------------------------------------------------
// This block specifies the encoding classes used by the compiler to
// output byte streams. Encoding classes are parameterized macros
--- 1655,1664 ----
*** 6961,7046 ****
%}
//----------Arithmetic Instructions--------------------------------------------
//----------Addition Instructions----------------------------------------------
- instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
- %{
- match(AddExactI dst src);
- effect(DEF cr);
-
- format %{ "addl $dst, $src\t# addExact int" %}
- ins_encode %{
- __ addl($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
- %{
- match(AddExactI dst src);
- effect(DEF cr);
-
- format %{ "addl $dst, $src\t# addExact int" %}
- ins_encode %{
- __ addl($dst$$Register, $src$$constant);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
- %{
- match(AddExactI dst (LoadI src));
- effect(DEF cr);
-
- ins_cost(125); // XXX
- format %{ "addl $dst, $src\t# addExact int" %}
- ins_encode %{
- __ addl($dst$$Register, $src$$Address);
- %}
-
- ins_pipe(ialu_reg_mem);
- %}
-
- instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
- %{
- match(AddExactL dst src);
- effect(DEF cr);
-
- format %{ "addq $dst, $src\t# addExact long" %}
- ins_encode %{
- __ addq($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
- %{
- match(AddExactL dst src);
- effect(DEF cr);
-
- format %{ "addq $dst, $src\t# addExact long" %}
- ins_encode %{
- __ addq($dst$$Register, $src$$constant);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
- %{
- match(AddExactL dst (LoadL src));
- effect(DEF cr);
-
- ins_cost(125); // XXX
- format %{ "addq $dst, $src\t# addExact long" %}
- ins_encode %{
- __ addq($dst$$Register, $src$$Address);
- %}
-
- ins_pipe(ialu_reg_mem);
- %}
-
instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
%{
match(Set dst (AddI dst src));
effect(KILL cr);
--- 6949,6958 ----
*** 7649,7732 ****
opcode(0x81); /* Opcode 81 /5 id */
ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
ins_pipe(ialu_mem_imm);
%}
- instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
- %{
- match(SubExactI dst src);
- effect(DEF cr);
-
- format %{ "subl $dst, $src\t# subExact int" %}
- ins_encode %{
- __ subl($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
- %{
- match(SubExactI dst src);
- effect(DEF cr);
-
- format %{ "subl $dst, $src\t# subExact int" %}
- ins_encode %{
- __ subl($dst$$Register, $src$$constant);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
- %{
- match(SubExactI dst (LoadI src));
- effect(DEF cr);
-
- ins_cost(125);
- format %{ "subl $dst, $src\t# subExact int" %}
- ins_encode %{
- __ subl($dst$$Register, $src$$Address);
- %}
- ins_pipe(ialu_reg_mem);
- %}
-
- instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
- %{
- match(SubExactL dst src);
- effect(DEF cr);
-
- format %{ "subq $dst, $src\t# subExact long" %}
- ins_encode %{
- __ subq($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
- %{
- match(SubExactL dst (LoadL src));
- effect(DEF cr);
-
- format %{ "subq $dst, $src\t# subExact long" %}
- ins_encode %{
- __ subq($dst$$Register, $src$$constant);
- %}
- ins_pipe(ialu_reg_reg);
- %}
-
- instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
- %{
- match(SubExactI dst src);
- effect(DEF cr);
-
- ins_cost(125);
- format %{ "subq $dst, $src\t# subExact long" %}
- ins_encode %{
- __ subq($dst$$Register, $src$$Address);
- %}
- ins_pipe(ialu_reg_mem);
- %}
-
instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
%{
match(Set dst (SubL dst src));
effect(KILL cr);
--- 7561,7570 ----
*** 7839,7873 ****
opcode(0xF7, 0x03); // Opcode F7 /3
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_reg);
%}
- instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
- %{
- match(NegExactI dst);
- effect(KILL cr);
-
- format %{ "negl $dst\t# negExact int" %}
- ins_encode %{
- __ negl($dst$$Register);
- %}
- ins_pipe(ialu_reg);
- %}
-
- instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
- %{
- match(NegExactL dst);
- effect(KILL cr);
-
- format %{ "negq $dst\t# negExact long" %}
- ins_encode %{
- __ negq($dst$$Register);
- %}
- ins_pipe(ialu_reg);
- %}
-
-
//----------Multiplication/Division Instructions-------------------------------
// Integer Multiplication Instructions
// Multiply Register
instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
--- 7677,7686 ----
*** 7980,8069 ****
opcode(0xF7, 0x5); /* Opcode F7 /5 */
ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
ins_pipe(ialu_reg_reg_alu0);
%}
-
- instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
- %{
- match(MulExactI dst src);
- effect(DEF cr);
-
- ins_cost(300);
- format %{ "imull $dst, $src\t# mulExact int" %}
- ins_encode %{
- __ imull($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg_alu0);
- %}
-
-
- instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
- %{
- match(MulExactI src imm);
- effect(DEF cr);
-
- ins_cost(300);
- format %{ "imull $dst, $src, $imm\t# mulExact int" %}
- ins_encode %{
- __ imull($dst$$Register, $src$$Register, $imm$$constant);
- %}
- ins_pipe(ialu_reg_reg_alu0);
- %}
-
- instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
- %{
- match(MulExactI dst (LoadI src));
- effect(DEF cr);
-
- ins_cost(350);
- format %{ "imull $dst, $src\t# mulExact int" %}
- ins_encode %{
- __ imull($dst$$Register, $src$$Address);
- %}
- ins_pipe(ialu_reg_mem_alu0);
- %}
-
- instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
- %{
- match(MulExactL dst src);
- effect(DEF cr);
-
- ins_cost(300);
- format %{ "imulq $dst, $src\t# mulExact long" %}
- ins_encode %{
- __ imulq($dst$$Register, $src$$Register);
- %}
- ins_pipe(ialu_reg_reg_alu0);
- %}
-
- instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
- %{
- match(MulExactL src imm);
- effect(DEF cr);
-
- ins_cost(300);
- format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
- ins_encode %{
- __ imulq($dst$$Register, $src$$Register, $imm$$constant);
- %}
- ins_pipe(ialu_reg_reg_alu0);
- %}
-
- instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
- %{
- match(MulExactL dst (LoadL src));
- effect(DEF cr);
-
- ins_cost(350);
- format %{ "imulq $dst, $src\t# mulExact long" %}
- ins_encode %{
- __ imulq($dst$$Register, $src$$Address);
- %}
- ins_pipe(ialu_reg_mem_alu0);
- %}
-
instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
rFlagsReg cr)
%{
match(Set rax (DivI rax div));
effect(KILL rdx, KILL cr);
--- 7793,7802 ----
*** 10668,10677 ****
--- 10401,10580 ----
$tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
%}
ins_pipe( pipe_slow );
%}
+ //----------Overflow Math Instructions-----------------------------------------
+
+ instruct addofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
+ %{
+ match(Set cr (OverflowAddI op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+
+ format %{ "addl $op1, $op2 #overflow check int" %}
+
+ ins_encode %{
+ __ addl($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct addofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
+ %{
+ match(Set cr (OverflowAddI op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+
+ format %{ "addl $op1, $op2 #overflow check int" %}
+
+ ins_encode %{
+ __ addl($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct addofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
+ %{
+ match(Set cr (OverflowAddL op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+
+ format %{ "addq $op1, $op2 #overflow check long" %}
+ ins_encode %{
+ __ addq($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct addofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
+ %{
+ match(Set cr (OverflowAddL op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+ ins_encode %{
+ __ addq($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct subofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
+ %{
+ match(Set cr (OverflowSubI op1 op2));
+ effect(DEF cr, USE op1, USE op2);
+
+ format %{ "cmpl $op1, $op2 #overflow check int" %}
+ ins_encode %{
+ __ cmpl($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct subofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
+ %{
+ match(Set cr (OverflowSubI op1 op2));
+ effect(DEF cr, USE op1, USE op2);
+
+ format %{ "cmpl $op1, $op2 #overflow check int" %}
+ ins_encode %{
+ __ cmpl($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct subofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
+ %{
+ match(Set cr (OverflowSubL op1 op2));
+ effect(DEF cr, USE op1, USE op2);
+
+ format %{ "cmpq $op1, $op2 #overflow check long" %}
+ ins_encode %{
+ __ cmpq($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct subofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
+ %{
+ match(Set cr (OverflowSubL op1 op2));
+ effect(DEF cr, USE op1, USE op2);
+
+ format %{ "cmpq $op1, $op2 #overflow check long" %}
+ ins_encode %{
+ __ cmpq($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct negofI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
+ %{
+ match(Set cr (OverflowSubI zero op2));
+ effect(DEF cr, USE_KILL op2);
+
+ format %{ "negl $op2 #overflow check int" %}
+ ins_encode %{
+ __ negl($op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct negofL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
+ %{
+ match(Set cr (OverflowSubL zero op2));
+ effect(DEF cr, USE_KILL op2);
+
+ format %{ "negq $op2 #overflow check long" %}
+ ins_encode %{
+ __ negq($op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+ %}
+
+ instruct mulofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
+ %{
+ match(Set cr (OverflowMulI op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+
+ format %{ "imull $op1, $op2 #overflow check int" %}
+ ins_encode %{
+ __ imull($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg_alu0);
+ %}
+
+ instruct mulofI_rReg_imm(rFlagsReg cr, rax_RegI op1, rRegI op2, immI op3)
+ %{
+ match(Set cr (OverflowMulI op2 op3));
+ effect(DEF cr, KILL op1, USE op2, USE op3);
+
+ format %{ "imull $op1, $op2, $op3 #overflow check int" %}
+ ins_encode %{
+ __ imull($op1$$Register, $op2$$Register, $op3$$constant);
+ %}
+ ins_pipe(ialu_reg_reg_alu0);
+ %}
+
+ instruct mulofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
+ %{
+ match(Set cr (OverflowMulL op1 op2));
+ effect(DEF cr, USE_KILL op1, USE op2);
+
+ format %{ "imulq $op1, $op2 #overflow check long" %}
+ ins_encode %{
+ __ imulq($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg_alu0);
+ %}
+
+ instruct mulofL_rReg_imm(rFlagsReg cr, rax_RegL op1, rRegL op2, immL32 op3)
+ %{
+ match(Set cr (OverflowMulL op2 op3));
+ effect(DEF cr, KILL op1, USE op2, USE op3);
+
+ format %{ "imulq $op1, $op2 #overflow check long" %}
+ ins_encode %{
+ __ imulq($op1$$Register, $op2$$Register, $op3$$constant);
+ %}
+ ins_pipe(ialu_reg_reg_alu0);
+ %}
+
//----------Control Flow Instructions------------------------------------------
// Signed compare Instructions
// XXX more variants!!
src/cpu/x86/vm/x86_64.ad
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