1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
577
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
589
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
595
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
601
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
607
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
611
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
615
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
623
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
631
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
636
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
641
642
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
645
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
656
657
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
660
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
675
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
688
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
697
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
710
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
721
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
732
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
744
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
749
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
758
759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
773
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
780
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
797
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
809
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
830
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
865
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
905
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
911
912 uint index = src2_enc;
913 int disp = disp32;
914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
923
924 // We should have a compiler bailout here rather than a guarantee.
925 // Better yet would be some mechanism to handle variable-size matches correctly.
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
927
928 if( disp == 0 ) {
929 // use reg-reg form
930 // bit 13 is already zero
931 instr |= index;
932 } else {
933 // use reg-imm form
934 instr |= 0x00002000; // set bit 13 to one
935 instr |= disp & 0x1FFF;
936 }
937
938 cbuf.insts()->emit_int32(instr);
939
940 #ifdef ASSERT
941 {
942 MacroAssembler _masm(&cbuf);
943 if (is_verified_oop_base) {
944 __ verify_oop(reg_to_register_object(src1_enc));
945 }
946 if (is_verified_oop_store) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 if (tmp_enc != -1) {
950 __ mov(O7, reg_to_register_object(tmp_enc));
951 }
952 if (is_verified_oop_load) {
953 __ verify_oop(reg_to_register_object(dst_enc));
954 }
955 }
956 #endif
957 }
958
959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
960 // The method which records debug information at every safepoint
961 // expects the call to be the first instruction in the snippet as
962 // it creates a PcDesc structure which tracks the offset of a call
963 // from the start of the codeBlob. This offset is computed as
964 // code_end() - code_begin() of the code which has been emitted
965 // so far.
966 // In this particular case we have skirted around the problem by
967 // putting the "mov" instruction in the delay slot but the problem
968 // may bite us again at some other point and a cleaner/generic
969 // solution using relocations would be needed.
970 MacroAssembler _masm(&cbuf);
971 __ set_inst_mark();
972
973 // We flush the current window just so that there is a valid stack copy
974 // the fact that the current window becomes active again instantly is
975 // not a problem there is nothing live in it.
976
977 #ifdef ASSERT
978 int startpos = __ offset();
979 #endif /* ASSERT */
980
981 __ call((address)entry_point, rtype);
982
983 if (preserve_g2) __ delayed()->mov(G2, L7);
984 else __ delayed()->nop();
985
986 if (preserve_g2) __ mov(L7, G2);
987
988 #ifdef ASSERT
989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
990 #ifdef _LP64
991 // Trash argument dump slots.
992 __ set(0xb0b8ac0db0b8ac0d, G1);
993 __ mov(G1, G5);
994 __ stx(G1, SP, STACK_BIAS + 0x80);
995 __ stx(G1, SP, STACK_BIAS + 0x88);
996 __ stx(G1, SP, STACK_BIAS + 0x90);
997 __ stx(G1, SP, STACK_BIAS + 0x98);
998 __ stx(G1, SP, STACK_BIAS + 0xA0);
999 __ stx(G1, SP, STACK_BIAS + 0xA8);
1000 #else // _LP64
1001 // this is also a native call, so smash the first 7 stack locations,
1002 // and the various registers
1003
1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1005 // while [SP+0x44..0x58] are the argument dump slots.
1006 __ set((intptr_t)0xbaadf00d, G1);
1007 __ mov(G1, G5);
1008 __ sllx(G1, 32, G1);
1009 __ or3(G1, G5, G1);
1010 __ mov(G1, G5);
1011 __ stx(G1, SP, 0x40);
1012 __ stx(G1, SP, 0x48);
1013 __ stx(G1, SP, 0x50);
1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1015 #endif // _LP64
1016 }
1017 #endif /*ASSERT*/
1018 }
1019
1020 //=============================================================================
1021 // REQUIRED FUNCTIONALITY for encoding
1022 void emit_lo(CodeBuffer &cbuf, int val) { }
1023 void emit_hi(CodeBuffer &cbuf, int val) { }
1024
1025
1026 //=============================================================================
1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1028
1029 int Compile::ConstantTable::calculate_table_base_offset() const {
1030 if (UseRDPCForConstantTableBase) {
1031 // The table base offset might be less but then it fits into
1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1033 return Assembler::min_simm13();
1034 } else {
1035 int offset = -(size() / 2);
1036 if (!Assembler::is_simm13(offset)) {
1037 offset = Assembler::min_simm13();
1038 }
1039 return offset;
1040 }
1041 }
1042
1043 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1044 Compile* C = ra_->C;
1045 Compile::ConstantTable& constant_table = C->constant_table();
1046 MacroAssembler _masm(&cbuf);
1047
1048 Register r = as_Register(ra_->get_encode(this));
1049 CodeSection* consts_section = __ code()->consts();
1050 int consts_size = consts_section->align_at_start(consts_section->size());
1051 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1052
1053 if (UseRDPCForConstantTableBase) {
1054 // For the following RDPC logic to work correctly the consts
1055 // section must be allocated right before the insts section. This
1056 // assert checks for that. The layout and the SECT_* constants
1057 // are defined in src/share/vm/asm/codeBuffer.hpp.
1058 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1059 int insts_offset = __ offset();
1060
1061 // Layout:
1062 //
1063 // |----------- consts section ------------|----------- insts section -----------...
1064 // |------ constant table -----|- padding -|------------------x----
1065 // \ current PC (RDPC instruction)
1066 // |<------------- consts_size ----------->|<- insts_offset ->|
1067 // \ table base
1068 // The table base offset is later added to the load displacement
1069 // so it has to be negative.
1070 int table_base_offset = -(consts_size + insts_offset);
1071 int disp;
1072
1073 // If the displacement from the current PC to the constant table
1074 // base fits into simm13 we set the constant table base to the
1075 // current PC.
1076 if (Assembler::is_simm13(table_base_offset)) {
1077 constant_table.set_table_base_offset(table_base_offset);
1078 disp = 0;
1079 } else {
1080 // Otherwise we set the constant table base offset to the
1081 // maximum negative displacement of load instructions to keep
1082 // the disp as small as possible:
1083 //
1084 // |<------------- consts_size ----------->|<- insts_offset ->|
1085 // |<--------- min_simm13 --------->|<-------- disp --------->|
1086 // \ table base
1087 table_base_offset = Assembler::min_simm13();
1088 constant_table.set_table_base_offset(table_base_offset);
1089 disp = (consts_size + insts_offset) + table_base_offset;
1090 }
1091
1092 __ rdpc(r);
1093
1094 if (disp != 0) {
1095 assert(r != O7, "need temporary");
1096 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1097 }
1098 }
1099 else {
1100 // Materialize the constant table base.
1101 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1102 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1103 AddressLiteral base(baseaddr, rspec);
1104 __ set(base, r);
1105 }
1106 }
1107
1108 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1109 if (UseRDPCForConstantTableBase) {
1110 // This is really the worst case but generally it's only 1 instruction.
1111 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1112 } else {
1113 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1114 }
1115 }
1116
1117 #ifndef PRODUCT
1118 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1119 char reg[128];
1120 ra_->dump_register(this, reg);
1121 if (UseRDPCForConstantTableBase) {
1122 st->print("RDPC %s\t! constant table base", reg);
1123 } else {
1124 st->print("SET &constanttable,%s\t! constant table base", reg);
1125 }
1126 }
1127 #endif
1128
1129
1130 //=============================================================================
1131
1132 #ifndef PRODUCT
1133 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1134 Compile* C = ra_->C;
1135
1136 for (int i = 0; i < OptoPrologueNops; i++) {
1137 st->print_cr("NOP"); st->print("\t");
1138 }
1139
1140 if( VerifyThread ) {
1141 st->print_cr("Verify_Thread"); st->print("\t");
1142 }
1143
1144 size_t framesize = C->frame_slots() << LogBytesPerInt;
1145
1146 // Calls to C2R adapters often do not accept exceptional returns.
1147 // We require that their callers must bang for them. But be careful, because
1148 // some VM calls (such as call site linkage) can use several kilobytes of
1149 // stack. But the stack safety zone should account for that.
1150 // See bugs 4446381, 4468289, 4497237.
1151 if (C->need_stack_bang(framesize)) {
1152 st->print_cr("! stack bang"); st->print("\t");
1153 }
1154
1155 if (Assembler::is_simm13(-framesize)) {
1156 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1157 } else {
1158 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1159 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1160 st->print ("SAVE R_SP,R_G3,R_SP");
1161 }
1162
1163 }
1164 #endif
1165
1166 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1167 Compile* C = ra_->C;
1168 MacroAssembler _masm(&cbuf);
1169
1170 for (int i = 0; i < OptoPrologueNops; i++) {
1171 __ nop();
1172 }
1173
1174 __ verify_thread();
1175
1176 size_t framesize = C->frame_slots() << LogBytesPerInt;
1177 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1178 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1179
1180 // Calls to C2R adapters often do not accept exceptional returns.
1181 // We require that their callers must bang for them. But be careful, because
1182 // some VM calls (such as call site linkage) can use several kilobytes of
1183 // stack. But the stack safety zone should account for that.
1184 // See bugs 4446381, 4468289, 4497237.
1185 if (C->need_stack_bang(framesize)) {
1186 __ generate_stack_overflow_check(framesize);
1187 }
1188
1189 if (Assembler::is_simm13(-framesize)) {
1190 __ save(SP, -framesize, SP);
1191 } else {
1192 __ sethi(-framesize & ~0x3ff, G3);
1193 __ add(G3, -framesize & 0x3ff, G3);
1194 __ save(SP, G3, SP);
1195 }
1196 C->set_frame_complete( __ offset() );
1197
1198 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1199 // NOTE: We set the table base offset here because users might be
1200 // emitted before MachConstantBaseNode.
1201 Compile::ConstantTable& constant_table = C->constant_table();
1202 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1203 }
1204 }
1205
1206 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1207 return MachNode::size(ra_);
1208 }
1209
1210 int MachPrologNode::reloc() const {
1211 return 10; // a large enough number
1212 }
1213
1214 //=============================================================================
1215 #ifndef PRODUCT
1216 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1217 Compile* C = ra_->C;
1218
1219 if( do_polling() && ra_->C->is_method_compilation() ) {
1220 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1221 #ifdef _LP64
1222 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1223 #else
1224 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1225 #endif
1226 }
1227
1228 if( do_polling() )
1229 st->print("RET\n\t");
1230
1231 st->print("RESTORE");
1232 }
1233 #endif
1234
1235 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1236 MacroAssembler _masm(&cbuf);
1237 Compile* C = ra_->C;
1238
1239 __ verify_thread();
1240
1241 // If this does safepoint polling, then do it here
1242 if( do_polling() && ra_->C->is_method_compilation() ) {
1243 AddressLiteral polling_page(os::get_polling_page());
1244 __ sethi(polling_page, L0);
1245 __ relocate(relocInfo::poll_return_type);
1246 __ ld_ptr( L0, 0, G0 );
1247 }
1248
1249 // If this is a return, then stuff the restore in the delay slot
1250 if( do_polling() ) {
1251 __ ret();
1252 __ delayed()->restore();
1253 } else {
1254 __ restore();
1255 }
1256 }
1257
1258 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachEpilogNode::reloc() const {
1263 return 16; // a large enough number
1264 }
1265
1266 const Pipeline * MachEpilogNode::pipeline() const {
1267 return MachNode::pipeline_class();
1268 }
1269
1270 int MachEpilogNode::safepoint_offset() const {
1271 assert( do_polling(), "no return for this epilog node");
1272 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1273 }
1274
1275 //=============================================================================
1276
1277 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1278 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1279 static enum RC rc_class( OptoReg::Name reg ) {
1280 if( !OptoReg::is_valid(reg) ) return rc_bad;
1281 if (OptoReg::is_stack(reg)) return rc_stack;
1282 VMReg r = OptoReg::as_VMReg(reg);
1283 if (r->is_Register()) return rc_int;
1284 assert(r->is_FloatRegister(), "must be");
1285 return rc_float;
1286 }
1287
1288 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1289 if (cbuf) {
1290 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1291 }
1292 #ifndef PRODUCT
1293 else if (!do_size) {
1294 if (size != 0) st->print("\n\t");
1295 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1296 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1297 }
1298 #endif
1299 return size+4;
1300 }
1301
1302 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1303 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1304 #ifndef PRODUCT
1305 else if( !do_size ) {
1306 if( size != 0 ) st->print("\n\t");
1307 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1308 }
1309 #endif
1310 return size+4;
1311 }
1312
1313 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1314 PhaseRegAlloc *ra_,
1315 bool do_size,
1316 outputStream* st ) const {
1317 // Get registers to move
1318 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1319 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1320 OptoReg::Name dst_second = ra_->get_reg_second(this );
1321 OptoReg::Name dst_first = ra_->get_reg_first(this );
1322
1323 enum RC src_second_rc = rc_class(src_second);
1324 enum RC src_first_rc = rc_class(src_first);
1325 enum RC dst_second_rc = rc_class(dst_second);
1326 enum RC dst_first_rc = rc_class(dst_first);
1327
1328 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1329
1330 // Generate spill code!
1331 int size = 0;
1332
1333 if( src_first == dst_first && src_second == dst_second )
1334 return size; // Self copy, no move
1335
1336 // --------------------------------------
1337 // Check for mem-mem move. Load into unused float registers and fall into
1338 // the float-store case.
1339 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1340 int offset = ra_->reg2offset(src_first);
1341 // Further check for aligned-adjacent pair, so we can use a double load
1342 if( (src_first&1)==0 && src_first+1 == src_second ) {
1343 src_second = OptoReg::Name(R_F31_num);
1344 src_second_rc = rc_float;
1345 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1346 } else {
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1348 }
1349 src_first = OptoReg::Name(R_F30_num);
1350 src_first_rc = rc_float;
1351 }
1352
1353 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1354 int offset = ra_->reg2offset(src_second);
1355 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1356 src_second = OptoReg::Name(R_F31_num);
1357 src_second_rc = rc_float;
1358 }
1359
1360 // --------------------------------------
1361 // Check for float->int copy; requires a trip through memory
1362 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1363 int offset = frame::register_save_words*wordSize;
1364 if (cbuf) {
1365 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1366 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1367 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1368 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1369 }
1370 #ifndef PRODUCT
1371 else if (!do_size) {
1372 if (size != 0) st->print("\n\t");
1373 st->print( "SUB R_SP,16,R_SP\n");
1374 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1375 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1376 st->print("\tADD R_SP,16,R_SP\n");
1377 }
1378 #endif
1379 size += 16;
1380 }
1381
1382 // Check for float->int copy on T4
1383 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1384 // Further check for aligned-adjacent pair, so we can use a double move
1385 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1386 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1387 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1388 }
1389 // Check for int->float copy on T4
1390 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1395 }
1396
1397 // --------------------------------------
1398 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1399 // In such cases, I have to do the big-endian swap. For aligned targets, the
1400 // hardware does the flop for me. Doubles are always aligned, so no problem
1401 // there. Misaligned sources only come from native-long-returns (handled
1402 // special below).
1403 #ifndef _LP64
1404 if( src_first_rc == rc_int && // source is already big-endian
1405 src_second_rc != rc_bad && // 64-bit move
1406 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1407 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1408 // Do the big-endian flop.
1409 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1410 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1411 }
1412 #endif
1413
1414 // --------------------------------------
1415 // Check for integer reg-reg copy
1416 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1417 #ifndef _LP64
1418 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1419 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1420 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1421 // operand contains the least significant word of the 64-bit value and vice versa.
1422 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1423 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1424 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1425 if( cbuf ) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1427 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1428 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1429 #ifndef PRODUCT
1430 } else if( !do_size ) {
1431 if( size != 0 ) st->print("\n\t");
1432 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1433 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1434 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1435 #endif
1436 }
1437 return size+12;
1438 }
1439 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1440 // returning a long value in I0/I1
1441 // a SpillCopy must be able to target a return instruction's reg_class
1442 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1443 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1444 // operand contains the least significant word of the 64-bit value and vice versa.
1445 OptoReg::Name tdest = dst_first;
1446
1447 if (src_first == dst_first) {
1448 tdest = OptoReg::Name(R_O7_num);
1449 size += 4;
1450 }
1451
1452 if( cbuf ) {
1453 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1454 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1455 // ShrL_reg_imm6
1456 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1457 // ShrR_reg_imm6 src, 0, dst
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1459 if (tdest != dst_first) {
1460 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1461 }
1462 }
1463 #ifndef PRODUCT
1464 else if( !do_size ) {
1465 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1466 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1467 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1468 if (tdest != dst_first) {
1469 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1470 }
1471 }
1472 #endif // PRODUCT
1473 return size+8;
1474 }
1475 #endif // !_LP64
1476 // Else normal reg-reg copy
1477 assert( src_second != dst_first, "smashed second before evacuating it" );
1478 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1479 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1480 // This moves an aligned adjacent pair.
1481 // See if we are done.
1482 if( src_first+1 == src_second && dst_first+1 == dst_second )
1483 return size;
1484 }
1485
1486 // Check for integer store
1487 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1488 int offset = ra_->reg2offset(dst_first);
1489 // Further check for aligned-adjacent pair, so we can use a double store
1490 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1491 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1492 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1493 }
1494
1495 // Check for integer load
1496 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1497 int offset = ra_->reg2offset(src_first);
1498 // Further check for aligned-adjacent pair, so we can use a double load
1499 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1500 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1501 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1502 }
1503
1504 // Check for float reg-reg copy
1505 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1506 // Further check for aligned-adjacent pair, so we can use a double move
1507 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1508 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1509 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1510 }
1511
1512 // Check for float store
1513 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1514 int offset = ra_->reg2offset(dst_first);
1515 // Further check for aligned-adjacent pair, so we can use a double store
1516 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1517 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1518 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1519 }
1520
1521 // Check for float load
1522 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1523 int offset = ra_->reg2offset(src_first);
1524 // Further check for aligned-adjacent pair, so we can use a double load
1525 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1526 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1527 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1528 }
1529
1530 // --------------------------------------------------------------------
1531 // Check for hi bits still needing moving. Only happens for misaligned
1532 // arguments to native calls.
1533 if( src_second == dst_second )
1534 return size; // Self copy; no move
1535 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1536
1537 #ifndef _LP64
1538 // In the LP64 build, all registers can be moved as aligned/adjacent
1539 // pairs, so there's never any need to move the high bits separately.
1540 // The 32-bit builds have to deal with the 32-bit ABI which can force
1541 // all sorts of silly alignment problems.
1542
1543 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1544 // 32-bits of a 64-bit register, but are needed in low bits of another
1545 // register (else it's a hi-bits-to-hi-bits copy which should have
1546 // happened already as part of a 64-bit move)
1547 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1548 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1549 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1550 // Shift src_second down to dst_second's low bits.
1551 if( cbuf ) {
1552 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1553 #ifndef PRODUCT
1554 } else if( !do_size ) {
1555 if( size != 0 ) st->print("\n\t");
1556 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1557 #endif
1558 }
1559 return size+4;
1560 }
1561
1562 // Check for high word integer store. Must down-shift the hi bits
1563 // into a temp register, then fall into the case of storing int bits.
1564 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1565 // Shift src_second down to dst_second's low bits.
1566 if( cbuf ) {
1567 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1568 #ifndef PRODUCT
1569 } else if( !do_size ) {
1570 if( size != 0 ) st->print("\n\t");
1571 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1572 #endif
1573 }
1574 size+=4;
1575 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1576 }
1577
1578 // Check for high word integer load
1579 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1580 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1581
1582 // Check for high word integer store
1583 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1584 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1585
1586 // Check for high word float store
1587 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1588 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1589
1590 #endif // !_LP64
1591
1592 Unimplemented();
1593 }
1594
1595 #ifndef PRODUCT
1596 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1597 implementation( NULL, ra_, false, st );
1598 }
1599 #endif
1600
1601 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1602 implementation( &cbuf, ra_, false, NULL );
1603 }
1604
1605 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1606 return implementation( NULL, ra_, true, NULL );
1607 }
1608
1609 //=============================================================================
1610 #ifndef PRODUCT
1611 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1612 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1613 }
1614 #endif
1615
1616 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1617 MacroAssembler _masm(&cbuf);
1618 for(int i = 0; i < _count; i += 1) {
1619 __ nop();
1620 }
1621 }
1622
1623 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1624 return 4 * _count;
1625 }
1626
1627
1628 //=============================================================================
1629 #ifndef PRODUCT
1630 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1631 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1632 int reg = ra_->get_reg_first(this);
1633 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1634 }
1635 #endif
1636
1637 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1638 MacroAssembler _masm(&cbuf);
1639 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1640 int reg = ra_->get_encode(this);
1641
1642 if (Assembler::is_simm13(offset)) {
1643 __ add(SP, offset, reg_to_register_object(reg));
1644 } else {
1645 __ set(offset, O7);
1646 __ add(SP, O7, reg_to_register_object(reg));
1647 }
1648 }
1649
1650 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1651 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1652 assert(ra_ == ra_->C->regalloc(), "sanity");
1653 return ra_->C->scratch_emit_size(this);
1654 }
1655
1656 //=============================================================================
1657 #ifndef PRODUCT
1658 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1659 st->print_cr("\nUEP:");
1660 #ifdef _LP64
1661 if (UseCompressedClassPointers) {
1662 assert(Universe::heap() != NULL, "java heap should be initialized");
1663 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1664 if (Universe::narrow_klass_base() != 0) {
1665 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1666 if (Universe::narrow_klass_shift() != 0) {
1667 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1668 }
1669 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1670 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1671 } else {
1672 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1673 }
1674 } else {
1675 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 }
1677 st->print_cr("\tCMP R_G5,R_G3" );
1678 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1679 #else // _LP64
1680 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1681 st->print_cr("\tCMP R_G5,R_G3" );
1682 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1683 #endif // _LP64
1684 }
1685 #endif
1686
1687 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1688 MacroAssembler _masm(&cbuf);
1689 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1690 Register temp_reg = G3;
1691 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1692
1693 // Load klass from receiver
1694 __ load_klass(O0, temp_reg);
1695 // Compare against expected klass
1696 __ cmp(temp_reg, G5_ic_reg);
1697 // Branch to miss code, checks xcc or icc depending
1698 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1699 }
1700
1701 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1702 return MachNode::size(ra_);
1703 }
1704
1705
1706 //=============================================================================
1707
1708 uint size_exception_handler() {
1709 if (TraceJumps) {
1710 return (400); // just a guess
1711 }
1712 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1713 }
1714
1715 uint size_deopt_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1720 }
1721
1722 // Emit exception handler code.
1723 int emit_exception_handler(CodeBuffer& cbuf) {
1724 Register temp_reg = G3;
1725 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1726 MacroAssembler _masm(&cbuf);
1727
1728 address base =
1729 __ start_a_stub(size_exception_handler());
1730 if (base == NULL) return 0; // CodeBuffer::expand failed
1731
1732 int offset = __ offset();
1733
1734 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1735 __ delayed()->nop();
1736
1737 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1738
1739 __ end_a_stub();
1740
1741 return offset;
1742 }
1743
1744 int emit_deopt_handler(CodeBuffer& cbuf) {
1745 // Can't use any of the current frame's registers as we may have deopted
1746 // at a poll and everything (including G3) can be live.
1747 Register temp_reg = L0;
1748 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1749 MacroAssembler _masm(&cbuf);
1750
1751 address base =
1752 __ start_a_stub(size_deopt_handler());
1753 if (base == NULL) return 0; // CodeBuffer::expand failed
1754
1755 int offset = __ offset();
1756 __ save_frame(0);
1757 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1758 __ delayed()->restore();
1759
1760 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1761
1762 __ end_a_stub();
1763 return offset;
1764
1765 }
1766
1767 // Given a register encoding, produce a Integer Register object
1768 static Register reg_to_register_object(int register_encoding) {
1769 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1770 return as_Register(register_encoding);
1771 }
1772
1773 // Given a register encoding, produce a single-precision Float Register object
1774 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1775 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1776 return as_SingleFloatRegister(register_encoding);
1777 }
1778
1779 // Given a register encoding, produce a double-precision Float Register object
1780 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1781 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1782 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1783 return as_DoubleFloatRegister(register_encoding);
1784 }
1785
1786 const bool Matcher::match_rule_supported(int opcode) {
1787 if (!has_match_rule(opcode))
1788 return false;
1789
1790 switch (opcode) {
1791 case Op_CountLeadingZerosI:
1792 case Op_CountLeadingZerosL:
1793 case Op_CountTrailingZerosI:
1794 case Op_CountTrailingZerosL:
1795 case Op_PopCountI:
1796 case Op_PopCountL:
1797 if (!UsePopCountInstruction)
1798 return false;
1799 case Op_CompareAndSwapL:
1800 #ifdef _LP64
1801 case Op_CompareAndSwapP:
1802 #endif
1803 if (!VM_Version::supports_cx8())
1804 return false;
1805 break;
1806 }
1807
1808 return true; // Per default match rules are supported.
1809 }
1810
1811 int Matcher::regnum_to_fpu_offset(int regnum) {
1812 return regnum - 32; // The FP registers are in the second chunk
1813 }
1814
1815 #ifdef ASSERT
1816 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1817 #endif
1818
1819 // Vector width in bytes
1820 const int Matcher::vector_width_in_bytes(BasicType bt) {
1821 assert(MaxVectorSize == 8, "");
1822 return 8;
1823 }
1824
1825 // Vector ideal reg
1826 const int Matcher::vector_ideal_reg(int size) {
1827 assert(MaxVectorSize == 8, "");
1828 return Op_RegD;
1829 }
1830
1831 const int Matcher::vector_shift_count_ideal_reg(int size) {
1832 fatal("vector shift is not supported");
1833 return Node::NotAMachineReg;
1834 }
1835
1836 // Limits on vector size (number of elements) loaded into vector.
1837 const int Matcher::max_vector_size(const BasicType bt) {
1838 assert(is_java_primitive(bt), "only primitive type vectors");
1839 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1840 }
1841
1842 const int Matcher::min_vector_size(const BasicType bt) {
1843 return max_vector_size(bt); // Same as max.
1844 }
1845
1846 // SPARC doesn't support misaligned vectors store/load.
1847 const bool Matcher::misaligned_vectors_ok() {
1848 return false;
1849 }
1850
1851 // Current (2013) SPARC platforms need to read original key
1852 // to construct decryption expanded key
1853 const bool Matcher::pass_original_key_for_aes() {
1854 return true;
1855 }
1856
1857 // USII supports fxtof through the whole range of number, USIII doesn't
1858 const bool Matcher::convL2FSupported(void) {
1859 return VM_Version::has_fast_fxtof();
1860 }
1861
1862 // Is this branch offset short enough that a short branch can be used?
1863 //
1864 // NOTE: If the platform does not provide any short branch variants, then
1865 // this method should return false for offset 0.
1866 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1867 // The passed offset is relative to address of the branch.
1868 // Don't need to adjust the offset.
1869 return UseCBCond && Assembler::is_simm12(offset);
1870 }
1871
1872 const bool Matcher::isSimpleConstant64(jlong value) {
1873 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1874 // Depends on optimizations in MacroAssembler::setx.
1875 int hi = (int)(value >> 32);
1876 int lo = (int)(value & ~0);
1877 return (hi == 0) || (hi == -1) || (lo == 0);
1878 }
1879
1880 // No scaling for the parameter the ClearArray node.
1881 const bool Matcher::init_array_count_is_in_bytes = true;
1882
1883 // Threshold size for cleararray.
1884 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1885
1886 // No additional cost for CMOVL.
1887 const int Matcher::long_cmove_cost() { return 0; }
1888
1889 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1890 const int Matcher::float_cmove_cost() {
1891 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1892 }
1893
1894 // Should the Matcher clone shifts on addressing modes, expecting them to
1895 // be subsumed into complex addressing expressions or compute them into
1896 // registers? True for Intel but false for most RISCs
1897 const bool Matcher::clone_shift_expressions = false;
1898
1899 // Do we need to mask the count passed to shift instructions or does
1900 // the cpu only look at the lower 5/6 bits anyway?
1901 const bool Matcher::need_masked_shift_count = false;
1902
1903 bool Matcher::narrow_oop_use_complex_address() {
1904 NOT_LP64(ShouldNotCallThis());
1905 assert(UseCompressedOops, "only for compressed oops code");
1906 return false;
1907 }
1908
1909 bool Matcher::narrow_klass_use_complex_address() {
1910 NOT_LP64(ShouldNotCallThis());
1911 assert(UseCompressedClassPointers, "only for compressed klass code");
1912 return false;
1913 }
1914
1915 // Is it better to copy float constants, or load them directly from memory?
1916 // Intel can load a float constant from a direct address, requiring no
1917 // extra registers. Most RISCs will have to materialize an address into a
1918 // register first, so they would do better to copy the constant from stack.
1919 const bool Matcher::rematerialize_float_constants = false;
1920
1921 // If CPU can load and store mis-aligned doubles directly then no fixup is
1922 // needed. Else we split the double into 2 integer pieces and move it
1923 // piece-by-piece. Only happens when passing doubles into C code as the
1924 // Java calling convention forces doubles to be aligned.
1925 #ifdef _LP64
1926 const bool Matcher::misaligned_doubles_ok = true;
1927 #else
1928 const bool Matcher::misaligned_doubles_ok = false;
1929 #endif
1930
1931 // No-op on SPARC.
1932 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1933 }
1934
1935 // Advertise here if the CPU requires explicit rounding operations
1936 // to implement the UseStrictFP mode.
1937 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1938
1939 // Are floats conerted to double when stored to stack during deoptimization?
1940 // Sparc does not handle callee-save floats.
1941 bool Matcher::float_in_double() { return false; }
1942
1943 // Do ints take an entire long register or just half?
1944 // Note that we if-def off of _LP64.
1945 // The relevant question is how the int is callee-saved. In _LP64
1946 // the whole long is written but de-opt'ing will have to extract
1947 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1948 #ifdef _LP64
1949 const bool Matcher::int_in_long = true;
1950 #else
1951 const bool Matcher::int_in_long = false;
1952 #endif
1953
1954 // Return whether or not this register is ever used as an argument. This
1955 // function is used on startup to build the trampoline stubs in generateOptoStub.
1956 // Registers not mentioned will be killed by the VM call in the trampoline, and
1957 // arguments in those registers not be available to the callee.
1958 bool Matcher::can_be_java_arg( int reg ) {
1959 // Standard sparc 6 args in registers
1960 if( reg == R_I0_num ||
1961 reg == R_I1_num ||
1962 reg == R_I2_num ||
1963 reg == R_I3_num ||
1964 reg == R_I4_num ||
1965 reg == R_I5_num ) return true;
1966 #ifdef _LP64
1967 // 64-bit builds can pass 64-bit pointers and longs in
1968 // the high I registers
1969 if( reg == R_I0H_num ||
1970 reg == R_I1H_num ||
1971 reg == R_I2H_num ||
1972 reg == R_I3H_num ||
1973 reg == R_I4H_num ||
1974 reg == R_I5H_num ) return true;
1975
1976 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1977 return true;
1978 }
1979
1980 #else
1981 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1982 // Longs cannot be passed in O regs, because O regs become I regs
1983 // after a 'save' and I regs get their high bits chopped off on
1984 // interrupt.
1985 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1986 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1987 #endif
1988 // A few float args in registers
1989 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1990
1991 return false;
1992 }
1993
1994 bool Matcher::is_spillable_arg( int reg ) {
1995 return can_be_java_arg(reg);
1996 }
1997
1998 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1999 // Use hardware SDIVX instruction when it is
2000 // faster than a code which use multiply.
2001 return VM_Version::has_fast_idiv();
2002 }
2003
2004 // Register for DIVI projection of divmodI
2005 RegMask Matcher::divI_proj_mask() {
2006 ShouldNotReachHere();
2007 return RegMask();
2008 }
2009
2010 // Register for MODI projection of divmodI
2011 RegMask Matcher::modI_proj_mask() {
2012 ShouldNotReachHere();
2013 return RegMask();
2014 }
2015
2016 // Register for DIVL projection of divmodL
2017 RegMask Matcher::divL_proj_mask() {
2018 ShouldNotReachHere();
2019 return RegMask();
2020 }
2021
2022 // Register for MODL projection of divmodL
2023 RegMask Matcher::modL_proj_mask() {
2024 ShouldNotReachHere();
2025 return RegMask();
2026 }
2027
2028 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2029 return L7_REGP_mask();
2030 }
2031
2032 %}
2033
2034
2035 // The intptr_t operand types, defined by textual substitution.
2036 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2037 #ifdef _LP64
2038 #define immX immL
2039 #define immX13 immL13
2040 #define immX13m7 immL13m7
2041 #define iRegX iRegL
2042 #define g1RegX g1RegL
2043 #else
2044 #define immX immI
2045 #define immX13 immI13
2046 #define immX13m7 immI13m7
2047 #define iRegX iRegI
2048 #define g1RegX g1RegI
2049 #endif
2050
2051 //----------ENCODING BLOCK-----------------------------------------------------
2052 // This block specifies the encoding classes used by the compiler to output
2053 // byte streams. Encoding classes are parameterized macros used by
2054 // Machine Instruction Nodes in order to generate the bit encoding of the
2055 // instruction. Operands specify their base encoding interface with the
2056 // interface keyword. There are currently supported four interfaces,
2057 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2058 // operand to generate a function which returns its register number when
2059 // queried. CONST_INTER causes an operand to generate a function which
2060 // returns the value of the constant when queried. MEMORY_INTER causes an
2061 // operand to generate four functions which return the Base Register, the
2062 // Index Register, the Scale Value, and the Offset Value of the operand when
2063 // queried. COND_INTER causes an operand to generate six functions which
2064 // return the encoding code (ie - encoding bits for the instruction)
2065 // associated with each basic boolean condition for a conditional instruction.
2066 //
2067 // Instructions specify two basic values for encoding. Again, a function
2068 // is available to check if the constant displacement is an oop. They use the
2069 // ins_encode keyword to specify their encoding classes (which must be
2070 // a sequence of enc_class names, and their parameters, specified in
2071 // the encoding block), and they use the
2072 // opcode keyword to specify, in order, their primary, secondary, and
2073 // tertiary opcode. Only the opcode sections which a particular instruction
2074 // needs for encoding need to be specified.
2075 encode %{
2076 enc_class enc_untested %{
2077 #ifdef ASSERT
2078 MacroAssembler _masm(&cbuf);
2079 __ untested("encoding");
2080 #endif
2081 %}
2082
2083 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2084 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2085 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2086 %}
2087
2088 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2089 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2090 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2091 %}
2092
2093 enc_class form3_mem_prefetch_read( memory mem ) %{
2094 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2095 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2096 %}
2097
2098 enc_class form3_mem_prefetch_write( memory mem ) %{
2099 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2100 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2101 %}
2102
2103 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2104 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2105 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2106 guarantee($mem$$index == R_G0_enc, "double index?");
2107 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2108 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2109 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2110 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2111 %}
2112
2113 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2114 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2115 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2116 guarantee($mem$$index == R_G0_enc, "double index?");
2117 // Load long with 2 instructions
2118 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2119 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2120 %}
2121
2122 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2123 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2124 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2125 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2126 %}
2127
2128 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2129 // Encode a reg-reg copy. If it is useless, then empty encoding.
2130 if( $rs2$$reg != $rd$$reg )
2131 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2132 %}
2133
2134 // Target lo half of long
2135 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2136 // Encode a reg-reg copy. If it is useless, then empty encoding.
2137 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2138 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2139 %}
2140
2141 // Source lo half of long
2142 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2143 // Encode a reg-reg copy. If it is useless, then empty encoding.
2144 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2145 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2146 %}
2147
2148 // Target hi half of long
2149 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2150 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2151 %}
2152
2153 // Source lo half of long, and leave it sign extended.
2154 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2155 // Sign extend low half
2156 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2157 %}
2158
2159 // Source hi half of long, and leave it sign extended.
2160 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2161 // Shift high half to low half
2162 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2163 %}
2164
2165 // Source hi half of long
2166 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2167 // Encode a reg-reg copy. If it is useless, then empty encoding.
2168 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2169 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2170 %}
2171
2172 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2173 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2174 %}
2175
2176 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2177 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2178 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2179 %}
2180
2181 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2182 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2183 // clear if nothing else is happening
2184 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2185 // blt,a,pn done
2186 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2187 // mov dst,-1 in delay slot
2188 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2189 %}
2190
2191 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2192 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2193 %}
2194
2195 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2196 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2197 %}
2198
2199 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2200 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2201 %}
2202
2203 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2204 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2205 %}
2206
2207 enc_class move_return_pc_to_o1() %{
2208 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2209 %}
2210
2211 #ifdef _LP64
2212 /* %%% merge with enc_to_bool */
2213 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2214 MacroAssembler _masm(&cbuf);
2215
2216 Register src_reg = reg_to_register_object($src$$reg);
2217 Register dst_reg = reg_to_register_object($dst$$reg);
2218 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2219 %}
2220 #endif
2221
2222 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2223 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2224 MacroAssembler _masm(&cbuf);
2225
2226 Register p_reg = reg_to_register_object($p$$reg);
2227 Register q_reg = reg_to_register_object($q$$reg);
2228 Register y_reg = reg_to_register_object($y$$reg);
2229 Register tmp_reg = reg_to_register_object($tmp$$reg);
2230
2231 __ subcc( p_reg, q_reg, p_reg );
2232 __ add ( p_reg, y_reg, tmp_reg );
2233 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2234 %}
2235
2236 enc_class form_d2i_helper(regD src, regF dst) %{
2237 // fcmp %fcc0,$src,$src
2238 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2239 // branch %fcc0 not-nan, predict taken
2240 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2241 // fdtoi $src,$dst
2242 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2243 // fitos $dst,$dst (if nan)
2244 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2245 // clear $dst (if nan)
2246 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2247 // carry on here...
2248 %}
2249
2250 enc_class form_d2l_helper(regD src, regD dst) %{
2251 // fcmp %fcc0,$src,$src check for NAN
2252 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2253 // branch %fcc0 not-nan, predict taken
2254 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2255 // fdtox $src,$dst convert in delay slot
2256 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2257 // fxtod $dst,$dst (if nan)
2258 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2259 // clear $dst (if nan)
2260 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2261 // carry on here...
2262 %}
2263
2264 enc_class form_f2i_helper(regF src, regF dst) %{
2265 // fcmps %fcc0,$src,$src
2266 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2267 // branch %fcc0 not-nan, predict taken
2268 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2269 // fstoi $src,$dst
2270 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2271 // fitos $dst,$dst (if nan)
2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2273 // clear $dst (if nan)
2274 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2275 // carry on here...
2276 %}
2277
2278 enc_class form_f2l_helper(regF src, regD dst) %{
2279 // fcmps %fcc0,$src,$src
2280 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2281 // branch %fcc0 not-nan, predict taken
2282 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2283 // fstox $src,$dst
2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2285 // fxtod $dst,$dst (if nan)
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2287 // clear $dst (if nan)
2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2289 // carry on here...
2290 %}
2291
2292 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2293 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2294 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2295 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2296
2297 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2298
2299 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2300 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2301
2302 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2303 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2304 %}
2305
2306 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2307 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2308 %}
2309
2310 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2311 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2312 %}
2313
2314 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2315 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2316 %}
2317
2318 enc_class form3_convI2F(regF rs2, regF rd) %{
2319 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2320 %}
2321
2322 // Encloding class for traceable jumps
2323 enc_class form_jmpl(g3RegP dest) %{
2324 emit_jmpl(cbuf, $dest$$reg);
2325 %}
2326
2327 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2328 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2329 %}
2330
2331 enc_class form2_nop() %{
2332 emit_nop(cbuf);
2333 %}
2334
2335 enc_class form2_illtrap() %{
2336 emit_illtrap(cbuf);
2337 %}
2338
2339
2340 // Compare longs and convert into -1, 0, 1.
2341 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2342 // CMP $src1,$src2
2343 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2344 // blt,a,pn done
2345 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2346 // mov dst,-1 in delay slot
2347 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2348 // bgt,a,pn done
2349 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2350 // mov dst,1 in delay slot
2351 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2352 // CLR $dst
2353 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2354 %}
2355
2356 enc_class enc_PartialSubtypeCheck() %{
2357 MacroAssembler _masm(&cbuf);
2358 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2359 __ delayed()->nop();
2360 %}
2361
2362 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2363 MacroAssembler _masm(&cbuf);
2364 Label* L = $labl$$label;
2365 Assembler::Predict predict_taken =
2366 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2367
2368 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2369 __ delayed()->nop();
2370 %}
2371
2372 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2373 MacroAssembler _masm(&cbuf);
2374 Label* L = $labl$$label;
2375 Assembler::Predict predict_taken =
2376 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2377
2378 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2379 __ delayed()->nop();
2380 %}
2381
2382 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2383 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) |
2385 (Assembler::movcc_op3 << 19) |
2386 (1 << 18) | // cc2 bit for 'icc'
2387 ($cmp$$cmpcode << 14) |
2388 (0 << 13) | // select register move
2389 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2390 ($src$$reg << 0);
2391 cbuf.insts()->emit_int32(op);
2392 %}
2393
2394 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2395 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2396 int op = (Assembler::arith_op << 30) |
2397 ($dst$$reg << 25) |
2398 (Assembler::movcc_op3 << 19) |
2399 (1 << 18) | // cc2 bit for 'icc'
2400 ($cmp$$cmpcode << 14) |
2401 (1 << 13) | // select immediate move
2402 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2403 (simm11 << 0);
2404 cbuf.insts()->emit_int32(op);
2405 %}
2406
2407 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2408 int op = (Assembler::arith_op << 30) |
2409 ($dst$$reg << 25) |
2410 (Assembler::movcc_op3 << 19) |
2411 (0 << 18) | // cc2 bit for 'fccX'
2412 ($cmp$$cmpcode << 14) |
2413 (0 << 13) | // select register move
2414 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2415 ($src$$reg << 0);
2416 cbuf.insts()->emit_int32(op);
2417 %}
2418
2419 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2420 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2421 int op = (Assembler::arith_op << 30) |
2422 ($dst$$reg << 25) |
2423 (Assembler::movcc_op3 << 19) |
2424 (0 << 18) | // cc2 bit for 'fccX'
2425 ($cmp$$cmpcode << 14) |
2426 (1 << 13) | // select immediate move
2427 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2428 (simm11 << 0);
2429 cbuf.insts()->emit_int32(op);
2430 %}
2431
2432 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2433 int op = (Assembler::arith_op << 30) |
2434 ($dst$$reg << 25) |
2435 (Assembler::fpop2_op3 << 19) |
2436 (0 << 18) |
2437 ($cmp$$cmpcode << 14) |
2438 (1 << 13) | // select register move
2439 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2440 ($primary << 5) | // select single, double or quad
2441 ($src$$reg << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2444
2445 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2446 int op = (Assembler::arith_op << 30) |
2447 ($dst$$reg << 25) |
2448 (Assembler::fpop2_op3 << 19) |
2449 (0 << 18) |
2450 ($cmp$$cmpcode << 14) |
2451 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2452 ($primary << 5) | // select single, double or quad
2453 ($src$$reg << 0);
2454 cbuf.insts()->emit_int32(op);
2455 %}
2456
2457 // Used by the MIN/MAX encodings. Same as a CMOV, but
2458 // the condition comes from opcode-field instead of an argument.
2459 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2460 int op = (Assembler::arith_op << 30) |
2461 ($dst$$reg << 25) |
2462 (Assembler::movcc_op3 << 19) |
2463 (1 << 18) | // cc2 bit for 'icc'
2464 ($primary << 14) |
2465 (0 << 13) | // select register move
2466 (0 << 11) | // cc1, cc0 bits for 'icc'
2467 ($src$$reg << 0);
2468 cbuf.insts()->emit_int32(op);
2469 %}
2470
2471 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2472 int op = (Assembler::arith_op << 30) |
2473 ($dst$$reg << 25) |
2474 (Assembler::movcc_op3 << 19) |
2475 (6 << 16) | // cc2 bit for 'xcc'
2476 ($primary << 14) |
2477 (0 << 13) | // select register move
2478 (0 << 11) | // cc1, cc0 bits for 'icc'
2479 ($src$$reg << 0);
2480 cbuf.insts()->emit_int32(op);
2481 %}
2482
2483 enc_class Set13( immI13 src, iRegI rd ) %{
2484 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2485 %}
2486
2487 enc_class SetHi22( immI src, iRegI rd ) %{
2488 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2489 %}
2490
2491 enc_class Set32( immI src, iRegI rd ) %{
2492 MacroAssembler _masm(&cbuf);
2493 __ set($src$$constant, reg_to_register_object($rd$$reg));
2494 %}
2495
2496 enc_class call_epilog %{
2497 if( VerifyStackAtCalls ) {
2498 MacroAssembler _masm(&cbuf);
2499 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2500 Register temp_reg = G3;
2501 __ add(SP, framesize, temp_reg);
2502 __ cmp(temp_reg, FP);
2503 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2504 }
2505 %}
2506
2507 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2508 // to G1 so the register allocator will not have to deal with the misaligned register
2509 // pair.
2510 enc_class adjust_long_from_native_call %{
2511 #ifndef _LP64
2512 if (returns_long()) {
2513 // sllx O0,32,O0
2514 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2515 // srl O1,0,O1
2516 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2517 // or O0,O1,G1
2518 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2519 }
2520 #endif
2521 %}
2522
2523 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2524 // CALL directly to the runtime
2525 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2526 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2527 /*preserve_g2=*/true);
2528 %}
2529
2530 enc_class preserve_SP %{
2531 MacroAssembler _masm(&cbuf);
2532 __ mov(SP, L7_mh_SP_save);
2533 %}
2534
2535 enc_class restore_SP %{
2536 MacroAssembler _masm(&cbuf);
2537 __ mov(L7_mh_SP_save, SP);
2538 %}
2539
2540 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2541 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2542 // who we intended to call.
2543 if (!_method) {
2544 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2545 } else if (_optimized_virtual) {
2546 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2547 } else {
2548 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2549 }
2550 if (_method) { // Emit stub for static call.
2551 CompiledStaticCall::emit_to_interp_stub(cbuf);
2552 }
2553 %}
2554
2555 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2556 MacroAssembler _masm(&cbuf);
2557 __ set_inst_mark();
2558 int vtable_index = this->_vtable_index;
2559 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2560 if (vtable_index < 0) {
2561 // must be invalid_vtable_index, not nonvirtual_vtable_index
2562 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2563 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2564 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2565 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2566 __ ic_call((address)$meth$$method);
2567 } else {
2568 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2569 // Just go thru the vtable
2570 // get receiver klass (receiver already checked for non-null)
2571 // If we end up going thru a c2i adapter interpreter expects method in G5
2572 int off = __ offset();
2573 __ load_klass(O0, G3_scratch);
2574 int klass_load_size;
2575 if (UseCompressedClassPointers) {
2576 assert(Universe::heap() != NULL, "java heap should be initialized");
2577 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2578 } else {
2579 klass_load_size = 1*BytesPerInstWord;
2580 }
2581 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2582 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2583 if (Assembler::is_simm13(v_off)) {
2584 __ ld_ptr(G3, v_off, G5_method);
2585 } else {
2586 // Generate 2 instructions
2587 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2588 __ or3(G5_method, v_off & 0x3ff, G5_method);
2589 // ld_ptr, set_hi, set
2590 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2591 "Unexpected instruction size(s)");
2592 __ ld_ptr(G3, G5_method, G5_method);
2593 }
2594 // NOTE: for vtable dispatches, the vtable entry will never be null.
2595 // However it may very well end up in handle_wrong_method if the
2596 // method is abstract for the particular class.
2597 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2598 // jump to target (either compiled code or c2iadapter)
2599 __ jmpl(G3_scratch, G0, O7);
2600 __ delayed()->nop();
2601 }
2602 %}
2603
2604 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2605 MacroAssembler _masm(&cbuf);
2606
2607 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2608 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2609 // we might be calling a C2I adapter which needs it.
2610
2611 assert(temp_reg != G5_ic_reg, "conflicting registers");
2612 // Load nmethod
2613 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2614
2615 // CALL to compiled java, indirect the contents of G3
2616 __ set_inst_mark();
2617 __ callr(temp_reg, G0);
2618 __ delayed()->nop();
2619 %}
2620
2621 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2622 MacroAssembler _masm(&cbuf);
2623 Register Rdividend = reg_to_register_object($src1$$reg);
2624 Register Rdivisor = reg_to_register_object($src2$$reg);
2625 Register Rresult = reg_to_register_object($dst$$reg);
2626
2627 __ sra(Rdivisor, 0, Rdivisor);
2628 __ sra(Rdividend, 0, Rdividend);
2629 __ sdivx(Rdividend, Rdivisor, Rresult);
2630 %}
2631
2632 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2633 MacroAssembler _masm(&cbuf);
2634
2635 Register Rdividend = reg_to_register_object($src1$$reg);
2636 int divisor = $imm$$constant;
2637 Register Rresult = reg_to_register_object($dst$$reg);
2638
2639 __ sra(Rdividend, 0, Rdividend);
2640 __ sdivx(Rdividend, divisor, Rresult);
2641 %}
2642
2643 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2644 MacroAssembler _masm(&cbuf);
2645 Register Rsrc1 = reg_to_register_object($src1$$reg);
2646 Register Rsrc2 = reg_to_register_object($src2$$reg);
2647 Register Rdst = reg_to_register_object($dst$$reg);
2648
2649 __ sra( Rsrc1, 0, Rsrc1 );
2650 __ sra( Rsrc2, 0, Rsrc2 );
2651 __ mulx( Rsrc1, Rsrc2, Rdst );
2652 __ srlx( Rdst, 32, Rdst );
2653 %}
2654
2655 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2656 MacroAssembler _masm(&cbuf);
2657 Register Rdividend = reg_to_register_object($src1$$reg);
2658 Register Rdivisor = reg_to_register_object($src2$$reg);
2659 Register Rresult = reg_to_register_object($dst$$reg);
2660 Register Rscratch = reg_to_register_object($scratch$$reg);
2661
2662 assert(Rdividend != Rscratch, "");
2663 assert(Rdivisor != Rscratch, "");
2664
2665 __ sra(Rdividend, 0, Rdividend);
2666 __ sra(Rdivisor, 0, Rdivisor);
2667 __ sdivx(Rdividend, Rdivisor, Rscratch);
2668 __ mulx(Rscratch, Rdivisor, Rscratch);
2669 __ sub(Rdividend, Rscratch, Rresult);
2670 %}
2671
2672 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2673 MacroAssembler _masm(&cbuf);
2674
2675 Register Rdividend = reg_to_register_object($src1$$reg);
2676 int divisor = $imm$$constant;
2677 Register Rresult = reg_to_register_object($dst$$reg);
2678 Register Rscratch = reg_to_register_object($scratch$$reg);
2679
2680 assert(Rdividend != Rscratch, "");
2681
2682 __ sra(Rdividend, 0, Rdividend);
2683 __ sdivx(Rdividend, divisor, Rscratch);
2684 __ mulx(Rscratch, divisor, Rscratch);
2685 __ sub(Rdividend, Rscratch, Rresult);
2686 %}
2687
2688 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2689 MacroAssembler _masm(&cbuf);
2690
2691 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2692 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2693
2694 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2695 %}
2696
2697 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2698 MacroAssembler _masm(&cbuf);
2699
2700 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2701 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2702
2703 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2704 %}
2705
2706 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2707 MacroAssembler _masm(&cbuf);
2708
2709 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2710 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2711
2712 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2713 %}
2714
2715 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2716 MacroAssembler _masm(&cbuf);
2717
2718 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2719 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2720
2721 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2722 %}
2723
2724 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2725 MacroAssembler _masm(&cbuf);
2726
2727 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2728 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2729
2730 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2731 %}
2732
2733 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2734 MacroAssembler _masm(&cbuf);
2735
2736 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2737 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2738
2739 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2740 %}
2741
2742 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2743 MacroAssembler _masm(&cbuf);
2744
2745 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2746 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2747
2748 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2749 %}
2750
2751 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2752 MacroAssembler _masm(&cbuf);
2753
2754 Register Roop = reg_to_register_object($oop$$reg);
2755 Register Rbox = reg_to_register_object($box$$reg);
2756 Register Rscratch = reg_to_register_object($scratch$$reg);
2757 Register Rmark = reg_to_register_object($scratch2$$reg);
2758
2759 assert(Roop != Rscratch, "");
2760 assert(Roop != Rmark, "");
2761 assert(Rbox != Rscratch, "");
2762 assert(Rbox != Rmark, "");
2763
2764 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2765 %}
2766
2767 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2768 MacroAssembler _masm(&cbuf);
2769
2770 Register Roop = reg_to_register_object($oop$$reg);
2771 Register Rbox = reg_to_register_object($box$$reg);
2772 Register Rscratch = reg_to_register_object($scratch$$reg);
2773 Register Rmark = reg_to_register_object($scratch2$$reg);
2774
2775 assert(Roop != Rscratch, "");
2776 assert(Roop != Rmark, "");
2777 assert(Rbox != Rscratch, "");
2778 assert(Rbox != Rmark, "");
2779
2780 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2781 %}
2782
2783 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2784 MacroAssembler _masm(&cbuf);
2785 Register Rmem = reg_to_register_object($mem$$reg);
2786 Register Rold = reg_to_register_object($old$$reg);
2787 Register Rnew = reg_to_register_object($new$$reg);
2788
2789 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2790 __ cmp( Rold, Rnew );
2791 %}
2792
2793 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2794 Register Rmem = reg_to_register_object($mem$$reg);
2795 Register Rold = reg_to_register_object($old$$reg);
2796 Register Rnew = reg_to_register_object($new$$reg);
2797
2798 MacroAssembler _masm(&cbuf);
2799 __ mov(Rnew, O7);
2800 __ casx(Rmem, Rold, O7);
2801 __ cmp( Rold, O7 );
2802 %}
2803
2804 // raw int cas, used for compareAndSwap
2805 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2806 Register Rmem = reg_to_register_object($mem$$reg);
2807 Register Rold = reg_to_register_object($old$$reg);
2808 Register Rnew = reg_to_register_object($new$$reg);
2809
2810 MacroAssembler _masm(&cbuf);
2811 __ mov(Rnew, O7);
2812 __ cas(Rmem, Rold, O7);
2813 __ cmp( Rold, O7 );
2814 %}
2815
2816 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2817 Register Rres = reg_to_register_object($res$$reg);
2818
2819 MacroAssembler _masm(&cbuf);
2820 __ mov(1, Rres);
2821 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2822 %}
2823
2824 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2825 Register Rres = reg_to_register_object($res$$reg);
2826
2827 MacroAssembler _masm(&cbuf);
2828 __ mov(1, Rres);
2829 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2830 %}
2831
2832 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2833 MacroAssembler _masm(&cbuf);
2834 Register Rdst = reg_to_register_object($dst$$reg);
2835 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2836 : reg_to_DoubleFloatRegister_object($src1$$reg);
2837 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2838 : reg_to_DoubleFloatRegister_object($src2$$reg);
2839
2840 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2841 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2842 %}
2843
2844
2845 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2846 Label Ldone, Lloop;
2847 MacroAssembler _masm(&cbuf);
2848
2849 Register str1_reg = reg_to_register_object($str1$$reg);
2850 Register str2_reg = reg_to_register_object($str2$$reg);
2851 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2852 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2853 Register result_reg = reg_to_register_object($result$$reg);
2854
2855 assert(result_reg != str1_reg &&
2856 result_reg != str2_reg &&
2857 result_reg != cnt1_reg &&
2858 result_reg != cnt2_reg ,
2859 "need different registers");
2860
2861 // Compute the minimum of the string lengths(str1_reg) and the
2862 // difference of the string lengths (stack)
2863
2864 // See if the lengths are different, and calculate min in str1_reg.
2865 // Stash diff in O7 in case we need it for a tie-breaker.
2866 Label Lskip;
2867 __ subcc(cnt1_reg, cnt2_reg, O7);
2868 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2869 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2870 // cnt2 is shorter, so use its count:
2871 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2872 __ bind(Lskip);
2873
2874 // reallocate cnt1_reg, cnt2_reg, result_reg
2875 // Note: limit_reg holds the string length pre-scaled by 2
2876 Register limit_reg = cnt1_reg;
2877 Register chr2_reg = cnt2_reg;
2878 Register chr1_reg = result_reg;
2879 // str{12} are the base pointers
2880
2881 // Is the minimum length zero?
2882 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2883 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2884 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2885
2886 // Load first characters
2887 __ lduh(str1_reg, 0, chr1_reg);
2888 __ lduh(str2_reg, 0, chr2_reg);
2889
2890 // Compare first characters
2891 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2892 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2893 assert(chr1_reg == result_reg, "result must be pre-placed");
2894 __ delayed()->nop();
2895
2896 {
2897 // Check after comparing first character to see if strings are equivalent
2898 Label LSkip2;
2899 // Check if the strings start at same location
2900 __ cmp(str1_reg, str2_reg);
2901 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2902 __ delayed()->nop();
2903
2904 // Check if the length difference is zero (in O7)
2905 __ cmp(G0, O7);
2906 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2907 __ delayed()->mov(G0, result_reg); // result is zero
2908
2909 // Strings might not be equal
2910 __ bind(LSkip2);
2911 }
2912
2913 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2914 __ signx(limit_reg);
2915
2916 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2917 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2918 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2919
2920 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2921 __ add(str1_reg, limit_reg, str1_reg);
2922 __ add(str2_reg, limit_reg, str2_reg);
2923 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2924
2925 // Compare the rest of the characters
2926 __ lduh(str1_reg, limit_reg, chr1_reg);
2927 __ bind(Lloop);
2928 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2929 __ lduh(str2_reg, limit_reg, chr2_reg);
2930 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2931 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2932 assert(chr1_reg == result_reg, "result must be pre-placed");
2933 __ delayed()->inccc(limit_reg, sizeof(jchar));
2934 // annul LDUH if branch is not taken to prevent access past end of string
2935 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2936 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2937
2938 // If strings are equal up to min length, return the length difference.
2939 __ mov(O7, result_reg);
2940
2941 // Otherwise, return the difference between the first mismatched chars.
2942 __ bind(Ldone);
2943 %}
2944
2945 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2946 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2947 MacroAssembler _masm(&cbuf);
2948
2949 Register str1_reg = reg_to_register_object($str1$$reg);
2950 Register str2_reg = reg_to_register_object($str2$$reg);
2951 Register cnt_reg = reg_to_register_object($cnt$$reg);
2952 Register tmp1_reg = O7;
2953 Register result_reg = reg_to_register_object($result$$reg);
2954
2955 assert(result_reg != str1_reg &&
2956 result_reg != str2_reg &&
2957 result_reg != cnt_reg &&
2958 result_reg != tmp1_reg ,
2959 "need different registers");
2960
2961 __ cmp(str1_reg, str2_reg); //same char[] ?
2962 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2963 __ delayed()->add(G0, 1, result_reg);
2964
2965 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2966 __ delayed()->add(G0, 1, result_reg); // count == 0
2967
2968 //rename registers
2969 Register limit_reg = cnt_reg;
2970 Register chr1_reg = result_reg;
2971 Register chr2_reg = tmp1_reg;
2972
2973 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2974 __ signx(limit_reg);
2975
2976 //check for alignment and position the pointers to the ends
2977 __ or3(str1_reg, str2_reg, chr1_reg);
2978 __ andcc(chr1_reg, 0x3, chr1_reg);
2979 // notZero means at least one not 4-byte aligned.
2980 // We could optimize the case when both arrays are not aligned
2981 // but it is not frequent case and it requires additional checks.
2982 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2983 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2984
2985 // Compare char[] arrays aligned to 4 bytes.
2986 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2987 chr1_reg, chr2_reg, Ldone);
2988 __ ba(Ldone);
2989 __ delayed()->add(G0, 1, result_reg);
2990
2991 // char by char compare
2992 __ bind(Lchar);
2993 __ add(str1_reg, limit_reg, str1_reg);
2994 __ add(str2_reg, limit_reg, str2_reg);
2995 __ neg(limit_reg); //negate count
2996
2997 __ lduh(str1_reg, limit_reg, chr1_reg);
2998 // Lchar_loop
2999 __ bind(Lchar_loop);
3000 __ lduh(str2_reg, limit_reg, chr2_reg);
3001 __ cmp(chr1_reg, chr2_reg);
3002 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3003 __ delayed()->mov(G0, result_reg); //not equal
3004 __ inccc(limit_reg, sizeof(jchar));
3005 // annul LDUH if branch is not taken to prevent access past end of string
3006 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3007 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3008
3009 __ add(G0, 1, result_reg); //equal
3010
3011 __ bind(Ldone);
3012 %}
3013
3014 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3015 Label Lvector, Ldone, Lloop;
3016 MacroAssembler _masm(&cbuf);
3017
3018 Register ary1_reg = reg_to_register_object($ary1$$reg);
3019 Register ary2_reg = reg_to_register_object($ary2$$reg);
3020 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3021 Register tmp2_reg = O7;
3022 Register result_reg = reg_to_register_object($result$$reg);
3023
3024 int length_offset = arrayOopDesc::length_offset_in_bytes();
3025 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3026
3027 // return true if the same array
3028 __ cmp(ary1_reg, ary2_reg);
3029 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3030 __ delayed()->add(G0, 1, result_reg); // equal
3031
3032 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3033 __ delayed()->mov(G0, result_reg); // not equal
3034
3035 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3036 __ delayed()->mov(G0, result_reg); // not equal
3037
3038 //load the lengths of arrays
3039 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3040 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3041
3042 // return false if the two arrays are not equal length
3043 __ cmp(tmp1_reg, tmp2_reg);
3044 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3045 __ delayed()->mov(G0, result_reg); // not equal
3046
3047 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3048 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3049
3050 // load array addresses
3051 __ add(ary1_reg, base_offset, ary1_reg);
3052 __ add(ary2_reg, base_offset, ary2_reg);
3053
3054 // renaming registers
3055 Register chr1_reg = result_reg; // for characters in ary1
3056 Register chr2_reg = tmp2_reg; // for characters in ary2
3057 Register limit_reg = tmp1_reg; // length
3058
3059 // set byte count
3060 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3061
3062 // Compare char[] arrays aligned to 4 bytes.
3063 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3064 chr1_reg, chr2_reg, Ldone);
3065 __ add(G0, 1, result_reg); // equals
3066
3067 __ bind(Ldone);
3068 %}
3069
3070 enc_class enc_rethrow() %{
3071 cbuf.set_insts_mark();
3072 Register temp_reg = G3;
3073 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3074 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3075 MacroAssembler _masm(&cbuf);
3076 #ifdef ASSERT
3077 __ save_frame(0);
3078 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3079 __ sethi(last_rethrow_addrlit, L1);
3080 Address addr(L1, last_rethrow_addrlit.low10());
3081 __ rdpc(L2);
3082 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3083 __ st_ptr(L2, addr);
3084 __ restore();
3085 #endif
3086 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3087 __ delayed()->nop();
3088 %}
3089
3090 enc_class emit_mem_nop() %{
3091 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3092 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3093 %}
3094
3095 enc_class emit_fadd_nop() %{
3096 // Generates the instruction FMOVS f31,f31
3097 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3098 %}
3099
3100 enc_class emit_br_nop() %{
3101 // Generates the instruction BPN,PN .
3102 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3103 %}
3104
3105 enc_class enc_membar_acquire %{
3106 MacroAssembler _masm(&cbuf);
3107 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3108 %}
3109
3110 enc_class enc_membar_release %{
3111 MacroAssembler _masm(&cbuf);
3112 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3113 %}
3114
3115 enc_class enc_membar_volatile %{
3116 MacroAssembler _masm(&cbuf);
3117 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3118 %}
3119
3120 %}
3121
3122 //----------FRAME--------------------------------------------------------------
3123 // Definition of frame structure and management information.
3124 //
3125 // S T A C K L A Y O U T Allocators stack-slot number
3126 // | (to get allocators register number
3127 // G Owned by | | v add VMRegImpl::stack0)
3128 // r CALLER | |
3129 // o | +--------+ pad to even-align allocators stack-slot
3130 // w V | pad0 | numbers; owned by CALLER
3131 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3132 // h ^ | in | 5
3133 // | | args | 4 Holes in incoming args owned by SELF
3134 // | | | | 3
3135 // | | +--------+
3136 // V | | old out| Empty on Intel, window on Sparc
3137 // | old |preserve| Must be even aligned.
3138 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3139 // | | in | 3 area for Intel ret address
3140 // Owned by |preserve| Empty on Sparc.
3141 // SELF +--------+
3142 // | | pad2 | 2 pad to align old SP
3143 // | +--------+ 1
3144 // | | locks | 0
3145 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3146 // | | pad1 | 11 pad to align new SP
3147 // | +--------+
3148 // | | | 10
3149 // | | spills | 9 spills
3150 // V | | 8 (pad0 slot for callee)
3151 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3152 // ^ | out | 7
3153 // | | args | 6 Holes in outgoing args owned by CALLEE
3154 // Owned by +--------+
3155 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3156 // | new |preserve| Must be even-aligned.
3157 // | SP-+--------+----> Matcher::_new_SP, even aligned
3158 // | | |
3159 //
3160 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3161 // known from SELF's arguments and the Java calling convention.
3162 // Region 6-7 is determined per call site.
3163 // Note 2: If the calling convention leaves holes in the incoming argument
3164 // area, those holes are owned by SELF. Holes in the outgoing area
3165 // are owned by the CALLEE. Holes should not be nessecary in the
3166 // incoming area, as the Java calling convention is completely under
3167 // the control of the AD file. Doubles can be sorted and packed to
3168 // avoid holes. Holes in the outgoing arguments may be nessecary for
3169 // varargs C calling conventions.
3170 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3171 // even aligned with pad0 as needed.
3172 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3173 // region 6-11 is even aligned; it may be padded out more so that
3174 // the region from SP to FP meets the minimum stack alignment.
3175
3176 frame %{
3177 // What direction does stack grow in (assumed to be same for native & Java)
3178 stack_direction(TOWARDS_LOW);
3179
3180 // These two registers define part of the calling convention
3181 // between compiled code and the interpreter.
3182 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3183 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3184
3185 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3186 cisc_spilling_operand_name(indOffset);
3187
3188 // Number of stack slots consumed by a Monitor enter
3189 #ifdef _LP64
3190 sync_stack_slots(2);
3191 #else
3192 sync_stack_slots(1);
3193 #endif
3194
3195 // Compiled code's Frame Pointer
3196 frame_pointer(R_SP);
3197
3198 // Stack alignment requirement
3199 stack_alignment(StackAlignmentInBytes);
3200 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3201 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3202
3203 // Number of stack slots between incoming argument block and the start of
3204 // a new frame. The PROLOG must add this many slots to the stack. The
3205 // EPILOG must remove this many slots.
3206 in_preserve_stack_slots(0);
3207
3208 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3209 // for calls to C. Supports the var-args backing area for register parms.
3210 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3211 #ifdef _LP64
3212 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3213 varargs_C_out_slots_killed(12);
3214 #else
3215 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3216 varargs_C_out_slots_killed( 7);
3217 #endif
3218
3219 // The after-PROLOG location of the return address. Location of
3220 // return address specifies a type (REG or STACK) and a number
3221 // representing the register number (i.e. - use a register name) or
3222 // stack slot.
3223 return_addr(REG R_I7); // Ret Addr is in register I7
3224
3225 // Body of function which returns an OptoRegs array locating
3226 // arguments either in registers or in stack slots for calling
3227 // java
3228 calling_convention %{
3229 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3230
3231 %}
3232
3233 // Body of function which returns an OptoRegs array locating
3234 // arguments either in registers or in stack slots for callin
3235 // C.
3236 c_calling_convention %{
3237 // This is obviously always outgoing
3238 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3239 %}
3240
3241 // Location of native (C/C++) and interpreter return values. This is specified to
3242 // be the same as Java. In the 32-bit VM, long values are actually returned from
3243 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3244 // to and from the register pairs is done by the appropriate call and epilog
3245 // opcodes. This simplifies the register allocator.
3246 c_return_value %{
3247 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3248 #ifdef _LP64
3249 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3250 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3251 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3252 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3253 #else // !_LP64
3254 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3255 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3256 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3257 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3258 #endif
3259 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3260 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3261 %}
3262
3263 // Location of compiled Java return values. Same as C
3264 return_value %{
3265 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3266 #ifdef _LP64
3267 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3268 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3269 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3270 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3271 #else // !_LP64
3272 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3273 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3274 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3275 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3276 #endif
3277 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3278 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3279 %}
3280
3281 %}
3282
3283
3284 //----------ATTRIBUTES---------------------------------------------------------
3285 //----------Operand Attributes-------------------------------------------------
3286 op_attrib op_cost(1); // Required cost attribute
3287
3288 //----------Instruction Attributes---------------------------------------------
3289 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3290 ins_attrib ins_size(32); // Required size attribute (in bits)
3291 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3292 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3293 // non-matching short branch variant of some
3294 // long branch?
3295
3296 //----------OPERANDS-----------------------------------------------------------
3297 // Operand definitions must precede instruction definitions for correct parsing
3298 // in the ADLC because operands constitute user defined types which are used in
3299 // instruction definitions.
3300
3301 //----------Simple Operands----------------------------------------------------
3302 // Immediate Operands
3303 // Integer Immediate: 32-bit
3304 operand immI() %{
3305 match(ConI);
3306
3307 op_cost(0);
3308 // formats are generated automatically for constants and base registers
3309 format %{ %}
3310 interface(CONST_INTER);
3311 %}
3312
3313 // Integer Immediate: 8-bit
3314 operand immI8() %{
3315 predicate(Assembler::is_simm8(n->get_int()));
3316 match(ConI);
3317 op_cost(0);
3318 format %{ %}
3319 interface(CONST_INTER);
3320 %}
3321
3322 // Integer Immediate: 13-bit
3323 operand immI13() %{
3324 predicate(Assembler::is_simm13(n->get_int()));
3325 match(ConI);
3326 op_cost(0);
3327
3328 format %{ %}
3329 interface(CONST_INTER);
3330 %}
3331
3332 // Integer Immediate: 13-bit minus 7
3333 operand immI13m7() %{
3334 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3335 match(ConI);
3336 op_cost(0);
3337
3338 format %{ %}
3339 interface(CONST_INTER);
3340 %}
3341
3342 // Integer Immediate: 16-bit
3343 operand immI16() %{
3344 predicate(Assembler::is_simm16(n->get_int()));
3345 match(ConI);
3346 op_cost(0);
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3352 operand immU12() %{
3353 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3354 match(ConI);
3355 op_cost(0);
3356
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360
3361 // Integer Immediate: 6-bit
3362 operand immU6() %{
3363 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3364 match(ConI);
3365 op_cost(0);
3366 format %{ %}
3367 interface(CONST_INTER);
3368 %}
3369
3370 // Integer Immediate: 11-bit
3371 operand immI11() %{
3372 predicate(Assembler::is_simm11(n->get_int()));
3373 match(ConI);
3374 op_cost(0);
3375 format %{ %}
3376 interface(CONST_INTER);
3377 %}
3378
3379 // Integer Immediate: 5-bit
3380 operand immI5() %{
3381 predicate(Assembler::is_simm5(n->get_int()));
3382 match(ConI);
3383 op_cost(0);
3384 format %{ %}
3385 interface(CONST_INTER);
3386 %}
3387
3388 // Int Immediate non-negative
3389 operand immU31()
3390 %{
3391 predicate(n->get_int() >= 0);
3392 match(ConI);
3393
3394 op_cost(0);
3395 format %{ %}
3396 interface(CONST_INTER);
3397 %}
3398
3399 // Integer Immediate: 0-bit
3400 operand immI0() %{
3401 predicate(n->get_int() == 0);
3402 match(ConI);
3403 op_cost(0);
3404
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Integer Immediate: the value 10
3410 operand immI10() %{
3411 predicate(n->get_int() == 10);
3412 match(ConI);
3413 op_cost(0);
3414
3415 format %{ %}
3416 interface(CONST_INTER);
3417 %}
3418
3419 // Integer Immediate: the values 0-31
3420 operand immU5() %{
3421 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3422 match(ConI);
3423 op_cost(0);
3424
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 // Integer Immediate: the values 1-31
3430 operand immI_1_31() %{
3431 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3432 match(ConI);
3433 op_cost(0);
3434
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 // Integer Immediate: the values 32-63
3440 operand immI_32_63() %{
3441 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3442 match(ConI);
3443 op_cost(0);
3444
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Immediates for special shifts (sign extend)
3450
3451 // Integer Immediate: the value 16
3452 operand immI_16() %{
3453 predicate(n->get_int() == 16);
3454 match(ConI);
3455 op_cost(0);
3456
3457 format %{ %}
3458 interface(CONST_INTER);
3459 %}
3460
3461 // Integer Immediate: the value 24
3462 operand immI_24() %{
3463 predicate(n->get_int() == 24);
3464 match(ConI);
3465 op_cost(0);
3466
3467 format %{ %}
3468 interface(CONST_INTER);
3469 %}
3470
3471 // Integer Immediate: the value 255
3472 operand immI_255() %{
3473 predicate( n->get_int() == 255 );
3474 match(ConI);
3475 op_cost(0);
3476
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 // Integer Immediate: the value 65535
3482 operand immI_65535() %{
3483 predicate(n->get_int() == 65535);
3484 match(ConI);
3485 op_cost(0);
3486
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3490
3491 // Long Immediate: the value FF
3492 operand immL_FF() %{
3493 predicate( n->get_long() == 0xFFL );
3494 match(ConL);
3495 op_cost(0);
3496
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3500
3501 // Long Immediate: the value FFFF
3502 operand immL_FFFF() %{
3503 predicate( n->get_long() == 0xFFFFL );
3504 match(ConL);
3505 op_cost(0);
3506
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Pointer Immediate: 32 or 64-bit
3512 operand immP() %{
3513 match(ConP);
3514
3515 op_cost(5);
3516 // formats are generated automatically for constants and base registers
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 #ifdef _LP64
3522 // Pointer Immediate: 64-bit
3523 operand immP_set() %{
3524 predicate(!VM_Version::is_niagara_plus());
3525 match(ConP);
3526
3527 op_cost(5);
3528 // formats are generated automatically for constants and base registers
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 // Pointer Immediate: 64-bit
3534 // From Niagara2 processors on a load should be better than materializing.
3535 operand immP_load() %{
3536 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3537 match(ConP);
3538
3539 op_cost(5);
3540 // formats are generated automatically for constants and base registers
3541 format %{ %}
3542 interface(CONST_INTER);
3543 %}
3544
3545 // Pointer Immediate: 64-bit
3546 operand immP_no_oop_cheap() %{
3547 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3548 match(ConP);
3549
3550 op_cost(5);
3551 // formats are generated automatically for constants and base registers
3552 format %{ %}
3553 interface(CONST_INTER);
3554 %}
3555 #endif
3556
3557 operand immP13() %{
3558 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3559 match(ConP);
3560 op_cost(0);
3561
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3565
3566 operand immP0() %{
3567 predicate(n->get_ptr() == 0);
3568 match(ConP);
3569 op_cost(0);
3570
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574
3575 operand immP_poll() %{
3576 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3577 match(ConP);
3578
3579 // formats are generated automatically for constants and base registers
3580 format %{ %}
3581 interface(CONST_INTER);
3582 %}
3583
3584 // Pointer Immediate
3585 operand immN()
3586 %{
3587 match(ConN);
3588
3589 op_cost(10);
3590 format %{ %}
3591 interface(CONST_INTER);
3592 %}
3593
3594 operand immNKlass()
3595 %{
3596 match(ConNKlass);
3597
3598 op_cost(10);
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 // NULL Pointer Immediate
3604 operand immN0()
3605 %{
3606 predicate(n->get_narrowcon() == 0);
3607 match(ConN);
3608
3609 op_cost(0);
3610 format %{ %}
3611 interface(CONST_INTER);
3612 %}
3613
3614 operand immL() %{
3615 match(ConL);
3616 op_cost(40);
3617 // formats are generated automatically for constants and base registers
3618 format %{ %}
3619 interface(CONST_INTER);
3620 %}
3621
3622 operand immL0() %{
3623 predicate(n->get_long() == 0L);
3624 match(ConL);
3625 op_cost(0);
3626 // formats are generated automatically for constants and base registers
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3630
3631 // Integer Immediate: 5-bit
3632 operand immL5() %{
3633 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3634 match(ConL);
3635 op_cost(0);
3636 format %{ %}
3637 interface(CONST_INTER);
3638 %}
3639
3640 // Long Immediate: 13-bit
3641 operand immL13() %{
3642 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3643 match(ConL);
3644 op_cost(0);
3645
3646 format %{ %}
3647 interface(CONST_INTER);
3648 %}
3649
3650 // Long Immediate: 13-bit minus 7
3651 operand immL13m7() %{
3652 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3653 match(ConL);
3654 op_cost(0);
3655
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Long Immediate: low 32-bit mask
3661 operand immL_32bits() %{
3662 predicate(n->get_long() == 0xFFFFFFFFL);
3663 match(ConL);
3664 op_cost(0);
3665
3666 format %{ %}
3667 interface(CONST_INTER);
3668 %}
3669
3670 // Long Immediate: cheap (materialize in <= 3 instructions)
3671 operand immL_cheap() %{
3672 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3673 match(ConL);
3674 op_cost(0);
3675
3676 format %{ %}
3677 interface(CONST_INTER);
3678 %}
3679
3680 // Long Immediate: expensive (materialize in > 3 instructions)
3681 operand immL_expensive() %{
3682 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3683 match(ConL);
3684 op_cost(0);
3685
3686 format %{ %}
3687 interface(CONST_INTER);
3688 %}
3689
3690 // Double Immediate
3691 operand immD() %{
3692 match(ConD);
3693
3694 op_cost(40);
3695 format %{ %}
3696 interface(CONST_INTER);
3697 %}
3698
3699 operand immD0() %{
3700 #ifdef _LP64
3701 // on 64-bit architectures this comparision is faster
3702 predicate(jlong_cast(n->getd()) == 0);
3703 #else
3704 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3705 #endif
3706 match(ConD);
3707
3708 op_cost(0);
3709 format %{ %}
3710 interface(CONST_INTER);
3711 %}
3712
3713 // Float Immediate
3714 operand immF() %{
3715 match(ConF);
3716
3717 op_cost(20);
3718 format %{ %}
3719 interface(CONST_INTER);
3720 %}
3721
3722 // Float Immediate: 0
3723 operand immF0() %{
3724 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3725 match(ConF);
3726
3727 op_cost(0);
3728 format %{ %}
3729 interface(CONST_INTER);
3730 %}
3731
3732 // Integer Register Operands
3733 // Integer Register
3734 operand iRegI() %{
3735 constraint(ALLOC_IN_RC(int_reg));
3736 match(RegI);
3737
3738 match(notemp_iRegI);
3739 match(g1RegI);
3740 match(o0RegI);
3741 match(iRegIsafe);
3742
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3746
3747 operand notemp_iRegI() %{
3748 constraint(ALLOC_IN_RC(notemp_int_reg));
3749 match(RegI);
3750
3751 match(o0RegI);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 operand o0RegI() %{
3758 constraint(ALLOC_IN_RC(o0_regI));
3759 match(iRegI);
3760
3761 format %{ %}
3762 interface(REG_INTER);
3763 %}
3764
3765 // Pointer Register
3766 operand iRegP() %{
3767 constraint(ALLOC_IN_RC(ptr_reg));
3768 match(RegP);
3769
3770 match(lock_ptr_RegP);
3771 match(g1RegP);
3772 match(g2RegP);
3773 match(g3RegP);
3774 match(g4RegP);
3775 match(i0RegP);
3776 match(o0RegP);
3777 match(o1RegP);
3778 match(l7RegP);
3779
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 operand sp_ptr_RegP() %{
3785 constraint(ALLOC_IN_RC(sp_ptr_reg));
3786 match(RegP);
3787 match(iRegP);
3788
3789 format %{ %}
3790 interface(REG_INTER);
3791 %}
3792
3793 operand lock_ptr_RegP() %{
3794 constraint(ALLOC_IN_RC(lock_ptr_reg));
3795 match(RegP);
3796 match(i0RegP);
3797 match(o0RegP);
3798 match(o1RegP);
3799 match(l7RegP);
3800
3801 format %{ %}
3802 interface(REG_INTER);
3803 %}
3804
3805 operand g1RegP() %{
3806 constraint(ALLOC_IN_RC(g1_regP));
3807 match(iRegP);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand g2RegP() %{
3814 constraint(ALLOC_IN_RC(g2_regP));
3815 match(iRegP);
3816
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3820
3821 operand g3RegP() %{
3822 constraint(ALLOC_IN_RC(g3_regP));
3823 match(iRegP);
3824
3825 format %{ %}
3826 interface(REG_INTER);
3827 %}
3828
3829 operand g1RegI() %{
3830 constraint(ALLOC_IN_RC(g1_regI));
3831 match(iRegI);
3832
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3836
3837 operand g3RegI() %{
3838 constraint(ALLOC_IN_RC(g3_regI));
3839 match(iRegI);
3840
3841 format %{ %}
3842 interface(REG_INTER);
3843 %}
3844
3845 operand g4RegI() %{
3846 constraint(ALLOC_IN_RC(g4_regI));
3847 match(iRegI);
3848
3849 format %{ %}
3850 interface(REG_INTER);
3851 %}
3852
3853 operand g4RegP() %{
3854 constraint(ALLOC_IN_RC(g4_regP));
3855 match(iRegP);
3856
3857 format %{ %}
3858 interface(REG_INTER);
3859 %}
3860
3861 operand i0RegP() %{
3862 constraint(ALLOC_IN_RC(i0_regP));
3863 match(iRegP);
3864
3865 format %{ %}
3866 interface(REG_INTER);
3867 %}
3868
3869 operand o0RegP() %{
3870 constraint(ALLOC_IN_RC(o0_regP));
3871 match(iRegP);
3872
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877 operand o1RegP() %{
3878 constraint(ALLOC_IN_RC(o1_regP));
3879 match(iRegP);
3880
3881 format %{ %}
3882 interface(REG_INTER);
3883 %}
3884
3885 operand o2RegP() %{
3886 constraint(ALLOC_IN_RC(o2_regP));
3887 match(iRegP);
3888
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3892
3893 operand o7RegP() %{
3894 constraint(ALLOC_IN_RC(o7_regP));
3895 match(iRegP);
3896
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3900
3901 operand l7RegP() %{
3902 constraint(ALLOC_IN_RC(l7_regP));
3903 match(iRegP);
3904
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3908
3909 operand o7RegI() %{
3910 constraint(ALLOC_IN_RC(o7_regI));
3911 match(iRegI);
3912
3913 format %{ %}
3914 interface(REG_INTER);
3915 %}
3916
3917 operand iRegN() %{
3918 constraint(ALLOC_IN_RC(int_reg));
3919 match(RegN);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 // Long Register
3926 operand iRegL() %{
3927 constraint(ALLOC_IN_RC(long_reg));
3928 match(RegL);
3929
3930 format %{ %}
3931 interface(REG_INTER);
3932 %}
3933
3934 operand o2RegL() %{
3935 constraint(ALLOC_IN_RC(o2_regL));
3936 match(iRegL);
3937
3938 format %{ %}
3939 interface(REG_INTER);
3940 %}
3941
3942 operand o7RegL() %{
3943 constraint(ALLOC_IN_RC(o7_regL));
3944 match(iRegL);
3945
3946 format %{ %}
3947 interface(REG_INTER);
3948 %}
3949
3950 operand g1RegL() %{
3951 constraint(ALLOC_IN_RC(g1_regL));
3952 match(iRegL);
3953
3954 format %{ %}
3955 interface(REG_INTER);
3956 %}
3957
3958 operand g3RegL() %{
3959 constraint(ALLOC_IN_RC(g3_regL));
3960 match(iRegL);
3961
3962 format %{ %}
3963 interface(REG_INTER);
3964 %}
3965
3966 // Int Register safe
3967 // This is 64bit safe
3968 operand iRegIsafe() %{
3969 constraint(ALLOC_IN_RC(long_reg));
3970
3971 match(iRegI);
3972
3973 format %{ %}
3974 interface(REG_INTER);
3975 %}
3976
3977 // Condition Code Flag Register
3978 operand flagsReg() %{
3979 constraint(ALLOC_IN_RC(int_flags));
3980 match(RegFlags);
3981
3982 format %{ "ccr" %} // both ICC and XCC
3983 interface(REG_INTER);
3984 %}
3985
3986 // Condition Code Register, unsigned comparisons.
3987 operand flagsRegU() %{
3988 constraint(ALLOC_IN_RC(int_flags));
3989 match(RegFlags);
3990
3991 format %{ "icc_U" %}
3992 interface(REG_INTER);
3993 %}
3994
3995 // Condition Code Register, pointer comparisons.
3996 operand flagsRegP() %{
3997 constraint(ALLOC_IN_RC(int_flags));
3998 match(RegFlags);
3999
4000 #ifdef _LP64
4001 format %{ "xcc_P" %}
4002 #else
4003 format %{ "icc_P" %}
4004 #endif
4005 interface(REG_INTER);
4006 %}
4007
4008 // Condition Code Register, long comparisons.
4009 operand flagsRegL() %{
4010 constraint(ALLOC_IN_RC(int_flags));
4011 match(RegFlags);
4012
4013 format %{ "xcc_L" %}
4014 interface(REG_INTER);
4015 %}
4016
4017 // Condition Code Register, floating comparisons, unordered same as "less".
4018 operand flagsRegF() %{
4019 constraint(ALLOC_IN_RC(float_flags));
4020 match(RegFlags);
4021 match(flagsRegF0);
4022
4023 format %{ %}
4024 interface(REG_INTER);
4025 %}
4026
4027 operand flagsRegF0() %{
4028 constraint(ALLOC_IN_RC(float_flag0));
4029 match(RegFlags);
4030
4031 format %{ %}
4032 interface(REG_INTER);
4033 %}
4034
4035
4036 // Condition Code Flag Register used by long compare
4037 operand flagsReg_long_LTGE() %{
4038 constraint(ALLOC_IN_RC(int_flags));
4039 match(RegFlags);
4040 format %{ "icc_LTGE" %}
4041 interface(REG_INTER);
4042 %}
4043 operand flagsReg_long_EQNE() %{
4044 constraint(ALLOC_IN_RC(int_flags));
4045 match(RegFlags);
4046 format %{ "icc_EQNE" %}
4047 interface(REG_INTER);
4048 %}
4049 operand flagsReg_long_LEGT() %{
4050 constraint(ALLOC_IN_RC(int_flags));
4051 match(RegFlags);
4052 format %{ "icc_LEGT" %}
4053 interface(REG_INTER);
4054 %}
4055
4056
4057 operand regD() %{
4058 constraint(ALLOC_IN_RC(dflt_reg));
4059 match(RegD);
4060
4061 match(regD_low);
4062
4063 format %{ %}
4064 interface(REG_INTER);
4065 %}
4066
4067 operand regF() %{
4068 constraint(ALLOC_IN_RC(sflt_reg));
4069 match(RegF);
4070
4071 format %{ %}
4072 interface(REG_INTER);
4073 %}
4074
4075 operand regD_low() %{
4076 constraint(ALLOC_IN_RC(dflt_low_reg));
4077 match(regD);
4078
4079 format %{ %}
4080 interface(REG_INTER);
4081 %}
4082
4083 // Special Registers
4084
4085 // Method Register
4086 operand inline_cache_regP(iRegP reg) %{
4087 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4088 match(reg);
4089 format %{ %}
4090 interface(REG_INTER);
4091 %}
4092
4093 operand interpreter_method_oop_regP(iRegP reg) %{
4094 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4095 match(reg);
4096 format %{ %}
4097 interface(REG_INTER);
4098 %}
4099
4100
4101 //----------Complex Operands---------------------------------------------------
4102 // Indirect Memory Reference
4103 operand indirect(sp_ptr_RegP reg) %{
4104 constraint(ALLOC_IN_RC(sp_ptr_reg));
4105 match(reg);
4106
4107 op_cost(100);
4108 format %{ "[$reg]" %}
4109 interface(MEMORY_INTER) %{
4110 base($reg);
4111 index(0x0);
4112 scale(0x0);
4113 disp(0x0);
4114 %}
4115 %}
4116
4117 // Indirect with simm13 Offset
4118 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4119 constraint(ALLOC_IN_RC(sp_ptr_reg));
4120 match(AddP reg offset);
4121
4122 op_cost(100);
4123 format %{ "[$reg + $offset]" %}
4124 interface(MEMORY_INTER) %{
4125 base($reg);
4126 index(0x0);
4127 scale(0x0);
4128 disp($offset);
4129 %}
4130 %}
4131
4132 // Indirect with simm13 Offset minus 7
4133 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4134 constraint(ALLOC_IN_RC(sp_ptr_reg));
4135 match(AddP reg offset);
4136
4137 op_cost(100);
4138 format %{ "[$reg + $offset]" %}
4139 interface(MEMORY_INTER) %{
4140 base($reg);
4141 index(0x0);
4142 scale(0x0);
4143 disp($offset);
4144 %}
4145 %}
4146
4147 // Note: Intel has a swapped version also, like this:
4148 //operand indOffsetX(iRegI reg, immP offset) %{
4149 // constraint(ALLOC_IN_RC(int_reg));
4150 // match(AddP offset reg);
4151 //
4152 // op_cost(100);
4153 // format %{ "[$reg + $offset]" %}
4154 // interface(MEMORY_INTER) %{
4155 // base($reg);
4156 // index(0x0);
4157 // scale(0x0);
4158 // disp($offset);
4159 // %}
4160 //%}
4161 //// However, it doesn't make sense for SPARC, since
4162 // we have no particularly good way to embed oops in
4163 // single instructions.
4164
4165 // Indirect with Register Index
4166 operand indIndex(iRegP addr, iRegX index) %{
4167 constraint(ALLOC_IN_RC(ptr_reg));
4168 match(AddP addr index);
4169
4170 op_cost(100);
4171 format %{ "[$addr + $index]" %}
4172 interface(MEMORY_INTER) %{
4173 base($addr);
4174 index($index);
4175 scale(0x0);
4176 disp(0x0);
4177 %}
4178 %}
4179
4180 //----------Special Memory Operands--------------------------------------------
4181 // Stack Slot Operand - This operand is used for loading and storing temporary
4182 // values on the stack where a match requires a value to
4183 // flow through memory.
4184 operand stackSlotI(sRegI reg) %{
4185 constraint(ALLOC_IN_RC(stack_slots));
4186 op_cost(100);
4187 //match(RegI);
4188 format %{ "[$reg]" %}
4189 interface(MEMORY_INTER) %{
4190 base(0xE); // R_SP
4191 index(0x0);
4192 scale(0x0);
4193 disp($reg); // Stack Offset
4194 %}
4195 %}
4196
4197 operand stackSlotP(sRegP reg) %{
4198 constraint(ALLOC_IN_RC(stack_slots));
4199 op_cost(100);
4200 //match(RegP);
4201 format %{ "[$reg]" %}
4202 interface(MEMORY_INTER) %{
4203 base(0xE); // R_SP
4204 index(0x0);
4205 scale(0x0);
4206 disp($reg); // Stack Offset
4207 %}
4208 %}
4209
4210 operand stackSlotF(sRegF reg) %{
4211 constraint(ALLOC_IN_RC(stack_slots));
4212 op_cost(100);
4213 //match(RegF);
4214 format %{ "[$reg]" %}
4215 interface(MEMORY_INTER) %{
4216 base(0xE); // R_SP
4217 index(0x0);
4218 scale(0x0);
4219 disp($reg); // Stack Offset
4220 %}
4221 %}
4222 operand stackSlotD(sRegD reg) %{
4223 constraint(ALLOC_IN_RC(stack_slots));
4224 op_cost(100);
4225 //match(RegD);
4226 format %{ "[$reg]" %}
4227 interface(MEMORY_INTER) %{
4228 base(0xE); // R_SP
4229 index(0x0);
4230 scale(0x0);
4231 disp($reg); // Stack Offset
4232 %}
4233 %}
4234 operand stackSlotL(sRegL reg) %{
4235 constraint(ALLOC_IN_RC(stack_slots));
4236 op_cost(100);
4237 //match(RegL);
4238 format %{ "[$reg]" %}
4239 interface(MEMORY_INTER) %{
4240 base(0xE); // R_SP
4241 index(0x0);
4242 scale(0x0);
4243 disp($reg); // Stack Offset
4244 %}
4245 %}
4246
4247 // Operands for expressing Control Flow
4248 // NOTE: Label is a predefined operand which should not be redefined in
4249 // the AD file. It is generically handled within the ADLC.
4250
4251 //----------Conditional Branch Operands----------------------------------------
4252 // Comparison Op - This is the operation of the comparison, and is limited to
4253 // the following set of codes:
4254 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4255 //
4256 // Other attributes of the comparison, such as unsignedness, are specified
4257 // by the comparison instruction that sets a condition code flags register.
4258 // That result is represented by a flags operand whose subtype is appropriate
4259 // to the unsignedness (etc.) of the comparison.
4260 //
4261 // Later, the instruction which matches both the Comparison Op (a Bool) and
4262 // the flags (produced by the Cmp) specifies the coding of the comparison op
4263 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4264
4265 operand cmpOp() %{
4266 match(Bool);
4267
4268 format %{ "" %}
4269 interface(COND_INTER) %{
4270 equal(0x1);
4271 not_equal(0x9);
4272 less(0x3);
4273 greater_equal(0xB);
4274 less_equal(0x2);
4275 greater(0xA);
4276 overflow(0x7);
4277 no_overflow(0xF);
4278 %}
4279 %}
4280
4281 // Comparison Op, unsigned
4282 operand cmpOpU() %{
4283 match(Bool);
4284 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4285 n->as_Bool()->_test._test != BoolTest::no_overflow);
4286
4287 format %{ "u" %}
4288 interface(COND_INTER) %{
4289 equal(0x1);
4290 not_equal(0x9);
4291 less(0x5);
4292 greater_equal(0xD);
4293 less_equal(0x4);
4294 greater(0xC);
4295 overflow(0x7);
4296 no_overflow(0xF);
4297 %}
4298 %}
4299
4300 // Comparison Op, pointer (same as unsigned)
4301 operand cmpOpP() %{
4302 match(Bool);
4303 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4304 n->as_Bool()->_test._test != BoolTest::no_overflow);
4305
4306 format %{ "p" %}
4307 interface(COND_INTER) %{
4308 equal(0x1);
4309 not_equal(0x9);
4310 less(0x5);
4311 greater_equal(0xD);
4312 less_equal(0x4);
4313 greater(0xC);
4314 overflow(0x7);
4315 no_overflow(0xF);
4316 %}
4317 %}
4318
4319 // Comparison Op, branch-register encoding
4320 operand cmpOp_reg() %{
4321 match(Bool);
4322 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4323 n->as_Bool()->_test._test != BoolTest::no_overflow);
4324
4325 format %{ "" %}
4326 interface(COND_INTER) %{
4327 equal (0x1);
4328 not_equal (0x5);
4329 less (0x3);
4330 greater_equal(0x7);
4331 less_equal (0x2);
4332 greater (0x6);
4333 overflow(0x7); // not supported
4334 no_overflow(0xF); // not supported
4335 %}
4336 %}
4337
4338 // Comparison Code, floating, unordered same as less
4339 operand cmpOpF() %{
4340 match(Bool);
4341 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4342 n->as_Bool()->_test._test != BoolTest::no_overflow);
4343
4344 format %{ "fl" %}
4345 interface(COND_INTER) %{
4346 equal(0x9);
4347 not_equal(0x1);
4348 less(0x3);
4349 greater_equal(0xB);
4350 less_equal(0xE);
4351 greater(0x6);
4352
4353 overflow(0x7); // not supported
4354 no_overflow(0xF); // not supported
4355 %}
4356 %}
4357
4358 // Used by long compare
4359 operand cmpOp_commute() %{
4360 match(Bool);
4361 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4362 n->as_Bool()->_test._test != BoolTest::no_overflow);
4363
4364 format %{ "" %}
4365 interface(COND_INTER) %{
4366 equal(0x1);
4367 not_equal(0x9);
4368 less(0xA);
4369 greater_equal(0x2);
4370 less_equal(0xB);
4371 greater(0x3);
4372 overflow(0x7);
4373 no_overflow(0xF);
4374 %}
4375 %}
4376
4377 //----------OPERAND CLASSES----------------------------------------------------
4378 // Operand Classes are groups of operands that are used to simplify
4379 // instruction definitions by not requiring the AD writer to specify separate
4380 // instructions for every form of operand when the instruction accepts
4381 // multiple operand types with the same basic encoding and format. The classic
4382 // case of this is memory operands.
4383 opclass memory( indirect, indOffset13, indIndex );
4384 opclass indIndexMemory( indIndex );
4385
4386 //----------PIPELINE-----------------------------------------------------------
4387 pipeline %{
4388
4389 //----------ATTRIBUTES---------------------------------------------------------
4390 attributes %{
4391 fixed_size_instructions; // Fixed size instructions
4392 branch_has_delay_slot; // Branch has delay slot following
4393 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4394 instruction_unit_size = 4; // An instruction is 4 bytes long
4395 instruction_fetch_unit_size = 16; // The processor fetches one line
4396 instruction_fetch_units = 1; // of 16 bytes
4397
4398 // List of nop instructions
4399 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4400 %}
4401
4402 //----------RESOURCES----------------------------------------------------------
4403 // Resources are the functional units available to the machine
4404 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4405
4406 //----------PIPELINE DESCRIPTION-----------------------------------------------
4407 // Pipeline Description specifies the stages in the machine's pipeline
4408
4409 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4410
4411 //----------PIPELINE CLASSES---------------------------------------------------
4412 // Pipeline Classes describe the stages in which input and output are
4413 // referenced by the hardware pipeline.
4414
4415 // Integer ALU reg-reg operation
4416 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4417 single_instruction;
4418 dst : E(write);
4419 src1 : R(read);
4420 src2 : R(read);
4421 IALU : R;
4422 %}
4423
4424 // Integer ALU reg-reg long operation
4425 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4426 instruction_count(2);
4427 dst : E(write);
4428 src1 : R(read);
4429 src2 : R(read);
4430 IALU : R;
4431 IALU : R;
4432 %}
4433
4434 // Integer ALU reg-reg long dependent operation
4435 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4436 instruction_count(1); multiple_bundles;
4437 dst : E(write);
4438 src1 : R(read);
4439 src2 : R(read);
4440 cr : E(write);
4441 IALU : R(2);
4442 %}
4443
4444 // Integer ALU reg-imm operaion
4445 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4446 single_instruction;
4447 dst : E(write);
4448 src1 : R(read);
4449 IALU : R;
4450 %}
4451
4452 // Integer ALU reg-reg operation with condition code
4453 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4454 single_instruction;
4455 dst : E(write);
4456 cr : E(write);
4457 src1 : R(read);
4458 src2 : R(read);
4459 IALU : R;
4460 %}
4461
4462 // Integer ALU reg-imm operation with condition code
4463 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4464 single_instruction;
4465 dst : E(write);
4466 cr : E(write);
4467 src1 : R(read);
4468 IALU : R;
4469 %}
4470
4471 // Integer ALU zero-reg operation
4472 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4473 single_instruction;
4474 dst : E(write);
4475 src2 : R(read);
4476 IALU : R;
4477 %}
4478
4479 // Integer ALU zero-reg operation with condition code only
4480 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4481 single_instruction;
4482 cr : E(write);
4483 src : R(read);
4484 IALU : R;
4485 %}
4486
4487 // Integer ALU reg-reg operation with condition code only
4488 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4489 single_instruction;
4490 cr : E(write);
4491 src1 : R(read);
4492 src2 : R(read);
4493 IALU : R;
4494 %}
4495
4496 // Integer ALU reg-imm operation with condition code only
4497 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4498 single_instruction;
4499 cr : E(write);
4500 src1 : R(read);
4501 IALU : R;
4502 %}
4503
4504 // Integer ALU reg-reg-zero operation with condition code only
4505 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4506 single_instruction;
4507 cr : E(write);
4508 src1 : R(read);
4509 src2 : R(read);
4510 IALU : R;
4511 %}
4512
4513 // Integer ALU reg-imm-zero operation with condition code only
4514 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4515 single_instruction;
4516 cr : E(write);
4517 src1 : R(read);
4518 IALU : R;
4519 %}
4520
4521 // Integer ALU reg-reg operation with condition code, src1 modified
4522 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4523 single_instruction;
4524 cr : E(write);
4525 src1 : E(write);
4526 src1 : R(read);
4527 src2 : R(read);
4528 IALU : R;
4529 %}
4530
4531 // Integer ALU reg-imm operation with condition code, src1 modified
4532 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4533 single_instruction;
4534 cr : E(write);
4535 src1 : E(write);
4536 src1 : R(read);
4537 IALU : R;
4538 %}
4539
4540 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4541 multiple_bundles;
4542 dst : E(write)+4;
4543 cr : E(write);
4544 src1 : R(read);
4545 src2 : R(read);
4546 IALU : R(3);
4547 BR : R(2);
4548 %}
4549
4550 // Integer ALU operation
4551 pipe_class ialu_none(iRegI dst) %{
4552 single_instruction;
4553 dst : E(write);
4554 IALU : R;
4555 %}
4556
4557 // Integer ALU reg operation
4558 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4559 single_instruction; may_have_no_code;
4560 dst : E(write);
4561 src : R(read);
4562 IALU : R;
4563 %}
4564
4565 // Integer ALU reg conditional operation
4566 // This instruction has a 1 cycle stall, and cannot execute
4567 // in the same cycle as the instruction setting the condition
4568 // code. We kludge this by pretending to read the condition code
4569 // 1 cycle earlier, and by marking the functional units as busy
4570 // for 2 cycles with the result available 1 cycle later than
4571 // is really the case.
4572 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4573 single_instruction;
4574 op2_out : C(write);
4575 op1 : R(read);
4576 cr : R(read); // This is really E, with a 1 cycle stall
4577 BR : R(2);
4578 MS : R(2);
4579 %}
4580
4581 #ifdef _LP64
4582 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4583 instruction_count(1); multiple_bundles;
4584 dst : C(write)+1;
4585 src : R(read)+1;
4586 IALU : R(1);
4587 BR : E(2);
4588 MS : E(2);
4589 %}
4590 #endif
4591
4592 // Integer ALU reg operation
4593 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4594 single_instruction; may_have_no_code;
4595 dst : E(write);
4596 src : R(read);
4597 IALU : R;
4598 %}
4599 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4600 single_instruction; may_have_no_code;
4601 dst : E(write);
4602 src : R(read);
4603 IALU : R;
4604 %}
4605
4606 // Two integer ALU reg operations
4607 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4608 instruction_count(2);
4609 dst : E(write);
4610 src : R(read);
4611 A0 : R;
4612 A1 : R;
4613 %}
4614
4615 // Two integer ALU reg operations
4616 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4617 instruction_count(2); may_have_no_code;
4618 dst : E(write);
4619 src : R(read);
4620 A0 : R;
4621 A1 : R;
4622 %}
4623
4624 // Integer ALU imm operation
4625 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4626 single_instruction;
4627 dst : E(write);
4628 IALU : R;
4629 %}
4630
4631 // Integer ALU reg-reg with carry operation
4632 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4633 single_instruction;
4634 dst : E(write);
4635 src1 : R(read);
4636 src2 : R(read);
4637 IALU : R;
4638 %}
4639
4640 // Integer ALU cc operation
4641 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4642 single_instruction;
4643 dst : E(write);
4644 cc : R(read);
4645 IALU : R;
4646 %}
4647
4648 // Integer ALU cc / second IALU operation
4649 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4650 instruction_count(1); multiple_bundles;
4651 dst : E(write)+1;
4652 src : R(read);
4653 IALU : R;
4654 %}
4655
4656 // Integer ALU cc / second IALU operation
4657 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4658 instruction_count(1); multiple_bundles;
4659 dst : E(write)+1;
4660 p : R(read);
4661 q : R(read);
4662 IALU : R;
4663 %}
4664
4665 // Integer ALU hi-lo-reg operation
4666 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4667 instruction_count(1); multiple_bundles;
4668 dst : E(write)+1;
4669 IALU : R(2);
4670 %}
4671
4672 // Float ALU hi-lo-reg operation (with temp)
4673 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4674 instruction_count(1); multiple_bundles;
4675 dst : E(write)+1;
4676 IALU : R(2);
4677 %}
4678
4679 // Long Constant
4680 pipe_class loadConL( iRegL dst, immL src ) %{
4681 instruction_count(2); multiple_bundles;
4682 dst : E(write)+1;
4683 IALU : R(2);
4684 IALU : R(2);
4685 %}
4686
4687 // Pointer Constant
4688 pipe_class loadConP( iRegP dst, immP src ) %{
4689 instruction_count(0); multiple_bundles;
4690 fixed_latency(6);
4691 %}
4692
4693 // Polling Address
4694 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4695 #ifdef _LP64
4696 instruction_count(0); multiple_bundles;
4697 fixed_latency(6);
4698 #else
4699 dst : E(write);
4700 IALU : R;
4701 #endif
4702 %}
4703
4704 // Long Constant small
4705 pipe_class loadConLlo( iRegL dst, immL src ) %{
4706 instruction_count(2);
4707 dst : E(write);
4708 IALU : R;
4709 IALU : R;
4710 %}
4711
4712 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4713 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4714 instruction_count(1); multiple_bundles;
4715 src : R(read);
4716 dst : M(write)+1;
4717 IALU : R;
4718 MS : E;
4719 %}
4720
4721 // Integer ALU nop operation
4722 pipe_class ialu_nop() %{
4723 single_instruction;
4724 IALU : R;
4725 %}
4726
4727 // Integer ALU nop operation
4728 pipe_class ialu_nop_A0() %{
4729 single_instruction;
4730 A0 : R;
4731 %}
4732
4733 // Integer ALU nop operation
4734 pipe_class ialu_nop_A1() %{
4735 single_instruction;
4736 A1 : R;
4737 %}
4738
4739 // Integer Multiply reg-reg operation
4740 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4741 single_instruction;
4742 dst : E(write);
4743 src1 : R(read);
4744 src2 : R(read);
4745 MS : R(5);
4746 %}
4747
4748 // Integer Multiply reg-imm operation
4749 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4750 single_instruction;
4751 dst : E(write);
4752 src1 : R(read);
4753 MS : R(5);
4754 %}
4755
4756 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4757 single_instruction;
4758 dst : E(write)+4;
4759 src1 : R(read);
4760 src2 : R(read);
4761 MS : R(6);
4762 %}
4763
4764 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4765 single_instruction;
4766 dst : E(write)+4;
4767 src1 : R(read);
4768 MS : R(6);
4769 %}
4770
4771 // Integer Divide reg-reg
4772 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4773 instruction_count(1); multiple_bundles;
4774 dst : E(write);
4775 temp : E(write);
4776 src1 : R(read);
4777 src2 : R(read);
4778 temp : R(read);
4779 MS : R(38);
4780 %}
4781
4782 // Integer Divide reg-imm
4783 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4784 instruction_count(1); multiple_bundles;
4785 dst : E(write);
4786 temp : E(write);
4787 src1 : R(read);
4788 temp : R(read);
4789 MS : R(38);
4790 %}
4791
4792 // Long Divide
4793 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4794 dst : E(write)+71;
4795 src1 : R(read);
4796 src2 : R(read)+1;
4797 MS : R(70);
4798 %}
4799
4800 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4801 dst : E(write)+71;
4802 src1 : R(read);
4803 MS : R(70);
4804 %}
4805
4806 // Floating Point Add Float
4807 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4808 single_instruction;
4809 dst : X(write);
4810 src1 : E(read);
4811 src2 : E(read);
4812 FA : R;
4813 %}
4814
4815 // Floating Point Add Double
4816 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4817 single_instruction;
4818 dst : X(write);
4819 src1 : E(read);
4820 src2 : E(read);
4821 FA : R;
4822 %}
4823
4824 // Floating Point Conditional Move based on integer flags
4825 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4826 single_instruction;
4827 dst : X(write);
4828 src : E(read);
4829 cr : R(read);
4830 FA : R(2);
4831 BR : R(2);
4832 %}
4833
4834 // Floating Point Conditional Move based on integer flags
4835 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4836 single_instruction;
4837 dst : X(write);
4838 src : E(read);
4839 cr : R(read);
4840 FA : R(2);
4841 BR : R(2);
4842 %}
4843
4844 // Floating Point Multiply Float
4845 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4846 single_instruction;
4847 dst : X(write);
4848 src1 : E(read);
4849 src2 : E(read);
4850 FM : R;
4851 %}
4852
4853 // Floating Point Multiply Double
4854 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4855 single_instruction;
4856 dst : X(write);
4857 src1 : E(read);
4858 src2 : E(read);
4859 FM : R;
4860 %}
4861
4862 // Floating Point Divide Float
4863 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4864 single_instruction;
4865 dst : X(write);
4866 src1 : E(read);
4867 src2 : E(read);
4868 FM : R;
4869 FDIV : C(14);
4870 %}
4871
4872 // Floating Point Divide Double
4873 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4874 single_instruction;
4875 dst : X(write);
4876 src1 : E(read);
4877 src2 : E(read);
4878 FM : R;
4879 FDIV : C(17);
4880 %}
4881
4882 // Floating Point Move/Negate/Abs Float
4883 pipe_class faddF_reg(regF dst, regF src) %{
4884 single_instruction;
4885 dst : W(write);
4886 src : E(read);
4887 FA : R(1);
4888 %}
4889
4890 // Floating Point Move/Negate/Abs Double
4891 pipe_class faddD_reg(regD dst, regD src) %{
4892 single_instruction;
4893 dst : W(write);
4894 src : E(read);
4895 FA : R;
4896 %}
4897
4898 // Floating Point Convert F->D
4899 pipe_class fcvtF2D(regD dst, regF src) %{
4900 single_instruction;
4901 dst : X(write);
4902 src : E(read);
4903 FA : R;
4904 %}
4905
4906 // Floating Point Convert I->D
4907 pipe_class fcvtI2D(regD dst, regF src) %{
4908 single_instruction;
4909 dst : X(write);
4910 src : E(read);
4911 FA : R;
4912 %}
4913
4914 // Floating Point Convert LHi->D
4915 pipe_class fcvtLHi2D(regD dst, regD src) %{
4916 single_instruction;
4917 dst : X(write);
4918 src : E(read);
4919 FA : R;
4920 %}
4921
4922 // Floating Point Convert L->D
4923 pipe_class fcvtL2D(regD dst, regF src) %{
4924 single_instruction;
4925 dst : X(write);
4926 src : E(read);
4927 FA : R;
4928 %}
4929
4930 // Floating Point Convert L->F
4931 pipe_class fcvtL2F(regD dst, regF src) %{
4932 single_instruction;
4933 dst : X(write);
4934 src : E(read);
4935 FA : R;
4936 %}
4937
4938 // Floating Point Convert D->F
4939 pipe_class fcvtD2F(regD dst, regF src) %{
4940 single_instruction;
4941 dst : X(write);
4942 src : E(read);
4943 FA : R;
4944 %}
4945
4946 // Floating Point Convert I->L
4947 pipe_class fcvtI2L(regD dst, regF src) %{
4948 single_instruction;
4949 dst : X(write);
4950 src : E(read);
4951 FA : R;
4952 %}
4953
4954 // Floating Point Convert D->F
4955 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4956 instruction_count(1); multiple_bundles;
4957 dst : X(write)+6;
4958 src : E(read);
4959 FA : R;
4960 %}
4961
4962 // Floating Point Convert D->L
4963 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4964 instruction_count(1); multiple_bundles;
4965 dst : X(write)+6;
4966 src : E(read);
4967 FA : R;
4968 %}
4969
4970 // Floating Point Convert F->I
4971 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4972 instruction_count(1); multiple_bundles;
4973 dst : X(write)+6;
4974 src : E(read);
4975 FA : R;
4976 %}
4977
4978 // Floating Point Convert F->L
4979 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4980 instruction_count(1); multiple_bundles;
4981 dst : X(write)+6;
4982 src : E(read);
4983 FA : R;
4984 %}
4985
4986 // Floating Point Convert I->F
4987 pipe_class fcvtI2F(regF dst, regF src) %{
4988 single_instruction;
4989 dst : X(write);
4990 src : E(read);
4991 FA : R;
4992 %}
4993
4994 // Floating Point Compare
4995 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4996 single_instruction;
4997 cr : X(write);
4998 src1 : E(read);
4999 src2 : E(read);
5000 FA : R;
5001 %}
5002
5003 // Floating Point Compare
5004 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5005 single_instruction;
5006 cr : X(write);
5007 src1 : E(read);
5008 src2 : E(read);
5009 FA : R;
5010 %}
5011
5012 // Floating Add Nop
5013 pipe_class fadd_nop() %{
5014 single_instruction;
5015 FA : R;
5016 %}
5017
5018 // Integer Store to Memory
5019 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5020 single_instruction;
5021 mem : R(read);
5022 src : C(read);
5023 MS : R;
5024 %}
5025
5026 // Integer Store to Memory
5027 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5028 single_instruction;
5029 mem : R(read);
5030 src : C(read);
5031 MS : R;
5032 %}
5033
5034 // Integer Store Zero to Memory
5035 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5036 single_instruction;
5037 mem : R(read);
5038 MS : R;
5039 %}
5040
5041 // Special Stack Slot Store
5042 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5043 single_instruction;
5044 stkSlot : R(read);
5045 src : C(read);
5046 MS : R;
5047 %}
5048
5049 // Special Stack Slot Store
5050 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5051 instruction_count(2); multiple_bundles;
5052 stkSlot : R(read);
5053 src : C(read);
5054 MS : R(2);
5055 %}
5056
5057 // Float Store
5058 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5059 single_instruction;
5060 mem : R(read);
5061 src : C(read);
5062 MS : R;
5063 %}
5064
5065 // Float Store
5066 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5067 single_instruction;
5068 mem : R(read);
5069 MS : R;
5070 %}
5071
5072 // Double Store
5073 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5074 instruction_count(1);
5075 mem : R(read);
5076 src : C(read);
5077 MS : R;
5078 %}
5079
5080 // Double Store
5081 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5082 single_instruction;
5083 mem : R(read);
5084 MS : R;
5085 %}
5086
5087 // Special Stack Slot Float Store
5088 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5089 single_instruction;
5090 stkSlot : R(read);
5091 src : C(read);
5092 MS : R;
5093 %}
5094
5095 // Special Stack Slot Double Store
5096 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5097 single_instruction;
5098 stkSlot : R(read);
5099 src : C(read);
5100 MS : R;
5101 %}
5102
5103 // Integer Load (when sign bit propagation not needed)
5104 pipe_class iload_mem(iRegI dst, memory mem) %{
5105 single_instruction;
5106 mem : R(read);
5107 dst : C(write);
5108 MS : R;
5109 %}
5110
5111 // Integer Load from stack operand
5112 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5113 single_instruction;
5114 mem : R(read);
5115 dst : C(write);
5116 MS : R;
5117 %}
5118
5119 // Integer Load (when sign bit propagation or masking is needed)
5120 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5121 single_instruction;
5122 mem : R(read);
5123 dst : M(write);
5124 MS : R;
5125 %}
5126
5127 // Float Load
5128 pipe_class floadF_mem(regF dst, memory mem) %{
5129 single_instruction;
5130 mem : R(read);
5131 dst : M(write);
5132 MS : R;
5133 %}
5134
5135 // Float Load
5136 pipe_class floadD_mem(regD dst, memory mem) %{
5137 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5138 mem : R(read);
5139 dst : M(write);
5140 MS : R;
5141 %}
5142
5143 // Float Load
5144 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5145 single_instruction;
5146 stkSlot : R(read);
5147 dst : M(write);
5148 MS : R;
5149 %}
5150
5151 // Float Load
5152 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5153 single_instruction;
5154 stkSlot : R(read);
5155 dst : M(write);
5156 MS : R;
5157 %}
5158
5159 // Memory Nop
5160 pipe_class mem_nop() %{
5161 single_instruction;
5162 MS : R;
5163 %}
5164
5165 pipe_class sethi(iRegP dst, immI src) %{
5166 single_instruction;
5167 dst : E(write);
5168 IALU : R;
5169 %}
5170
5171 pipe_class loadPollP(iRegP poll) %{
5172 single_instruction;
5173 poll : R(read);
5174 MS : R;
5175 %}
5176
5177 pipe_class br(Universe br, label labl) %{
5178 single_instruction_with_delay_slot;
5179 BR : R;
5180 %}
5181
5182 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5183 single_instruction_with_delay_slot;
5184 cr : E(read);
5185 BR : R;
5186 %}
5187
5188 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5189 single_instruction_with_delay_slot;
5190 op1 : E(read);
5191 BR : R;
5192 MS : R;
5193 %}
5194
5195 // Compare and branch
5196 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5197 instruction_count(2); has_delay_slot;
5198 cr : E(write);
5199 src1 : R(read);
5200 src2 : R(read);
5201 IALU : R;
5202 BR : R;
5203 %}
5204
5205 // Compare and branch
5206 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5207 instruction_count(2); has_delay_slot;
5208 cr : E(write);
5209 src1 : R(read);
5210 IALU : R;
5211 BR : R;
5212 %}
5213
5214 // Compare and branch using cbcond
5215 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5216 single_instruction;
5217 src1 : E(read);
5218 src2 : E(read);
5219 IALU : R;
5220 BR : R;
5221 %}
5222
5223 // Compare and branch using cbcond
5224 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5225 single_instruction;
5226 src1 : E(read);
5227 IALU : R;
5228 BR : R;
5229 %}
5230
5231 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5232 single_instruction_with_delay_slot;
5233 cr : E(read);
5234 BR : R;
5235 %}
5236
5237 pipe_class br_nop() %{
5238 single_instruction;
5239 BR : R;
5240 %}
5241
5242 pipe_class simple_call(method meth) %{
5243 instruction_count(2); multiple_bundles; force_serialization;
5244 fixed_latency(100);
5245 BR : R(1);
5246 MS : R(1);
5247 A0 : R(1);
5248 %}
5249
5250 pipe_class compiled_call(method meth) %{
5251 instruction_count(1); multiple_bundles; force_serialization;
5252 fixed_latency(100);
5253 MS : R(1);
5254 %}
5255
5256 pipe_class call(method meth) %{
5257 instruction_count(0); multiple_bundles; force_serialization;
5258 fixed_latency(100);
5259 %}
5260
5261 pipe_class tail_call(Universe ignore, label labl) %{
5262 single_instruction; has_delay_slot;
5263 fixed_latency(100);
5264 BR : R(1);
5265 MS : R(1);
5266 %}
5267
5268 pipe_class ret(Universe ignore) %{
5269 single_instruction; has_delay_slot;
5270 BR : R(1);
5271 MS : R(1);
5272 %}
5273
5274 pipe_class ret_poll(g3RegP poll) %{
5275 instruction_count(3); has_delay_slot;
5276 poll : E(read);
5277 MS : R;
5278 %}
5279
5280 // The real do-nothing guy
5281 pipe_class empty( ) %{
5282 instruction_count(0);
5283 %}
5284
5285 pipe_class long_memory_op() %{
5286 instruction_count(0); multiple_bundles; force_serialization;
5287 fixed_latency(25);
5288 MS : R(1);
5289 %}
5290
5291 // Check-cast
5292 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5293 array : R(read);
5294 match : R(read);
5295 IALU : R(2);
5296 BR : R(2);
5297 MS : R;
5298 %}
5299
5300 // Convert FPU flags into +1,0,-1
5301 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5302 src1 : E(read);
5303 src2 : E(read);
5304 dst : E(write);
5305 FA : R;
5306 MS : R(2);
5307 BR : R(2);
5308 %}
5309
5310 // Compare for p < q, and conditionally add y
5311 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5312 p : E(read);
5313 q : E(read);
5314 y : E(read);
5315 IALU : R(3)
5316 %}
5317
5318 // Perform a compare, then move conditionally in a branch delay slot.
5319 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5320 src2 : E(read);
5321 srcdst : E(read);
5322 IALU : R;
5323 BR : R;
5324 %}
5325
5326 // Define the class for the Nop node
5327 define %{
5328 MachNop = ialu_nop;
5329 %}
5330
5331 %}
5332
5333 //----------INSTRUCTIONS-------------------------------------------------------
5334
5335 //------------Special Stack Slot instructions - no match rules-----------------
5336 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5337 // No match rule to avoid chain rule match.
5338 effect(DEF dst, USE src);
5339 ins_cost(MEMORY_REF_COST);
5340 size(4);
5341 format %{ "LDF $src,$dst\t! stkI to regF" %}
5342 opcode(Assembler::ldf_op3);
5343 ins_encode(simple_form3_mem_reg(src, dst));
5344 ins_pipe(floadF_stk);
5345 %}
5346
5347 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5348 // No match rule to avoid chain rule match.
5349 effect(DEF dst, USE src);
5350 ins_cost(MEMORY_REF_COST);
5351 size(4);
5352 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5353 opcode(Assembler::lddf_op3);
5354 ins_encode(simple_form3_mem_reg(src, dst));
5355 ins_pipe(floadD_stk);
5356 %}
5357
5358 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5359 // No match rule to avoid chain rule match.
5360 effect(DEF dst, USE src);
5361 ins_cost(MEMORY_REF_COST);
5362 size(4);
5363 format %{ "STF $src,$dst\t! regF to stkI" %}
5364 opcode(Assembler::stf_op3);
5365 ins_encode(simple_form3_mem_reg(dst, src));
5366 ins_pipe(fstoreF_stk_reg);
5367 %}
5368
5369 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5370 // No match rule to avoid chain rule match.
5371 effect(DEF dst, USE src);
5372 ins_cost(MEMORY_REF_COST);
5373 size(4);
5374 format %{ "STDF $src,$dst\t! regD to stkL" %}
5375 opcode(Assembler::stdf_op3);
5376 ins_encode(simple_form3_mem_reg(dst, src));
5377 ins_pipe(fstoreD_stk_reg);
5378 %}
5379
5380 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5381 effect(DEF dst, USE src);
5382 ins_cost(MEMORY_REF_COST*2);
5383 size(8);
5384 format %{ "STW $src,$dst.hi\t! long\n\t"
5385 "STW R_G0,$dst.lo" %}
5386 opcode(Assembler::stw_op3);
5387 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5388 ins_pipe(lstoreI_stk_reg);
5389 %}
5390
5391 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5392 // No match rule to avoid chain rule match.
5393 effect(DEF dst, USE src);
5394 ins_cost(MEMORY_REF_COST);
5395 size(4);
5396 format %{ "STX $src,$dst\t! regL to stkD" %}
5397 opcode(Assembler::stx_op3);
5398 ins_encode(simple_form3_mem_reg( dst, src ) );
5399 ins_pipe(istore_stk_reg);
5400 %}
5401
5402 //---------- Chain stack slots between similar types --------
5403
5404 // Load integer from stack slot
5405 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5406 match(Set dst src);
5407 ins_cost(MEMORY_REF_COST);
5408
5409 size(4);
5410 format %{ "LDUW $src,$dst\t!stk" %}
5411 opcode(Assembler::lduw_op3);
5412 ins_encode(simple_form3_mem_reg( src, dst ) );
5413 ins_pipe(iload_mem);
5414 %}
5415
5416 // Store integer to stack slot
5417 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5418 match(Set dst src);
5419 ins_cost(MEMORY_REF_COST);
5420
5421 size(4);
5422 format %{ "STW $src,$dst\t!stk" %}
5423 opcode(Assembler::stw_op3);
5424 ins_encode(simple_form3_mem_reg( dst, src ) );
5425 ins_pipe(istore_mem_reg);
5426 %}
5427
5428 // Load long from stack slot
5429 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5430 match(Set dst src);
5431
5432 ins_cost(MEMORY_REF_COST);
5433 size(4);
5434 format %{ "LDX $src,$dst\t! long" %}
5435 opcode(Assembler::ldx_op3);
5436 ins_encode(simple_form3_mem_reg( src, dst ) );
5437 ins_pipe(iload_mem);
5438 %}
5439
5440 // Store long to stack slot
5441 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5442 match(Set dst src);
5443
5444 ins_cost(MEMORY_REF_COST);
5445 size(4);
5446 format %{ "STX $src,$dst\t! long" %}
5447 opcode(Assembler::stx_op3);
5448 ins_encode(simple_form3_mem_reg( dst, src ) );
5449 ins_pipe(istore_mem_reg);
5450 %}
5451
5452 #ifdef _LP64
5453 // Load pointer from stack slot, 64-bit encoding
5454 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5455 match(Set dst src);
5456 ins_cost(MEMORY_REF_COST);
5457 size(4);
5458 format %{ "LDX $src,$dst\t!ptr" %}
5459 opcode(Assembler::ldx_op3);
5460 ins_encode(simple_form3_mem_reg( src, dst ) );
5461 ins_pipe(iload_mem);
5462 %}
5463
5464 // Store pointer to stack slot
5465 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5466 match(Set dst src);
5467 ins_cost(MEMORY_REF_COST);
5468 size(4);
5469 format %{ "STX $src,$dst\t!ptr" %}
5470 opcode(Assembler::stx_op3);
5471 ins_encode(simple_form3_mem_reg( dst, src ) );
5472 ins_pipe(istore_mem_reg);
5473 %}
5474 #else // _LP64
5475 // Load pointer from stack slot, 32-bit encoding
5476 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5477 match(Set dst src);
5478 ins_cost(MEMORY_REF_COST);
5479 format %{ "LDUW $src,$dst\t!ptr" %}
5480 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5481 ins_encode(simple_form3_mem_reg( src, dst ) );
5482 ins_pipe(iload_mem);
5483 %}
5484
5485 // Store pointer to stack slot
5486 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5487 match(Set dst src);
5488 ins_cost(MEMORY_REF_COST);
5489 format %{ "STW $src,$dst\t!ptr" %}
5490 opcode(Assembler::stw_op3, Assembler::ldst_op);
5491 ins_encode(simple_form3_mem_reg( dst, src ) );
5492 ins_pipe(istore_mem_reg);
5493 %}
5494 #endif // _LP64
5495
5496 //------------Special Nop instructions for bundling - no match rules-----------
5497 // Nop using the A0 functional unit
5498 instruct Nop_A0() %{
5499 ins_cost(0);
5500
5501 format %{ "NOP ! Alu Pipeline" %}
5502 opcode(Assembler::or_op3, Assembler::arith_op);
5503 ins_encode( form2_nop() );
5504 ins_pipe(ialu_nop_A0);
5505 %}
5506
5507 // Nop using the A1 functional unit
5508 instruct Nop_A1( ) %{
5509 ins_cost(0);
5510
5511 format %{ "NOP ! Alu Pipeline" %}
5512 opcode(Assembler::or_op3, Assembler::arith_op);
5513 ins_encode( form2_nop() );
5514 ins_pipe(ialu_nop_A1);
5515 %}
5516
5517 // Nop using the memory functional unit
5518 instruct Nop_MS( ) %{
5519 ins_cost(0);
5520
5521 format %{ "NOP ! Memory Pipeline" %}
5522 ins_encode( emit_mem_nop );
5523 ins_pipe(mem_nop);
5524 %}
5525
5526 // Nop using the floating add functional unit
5527 instruct Nop_FA( ) %{
5528 ins_cost(0);
5529
5530 format %{ "NOP ! Floating Add Pipeline" %}
5531 ins_encode( emit_fadd_nop );
5532 ins_pipe(fadd_nop);
5533 %}
5534
5535 // Nop using the branch functional unit
5536 instruct Nop_BR( ) %{
5537 ins_cost(0);
5538
5539 format %{ "NOP ! Branch Pipeline" %}
5540 ins_encode( emit_br_nop );
5541 ins_pipe(br_nop);
5542 %}
5543
5544 //----------Load/Store/Move Instructions---------------------------------------
5545 //----------Load Instructions--------------------------------------------------
5546 // Load Byte (8bit signed)
5547 instruct loadB(iRegI dst, memory mem) %{
5548 match(Set dst (LoadB mem));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 size(4);
5552 format %{ "LDSB $mem,$dst\t! byte" %}
5553 ins_encode %{
5554 __ ldsb($mem$$Address, $dst$$Register);
5555 %}
5556 ins_pipe(iload_mask_mem);
5557 %}
5558
5559 // Load Byte (8bit signed) into a Long Register
5560 instruct loadB2L(iRegL dst, memory mem) %{
5561 match(Set dst (ConvI2L (LoadB mem)));
5562 ins_cost(MEMORY_REF_COST);
5563
5564 size(4);
5565 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5566 ins_encode %{
5567 __ ldsb($mem$$Address, $dst$$Register);
5568 %}
5569 ins_pipe(iload_mask_mem);
5570 %}
5571
5572 // Load Unsigned Byte (8bit UNsigned) into an int reg
5573 instruct loadUB(iRegI dst, memory mem) %{
5574 match(Set dst (LoadUB mem));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDUB $mem,$dst\t! ubyte" %}
5579 ins_encode %{
5580 __ ldub($mem$$Address, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mem);
5583 %}
5584
5585 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5586 instruct loadUB2L(iRegL dst, memory mem) %{
5587 match(Set dst (ConvI2L (LoadUB mem)));
5588 ins_cost(MEMORY_REF_COST);
5589
5590 size(4);
5591 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5592 ins_encode %{
5593 __ ldub($mem$$Address, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5599 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5600 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5601 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5602
5603 size(2*4);
5604 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5605 "AND $dst,$mask,$dst" %}
5606 ins_encode %{
5607 __ ldub($mem$$Address, $dst$$Register);
5608 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5609 %}
5610 ins_pipe(iload_mem);
5611 %}
5612
5613 // Load Short (16bit signed)
5614 instruct loadS(iRegI dst, memory mem) %{
5615 match(Set dst (LoadS mem));
5616 ins_cost(MEMORY_REF_COST);
5617
5618 size(4);
5619 format %{ "LDSH $mem,$dst\t! short" %}
5620 ins_encode %{
5621 __ ldsh($mem$$Address, $dst$$Register);
5622 %}
5623 ins_pipe(iload_mask_mem);
5624 %}
5625
5626 // Load Short (16 bit signed) to Byte (8 bit signed)
5627 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5628 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5629 ins_cost(MEMORY_REF_COST);
5630
5631 size(4);
5632
5633 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5634 ins_encode %{
5635 __ ldsb($mem$$Address, $dst$$Register, 1);
5636 %}
5637 ins_pipe(iload_mask_mem);
5638 %}
5639
5640 // Load Short (16bit signed) into a Long Register
5641 instruct loadS2L(iRegL dst, memory mem) %{
5642 match(Set dst (ConvI2L (LoadS mem)));
5643 ins_cost(MEMORY_REF_COST);
5644
5645 size(4);
5646 format %{ "LDSH $mem,$dst\t! short -> long" %}
5647 ins_encode %{
5648 __ ldsh($mem$$Address, $dst$$Register);
5649 %}
5650 ins_pipe(iload_mask_mem);
5651 %}
5652
5653 // Load Unsigned Short/Char (16bit UNsigned)
5654 instruct loadUS(iRegI dst, memory mem) %{
5655 match(Set dst (LoadUS mem));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 size(4);
5659 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5660 ins_encode %{
5661 __ lduh($mem$$Address, $dst$$Register);
5662 %}
5663 ins_pipe(iload_mem);
5664 %}
5665
5666 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5667 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5668 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5673 ins_encode %{
5674 __ ldsb($mem$$Address, $dst$$Register, 1);
5675 %}
5676 ins_pipe(iload_mask_mem);
5677 %}
5678
5679 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5680 instruct loadUS2L(iRegL dst, memory mem) %{
5681 match(Set dst (ConvI2L (LoadUS mem)));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 size(4);
5685 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5686 ins_encode %{
5687 __ lduh($mem$$Address, $dst$$Register);
5688 %}
5689 ins_pipe(iload_mem);
5690 %}
5691
5692 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5693 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5694 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5695 ins_cost(MEMORY_REF_COST);
5696
5697 size(4);
5698 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5699 ins_encode %{
5700 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5701 %}
5702 ins_pipe(iload_mem);
5703 %}
5704
5705 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5706 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5707 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5708 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5709
5710 size(2*4);
5711 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5712 "AND $dst,$mask,$dst" %}
5713 ins_encode %{
5714 Register Rdst = $dst$$Register;
5715 __ lduh($mem$$Address, Rdst);
5716 __ and3(Rdst, $mask$$constant, Rdst);
5717 %}
5718 ins_pipe(iload_mem);
5719 %}
5720
5721 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5722 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5723 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5724 effect(TEMP dst, TEMP tmp);
5725 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5726
5727 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5728 "SET $mask,$tmp\n\t"
5729 "AND $dst,$tmp,$dst" %}
5730 ins_encode %{
5731 Register Rdst = $dst$$Register;
5732 Register Rtmp = $tmp$$Register;
5733 __ lduh($mem$$Address, Rdst);
5734 __ set($mask$$constant, Rtmp);
5735 __ and3(Rdst, Rtmp, Rdst);
5736 %}
5737 ins_pipe(iload_mem);
5738 %}
5739
5740 // Load Integer
5741 instruct loadI(iRegI dst, memory mem) %{
5742 match(Set dst (LoadI mem));
5743 ins_cost(MEMORY_REF_COST);
5744
5745 size(4);
5746 format %{ "LDUW $mem,$dst\t! int" %}
5747 ins_encode %{
5748 __ lduw($mem$$Address, $dst$$Register);
5749 %}
5750 ins_pipe(iload_mem);
5751 %}
5752
5753 // Load Integer to Byte (8 bit signed)
5754 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5755 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5756 ins_cost(MEMORY_REF_COST);
5757
5758 size(4);
5759
5760 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5761 ins_encode %{
5762 __ ldsb($mem$$Address, $dst$$Register, 3);
5763 %}
5764 ins_pipe(iload_mask_mem);
5765 %}
5766
5767 // Load Integer to Unsigned Byte (8 bit UNsigned)
5768 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5769 match(Set dst (AndI (LoadI mem) mask));
5770 ins_cost(MEMORY_REF_COST);
5771
5772 size(4);
5773
5774 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5775 ins_encode %{
5776 __ ldub($mem$$Address, $dst$$Register, 3);
5777 %}
5778 ins_pipe(iload_mask_mem);
5779 %}
5780
5781 // Load Integer to Short (16 bit signed)
5782 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5783 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5784 ins_cost(MEMORY_REF_COST);
5785
5786 size(4);
5787
5788 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5789 ins_encode %{
5790 __ ldsh($mem$$Address, $dst$$Register, 2);
5791 %}
5792 ins_pipe(iload_mask_mem);
5793 %}
5794
5795 // Load Integer to Unsigned Short (16 bit UNsigned)
5796 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5797 match(Set dst (AndI (LoadI mem) mask));
5798 ins_cost(MEMORY_REF_COST);
5799
5800 size(4);
5801
5802 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5803 ins_encode %{
5804 __ lduh($mem$$Address, $dst$$Register, 2);
5805 %}
5806 ins_pipe(iload_mask_mem);
5807 %}
5808
5809 // Load Integer into a Long Register
5810 instruct loadI2L(iRegL dst, memory mem) %{
5811 match(Set dst (ConvI2L (LoadI mem)));
5812 ins_cost(MEMORY_REF_COST);
5813
5814 size(4);
5815 format %{ "LDSW $mem,$dst\t! int -> long" %}
5816 ins_encode %{
5817 __ ldsw($mem$$Address, $dst$$Register);
5818 %}
5819 ins_pipe(iload_mask_mem);
5820 %}
5821
5822 // Load Integer with mask 0xFF into a Long Register
5823 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5824 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5825 ins_cost(MEMORY_REF_COST);
5826
5827 size(4);
5828 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5829 ins_encode %{
5830 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5831 %}
5832 ins_pipe(iload_mem);
5833 %}
5834
5835 // Load Integer with mask 0xFFFF into a Long Register
5836 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5837 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5838 ins_cost(MEMORY_REF_COST);
5839
5840 size(4);
5841 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5842 ins_encode %{
5843 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5844 %}
5845 ins_pipe(iload_mem);
5846 %}
5847
5848 // Load Integer with a 12-bit mask into a Long Register
5849 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5852
5853 size(2*4);
5854 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5855 "AND $dst,$mask,$dst" %}
5856 ins_encode %{
5857 Register Rdst = $dst$$Register;
5858 __ lduw($mem$$Address, Rdst);
5859 __ and3(Rdst, $mask$$constant, Rdst);
5860 %}
5861 ins_pipe(iload_mem);
5862 %}
5863
5864 // Load Integer with a 31-bit mask into a Long Register
5865 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5866 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5867 effect(TEMP dst, TEMP tmp);
5868 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5869
5870 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5871 "SET $mask,$tmp\n\t"
5872 "AND $dst,$tmp,$dst" %}
5873 ins_encode %{
5874 Register Rdst = $dst$$Register;
5875 Register Rtmp = $tmp$$Register;
5876 __ lduw($mem$$Address, Rdst);
5877 __ set($mask$$constant, Rtmp);
5878 __ and3(Rdst, Rtmp, Rdst);
5879 %}
5880 ins_pipe(iload_mem);
5881 %}
5882
5883 // Load Unsigned Integer into a Long Register
5884 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5885 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5886 ins_cost(MEMORY_REF_COST);
5887
5888 size(4);
5889 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5890 ins_encode %{
5891 __ lduw($mem$$Address, $dst$$Register);
5892 %}
5893 ins_pipe(iload_mem);
5894 %}
5895
5896 // Load Long - aligned
5897 instruct loadL(iRegL dst, memory mem ) %{
5898 match(Set dst (LoadL mem));
5899 ins_cost(MEMORY_REF_COST);
5900
5901 size(4);
5902 format %{ "LDX $mem,$dst\t! long" %}
5903 ins_encode %{
5904 __ ldx($mem$$Address, $dst$$Register);
5905 %}
5906 ins_pipe(iload_mem);
5907 %}
5908
5909 // Load Long - UNaligned
5910 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5911 match(Set dst (LoadL_unaligned mem));
5912 effect(KILL tmp);
5913 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5914 size(16);
5915 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5916 "\tLDUW $mem ,$dst\n"
5917 "\tSLLX #32, $dst, $dst\n"
5918 "\tOR $dst, R_O7, $dst" %}
5919 opcode(Assembler::lduw_op3);
5920 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5921 ins_pipe(iload_mem);
5922 %}
5923
5924 // Load Range
5925 instruct loadRange(iRegI dst, memory mem) %{
5926 match(Set dst (LoadRange mem));
5927 ins_cost(MEMORY_REF_COST);
5928
5929 size(4);
5930 format %{ "LDUW $mem,$dst\t! range" %}
5931 opcode(Assembler::lduw_op3);
5932 ins_encode(simple_form3_mem_reg( mem, dst ) );
5933 ins_pipe(iload_mem);
5934 %}
5935
5936 // Load Integer into %f register (for fitos/fitod)
5937 instruct loadI_freg(regF dst, memory mem) %{
5938 match(Set dst (LoadI mem));
5939 ins_cost(MEMORY_REF_COST);
5940 size(4);
5941
5942 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5943 opcode(Assembler::ldf_op3);
5944 ins_encode(simple_form3_mem_reg( mem, dst ) );
5945 ins_pipe(floadF_mem);
5946 %}
5947
5948 // Load Pointer
5949 instruct loadP(iRegP dst, memory mem) %{
5950 match(Set dst (LoadP mem));
5951 ins_cost(MEMORY_REF_COST);
5952 size(4);
5953
5954 #ifndef _LP64
5955 format %{ "LDUW $mem,$dst\t! ptr" %}
5956 ins_encode %{
5957 __ lduw($mem$$Address, $dst$$Register);
5958 %}
5959 #else
5960 format %{ "LDX $mem,$dst\t! ptr" %}
5961 ins_encode %{
5962 __ ldx($mem$$Address, $dst$$Register);
5963 %}
5964 #endif
5965 ins_pipe(iload_mem);
5966 %}
5967
5968 // Load Compressed Pointer
5969 instruct loadN(iRegN dst, memory mem) %{
5970 match(Set dst (LoadN mem));
5971 ins_cost(MEMORY_REF_COST);
5972 size(4);
5973
5974 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5975 ins_encode %{
5976 __ lduw($mem$$Address, $dst$$Register);
5977 %}
5978 ins_pipe(iload_mem);
5979 %}
5980
5981 // Load Klass Pointer
5982 instruct loadKlass(iRegP dst, memory mem) %{
5983 match(Set dst (LoadKlass mem));
5984 ins_cost(MEMORY_REF_COST);
5985 size(4);
5986
5987 #ifndef _LP64
5988 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5989 ins_encode %{
5990 __ lduw($mem$$Address, $dst$$Register);
5991 %}
5992 #else
5993 format %{ "LDX $mem,$dst\t! klass ptr" %}
5994 ins_encode %{
5995 __ ldx($mem$$Address, $dst$$Register);
5996 %}
5997 #endif
5998 ins_pipe(iload_mem);
5999 %}
6000
6001 // Load narrow Klass Pointer
6002 instruct loadNKlass(iRegN dst, memory mem) %{
6003 match(Set dst (LoadNKlass mem));
6004 ins_cost(MEMORY_REF_COST);
6005 size(4);
6006
6007 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6008 ins_encode %{
6009 __ lduw($mem$$Address, $dst$$Register);
6010 %}
6011 ins_pipe(iload_mem);
6012 %}
6013
6014 // Load Double
6015 instruct loadD(regD dst, memory mem) %{
6016 match(Set dst (LoadD mem));
6017 ins_cost(MEMORY_REF_COST);
6018
6019 size(4);
6020 format %{ "LDDF $mem,$dst" %}
6021 opcode(Assembler::lddf_op3);
6022 ins_encode(simple_form3_mem_reg( mem, dst ) );
6023 ins_pipe(floadD_mem);
6024 %}
6025
6026 // Load Double - UNaligned
6027 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6028 match(Set dst (LoadD_unaligned mem));
6029 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6030 size(8);
6031 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6032 "\tLDF $mem+4,$dst.lo\t!" %}
6033 opcode(Assembler::ldf_op3);
6034 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6035 ins_pipe(iload_mem);
6036 %}
6037
6038 // Load Float
6039 instruct loadF(regF dst, memory mem) %{
6040 match(Set dst (LoadF mem));
6041 ins_cost(MEMORY_REF_COST);
6042
6043 size(4);
6044 format %{ "LDF $mem,$dst" %}
6045 opcode(Assembler::ldf_op3);
6046 ins_encode(simple_form3_mem_reg( mem, dst ) );
6047 ins_pipe(floadF_mem);
6048 %}
6049
6050 // Load Constant
6051 instruct loadConI( iRegI dst, immI src ) %{
6052 match(Set dst src);
6053 ins_cost(DEFAULT_COST * 3/2);
6054 format %{ "SET $src,$dst" %}
6055 ins_encode( Set32(src, dst) );
6056 ins_pipe(ialu_hi_lo_reg);
6057 %}
6058
6059 instruct loadConI13( iRegI dst, immI13 src ) %{
6060 match(Set dst src);
6061
6062 size(4);
6063 format %{ "MOV $src,$dst" %}
6064 ins_encode( Set13( src, dst ) );
6065 ins_pipe(ialu_imm);
6066 %}
6067
6068 #ifndef _LP64
6069 instruct loadConP(iRegP dst, immP con) %{
6070 match(Set dst con);
6071 ins_cost(DEFAULT_COST * 3/2);
6072 format %{ "SET $con,$dst\t!ptr" %}
6073 ins_encode %{
6074 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6075 intptr_t val = $con$$constant;
6076 if (constant_reloc == relocInfo::oop_type) {
6077 __ set_oop_constant((jobject) val, $dst$$Register);
6078 } else if (constant_reloc == relocInfo::metadata_type) {
6079 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6080 } else { // non-oop pointers, e.g. card mark base, heap top
6081 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6082 __ set(val, $dst$$Register);
6083 }
6084 %}
6085 ins_pipe(loadConP);
6086 %}
6087 #else
6088 instruct loadConP_set(iRegP dst, immP_set con) %{
6089 match(Set dst con);
6090 ins_cost(DEFAULT_COST * 3/2);
6091 format %{ "SET $con,$dst\t! ptr" %}
6092 ins_encode %{
6093 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6094 intptr_t val = $con$$constant;
6095 if (constant_reloc == relocInfo::oop_type) {
6096 __ set_oop_constant((jobject) val, $dst$$Register);
6097 } else if (constant_reloc == relocInfo::metadata_type) {
6098 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6099 } else { // non-oop pointers, e.g. card mark base, heap top
6100 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6101 __ set(val, $dst$$Register);
6102 }
6103 %}
6104 ins_pipe(loadConP);
6105 %}
6106
6107 instruct loadConP_load(iRegP dst, immP_load con) %{
6108 match(Set dst con);
6109 ins_cost(MEMORY_REF_COST);
6110 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6111 ins_encode %{
6112 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6113 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6114 %}
6115 ins_pipe(loadConP);
6116 %}
6117
6118 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6119 match(Set dst con);
6120 ins_cost(DEFAULT_COST * 3/2);
6121 format %{ "SET $con,$dst\t! non-oop ptr" %}
6122 ins_encode %{
6123 __ set($con$$constant, $dst$$Register);
6124 %}
6125 ins_pipe(loadConP);
6126 %}
6127 #endif // _LP64
6128
6129 instruct loadConP0(iRegP dst, immP0 src) %{
6130 match(Set dst src);
6131
6132 size(4);
6133 format %{ "CLR $dst\t!ptr" %}
6134 ins_encode %{
6135 __ clr($dst$$Register);
6136 %}
6137 ins_pipe(ialu_imm);
6138 %}
6139
6140 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6141 match(Set dst src);
6142 ins_cost(DEFAULT_COST);
6143 format %{ "SET $src,$dst\t!ptr" %}
6144 ins_encode %{
6145 AddressLiteral polling_page(os::get_polling_page());
6146 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6147 %}
6148 ins_pipe(loadConP_poll);
6149 %}
6150
6151 instruct loadConN0(iRegN dst, immN0 src) %{
6152 match(Set dst src);
6153
6154 size(4);
6155 format %{ "CLR $dst\t! compressed NULL ptr" %}
6156 ins_encode %{
6157 __ clr($dst$$Register);
6158 %}
6159 ins_pipe(ialu_imm);
6160 %}
6161
6162 instruct loadConN(iRegN dst, immN src) %{
6163 match(Set dst src);
6164 ins_cost(DEFAULT_COST * 3/2);
6165 format %{ "SET $src,$dst\t! compressed ptr" %}
6166 ins_encode %{
6167 Register dst = $dst$$Register;
6168 __ set_narrow_oop((jobject)$src$$constant, dst);
6169 %}
6170 ins_pipe(ialu_hi_lo_reg);
6171 %}
6172
6173 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6174 match(Set dst src);
6175 ins_cost(DEFAULT_COST * 3/2);
6176 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6177 ins_encode %{
6178 Register dst = $dst$$Register;
6179 __ set_narrow_klass((Klass*)$src$$constant, dst);
6180 %}
6181 ins_pipe(ialu_hi_lo_reg);
6182 %}
6183
6184 // Materialize long value (predicated by immL_cheap).
6185 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6186 match(Set dst con);
6187 effect(KILL tmp);
6188 ins_cost(DEFAULT_COST * 3);
6189 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6190 ins_encode %{
6191 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6192 %}
6193 ins_pipe(loadConL);
6194 %}
6195
6196 // Load long value from constant table (predicated by immL_expensive).
6197 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6198 match(Set dst con);
6199 ins_cost(MEMORY_REF_COST);
6200 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6201 ins_encode %{
6202 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6203 __ ldx($constanttablebase, con_offset, $dst$$Register);
6204 %}
6205 ins_pipe(loadConL);
6206 %}
6207
6208 instruct loadConL0( iRegL dst, immL0 src ) %{
6209 match(Set dst src);
6210 ins_cost(DEFAULT_COST);
6211 size(4);
6212 format %{ "CLR $dst\t! long" %}
6213 ins_encode( Set13( src, dst ) );
6214 ins_pipe(ialu_imm);
6215 %}
6216
6217 instruct loadConL13( iRegL dst, immL13 src ) %{
6218 match(Set dst src);
6219 ins_cost(DEFAULT_COST * 2);
6220
6221 size(4);
6222 format %{ "MOV $src,$dst\t! long" %}
6223 ins_encode( Set13( src, dst ) );
6224 ins_pipe(ialu_imm);
6225 %}
6226
6227 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6228 match(Set dst con);
6229 effect(KILL tmp);
6230 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6231 ins_encode %{
6232 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6233 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6234 %}
6235 ins_pipe(loadConFD);
6236 %}
6237
6238 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6239 match(Set dst con);
6240 effect(KILL tmp);
6241 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6242 ins_encode %{
6243 // XXX This is a quick fix for 6833573.
6244 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6245 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6246 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6247 %}
6248 ins_pipe(loadConFD);
6249 %}
6250
6251 // Prefetch instructions.
6252 // Must be safe to execute with invalid address (cannot fault).
6253
6254 instruct prefetchr( memory mem ) %{
6255 match( PrefetchRead mem );
6256 ins_cost(MEMORY_REF_COST);
6257 size(4);
6258
6259 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6260 opcode(Assembler::prefetch_op3);
6261 ins_encode( form3_mem_prefetch_read( mem ) );
6262 ins_pipe(iload_mem);
6263 %}
6264
6265 instruct prefetchw( memory mem ) %{
6266 match( PrefetchWrite mem );
6267 ins_cost(MEMORY_REF_COST);
6268 size(4);
6269
6270 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6271 opcode(Assembler::prefetch_op3);
6272 ins_encode( form3_mem_prefetch_write( mem ) );
6273 ins_pipe(iload_mem);
6274 %}
6275
6276 // Prefetch instructions for allocation.
6277
6278 instruct prefetchAlloc( memory mem ) %{
6279 predicate(AllocatePrefetchInstr == 0);
6280 match( PrefetchAllocation mem );
6281 ins_cost(MEMORY_REF_COST);
6282 size(4);
6283
6284 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6285 opcode(Assembler::prefetch_op3);
6286 ins_encode( form3_mem_prefetch_write( mem ) );
6287 ins_pipe(iload_mem);
6288 %}
6289
6290 // Use BIS instruction to prefetch for allocation.
6291 // Could fault, need space at the end of TLAB.
6292 instruct prefetchAlloc_bis( iRegP dst ) %{
6293 predicate(AllocatePrefetchInstr == 1);
6294 match( PrefetchAllocation dst );
6295 ins_cost(MEMORY_REF_COST);
6296 size(4);
6297
6298 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6299 ins_encode %{
6300 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6301 %}
6302 ins_pipe(istore_mem_reg);
6303 %}
6304
6305 // Next code is used for finding next cache line address to prefetch.
6306 #ifndef _LP64
6307 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6308 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6309 ins_cost(DEFAULT_COST);
6310 size(4);
6311
6312 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6313 ins_encode %{
6314 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6315 %}
6316 ins_pipe(ialu_reg_imm);
6317 %}
6318 #else
6319 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6320 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6321 ins_cost(DEFAULT_COST);
6322 size(4);
6323
6324 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6325 ins_encode %{
6326 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6327 %}
6328 ins_pipe(ialu_reg_imm);
6329 %}
6330 #endif
6331
6332 //----------Store Instructions-------------------------------------------------
6333 // Store Byte
6334 instruct storeB(memory mem, iRegI src) %{
6335 match(Set mem (StoreB mem src));
6336 ins_cost(MEMORY_REF_COST);
6337
6338 size(4);
6339 format %{ "STB $src,$mem\t! byte" %}
6340 opcode(Assembler::stb_op3);
6341 ins_encode(simple_form3_mem_reg( mem, src ) );
6342 ins_pipe(istore_mem_reg);
6343 %}
6344
6345 instruct storeB0(memory mem, immI0 src) %{
6346 match(Set mem (StoreB mem src));
6347 ins_cost(MEMORY_REF_COST);
6348
6349 size(4);
6350 format %{ "STB $src,$mem\t! byte" %}
6351 opcode(Assembler::stb_op3);
6352 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6353 ins_pipe(istore_mem_zero);
6354 %}
6355
6356 instruct storeCM0(memory mem, immI0 src) %{
6357 match(Set mem (StoreCM mem src));
6358 ins_cost(MEMORY_REF_COST);
6359
6360 size(4);
6361 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6362 opcode(Assembler::stb_op3);
6363 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6364 ins_pipe(istore_mem_zero);
6365 %}
6366
6367 // Store Char/Short
6368 instruct storeC(memory mem, iRegI src) %{
6369 match(Set mem (StoreC mem src));
6370 ins_cost(MEMORY_REF_COST);
6371
6372 size(4);
6373 format %{ "STH $src,$mem\t! short" %}
6374 opcode(Assembler::sth_op3);
6375 ins_encode(simple_form3_mem_reg( mem, src ) );
6376 ins_pipe(istore_mem_reg);
6377 %}
6378
6379 instruct storeC0(memory mem, immI0 src) %{
6380 match(Set mem (StoreC mem src));
6381 ins_cost(MEMORY_REF_COST);
6382
6383 size(4);
6384 format %{ "STH $src,$mem\t! short" %}
6385 opcode(Assembler::sth_op3);
6386 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6387 ins_pipe(istore_mem_zero);
6388 %}
6389
6390 // Store Integer
6391 instruct storeI(memory mem, iRegI src) %{
6392 match(Set mem (StoreI mem src));
6393 ins_cost(MEMORY_REF_COST);
6394
6395 size(4);
6396 format %{ "STW $src,$mem" %}
6397 opcode(Assembler::stw_op3);
6398 ins_encode(simple_form3_mem_reg( mem, src ) );
6399 ins_pipe(istore_mem_reg);
6400 %}
6401
6402 // Store Long
6403 instruct storeL(memory mem, iRegL src) %{
6404 match(Set mem (StoreL mem src));
6405 ins_cost(MEMORY_REF_COST);
6406 size(4);
6407 format %{ "STX $src,$mem\t! long" %}
6408 opcode(Assembler::stx_op3);
6409 ins_encode(simple_form3_mem_reg( mem, src ) );
6410 ins_pipe(istore_mem_reg);
6411 %}
6412
6413 instruct storeI0(memory mem, immI0 src) %{
6414 match(Set mem (StoreI mem src));
6415 ins_cost(MEMORY_REF_COST);
6416
6417 size(4);
6418 format %{ "STW $src,$mem" %}
6419 opcode(Assembler::stw_op3);
6420 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6421 ins_pipe(istore_mem_zero);
6422 %}
6423
6424 instruct storeL0(memory mem, immL0 src) %{
6425 match(Set mem (StoreL mem src));
6426 ins_cost(MEMORY_REF_COST);
6427
6428 size(4);
6429 format %{ "STX $src,$mem" %}
6430 opcode(Assembler::stx_op3);
6431 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6432 ins_pipe(istore_mem_zero);
6433 %}
6434
6435 // Store Integer from float register (used after fstoi)
6436 instruct storeI_Freg(memory mem, regF src) %{
6437 match(Set mem (StoreI mem src));
6438 ins_cost(MEMORY_REF_COST);
6439
6440 size(4);
6441 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6442 opcode(Assembler::stf_op3);
6443 ins_encode(simple_form3_mem_reg( mem, src ) );
6444 ins_pipe(fstoreF_mem_reg);
6445 %}
6446
6447 // Store Pointer
6448 instruct storeP(memory dst, sp_ptr_RegP src) %{
6449 match(Set dst (StoreP dst src));
6450 ins_cost(MEMORY_REF_COST);
6451 size(4);
6452
6453 #ifndef _LP64
6454 format %{ "STW $src,$dst\t! ptr" %}
6455 opcode(Assembler::stw_op3, 0, REGP_OP);
6456 #else
6457 format %{ "STX $src,$dst\t! ptr" %}
6458 opcode(Assembler::stx_op3, 0, REGP_OP);
6459 #endif
6460 ins_encode( form3_mem_reg( dst, src ) );
6461 ins_pipe(istore_mem_spORreg);
6462 %}
6463
6464 instruct storeP0(memory dst, immP0 src) %{
6465 match(Set dst (StoreP dst src));
6466 ins_cost(MEMORY_REF_COST);
6467 size(4);
6468
6469 #ifndef _LP64
6470 format %{ "STW $src,$dst\t! ptr" %}
6471 opcode(Assembler::stw_op3, 0, REGP_OP);
6472 #else
6473 format %{ "STX $src,$dst\t! ptr" %}
6474 opcode(Assembler::stx_op3, 0, REGP_OP);
6475 #endif
6476 ins_encode( form3_mem_reg( dst, R_G0 ) );
6477 ins_pipe(istore_mem_zero);
6478 %}
6479
6480 // Store Compressed Pointer
6481 instruct storeN(memory dst, iRegN src) %{
6482 match(Set dst (StoreN dst src));
6483 ins_cost(MEMORY_REF_COST);
6484 size(4);
6485
6486 format %{ "STW $src,$dst\t! compressed ptr" %}
6487 ins_encode %{
6488 Register base = as_Register($dst$$base);
6489 Register index = as_Register($dst$$index);
6490 Register src = $src$$Register;
6491 if (index != G0) {
6492 __ stw(src, base, index);
6493 } else {
6494 __ stw(src, base, $dst$$disp);
6495 }
6496 %}
6497 ins_pipe(istore_mem_spORreg);
6498 %}
6499
6500 instruct storeNKlass(memory dst, iRegN src) %{
6501 match(Set dst (StoreNKlass dst src));
6502 ins_cost(MEMORY_REF_COST);
6503 size(4);
6504
6505 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6506 ins_encode %{
6507 Register base = as_Register($dst$$base);
6508 Register index = as_Register($dst$$index);
6509 Register src = $src$$Register;
6510 if (index != G0) {
6511 __ stw(src, base, index);
6512 } else {
6513 __ stw(src, base, $dst$$disp);
6514 }
6515 %}
6516 ins_pipe(istore_mem_spORreg);
6517 %}
6518
6519 instruct storeN0(memory dst, immN0 src) %{
6520 match(Set dst (StoreN dst src));
6521 ins_cost(MEMORY_REF_COST);
6522 size(4);
6523
6524 format %{ "STW $src,$dst\t! compressed ptr" %}
6525 ins_encode %{
6526 Register base = as_Register($dst$$base);
6527 Register index = as_Register($dst$$index);
6528 if (index != G0) {
6529 __ stw(0, base, index);
6530 } else {
6531 __ stw(0, base, $dst$$disp);
6532 }
6533 %}
6534 ins_pipe(istore_mem_zero);
6535 %}
6536
6537 // Store Double
6538 instruct storeD( memory mem, regD src) %{
6539 match(Set mem (StoreD mem src));
6540 ins_cost(MEMORY_REF_COST);
6541
6542 size(4);
6543 format %{ "STDF $src,$mem" %}
6544 opcode(Assembler::stdf_op3);
6545 ins_encode(simple_form3_mem_reg( mem, src ) );
6546 ins_pipe(fstoreD_mem_reg);
6547 %}
6548
6549 instruct storeD0( memory mem, immD0 src) %{
6550 match(Set mem (StoreD mem src));
6551 ins_cost(MEMORY_REF_COST);
6552
6553 size(4);
6554 format %{ "STX $src,$mem" %}
6555 opcode(Assembler::stx_op3);
6556 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6557 ins_pipe(fstoreD_mem_zero);
6558 %}
6559
6560 // Store Float
6561 instruct storeF( memory mem, regF src) %{
6562 match(Set mem (StoreF mem src));
6563 ins_cost(MEMORY_REF_COST);
6564
6565 size(4);
6566 format %{ "STF $src,$mem" %}
6567 opcode(Assembler::stf_op3);
6568 ins_encode(simple_form3_mem_reg( mem, src ) );
6569 ins_pipe(fstoreF_mem_reg);
6570 %}
6571
6572 instruct storeF0( memory mem, immF0 src) %{
6573 match(Set mem (StoreF mem src));
6574 ins_cost(MEMORY_REF_COST);
6575
6576 size(4);
6577 format %{ "STW $src,$mem\t! storeF0" %}
6578 opcode(Assembler::stw_op3);
6579 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6580 ins_pipe(fstoreF_mem_zero);
6581 %}
6582
6583 // Convert oop pointer into compressed form
6584 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6585 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6586 match(Set dst (EncodeP src));
6587 format %{ "encode_heap_oop $src, $dst" %}
6588 ins_encode %{
6589 __ encode_heap_oop($src$$Register, $dst$$Register);
6590 %}
6591 ins_pipe(ialu_reg);
6592 %}
6593
6594 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6595 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6596 match(Set dst (EncodeP src));
6597 format %{ "encode_heap_oop_not_null $src, $dst" %}
6598 ins_encode %{
6599 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6600 %}
6601 ins_pipe(ialu_reg);
6602 %}
6603
6604 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6605 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6606 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6607 match(Set dst (DecodeN src));
6608 format %{ "decode_heap_oop $src, $dst" %}
6609 ins_encode %{
6610 __ decode_heap_oop($src$$Register, $dst$$Register);
6611 %}
6612 ins_pipe(ialu_reg);
6613 %}
6614
6615 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6616 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6617 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6618 match(Set dst (DecodeN src));
6619 format %{ "decode_heap_oop_not_null $src, $dst" %}
6620 ins_encode %{
6621 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6622 %}
6623 ins_pipe(ialu_reg);
6624 %}
6625
6626 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6627 match(Set dst (EncodePKlass src));
6628 format %{ "encode_klass_not_null $src, $dst" %}
6629 ins_encode %{
6630 __ encode_klass_not_null($src$$Register, $dst$$Register);
6631 %}
6632 ins_pipe(ialu_reg);
6633 %}
6634
6635 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6636 match(Set dst (DecodeNKlass src));
6637 format %{ "decode_klass_not_null $src, $dst" %}
6638 ins_encode %{
6639 __ decode_klass_not_null($src$$Register, $dst$$Register);
6640 %}
6641 ins_pipe(ialu_reg);
6642 %}
6643
6644 //----------MemBar Instructions-----------------------------------------------
6645 // Memory barrier flavors
6646
6647 instruct membar_acquire() %{
6648 match(MemBarAcquire);
6649 ins_cost(4*MEMORY_REF_COST);
6650
6651 size(0);
6652 format %{ "MEMBAR-acquire" %}
6653 ins_encode( enc_membar_acquire );
6654 ins_pipe(long_memory_op);
6655 %}
6656
6657 instruct membar_acquire_lock() %{
6658 match(MemBarAcquireLock);
6659 ins_cost(0);
6660
6661 size(0);
6662 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6663 ins_encode( );
6664 ins_pipe(empty);
6665 %}
6666
6667 instruct membar_release() %{
6668 match(MemBarRelease);
6669 ins_cost(4*MEMORY_REF_COST);
6670
6671 size(0);
6672 format %{ "MEMBAR-release" %}
6673 ins_encode( enc_membar_release );
6674 ins_pipe(long_memory_op);
6675 %}
6676
6677 instruct membar_release_lock() %{
6678 match(MemBarReleaseLock);
6679 ins_cost(0);
6680
6681 size(0);
6682 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6683 ins_encode( );
6684 ins_pipe(empty);
6685 %}
6686
6687 instruct membar_volatile() %{
6688 match(MemBarVolatile);
6689 ins_cost(4*MEMORY_REF_COST);
6690
6691 size(4);
6692 format %{ "MEMBAR-volatile" %}
6693 ins_encode( enc_membar_volatile );
6694 ins_pipe(long_memory_op);
6695 %}
6696
6697 instruct unnecessary_membar_volatile() %{
6698 match(MemBarVolatile);
6699 predicate(Matcher::post_store_load_barrier(n));
6700 ins_cost(0);
6701
6702 size(0);
6703 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6704 ins_encode( );
6705 ins_pipe(empty);
6706 %}
6707
6708 instruct membar_storestore() %{
6709 match(MemBarStoreStore);
6710 ins_cost(0);
6711
6712 size(0);
6713 format %{ "!MEMBAR-storestore (empty encoding)" %}
6714 ins_encode( );
6715 ins_pipe(empty);
6716 %}
6717
6718 //----------Register Move Instructions-----------------------------------------
6719 instruct roundDouble_nop(regD dst) %{
6720 match(Set dst (RoundDouble dst));
6721 ins_cost(0);
6722 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6723 ins_encode( );
6724 ins_pipe(empty);
6725 %}
6726
6727
6728 instruct roundFloat_nop(regF dst) %{
6729 match(Set dst (RoundFloat dst));
6730 ins_cost(0);
6731 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6732 ins_encode( );
6733 ins_pipe(empty);
6734 %}
6735
6736
6737 // Cast Index to Pointer for unsafe natives
6738 instruct castX2P(iRegX src, iRegP dst) %{
6739 match(Set dst (CastX2P src));
6740
6741 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6742 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6743 ins_pipe(ialu_reg);
6744 %}
6745
6746 // Cast Pointer to Index for unsafe natives
6747 instruct castP2X(iRegP src, iRegX dst) %{
6748 match(Set dst (CastP2X src));
6749
6750 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6751 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6752 ins_pipe(ialu_reg);
6753 %}
6754
6755 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6756 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6757 match(Set stkSlot src); // chain rule
6758 ins_cost(MEMORY_REF_COST);
6759 format %{ "STDF $src,$stkSlot\t!stk" %}
6760 opcode(Assembler::stdf_op3);
6761 ins_encode(simple_form3_mem_reg(stkSlot, src));
6762 ins_pipe(fstoreD_stk_reg);
6763 %}
6764
6765 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6766 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6767 match(Set dst stkSlot); // chain rule
6768 ins_cost(MEMORY_REF_COST);
6769 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6770 opcode(Assembler::lddf_op3);
6771 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6772 ins_pipe(floadD_stk);
6773 %}
6774
6775 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6776 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6777 match(Set stkSlot src); // chain rule
6778 ins_cost(MEMORY_REF_COST);
6779 format %{ "STF $src,$stkSlot\t!stk" %}
6780 opcode(Assembler::stf_op3);
6781 ins_encode(simple_form3_mem_reg(stkSlot, src));
6782 ins_pipe(fstoreF_stk_reg);
6783 %}
6784
6785 //----------Conditional Move---------------------------------------------------
6786 // Conditional move
6787 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6788 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6789 ins_cost(150);
6790 format %{ "MOV$cmp $pcc,$src,$dst" %}
6791 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6792 ins_pipe(ialu_reg);
6793 %}
6794
6795 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6796 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6797 ins_cost(140);
6798 format %{ "MOV$cmp $pcc,$src,$dst" %}
6799 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6800 ins_pipe(ialu_imm);
6801 %}
6802
6803 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6804 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6805 ins_cost(150);
6806 size(4);
6807 format %{ "MOV$cmp $icc,$src,$dst" %}
6808 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6809 ins_pipe(ialu_reg);
6810 %}
6811
6812 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6813 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6814 ins_cost(140);
6815 size(4);
6816 format %{ "MOV$cmp $icc,$src,$dst" %}
6817 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6818 ins_pipe(ialu_imm);
6819 %}
6820
6821 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6822 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6823 ins_cost(150);
6824 size(4);
6825 format %{ "MOV$cmp $icc,$src,$dst" %}
6826 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6827 ins_pipe(ialu_reg);
6828 %}
6829
6830 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6831 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6832 ins_cost(140);
6833 size(4);
6834 format %{ "MOV$cmp $icc,$src,$dst" %}
6835 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6836 ins_pipe(ialu_imm);
6837 %}
6838
6839 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6840 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6841 ins_cost(150);
6842 size(4);
6843 format %{ "MOV$cmp $fcc,$src,$dst" %}
6844 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6845 ins_pipe(ialu_reg);
6846 %}
6847
6848 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6849 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6850 ins_cost(140);
6851 size(4);
6852 format %{ "MOV$cmp $fcc,$src,$dst" %}
6853 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6854 ins_pipe(ialu_imm);
6855 %}
6856
6857 // Conditional move for RegN. Only cmov(reg,reg).
6858 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6859 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6860 ins_cost(150);
6861 format %{ "MOV$cmp $pcc,$src,$dst" %}
6862 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6863 ins_pipe(ialu_reg);
6864 %}
6865
6866 // This instruction also works with CmpN so we don't need cmovNN_reg.
6867 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6868 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6869 ins_cost(150);
6870 size(4);
6871 format %{ "MOV$cmp $icc,$src,$dst" %}
6872 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6873 ins_pipe(ialu_reg);
6874 %}
6875
6876 // This instruction also works with CmpN so we don't need cmovNN_reg.
6877 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6878 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6879 ins_cost(150);
6880 size(4);
6881 format %{ "MOV$cmp $icc,$src,$dst" %}
6882 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6883 ins_pipe(ialu_reg);
6884 %}
6885
6886 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6887 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6888 ins_cost(150);
6889 size(4);
6890 format %{ "MOV$cmp $fcc,$src,$dst" %}
6891 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6892 ins_pipe(ialu_reg);
6893 %}
6894
6895 // Conditional move
6896 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6897 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6898 ins_cost(150);
6899 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6900 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6901 ins_pipe(ialu_reg);
6902 %}
6903
6904 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6905 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6906 ins_cost(140);
6907 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6908 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6909 ins_pipe(ialu_imm);
6910 %}
6911
6912 // This instruction also works with CmpN so we don't need cmovPN_reg.
6913 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6914 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6915 ins_cost(150);
6916
6917 size(4);
6918 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6919 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6920 ins_pipe(ialu_reg);
6921 %}
6922
6923 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6924 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6925 ins_cost(150);
6926
6927 size(4);
6928 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6929 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6930 ins_pipe(ialu_reg);
6931 %}
6932
6933 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6934 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6935 ins_cost(140);
6936
6937 size(4);
6938 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6939 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6940 ins_pipe(ialu_imm);
6941 %}
6942
6943 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6944 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6945 ins_cost(140);
6946
6947 size(4);
6948 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6949 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6950 ins_pipe(ialu_imm);
6951 %}
6952
6953 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6954 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6955 ins_cost(150);
6956 size(4);
6957 format %{ "MOV$cmp $fcc,$src,$dst" %}
6958 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6959 ins_pipe(ialu_imm);
6960 %}
6961
6962 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6963 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6964 ins_cost(140);
6965 size(4);
6966 format %{ "MOV$cmp $fcc,$src,$dst" %}
6967 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6968 ins_pipe(ialu_imm);
6969 %}
6970
6971 // Conditional move
6972 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6973 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6974 ins_cost(150);
6975 opcode(0x101);
6976 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6977 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6978 ins_pipe(int_conditional_float_move);
6979 %}
6980
6981 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6982 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6983 ins_cost(150);
6984
6985 size(4);
6986 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6987 opcode(0x101);
6988 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6989 ins_pipe(int_conditional_float_move);
6990 %}
6991
6992 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6993 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6994 ins_cost(150);
6995
6996 size(4);
6997 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6998 opcode(0x101);
6999 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7000 ins_pipe(int_conditional_float_move);
7001 %}
7002
7003 // Conditional move,
7004 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7005 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7006 ins_cost(150);
7007 size(4);
7008 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7009 opcode(0x1);
7010 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7011 ins_pipe(int_conditional_double_move);
7012 %}
7013
7014 // Conditional move
7015 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7016 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7017 ins_cost(150);
7018 size(4);
7019 opcode(0x102);
7020 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7021 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7022 ins_pipe(int_conditional_double_move);
7023 %}
7024
7025 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7026 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7027 ins_cost(150);
7028
7029 size(4);
7030 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7031 opcode(0x102);
7032 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7033 ins_pipe(int_conditional_double_move);
7034 %}
7035
7036 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7037 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7038 ins_cost(150);
7039
7040 size(4);
7041 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7042 opcode(0x102);
7043 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7044 ins_pipe(int_conditional_double_move);
7045 %}
7046
7047 // Conditional move,
7048 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7049 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7050 ins_cost(150);
7051 size(4);
7052 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7053 opcode(0x2);
7054 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7055 ins_pipe(int_conditional_double_move);
7056 %}
7057
7058 // Conditional move
7059 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7060 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7061 ins_cost(150);
7062 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7063 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7064 ins_pipe(ialu_reg);
7065 %}
7066
7067 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7068 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7069 ins_cost(140);
7070 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7071 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7072 ins_pipe(ialu_imm);
7073 %}
7074
7075 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7076 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7077 ins_cost(150);
7078
7079 size(4);
7080 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7081 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7082 ins_pipe(ialu_reg);
7083 %}
7084
7085
7086 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7087 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7088 ins_cost(150);
7089
7090 size(4);
7091 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7092 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7093 ins_pipe(ialu_reg);
7094 %}
7095
7096
7097 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7098 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7099 ins_cost(150);
7100
7101 size(4);
7102 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7103 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7104 ins_pipe(ialu_reg);
7105 %}
7106
7107
7108
7109 //----------OS and Locking Instructions----------------------------------------
7110
7111 // This name is KNOWN by the ADLC and cannot be changed.
7112 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7113 // for this guy.
7114 instruct tlsLoadP(g2RegP dst) %{
7115 match(Set dst (ThreadLocal));
7116
7117 size(0);
7118 ins_cost(0);
7119 format %{ "# TLS is in G2" %}
7120 ins_encode( /*empty encoding*/ );
7121 ins_pipe(ialu_none);
7122 %}
7123
7124 instruct checkCastPP( iRegP dst ) %{
7125 match(Set dst (CheckCastPP dst));
7126
7127 size(0);
7128 format %{ "# checkcastPP of $dst" %}
7129 ins_encode( /*empty encoding*/ );
7130 ins_pipe(empty);
7131 %}
7132
7133
7134 instruct castPP( iRegP dst ) %{
7135 match(Set dst (CastPP dst));
7136 format %{ "# castPP of $dst" %}
7137 ins_encode( /*empty encoding*/ );
7138 ins_pipe(empty);
7139 %}
7140
7141 instruct castII( iRegI dst ) %{
7142 match(Set dst (CastII dst));
7143 format %{ "# castII of $dst" %}
7144 ins_encode( /*empty encoding*/ );
7145 ins_cost(0);
7146 ins_pipe(empty);
7147 %}
7148
7149 //----------Arithmetic Instructions--------------------------------------------
7150 // Addition Instructions
7151 // Register Addition
7152 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7153 match(Set dst (AddI src1 src2));
7154
7155 size(4);
7156 format %{ "ADD $src1,$src2,$dst" %}
7157 ins_encode %{
7158 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7159 %}
7160 ins_pipe(ialu_reg_reg);
7161 %}
7162
7163 // Immediate Addition
7164 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7165 match(Set dst (AddI src1 src2));
7166
7167 size(4);
7168 format %{ "ADD $src1,$src2,$dst" %}
7169 opcode(Assembler::add_op3, Assembler::arith_op);
7170 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7171 ins_pipe(ialu_reg_imm);
7172 %}
7173
7174 // Pointer Register Addition
7175 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7176 match(Set dst (AddP src1 src2));
7177
7178 size(4);
7179 format %{ "ADD $src1,$src2,$dst" %}
7180 opcode(Assembler::add_op3, Assembler::arith_op);
7181 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7182 ins_pipe(ialu_reg_reg);
7183 %}
7184
7185 // Pointer Immediate Addition
7186 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7187 match(Set dst (AddP src1 src2));
7188
7189 size(4);
7190 format %{ "ADD $src1,$src2,$dst" %}
7191 opcode(Assembler::add_op3, Assembler::arith_op);
7192 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7193 ins_pipe(ialu_reg_imm);
7194 %}
7195
7196 // Long Addition
7197 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7198 match(Set dst (AddL src1 src2));
7199
7200 size(4);
7201 format %{ "ADD $src1,$src2,$dst\t! long" %}
7202 opcode(Assembler::add_op3, Assembler::arith_op);
7203 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7204 ins_pipe(ialu_reg_reg);
7205 %}
7206
7207 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7208 match(Set dst (AddL src1 con));
7209
7210 size(4);
7211 format %{ "ADD $src1,$con,$dst" %}
7212 opcode(Assembler::add_op3, Assembler::arith_op);
7213 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7214 ins_pipe(ialu_reg_imm);
7215 %}
7216
7217 //----------Conditional_store--------------------------------------------------
7218 // Conditional-store of the updated heap-top.
7219 // Used during allocation of the shared heap.
7220 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7221
7222 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7223 instruct loadPLocked(iRegP dst, memory mem) %{
7224 match(Set dst (LoadPLocked mem));
7225 ins_cost(MEMORY_REF_COST);
7226
7227 #ifndef _LP64
7228 size(4);
7229 format %{ "LDUW $mem,$dst\t! ptr" %}
7230 opcode(Assembler::lduw_op3, 0, REGP_OP);
7231 #else
7232 format %{ "LDX $mem,$dst\t! ptr" %}
7233 opcode(Assembler::ldx_op3, 0, REGP_OP);
7234 #endif
7235 ins_encode( form3_mem_reg( mem, dst ) );
7236 ins_pipe(iload_mem);
7237 %}
7238
7239 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7240 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7241 effect( KILL newval );
7242 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7243 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7244 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7245 ins_pipe( long_memory_op );
7246 %}
7247
7248 // Conditional-store of an int value.
7249 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7250 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7251 effect( KILL newval );
7252 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7253 "CMP $oldval,$newval\t\t! See if we made progress" %}
7254 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7255 ins_pipe( long_memory_op );
7256 %}
7257
7258 // Conditional-store of a long value.
7259 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7260 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7261 effect( KILL newval );
7262 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7263 "CMP $oldval,$newval\t\t! See if we made progress" %}
7264 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7265 ins_pipe( long_memory_op );
7266 %}
7267
7268 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7269
7270 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7271 predicate(VM_Version::supports_cx8());
7272 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7273 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7274 format %{
7275 "MOV $newval,O7\n\t"
7276 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7277 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7278 "MOV 1,$res\n\t"
7279 "MOVne xcc,R_G0,$res"
7280 %}
7281 ins_encode( enc_casx(mem_ptr, oldval, newval),
7282 enc_lflags_ne_to_boolean(res) );
7283 ins_pipe( long_memory_op );
7284 %}
7285
7286
7287 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7288 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7289 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7290 format %{
7291 "MOV $newval,O7\n\t"
7292 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7293 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7294 "MOV 1,$res\n\t"
7295 "MOVne icc,R_G0,$res"
7296 %}
7297 ins_encode( enc_casi(mem_ptr, oldval, newval),
7298 enc_iflags_ne_to_boolean(res) );
7299 ins_pipe( long_memory_op );
7300 %}
7301
7302 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7303 #ifdef _LP64
7304 predicate(VM_Version::supports_cx8());
7305 #endif
7306 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7307 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7308 format %{
7309 "MOV $newval,O7\n\t"
7310 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7311 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7312 "MOV 1,$res\n\t"
7313 "MOVne xcc,R_G0,$res"
7314 %}
7315 #ifdef _LP64
7316 ins_encode( enc_casx(mem_ptr, oldval, newval),
7317 enc_lflags_ne_to_boolean(res) );
7318 #else
7319 ins_encode( enc_casi(mem_ptr, oldval, newval),
7320 enc_iflags_ne_to_boolean(res) );
7321 #endif
7322 ins_pipe( long_memory_op );
7323 %}
7324
7325 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7326 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7327 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7328 format %{
7329 "MOV $newval,O7\n\t"
7330 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7331 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7332 "MOV 1,$res\n\t"
7333 "MOVne icc,R_G0,$res"
7334 %}
7335 ins_encode( enc_casi(mem_ptr, oldval, newval),
7336 enc_iflags_ne_to_boolean(res) );
7337 ins_pipe( long_memory_op );
7338 %}
7339
7340 instruct xchgI( memory mem, iRegI newval) %{
7341 match(Set newval (GetAndSetI mem newval));
7342 format %{ "SWAP [$mem],$newval" %}
7343 size(4);
7344 ins_encode %{
7345 __ swap($mem$$Address, $newval$$Register);
7346 %}
7347 ins_pipe( long_memory_op );
7348 %}
7349
7350 #ifndef _LP64
7351 instruct xchgP( memory mem, iRegP newval) %{
7352 match(Set newval (GetAndSetP mem newval));
7353 format %{ "SWAP [$mem],$newval" %}
7354 size(4);
7355 ins_encode %{
7356 __ swap($mem$$Address, $newval$$Register);
7357 %}
7358 ins_pipe( long_memory_op );
7359 %}
7360 #endif
7361
7362 instruct xchgN( memory mem, iRegN newval) %{
7363 match(Set newval (GetAndSetN mem newval));
7364 format %{ "SWAP [$mem],$newval" %}
7365 size(4);
7366 ins_encode %{
7367 __ swap($mem$$Address, $newval$$Register);
7368 %}
7369 ins_pipe( long_memory_op );
7370 %}
7371
7372 //---------------------
7373 // Subtraction Instructions
7374 // Register Subtraction
7375 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7376 match(Set dst (SubI src1 src2));
7377
7378 size(4);
7379 format %{ "SUB $src1,$src2,$dst" %}
7380 opcode(Assembler::sub_op3, Assembler::arith_op);
7381 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7382 ins_pipe(ialu_reg_reg);
7383 %}
7384
7385 // Immediate Subtraction
7386 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7387 match(Set dst (SubI src1 src2));
7388
7389 size(4);
7390 format %{ "SUB $src1,$src2,$dst" %}
7391 opcode(Assembler::sub_op3, Assembler::arith_op);
7392 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7393 ins_pipe(ialu_reg_imm);
7394 %}
7395
7396 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7397 match(Set dst (SubI zero src2));
7398
7399 size(4);
7400 format %{ "NEG $src2,$dst" %}
7401 opcode(Assembler::sub_op3, Assembler::arith_op);
7402 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7403 ins_pipe(ialu_zero_reg);
7404 %}
7405
7406 // Long subtraction
7407 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7408 match(Set dst (SubL src1 src2));
7409
7410 size(4);
7411 format %{ "SUB $src1,$src2,$dst\t! long" %}
7412 opcode(Assembler::sub_op3, Assembler::arith_op);
7413 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7414 ins_pipe(ialu_reg_reg);
7415 %}
7416
7417 // Immediate Subtraction
7418 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7419 match(Set dst (SubL src1 con));
7420
7421 size(4);
7422 format %{ "SUB $src1,$con,$dst\t! long" %}
7423 opcode(Assembler::sub_op3, Assembler::arith_op);
7424 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7425 ins_pipe(ialu_reg_imm);
7426 %}
7427
7428 // Long negation
7429 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7430 match(Set dst (SubL zero src2));
7431
7432 size(4);
7433 format %{ "NEG $src2,$dst\t! long" %}
7434 opcode(Assembler::sub_op3, Assembler::arith_op);
7435 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7436 ins_pipe(ialu_zero_reg);
7437 %}
7438
7439 // Multiplication Instructions
7440 // Integer Multiplication
7441 // Register Multiplication
7442 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7443 match(Set dst (MulI src1 src2));
7444
7445 size(4);
7446 format %{ "MULX $src1,$src2,$dst" %}
7447 opcode(Assembler::mulx_op3, Assembler::arith_op);
7448 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7449 ins_pipe(imul_reg_reg);
7450 %}
7451
7452 // Immediate Multiplication
7453 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7454 match(Set dst (MulI src1 src2));
7455
7456 size(4);
7457 format %{ "MULX $src1,$src2,$dst" %}
7458 opcode(Assembler::mulx_op3, Assembler::arith_op);
7459 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7460 ins_pipe(imul_reg_imm);
7461 %}
7462
7463 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7464 match(Set dst (MulL src1 src2));
7465 ins_cost(DEFAULT_COST * 5);
7466 size(4);
7467 format %{ "MULX $src1,$src2,$dst\t! long" %}
7468 opcode(Assembler::mulx_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7470 ins_pipe(mulL_reg_reg);
7471 %}
7472
7473 // Immediate Multiplication
7474 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7475 match(Set dst (MulL src1 src2));
7476 ins_cost(DEFAULT_COST * 5);
7477 size(4);
7478 format %{ "MULX $src1,$src2,$dst" %}
7479 opcode(Assembler::mulx_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7481 ins_pipe(mulL_reg_imm);
7482 %}
7483
7484 // Integer Division
7485 // Register Division
7486 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7487 match(Set dst (DivI src1 src2));
7488 ins_cost((2+71)*DEFAULT_COST);
7489
7490 format %{ "SRA $src2,0,$src2\n\t"
7491 "SRA $src1,0,$src1\n\t"
7492 "SDIVX $src1,$src2,$dst" %}
7493 ins_encode( idiv_reg( src1, src2, dst ) );
7494 ins_pipe(sdiv_reg_reg);
7495 %}
7496
7497 // Immediate Division
7498 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7499 match(Set dst (DivI src1 src2));
7500 ins_cost((2+71)*DEFAULT_COST);
7501
7502 format %{ "SRA $src1,0,$src1\n\t"
7503 "SDIVX $src1,$src2,$dst" %}
7504 ins_encode( idiv_imm( src1, src2, dst ) );
7505 ins_pipe(sdiv_reg_imm);
7506 %}
7507
7508 //----------Div-By-10-Expansion------------------------------------------------
7509 // Extract hi bits of a 32x32->64 bit multiply.
7510 // Expand rule only, not matched
7511 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7512 effect( DEF dst, USE src1, USE src2 );
7513 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7514 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7515 ins_encode( enc_mul_hi(dst,src1,src2));
7516 ins_pipe(sdiv_reg_reg);
7517 %}
7518
7519 // Magic constant, reciprocal of 10
7520 instruct loadConI_x66666667(iRegIsafe dst) %{
7521 effect( DEF dst );
7522
7523 size(8);
7524 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7525 ins_encode( Set32(0x66666667, dst) );
7526 ins_pipe(ialu_hi_lo_reg);
7527 %}
7528
7529 // Register Shift Right Arithmetic Long by 32-63
7530 instruct sra_31( iRegI dst, iRegI src ) %{
7531 effect( DEF dst, USE src );
7532 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7533 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7534 ins_pipe(ialu_reg_reg);
7535 %}
7536
7537 // Arithmetic Shift Right by 8-bit immediate
7538 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7539 effect( DEF dst, USE src );
7540 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7541 opcode(Assembler::sra_op3, Assembler::arith_op);
7542 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7543 ins_pipe(ialu_reg_imm);
7544 %}
7545
7546 // Integer DIV with 10
7547 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7548 match(Set dst (DivI src div));
7549 ins_cost((6+6)*DEFAULT_COST);
7550 expand %{
7551 iRegIsafe tmp1; // Killed temps;
7552 iRegIsafe tmp2; // Killed temps;
7553 iRegI tmp3; // Killed temps;
7554 iRegI tmp4; // Killed temps;
7555 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7556 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7557 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7558 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7559 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7560 %}
7561 %}
7562
7563 // Register Long Division
7564 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7565 match(Set dst (DivL src1 src2));
7566 ins_cost(DEFAULT_COST*71);
7567 size(4);
7568 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7569 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7570 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7571 ins_pipe(divL_reg_reg);
7572 %}
7573
7574 // Register Long Division
7575 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7576 match(Set dst (DivL src1 src2));
7577 ins_cost(DEFAULT_COST*71);
7578 size(4);
7579 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7580 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7581 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7582 ins_pipe(divL_reg_imm);
7583 %}
7584
7585 // Integer Remainder
7586 // Register Remainder
7587 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7588 match(Set dst (ModI src1 src2));
7589 effect( KILL ccr, KILL temp);
7590
7591 format %{ "SREM $src1,$src2,$dst" %}
7592 ins_encode( irem_reg(src1, src2, dst, temp) );
7593 ins_pipe(sdiv_reg_reg);
7594 %}
7595
7596 // Immediate Remainder
7597 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7598 match(Set dst (ModI src1 src2));
7599 effect( KILL ccr, KILL temp);
7600
7601 format %{ "SREM $src1,$src2,$dst" %}
7602 ins_encode( irem_imm(src1, src2, dst, temp) );
7603 ins_pipe(sdiv_reg_imm);
7604 %}
7605
7606 // Register Long Remainder
7607 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7608 effect(DEF dst, USE src1, USE src2);
7609 size(4);
7610 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7611 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7612 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7613 ins_pipe(divL_reg_reg);
7614 %}
7615
7616 // Register Long Division
7617 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7618 effect(DEF dst, USE src1, USE src2);
7619 size(4);
7620 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7621 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7622 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7623 ins_pipe(divL_reg_imm);
7624 %}
7625
7626 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7627 effect(DEF dst, USE src1, USE src2);
7628 size(4);
7629 format %{ "MULX $src1,$src2,$dst\t! long" %}
7630 opcode(Assembler::mulx_op3, Assembler::arith_op);
7631 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7632 ins_pipe(mulL_reg_reg);
7633 %}
7634
7635 // Immediate Multiplication
7636 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7637 effect(DEF dst, USE src1, USE src2);
7638 size(4);
7639 format %{ "MULX $src1,$src2,$dst" %}
7640 opcode(Assembler::mulx_op3, Assembler::arith_op);
7641 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7642 ins_pipe(mulL_reg_imm);
7643 %}
7644
7645 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7646 effect(DEF dst, USE src1, USE src2);
7647 size(4);
7648 format %{ "SUB $src1,$src2,$dst\t! long" %}
7649 opcode(Assembler::sub_op3, Assembler::arith_op);
7650 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7651 ins_pipe(ialu_reg_reg);
7652 %}
7653
7654 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7655 effect(DEF dst, USE src1, USE src2);
7656 size(4);
7657 format %{ "SUB $src1,$src2,$dst\t! long" %}
7658 opcode(Assembler::sub_op3, Assembler::arith_op);
7659 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7660 ins_pipe(ialu_reg_reg);
7661 %}
7662
7663 // Register Long Remainder
7664 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7665 match(Set dst (ModL src1 src2));
7666 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7667 expand %{
7668 iRegL tmp1;
7669 iRegL tmp2;
7670 divL_reg_reg_1(tmp1, src1, src2);
7671 mulL_reg_reg_1(tmp2, tmp1, src2);
7672 subL_reg_reg_1(dst, src1, tmp2);
7673 %}
7674 %}
7675
7676 // Register Long Remainder
7677 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7678 match(Set dst (ModL src1 src2));
7679 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7680 expand %{
7681 iRegL tmp1;
7682 iRegL tmp2;
7683 divL_reg_imm13_1(tmp1, src1, src2);
7684 mulL_reg_imm13_1(tmp2, tmp1, src2);
7685 subL_reg_reg_2 (dst, src1, tmp2);
7686 %}
7687 %}
7688
7689 // Integer Shift Instructions
7690 // Register Shift Left
7691 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7692 match(Set dst (LShiftI src1 src2));
7693
7694 size(4);
7695 format %{ "SLL $src1,$src2,$dst" %}
7696 opcode(Assembler::sll_op3, Assembler::arith_op);
7697 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7698 ins_pipe(ialu_reg_reg);
7699 %}
7700
7701 // Register Shift Left Immediate
7702 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7703 match(Set dst (LShiftI src1 src2));
7704
7705 size(4);
7706 format %{ "SLL $src1,$src2,$dst" %}
7707 opcode(Assembler::sll_op3, Assembler::arith_op);
7708 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7709 ins_pipe(ialu_reg_imm);
7710 %}
7711
7712 // Register Shift Left
7713 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7714 match(Set dst (LShiftL src1 src2));
7715
7716 size(4);
7717 format %{ "SLLX $src1,$src2,$dst" %}
7718 opcode(Assembler::sllx_op3, Assembler::arith_op);
7719 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7720 ins_pipe(ialu_reg_reg);
7721 %}
7722
7723 // Register Shift Left Immediate
7724 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7725 match(Set dst (LShiftL src1 src2));
7726
7727 size(4);
7728 format %{ "SLLX $src1,$src2,$dst" %}
7729 opcode(Assembler::sllx_op3, Assembler::arith_op);
7730 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7731 ins_pipe(ialu_reg_imm);
7732 %}
7733
7734 // Register Arithmetic Shift Right
7735 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7736 match(Set dst (RShiftI src1 src2));
7737 size(4);
7738 format %{ "SRA $src1,$src2,$dst" %}
7739 opcode(Assembler::sra_op3, Assembler::arith_op);
7740 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7741 ins_pipe(ialu_reg_reg);
7742 %}
7743
7744 // Register Arithmetic Shift Right Immediate
7745 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7746 match(Set dst (RShiftI src1 src2));
7747
7748 size(4);
7749 format %{ "SRA $src1,$src2,$dst" %}
7750 opcode(Assembler::sra_op3, Assembler::arith_op);
7751 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7752 ins_pipe(ialu_reg_imm);
7753 %}
7754
7755 // Register Shift Right Arithmatic Long
7756 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7757 match(Set dst (RShiftL src1 src2));
7758
7759 size(4);
7760 format %{ "SRAX $src1,$src2,$dst" %}
7761 opcode(Assembler::srax_op3, Assembler::arith_op);
7762 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7763 ins_pipe(ialu_reg_reg);
7764 %}
7765
7766 // Register Shift Left Immediate
7767 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7768 match(Set dst (RShiftL src1 src2));
7769
7770 size(4);
7771 format %{ "SRAX $src1,$src2,$dst" %}
7772 opcode(Assembler::srax_op3, Assembler::arith_op);
7773 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7774 ins_pipe(ialu_reg_imm);
7775 %}
7776
7777 // Register Shift Right
7778 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7779 match(Set dst (URShiftI src1 src2));
7780
7781 size(4);
7782 format %{ "SRL $src1,$src2,$dst" %}
7783 opcode(Assembler::srl_op3, Assembler::arith_op);
7784 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7785 ins_pipe(ialu_reg_reg);
7786 %}
7787
7788 // Register Shift Right Immediate
7789 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7790 match(Set dst (URShiftI src1 src2));
7791
7792 size(4);
7793 format %{ "SRL $src1,$src2,$dst" %}
7794 opcode(Assembler::srl_op3, Assembler::arith_op);
7795 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7796 ins_pipe(ialu_reg_imm);
7797 %}
7798
7799 // Register Shift Right
7800 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7801 match(Set dst (URShiftL src1 src2));
7802
7803 size(4);
7804 format %{ "SRLX $src1,$src2,$dst" %}
7805 opcode(Assembler::srlx_op3, Assembler::arith_op);
7806 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7807 ins_pipe(ialu_reg_reg);
7808 %}
7809
7810 // Register Shift Right Immediate
7811 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7812 match(Set dst (URShiftL src1 src2));
7813
7814 size(4);
7815 format %{ "SRLX $src1,$src2,$dst" %}
7816 opcode(Assembler::srlx_op3, Assembler::arith_op);
7817 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7818 ins_pipe(ialu_reg_imm);
7819 %}
7820
7821 // Register Shift Right Immediate with a CastP2X
7822 #ifdef _LP64
7823 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7824 match(Set dst (URShiftL (CastP2X src1) src2));
7825 size(4);
7826 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7827 opcode(Assembler::srlx_op3, Assembler::arith_op);
7828 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7829 ins_pipe(ialu_reg_imm);
7830 %}
7831 #else
7832 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7833 match(Set dst (URShiftI (CastP2X src1) src2));
7834 size(4);
7835 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7836 opcode(Assembler::srl_op3, Assembler::arith_op);
7837 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7838 ins_pipe(ialu_reg_imm);
7839 %}
7840 #endif
7841
7842
7843 //----------Floating Point Arithmetic Instructions-----------------------------
7844
7845 // Add float single precision
7846 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7847 match(Set dst (AddF src1 src2));
7848
7849 size(4);
7850 format %{ "FADDS $src1,$src2,$dst" %}
7851 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7852 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7853 ins_pipe(faddF_reg_reg);
7854 %}
7855
7856 // Add float double precision
7857 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7858 match(Set dst (AddD src1 src2));
7859
7860 size(4);
7861 format %{ "FADDD $src1,$src2,$dst" %}
7862 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7863 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7864 ins_pipe(faddD_reg_reg);
7865 %}
7866
7867 // Sub float single precision
7868 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7869 match(Set dst (SubF src1 src2));
7870
7871 size(4);
7872 format %{ "FSUBS $src1,$src2,$dst" %}
7873 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7874 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7875 ins_pipe(faddF_reg_reg);
7876 %}
7877
7878 // Sub float double precision
7879 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7880 match(Set dst (SubD src1 src2));
7881
7882 size(4);
7883 format %{ "FSUBD $src1,$src2,$dst" %}
7884 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7885 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7886 ins_pipe(faddD_reg_reg);
7887 %}
7888
7889 // Mul float single precision
7890 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7891 match(Set dst (MulF src1 src2));
7892
7893 size(4);
7894 format %{ "FMULS $src1,$src2,$dst" %}
7895 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7896 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7897 ins_pipe(fmulF_reg_reg);
7898 %}
7899
7900 // Mul float double precision
7901 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7902 match(Set dst (MulD src1 src2));
7903
7904 size(4);
7905 format %{ "FMULD $src1,$src2,$dst" %}
7906 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7907 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7908 ins_pipe(fmulD_reg_reg);
7909 %}
7910
7911 // Div float single precision
7912 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7913 match(Set dst (DivF src1 src2));
7914
7915 size(4);
7916 format %{ "FDIVS $src1,$src2,$dst" %}
7917 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7918 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7919 ins_pipe(fdivF_reg_reg);
7920 %}
7921
7922 // Div float double precision
7923 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7924 match(Set dst (DivD src1 src2));
7925
7926 size(4);
7927 format %{ "FDIVD $src1,$src2,$dst" %}
7928 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7929 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7930 ins_pipe(fdivD_reg_reg);
7931 %}
7932
7933 // Absolute float double precision
7934 instruct absD_reg(regD dst, regD src) %{
7935 match(Set dst (AbsD src));
7936
7937 format %{ "FABSd $src,$dst" %}
7938 ins_encode(fabsd(dst, src));
7939 ins_pipe(faddD_reg);
7940 %}
7941
7942 // Absolute float single precision
7943 instruct absF_reg(regF dst, regF src) %{
7944 match(Set dst (AbsF src));
7945
7946 format %{ "FABSs $src,$dst" %}
7947 ins_encode(fabss(dst, src));
7948 ins_pipe(faddF_reg);
7949 %}
7950
7951 instruct negF_reg(regF dst, regF src) %{
7952 match(Set dst (NegF src));
7953
7954 size(4);
7955 format %{ "FNEGs $src,$dst" %}
7956 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7957 ins_encode(form3_opf_rs2F_rdF(src, dst));
7958 ins_pipe(faddF_reg);
7959 %}
7960
7961 instruct negD_reg(regD dst, regD src) %{
7962 match(Set dst (NegD src));
7963
7964 format %{ "FNEGd $src,$dst" %}
7965 ins_encode(fnegd(dst, src));
7966 ins_pipe(faddD_reg);
7967 %}
7968
7969 // Sqrt float double precision
7970 instruct sqrtF_reg_reg(regF dst, regF src) %{
7971 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7972
7973 size(4);
7974 format %{ "FSQRTS $src,$dst" %}
7975 ins_encode(fsqrts(dst, src));
7976 ins_pipe(fdivF_reg_reg);
7977 %}
7978
7979 // Sqrt float double precision
7980 instruct sqrtD_reg_reg(regD dst, regD src) %{
7981 match(Set dst (SqrtD src));
7982
7983 size(4);
7984 format %{ "FSQRTD $src,$dst" %}
7985 ins_encode(fsqrtd(dst, src));
7986 ins_pipe(fdivD_reg_reg);
7987 %}
7988
7989 //----------Logical Instructions-----------------------------------------------
7990 // And Instructions
7991 // Register And
7992 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7993 match(Set dst (AndI src1 src2));
7994
7995 size(4);
7996 format %{ "AND $src1,$src2,$dst" %}
7997 opcode(Assembler::and_op3, Assembler::arith_op);
7998 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7999 ins_pipe(ialu_reg_reg);
8000 %}
8001
8002 // Immediate And
8003 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8004 match(Set dst (AndI src1 src2));
8005
8006 size(4);
8007 format %{ "AND $src1,$src2,$dst" %}
8008 opcode(Assembler::and_op3, Assembler::arith_op);
8009 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8010 ins_pipe(ialu_reg_imm);
8011 %}
8012
8013 // Register And Long
8014 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8015 match(Set dst (AndL src1 src2));
8016
8017 ins_cost(DEFAULT_COST);
8018 size(4);
8019 format %{ "AND $src1,$src2,$dst\t! long" %}
8020 opcode(Assembler::and_op3, Assembler::arith_op);
8021 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8022 ins_pipe(ialu_reg_reg);
8023 %}
8024
8025 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8026 match(Set dst (AndL src1 con));
8027
8028 ins_cost(DEFAULT_COST);
8029 size(4);
8030 format %{ "AND $src1,$con,$dst\t! long" %}
8031 opcode(Assembler::and_op3, Assembler::arith_op);
8032 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8033 ins_pipe(ialu_reg_imm);
8034 %}
8035
8036 // Or Instructions
8037 // Register Or
8038 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8039 match(Set dst (OrI src1 src2));
8040
8041 size(4);
8042 format %{ "OR $src1,$src2,$dst" %}
8043 opcode(Assembler::or_op3, Assembler::arith_op);
8044 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8045 ins_pipe(ialu_reg_reg);
8046 %}
8047
8048 // Immediate Or
8049 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8050 match(Set dst (OrI src1 src2));
8051
8052 size(4);
8053 format %{ "OR $src1,$src2,$dst" %}
8054 opcode(Assembler::or_op3, Assembler::arith_op);
8055 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8056 ins_pipe(ialu_reg_imm);
8057 %}
8058
8059 // Register Or Long
8060 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8061 match(Set dst (OrL src1 src2));
8062
8063 ins_cost(DEFAULT_COST);
8064 size(4);
8065 format %{ "OR $src1,$src2,$dst\t! long" %}
8066 opcode(Assembler::or_op3, Assembler::arith_op);
8067 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8068 ins_pipe(ialu_reg_reg);
8069 %}
8070
8071 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8072 match(Set dst (OrL src1 con));
8073 ins_cost(DEFAULT_COST*2);
8074
8075 ins_cost(DEFAULT_COST);
8076 size(4);
8077 format %{ "OR $src1,$con,$dst\t! long" %}
8078 opcode(Assembler::or_op3, Assembler::arith_op);
8079 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8080 ins_pipe(ialu_reg_imm);
8081 %}
8082
8083 #ifndef _LP64
8084
8085 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8086 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8087 match(Set dst (OrI src1 (CastP2X src2)));
8088
8089 size(4);
8090 format %{ "OR $src1,$src2,$dst" %}
8091 opcode(Assembler::or_op3, Assembler::arith_op);
8092 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8093 ins_pipe(ialu_reg_reg);
8094 %}
8095
8096 #else
8097
8098 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8099 match(Set dst (OrL src1 (CastP2X src2)));
8100
8101 ins_cost(DEFAULT_COST);
8102 size(4);
8103 format %{ "OR $src1,$src2,$dst\t! long" %}
8104 opcode(Assembler::or_op3, Assembler::arith_op);
8105 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8106 ins_pipe(ialu_reg_reg);
8107 %}
8108
8109 #endif
8110
8111 // Xor Instructions
8112 // Register Xor
8113 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8114 match(Set dst (XorI src1 src2));
8115
8116 size(4);
8117 format %{ "XOR $src1,$src2,$dst" %}
8118 opcode(Assembler::xor_op3, Assembler::arith_op);
8119 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8120 ins_pipe(ialu_reg_reg);
8121 %}
8122
8123 // Immediate Xor
8124 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8125 match(Set dst (XorI src1 src2));
8126
8127 size(4);
8128 format %{ "XOR $src1,$src2,$dst" %}
8129 opcode(Assembler::xor_op3, Assembler::arith_op);
8130 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8131 ins_pipe(ialu_reg_imm);
8132 %}
8133
8134 // Register Xor Long
8135 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8136 match(Set dst (XorL src1 src2));
8137
8138 ins_cost(DEFAULT_COST);
8139 size(4);
8140 format %{ "XOR $src1,$src2,$dst\t! long" %}
8141 opcode(Assembler::xor_op3, Assembler::arith_op);
8142 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8143 ins_pipe(ialu_reg_reg);
8144 %}
8145
8146 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8147 match(Set dst (XorL src1 con));
8148
8149 ins_cost(DEFAULT_COST);
8150 size(4);
8151 format %{ "XOR $src1,$con,$dst\t! long" %}
8152 opcode(Assembler::xor_op3, Assembler::arith_op);
8153 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8154 ins_pipe(ialu_reg_imm);
8155 %}
8156
8157 //----------Convert to Boolean-------------------------------------------------
8158 // Nice hack for 32-bit tests but doesn't work for
8159 // 64-bit pointers.
8160 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8161 match(Set dst (Conv2B src));
8162 effect( KILL ccr );
8163 ins_cost(DEFAULT_COST*2);
8164 format %{ "CMP R_G0,$src\n\t"
8165 "ADDX R_G0,0,$dst" %}
8166 ins_encode( enc_to_bool( src, dst ) );
8167 ins_pipe(ialu_reg_ialu);
8168 %}
8169
8170 #ifndef _LP64
8171 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8172 match(Set dst (Conv2B src));
8173 effect( KILL ccr );
8174 ins_cost(DEFAULT_COST*2);
8175 format %{ "CMP R_G0,$src\n\t"
8176 "ADDX R_G0,0,$dst" %}
8177 ins_encode( enc_to_bool( src, dst ) );
8178 ins_pipe(ialu_reg_ialu);
8179 %}
8180 #else
8181 instruct convP2B( iRegI dst, iRegP src ) %{
8182 match(Set dst (Conv2B src));
8183 ins_cost(DEFAULT_COST*2);
8184 format %{ "MOV $src,$dst\n\t"
8185 "MOVRNZ $src,1,$dst" %}
8186 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8187 ins_pipe(ialu_clr_and_mover);
8188 %}
8189 #endif
8190
8191 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8192 match(Set dst (CmpLTMask src zero));
8193 effect(KILL ccr);
8194 size(4);
8195 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8196 ins_encode %{
8197 __ sra($src$$Register, 31, $dst$$Register);
8198 %}
8199 ins_pipe(ialu_reg_imm);
8200 %}
8201
8202 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8203 match(Set dst (CmpLTMask p q));
8204 effect( KILL ccr );
8205 ins_cost(DEFAULT_COST*4);
8206 format %{ "CMP $p,$q\n\t"
8207 "MOV #0,$dst\n\t"
8208 "BLT,a .+8\n\t"
8209 "MOV #-1,$dst" %}
8210 ins_encode( enc_ltmask(p,q,dst) );
8211 ins_pipe(ialu_reg_reg_ialu);
8212 %}
8213
8214 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8215 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8216 effect(KILL ccr, TEMP tmp);
8217 ins_cost(DEFAULT_COST*3);
8218
8219 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8220 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8221 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8222 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8223 ins_pipe(cadd_cmpltmask);
8224 %}
8225
8226 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8227 match(Set p (AndI (CmpLTMask p q) y));
8228 effect(KILL ccr);
8229 ins_cost(DEFAULT_COST*3);
8230
8231 format %{ "CMP $p,$q\n\t"
8232 "MOV $y,$p\n\t"
8233 "MOVge G0,$p" %}
8234 ins_encode %{
8235 __ cmp($p$$Register, $q$$Register);
8236 __ mov($y$$Register, $p$$Register);
8237 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8238 %}
8239 ins_pipe(ialu_reg_reg_ialu);
8240 %}
8241
8242 //-----------------------------------------------------------------
8243 // Direct raw moves between float and general registers using VIS3.
8244
8245 // ins_pipe(faddF_reg);
8246 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8247 predicate(UseVIS >= 3);
8248 match(Set dst (MoveF2I src));
8249
8250 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8251 ins_encode %{
8252 __ movstouw($src$$FloatRegister, $dst$$Register);
8253 %}
8254 ins_pipe(ialu_reg_reg);
8255 %}
8256
8257 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8258 predicate(UseVIS >= 3);
8259 match(Set dst (MoveI2F src));
8260
8261 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8262 ins_encode %{
8263 __ movwtos($src$$Register, $dst$$FloatRegister);
8264 %}
8265 ins_pipe(ialu_reg_reg);
8266 %}
8267
8268 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8269 predicate(UseVIS >= 3);
8270 match(Set dst (MoveD2L src));
8271
8272 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8273 ins_encode %{
8274 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8275 %}
8276 ins_pipe(ialu_reg_reg);
8277 %}
8278
8279 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8280 predicate(UseVIS >= 3);
8281 match(Set dst (MoveL2D src));
8282
8283 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8284 ins_encode %{
8285 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8286 %}
8287 ins_pipe(ialu_reg_reg);
8288 %}
8289
8290
8291 // Raw moves between float and general registers using stack.
8292
8293 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8294 match(Set dst (MoveF2I src));
8295 effect(DEF dst, USE src);
8296 ins_cost(MEMORY_REF_COST);
8297
8298 size(4);
8299 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8300 opcode(Assembler::lduw_op3);
8301 ins_encode(simple_form3_mem_reg( src, dst ) );
8302 ins_pipe(iload_mem);
8303 %}
8304
8305 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8306 match(Set dst (MoveI2F src));
8307 effect(DEF dst, USE src);
8308 ins_cost(MEMORY_REF_COST);
8309
8310 size(4);
8311 format %{ "LDF $src,$dst\t! MoveI2F" %}
8312 opcode(Assembler::ldf_op3);
8313 ins_encode(simple_form3_mem_reg(src, dst));
8314 ins_pipe(floadF_stk);
8315 %}
8316
8317 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8318 match(Set dst (MoveD2L src));
8319 effect(DEF dst, USE src);
8320 ins_cost(MEMORY_REF_COST);
8321
8322 size(4);
8323 format %{ "LDX $src,$dst\t! MoveD2L" %}
8324 opcode(Assembler::ldx_op3);
8325 ins_encode(simple_form3_mem_reg( src, dst ) );
8326 ins_pipe(iload_mem);
8327 %}
8328
8329 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8330 match(Set dst (MoveL2D src));
8331 effect(DEF dst, USE src);
8332 ins_cost(MEMORY_REF_COST);
8333
8334 size(4);
8335 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8336 opcode(Assembler::lddf_op3);
8337 ins_encode(simple_form3_mem_reg(src, dst));
8338 ins_pipe(floadD_stk);
8339 %}
8340
8341 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8342 match(Set dst (MoveF2I src));
8343 effect(DEF dst, USE src);
8344 ins_cost(MEMORY_REF_COST);
8345
8346 size(4);
8347 format %{ "STF $src,$dst\t! MoveF2I" %}
8348 opcode(Assembler::stf_op3);
8349 ins_encode(simple_form3_mem_reg(dst, src));
8350 ins_pipe(fstoreF_stk_reg);
8351 %}
8352
8353 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8354 match(Set dst (MoveI2F src));
8355 effect(DEF dst, USE src);
8356 ins_cost(MEMORY_REF_COST);
8357
8358 size(4);
8359 format %{ "STW $src,$dst\t! MoveI2F" %}
8360 opcode(Assembler::stw_op3);
8361 ins_encode(simple_form3_mem_reg( dst, src ) );
8362 ins_pipe(istore_mem_reg);
8363 %}
8364
8365 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8366 match(Set dst (MoveD2L src));
8367 effect(DEF dst, USE src);
8368 ins_cost(MEMORY_REF_COST);
8369
8370 size(4);
8371 format %{ "STDF $src,$dst\t! MoveD2L" %}
8372 opcode(Assembler::stdf_op3);
8373 ins_encode(simple_form3_mem_reg(dst, src));
8374 ins_pipe(fstoreD_stk_reg);
8375 %}
8376
8377 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8378 match(Set dst (MoveL2D src));
8379 effect(DEF dst, USE src);
8380 ins_cost(MEMORY_REF_COST);
8381
8382 size(4);
8383 format %{ "STX $src,$dst\t! MoveL2D" %}
8384 opcode(Assembler::stx_op3);
8385 ins_encode(simple_form3_mem_reg( dst, src ) );
8386 ins_pipe(istore_mem_reg);
8387 %}
8388
8389
8390 //----------Arithmetic Conversion Instructions---------------------------------
8391 // The conversions operations are all Alpha sorted. Please keep it that way!
8392
8393 instruct convD2F_reg(regF dst, regD src) %{
8394 match(Set dst (ConvD2F src));
8395 size(4);
8396 format %{ "FDTOS $src,$dst" %}
8397 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8398 ins_encode(form3_opf_rs2D_rdF(src, dst));
8399 ins_pipe(fcvtD2F);
8400 %}
8401
8402
8403 // Convert a double to an int in a float register.
8404 // If the double is a NAN, stuff a zero in instead.
8405 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8406 effect(DEF dst, USE src, KILL fcc0);
8407 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8408 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8409 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8410 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8411 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8412 "skip:" %}
8413 ins_encode(form_d2i_helper(src,dst));
8414 ins_pipe(fcvtD2I);
8415 %}
8416
8417 instruct convD2I_stk(stackSlotI dst, regD src) %{
8418 match(Set dst (ConvD2I src));
8419 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8420 expand %{
8421 regF tmp;
8422 convD2I_helper(tmp, src);
8423 regF_to_stkI(dst, tmp);
8424 %}
8425 %}
8426
8427 instruct convD2I_reg(iRegI dst, regD src) %{
8428 predicate(UseVIS >= 3);
8429 match(Set dst (ConvD2I src));
8430 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8431 expand %{
8432 regF tmp;
8433 convD2I_helper(tmp, src);
8434 MoveF2I_reg_reg(dst, tmp);
8435 %}
8436 %}
8437
8438
8439 // Convert a double to a long in a double register.
8440 // If the double is a NAN, stuff a zero in instead.
8441 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8442 effect(DEF dst, USE src, KILL fcc0);
8443 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8444 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8445 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8446 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8447 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8448 "skip:" %}
8449 ins_encode(form_d2l_helper(src,dst));
8450 ins_pipe(fcvtD2L);
8451 %}
8452
8453 instruct convD2L_stk(stackSlotL dst, regD src) %{
8454 match(Set dst (ConvD2L src));
8455 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8456 expand %{
8457 regD tmp;
8458 convD2L_helper(tmp, src);
8459 regD_to_stkL(dst, tmp);
8460 %}
8461 %}
8462
8463 instruct convD2L_reg(iRegL dst, regD src) %{
8464 predicate(UseVIS >= 3);
8465 match(Set dst (ConvD2L src));
8466 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8467 expand %{
8468 regD tmp;
8469 convD2L_helper(tmp, src);
8470 MoveD2L_reg_reg(dst, tmp);
8471 %}
8472 %}
8473
8474
8475 instruct convF2D_reg(regD dst, regF src) %{
8476 match(Set dst (ConvF2D src));
8477 format %{ "FSTOD $src,$dst" %}
8478 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8479 ins_encode(form3_opf_rs2F_rdD(src, dst));
8480 ins_pipe(fcvtF2D);
8481 %}
8482
8483
8484 // Convert a float to an int in a float register.
8485 // If the float is a NAN, stuff a zero in instead.
8486 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8487 effect(DEF dst, USE src, KILL fcc0);
8488 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8489 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8490 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8491 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8492 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8493 "skip:" %}
8494 ins_encode(form_f2i_helper(src,dst));
8495 ins_pipe(fcvtF2I);
8496 %}
8497
8498 instruct convF2I_stk(stackSlotI dst, regF src) %{
8499 match(Set dst (ConvF2I src));
8500 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8501 expand %{
8502 regF tmp;
8503 convF2I_helper(tmp, src);
8504 regF_to_stkI(dst, tmp);
8505 %}
8506 %}
8507
8508 instruct convF2I_reg(iRegI dst, regF src) %{
8509 predicate(UseVIS >= 3);
8510 match(Set dst (ConvF2I src));
8511 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8512 expand %{
8513 regF tmp;
8514 convF2I_helper(tmp, src);
8515 MoveF2I_reg_reg(dst, tmp);
8516 %}
8517 %}
8518
8519
8520 // Convert a float to a long in a float register.
8521 // If the float is a NAN, stuff a zero in instead.
8522 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8523 effect(DEF dst, USE src, KILL fcc0);
8524 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8525 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8526 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8527 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8528 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8529 "skip:" %}
8530 ins_encode(form_f2l_helper(src,dst));
8531 ins_pipe(fcvtF2L);
8532 %}
8533
8534 instruct convF2L_stk(stackSlotL dst, regF src) %{
8535 match(Set dst (ConvF2L src));
8536 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8537 expand %{
8538 regD tmp;
8539 convF2L_helper(tmp, src);
8540 regD_to_stkL(dst, tmp);
8541 %}
8542 %}
8543
8544 instruct convF2L_reg(iRegL dst, regF src) %{
8545 predicate(UseVIS >= 3);
8546 match(Set dst (ConvF2L src));
8547 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8548 expand %{
8549 regD tmp;
8550 convF2L_helper(tmp, src);
8551 MoveD2L_reg_reg(dst, tmp);
8552 %}
8553 %}
8554
8555
8556 instruct convI2D_helper(regD dst, regF tmp) %{
8557 effect(USE tmp, DEF dst);
8558 format %{ "FITOD $tmp,$dst" %}
8559 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8560 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8561 ins_pipe(fcvtI2D);
8562 %}
8563
8564 instruct convI2D_stk(stackSlotI src, regD dst) %{
8565 match(Set dst (ConvI2D src));
8566 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8567 expand %{
8568 regF tmp;
8569 stkI_to_regF(tmp, src);
8570 convI2D_helper(dst, tmp);
8571 %}
8572 %}
8573
8574 instruct convI2D_reg(regD_low dst, iRegI src) %{
8575 predicate(UseVIS >= 3);
8576 match(Set dst (ConvI2D src));
8577 expand %{
8578 regF tmp;
8579 MoveI2F_reg_reg(tmp, src);
8580 convI2D_helper(dst, tmp);
8581 %}
8582 %}
8583
8584 instruct convI2D_mem(regD_low dst, memory mem) %{
8585 match(Set dst (ConvI2D (LoadI mem)));
8586 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8587 size(8);
8588 format %{ "LDF $mem,$dst\n\t"
8589 "FITOD $dst,$dst" %}
8590 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8591 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8592 ins_pipe(floadF_mem);
8593 %}
8594
8595
8596 instruct convI2F_helper(regF dst, regF tmp) %{
8597 effect(DEF dst, USE tmp);
8598 format %{ "FITOS $tmp,$dst" %}
8599 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8600 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8601 ins_pipe(fcvtI2F);
8602 %}
8603
8604 instruct convI2F_stk(regF dst, stackSlotI src) %{
8605 match(Set dst (ConvI2F src));
8606 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8607 expand %{
8608 regF tmp;
8609 stkI_to_regF(tmp,src);
8610 convI2F_helper(dst, tmp);
8611 %}
8612 %}
8613
8614 instruct convI2F_reg(regF dst, iRegI src) %{
8615 predicate(UseVIS >= 3);
8616 match(Set dst (ConvI2F src));
8617 ins_cost(DEFAULT_COST);
8618 expand %{
8619 regF tmp;
8620 MoveI2F_reg_reg(tmp, src);
8621 convI2F_helper(dst, tmp);
8622 %}
8623 %}
8624
8625 instruct convI2F_mem( regF dst, memory mem ) %{
8626 match(Set dst (ConvI2F (LoadI mem)));
8627 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8628 size(8);
8629 format %{ "LDF $mem,$dst\n\t"
8630 "FITOS $dst,$dst" %}
8631 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8632 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8633 ins_pipe(floadF_mem);
8634 %}
8635
8636
8637 instruct convI2L_reg(iRegL dst, iRegI src) %{
8638 match(Set dst (ConvI2L src));
8639 size(4);
8640 format %{ "SRA $src,0,$dst\t! int->long" %}
8641 opcode(Assembler::sra_op3, Assembler::arith_op);
8642 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8643 ins_pipe(ialu_reg_reg);
8644 %}
8645
8646 // Zero-extend convert int to long
8647 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8648 match(Set dst (AndL (ConvI2L src) mask) );
8649 size(4);
8650 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8651 opcode(Assembler::srl_op3, Assembler::arith_op);
8652 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8653 ins_pipe(ialu_reg_reg);
8654 %}
8655
8656 // Zero-extend long
8657 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8658 match(Set dst (AndL src mask) );
8659 size(4);
8660 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8661 opcode(Assembler::srl_op3, Assembler::arith_op);
8662 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8663 ins_pipe(ialu_reg_reg);
8664 %}
8665
8666
8667 //-----------
8668 // Long to Double conversion using V8 opcodes.
8669 // Still useful because cheetah traps and becomes
8670 // amazingly slow for some common numbers.
8671
8672 // Magic constant, 0x43300000
8673 instruct loadConI_x43300000(iRegI dst) %{
8674 effect(DEF dst);
8675 size(4);
8676 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8677 ins_encode(SetHi22(0x43300000, dst));
8678 ins_pipe(ialu_none);
8679 %}
8680
8681 // Magic constant, 0x41f00000
8682 instruct loadConI_x41f00000(iRegI dst) %{
8683 effect(DEF dst);
8684 size(4);
8685 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8686 ins_encode(SetHi22(0x41f00000, dst));
8687 ins_pipe(ialu_none);
8688 %}
8689
8690 // Construct a double from two float halves
8691 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8692 effect(DEF dst, USE src1, USE src2);
8693 size(8);
8694 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8695 "FMOVS $src2.lo,$dst.lo" %}
8696 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8697 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8698 ins_pipe(faddD_reg_reg);
8699 %}
8700
8701 // Convert integer in high half of a double register (in the lower half of
8702 // the double register file) to double
8703 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8704 effect(DEF dst, USE src);
8705 size(4);
8706 format %{ "FITOD $src,$dst" %}
8707 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8708 ins_encode(form3_opf_rs2D_rdD(src, dst));
8709 ins_pipe(fcvtLHi2D);
8710 %}
8711
8712 // Add float double precision
8713 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8714 effect(DEF dst, USE src1, USE src2);
8715 size(4);
8716 format %{ "FADDD $src1,$src2,$dst" %}
8717 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8718 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8719 ins_pipe(faddD_reg_reg);
8720 %}
8721
8722 // Sub float double precision
8723 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8724 effect(DEF dst, USE src1, USE src2);
8725 size(4);
8726 format %{ "FSUBD $src1,$src2,$dst" %}
8727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8728 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8729 ins_pipe(faddD_reg_reg);
8730 %}
8731
8732 // Mul float double precision
8733 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8734 effect(DEF dst, USE src1, USE src2);
8735 size(4);
8736 format %{ "FMULD $src1,$src2,$dst" %}
8737 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8738 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8739 ins_pipe(fmulD_reg_reg);
8740 %}
8741
8742 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8743 match(Set dst (ConvL2D src));
8744 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8745
8746 expand %{
8747 regD_low tmpsrc;
8748 iRegI ix43300000;
8749 iRegI ix41f00000;
8750 stackSlotL lx43300000;
8751 stackSlotL lx41f00000;
8752 regD_low dx43300000;
8753 regD dx41f00000;
8754 regD tmp1;
8755 regD_low tmp2;
8756 regD tmp3;
8757 regD tmp4;
8758
8759 stkL_to_regD(tmpsrc, src);
8760
8761 loadConI_x43300000(ix43300000);
8762 loadConI_x41f00000(ix41f00000);
8763 regI_to_stkLHi(lx43300000, ix43300000);
8764 regI_to_stkLHi(lx41f00000, ix41f00000);
8765 stkL_to_regD(dx43300000, lx43300000);
8766 stkL_to_regD(dx41f00000, lx41f00000);
8767
8768 convI2D_regDHi_regD(tmp1, tmpsrc);
8769 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8770 subD_regD_regD(tmp3, tmp2, dx43300000);
8771 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8772 addD_regD_regD(dst, tmp3, tmp4);
8773 %}
8774 %}
8775
8776 // Long to Double conversion using fast fxtof
8777 instruct convL2D_helper(regD dst, regD tmp) %{
8778 effect(DEF dst, USE tmp);
8779 size(4);
8780 format %{ "FXTOD $tmp,$dst" %}
8781 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8782 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8783 ins_pipe(fcvtL2D);
8784 %}
8785
8786 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8787 predicate(VM_Version::has_fast_fxtof());
8788 match(Set dst (ConvL2D src));
8789 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8790 expand %{
8791 regD tmp;
8792 stkL_to_regD(tmp, src);
8793 convL2D_helper(dst, tmp);
8794 %}
8795 %}
8796
8797 instruct convL2D_reg(regD dst, iRegL src) %{
8798 predicate(UseVIS >= 3);
8799 match(Set dst (ConvL2D src));
8800 expand %{
8801 regD tmp;
8802 MoveL2D_reg_reg(tmp, src);
8803 convL2D_helper(dst, tmp);
8804 %}
8805 %}
8806
8807 // Long to Float conversion using fast fxtof
8808 instruct convL2F_helper(regF dst, regD tmp) %{
8809 effect(DEF dst, USE tmp);
8810 size(4);
8811 format %{ "FXTOS $tmp,$dst" %}
8812 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8813 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8814 ins_pipe(fcvtL2F);
8815 %}
8816
8817 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8818 match(Set dst (ConvL2F src));
8819 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8820 expand %{
8821 regD tmp;
8822 stkL_to_regD(tmp, src);
8823 convL2F_helper(dst, tmp);
8824 %}
8825 %}
8826
8827 instruct convL2F_reg(regF dst, iRegL src) %{
8828 predicate(UseVIS >= 3);
8829 match(Set dst (ConvL2F src));
8830 ins_cost(DEFAULT_COST);
8831 expand %{
8832 regD tmp;
8833 MoveL2D_reg_reg(tmp, src);
8834 convL2F_helper(dst, tmp);
8835 %}
8836 %}
8837
8838 //-----------
8839
8840 instruct convL2I_reg(iRegI dst, iRegL src) %{
8841 match(Set dst (ConvL2I src));
8842 #ifndef _LP64
8843 format %{ "MOV $src.lo,$dst\t! long->int" %}
8844 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8845 ins_pipe(ialu_move_reg_I_to_L);
8846 #else
8847 size(4);
8848 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8849 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8850 ins_pipe(ialu_reg);
8851 #endif
8852 %}
8853
8854 // Register Shift Right Immediate
8855 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8856 match(Set dst (ConvL2I (RShiftL src cnt)));
8857
8858 size(4);
8859 format %{ "SRAX $src,$cnt,$dst" %}
8860 opcode(Assembler::srax_op3, Assembler::arith_op);
8861 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8862 ins_pipe(ialu_reg_imm);
8863 %}
8864
8865 //----------Control Flow Instructions------------------------------------------
8866 // Compare Instructions
8867 // Compare Integers
8868 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8869 match(Set icc (CmpI op1 op2));
8870 effect( DEF icc, USE op1, USE op2 );
8871
8872 size(4);
8873 format %{ "CMP $op1,$op2" %}
8874 opcode(Assembler::subcc_op3, Assembler::arith_op);
8875 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8876 ins_pipe(ialu_cconly_reg_reg);
8877 %}
8878
8879 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8880 match(Set icc (CmpU op1 op2));
8881
8882 size(4);
8883 format %{ "CMP $op1,$op2\t! unsigned" %}
8884 opcode(Assembler::subcc_op3, Assembler::arith_op);
8885 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8886 ins_pipe(ialu_cconly_reg_reg);
8887 %}
8888
8889 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8890 match(Set icc (CmpI op1 op2));
8891 effect( DEF icc, USE op1 );
8892
8893 size(4);
8894 format %{ "CMP $op1,$op2" %}
8895 opcode(Assembler::subcc_op3, Assembler::arith_op);
8896 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8897 ins_pipe(ialu_cconly_reg_imm);
8898 %}
8899
8900 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8901 match(Set icc (CmpI (AndI op1 op2) zero));
8902
8903 size(4);
8904 format %{ "BTST $op2,$op1" %}
8905 opcode(Assembler::andcc_op3, Assembler::arith_op);
8906 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8907 ins_pipe(ialu_cconly_reg_reg_zero);
8908 %}
8909
8910 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8911 match(Set icc (CmpI (AndI op1 op2) zero));
8912
8913 size(4);
8914 format %{ "BTST $op2,$op1" %}
8915 opcode(Assembler::andcc_op3, Assembler::arith_op);
8916 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8917 ins_pipe(ialu_cconly_reg_imm_zero);
8918 %}
8919
8920 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8921 match(Set xcc (CmpL op1 op2));
8922 effect( DEF xcc, USE op1, USE op2 );
8923
8924 size(4);
8925 format %{ "CMP $op1,$op2\t\t! long" %}
8926 opcode(Assembler::subcc_op3, Assembler::arith_op);
8927 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8928 ins_pipe(ialu_cconly_reg_reg);
8929 %}
8930
8931 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8932 match(Set xcc (CmpL op1 con));
8933 effect( DEF xcc, USE op1, USE con );
8934
8935 size(4);
8936 format %{ "CMP $op1,$con\t\t! long" %}
8937 opcode(Assembler::subcc_op3, Assembler::arith_op);
8938 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8939 ins_pipe(ialu_cconly_reg_reg);
8940 %}
8941
8942 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8943 match(Set xcc (CmpL (AndL op1 op2) zero));
8944 effect( DEF xcc, USE op1, USE op2 );
8945
8946 size(4);
8947 format %{ "BTST $op1,$op2\t\t! long" %}
8948 opcode(Assembler::andcc_op3, Assembler::arith_op);
8949 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8950 ins_pipe(ialu_cconly_reg_reg);
8951 %}
8952
8953 // useful for checking the alignment of a pointer:
8954 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8955 match(Set xcc (CmpL (AndL op1 con) zero));
8956 effect( DEF xcc, USE op1, USE con );
8957
8958 size(4);
8959 format %{ "BTST $op1,$con\t\t! long" %}
8960 opcode(Assembler::andcc_op3, Assembler::arith_op);
8961 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8962 ins_pipe(ialu_cconly_reg_reg);
8963 %}
8964
8965 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8966 match(Set icc (CmpU op1 op2));
8967
8968 size(4);
8969 format %{ "CMP $op1,$op2\t! unsigned" %}
8970 opcode(Assembler::subcc_op3, Assembler::arith_op);
8971 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8972 ins_pipe(ialu_cconly_reg_imm);
8973 %}
8974
8975 // Compare Pointers
8976 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8977 match(Set pcc (CmpP op1 op2));
8978
8979 size(4);
8980 format %{ "CMP $op1,$op2\t! ptr" %}
8981 opcode(Assembler::subcc_op3, Assembler::arith_op);
8982 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8983 ins_pipe(ialu_cconly_reg_reg);
8984 %}
8985
8986 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8987 match(Set pcc (CmpP op1 op2));
8988
8989 size(4);
8990 format %{ "CMP $op1,$op2\t! ptr" %}
8991 opcode(Assembler::subcc_op3, Assembler::arith_op);
8992 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8993 ins_pipe(ialu_cconly_reg_imm);
8994 %}
8995
8996 // Compare Narrow oops
8997 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8998 match(Set icc (CmpN op1 op2));
8999
9000 size(4);
9001 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9002 opcode(Assembler::subcc_op3, Assembler::arith_op);
9003 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9004 ins_pipe(ialu_cconly_reg_reg);
9005 %}
9006
9007 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9008 match(Set icc (CmpN op1 op2));
9009
9010 size(4);
9011 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9012 opcode(Assembler::subcc_op3, Assembler::arith_op);
9013 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9014 ins_pipe(ialu_cconly_reg_imm);
9015 %}
9016
9017 //----------Max and Min--------------------------------------------------------
9018 // Min Instructions
9019 // Conditional move for min
9020 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9021 effect( USE_DEF op2, USE op1, USE icc );
9022
9023 size(4);
9024 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9025 opcode(Assembler::less);
9026 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9027 ins_pipe(ialu_reg_flags);
9028 %}
9029
9030 // Min Register with Register.
9031 instruct minI_eReg(iRegI op1, iRegI op2) %{
9032 match(Set op2 (MinI op1 op2));
9033 ins_cost(DEFAULT_COST*2);
9034 expand %{
9035 flagsReg icc;
9036 compI_iReg(icc,op1,op2);
9037 cmovI_reg_lt(op2,op1,icc);
9038 %}
9039 %}
9040
9041 // Max Instructions
9042 // Conditional move for max
9043 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9044 effect( USE_DEF op2, USE op1, USE icc );
9045 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9046 opcode(Assembler::greater);
9047 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9048 ins_pipe(ialu_reg_flags);
9049 %}
9050
9051 // Max Register with Register
9052 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9053 match(Set op2 (MaxI op1 op2));
9054 ins_cost(DEFAULT_COST*2);
9055 expand %{
9056 flagsReg icc;
9057 compI_iReg(icc,op1,op2);
9058 cmovI_reg_gt(op2,op1,icc);
9059 %}
9060 %}
9061
9062
9063 //----------Float Compares----------------------------------------------------
9064 // Compare floating, generate condition code
9065 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9066 match(Set fcc (CmpF src1 src2));
9067
9068 size(4);
9069 format %{ "FCMPs $fcc,$src1,$src2" %}
9070 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9071 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9072 ins_pipe(faddF_fcc_reg_reg_zero);
9073 %}
9074
9075 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9076 match(Set fcc (CmpD src1 src2));
9077
9078 size(4);
9079 format %{ "FCMPd $fcc,$src1,$src2" %}
9080 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9081 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9082 ins_pipe(faddD_fcc_reg_reg_zero);
9083 %}
9084
9085
9086 // Compare floating, generate -1,0,1
9087 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9088 match(Set dst (CmpF3 src1 src2));
9089 effect(KILL fcc0);
9090 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9091 format %{ "fcmpl $dst,$src1,$src2" %}
9092 // Primary = float
9093 opcode( true );
9094 ins_encode( floating_cmp( dst, src1, src2 ) );
9095 ins_pipe( floating_cmp );
9096 %}
9097
9098 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9099 match(Set dst (CmpD3 src1 src2));
9100 effect(KILL fcc0);
9101 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9102 format %{ "dcmpl $dst,$src1,$src2" %}
9103 // Primary = double (not float)
9104 opcode( false );
9105 ins_encode( floating_cmp( dst, src1, src2 ) );
9106 ins_pipe( floating_cmp );
9107 %}
9108
9109 //----------Branches---------------------------------------------------------
9110 // Jump
9111 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9112 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9113 match(Jump switch_val);
9114 effect(TEMP table);
9115
9116 ins_cost(350);
9117
9118 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9119 "LD [O7 + $switch_val], O7\n\t"
9120 "JUMP O7" %}
9121 ins_encode %{
9122 // Calculate table address into a register.
9123 Register table_reg;
9124 Register label_reg = O7;
9125 // If we are calculating the size of this instruction don't trust
9126 // zero offsets because they might change when
9127 // MachConstantBaseNode decides to optimize the constant table
9128 // base.
9129 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9130 table_reg = $constanttablebase;
9131 } else {
9132 table_reg = O7;
9133 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9134 __ add($constanttablebase, con_offset, table_reg);
9135 }
9136
9137 // Jump to base address + switch value
9138 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9139 __ jmp(label_reg, G0);
9140 __ delayed()->nop();
9141 %}
9142 ins_pipe(ialu_reg_reg);
9143 %}
9144
9145 // Direct Branch. Use V8 version with longer range.
9146 instruct branch(label labl) %{
9147 match(Goto);
9148 effect(USE labl);
9149
9150 size(8);
9151 ins_cost(BRANCH_COST);
9152 format %{ "BA $labl" %}
9153 ins_encode %{
9154 Label* L = $labl$$label;
9155 __ ba(*L);
9156 __ delayed()->nop();
9157 %}
9158 ins_pipe(br);
9159 %}
9160
9161 // Direct Branch, short with no delay slot
9162 instruct branch_short(label labl) %{
9163 match(Goto);
9164 predicate(UseCBCond);
9165 effect(USE labl);
9166
9167 size(4);
9168 ins_cost(BRANCH_COST);
9169 format %{ "BA $labl\t! short branch" %}
9170 ins_encode %{
9171 Label* L = $labl$$label;
9172 assert(__ use_cbcond(*L), "back to back cbcond");
9173 __ ba_short(*L);
9174 %}
9175 ins_short_branch(1);
9176 ins_avoid_back_to_back(1);
9177 ins_pipe(cbcond_reg_imm);
9178 %}
9179
9180 // Conditional Direct Branch
9181 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9182 match(If cmp icc);
9183 effect(USE labl);
9184
9185 size(8);
9186 ins_cost(BRANCH_COST);
9187 format %{ "BP$cmp $icc,$labl" %}
9188 // Prim = bits 24-22, Secnd = bits 31-30
9189 ins_encode( enc_bp( labl, cmp, icc ) );
9190 ins_pipe(br_cc);
9191 %}
9192
9193 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9194 match(If cmp icc);
9195 effect(USE labl);
9196
9197 ins_cost(BRANCH_COST);
9198 format %{ "BP$cmp $icc,$labl" %}
9199 // Prim = bits 24-22, Secnd = bits 31-30
9200 ins_encode( enc_bp( labl, cmp, icc ) );
9201 ins_pipe(br_cc);
9202 %}
9203
9204 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9205 match(If cmp pcc);
9206 effect(USE labl);
9207
9208 size(8);
9209 ins_cost(BRANCH_COST);
9210 format %{ "BP$cmp $pcc,$labl" %}
9211 ins_encode %{
9212 Label* L = $labl$$label;
9213 Assembler::Predict predict_taken =
9214 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9215
9216 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9217 __ delayed()->nop();
9218 %}
9219 ins_pipe(br_cc);
9220 %}
9221
9222 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9223 match(If cmp fcc);
9224 effect(USE labl);
9225
9226 size(8);
9227 ins_cost(BRANCH_COST);
9228 format %{ "FBP$cmp $fcc,$labl" %}
9229 ins_encode %{
9230 Label* L = $labl$$label;
9231 Assembler::Predict predict_taken =
9232 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9233
9234 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9235 __ delayed()->nop();
9236 %}
9237 ins_pipe(br_fcc);
9238 %}
9239
9240 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9241 match(CountedLoopEnd cmp icc);
9242 effect(USE labl);
9243
9244 size(8);
9245 ins_cost(BRANCH_COST);
9246 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9247 // Prim = bits 24-22, Secnd = bits 31-30
9248 ins_encode( enc_bp( labl, cmp, icc ) );
9249 ins_pipe(br_cc);
9250 %}
9251
9252 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9253 match(CountedLoopEnd cmp icc);
9254 effect(USE labl);
9255
9256 size(8);
9257 ins_cost(BRANCH_COST);
9258 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9259 // Prim = bits 24-22, Secnd = bits 31-30
9260 ins_encode( enc_bp( labl, cmp, icc ) );
9261 ins_pipe(br_cc);
9262 %}
9263
9264 // Compare and branch instructions
9265 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9266 match(If cmp (CmpI op1 op2));
9267 effect(USE labl, KILL icc);
9268
9269 size(12);
9270 ins_cost(BRANCH_COST);
9271 format %{ "CMP $op1,$op2\t! int\n\t"
9272 "BP$cmp $labl" %}
9273 ins_encode %{
9274 Label* L = $labl$$label;
9275 Assembler::Predict predict_taken =
9276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9277 __ cmp($op1$$Register, $op2$$Register);
9278 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9279 __ delayed()->nop();
9280 %}
9281 ins_pipe(cmp_br_reg_reg);
9282 %}
9283
9284 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9285 match(If cmp (CmpI op1 op2));
9286 effect(USE labl, KILL icc);
9287
9288 size(12);
9289 ins_cost(BRANCH_COST);
9290 format %{ "CMP $op1,$op2\t! int\n\t"
9291 "BP$cmp $labl" %}
9292 ins_encode %{
9293 Label* L = $labl$$label;
9294 Assembler::Predict predict_taken =
9295 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9296 __ cmp($op1$$Register, $op2$$constant);
9297 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9298 __ delayed()->nop();
9299 %}
9300 ins_pipe(cmp_br_reg_imm);
9301 %}
9302
9303 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9304 match(If cmp (CmpU op1 op2));
9305 effect(USE labl, KILL icc);
9306
9307 size(12);
9308 ins_cost(BRANCH_COST);
9309 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9310 "BP$cmp $labl" %}
9311 ins_encode %{
9312 Label* L = $labl$$label;
9313 Assembler::Predict predict_taken =
9314 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9315 __ cmp($op1$$Register, $op2$$Register);
9316 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9317 __ delayed()->nop();
9318 %}
9319 ins_pipe(cmp_br_reg_reg);
9320 %}
9321
9322 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9323 match(If cmp (CmpU op1 op2));
9324 effect(USE labl, KILL icc);
9325
9326 size(12);
9327 ins_cost(BRANCH_COST);
9328 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9329 "BP$cmp $labl" %}
9330 ins_encode %{
9331 Label* L = $labl$$label;
9332 Assembler::Predict predict_taken =
9333 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9334 __ cmp($op1$$Register, $op2$$constant);
9335 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9336 __ delayed()->nop();
9337 %}
9338 ins_pipe(cmp_br_reg_imm);
9339 %}
9340
9341 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9342 match(If cmp (CmpL op1 op2));
9343 effect(USE labl, KILL xcc);
9344
9345 size(12);
9346 ins_cost(BRANCH_COST);
9347 format %{ "CMP $op1,$op2\t! long\n\t"
9348 "BP$cmp $labl" %}
9349 ins_encode %{
9350 Label* L = $labl$$label;
9351 Assembler::Predict predict_taken =
9352 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9353 __ cmp($op1$$Register, $op2$$Register);
9354 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9355 __ delayed()->nop();
9356 %}
9357 ins_pipe(cmp_br_reg_reg);
9358 %}
9359
9360 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9361 match(If cmp (CmpL op1 op2));
9362 effect(USE labl, KILL xcc);
9363
9364 size(12);
9365 ins_cost(BRANCH_COST);
9366 format %{ "CMP $op1,$op2\t! long\n\t"
9367 "BP$cmp $labl" %}
9368 ins_encode %{
9369 Label* L = $labl$$label;
9370 Assembler::Predict predict_taken =
9371 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9372 __ cmp($op1$$Register, $op2$$constant);
9373 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9374 __ delayed()->nop();
9375 %}
9376 ins_pipe(cmp_br_reg_imm);
9377 %}
9378
9379 // Compare Pointers and branch
9380 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9381 match(If cmp (CmpP op1 op2));
9382 effect(USE labl, KILL pcc);
9383
9384 size(12);
9385 ins_cost(BRANCH_COST);
9386 format %{ "CMP $op1,$op2\t! ptr\n\t"
9387 "B$cmp $labl" %}
9388 ins_encode %{
9389 Label* L = $labl$$label;
9390 Assembler::Predict predict_taken =
9391 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9392 __ cmp($op1$$Register, $op2$$Register);
9393 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9394 __ delayed()->nop();
9395 %}
9396 ins_pipe(cmp_br_reg_reg);
9397 %}
9398
9399 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9400 match(If cmp (CmpP op1 null));
9401 effect(USE labl, KILL pcc);
9402
9403 size(12);
9404 ins_cost(BRANCH_COST);
9405 format %{ "CMP $op1,0\t! ptr\n\t"
9406 "B$cmp $labl" %}
9407 ins_encode %{
9408 Label* L = $labl$$label;
9409 Assembler::Predict predict_taken =
9410 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9411 __ cmp($op1$$Register, G0);
9412 // bpr() is not used here since it has shorter distance.
9413 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9414 __ delayed()->nop();
9415 %}
9416 ins_pipe(cmp_br_reg_reg);
9417 %}
9418
9419 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9420 match(If cmp (CmpN op1 op2));
9421 effect(USE labl, KILL icc);
9422
9423 size(12);
9424 ins_cost(BRANCH_COST);
9425 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9426 "BP$cmp $labl" %}
9427 ins_encode %{
9428 Label* L = $labl$$label;
9429 Assembler::Predict predict_taken =
9430 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9431 __ cmp($op1$$Register, $op2$$Register);
9432 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9433 __ delayed()->nop();
9434 %}
9435 ins_pipe(cmp_br_reg_reg);
9436 %}
9437
9438 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9439 match(If cmp (CmpN op1 null));
9440 effect(USE labl, KILL icc);
9441
9442 size(12);
9443 ins_cost(BRANCH_COST);
9444 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9445 "BP$cmp $labl" %}
9446 ins_encode %{
9447 Label* L = $labl$$label;
9448 Assembler::Predict predict_taken =
9449 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9450 __ cmp($op1$$Register, G0);
9451 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9452 __ delayed()->nop();
9453 %}
9454 ins_pipe(cmp_br_reg_reg);
9455 %}
9456
9457 // Loop back branch
9458 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9459 match(CountedLoopEnd cmp (CmpI op1 op2));
9460 effect(USE labl, KILL icc);
9461
9462 size(12);
9463 ins_cost(BRANCH_COST);
9464 format %{ "CMP $op1,$op2\t! int\n\t"
9465 "BP$cmp $labl\t! Loop end" %}
9466 ins_encode %{
9467 Label* L = $labl$$label;
9468 Assembler::Predict predict_taken =
9469 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9470 __ cmp($op1$$Register, $op2$$Register);
9471 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9472 __ delayed()->nop();
9473 %}
9474 ins_pipe(cmp_br_reg_reg);
9475 %}
9476
9477 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9478 match(CountedLoopEnd cmp (CmpI op1 op2));
9479 effect(USE labl, KILL icc);
9480
9481 size(12);
9482 ins_cost(BRANCH_COST);
9483 format %{ "CMP $op1,$op2\t! int\n\t"
9484 "BP$cmp $labl\t! Loop end" %}
9485 ins_encode %{
9486 Label* L = $labl$$label;
9487 Assembler::Predict predict_taken =
9488 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9489 __ cmp($op1$$Register, $op2$$constant);
9490 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9491 __ delayed()->nop();
9492 %}
9493 ins_pipe(cmp_br_reg_imm);
9494 %}
9495
9496 // Short compare and branch instructions
9497 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9498 match(If cmp (CmpI op1 op2));
9499 predicate(UseCBCond);
9500 effect(USE labl, KILL icc);
9501
9502 size(4);
9503 ins_cost(BRANCH_COST);
9504 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9505 ins_encode %{
9506 Label* L = $labl$$label;
9507 assert(__ use_cbcond(*L), "back to back cbcond");
9508 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9509 %}
9510 ins_short_branch(1);
9511 ins_avoid_back_to_back(1);
9512 ins_pipe(cbcond_reg_reg);
9513 %}
9514
9515 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9516 match(If cmp (CmpI op1 op2));
9517 predicate(UseCBCond);
9518 effect(USE labl, KILL icc);
9519
9520 size(4);
9521 ins_cost(BRANCH_COST);
9522 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9523 ins_encode %{
9524 Label* L = $labl$$label;
9525 assert(__ use_cbcond(*L), "back to back cbcond");
9526 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9527 %}
9528 ins_short_branch(1);
9529 ins_avoid_back_to_back(1);
9530 ins_pipe(cbcond_reg_imm);
9531 %}
9532
9533 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9534 match(If cmp (CmpU op1 op2));
9535 predicate(UseCBCond);
9536 effect(USE labl, KILL icc);
9537
9538 size(4);
9539 ins_cost(BRANCH_COST);
9540 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9541 ins_encode %{
9542 Label* L = $labl$$label;
9543 assert(__ use_cbcond(*L), "back to back cbcond");
9544 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9545 %}
9546 ins_short_branch(1);
9547 ins_avoid_back_to_back(1);
9548 ins_pipe(cbcond_reg_reg);
9549 %}
9550
9551 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9552 match(If cmp (CmpU op1 op2));
9553 predicate(UseCBCond);
9554 effect(USE labl, KILL icc);
9555
9556 size(4);
9557 ins_cost(BRANCH_COST);
9558 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9559 ins_encode %{
9560 Label* L = $labl$$label;
9561 assert(__ use_cbcond(*L), "back to back cbcond");
9562 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9563 %}
9564 ins_short_branch(1);
9565 ins_avoid_back_to_back(1);
9566 ins_pipe(cbcond_reg_imm);
9567 %}
9568
9569 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9570 match(If cmp (CmpL op1 op2));
9571 predicate(UseCBCond);
9572 effect(USE labl, KILL xcc);
9573
9574 size(4);
9575 ins_cost(BRANCH_COST);
9576 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9577 ins_encode %{
9578 Label* L = $labl$$label;
9579 assert(__ use_cbcond(*L), "back to back cbcond");
9580 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9581 %}
9582 ins_short_branch(1);
9583 ins_avoid_back_to_back(1);
9584 ins_pipe(cbcond_reg_reg);
9585 %}
9586
9587 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9588 match(If cmp (CmpL op1 op2));
9589 predicate(UseCBCond);
9590 effect(USE labl, KILL xcc);
9591
9592 size(4);
9593 ins_cost(BRANCH_COST);
9594 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9595 ins_encode %{
9596 Label* L = $labl$$label;
9597 assert(__ use_cbcond(*L), "back to back cbcond");
9598 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9599 %}
9600 ins_short_branch(1);
9601 ins_avoid_back_to_back(1);
9602 ins_pipe(cbcond_reg_imm);
9603 %}
9604
9605 // Compare Pointers and branch
9606 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9607 match(If cmp (CmpP op1 op2));
9608 predicate(UseCBCond);
9609 effect(USE labl, KILL pcc);
9610
9611 size(4);
9612 ins_cost(BRANCH_COST);
9613 #ifdef _LP64
9614 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9615 #else
9616 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9617 #endif
9618 ins_encode %{
9619 Label* L = $labl$$label;
9620 assert(__ use_cbcond(*L), "back to back cbcond");
9621 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9622 %}
9623 ins_short_branch(1);
9624 ins_avoid_back_to_back(1);
9625 ins_pipe(cbcond_reg_reg);
9626 %}
9627
9628 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9629 match(If cmp (CmpP op1 null));
9630 predicate(UseCBCond);
9631 effect(USE labl, KILL pcc);
9632
9633 size(4);
9634 ins_cost(BRANCH_COST);
9635 #ifdef _LP64
9636 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9637 #else
9638 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9639 #endif
9640 ins_encode %{
9641 Label* L = $labl$$label;
9642 assert(__ use_cbcond(*L), "back to back cbcond");
9643 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9644 %}
9645 ins_short_branch(1);
9646 ins_avoid_back_to_back(1);
9647 ins_pipe(cbcond_reg_reg);
9648 %}
9649
9650 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9651 match(If cmp (CmpN op1 op2));
9652 predicate(UseCBCond);
9653 effect(USE labl, KILL icc);
9654
9655 size(4);
9656 ins_cost(BRANCH_COST);
9657 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9658 ins_encode %{
9659 Label* L = $labl$$label;
9660 assert(__ use_cbcond(*L), "back to back cbcond");
9661 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9662 %}
9663 ins_short_branch(1);
9664 ins_avoid_back_to_back(1);
9665 ins_pipe(cbcond_reg_reg);
9666 %}
9667
9668 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9669 match(If cmp (CmpN op1 null));
9670 predicate(UseCBCond);
9671 effect(USE labl, KILL icc);
9672
9673 size(4);
9674 ins_cost(BRANCH_COST);
9675 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9676 ins_encode %{
9677 Label* L = $labl$$label;
9678 assert(__ use_cbcond(*L), "back to back cbcond");
9679 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9680 %}
9681 ins_short_branch(1);
9682 ins_avoid_back_to_back(1);
9683 ins_pipe(cbcond_reg_reg);
9684 %}
9685
9686 // Loop back branch
9687 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9688 match(CountedLoopEnd cmp (CmpI op1 op2));
9689 predicate(UseCBCond);
9690 effect(USE labl, KILL icc);
9691
9692 size(4);
9693 ins_cost(BRANCH_COST);
9694 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9695 ins_encode %{
9696 Label* L = $labl$$label;
9697 assert(__ use_cbcond(*L), "back to back cbcond");
9698 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9699 %}
9700 ins_short_branch(1);
9701 ins_avoid_back_to_back(1);
9702 ins_pipe(cbcond_reg_reg);
9703 %}
9704
9705 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9706 match(CountedLoopEnd cmp (CmpI op1 op2));
9707 predicate(UseCBCond);
9708 effect(USE labl, KILL icc);
9709
9710 size(4);
9711 ins_cost(BRANCH_COST);
9712 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9713 ins_encode %{
9714 Label* L = $labl$$label;
9715 assert(__ use_cbcond(*L), "back to back cbcond");
9716 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9717 %}
9718 ins_short_branch(1);
9719 ins_avoid_back_to_back(1);
9720 ins_pipe(cbcond_reg_imm);
9721 %}
9722
9723 // Branch-on-register tests all 64 bits. We assume that values
9724 // in 64-bit registers always remains zero or sign extended
9725 // unless our code munges the high bits. Interrupts can chop
9726 // the high order bits to zero or sign at any time.
9727 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9728 match(If cmp (CmpI op1 zero));
9729 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9730 effect(USE labl);
9731
9732 size(8);
9733 ins_cost(BRANCH_COST);
9734 format %{ "BR$cmp $op1,$labl" %}
9735 ins_encode( enc_bpr( labl, cmp, op1 ) );
9736 ins_pipe(br_reg);
9737 %}
9738
9739 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9740 match(If cmp (CmpP op1 null));
9741 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9742 effect(USE labl);
9743
9744 size(8);
9745 ins_cost(BRANCH_COST);
9746 format %{ "BR$cmp $op1,$labl" %}
9747 ins_encode( enc_bpr( labl, cmp, op1 ) );
9748 ins_pipe(br_reg);
9749 %}
9750
9751 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9752 match(If cmp (CmpL op1 zero));
9753 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9754 effect(USE labl);
9755
9756 size(8);
9757 ins_cost(BRANCH_COST);
9758 format %{ "BR$cmp $op1,$labl" %}
9759 ins_encode( enc_bpr( labl, cmp, op1 ) );
9760 ins_pipe(br_reg);
9761 %}
9762
9763
9764 // ============================================================================
9765 // Long Compare
9766 //
9767 // Currently we hold longs in 2 registers. Comparing such values efficiently
9768 // is tricky. The flavor of compare used depends on whether we are testing
9769 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9770 // The GE test is the negated LT test. The LE test can be had by commuting
9771 // the operands (yielding a GE test) and then negating; negate again for the
9772 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9773 // NE test is negated from that.
9774
9775 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9776 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9777 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9778 // are collapsed internally in the ADLC's dfa-gen code. The match for
9779 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9780 // foo match ends up with the wrong leaf. One fix is to not match both
9781 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9782 // both forms beat the trinary form of long-compare and both are very useful
9783 // on Intel which has so few registers.
9784
9785 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9786 match(If cmp xcc);
9787 effect(USE labl);
9788
9789 size(8);
9790 ins_cost(BRANCH_COST);
9791 format %{ "BP$cmp $xcc,$labl" %}
9792 ins_encode %{
9793 Label* L = $labl$$label;
9794 Assembler::Predict predict_taken =
9795 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9796
9797 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9798 __ delayed()->nop();
9799 %}
9800 ins_pipe(br_cc);
9801 %}
9802
9803 // Manifest a CmpL3 result in an integer register. Very painful.
9804 // This is the test to avoid.
9805 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9806 match(Set dst (CmpL3 src1 src2) );
9807 effect( KILL ccr );
9808 ins_cost(6*DEFAULT_COST);
9809 size(24);
9810 format %{ "CMP $src1,$src2\t\t! long\n"
9811 "\tBLT,a,pn done\n"
9812 "\tMOV -1,$dst\t! delay slot\n"
9813 "\tBGT,a,pn done\n"
9814 "\tMOV 1,$dst\t! delay slot\n"
9815 "\tCLR $dst\n"
9816 "done:" %}
9817 ins_encode( cmpl_flag(src1,src2,dst) );
9818 ins_pipe(cmpL_reg);
9819 %}
9820
9821 // Conditional move
9822 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9823 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9824 ins_cost(150);
9825 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9826 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9827 ins_pipe(ialu_reg);
9828 %}
9829
9830 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9831 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9832 ins_cost(140);
9833 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9834 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9835 ins_pipe(ialu_imm);
9836 %}
9837
9838 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9839 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9840 ins_cost(150);
9841 format %{ "MOV$cmp $xcc,$src,$dst" %}
9842 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9843 ins_pipe(ialu_reg);
9844 %}
9845
9846 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9847 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9848 ins_cost(140);
9849 format %{ "MOV$cmp $xcc,$src,$dst" %}
9850 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9851 ins_pipe(ialu_imm);
9852 %}
9853
9854 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9855 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9856 ins_cost(150);
9857 format %{ "MOV$cmp $xcc,$src,$dst" %}
9858 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9859 ins_pipe(ialu_reg);
9860 %}
9861
9862 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9863 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9864 ins_cost(150);
9865 format %{ "MOV$cmp $xcc,$src,$dst" %}
9866 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9867 ins_pipe(ialu_reg);
9868 %}
9869
9870 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9871 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9872 ins_cost(140);
9873 format %{ "MOV$cmp $xcc,$src,$dst" %}
9874 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9875 ins_pipe(ialu_imm);
9876 %}
9877
9878 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9879 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9880 ins_cost(150);
9881 opcode(0x101);
9882 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9883 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9884 ins_pipe(int_conditional_float_move);
9885 %}
9886
9887 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9888 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9889 ins_cost(150);
9890 opcode(0x102);
9891 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9892 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9893 ins_pipe(int_conditional_float_move);
9894 %}
9895
9896 // ============================================================================
9897 // Safepoint Instruction
9898 instruct safePoint_poll(iRegP poll) %{
9899 match(SafePoint poll);
9900 effect(USE poll);
9901
9902 size(4);
9903 #ifdef _LP64
9904 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9905 #else
9906 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9907 #endif
9908 ins_encode %{
9909 __ relocate(relocInfo::poll_type);
9910 __ ld_ptr($poll$$Register, 0, G0);
9911 %}
9912 ins_pipe(loadPollP);
9913 %}
9914
9915 // ============================================================================
9916 // Call Instructions
9917 // Call Java Static Instruction
9918 instruct CallStaticJavaDirect( method meth ) %{
9919 match(CallStaticJava);
9920 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9921 effect(USE meth);
9922
9923 size(8);
9924 ins_cost(CALL_COST);
9925 format %{ "CALL,static ; NOP ==> " %}
9926 ins_encode( Java_Static_Call( meth ), call_epilog );
9927 ins_pipe(simple_call);
9928 %}
9929
9930 // Call Java Static Instruction (method handle version)
9931 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9932 match(CallStaticJava);
9933 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9934 effect(USE meth, KILL l7_mh_SP_save);
9935
9936 size(16);
9937 ins_cost(CALL_COST);
9938 format %{ "CALL,static/MethodHandle" %}
9939 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9940 ins_pipe(simple_call);
9941 %}
9942
9943 // Call Java Dynamic Instruction
9944 instruct CallDynamicJavaDirect( method meth ) %{
9945 match(CallDynamicJava);
9946 effect(USE meth);
9947
9948 ins_cost(CALL_COST);
9949 format %{ "SET (empty),R_G5\n\t"
9950 "CALL,dynamic ; NOP ==> " %}
9951 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9952 ins_pipe(call);
9953 %}
9954
9955 // Call Runtime Instruction
9956 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9957 match(CallRuntime);
9958 effect(USE meth, KILL l7);
9959 ins_cost(CALL_COST);
9960 format %{ "CALL,runtime" %}
9961 ins_encode( Java_To_Runtime( meth ),
9962 call_epilog, adjust_long_from_native_call );
9963 ins_pipe(simple_call);
9964 %}
9965
9966 // Call runtime without safepoint - same as CallRuntime
9967 instruct CallLeafDirect(method meth, l7RegP l7) %{
9968 match(CallLeaf);
9969 effect(USE meth, KILL l7);
9970 ins_cost(CALL_COST);
9971 format %{ "CALL,runtime leaf" %}
9972 ins_encode( Java_To_Runtime( meth ),
9973 call_epilog,
9974 adjust_long_from_native_call );
9975 ins_pipe(simple_call);
9976 %}
9977
9978 // Call runtime without safepoint - same as CallLeaf
9979 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9980 match(CallLeafNoFP);
9981 effect(USE meth, KILL l7);
9982 ins_cost(CALL_COST);
9983 format %{ "CALL,runtime leaf nofp" %}
9984 ins_encode( Java_To_Runtime( meth ),
9985 call_epilog,
9986 adjust_long_from_native_call );
9987 ins_pipe(simple_call);
9988 %}
9989
9990 // Tail Call; Jump from runtime stub to Java code.
9991 // Also known as an 'interprocedural jump'.
9992 // Target of jump will eventually return to caller.
9993 // TailJump below removes the return address.
9994 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9995 match(TailCall jump_target method_oop );
9996
9997 ins_cost(CALL_COST);
9998 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9999 ins_encode(form_jmpl(jump_target));
10000 ins_pipe(tail_call);
10001 %}
10002
10003
10004 // Return Instruction
10005 instruct Ret() %{
10006 match(Return);
10007
10008 // The epilogue node did the ret already.
10009 size(0);
10010 format %{ "! return" %}
10011 ins_encode();
10012 ins_pipe(empty);
10013 %}
10014
10015
10016 // Tail Jump; remove the return address; jump to target.
10017 // TailCall above leaves the return address around.
10018 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10019 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10020 // "restore" before this instruction (in Epilogue), we need to materialize it
10021 // in %i0.
10022 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10023 match( TailJump jump_target ex_oop );
10024 ins_cost(CALL_COST);
10025 format %{ "! discard R_O7\n\t"
10026 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10027 ins_encode(form_jmpl_set_exception_pc(jump_target));
10028 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10029 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10030 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10031 ins_pipe(tail_call);
10032 %}
10033
10034 // Create exception oop: created by stack-crawling runtime code.
10035 // Created exception is now available to this handler, and is setup
10036 // just prior to jumping to this handler. No code emitted.
10037 instruct CreateException( o0RegP ex_oop )
10038 %{
10039 match(Set ex_oop (CreateEx));
10040 ins_cost(0);
10041
10042 size(0);
10043 // use the following format syntax
10044 format %{ "! exception oop is in R_O0; no code emitted" %}
10045 ins_encode();
10046 ins_pipe(empty);
10047 %}
10048
10049
10050 // Rethrow exception:
10051 // The exception oop will come in the first argument position.
10052 // Then JUMP (not call) to the rethrow stub code.
10053 instruct RethrowException()
10054 %{
10055 match(Rethrow);
10056 ins_cost(CALL_COST);
10057
10058 // use the following format syntax
10059 format %{ "Jmp rethrow_stub" %}
10060 ins_encode(enc_rethrow);
10061 ins_pipe(tail_call);
10062 %}
10063
10064
10065 // Die now
10066 instruct ShouldNotReachHere( )
10067 %{
10068 match(Halt);
10069 ins_cost(CALL_COST);
10070
10071 size(4);
10072 // Use the following format syntax
10073 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10074 ins_encode( form2_illtrap() );
10075 ins_pipe(tail_call);
10076 %}
10077
10078 // ============================================================================
10079 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10080 // array for an instance of the superklass. Set a hidden internal cache on a
10081 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10082 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10083 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10084 match(Set index (PartialSubtypeCheck sub super));
10085 effect( KILL pcc, KILL o7 );
10086 ins_cost(DEFAULT_COST*10);
10087 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10088 ins_encode( enc_PartialSubtypeCheck() );
10089 ins_pipe(partial_subtype_check_pipe);
10090 %}
10091
10092 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10093 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10094 effect( KILL idx, KILL o7 );
10095 ins_cost(DEFAULT_COST*10);
10096 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10097 ins_encode( enc_PartialSubtypeCheck() );
10098 ins_pipe(partial_subtype_check_pipe);
10099 %}
10100
10101
10102 // ============================================================================
10103 // inlined locking and unlocking
10104
10105 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10106 match(Set pcc (FastLock object box));
10107
10108 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10109 ins_cost(100);
10110
10111 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10112 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10113 ins_pipe(long_memory_op);
10114 %}
10115
10116
10117 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10118 match(Set pcc (FastUnlock object box));
10119 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10120 ins_cost(100);
10121
10122 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10123 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10124 ins_pipe(long_memory_op);
10125 %}
10126
10127 // The encodings are generic.
10128 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10129 predicate(!use_block_zeroing(n->in(2)) );
10130 match(Set dummy (ClearArray cnt base));
10131 effect(TEMP temp, KILL ccr);
10132 ins_cost(300);
10133 format %{ "MOV $cnt,$temp\n"
10134 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10135 " BRge loop\t\t! Clearing loop\n"
10136 " STX G0,[$base+$temp]\t! delay slot" %}
10137
10138 ins_encode %{
10139 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10140 Register nof_bytes_arg = $cnt$$Register;
10141 Register nof_bytes_tmp = $temp$$Register;
10142 Register base_pointer_arg = $base$$Register;
10143
10144 Label loop;
10145 __ mov(nof_bytes_arg, nof_bytes_tmp);
10146
10147 // Loop and clear, walking backwards through the array.
10148 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10149 __ bind(loop);
10150 __ deccc(nof_bytes_tmp, 8);
10151 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10152 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10153 // %%%% this mini-loop must not cross a cache boundary!
10154 %}
10155 ins_pipe(long_memory_op);
10156 %}
10157
10158 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10159 predicate(use_block_zeroing(n->in(2)));
10160 match(Set dummy (ClearArray cnt base));
10161 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10162 ins_cost(300);
10163 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10164
10165 ins_encode %{
10166
10167 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10168 Register to = $base$$Register;
10169 Register count = $cnt$$Register;
10170
10171 Label Ldone;
10172 __ nop(); // Separate short branches
10173 // Use BIS for zeroing (temp is not used).
10174 __ bis_zeroing(to, count, G0, Ldone);
10175 __ bind(Ldone);
10176
10177 %}
10178 ins_pipe(long_memory_op);
10179 %}
10180
10181 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10182 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10183 match(Set dummy (ClearArray cnt base));
10184 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10185 ins_cost(300);
10186 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10187
10188 ins_encode %{
10189
10190 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10191 Register to = $base$$Register;
10192 Register count = $cnt$$Register;
10193 Register temp = $tmp$$Register;
10194
10195 Label Ldone;
10196 __ nop(); // Separate short branches
10197 // Use BIS for zeroing
10198 __ bis_zeroing(to, count, temp, Ldone);
10199 __ bind(Ldone);
10200
10201 %}
10202 ins_pipe(long_memory_op);
10203 %}
10204
10205 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10206 o7RegI tmp, flagsReg ccr) %{
10207 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10208 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10209 ins_cost(300);
10210 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10211 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10212 ins_pipe(long_memory_op);
10213 %}
10214
10215 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10216 o7RegI tmp, flagsReg ccr) %{
10217 match(Set result (StrEquals (Binary str1 str2) cnt));
10218 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10219 ins_cost(300);
10220 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10221 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10222 ins_pipe(long_memory_op);
10223 %}
10224
10225 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10226 o7RegI tmp2, flagsReg ccr) %{
10227 match(Set result (AryEq ary1 ary2));
10228 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10229 ins_cost(300);
10230 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10231 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10232 ins_pipe(long_memory_op);
10233 %}
10234
10235
10236 //---------- Zeros Count Instructions ------------------------------------------
10237
10238 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10239 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10240 match(Set dst (CountLeadingZerosI src));
10241 effect(TEMP dst, TEMP tmp, KILL cr);
10242
10243 // x |= (x >> 1);
10244 // x |= (x >> 2);
10245 // x |= (x >> 4);
10246 // x |= (x >> 8);
10247 // x |= (x >> 16);
10248 // return (WORDBITS - popc(x));
10249 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10250 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10251 "OR $dst,$tmp,$dst\n\t"
10252 "SRL $dst,2,$tmp\n\t"
10253 "OR $dst,$tmp,$dst\n\t"
10254 "SRL $dst,4,$tmp\n\t"
10255 "OR $dst,$tmp,$dst\n\t"
10256 "SRL $dst,8,$tmp\n\t"
10257 "OR $dst,$tmp,$dst\n\t"
10258 "SRL $dst,16,$tmp\n\t"
10259 "OR $dst,$tmp,$dst\n\t"
10260 "POPC $dst,$dst\n\t"
10261 "MOV 32,$tmp\n\t"
10262 "SUB $tmp,$dst,$dst" %}
10263 ins_encode %{
10264 Register Rdst = $dst$$Register;
10265 Register Rsrc = $src$$Register;
10266 Register Rtmp = $tmp$$Register;
10267 __ srl(Rsrc, 1, Rtmp);
10268 __ srl(Rsrc, 0, Rdst);
10269 __ or3(Rdst, Rtmp, Rdst);
10270 __ srl(Rdst, 2, Rtmp);
10271 __ or3(Rdst, Rtmp, Rdst);
10272 __ srl(Rdst, 4, Rtmp);
10273 __ or3(Rdst, Rtmp, Rdst);
10274 __ srl(Rdst, 8, Rtmp);
10275 __ or3(Rdst, Rtmp, Rdst);
10276 __ srl(Rdst, 16, Rtmp);
10277 __ or3(Rdst, Rtmp, Rdst);
10278 __ popc(Rdst, Rdst);
10279 __ mov(BitsPerInt, Rtmp);
10280 __ sub(Rtmp, Rdst, Rdst);
10281 %}
10282 ins_pipe(ialu_reg);
10283 %}
10284
10285 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10286 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10287 match(Set dst (CountLeadingZerosL src));
10288 effect(TEMP dst, TEMP tmp, KILL cr);
10289
10290 // x |= (x >> 1);
10291 // x |= (x >> 2);
10292 // x |= (x >> 4);
10293 // x |= (x >> 8);
10294 // x |= (x >> 16);
10295 // x |= (x >> 32);
10296 // return (WORDBITS - popc(x));
10297 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10298 "OR $src,$tmp,$dst\n\t"
10299 "SRLX $dst,2,$tmp\n\t"
10300 "OR $dst,$tmp,$dst\n\t"
10301 "SRLX $dst,4,$tmp\n\t"
10302 "OR $dst,$tmp,$dst\n\t"
10303 "SRLX $dst,8,$tmp\n\t"
10304 "OR $dst,$tmp,$dst\n\t"
10305 "SRLX $dst,16,$tmp\n\t"
10306 "OR $dst,$tmp,$dst\n\t"
10307 "SRLX $dst,32,$tmp\n\t"
10308 "OR $dst,$tmp,$dst\n\t"
10309 "POPC $dst,$dst\n\t"
10310 "MOV 64,$tmp\n\t"
10311 "SUB $tmp,$dst,$dst" %}
10312 ins_encode %{
10313 Register Rdst = $dst$$Register;
10314 Register Rsrc = $src$$Register;
10315 Register Rtmp = $tmp$$Register;
10316 __ srlx(Rsrc, 1, Rtmp);
10317 __ or3( Rsrc, Rtmp, Rdst);
10318 __ srlx(Rdst, 2, Rtmp);
10319 __ or3( Rdst, Rtmp, Rdst);
10320 __ srlx(Rdst, 4, Rtmp);
10321 __ or3( Rdst, Rtmp, Rdst);
10322 __ srlx(Rdst, 8, Rtmp);
10323 __ or3( Rdst, Rtmp, Rdst);
10324 __ srlx(Rdst, 16, Rtmp);
10325 __ or3( Rdst, Rtmp, Rdst);
10326 __ srlx(Rdst, 32, Rtmp);
10327 __ or3( Rdst, Rtmp, Rdst);
10328 __ popc(Rdst, Rdst);
10329 __ mov(BitsPerLong, Rtmp);
10330 __ sub(Rtmp, Rdst, Rdst);
10331 %}
10332 ins_pipe(ialu_reg);
10333 %}
10334
10335 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10336 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10337 match(Set dst (CountTrailingZerosI src));
10338 effect(TEMP dst, KILL cr);
10339
10340 // return popc(~x & (x - 1));
10341 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10342 "ANDN $dst,$src,$dst\n\t"
10343 "SRL $dst,R_G0,$dst\n\t"
10344 "POPC $dst,$dst" %}
10345 ins_encode %{
10346 Register Rdst = $dst$$Register;
10347 Register Rsrc = $src$$Register;
10348 __ sub(Rsrc, 1, Rdst);
10349 __ andn(Rdst, Rsrc, Rdst);
10350 __ srl(Rdst, G0, Rdst);
10351 __ popc(Rdst, Rdst);
10352 %}
10353 ins_pipe(ialu_reg);
10354 %}
10355
10356 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10357 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10358 match(Set dst (CountTrailingZerosL src));
10359 effect(TEMP dst, KILL cr);
10360
10361 // return popc(~x & (x - 1));
10362 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10363 "ANDN $dst,$src,$dst\n\t"
10364 "POPC $dst,$dst" %}
10365 ins_encode %{
10366 Register Rdst = $dst$$Register;
10367 Register Rsrc = $src$$Register;
10368 __ sub(Rsrc, 1, Rdst);
10369 __ andn(Rdst, Rsrc, Rdst);
10370 __ popc(Rdst, Rdst);
10371 %}
10372 ins_pipe(ialu_reg);
10373 %}
10374
10375
10376 //---------- Population Count Instructions -------------------------------------
10377
10378 instruct popCountI(iRegIsafe dst, iRegI src) %{
10379 predicate(UsePopCountInstruction);
10380 match(Set dst (PopCountI src));
10381
10382 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10383 "POPC $dst, $dst" %}
10384 ins_encode %{
10385 __ srl($src$$Register, G0, $dst$$Register);
10386 __ popc($dst$$Register, $dst$$Register);
10387 %}
10388 ins_pipe(ialu_reg);
10389 %}
10390
10391 // Note: Long.bitCount(long) returns an int.
10392 instruct popCountL(iRegIsafe dst, iRegL src) %{
10393 predicate(UsePopCountInstruction);
10394 match(Set dst (PopCountL src));
10395
10396 format %{ "POPC $src, $dst" %}
10397 ins_encode %{
10398 __ popc($src$$Register, $dst$$Register);
10399 %}
10400 ins_pipe(ialu_reg);
10401 %}
10402
10403
10404 // ============================================================================
10405 //------------Bytes reverse--------------------------------------------------
10406
10407 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10408 match(Set dst (ReverseBytesI src));
10409
10410 // Op cost is artificially doubled to make sure that load or store
10411 // instructions are preferred over this one which requires a spill
10412 // onto a stack slot.
10413 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10414 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10415
10416 ins_encode %{
10417 __ set($src$$disp + STACK_BIAS, O7);
10418 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10419 %}
10420 ins_pipe( iload_mem );
10421 %}
10422
10423 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10424 match(Set dst (ReverseBytesL src));
10425
10426 // Op cost is artificially doubled to make sure that load or store
10427 // instructions are preferred over this one which requires a spill
10428 // onto a stack slot.
10429 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10430 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10431
10432 ins_encode %{
10433 __ set($src$$disp + STACK_BIAS, O7);
10434 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10435 %}
10436 ins_pipe( iload_mem );
10437 %}
10438
10439 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10440 match(Set dst (ReverseBytesUS src));
10441
10442 // Op cost is artificially doubled to make sure that load or store
10443 // instructions are preferred over this one which requires a spill
10444 // onto a stack slot.
10445 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10446 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10447
10448 ins_encode %{
10449 // the value was spilled as an int so bias the load
10450 __ set($src$$disp + STACK_BIAS + 2, O7);
10451 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10452 %}
10453 ins_pipe( iload_mem );
10454 %}
10455
10456 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10457 match(Set dst (ReverseBytesS src));
10458
10459 // Op cost is artificially doubled to make sure that load or store
10460 // instructions are preferred over this one which requires a spill
10461 // onto a stack slot.
10462 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10463 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10464
10465 ins_encode %{
10466 // the value was spilled as an int so bias the load
10467 __ set($src$$disp + STACK_BIAS + 2, O7);
10468 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10469 %}
10470 ins_pipe( iload_mem );
10471 %}
10472
10473 // Load Integer reversed byte order
10474 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10475 match(Set dst (ReverseBytesI (LoadI src)));
10476
10477 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10478 size(4);
10479 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10480
10481 ins_encode %{
10482 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10483 %}
10484 ins_pipe(iload_mem);
10485 %}
10486
10487 // Load Long - aligned and reversed
10488 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10489 match(Set dst (ReverseBytesL (LoadL src)));
10490
10491 ins_cost(MEMORY_REF_COST);
10492 size(4);
10493 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10494
10495 ins_encode %{
10496 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10497 %}
10498 ins_pipe(iload_mem);
10499 %}
10500
10501 // Load unsigned short / char reversed byte order
10502 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10503 match(Set dst (ReverseBytesUS (LoadUS src)));
10504
10505 ins_cost(MEMORY_REF_COST);
10506 size(4);
10507 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10508
10509 ins_encode %{
10510 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10511 %}
10512 ins_pipe(iload_mem);
10513 %}
10514
10515 // Load short reversed byte order
10516 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10517 match(Set dst (ReverseBytesS (LoadS src)));
10518
10519 ins_cost(MEMORY_REF_COST);
10520 size(4);
10521 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10522
10523 ins_encode %{
10524 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10525 %}
10526 ins_pipe(iload_mem);
10527 %}
10528
10529 // Store Integer reversed byte order
10530 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10531 match(Set dst (StoreI dst (ReverseBytesI src)));
10532
10533 ins_cost(MEMORY_REF_COST);
10534 size(4);
10535 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10536
10537 ins_encode %{
10538 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10539 %}
10540 ins_pipe(istore_mem_reg);
10541 %}
10542
10543 // Store Long reversed byte order
10544 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10545 match(Set dst (StoreL dst (ReverseBytesL src)));
10546
10547 ins_cost(MEMORY_REF_COST);
10548 size(4);
10549 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10550
10551 ins_encode %{
10552 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10553 %}
10554 ins_pipe(istore_mem_reg);
10555 %}
10556
10557 // Store unsighed short/char reversed byte order
10558 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10559 match(Set dst (StoreC dst (ReverseBytesUS src)));
10560
10561 ins_cost(MEMORY_REF_COST);
10562 size(4);
10563 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10564
10565 ins_encode %{
10566 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10567 %}
10568 ins_pipe(istore_mem_reg);
10569 %}
10570
10571 // Store short reversed byte order
10572 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10573 match(Set dst (StoreC dst (ReverseBytesS src)));
10574
10575 ins_cost(MEMORY_REF_COST);
10576 size(4);
10577 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10578
10579 ins_encode %{
10580 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10581 %}
10582 ins_pipe(istore_mem_reg);
10583 %}
10584
10585 // ====================VECTOR INSTRUCTIONS=====================================
10586
10587 // Load Aligned Packed values into a Double Register
10588 instruct loadV8(regD dst, memory mem) %{
10589 predicate(n->as_LoadVector()->memory_size() == 8);
10590 match(Set dst (LoadVector mem));
10591 ins_cost(MEMORY_REF_COST);
10592 size(4);
10593 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10594 ins_encode %{
10595 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10596 %}
10597 ins_pipe(floadD_mem);
10598 %}
10599
10600 // Store Vector in Double register to memory
10601 instruct storeV8(memory mem, regD src) %{
10602 predicate(n->as_StoreVector()->memory_size() == 8);
10603 match(Set mem (StoreVector mem src));
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10607 ins_encode %{
10608 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10609 %}
10610 ins_pipe(fstoreD_mem_reg);
10611 %}
10612
10613 // Store Zero into vector in memory
10614 instruct storeV8B_zero(memory mem, immI0 zero) %{
10615 predicate(n->as_StoreVector()->memory_size() == 8);
10616 match(Set mem (StoreVector mem (ReplicateB zero)));
10617 ins_cost(MEMORY_REF_COST);
10618 size(4);
10619 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10620 ins_encode %{
10621 __ stx(G0, $mem$$Address);
10622 %}
10623 ins_pipe(fstoreD_mem_zero);
10624 %}
10625
10626 instruct storeV4S_zero(memory mem, immI0 zero) %{
10627 predicate(n->as_StoreVector()->memory_size() == 8);
10628 match(Set mem (StoreVector mem (ReplicateS zero)));
10629 ins_cost(MEMORY_REF_COST);
10630 size(4);
10631 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10632 ins_encode %{
10633 __ stx(G0, $mem$$Address);
10634 %}
10635 ins_pipe(fstoreD_mem_zero);
10636 %}
10637
10638 instruct storeV2I_zero(memory mem, immI0 zero) %{
10639 predicate(n->as_StoreVector()->memory_size() == 8);
10640 match(Set mem (StoreVector mem (ReplicateI zero)));
10641 ins_cost(MEMORY_REF_COST);
10642 size(4);
10643 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10644 ins_encode %{
10645 __ stx(G0, $mem$$Address);
10646 %}
10647 ins_pipe(fstoreD_mem_zero);
10648 %}
10649
10650 instruct storeV2F_zero(memory mem, immF0 zero) %{
10651 predicate(n->as_StoreVector()->memory_size() == 8);
10652 match(Set mem (StoreVector mem (ReplicateF zero)));
10653 ins_cost(MEMORY_REF_COST);
10654 size(4);
10655 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10656 ins_encode %{
10657 __ stx(G0, $mem$$Address);
10658 %}
10659 ins_pipe(fstoreD_mem_zero);
10660 %}
10661
10662 // Replicate scalar to packed byte values into Double register
10663 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10664 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10665 match(Set dst (ReplicateB src));
10666 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10667 format %{ "SLLX $src,56,$tmp\n\t"
10668 "SRLX $tmp, 8,$tmp2\n\t"
10669 "OR $tmp,$tmp2,$tmp\n\t"
10670 "SRLX $tmp,16,$tmp2\n\t"
10671 "OR $tmp,$tmp2,$tmp\n\t"
10672 "SRLX $tmp,32,$tmp2\n\t"
10673 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10674 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10675 ins_encode %{
10676 Register Rsrc = $src$$Register;
10677 Register Rtmp = $tmp$$Register;
10678 Register Rtmp2 = $tmp2$$Register;
10679 __ sllx(Rsrc, 56, Rtmp);
10680 __ srlx(Rtmp, 8, Rtmp2);
10681 __ or3 (Rtmp, Rtmp2, Rtmp);
10682 __ srlx(Rtmp, 16, Rtmp2);
10683 __ or3 (Rtmp, Rtmp2, Rtmp);
10684 __ srlx(Rtmp, 32, Rtmp2);
10685 __ or3 (Rtmp, Rtmp2, Rtmp);
10686 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10687 %}
10688 ins_pipe(ialu_reg);
10689 %}
10690
10691 // Replicate scalar to packed byte values into Double stack
10692 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10693 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10694 match(Set dst (ReplicateB src));
10695 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10696 format %{ "SLLX $src,56,$tmp\n\t"
10697 "SRLX $tmp, 8,$tmp2\n\t"
10698 "OR $tmp,$tmp2,$tmp\n\t"
10699 "SRLX $tmp,16,$tmp2\n\t"
10700 "OR $tmp,$tmp2,$tmp\n\t"
10701 "SRLX $tmp,32,$tmp2\n\t"
10702 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10703 "STX $tmp,$dst\t! regL to stkD" %}
10704 ins_encode %{
10705 Register Rsrc = $src$$Register;
10706 Register Rtmp = $tmp$$Register;
10707 Register Rtmp2 = $tmp2$$Register;
10708 __ sllx(Rsrc, 56, Rtmp);
10709 __ srlx(Rtmp, 8, Rtmp2);
10710 __ or3 (Rtmp, Rtmp2, Rtmp);
10711 __ srlx(Rtmp, 16, Rtmp2);
10712 __ or3 (Rtmp, Rtmp2, Rtmp);
10713 __ srlx(Rtmp, 32, Rtmp2);
10714 __ or3 (Rtmp, Rtmp2, Rtmp);
10715 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10716 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10717 %}
10718 ins_pipe(ialu_reg);
10719 %}
10720
10721 // Replicate scalar constant to packed byte values in Double register
10722 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10723 predicate(n->as_Vector()->length() == 8);
10724 match(Set dst (ReplicateB con));
10725 effect(KILL tmp);
10726 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10727 ins_encode %{
10728 // XXX This is a quick fix for 6833573.
10729 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10730 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10731 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10732 %}
10733 ins_pipe(loadConFD);
10734 %}
10735
10736 // Replicate scalar to packed char/short values into Double register
10737 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10738 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10739 match(Set dst (ReplicateS src));
10740 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10741 format %{ "SLLX $src,48,$tmp\n\t"
10742 "SRLX $tmp,16,$tmp2\n\t"
10743 "OR $tmp,$tmp2,$tmp\n\t"
10744 "SRLX $tmp,32,$tmp2\n\t"
10745 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10746 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10747 ins_encode %{
10748 Register Rsrc = $src$$Register;
10749 Register Rtmp = $tmp$$Register;
10750 Register Rtmp2 = $tmp2$$Register;
10751 __ sllx(Rsrc, 48, Rtmp);
10752 __ srlx(Rtmp, 16, Rtmp2);
10753 __ or3 (Rtmp, Rtmp2, Rtmp);
10754 __ srlx(Rtmp, 32, Rtmp2);
10755 __ or3 (Rtmp, Rtmp2, Rtmp);
10756 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10757 %}
10758 ins_pipe(ialu_reg);
10759 %}
10760
10761 // Replicate scalar to packed char/short values into Double stack
10762 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10763 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10764 match(Set dst (ReplicateS src));
10765 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10766 format %{ "SLLX $src,48,$tmp\n\t"
10767 "SRLX $tmp,16,$tmp2\n\t"
10768 "OR $tmp,$tmp2,$tmp\n\t"
10769 "SRLX $tmp,32,$tmp2\n\t"
10770 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10771 "STX $tmp,$dst\t! regL to stkD" %}
10772 ins_encode %{
10773 Register Rsrc = $src$$Register;
10774 Register Rtmp = $tmp$$Register;
10775 Register Rtmp2 = $tmp2$$Register;
10776 __ sllx(Rsrc, 48, Rtmp);
10777 __ srlx(Rtmp, 16, Rtmp2);
10778 __ or3 (Rtmp, Rtmp2, Rtmp);
10779 __ srlx(Rtmp, 32, Rtmp2);
10780 __ or3 (Rtmp, Rtmp2, Rtmp);
10781 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10782 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10783 %}
10784 ins_pipe(ialu_reg);
10785 %}
10786
10787 // Replicate scalar constant to packed char/short values in Double register
10788 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10789 predicate(n->as_Vector()->length() == 4);
10790 match(Set dst (ReplicateS con));
10791 effect(KILL tmp);
10792 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10793 ins_encode %{
10794 // XXX This is a quick fix for 6833573.
10795 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10796 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10797 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10798 %}
10799 ins_pipe(loadConFD);
10800 %}
10801
10802 // Replicate scalar to packed int values into Double register
10803 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10804 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10805 match(Set dst (ReplicateI src));
10806 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10807 format %{ "SLLX $src,32,$tmp\n\t"
10808 "SRLX $tmp,32,$tmp2\n\t"
10809 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10810 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10811 ins_encode %{
10812 Register Rsrc = $src$$Register;
10813 Register Rtmp = $tmp$$Register;
10814 Register Rtmp2 = $tmp2$$Register;
10815 __ sllx(Rsrc, 32, Rtmp);
10816 __ srlx(Rtmp, 32, Rtmp2);
10817 __ or3 (Rtmp, Rtmp2, Rtmp);
10818 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10819 %}
10820 ins_pipe(ialu_reg);
10821 %}
10822
10823 // Replicate scalar to packed int values into Double stack
10824 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10825 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10826 match(Set dst (ReplicateI src));
10827 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10828 format %{ "SLLX $src,32,$tmp\n\t"
10829 "SRLX $tmp,32,$tmp2\n\t"
10830 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10831 "STX $tmp,$dst\t! regL to stkD" %}
10832 ins_encode %{
10833 Register Rsrc = $src$$Register;
10834 Register Rtmp = $tmp$$Register;
10835 Register Rtmp2 = $tmp2$$Register;
10836 __ sllx(Rsrc, 32, Rtmp);
10837 __ srlx(Rtmp, 32, Rtmp2);
10838 __ or3 (Rtmp, Rtmp2, Rtmp);
10839 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10840 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10841 %}
10842 ins_pipe(ialu_reg);
10843 %}
10844
10845 // Replicate scalar zero constant to packed int values in Double register
10846 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10847 predicate(n->as_Vector()->length() == 2);
10848 match(Set dst (ReplicateI con));
10849 effect(KILL tmp);
10850 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10851 ins_encode %{
10852 // XXX This is a quick fix for 6833573.
10853 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10854 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10855 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10856 %}
10857 ins_pipe(loadConFD);
10858 %}
10859
10860 // Replicate scalar to packed float values into Double stack
10861 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10862 predicate(n->as_Vector()->length() == 2);
10863 match(Set dst (ReplicateF src));
10864 ins_cost(MEMORY_REF_COST*2);
10865 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10866 "STF $src,$dst.lo" %}
10867 opcode(Assembler::stf_op3);
10868 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10869 ins_pipe(fstoreF_stk_reg);
10870 %}
10871
10872 // Replicate scalar zero constant to packed float values in Double register
10873 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10874 predicate(n->as_Vector()->length() == 2);
10875 match(Set dst (ReplicateF con));
10876 effect(KILL tmp);
10877 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10878 ins_encode %{
10879 // XXX This is a quick fix for 6833573.
10880 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10881 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10882 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10883 %}
10884 ins_pipe(loadConFD);
10885 %}
10886
10887 //----------PEEPHOLE RULES-----------------------------------------------------
10888 // These must follow all instruction definitions as they use the names
10889 // defined in the instructions definitions.
10890 //
10891 // peepmatch ( root_instr_name [preceding_instruction]* );
10892 //
10893 // peepconstraint %{
10894 // (instruction_number.operand_name relational_op instruction_number.operand_name
10895 // [, ...] );
10896 // // instruction numbers are zero-based using left to right order in peepmatch
10897 //
10898 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10899 // // provide an instruction_number.operand_name for each operand that appears
10900 // // in the replacement instruction's match rule
10901 //
10902 // ---------VM FLAGS---------------------------------------------------------
10903 //
10904 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10905 //
10906 // Each peephole rule is given an identifying number starting with zero and
10907 // increasing by one in the order seen by the parser. An individual peephole
10908 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10909 // on the command-line.
10910 //
10911 // ---------CURRENT LIMITATIONS----------------------------------------------
10912 //
10913 // Only match adjacent instructions in same basic block
10914 // Only equality constraints
10915 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10916 // Only one replacement instruction
10917 //
10918 // ---------EXAMPLE----------------------------------------------------------
10919 //
10920 // // pertinent parts of existing instructions in architecture description
10921 // instruct movI(eRegI dst, eRegI src) %{
10922 // match(Set dst (CopyI src));
10923 // %}
10924 //
10925 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10926 // match(Set dst (AddI dst src));
10927 // effect(KILL cr);
10928 // %}
10929 //
10930 // // Change (inc mov) to lea
10931 // peephole %{
10932 // // increment preceeded by register-register move
10933 // peepmatch ( incI_eReg movI );
10934 // // require that the destination register of the increment
10935 // // match the destination register of the move
10936 // peepconstraint ( 0.dst == 1.dst );
10937 // // construct a replacement instruction that sets
10938 // // the destination to ( move's source register + one )
10939 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10940 // %}
10941 //
10942
10943 // // Change load of spilled value to only a spill
10944 // instruct storeI(memory mem, eRegI src) %{
10945 // match(Set mem (StoreI mem src));
10946 // %}
10947 //
10948 // instruct loadI(eRegI dst, memory mem) %{
10949 // match(Set dst (LoadI mem));
10950 // %}
10951 //
10952 // peephole %{
10953 // peepmatch ( loadI storeI );
10954 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10955 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10956 // %}
10957
10958 //----------SMARTSPILL RULES---------------------------------------------------
10959 // These must follow all instruction definitions as they use the names
10960 // defined in the instructions definitions.
10961 //
10962 // SPARC will probably not have any of these rules due to RISC instruction set.
10963
10964 //----------PIPELINE-----------------------------------------------------------
10965 // Rules which define the behavior of the target architectures pipeline.