1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding
492 }
493
494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
495 return 0;
496 }
497
498 #ifndef PRODUCT
499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
500 st->print("# MachConstantBaseNode (empty encoding)");
501 }
502 #endif
503
504
505 //=============================================================================
506 #ifndef PRODUCT
507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
508 Compile* C = ra_->C;
509
510 int framesize = C->frame_slots() << LogBytesPerInt;
511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
512 // Remove wordSize for return addr which is already pushed.
513 framesize -= wordSize;
514
515 if (C->need_stack_bang(framesize)) {
516 framesize -= wordSize;
517 st->print("# stack bang");
518 st->print("\n\t");
519 st->print("PUSH EBP\t# Save EBP");
520 if (framesize) {
521 st->print("\n\t");
522 st->print("SUB ESP, #%d\t# Create frame",framesize);
523 }
524 } else {
525 st->print("SUB ESP, #%d\t# Create frame",framesize);
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
529 }
530
531 if (VerifyStackAtCalls) {
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
535 }
536
537 if( C->in_24_bit_fp_mode() ) {
538 st->print("\n\t");
539 st->print("FLDCW \t# load 24 bit fpu control word");
540 }
541 if (UseSSE >= 2 && VerifyFPU) {
542 st->print("\n\t");
543 st->print("# verify FPU stack (must be clean on entry)");
544 }
545
546 #ifdef ASSERT
547 if (VerifyStackAtCalls) {
548 st->print("\n\t");
549 st->print("# stack alignment check");
550 }
551 #endif
552 st->cr();
553 }
554 #endif
555
556
557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
558 Compile* C = ra_->C;
559 MacroAssembler _masm(&cbuf);
560
561 int framesize = C->frame_slots() << LogBytesPerInt;
562
563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
564
565 C->set_frame_complete(cbuf.insts_size());
566
567 if (C->has_mach_constant_base_node()) {
568 // NOTE: We set the table base offset here because users might be
569 // emitted before MachConstantBaseNode.
570 Compile::ConstantTable& constant_table = C->constant_table();
571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
572 }
573 }
574
575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
576 return MachNode::size(ra_); // too many variables; just compute it the hard way
577 }
578
579 int MachPrologNode::reloc() const {
580 return 0; // a large enough number
581 }
582
583 //=============================================================================
584 #ifndef PRODUCT
585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
586 Compile *C = ra_->C;
587 int framesize = C->frame_slots() << LogBytesPerInt;
588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
589 // Remove two words for return addr and rbp,
590 framesize -= 2*wordSize;
591
592 if (C->max_vector_size() > 16) {
593 st->print("VZEROUPPER");
594 st->cr(); st->print("\t");
595 }
596 if (C->in_24_bit_fp_mode()) {
597 st->print("FLDCW standard control word");
598 st->cr(); st->print("\t");
599 }
600 if (framesize) {
601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
602 st->cr(); st->print("\t");
603 }
604 st->print_cr("POPL EBP"); st->print("\t");
605 if (do_polling() && C->is_method_compilation()) {
606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
607 st->cr(); st->print("\t");
608 }
609 }
610 #endif
611
612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
613 Compile *C = ra_->C;
614
615 if (C->max_vector_size() > 16) {
616 // Clear upper bits of YMM registers when current compiled code uses
617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
618 MacroAssembler masm(&cbuf);
619 masm.vzeroupper();
620 }
621 // If method set FPU control word, restore to standard control word
622 if (C->in_24_bit_fp_mode()) {
623 MacroAssembler masm(&cbuf);
624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
625 }
626
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
631
632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
633
634 if (framesize >= 128) {
635 emit_opcode(cbuf, 0x81); // add SP, #framesize
636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
637 emit_d32(cbuf, framesize);
638 } else if (framesize) {
639 emit_opcode(cbuf, 0x83); // add SP, #framesize
640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
643
644 emit_opcode(cbuf, 0x58 | EBP_enc);
645
646 if (do_polling() && C->is_method_compilation()) {
647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
648 emit_opcode(cbuf,0x85);
649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
651 }
652 }
653
654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656 // If method set FPU control word, restore to standard control word
657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
659 if (do_polling() && C->is_method_compilation()) size += 6;
660
661 int framesize = C->frame_slots() << LogBytesPerInt;
662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
663 // Remove two words for return addr and rbp,
664 framesize -= 2*wordSize;
665
666 size++; // popl rbp,
667
668 if (framesize >= 128) {
669 size += 6;
670 } else {
671 size += framesize ? 3 : 0;
672 }
673 return size;
674 }
675
676 int MachEpilogNode::reloc() const {
677 return 0; // a large enough number
678 }
679
680 const Pipeline * MachEpilogNode::pipeline() const {
681 return MachNode::pipeline_class();
682 }
683
684 int MachEpilogNode::safepoint_offset() const { return 0; }
685
686 //=============================================================================
687
688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
689 static enum RC rc_class( OptoReg::Name reg ) {
690
691 if( !OptoReg::is_valid(reg) ) return rc_bad;
692 if (OptoReg::is_stack(reg)) return rc_stack;
693
694 VMReg r = OptoReg::as_VMReg(reg);
695 if (r->is_Register()) return rc_int;
696 if (r->is_FloatRegister()) {
697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
698 return rc_float;
699 }
700 assert(r->is_XMMRegister(), "must be");
701 return rc_xmm;
702 }
703
704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
705 int opcode, const char *op_str, int size, outputStream* st ) {
706 if( cbuf ) {
707 emit_opcode (*cbuf, opcode );
708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
709 #ifndef PRODUCT
710 } else if( !do_size ) {
711 if( size != 0 ) st->print("\n\t");
712 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
715 } else { // FLD, FST, PUSH, POP
716 st->print("%s [ESP + #%d]",op_str,offset);
717 }
718 #endif
719 }
720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
721 return size+3+offset_size;
722 }
723
724 // Helper for XMM registers. Extra opcode bits, limited syntax.
725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
727 if (cbuf) {
728 MacroAssembler _masm(cbuf);
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) {
731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
732 } else {
733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
734 }
735 } else {
736 if (is_load) {
737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
738 } else {
739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
740 }
741 }
742 #ifndef PRODUCT
743 } else if (!do_size) {
744 if (size != 0) st->print("\n\t");
745 if (reg_lo+1 == reg_hi) { // double move?
746 if (is_load) st->print("%s %s,[ESP + #%d]",
747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
748 Matcher::regName[reg_lo], offset);
749 else st->print("MOVSD [ESP + #%d],%s",
750 offset, Matcher::regName[reg_lo]);
751 } else {
752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSS [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 }
757 #endif
758 }
759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
761 return size+5+offset_size;
762 }
763
764
765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
766 int src_hi, int dst_hi, int size, outputStream* st ) {
767 if (cbuf) {
768 MacroAssembler _masm(cbuf);
769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
771 as_XMMRegister(Matcher::_regEncode[src_lo]));
772 } else {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
774 as_XMMRegister(Matcher::_regEncode[src_lo]));
775 }
776 #ifndef PRODUCT
777 } else if (!do_size) {
778 if (size != 0) st->print("\n\t");
779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
782 } else {
783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
784 }
785 } else {
786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
788 } else {
789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
790 }
791 }
792 #endif
793 }
794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
795 // Only MOVAPS SSE prefix uses 1 byte.
796 int sz = 4;
797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
799 return size + sz;
800 }
801
802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
808 as_Register(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817
818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 int src_hi, int dst_hi, int size, outputStream* st ) {
820 // 32-bit
821 if (cbuf) {
822 MacroAssembler _masm(cbuf);
823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
824 as_XMMRegister(Matcher::_regEncode[src_lo]));
825 #ifndef PRODUCT
826 } else if (!do_size) {
827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
828 #endif
829 }
830 return 4;
831 }
832
833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
834 if( cbuf ) {
835 emit_opcode(*cbuf, 0x8B );
836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
837 #ifndef PRODUCT
838 } else if( !do_size ) {
839 if( size != 0 ) st->print("\n\t");
840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
841 #endif
842 }
843 return size+2;
844 }
845
846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
847 int offset, int size, outputStream* st ) {
848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
849 if( cbuf ) {
850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
852 #ifndef PRODUCT
853 } else if( !do_size ) {
854 if( size != 0 ) st->print("\n\t");
855 st->print("FLD %s",Matcher::regName[src_lo]);
856 #endif
857 }
858 size += 2;
859 }
860
861 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
862 const char *op_str;
863 int op;
864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
866 op = 0xDD;
867 } else { // 32-bit store
868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
869 op = 0xD9;
870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
871 }
872
873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
874 }
875
876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
878 int src_hi, int dst_hi, uint ireg, outputStream* st);
879
880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
881 int stack_offset, int reg, uint ireg, outputStream* st);
882
883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
884 int dst_offset, uint ireg, outputStream* st) {
885 int calc_size = 0;
886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
888 switch (ireg) {
889 case Op_VecS:
890 calc_size = 3+src_offset_size + 3+dst_offset_size;
891 break;
892 case Op_VecD:
893 calc_size = 3+src_offset_size + 3+dst_offset_size;
894 src_offset += 4;
895 dst_offset += 4;
896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
898 calc_size += 3+src_offset_size + 3+dst_offset_size;
899 break;
900 case Op_VecX:
901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
902 break;
903 case Op_VecY:
904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
905 break;
906 default:
907 ShouldNotReachHere();
908 }
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 int offset = __ offset();
912 switch (ireg) {
913 case Op_VecS:
914 __ pushl(Address(rsp, src_offset));
915 __ popl (Address(rsp, dst_offset));
916 break;
917 case Op_VecD:
918 __ pushl(Address(rsp, src_offset));
919 __ popl (Address(rsp, dst_offset));
920 __ pushl(Address(rsp, src_offset+4));
921 __ popl (Address(rsp, dst_offset+4));
922 break;
923 case Op_VecX:
924 __ movdqu(Address(rsp, -16), xmm0);
925 __ movdqu(xmm0, Address(rsp, src_offset));
926 __ movdqu(Address(rsp, dst_offset), xmm0);
927 __ movdqu(xmm0, Address(rsp, -16));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 int size = __ offset() - offset;
939 assert(size == calc_size, "incorrect size calculattion");
940 return size;
941 #ifndef PRODUCT
942 } else if (!do_size) {
943 switch (ireg) {
944 case Op_VecS:
945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
946 "popl [rsp + #%d]",
947 src_offset, dst_offset);
948 break;
949 case Op_VecD:
950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
951 "popq [rsp + #%d]\n\t"
952 "pushl [rsp + #%d]\n\t"
953 "popq [rsp + #%d]",
954 src_offset, dst_offset, src_offset+4, dst_offset+4);
955 break;
956 case Op_VecX:
957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
958 "movdqu xmm0, [rsp + #%d]\n\t"
959 "movdqu [rsp + #%d], xmm0\n\t"
960 "movdqu xmm0, [rsp - #16]",
961 src_offset, dst_offset);
962 break;
963 case Op_VecY:
964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
965 "vmovdqu xmm0, [rsp + #%d]\n\t"
966 "vmovdqu [rsp + #%d], xmm0\n\t"
967 "vmovdqu xmm0, [rsp - #32]",
968 src_offset, dst_offset);
969 break;
970 default:
971 ShouldNotReachHere();
972 }
973 #endif
974 }
975 return calc_size;
976 }
977
978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this );
983 OptoReg::Name dst_first = ra_->get_reg_first(this );
984
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
989
990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
991
992 // Generate spill code!
993 int size = 0;
994
995 if( src_first == dst_first && src_second == dst_second )
996 return size; // Self copy, no move
997
998 if (bottom_type()->isa_vect() != NULL) {
999 uint ireg = ideal_reg();
1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004 // mem -> mem
1005 int src_offset = ra_->reg2offset(src_first);
1006 int dst_offset = ra_->reg2offset(dst_first);
1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011 int stack_offset = ra_->reg2offset(dst_first);
1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014 int stack_offset = ra_->reg2offset(src_first);
1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1016 } else {
1017 ShouldNotReachHere();
1018 }
1019 }
1020
1021 // --------------------------------------
1022 // Check for mem-mem move. push/pop to move.
1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024 if( src_second == dst_first ) { // overlapping stack copy ranges
1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1029 }
1030 // move low bits
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1036 }
1037 return size;
1038 }
1039
1040 // --------------------------------------
1041 // Check for integer reg-reg copy
1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044
1045 // Check for integer store
1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048
1049 // Check for integer load
1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052
1053 // Check for integer reg-xmm reg copy
1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056 "no 64 bit integer-float reg moves" );
1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1059 // --------------------------------------
1060 // Check for float reg-reg copy
1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064 if( cbuf ) {
1065
1066 // Note the mucking with the register encode to compensate for the 0/1
1067 // indexing issue mentioned in a comment in the reg_def sections
1068 // for FPR registers many lines above here.
1069
1070 if( src_first != FPR1L_num ) {
1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 } else {
1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078 }
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083 else st->print( "FST %s", Matcher::regName[dst_first]);
1084 #endif
1085 }
1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087 }
1088
1089 // Check for float store
1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092 }
1093
1094 // Check for float load
1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096 int offset = ra_->reg2offset(src_first);
1097 const char *op_str;
1098 int op;
1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100 op_str = "FLD_D";
1101 op = 0xDD;
1102 } else { // 32-bit load
1103 op_str = "FLD_S";
1104 op = 0xD9;
1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106 }
1107 if( cbuf ) {
1108 emit_opcode (*cbuf, op );
1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113 } else if( !do_size ) {
1114 if( size != 0 ) st->print("\n\t");
1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117 }
1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119 return size + 3+offset_size+2;
1120 }
1121
1122 // Check for xmm reg-reg copy
1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125 (src_first+1 == src_second && dst_first+1 == dst_second),
1126 "no non-adjacent float-moves" );
1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128 }
1129
1130 // Check for xmm reg-integer reg copy
1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133 "no 64 bit float-integer reg moves" );
1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm store
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140 }
1141
1142 // Check for float xmm load
1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145 }
1146
1147 // Copy from float reg to xmm reg
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149 // copy to the top of stack from floating point reg
1150 // and use LEA to preserve flags
1151 if( cbuf ) {
1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155 emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157 } else if( !do_size ) {
1158 if( size != 0 ) st->print("\n\t");
1159 st->print("LEA ESP,[ESP-8]");
1160 #endif
1161 }
1162 size += 4;
1163
1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165
1166 // Copy from the temp memory to the xmm reg.
1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168
1169 if( cbuf ) {
1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173 emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175 } else if( !do_size ) {
1176 if( size != 0 ) st->print("\n\t");
1177 st->print("LEA ESP,[ESP+8]");
1178 #endif
1179 }
1180 size += 4;
1181 return size;
1182 }
1183
1184 assert( size > 0, "missed a case" );
1185
1186 // --------------------------------------------------------------------
1187 // Check for second bits still needing moving.
1188 if( src_second == dst_second )
1189 return size; // Self copy; no move
1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191
1192 // Check for second word int-int move
1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195
1196 // Check for second word integer store
1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199
1200 // Check for second word integer load
1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203
1204
1205 Unimplemented();
1206 }
1207
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210 implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215 implementation( &cbuf, ra_, false, NULL );
1216 }
1217
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219 return implementation( NULL, ra_, true, NULL );
1220 }
1221
1222
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227 int reg = ra_->get_reg_first(this);
1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_encode(this);
1235 if( offset >= 128 ) {
1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1237 emit_rm(cbuf, 0x2, reg, 0x04);
1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239 emit_d32(cbuf, offset);
1240 }
1241 else {
1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1243 emit_rm(cbuf, 0x1, reg, 0x04);
1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245 emit_d8(cbuf, offset);
1246 }
1247 }
1248
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 if( offset >= 128 ) {
1252 return 7;
1253 }
1254 else {
1255 return 4;
1256 }
1257 }
1258
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1264 st->print_cr("\tNOP");
1265 st->print_cr("\tNOP");
1266 if( !OptoBreakpoint )
1267 st->print_cr("\tNOP");
1268 }
1269 #endif
1270
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272 MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274 uint insts_size = cbuf.insts_size();
1275 #endif
1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277 masm.jump_cc(Assembler::notEqual,
1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279 /* WARNING these NOPs are critical so that verified entry point is properly
1280 aligned for patching by NativeJump::patch_verified_entry() */
1281 int nops_cnt = 2;
1282 if( !OptoBreakpoint ) // Leave space for int3
1283 nops_cnt += 1;
1284 masm.nop(nops_cnt);
1285
1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290 return OptoBreakpoint ? 11 : 12;
1291 }
1292
1293
1294 //=============================================================================
1295 uint size_exception_handler() {
1296 // NativeCall instruction size is the same as NativeJump.
1297 // exception handler starts out as jump and can be patched to
1298 // a call be deoptimization. (4932387)
1299 // Note that this value is also credited (in output.cpp) to
1300 // the size of the code section.
1301 return NativeJump::instruction_size;
1302 }
1303
1304 // Emit exception handler code. Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307
1308 // Note that the code buffer's insts_mark is always relative to insts.
1309 // That's why we must use the macroassembler to generate a handler.
1310 MacroAssembler _masm(&cbuf);
1311 address base =
1312 __ start_a_stub(size_exception_handler());
1313 if (base == NULL) return 0; // CodeBuffer::expand failed
1314 int offset = __ offset();
1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317 __ end_a_stub();
1318 return offset;
1319 }
1320
1321 uint size_deopt_handler() {
1322 // NativeCall instruction size is the same as NativeJump.
1323 // exception handler starts out as jump and can be patched to
1324 // a call be deoptimization. (4932387)
1325 // Note that this value is also credited (in output.cpp) to
1326 // the size of the code section.
1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 InternalAddress here(__ pc());
1341 __ pushptr(here.addr());
1342
1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345 __ end_a_stub();
1346 return offset;
1347 }
1348
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1352
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1357
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 // this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363 // The passed offset is relative to address of the branch.
1364 // On 86 a branch displacement is calculated relative to address
1365 // of a next instruction.
1366 offset -= br_size;
1367
1368 // the short version of jmpConUCF2 contains multiple branches,
1369 // making the reach slightly less
1370 if (rule == jmpConUCF2_rule)
1371 return (-126 <= offset && offset <= 125);
1372 return (-128 <= offset && offset <= 127);
1373 }
1374
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377 return false;
1378 }
1379
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400
1401 bool Matcher::narrow_oop_use_complex_address() {
1402 ShouldNotCallThis();
1403 return true;
1404 }
1405
1406 bool Matcher::narrow_klass_use_complex_address() {
1407 ShouldNotCallThis();
1408 return true;
1409 }
1410
1411
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers. Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed. Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece. Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423
1424
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426 // Get the memory operand from the node
1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430 uint opcnt = 1; // First operand
1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432 while( idx >= skipped+num_edges ) {
1433 skipped += num_edges;
1434 opcnt++; // Bump operand count
1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437 }
1438
1439 MachOper *memory = node->_opnds[opcnt];
1440 MachOper *new_memory = NULL;
1441 switch (memory->opcode()) {
1442 case DIRECT:
1443 case INDOFFSET32X:
1444 // No transformation necessary.
1445 return;
1446 case INDIRECT:
1447 new_memory = new (C) indirect_win95_safeOper( );
1448 break;
1449 case INDOFFSET8:
1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDOFFSET32:
1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXOFFSET:
1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457 break;
1458 case INDINDEXSCALE:
1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460 break;
1461 case INDINDEXSCALEOFFSET:
1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463 break;
1464 case LOAD_LONG_INDIRECT:
1465 case LOAD_LONG_INDOFFSET32:
1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467 return;
1468 default:
1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470 return;
1471 }
1472 node->_opnds[opcnt] = new_memory;
1473 }
1474
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485
1486 // Return whether or not this register is ever used as an argument. This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491 if( reg == ECX_num || reg == EDX_num ) return true;
1492 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494 return false;
1495 }
1496
1497 bool Matcher::is_spillable_arg( int reg ) {
1498 return can_be_java_arg(reg);
1499 }
1500
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502 // Use hardware integer DIV instruction when
1503 // it is faster than a code which use multiply.
1504 // Only when constant divisor fits into 32 bit
1505 // (min_jint is excluded to get only correct
1506 // positive 32 bit values from negative).
1507 return VM_Version::has_fast_idiv() &&
1508 (divisor == (int)divisor && divisor != min_jint);
1509 }
1510
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513 return EAX_REG_mask();
1514 }
1515
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518 return EDX_REG_mask();
1519 }
1520
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 // Returns true if the high 32 bits of the value is known to be zero.
1538 bool is_operand_hi32_zero(Node* n) {
1539 int opc = n->Opcode();
1540 if (opc == Op_AndL) {
1541 Node* o2 = n->in(2);
1542 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1543 return true;
1544 }
1545 }
1546 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1547 return true;
1548 }
1549 return false;
1550 }
1551
1552 %}
1553
1554 //----------ENCODING BLOCK-----------------------------------------------------
1555 // This block specifies the encoding classes used by the compiler to output
1556 // byte streams. Encoding classes generate functions which are called by
1557 // Machine Instruction Nodes in order to generate the bit encoding of the
1558 // instruction. Operands specify their base encoding interface with the
1559 // interface keyword. There are currently supported four interfaces,
1560 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1561 // operand to generate a function which returns its register number when
1562 // queried. CONST_INTER causes an operand to generate a function which
1563 // returns the value of the constant when queried. MEMORY_INTER causes an
1564 // operand to generate four functions which return the Base Register, the
1565 // Index Register, the Scale Value, and the Offset Value of the operand when
1566 // queried. COND_INTER causes an operand to generate six functions which
1567 // return the encoding code (ie - encoding bits for the instruction)
1568 // associated with each basic boolean condition for a conditional instruction.
1569 // Instructions specify two basic values for encoding. They use the
1570 // ins_encode keyword to specify their encoding class (which must be one of
1571 // the class names specified in the encoding block), and they use the
1572 // opcode keyword to specify, in order, their primary, secondary, and
1573 // tertiary opcode. Only the opcode sections which a particular instruction
1574 // needs for encoding need to be specified.
1575 encode %{
1576 // Build emit functions for each basic byte or larger field in the intel
1577 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1578 // code in the enc_class source block. Emit functions will live in the
1579 // main source block for now. In future, we can generalize this by
1580 // adding a syntax that specifies the sizes of fields in an order,
1581 // so that the adlc can build the emit functions automagically
1582
1583 // Emit primary opcode
1584 enc_class OpcP %{
1585 emit_opcode(cbuf, $primary);
1586 %}
1587
1588 // Emit secondary opcode
1589 enc_class OpcS %{
1590 emit_opcode(cbuf, $secondary);
1591 %}
1592
1593 // Emit opcode directly
1594 enc_class Opcode(immI d8) %{
1595 emit_opcode(cbuf, $d8$$constant);
1596 %}
1597
1598 enc_class SizePrefix %{
1599 emit_opcode(cbuf,0x66);
1600 %}
1601
1602 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1603 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1604 %}
1605
1606 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1607 emit_opcode(cbuf,$opcode$$constant);
1608 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1609 %}
1610
1611 enc_class mov_r32_imm0( rRegI dst ) %{
1612 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1613 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1614 %}
1615
1616 enc_class cdq_enc %{
1617 // Full implementation of Java idiv and irem; checks for
1618 // special case as described in JVM spec., p.243 & p.271.
1619 //
1620 // normal case special case
1621 //
1622 // input : rax,: dividend min_int
1623 // reg: divisor -1
1624 //
1625 // output: rax,: quotient (= rax, idiv reg) min_int
1626 // rdx: remainder (= rax, irem reg) 0
1627 //
1628 // Code sequnce:
1629 //
1630 // 81 F8 00 00 00 80 cmp rax,80000000h
1631 // 0F 85 0B 00 00 00 jne normal_case
1632 // 33 D2 xor rdx,edx
1633 // 83 F9 FF cmp rcx,0FFh
1634 // 0F 84 03 00 00 00 je done
1635 // normal_case:
1636 // 99 cdq
1637 // F7 F9 idiv rax,ecx
1638 // done:
1639 //
1640 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1641 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1643 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1644 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1645 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1646 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1647 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1648 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1649 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1651 // normal_case:
1652 emit_opcode(cbuf,0x99); // cdq
1653 // idiv (note: must be emitted by the user of this rule)
1654 // normal:
1655 %}
1656
1657 // Dense encoding for older common ops
1658 enc_class Opc_plus(immI opcode, rRegI reg) %{
1659 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1660 %}
1661
1662
1663 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1664 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1667 emit_opcode(cbuf, $primary | 0x02);
1668 }
1669 else { // If 32-bit immediate
1670 emit_opcode(cbuf, $primary);
1671 }
1672 %}
1673
1674 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1675 // Emit primary opcode and set sign-extend bit
1676 // Check for 8-bit immediate, and set sign extend bit in opcode
1677 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1678 emit_opcode(cbuf, $primary | 0x02); }
1679 else { // If 32-bit immediate
1680 emit_opcode(cbuf, $primary);
1681 }
1682 // Emit r/m byte with secondary opcode, after primary opcode.
1683 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1684 %}
1685
1686 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1687 // Check for 8-bit immediate, and set sign extend bit in opcode
1688 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1689 $$$emit8$imm$$constant;
1690 }
1691 else { // If 32-bit immediate
1692 // Output immediate
1693 $$$emit32$imm$$constant;
1694 }
1695 %}
1696
1697 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1698 // Emit primary opcode and set sign-extend bit
1699 // Check for 8-bit immediate, and set sign extend bit in opcode
1700 int con = (int)$imm$$constant; // Throw away top bits
1701 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1702 // Emit r/m byte with secondary opcode, after primary opcode.
1703 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1704 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1705 else emit_d32(cbuf,con);
1706 %}
1707
1708 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1709 // Emit primary opcode and set sign-extend bit
1710 // Check for 8-bit immediate, and set sign extend bit in opcode
1711 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1712 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1713 // Emit r/m byte with tertiary opcode, after primary opcode.
1714 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1715 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1716 else emit_d32(cbuf,con);
1717 %}
1718
1719 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1720 emit_cc(cbuf, $secondary, $dst$$reg );
1721 %}
1722
1723 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1724 int destlo = $dst$$reg;
1725 int desthi = HIGH_FROM_LOW(destlo);
1726 // bswap lo
1727 emit_opcode(cbuf, 0x0F);
1728 emit_cc(cbuf, 0xC8, destlo);
1729 // bswap hi
1730 emit_opcode(cbuf, 0x0F);
1731 emit_cc(cbuf, 0xC8, desthi);
1732 // xchg lo and hi
1733 emit_opcode(cbuf, 0x87);
1734 emit_rm(cbuf, 0x3, destlo, desthi);
1735 %}
1736
1737 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1738 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1739 %}
1740
1741 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1742 $$$emit8$primary;
1743 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1744 %}
1745
1746 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1747 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1748 emit_d8(cbuf, op >> 8 );
1749 emit_d8(cbuf, op & 255);
1750 %}
1751
1752 // emulate a CMOV with a conditional branch around a MOV
1753 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1754 // Invert sense of branch from sense of CMOV
1755 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1756 emit_d8( cbuf, $brOffs$$constant );
1757 %}
1758
1759 enc_class enc_PartialSubtypeCheck( ) %{
1760 Register Redi = as_Register(EDI_enc); // result register
1761 Register Reax = as_Register(EAX_enc); // super class
1762 Register Recx = as_Register(ECX_enc); // killed
1763 Register Resi = as_Register(ESI_enc); // sub class
1764 Label miss;
1765
1766 MacroAssembler _masm(&cbuf);
1767 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1768 NULL, &miss,
1769 /*set_cond_codes:*/ true);
1770 if ($primary) {
1771 __ xorptr(Redi, Redi);
1772 }
1773 __ bind(miss);
1774 %}
1775
1776 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1777 MacroAssembler masm(&cbuf);
1778 int start = masm.offset();
1779 if (UseSSE >= 2) {
1780 if (VerifyFPU) {
1781 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1782 }
1783 } else {
1784 // External c_calling_convention expects the FPU stack to be 'clean'.
1785 // Compiled code leaves it dirty. Do cleanup now.
1786 masm.empty_FPU_stack();
1787 }
1788 if (sizeof_FFree_Float_Stack_All == -1) {
1789 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1790 } else {
1791 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1792 }
1793 %}
1794
1795 enc_class Verify_FPU_For_Leaf %{
1796 if( VerifyFPU ) {
1797 MacroAssembler masm(&cbuf);
1798 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1799 }
1800 %}
1801
1802 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1803 // This is the instruction starting address for relocation info.
1804 cbuf.set_insts_mark();
1805 $$$emit8$primary;
1806 // CALL directly to the runtime
1807 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1808 runtime_call_Relocation::spec(), RELOC_IMM32 );
1809
1810 if (UseSSE >= 2) {
1811 MacroAssembler _masm(&cbuf);
1812 BasicType rt = tf()->return_type();
1813
1814 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1815 // A C runtime call where the return value is unused. In SSE2+
1816 // mode the result needs to be removed from the FPU stack. It's
1817 // likely that this function call could be removed by the
1818 // optimizer if the C function is a pure function.
1819 __ ffree(0);
1820 } else if (rt == T_FLOAT) {
1821 __ lea(rsp, Address(rsp, -4));
1822 __ fstp_s(Address(rsp, 0));
1823 __ movflt(xmm0, Address(rsp, 0));
1824 __ lea(rsp, Address(rsp, 4));
1825 } else if (rt == T_DOUBLE) {
1826 __ lea(rsp, Address(rsp, -8));
1827 __ fstp_d(Address(rsp, 0));
1828 __ movdbl(xmm0, Address(rsp, 0));
1829 __ lea(rsp, Address(rsp, 8));
1830 }
1831 }
1832 %}
1833
1834
1835 enc_class pre_call_resets %{
1836 // If method sets FPU control word restore it here
1837 debug_only(int off0 = cbuf.insts_size());
1838 if (ra_->C->in_24_bit_fp_mode()) {
1839 MacroAssembler _masm(&cbuf);
1840 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1841 }
1842 if (ra_->C->max_vector_size() > 16) {
1843 // Clear upper bits of YMM registers when current compiled code uses
1844 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1845 MacroAssembler _masm(&cbuf);
1846 __ vzeroupper();
1847 }
1848 debug_only(int off1 = cbuf.insts_size());
1849 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1850 %}
1851
1852 enc_class post_call_FPU %{
1853 // If method sets FPU control word do it here also
1854 if (Compile::current()->in_24_bit_fp_mode()) {
1855 MacroAssembler masm(&cbuf);
1856 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1857 }
1858 %}
1859
1860 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1861 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1862 // who we intended to call.
1863 cbuf.set_insts_mark();
1864 $$$emit8$primary;
1865 if (!_method) {
1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1867 runtime_call_Relocation::spec(), RELOC_IMM32 );
1868 } else if (_optimized_virtual) {
1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1870 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1871 } else {
1872 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1873 static_call_Relocation::spec(), RELOC_IMM32 );
1874 }
1875 if (_method) { // Emit stub for static call.
1876 CompiledStaticCall::emit_to_interp_stub(cbuf);
1877 }
1878 %}
1879
1880 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1881 MacroAssembler _masm(&cbuf);
1882 __ ic_call((address)$meth$$method);
1883 %}
1884
1885 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1886 int disp = in_bytes(Method::from_compiled_offset());
1887 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1888
1889 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1890 cbuf.set_insts_mark();
1891 $$$emit8$primary;
1892 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1893 emit_d8(cbuf, disp); // Displacement
1894
1895 %}
1896
1897 // Following encoding is no longer used, but may be restored if calling
1898 // convention changes significantly.
1899 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1900 //
1901 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1902 // // int ic_reg = Matcher::inline_cache_reg();
1903 // // int ic_encode = Matcher::_regEncode[ic_reg];
1904 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1905 // // int imo_encode = Matcher::_regEncode[imo_reg];
1906 //
1907 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1908 // // // so we load it immediately before the call
1909 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1910 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1911 //
1912 // // xor rbp,ebp
1913 // emit_opcode(cbuf, 0x33);
1914 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1915 //
1916 // // CALL to interpreter.
1917 // cbuf.set_insts_mark();
1918 // $$$emit8$primary;
1919 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1920 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1921 // %}
1922
1923 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1924 $$$emit8$primary;
1925 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1926 $$$emit8$shift$$constant;
1927 %}
1928
1929 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1933 $$$emit32$src$$constant;
1934 %}
1935
1936 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1937 // Load immediate does not have a zero or sign extended version
1938 // for 8-bit immediates
1939 emit_opcode(cbuf, $primary + $dst$$reg);
1940 $$$emit32$src$$constant;
1941 %}
1942
1943 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1944 // Load immediate does not have a zero or sign extended version
1945 // for 8-bit immediates
1946 int dst_enc = $dst$$reg;
1947 int src_con = $src$$constant & 0x0FFFFFFFFL;
1948 if (src_con == 0) {
1949 // xor dst, dst
1950 emit_opcode(cbuf, 0x33);
1951 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1952 } else {
1953 emit_opcode(cbuf, $primary + dst_enc);
1954 emit_d32(cbuf, src_con);
1955 }
1956 %}
1957
1958 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1959 // Load immediate does not have a zero or sign extended version
1960 // for 8-bit immediates
1961 int dst_enc = $dst$$reg + 2;
1962 int src_con = ((julong)($src$$constant)) >> 32;
1963 if (src_con == 0) {
1964 // xor dst, dst
1965 emit_opcode(cbuf, 0x33);
1966 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1967 } else {
1968 emit_opcode(cbuf, $primary + dst_enc);
1969 emit_d32(cbuf, src_con);
1970 }
1971 %}
1972
1973
1974 // Encode a reg-reg copy. If it is useless, then empty encoding.
1975 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1976 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1977 %}
1978
1979 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1980 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1981 %}
1982
1983 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1988 $$$emit8$primary;
1989 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1990 %}
1991
1992 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1993 $$$emit8$secondary;
1994 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1995 %}
1996
1997 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1998 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1999 %}
2000
2001 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2006 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2007 %}
2008
2009 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2010 // Output immediate
2011 $$$emit32$src$$constant;
2012 %}
2013
2014 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2015 // Output Float immediate bits
2016 jfloat jf = $src$$constant;
2017 int jf_as_bits = jint_cast( jf );
2018 emit_d32(cbuf, jf_as_bits);
2019 %}
2020
2021 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2022 // Output Float immediate bits
2023 jfloat jf = $src$$constant;
2024 int jf_as_bits = jint_cast( jf );
2025 emit_d32(cbuf, jf_as_bits);
2026 %}
2027
2028 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2029 // Output immediate
2030 $$$emit16$src$$constant;
2031 %}
2032
2033 enc_class Con_d32(immI src) %{
2034 emit_d32(cbuf,$src$$constant);
2035 %}
2036
2037 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2038 // Output immediate memory reference
2039 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2040 emit_d32(cbuf, 0x00);
2041 %}
2042
2043 enc_class lock_prefix( ) %{
2044 if( os::is_MP() )
2045 emit_opcode(cbuf,0xF0); // [Lock]
2046 %}
2047
2048 // Cmp-xchg long value.
2049 // Note: we need to swap rbx, and rcx before and after the
2050 // cmpxchg8 instruction because the instruction uses
2051 // rcx as the high order word of the new value to store but
2052 // our register encoding uses rbx,.
2053 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2054
2055 // XCHG rbx,ecx
2056 emit_opcode(cbuf,0x87);
2057 emit_opcode(cbuf,0xD9);
2058 // [Lock]
2059 if( os::is_MP() )
2060 emit_opcode(cbuf,0xF0);
2061 // CMPXCHG8 [Eptr]
2062 emit_opcode(cbuf,0x0F);
2063 emit_opcode(cbuf,0xC7);
2064 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2065 // XCHG rbx,ecx
2066 emit_opcode(cbuf,0x87);
2067 emit_opcode(cbuf,0xD9);
2068 %}
2069
2070 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074
2075 // CMPXCHG [Eptr]
2076 emit_opcode(cbuf,0x0F);
2077 emit_opcode(cbuf,0xB1);
2078 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2079 %}
2080
2081 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2082 int res_encoding = $res$$reg;
2083
2084 // MOV res,0
2085 emit_opcode( cbuf, 0xB8 + res_encoding);
2086 emit_d32( cbuf, 0 );
2087 // JNE,s fail
2088 emit_opcode(cbuf,0x75);
2089 emit_d8(cbuf, 5 );
2090 // MOV res,1
2091 emit_opcode( cbuf, 0xB8 + res_encoding);
2092 emit_d32( cbuf, 1 );
2093 // fail:
2094 %}
2095
2096 enc_class set_instruction_start( ) %{
2097 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2098 %}
2099
2100 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2101 int reg_encoding = $ereg$$reg;
2102 int base = $mem$$base;
2103 int index = $mem$$index;
2104 int scale = $mem$$scale;
2105 int displace = $mem$$disp;
2106 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2107 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2108 %}
2109
2110 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2111 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2112 int base = $mem$$base;
2113 int index = $mem$$index;
2114 int scale = $mem$$scale;
2115 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2116 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2117 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2118 %}
2119
2120 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2121 int r1, r2;
2122 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2123 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,$tertiary);
2126 emit_rm(cbuf, 0x3, r1, r2);
2127 emit_d8(cbuf,$cnt$$constant);
2128 emit_d8(cbuf,$primary);
2129 emit_rm(cbuf, 0x3, $secondary, r1);
2130 emit_d8(cbuf,$cnt$$constant);
2131 %}
2132
2133 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2134 emit_opcode( cbuf, 0x8B ); // Move
2135 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2136 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2137 emit_d8(cbuf,$primary);
2138 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2139 emit_d8(cbuf,$cnt$$constant-32);
2140 }
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2143 emit_d8(cbuf,31);
2144 %}
2145
2146 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2147 int r1, r2;
2148 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2149 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2150
2151 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2152 emit_rm(cbuf, 0x3, r1, r2);
2153 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2154 emit_opcode(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, r1);
2156 emit_d8(cbuf,$cnt$$constant-32);
2157 }
2158 emit_opcode(cbuf,0x33); // XOR r2,r2
2159 emit_rm(cbuf, 0x3, r2, r2);
2160 %}
2161
2162 // Clone of RegMem but accepts an extra parameter to access each
2163 // half of a double in memory; it never needs relocation info.
2164 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2165 emit_opcode(cbuf,$opcode$$constant);
2166 int reg_encoding = $rm_reg$$reg;
2167 int base = $mem$$base;
2168 int index = $mem$$index;
2169 int scale = $mem$$scale;
2170 int displace = $mem$$disp + $disp_for_half$$constant;
2171 relocInfo::relocType disp_reloc = relocInfo::none;
2172 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2173 %}
2174
2175 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2176 //
2177 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2178 // and it never needs relocation information.
2179 // Frequently used to move data between FPU's Stack Top and memory.
2180 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2181 int rm_byte_opcode = $rm_opcode$$constant;
2182 int base = $mem$$base;
2183 int index = $mem$$index;
2184 int scale = $mem$$scale;
2185 int displace = $mem$$disp;
2186 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2187 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2188 %}
2189
2190 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2191 int rm_byte_opcode = $rm_opcode$$constant;
2192 int base = $mem$$base;
2193 int index = $mem$$index;
2194 int scale = $mem$$scale;
2195 int displace = $mem$$disp;
2196 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2197 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2198 %}
2199
2200 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2201 int reg_encoding = $dst$$reg;
2202 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2203 int index = 0x04; // 0x04 indicates no index
2204 int scale = 0x00; // 0x00 indicates no scale
2205 int displace = $src1$$constant; // 0x00 indicates no displacement
2206 relocInfo::relocType disp_reloc = relocInfo::none;
2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2208 %}
2209
2210 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2211 // Compare dst,src
2212 emit_opcode(cbuf,0x3B);
2213 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2214 // jmp dst < src around move
2215 emit_opcode(cbuf,0x7C);
2216 emit_d8(cbuf,2);
2217 // move dst,src
2218 emit_opcode(cbuf,0x8B);
2219 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2220 %}
2221
2222 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2223 // Compare dst,src
2224 emit_opcode(cbuf,0x3B);
2225 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2226 // jmp dst > src around move
2227 emit_opcode(cbuf,0x7F);
2228 emit_d8(cbuf,2);
2229 // move dst,src
2230 emit_opcode(cbuf,0x8B);
2231 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232 %}
2233
2234 enc_class enc_FPR_store(memory mem, regDPR src) %{
2235 // If src is FPR1, we can just FST to store it.
2236 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2237 int reg_encoding = 0x2; // Just store
2238 int base = $mem$$base;
2239 int index = $mem$$index;
2240 int scale = $mem$$scale;
2241 int displace = $mem$$disp;
2242 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2243 if( $src$$reg != FPR1L_enc ) {
2244 reg_encoding = 0x3; // Store & pop
2245 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2246 emit_d8( cbuf, 0xC0-1+$src$$reg );
2247 }
2248 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2249 emit_opcode(cbuf,$primary);
2250 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2251 %}
2252
2253 enc_class neg_reg(rRegI dst) %{
2254 // NEG $dst
2255 emit_opcode(cbuf,0xF7);
2256 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2257 %}
2258
2259 enc_class setLT_reg(eCXRegI dst) %{
2260 // SETLT $dst
2261 emit_opcode(cbuf,0x0F);
2262 emit_opcode(cbuf,0x9C);
2263 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2264 %}
2265
2266 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2267 int tmpReg = $tmp$$reg;
2268
2269 // SUB $p,$q
2270 emit_opcode(cbuf,0x2B);
2271 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2272 // SBB $tmp,$tmp
2273 emit_opcode(cbuf,0x1B);
2274 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2275 // AND $tmp,$y
2276 emit_opcode(cbuf,0x23);
2277 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2278 // ADD $p,$tmp
2279 emit_opcode(cbuf,0x03);
2280 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2281 %}
2282
2283 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2284 // TEST shift,32
2285 emit_opcode(cbuf,0xF7);
2286 emit_rm(cbuf, 0x3, 0, ECX_enc);
2287 emit_d32(cbuf,0x20);
2288 // JEQ,s small
2289 emit_opcode(cbuf, 0x74);
2290 emit_d8(cbuf, 0x04);
2291 // MOV $dst.hi,$dst.lo
2292 emit_opcode( cbuf, 0x8B );
2293 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2294 // CLR $dst.lo
2295 emit_opcode(cbuf, 0x33);
2296 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2297 // small:
2298 // SHLD $dst.hi,$dst.lo,$shift
2299 emit_opcode(cbuf,0x0F);
2300 emit_opcode(cbuf,0xA5);
2301 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2302 // SHL $dst.lo,$shift"
2303 emit_opcode(cbuf,0xD3);
2304 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2305 %}
2306
2307 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2308 // TEST shift,32
2309 emit_opcode(cbuf,0xF7);
2310 emit_rm(cbuf, 0x3, 0, ECX_enc);
2311 emit_d32(cbuf,0x20);
2312 // JEQ,s small
2313 emit_opcode(cbuf, 0x74);
2314 emit_d8(cbuf, 0x04);
2315 // MOV $dst.lo,$dst.hi
2316 emit_opcode( cbuf, 0x8B );
2317 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2318 // CLR $dst.hi
2319 emit_opcode(cbuf, 0x33);
2320 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2321 // small:
2322 // SHRD $dst.lo,$dst.hi,$shift
2323 emit_opcode(cbuf,0x0F);
2324 emit_opcode(cbuf,0xAD);
2325 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2326 // SHR $dst.hi,$shift"
2327 emit_opcode(cbuf,0xD3);
2328 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2329 %}
2330
2331 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2332 // TEST shift,32
2333 emit_opcode(cbuf,0xF7);
2334 emit_rm(cbuf, 0x3, 0, ECX_enc);
2335 emit_d32(cbuf,0x20);
2336 // JEQ,s small
2337 emit_opcode(cbuf, 0x74);
2338 emit_d8(cbuf, 0x05);
2339 // MOV $dst.lo,$dst.hi
2340 emit_opcode( cbuf, 0x8B );
2341 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2342 // SAR $dst.hi,31
2343 emit_opcode(cbuf, 0xC1);
2344 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2345 emit_d8(cbuf, 0x1F );
2346 // small:
2347 // SHRD $dst.lo,$dst.hi,$shift
2348 emit_opcode(cbuf,0x0F);
2349 emit_opcode(cbuf,0xAD);
2350 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2351 // SAR $dst.hi,$shift"
2352 emit_opcode(cbuf,0xD3);
2353 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2354 %}
2355
2356
2357 // ----------------- Encodings for floating point unit -----------------
2358 // May leave result in FPU-TOS or FPU reg depending on opcodes
2359 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2360 $$$emit8$primary;
2361 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2362 %}
2363
2364 // Pop argument in FPR0 with FSTP ST(0)
2365 enc_class PopFPU() %{
2366 emit_opcode( cbuf, 0xDD );
2367 emit_d8( cbuf, 0xD8 );
2368 %}
2369
2370 // !!!!! equivalent to Pop_Reg_F
2371 enc_class Pop_Reg_DPR( regDPR dst ) %{
2372 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2373 emit_d8( cbuf, 0xD8+$dst$$reg );
2374 %}
2375
2376 enc_class Push_Reg_DPR( regDPR dst ) %{
2377 emit_opcode( cbuf, 0xD9 );
2378 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2379 %}
2380
2381 enc_class strictfp_bias1( regDPR dst ) %{
2382 emit_opcode( cbuf, 0xDB ); // FLD m80real
2383 emit_opcode( cbuf, 0x2D );
2384 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2385 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2386 emit_opcode( cbuf, 0xC8+$dst$$reg );
2387 %}
2388
2389 enc_class strictfp_bias2( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xDB ); // FLD m80real
2391 emit_opcode( cbuf, 0x2D );
2392 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2393 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2394 emit_opcode( cbuf, 0xC8+$dst$$reg );
2395 %}
2396
2397 // Special case for moving an integer register to a stack slot.
2398 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2399 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2400 %}
2401
2402 // Special case for moving a register to a stack slot.
2403 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2404 // Opcode already emitted
2405 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2406 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2407 emit_d32(cbuf, $dst$$disp); // Displacement
2408 %}
2409
2410 // Push the integer in stackSlot 'src' onto FP-stack
2411 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2412 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2413 %}
2414
2415 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2416 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2417 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2418 %}
2419
2420 // Same as Pop_Mem_F except for opcode
2421 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2422 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2423 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2424 %}
2425
2426 enc_class Pop_Reg_FPR( regFPR dst ) %{
2427 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2428 emit_d8( cbuf, 0xD8+$dst$$reg );
2429 %}
2430
2431 enc_class Push_Reg_FPR( regFPR dst ) %{
2432 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2433 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2434 %}
2435
2436 // Push FPU's float to a stack-slot, and pop FPU-stack
2437 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2438 int pop = 0x02;
2439 if ($src$$reg != FPR1L_enc) {
2440 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2441 emit_d8( cbuf, 0xC0-1+$src$$reg );
2442 pop = 0x03;
2443 }
2444 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2445 %}
2446
2447 // Push FPU's double to a stack-slot, and pop FPU-stack
2448 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2449 int pop = 0x02;
2450 if ($src$$reg != FPR1L_enc) {
2451 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2452 emit_d8( cbuf, 0xC0-1+$src$$reg );
2453 pop = 0x03;
2454 }
2455 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2456 %}
2457
2458 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2459 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2460 int pop = 0xD0 - 1; // -1 since we skip FLD
2461 if ($src$$reg != FPR1L_enc) {
2462 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2463 emit_d8( cbuf, 0xC0-1+$src$$reg );
2464 pop = 0xD8;
2465 }
2466 emit_opcode( cbuf, 0xDD );
2467 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2468 %}
2469
2470
2471 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2472 // load dst in FPR0
2473 emit_opcode( cbuf, 0xD9 );
2474 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2475 if ($src$$reg != FPR1L_enc) {
2476 // fincstp
2477 emit_opcode (cbuf, 0xD9);
2478 emit_opcode (cbuf, 0xF7);
2479 // swap src with FPR1:
2480 // FXCH FPR1 with src
2481 emit_opcode(cbuf, 0xD9);
2482 emit_d8(cbuf, 0xC8-1+$src$$reg );
2483 // fdecstp
2484 emit_opcode (cbuf, 0xD9);
2485 emit_opcode (cbuf, 0xF6);
2486 }
2487 %}
2488
2489 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2490 MacroAssembler _masm(&cbuf);
2491 __ subptr(rsp, 8);
2492 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2493 __ fld_d(Address(rsp, 0));
2494 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2495 __ fld_d(Address(rsp, 0));
2496 %}
2497
2498 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2499 MacroAssembler _masm(&cbuf);
2500 __ subptr(rsp, 4);
2501 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2502 __ fld_s(Address(rsp, 0));
2503 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2504 __ fld_s(Address(rsp, 0));
2505 %}
2506
2507 enc_class Push_ResultD(regD dst) %{
2508 MacroAssembler _masm(&cbuf);
2509 __ fstp_d(Address(rsp, 0));
2510 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2511 __ addptr(rsp, 8);
2512 %}
2513
2514 enc_class Push_ResultF(regF dst, immI d8) %{
2515 MacroAssembler _masm(&cbuf);
2516 __ fstp_s(Address(rsp, 0));
2517 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2518 __ addptr(rsp, $d8$$constant);
2519 %}
2520
2521 enc_class Push_SrcD(regD src) %{
2522 MacroAssembler _masm(&cbuf);
2523 __ subptr(rsp, 8);
2524 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2525 __ fld_d(Address(rsp, 0));
2526 %}
2527
2528 enc_class push_stack_temp_qword() %{
2529 MacroAssembler _masm(&cbuf);
2530 __ subptr(rsp, 8);
2531 %}
2532
2533 enc_class pop_stack_temp_qword() %{
2534 MacroAssembler _masm(&cbuf);
2535 __ addptr(rsp, 8);
2536 %}
2537
2538 enc_class push_xmm_to_fpr1(regD src) %{
2539 MacroAssembler _masm(&cbuf);
2540 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2541 __ fld_d(Address(rsp, 0));
2542 %}
2543
2544 enc_class Push_Result_Mod_DPR( regDPR src) %{
2545 if ($src$$reg != FPR1L_enc) {
2546 // fincstp
2547 emit_opcode (cbuf, 0xD9);
2548 emit_opcode (cbuf, 0xF7);
2549 // FXCH FPR1 with src
2550 emit_opcode(cbuf, 0xD9);
2551 emit_d8(cbuf, 0xC8-1+$src$$reg );
2552 // fdecstp
2553 emit_opcode (cbuf, 0xD9);
2554 emit_opcode (cbuf, 0xF6);
2555 }
2556 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2557 // // FSTP FPR$dst$$reg
2558 // emit_opcode( cbuf, 0xDD );
2559 // emit_d8( cbuf, 0xD8+$dst$$reg );
2560 %}
2561
2562 enc_class fnstsw_sahf_skip_parity() %{
2563 // fnstsw ax
2564 emit_opcode( cbuf, 0xDF );
2565 emit_opcode( cbuf, 0xE0 );
2566 // sahf
2567 emit_opcode( cbuf, 0x9E );
2568 // jnp ::skip
2569 emit_opcode( cbuf, 0x7B );
2570 emit_opcode( cbuf, 0x05 );
2571 %}
2572
2573 enc_class emitModDPR() %{
2574 // fprem must be iterative
2575 // :: loop
2576 // fprem
2577 emit_opcode( cbuf, 0xD9 );
2578 emit_opcode( cbuf, 0xF8 );
2579 // wait
2580 emit_opcode( cbuf, 0x9b );
2581 // fnstsw ax
2582 emit_opcode( cbuf, 0xDF );
2583 emit_opcode( cbuf, 0xE0 );
2584 // sahf
2585 emit_opcode( cbuf, 0x9E );
2586 // jp ::loop
2587 emit_opcode( cbuf, 0x0F );
2588 emit_opcode( cbuf, 0x8A );
2589 emit_opcode( cbuf, 0xF4 );
2590 emit_opcode( cbuf, 0xFF );
2591 emit_opcode( cbuf, 0xFF );
2592 emit_opcode( cbuf, 0xFF );
2593 %}
2594
2595 enc_class fpu_flags() %{
2596 // fnstsw_ax
2597 emit_opcode( cbuf, 0xDF);
2598 emit_opcode( cbuf, 0xE0);
2599 // test ax,0x0400
2600 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2601 emit_opcode( cbuf, 0xA9 );
2602 emit_d16 ( cbuf, 0x0400 );
2603 // // // This sequence works, but stalls for 12-16 cycles on PPro
2604 // // test rax,0x0400
2605 // emit_opcode( cbuf, 0xA9 );
2606 // emit_d32 ( cbuf, 0x00000400 );
2607 //
2608 // jz exit (no unordered comparison)
2609 emit_opcode( cbuf, 0x74 );
2610 emit_d8 ( cbuf, 0x02 );
2611 // mov ah,1 - treat as LT case (set carry flag)
2612 emit_opcode( cbuf, 0xB4 );
2613 emit_d8 ( cbuf, 0x01 );
2614 // sahf
2615 emit_opcode( cbuf, 0x9E);
2616 %}
2617
2618 enc_class cmpF_P6_fixup() %{
2619 // Fixup the integer flags in case comparison involved a NaN
2620 //
2621 // JNP exit (no unordered comparison, P-flag is set by NaN)
2622 emit_opcode( cbuf, 0x7B );
2623 emit_d8 ( cbuf, 0x03 );
2624 // MOV AH,1 - treat as LT case (set carry flag)
2625 emit_opcode( cbuf, 0xB4 );
2626 emit_d8 ( cbuf, 0x01 );
2627 // SAHF
2628 emit_opcode( cbuf, 0x9E);
2629 // NOP // target for branch to avoid branch to branch
2630 emit_opcode( cbuf, 0x90);
2631 %}
2632
2633 // fnstsw_ax();
2634 // sahf();
2635 // movl(dst, nan_result);
2636 // jcc(Assembler::parity, exit);
2637 // movl(dst, less_result);
2638 // jcc(Assembler::below, exit);
2639 // movl(dst, equal_result);
2640 // jcc(Assembler::equal, exit);
2641 // movl(dst, greater_result);
2642
2643 // less_result = 1;
2644 // greater_result = -1;
2645 // equal_result = 0;
2646 // nan_result = -1;
2647
2648 enc_class CmpF_Result(rRegI dst) %{
2649 // fnstsw_ax();
2650 emit_opcode( cbuf, 0xDF);
2651 emit_opcode( cbuf, 0xE0);
2652 // sahf
2653 emit_opcode( cbuf, 0x9E);
2654 // movl(dst, nan_result);
2655 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2656 emit_d32( cbuf, -1 );
2657 // jcc(Assembler::parity, exit);
2658 emit_opcode( cbuf, 0x7A );
2659 emit_d8 ( cbuf, 0x13 );
2660 // movl(dst, less_result);
2661 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2662 emit_d32( cbuf, -1 );
2663 // jcc(Assembler::below, exit);
2664 emit_opcode( cbuf, 0x72 );
2665 emit_d8 ( cbuf, 0x0C );
2666 // movl(dst, equal_result);
2667 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2668 emit_d32( cbuf, 0 );
2669 // jcc(Assembler::equal, exit);
2670 emit_opcode( cbuf, 0x74 );
2671 emit_d8 ( cbuf, 0x05 );
2672 // movl(dst, greater_result);
2673 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2674 emit_d32( cbuf, 1 );
2675 %}
2676
2677
2678 // Compare the longs and set flags
2679 // BROKEN! Do Not use as-is
2680 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2681 // CMP $src1.hi,$src2.hi
2682 emit_opcode( cbuf, 0x3B );
2683 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2684 // JNE,s done
2685 emit_opcode(cbuf,0x75);
2686 emit_d8(cbuf, 2 );
2687 // CMP $src1.lo,$src2.lo
2688 emit_opcode( cbuf, 0x3B );
2689 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2690 // done:
2691 %}
2692
2693 enc_class convert_int_long( regL dst, rRegI src ) %{
2694 // mov $dst.lo,$src
2695 int dst_encoding = $dst$$reg;
2696 int src_encoding = $src$$reg;
2697 encode_Copy( cbuf, dst_encoding , src_encoding );
2698 // mov $dst.hi,$src
2699 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2700 // sar $dst.hi,31
2701 emit_opcode( cbuf, 0xC1 );
2702 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2703 emit_d8(cbuf, 0x1F );
2704 %}
2705
2706 enc_class convert_long_double( eRegL src ) %{
2707 // push $src.hi
2708 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2709 // push $src.lo
2710 emit_opcode(cbuf, 0x50+$src$$reg );
2711 // fild 64-bits at [SP]
2712 emit_opcode(cbuf,0xdf);
2713 emit_d8(cbuf, 0x6C);
2714 emit_d8(cbuf, 0x24);
2715 emit_d8(cbuf, 0x00);
2716 // pop stack
2717 emit_opcode(cbuf, 0x83); // add SP, #8
2718 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2719 emit_d8(cbuf, 0x8);
2720 %}
2721
2722 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2723 // IMUL EDX:EAX,$src1
2724 emit_opcode( cbuf, 0xF7 );
2725 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2726 // SAR EDX,$cnt-32
2727 int shift_count = ((int)$cnt$$constant) - 32;
2728 if (shift_count > 0) {
2729 emit_opcode(cbuf, 0xC1);
2730 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2731 emit_d8(cbuf, shift_count);
2732 }
2733 %}
2734
2735 // this version doesn't have add sp, 8
2736 enc_class convert_long_double2( eRegL src ) %{
2737 // push $src.hi
2738 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2739 // push $src.lo
2740 emit_opcode(cbuf, 0x50+$src$$reg );
2741 // fild 64-bits at [SP]
2742 emit_opcode(cbuf,0xdf);
2743 emit_d8(cbuf, 0x6C);
2744 emit_d8(cbuf, 0x24);
2745 emit_d8(cbuf, 0x00);
2746 %}
2747
2748 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2749 // Basic idea: long = (long)int * (long)int
2750 // IMUL EDX:EAX, src
2751 emit_opcode( cbuf, 0xF7 );
2752 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2753 %}
2754
2755 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2756 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2757 // MUL EDX:EAX, src
2758 emit_opcode( cbuf, 0xF7 );
2759 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2760 %}
2761
2762 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2763 // Basic idea: lo(result) = lo(x_lo * y_lo)
2764 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2765 // MOV $tmp,$src.lo
2766 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2767 // IMUL $tmp,EDX
2768 emit_opcode( cbuf, 0x0F );
2769 emit_opcode( cbuf, 0xAF );
2770 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2771 // MOV EDX,$src.hi
2772 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2773 // IMUL EDX,EAX
2774 emit_opcode( cbuf, 0x0F );
2775 emit_opcode( cbuf, 0xAF );
2776 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2777 // ADD $tmp,EDX
2778 emit_opcode( cbuf, 0x03 );
2779 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2780 // MUL EDX:EAX,$src.lo
2781 emit_opcode( cbuf, 0xF7 );
2782 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2783 // ADD EDX,ESI
2784 emit_opcode( cbuf, 0x03 );
2785 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2786 %}
2787
2788 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2789 // Basic idea: lo(result) = lo(src * y_lo)
2790 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2791 // IMUL $tmp,EDX,$src
2792 emit_opcode( cbuf, 0x6B );
2793 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2794 emit_d8( cbuf, (int)$src$$constant );
2795 // MOV EDX,$src
2796 emit_opcode(cbuf, 0xB8 + EDX_enc);
2797 emit_d32( cbuf, (int)$src$$constant );
2798 // MUL EDX:EAX,EDX
2799 emit_opcode( cbuf, 0xF7 );
2800 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2801 // ADD EDX,ESI
2802 emit_opcode( cbuf, 0x03 );
2803 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2804 %}
2805
2806 enc_class long_div( eRegL src1, eRegL src2 ) %{
2807 // PUSH src1.hi
2808 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2809 // PUSH src1.lo
2810 emit_opcode(cbuf, 0x50+$src1$$reg );
2811 // PUSH src2.hi
2812 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2813 // PUSH src2.lo
2814 emit_opcode(cbuf, 0x50+$src2$$reg );
2815 // CALL directly to the runtime
2816 cbuf.set_insts_mark();
2817 emit_opcode(cbuf,0xE8); // Call into runtime
2818 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2819 // Restore stack
2820 emit_opcode(cbuf, 0x83); // add SP, #framesize
2821 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2822 emit_d8(cbuf, 4*4);
2823 %}
2824
2825 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2826 // PUSH src1.hi
2827 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2828 // PUSH src1.lo
2829 emit_opcode(cbuf, 0x50+$src1$$reg );
2830 // PUSH src2.hi
2831 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2832 // PUSH src2.lo
2833 emit_opcode(cbuf, 0x50+$src2$$reg );
2834 // CALL directly to the runtime
2835 cbuf.set_insts_mark();
2836 emit_opcode(cbuf,0xE8); // Call into runtime
2837 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2838 // Restore stack
2839 emit_opcode(cbuf, 0x83); // add SP, #framesize
2840 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2841 emit_d8(cbuf, 4*4);
2842 %}
2843
2844 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2845 // MOV $tmp,$src.lo
2846 emit_opcode(cbuf, 0x8B);
2847 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2848 // OR $tmp,$src.hi
2849 emit_opcode(cbuf, 0x0B);
2850 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2851 %}
2852
2853 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2854 // CMP $src1.lo,$src2.lo
2855 emit_opcode( cbuf, 0x3B );
2856 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2857 // JNE,s skip
2858 emit_cc(cbuf, 0x70, 0x5);
2859 emit_d8(cbuf,2);
2860 // CMP $src1.hi,$src2.hi
2861 emit_opcode( cbuf, 0x3B );
2862 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2863 %}
2864
2865 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2866 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2867 emit_opcode( cbuf, 0x3B );
2868 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2869 // MOV $tmp,$src1.hi
2870 emit_opcode( cbuf, 0x8B );
2871 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2872 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2873 emit_opcode( cbuf, 0x1B );
2874 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2875 %}
2876
2877 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2878 // XOR $tmp,$tmp
2879 emit_opcode(cbuf,0x33); // XOR
2880 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2881 // CMP $tmp,$src.lo
2882 emit_opcode( cbuf, 0x3B );
2883 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2884 // SBB $tmp,$src.hi
2885 emit_opcode( cbuf, 0x1B );
2886 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2887 %}
2888
2889 // Sniff, sniff... smells like Gnu Superoptimizer
2890 enc_class neg_long( eRegL dst ) %{
2891 emit_opcode(cbuf,0xF7); // NEG hi
2892 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2893 emit_opcode(cbuf,0xF7); // NEG lo
2894 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2895 emit_opcode(cbuf,0x83); // SBB hi,0
2896 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2897 emit_d8 (cbuf,0 );
2898 %}
2899
2900
2901 // Because the transitions from emitted code to the runtime
2902 // monitorenter/exit helper stubs are so slow it's critical that
2903 // we inline both the stack-locking fast-path and the inflated fast path.
2904 //
2905 // See also: cmpFastLock and cmpFastUnlock.
2906 //
2907 // What follows is a specialized inline transliteration of the code
2908 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2909 // another option would be to emit TrySlowEnter and TrySlowExit methods
2910 // at startup-time. These methods would accept arguments as
2911 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2912 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2913 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2914 // In practice, however, the # of lock sites is bounded and is usually small.
2915 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2916 // if the processor uses simple bimodal branch predictors keyed by EIP
2917 // Since the helper routines would be called from multiple synchronization
2918 // sites.
2919 //
2920 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2921 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2922 // to those specialized methods. That'd give us a mostly platform-independent
2923 // implementation that the JITs could optimize and inline at their pleasure.
2924 // Done correctly, the only time we'd need to cross to native could would be
2925 // to park() or unpark() threads. We'd also need a few more unsafe operators
2926 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2927 // (b) explicit barriers or fence operations.
2928 //
2929 // TODO:
2930 //
2931 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2932 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2933 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2934 // the lock operators would typically be faster than reifying Self.
2935 //
2936 // * Ideally I'd define the primitives as:
2937 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2938 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2939 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2940 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2941 // Furthermore the register assignments are overconstrained, possibly resulting in
2942 // sub-optimal code near the synchronization site.
2943 //
2944 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2945 // Alternately, use a better sp-proximity test.
2946 //
2947 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2948 // Either one is sufficient to uniquely identify a thread.
2949 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2950 //
2951 // * Intrinsify notify() and notifyAll() for the common cases where the
2952 // object is locked by the calling thread but the waitlist is empty.
2953 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2954 //
2955 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2956 // But beware of excessive branch density on AMD Opterons.
2957 //
2958 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2959 // or failure of the fast-path. If the fast-path fails then we pass
2960 // control to the slow-path, typically in C. In Fast_Lock and
2961 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2962 // will emit a conditional branch immediately after the node.
2963 // So we have branches to branches and lots of ICC.ZF games.
2964 // Instead, it might be better to have C2 pass a "FailureLabel"
2965 // into Fast_Lock and Fast_Unlock. In the case of success, control
2966 // will drop through the node. ICC.ZF is undefined at exit.
2967 // In the case of failure, the node will branch directly to the
2968 // FailureLabel
2969
2970
2971 // obj: object to lock
2972 // box: on-stack box address (displaced header location) - KILLED
2973 // rax,: tmp -- KILLED
2974 // scr: tmp -- KILLED
2975 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2976
2977 Register objReg = as_Register($obj$$reg);
2978 Register boxReg = as_Register($box$$reg);
2979 Register tmpReg = as_Register($tmp$$reg);
2980 Register scrReg = as_Register($scr$$reg);
2981
2982 // Ensure the register assignents are disjoint
2983 guarantee (objReg != boxReg, "") ;
2984 guarantee (objReg != tmpReg, "") ;
2985 guarantee (objReg != scrReg, "") ;
2986 guarantee (boxReg != tmpReg, "") ;
2987 guarantee (boxReg != scrReg, "") ;
2988 guarantee (tmpReg == as_Register(EAX_enc), "") ;
2989
2990 MacroAssembler masm(&cbuf);
2991
2992 if (_counters != NULL) {
2993 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2994 }
2995 if (EmitSync & 1) {
2996 // set box->dhw = unused_mark (3)
2997 // Force all sync thru slow-path: slow_enter() and slow_exit()
2998 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
2999 masm.cmpptr (rsp, (int32_t)0) ;
3000 } else
3001 if (EmitSync & 2) {
3002 Label DONE_LABEL ;
3003 if (UseBiasedLocking) {
3004 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3005 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3006 }
3007
3008 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3009 masm.orptr (tmpReg, 0x1);
3010 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3011 if (os::is_MP()) { masm.lock(); }
3012 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3013 masm.jcc(Assembler::equal, DONE_LABEL);
3014 // Recursive locking
3015 masm.subptr(tmpReg, rsp);
3016 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3017 masm.movptr(Address(boxReg, 0), tmpReg);
3018 masm.bind(DONE_LABEL) ;
3019 } else {
3020 // Possible cases that we'll encounter in fast_lock
3021 // ------------------------------------------------
3022 // * Inflated
3023 // -- unlocked
3024 // -- Locked
3025 // = by self
3026 // = by other
3027 // * biased
3028 // -- by Self
3029 // -- by other
3030 // * neutral
3031 // * stack-locked
3032 // -- by self
3033 // = sp-proximity test hits
3034 // = sp-proximity test generates false-negative
3035 // -- by other
3036 //
3037
3038 Label IsInflated, DONE_LABEL, PopDone ;
3039
3040 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3041 // order to reduce the number of conditional branches in the most common cases.
3042 // Beware -- there's a subtle invariant that fetch of the markword
3043 // at [FETCH], below, will never observe a biased encoding (*101b).
3044 // If this invariant is not held we risk exclusion (safety) failure.
3045 if (UseBiasedLocking && !UseOptoBiasInlining) {
3046 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3047 }
3048
3049 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3050 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3051 masm.jccb (Assembler::notZero, IsInflated) ;
3052
3053 // Attempt stack-locking ...
3054 masm.orptr (tmpReg, 0x1);
3055 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3056 if (os::is_MP()) { masm.lock(); }
3057 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3058 if (_counters != NULL) {
3059 masm.cond_inc32(Assembler::equal,
3060 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3061 }
3062 masm.jccb (Assembler::equal, DONE_LABEL);
3063
3064 // Recursive locking
3065 masm.subptr(tmpReg, rsp);
3066 masm.andptr(tmpReg, 0xFFFFF003 );
3067 masm.movptr(Address(boxReg, 0), tmpReg);
3068 if (_counters != NULL) {
3069 masm.cond_inc32(Assembler::equal,
3070 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3071 }
3072 masm.jmp (DONE_LABEL) ;
3073
3074 masm.bind (IsInflated) ;
3075
3076 // The object is inflated.
3077 //
3078 // TODO-FIXME: eliminate the ugly use of manifest constants:
3079 // Use markOopDesc::monitor_value instead of "2".
3080 // use markOop::unused_mark() instead of "3".
3081 // The tmpReg value is an objectMonitor reference ORed with
3082 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3083 // objectmonitor pointer by masking off the "2" bit or we can just
3084 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3085 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3086 //
3087 // I use the latter as it avoids AGI stalls.
3088 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3089 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3090 //
3091 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3092
3093 // boxReg refers to the on-stack BasicLock in the current frame.
3094 // We'd like to write:
3095 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3096 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3097 // additional latency as we have another ST in the store buffer that must drain.
3098
3099 if (EmitSync & 8192) {
3100 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3101 masm.get_thread (scrReg) ;
3102 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3103 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3104 if (os::is_MP()) { masm.lock(); }
3105 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3106 } else
3107 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3108 masm.movptr(scrReg, boxReg) ;
3109 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3110
3111 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3112 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3113 // prefetchw [eax + Offset(_owner)-2]
3114 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3115 }
3116
3117 if ((EmitSync & 64) == 0) {
3118 // Optimistic form: consider XORL tmpReg,tmpReg
3119 masm.movptr(tmpReg, NULL_WORD) ;
3120 } else {
3121 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3122 // Test-And-CAS instead of CAS
3123 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3124 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3125 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3126 }
3127
3128 // Appears unlocked - try to swing _owner from null to non-null.
3129 // Ideally, I'd manifest "Self" with get_thread and then attempt
3130 // to CAS the register containing Self into m->Owner.
3131 // But we don't have enough registers, so instead we can either try to CAS
3132 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3133 // we later store "Self" into m->Owner. Transiently storing a stack address
3134 // (rsp or the address of the box) into m->owner is harmless.
3135 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3136 if (os::is_MP()) { masm.lock(); }
3137 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3138 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3139 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3140 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3141 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3142 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3143
3144 // If the CAS fails we can either retry or pass control to the slow-path.
3145 // We use the latter tactic.
3146 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3147 // If the CAS was successful ...
3148 // Self has acquired the lock
3149 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3150 // Intentional fall-through into DONE_LABEL ...
3151 } else {
3152 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3153 masm.movptr(boxReg, tmpReg) ;
3154
3155 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3156 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3157 // prefetchw [eax + Offset(_owner)-2]
3158 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3159 }
3160
3161 if ((EmitSync & 64) == 0) {
3162 // Optimistic form
3163 masm.xorptr (tmpReg, tmpReg) ;
3164 } else {
3165 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3166 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3167 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3168 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3169 }
3170
3171 // Appears unlocked - try to swing _owner from null to non-null.
3172 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3173 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3174 masm.get_thread (scrReg) ;
3175 if (os::is_MP()) { masm.lock(); }
3176 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3177
3178 // If the CAS fails we can either retry or pass control to the slow-path.
3179 // We use the latter tactic.
3180 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3181 // If the CAS was successful ...
3182 // Self has acquired the lock
3183 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3184 // Intentional fall-through into DONE_LABEL ...
3185 }
3186
3187 // DONE_LABEL is a hot target - we'd really like to place it at the
3188 // start of cache line by padding with NOPs.
3189 // See the AMD and Intel software optimization manuals for the
3190 // most efficient "long" NOP encodings.
3191 // Unfortunately none of our alignment mechanisms suffice.
3192 masm.bind(DONE_LABEL);
3193
3194 // Avoid branch-to-branch on AMD processors
3195 // This appears to be superstition.
3196 if (EmitSync & 32) masm.nop() ;
3197
3198
3199 // At DONE_LABEL the icc ZFlag is set as follows ...
3200 // Fast_Unlock uses the same protocol.
3201 // ZFlag == 1 -> Success
3202 // ZFlag == 0 -> Failure - force control through the slow-path
3203 }
3204 %}
3205
3206 // obj: object to unlock
3207 // box: box address (displaced header location), killed. Must be EAX.
3208 // rbx,: killed tmp; cannot be obj nor box.
3209 //
3210 // Some commentary on balanced locking:
3211 //
3212 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3213 // Methods that don't have provably balanced locking are forced to run in the
3214 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3215 // The interpreter provides two properties:
3216 // I1: At return-time the interpreter automatically and quietly unlocks any
3217 // objects acquired the current activation (frame). Recall that the
3218 // interpreter maintains an on-stack list of locks currently held by
3219 // a frame.
3220 // I2: If a method attempts to unlock an object that is not held by the
3221 // the frame the interpreter throws IMSX.
3222 //
3223 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3224 // B() doesn't have provably balanced locking so it runs in the interpreter.
3225 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3226 // is still locked by A().
3227 //
3228 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3229 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3230 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3231 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3232
3233 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3234
3235 Register objReg = as_Register($obj$$reg);
3236 Register boxReg = as_Register($box$$reg);
3237 Register tmpReg = as_Register($tmp$$reg);
3238
3239 guarantee (objReg != boxReg, "") ;
3240 guarantee (objReg != tmpReg, "") ;
3241 guarantee (boxReg != tmpReg, "") ;
3242 guarantee (boxReg == as_Register(EAX_enc), "") ;
3243 MacroAssembler masm(&cbuf);
3244
3245 if (EmitSync & 4) {
3246 // Disable - inhibit all inlining. Force control through the slow-path
3247 masm.cmpptr (rsp, 0) ;
3248 } else
3249 if (EmitSync & 8) {
3250 Label DONE_LABEL ;
3251 if (UseBiasedLocking) {
3252 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3253 }
3254 // classic stack-locking code ...
3255 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3256 masm.testptr(tmpReg, tmpReg) ;
3257 masm.jcc (Assembler::zero, DONE_LABEL) ;
3258 if (os::is_MP()) { masm.lock(); }
3259 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3260 masm.bind(DONE_LABEL);
3261 } else {
3262 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3263
3264 // Critically, the biased locking test must have precedence over
3265 // and appear before the (box->dhw == 0) recursive stack-lock test.
3266 if (UseBiasedLocking && !UseOptoBiasInlining) {
3267 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3268 }
3269
3270 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3271 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3272 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3273
3274 masm.testptr(tmpReg, 0x02) ; // Inflated?
3275 masm.jccb (Assembler::zero, Stacked) ;
3276
3277 masm.bind (Inflated) ;
3278 // It's inflated.
3279 // Despite our balanced locking property we still check that m->_owner == Self
3280 // as java routines or native JNI code called by this thread might
3281 // have released the lock.
3282 // Refer to the comments in synchronizer.cpp for how we might encode extra
3283 // state in _succ so we can avoid fetching EntryList|cxq.
3284 //
3285 // I'd like to add more cases in fast_lock() and fast_unlock() --
3286 // such as recursive enter and exit -- but we have to be wary of
3287 // I$ bloat, T$ effects and BP$ effects.
3288 //
3289 // If there's no contention try a 1-0 exit. That is, exit without
3290 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3291 // we detect and recover from the race that the 1-0 exit admits.
3292 //
3293 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3294 // before it STs null into _owner, releasing the lock. Updates
3295 // to data protected by the critical section must be visible before
3296 // we drop the lock (and thus before any other thread could acquire
3297 // the lock and observe the fields protected by the lock).
3298 // IA32's memory-model is SPO, so STs are ordered with respect to
3299 // each other and there's no need for an explicit barrier (fence).
3300 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3301
3302 masm.get_thread (boxReg) ;
3303 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3304 // prefetchw [ebx + Offset(_owner)-2]
3305 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3306 }
3307
3308 // Note that we could employ various encoding schemes to reduce
3309 // the number of loads below (currently 4) to just 2 or 3.
3310 // Refer to the comments in synchronizer.cpp.
3311 // In practice the chain of fetches doesn't seem to impact performance, however.
3312 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3313 // Attempt to reduce branch density - AMD's branch predictor.
3314 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3315 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3316 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3317 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3318 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3319 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3320 masm.jmpb (DONE_LABEL) ;
3321 } else {
3322 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3323 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3324 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3325 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3326 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3327 masm.jccb (Assembler::notZero, CheckSucc) ;
3328 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3329 masm.jmpb (DONE_LABEL) ;
3330 }
3331
3332 // The Following code fragment (EmitSync & 65536) improves the performance of
3333 // contended applications and contended synchronization microbenchmarks.
3334 // Unfortunately the emission of the code - even though not executed - causes regressions
3335 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3336 // with an equal number of never-executed NOPs results in the same regression.
3337 // We leave it off by default.
3338
3339 if ((EmitSync & 65536) != 0) {
3340 Label LSuccess, LGoSlowPath ;
3341
3342 masm.bind (CheckSucc) ;
3343
3344 // Optional pre-test ... it's safe to elide this
3345 if ((EmitSync & 16) == 0) {
3346 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3347 masm.jccb (Assembler::zero, LGoSlowPath) ;
3348 }
3349
3350 // We have a classic Dekker-style idiom:
3351 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3352 // There are a number of ways to implement the barrier:
3353 // (1) lock:andl &m->_owner, 0
3354 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3355 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3356 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3357 // (2) If supported, an explicit MFENCE is appealing.
3358 // In older IA32 processors MFENCE is slower than lock:add or xchg
3359 // particularly if the write-buffer is full as might be the case if
3360 // if stores closely precede the fence or fence-equivalent instruction.
3361 // In more modern implementations MFENCE appears faster, however.
3362 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3363 // The $lines underlying the top-of-stack should be in M-state.
3364 // The locked add instruction is serializing, of course.
3365 // (4) Use xchg, which is serializing
3366 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3367 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3368 // The integer condition codes will tell us if succ was 0.
3369 // Since _succ and _owner should reside in the same $line and
3370 // we just stored into _owner, it's likely that the $line
3371 // remains in M-state for the lock:orl.
3372 //
3373 // We currently use (3), although it's likely that switching to (2)
3374 // is correct for the future.
3375
3376 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3377 if (os::is_MP()) {
3378 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3379 masm.mfence();
3380 } else {
3381 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3382 }
3383 }
3384 // Ratify _succ remains non-null
3385 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3386 masm.jccb (Assembler::notZero, LSuccess) ;
3387
3388 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3389 if (os::is_MP()) { masm.lock(); }
3390 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3391 masm.jccb (Assembler::notEqual, LSuccess) ;
3392 // Since we're low on registers we installed rsp as a placeholding in _owner.
3393 // Now install Self over rsp. This is safe as we're transitioning from
3394 // non-null to non=null
3395 masm.get_thread (boxReg) ;
3396 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3397 // Intentional fall-through into LGoSlowPath ...
3398
3399 masm.bind (LGoSlowPath) ;
3400 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3401 masm.jmpb (DONE_LABEL) ;
3402
3403 masm.bind (LSuccess) ;
3404 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3405 masm.jmpb (DONE_LABEL) ;
3406 }
3407
3408 masm.bind (Stacked) ;
3409 // It's not inflated and it's not recursively stack-locked and it's not biased.
3410 // It must be stack-locked.
3411 // Try to reset the header to displaced header.
3412 // The "box" value on the stack is stable, so we can reload
3413 // and be assured we observe the same value as above.
3414 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3415 if (os::is_MP()) { masm.lock(); }
3416 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3417 // Intention fall-thru into DONE_LABEL
3418
3419
3420 // DONE_LABEL is a hot target - we'd really like to place it at the
3421 // start of cache line by padding with NOPs.
3422 // See the AMD and Intel software optimization manuals for the
3423 // most efficient "long" NOP encodings.
3424 // Unfortunately none of our alignment mechanisms suffice.
3425 if ((EmitSync & 65536) == 0) {
3426 masm.bind (CheckSucc) ;
3427 }
3428 masm.bind(DONE_LABEL);
3429
3430 // Avoid branch to branch on AMD processors
3431 if (EmitSync & 32768) { masm.nop() ; }
3432 }
3433 %}
3434
3435
3436 enc_class enc_pop_rdx() %{
3437 emit_opcode(cbuf,0x5A);
3438 %}
3439
3440 enc_class enc_rethrow() %{
3441 cbuf.set_insts_mark();
3442 emit_opcode(cbuf, 0xE9); // jmp entry
3443 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3444 runtime_call_Relocation::spec(), RELOC_IMM32 );
3445 %}
3446
3447
3448 // Convert a double to an int. Java semantics require we do complex
3449 // manglelations in the corner cases. So we set the rounding mode to
3450 // 'zero', store the darned double down as an int, and reset the
3451 // rounding mode to 'nearest'. The hardware throws an exception which
3452 // patches up the correct value directly to the stack.
3453 enc_class DPR2I_encoding( regDPR src ) %{
3454 // Flip to round-to-zero mode. We attempted to allow invalid-op
3455 // exceptions here, so that a NAN or other corner-case value will
3456 // thrown an exception (but normal values get converted at full speed).
3457 // However, I2C adapters and other float-stack manglers leave pending
3458 // invalid-op exceptions hanging. We would have to clear them before
3459 // enabling them and that is more expensive than just testing for the
3460 // invalid value Intel stores down in the corner cases.
3461 emit_opcode(cbuf,0xD9); // FLDCW trunc
3462 emit_opcode(cbuf,0x2D);
3463 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3464 // Allocate a word
3465 emit_opcode(cbuf,0x83); // SUB ESP,4
3466 emit_opcode(cbuf,0xEC);
3467 emit_d8(cbuf,0x04);
3468 // Encoding assumes a double has been pushed into FPR0.
3469 // Store down the double as an int, popping the FPU stack
3470 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3471 emit_opcode(cbuf,0x1C);
3472 emit_d8(cbuf,0x24);
3473 // Restore the rounding mode; mask the exception
3474 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3475 emit_opcode(cbuf,0x2D);
3476 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3477 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3478 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3479
3480 // Load the converted int; adjust CPU stack
3481 emit_opcode(cbuf,0x58); // POP EAX
3482 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3483 emit_d32 (cbuf,0x80000000); // 0x80000000
3484 emit_opcode(cbuf,0x75); // JNE around_slow_call
3485 emit_d8 (cbuf,0x07); // Size of slow_call
3486 // Push src onto stack slow-path
3487 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3488 emit_d8 (cbuf,0xC0-1+$src$$reg );
3489 // CALL directly to the runtime
3490 cbuf.set_insts_mark();
3491 emit_opcode(cbuf,0xE8); // Call into runtime
3492 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3493 // Carry on here...
3494 %}
3495
3496 enc_class DPR2L_encoding( regDPR src ) %{
3497 emit_opcode(cbuf,0xD9); // FLDCW trunc
3498 emit_opcode(cbuf,0x2D);
3499 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3500 // Allocate a word
3501 emit_opcode(cbuf,0x83); // SUB ESP,8
3502 emit_opcode(cbuf,0xEC);
3503 emit_d8(cbuf,0x08);
3504 // Encoding assumes a double has been pushed into FPR0.
3505 // Store down the double as a long, popping the FPU stack
3506 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3507 emit_opcode(cbuf,0x3C);
3508 emit_d8(cbuf,0x24);
3509 // Restore the rounding mode; mask the exception
3510 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3511 emit_opcode(cbuf,0x2D);
3512 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3513 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3514 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3515
3516 // Load the converted int; adjust CPU stack
3517 emit_opcode(cbuf,0x58); // POP EAX
3518 emit_opcode(cbuf,0x5A); // POP EDX
3519 emit_opcode(cbuf,0x81); // CMP EDX,imm
3520 emit_d8 (cbuf,0xFA); // rdx
3521 emit_d32 (cbuf,0x80000000); // 0x80000000
3522 emit_opcode(cbuf,0x75); // JNE around_slow_call
3523 emit_d8 (cbuf,0x07+4); // Size of slow_call
3524 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3525 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3526 emit_opcode(cbuf,0x75); // JNE around_slow_call
3527 emit_d8 (cbuf,0x07); // Size of slow_call
3528 // Push src onto stack slow-path
3529 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3530 emit_d8 (cbuf,0xC0-1+$src$$reg );
3531 // CALL directly to the runtime
3532 cbuf.set_insts_mark();
3533 emit_opcode(cbuf,0xE8); // Call into runtime
3534 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3535 // Carry on here...
3536 %}
3537
3538 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3539 // Operand was loaded from memory into fp ST (stack top)
3540 // FMUL ST,$src /* D8 C8+i */
3541 emit_opcode(cbuf, 0xD8);
3542 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3543 %}
3544
3545 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3546 // FADDP ST,src2 /* D8 C0+i */
3547 emit_opcode(cbuf, 0xD8);
3548 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3549 //could use FADDP src2,fpST /* DE C0+i */
3550 %}
3551
3552 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3553 // FADDP src2,ST /* DE C0+i */
3554 emit_opcode(cbuf, 0xDE);
3555 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3556 %}
3557
3558 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3559 // Operand has been loaded into fp ST (stack top)
3560 // FSUB ST,$src1
3561 emit_opcode(cbuf, 0xD8);
3562 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3563
3564 // FDIV
3565 emit_opcode(cbuf, 0xD8);
3566 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3567 %}
3568
3569 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3570 // Operand was loaded from memory into fp ST (stack top)
3571 // FADD ST,$src /* D8 C0+i */
3572 emit_opcode(cbuf, 0xD8);
3573 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3574
3575 // FMUL ST,src2 /* D8 C*+i */
3576 emit_opcode(cbuf, 0xD8);
3577 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3578 %}
3579
3580
3581 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3582 // Operand was loaded from memory into fp ST (stack top)
3583 // FADD ST,$src /* D8 C0+i */
3584 emit_opcode(cbuf, 0xD8);
3585 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3586
3587 // FMULP src2,ST /* DE C8+i */
3588 emit_opcode(cbuf, 0xDE);
3589 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3590 %}
3591
3592 // Atomically load the volatile long
3593 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3594 emit_opcode(cbuf,0xDF);
3595 int rm_byte_opcode = 0x05;
3596 int base = $mem$$base;
3597 int index = $mem$$index;
3598 int scale = $mem$$scale;
3599 int displace = $mem$$disp;
3600 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3601 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3602 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3603 %}
3604
3605 // Volatile Store Long. Must be atomic, so move it into
3606 // the FP TOS and then do a 64-bit FIST. Has to probe the
3607 // target address before the store (for null-ptr checks)
3608 // so the memory operand is used twice in the encoding.
3609 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3610 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3611 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3612 emit_opcode(cbuf,0xDF);
3613 int rm_byte_opcode = 0x07;
3614 int base = $mem$$base;
3615 int index = $mem$$index;
3616 int scale = $mem$$scale;
3617 int displace = $mem$$disp;
3618 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3619 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3620 %}
3621
3622 // Safepoint Poll. This polls the safepoint page, and causes an
3623 // exception if it is not readable. Unfortunately, it kills the condition code
3624 // in the process
3625 // We current use TESTL [spp],EDI
3626 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3627
3628 enc_class Safepoint_Poll() %{
3629 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3630 emit_opcode(cbuf,0x85);
3631 emit_rm (cbuf, 0x0, 0x7, 0x5);
3632 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3633 %}
3634 %}
3635
3636
3637 //----------FRAME--------------------------------------------------------------
3638 // Definition of frame structure and management information.
3639 //
3640 // S T A C K L A Y O U T Allocators stack-slot number
3641 // | (to get allocators register number
3642 // G Owned by | | v add OptoReg::stack0())
3643 // r CALLER | |
3644 // o | +--------+ pad to even-align allocators stack-slot
3645 // w V | pad0 | numbers; owned by CALLER
3646 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3647 // h ^ | in | 5
3648 // | | args | 4 Holes in incoming args owned by SELF
3649 // | | | | 3
3650 // | | +--------+
3651 // V | | old out| Empty on Intel, window on Sparc
3652 // | old |preserve| Must be even aligned.
3653 // | SP-+--------+----> Matcher::_old_SP, even aligned
3654 // | | in | 3 area for Intel ret address
3655 // Owned by |preserve| Empty on Sparc.
3656 // SELF +--------+
3657 // | | pad2 | 2 pad to align old SP
3658 // | +--------+ 1
3659 // | | locks | 0
3660 // | +--------+----> OptoReg::stack0(), even aligned
3661 // | | pad1 | 11 pad to align new SP
3662 // | +--------+
3663 // | | | 10
3664 // | | spills | 9 spills
3665 // V | | 8 (pad0 slot for callee)
3666 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3667 // ^ | out | 7
3668 // | | args | 6 Holes in outgoing args owned by CALLEE
3669 // Owned by +--------+
3670 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3671 // | new |preserve| Must be even-aligned.
3672 // | SP-+--------+----> Matcher::_new_SP, even aligned
3673 // | | |
3674 //
3675 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3676 // known from SELF's arguments and the Java calling convention.
3677 // Region 6-7 is determined per call site.
3678 // Note 2: If the calling convention leaves holes in the incoming argument
3679 // area, those holes are owned by SELF. Holes in the outgoing area
3680 // are owned by the CALLEE. Holes should not be nessecary in the
3681 // incoming area, as the Java calling convention is completely under
3682 // the control of the AD file. Doubles can be sorted and packed to
3683 // avoid holes. Holes in the outgoing arguments may be nessecary for
3684 // varargs C calling conventions.
3685 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3686 // even aligned with pad0 as needed.
3687 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3688 // region 6-11 is even aligned; it may be padded out more so that
3689 // the region from SP to FP meets the minimum stack alignment.
3690
3691 frame %{
3692 // What direction does stack grow in (assumed to be same for C & Java)
3693 stack_direction(TOWARDS_LOW);
3694
3695 // These three registers define part of the calling convention
3696 // between compiled code and the interpreter.
3697 inline_cache_reg(EAX); // Inline Cache Register
3698 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3699
3700 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3701 cisc_spilling_operand_name(indOffset32);
3702
3703 // Number of stack slots consumed by locking an object
3704 sync_stack_slots(1);
3705
3706 // Compiled code's Frame Pointer
3707 frame_pointer(ESP);
3708 // Interpreter stores its frame pointer in a register which is
3709 // stored to the stack by I2CAdaptors.
3710 // I2CAdaptors convert from interpreted java to compiled java.
3711 interpreter_frame_pointer(EBP);
3712
3713 // Stack alignment requirement
3714 // Alignment size in bytes (128-bit -> 16 bytes)
3715 stack_alignment(StackAlignmentInBytes);
3716
3717 // Number of stack slots between incoming argument block and the start of
3718 // a new frame. The PROLOG must add this many slots to the stack. The
3719 // EPILOG must remove this many slots. Intel needs one slot for
3720 // return address and one for rbp, (must save rbp)
3721 in_preserve_stack_slots(2+VerifyStackAtCalls);
3722
3723 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3724 // for calls to C. Supports the var-args backing area for register parms.
3725 varargs_C_out_slots_killed(0);
3726
3727 // The after-PROLOG location of the return address. Location of
3728 // return address specifies a type (REG or STACK) and a number
3729 // representing the register number (i.e. - use a register name) or
3730 // stack slot.
3731 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3732 // Otherwise, it is above the locks and verification slot and alignment word
3733 return_addr(STACK - 1 +
3734 round_to((Compile::current()->in_preserve_stack_slots() +
3735 Compile::current()->fixed_slots()),
3736 stack_alignment_in_slots()));
3737
3738 // Body of function which returns an integer array locating
3739 // arguments either in registers or in stack slots. Passed an array
3740 // of ideal registers called "sig" and a "length" count. Stack-slot
3741 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3742 // arguments for a CALLEE. Incoming stack arguments are
3743 // automatically biased by the preserve_stack_slots field above.
3744 calling_convention %{
3745 // No difference between ingoing/outgoing just pass false
3746 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3747 %}
3748
3749
3750 // Body of function which returns an integer array locating
3751 // arguments either in registers or in stack slots. Passed an array
3752 // of ideal registers called "sig" and a "length" count. Stack-slot
3753 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3754 // arguments for a CALLEE. Incoming stack arguments are
3755 // automatically biased by the preserve_stack_slots field above.
3756 c_calling_convention %{
3757 // This is obviously always outgoing
3758 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3759 %}
3760
3761 // Location of C & interpreter return values
3762 c_return_value %{
3763 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3764 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3765 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3766
3767 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3768 // that C functions return float and double results in XMM0.
3769 if( ideal_reg == Op_RegD && UseSSE>=2 )
3770 return OptoRegPair(XMM0b_num,XMM0_num);
3771 if( ideal_reg == Op_RegF && UseSSE>=2 )
3772 return OptoRegPair(OptoReg::Bad,XMM0_num);
3773
3774 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3775 %}
3776
3777 // Location of return values
3778 return_value %{
3779 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3780 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3781 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3782 if( ideal_reg == Op_RegD && UseSSE>=2 )
3783 return OptoRegPair(XMM0b_num,XMM0_num);
3784 if( ideal_reg == Op_RegF && UseSSE>=1 )
3785 return OptoRegPair(OptoReg::Bad,XMM0_num);
3786 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3787 %}
3788
3789 %}
3790
3791 //----------ATTRIBUTES---------------------------------------------------------
3792 //----------Operand Attributes-------------------------------------------------
3793 op_attrib op_cost(0); // Required cost attribute
3794
3795 //----------Instruction Attributes---------------------------------------------
3796 ins_attrib ins_cost(100); // Required cost attribute
3797 ins_attrib ins_size(8); // Required size attribute (in bits)
3798 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3799 // non-matching short branch variant of some
3800 // long branch?
3801 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3802 // specifies the alignment that some part of the instruction (not
3803 // necessarily the start) requires. If > 1, a compute_padding()
3804 // function must be provided for the instruction
3805
3806 //----------OPERANDS-----------------------------------------------------------
3807 // Operand definitions must precede instruction definitions for correct parsing
3808 // in the ADLC because operands constitute user defined types which are used in
3809 // instruction definitions.
3810
3811 //----------Simple Operands----------------------------------------------------
3812 // Immediate Operands
3813 // Integer Immediate
3814 operand immI() %{
3815 match(ConI);
3816
3817 op_cost(10);
3818 format %{ %}
3819 interface(CONST_INTER);
3820 %}
3821
3822 // Constant for test vs zero
3823 operand immI0() %{
3824 predicate(n->get_int() == 0);
3825 match(ConI);
3826
3827 op_cost(0);
3828 format %{ %}
3829 interface(CONST_INTER);
3830 %}
3831
3832 // Constant for increment
3833 operand immI1() %{
3834 predicate(n->get_int() == 1);
3835 match(ConI);
3836
3837 op_cost(0);
3838 format %{ %}
3839 interface(CONST_INTER);
3840 %}
3841
3842 // Constant for decrement
3843 operand immI_M1() %{
3844 predicate(n->get_int() == -1);
3845 match(ConI);
3846
3847 op_cost(0);
3848 format %{ %}
3849 interface(CONST_INTER);
3850 %}
3851
3852 // Valid scale values for addressing modes
3853 operand immI2() %{
3854 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3855 match(ConI);
3856
3857 format %{ %}
3858 interface(CONST_INTER);
3859 %}
3860
3861 operand immI8() %{
3862 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3863 match(ConI);
3864
3865 op_cost(5);
3866 format %{ %}
3867 interface(CONST_INTER);
3868 %}
3869
3870 operand immI16() %{
3871 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3872 match(ConI);
3873
3874 op_cost(10);
3875 format %{ %}
3876 interface(CONST_INTER);
3877 %}
3878
3879 // Int Immediate non-negative
3880 operand immU31()
3881 %{
3882 predicate(n->get_int() >= 0);
3883 match(ConI);
3884
3885 op_cost(0);
3886 format %{ %}
3887 interface(CONST_INTER);
3888 %}
3889
3890 // Constant for long shifts
3891 operand immI_32() %{
3892 predicate( n->get_int() == 32 );
3893 match(ConI);
3894
3895 op_cost(0);
3896 format %{ %}
3897 interface(CONST_INTER);
3898 %}
3899
3900 operand immI_1_31() %{
3901 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3902 match(ConI);
3903
3904 op_cost(0);
3905 format %{ %}
3906 interface(CONST_INTER);
3907 %}
3908
3909 operand immI_32_63() %{
3910 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3911 match(ConI);
3912 op_cost(0);
3913
3914 format %{ %}
3915 interface(CONST_INTER);
3916 %}
3917
3918 operand immI_1() %{
3919 predicate( n->get_int() == 1 );
3920 match(ConI);
3921
3922 op_cost(0);
3923 format %{ %}
3924 interface(CONST_INTER);
3925 %}
3926
3927 operand immI_2() %{
3928 predicate( n->get_int() == 2 );
3929 match(ConI);
3930
3931 op_cost(0);
3932 format %{ %}
3933 interface(CONST_INTER);
3934 %}
3935
3936 operand immI_3() %{
3937 predicate( n->get_int() == 3 );
3938 match(ConI);
3939
3940 op_cost(0);
3941 format %{ %}
3942 interface(CONST_INTER);
3943 %}
3944
3945 // Pointer Immediate
3946 operand immP() %{
3947 match(ConP);
3948
3949 op_cost(10);
3950 format %{ %}
3951 interface(CONST_INTER);
3952 %}
3953
3954 // NULL Pointer Immediate
3955 operand immP0() %{
3956 predicate( n->get_ptr() == 0 );
3957 match(ConP);
3958 op_cost(0);
3959
3960 format %{ %}
3961 interface(CONST_INTER);
3962 %}
3963
3964 // Long Immediate
3965 operand immL() %{
3966 match(ConL);
3967
3968 op_cost(20);
3969 format %{ %}
3970 interface(CONST_INTER);
3971 %}
3972
3973 // Long Immediate zero
3974 operand immL0() %{
3975 predicate( n->get_long() == 0L );
3976 match(ConL);
3977 op_cost(0);
3978
3979 format %{ %}
3980 interface(CONST_INTER);
3981 %}
3982
3983 // Long Immediate zero
3984 operand immL_M1() %{
3985 predicate( n->get_long() == -1L );
3986 match(ConL);
3987 op_cost(0);
3988
3989 format %{ %}
3990 interface(CONST_INTER);
3991 %}
3992
3993 // Long immediate from 0 to 127.
3994 // Used for a shorter form of long mul by 10.
3995 operand immL_127() %{
3996 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3997 match(ConL);
3998 op_cost(0);
3999
4000 format %{ %}
4001 interface(CONST_INTER);
4002 %}
4003
4004 // Long Immediate: low 32-bit mask
4005 operand immL_32bits() %{
4006 predicate(n->get_long() == 0xFFFFFFFFL);
4007 match(ConL);
4008 op_cost(0);
4009
4010 format %{ %}
4011 interface(CONST_INTER);
4012 %}
4013
4014 // Long Immediate: low 32-bit mask
4015 operand immL32() %{
4016 predicate(n->get_long() == (int)(n->get_long()));
4017 match(ConL);
4018 op_cost(20);
4019
4020 format %{ %}
4021 interface(CONST_INTER);
4022 %}
4023
4024 //Double Immediate zero
4025 operand immDPR0() %{
4026 // Do additional (and counter-intuitive) test against NaN to work around VC++
4027 // bug that generates code such that NaNs compare equal to 0.0
4028 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4029 match(ConD);
4030
4031 op_cost(5);
4032 format %{ %}
4033 interface(CONST_INTER);
4034 %}
4035
4036 // Double Immediate one
4037 operand immDPR1() %{
4038 predicate( UseSSE<=1 && n->getd() == 1.0 );
4039 match(ConD);
4040
4041 op_cost(5);
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4045
4046 // Double Immediate
4047 operand immDPR() %{
4048 predicate(UseSSE<=1);
4049 match(ConD);
4050
4051 op_cost(5);
4052 format %{ %}
4053 interface(CONST_INTER);
4054 %}
4055
4056 operand immD() %{
4057 predicate(UseSSE>=2);
4058 match(ConD);
4059
4060 op_cost(5);
4061 format %{ %}
4062 interface(CONST_INTER);
4063 %}
4064
4065 // Double Immediate zero
4066 operand immD0() %{
4067 // Do additional (and counter-intuitive) test against NaN to work around VC++
4068 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4069 // compare equal to -0.0.
4070 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4071 match(ConD);
4072
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 // Float Immediate zero
4078 operand immFPR0() %{
4079 predicate(UseSSE == 0 && n->getf() == 0.0F);
4080 match(ConF);
4081
4082 op_cost(5);
4083 format %{ %}
4084 interface(CONST_INTER);
4085 %}
4086
4087 // Float Immediate one
4088 operand immFPR1() %{
4089 predicate(UseSSE == 0 && n->getf() == 1.0F);
4090 match(ConF);
4091
4092 op_cost(5);
4093 format %{ %}
4094 interface(CONST_INTER);
4095 %}
4096
4097 // Float Immediate
4098 operand immFPR() %{
4099 predicate( UseSSE == 0 );
4100 match(ConF);
4101
4102 op_cost(5);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4106
4107 // Float Immediate
4108 operand immF() %{
4109 predicate(UseSSE >= 1);
4110 match(ConF);
4111
4112 op_cost(5);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4116
4117 // Float Immediate zero. Zero and not -0.0
4118 operand immF0() %{
4119 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4120 match(ConF);
4121
4122 op_cost(5);
4123 format %{ %}
4124 interface(CONST_INTER);
4125 %}
4126
4127 // Immediates for special shifts (sign extend)
4128
4129 // Constants for increment
4130 operand immI_16() %{
4131 predicate( n->get_int() == 16 );
4132 match(ConI);
4133
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 operand immI_24() %{
4139 predicate( n->get_int() == 24 );
4140 match(ConI);
4141
4142 format %{ %}
4143 interface(CONST_INTER);
4144 %}
4145
4146 // Constant for byte-wide masking
4147 operand immI_255() %{
4148 predicate( n->get_int() == 255 );
4149 match(ConI);
4150
4151 format %{ %}
4152 interface(CONST_INTER);
4153 %}
4154
4155 // Constant for short-wide masking
4156 operand immI_65535() %{
4157 predicate(n->get_int() == 65535);
4158 match(ConI);
4159
4160 format %{ %}
4161 interface(CONST_INTER);
4162 %}
4163
4164 // Register Operands
4165 // Integer Register
4166 operand rRegI() %{
4167 constraint(ALLOC_IN_RC(int_reg));
4168 match(RegI);
4169 match(xRegI);
4170 match(eAXRegI);
4171 match(eBXRegI);
4172 match(eCXRegI);
4173 match(eDXRegI);
4174 match(eDIRegI);
4175 match(eSIRegI);
4176
4177 format %{ %}
4178 interface(REG_INTER);
4179 %}
4180
4181 // Subset of Integer Register
4182 operand xRegI(rRegI reg) %{
4183 constraint(ALLOC_IN_RC(int_x_reg));
4184 match(reg);
4185 match(eAXRegI);
4186 match(eBXRegI);
4187 match(eCXRegI);
4188 match(eDXRegI);
4189
4190 format %{ %}
4191 interface(REG_INTER);
4192 %}
4193
4194 // Special Registers
4195 operand eAXRegI(xRegI reg) %{
4196 constraint(ALLOC_IN_RC(eax_reg));
4197 match(reg);
4198 match(rRegI);
4199
4200 format %{ "EAX" %}
4201 interface(REG_INTER);
4202 %}
4203
4204 // Special Registers
4205 operand eBXRegI(xRegI reg) %{
4206 constraint(ALLOC_IN_RC(ebx_reg));
4207 match(reg);
4208 match(rRegI);
4209
4210 format %{ "EBX" %}
4211 interface(REG_INTER);
4212 %}
4213
4214 operand eCXRegI(xRegI reg) %{
4215 constraint(ALLOC_IN_RC(ecx_reg));
4216 match(reg);
4217 match(rRegI);
4218
4219 format %{ "ECX" %}
4220 interface(REG_INTER);
4221 %}
4222
4223 operand eDXRegI(xRegI reg) %{
4224 constraint(ALLOC_IN_RC(edx_reg));
4225 match(reg);
4226 match(rRegI);
4227
4228 format %{ "EDX" %}
4229 interface(REG_INTER);
4230 %}
4231
4232 operand eDIRegI(xRegI reg) %{
4233 constraint(ALLOC_IN_RC(edi_reg));
4234 match(reg);
4235 match(rRegI);
4236
4237 format %{ "EDI" %}
4238 interface(REG_INTER);
4239 %}
4240
4241 operand naxRegI() %{
4242 constraint(ALLOC_IN_RC(nax_reg));
4243 match(RegI);
4244 match(eCXRegI);
4245 match(eDXRegI);
4246 match(eSIRegI);
4247 match(eDIRegI);
4248
4249 format %{ %}
4250 interface(REG_INTER);
4251 %}
4252
4253 operand nadxRegI() %{
4254 constraint(ALLOC_IN_RC(nadx_reg));
4255 match(RegI);
4256 match(eBXRegI);
4257 match(eCXRegI);
4258 match(eSIRegI);
4259 match(eDIRegI);
4260
4261 format %{ %}
4262 interface(REG_INTER);
4263 %}
4264
4265 operand ncxRegI() %{
4266 constraint(ALLOC_IN_RC(ncx_reg));
4267 match(RegI);
4268 match(eAXRegI);
4269 match(eDXRegI);
4270 match(eSIRegI);
4271 match(eDIRegI);
4272
4273 format %{ %}
4274 interface(REG_INTER);
4275 %}
4276
4277 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4278 // //
4279 operand eSIRegI(xRegI reg) %{
4280 constraint(ALLOC_IN_RC(esi_reg));
4281 match(reg);
4282 match(rRegI);
4283
4284 format %{ "ESI" %}
4285 interface(REG_INTER);
4286 %}
4287
4288 // Pointer Register
4289 operand anyRegP() %{
4290 constraint(ALLOC_IN_RC(any_reg));
4291 match(RegP);
4292 match(eAXRegP);
4293 match(eBXRegP);
4294 match(eCXRegP);
4295 match(eDIRegP);
4296 match(eRegP);
4297
4298 format %{ %}
4299 interface(REG_INTER);
4300 %}
4301
4302 operand eRegP() %{
4303 constraint(ALLOC_IN_RC(int_reg));
4304 match(RegP);
4305 match(eAXRegP);
4306 match(eBXRegP);
4307 match(eCXRegP);
4308 match(eDIRegP);
4309
4310 format %{ %}
4311 interface(REG_INTER);
4312 %}
4313
4314 // On windows95, EBP is not safe to use for implicit null tests.
4315 operand eRegP_no_EBP() %{
4316 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4317 match(RegP);
4318 match(eAXRegP);
4319 match(eBXRegP);
4320 match(eCXRegP);
4321 match(eDIRegP);
4322
4323 op_cost(100);
4324 format %{ %}
4325 interface(REG_INTER);
4326 %}
4327
4328 operand naxRegP() %{
4329 constraint(ALLOC_IN_RC(nax_reg));
4330 match(RegP);
4331 match(eBXRegP);
4332 match(eDXRegP);
4333 match(eCXRegP);
4334 match(eSIRegP);
4335 match(eDIRegP);
4336
4337 format %{ %}
4338 interface(REG_INTER);
4339 %}
4340
4341 operand nabxRegP() %{
4342 constraint(ALLOC_IN_RC(nabx_reg));
4343 match(RegP);
4344 match(eCXRegP);
4345 match(eDXRegP);
4346 match(eSIRegP);
4347 match(eDIRegP);
4348
4349 format %{ %}
4350 interface(REG_INTER);
4351 %}
4352
4353 operand pRegP() %{
4354 constraint(ALLOC_IN_RC(p_reg));
4355 match(RegP);
4356 match(eBXRegP);
4357 match(eDXRegP);
4358 match(eSIRegP);
4359 match(eDIRegP);
4360
4361 format %{ %}
4362 interface(REG_INTER);
4363 %}
4364
4365 // Special Registers
4366 // Return a pointer value
4367 operand eAXRegP(eRegP reg) %{
4368 constraint(ALLOC_IN_RC(eax_reg));
4369 match(reg);
4370 format %{ "EAX" %}
4371 interface(REG_INTER);
4372 %}
4373
4374 // Used in AtomicAdd
4375 operand eBXRegP(eRegP reg) %{
4376 constraint(ALLOC_IN_RC(ebx_reg));
4377 match(reg);
4378 format %{ "EBX" %}
4379 interface(REG_INTER);
4380 %}
4381
4382 // Tail-call (interprocedural jump) to interpreter
4383 operand eCXRegP(eRegP reg) %{
4384 constraint(ALLOC_IN_RC(ecx_reg));
4385 match(reg);
4386 format %{ "ECX" %}
4387 interface(REG_INTER);
4388 %}
4389
4390 operand eSIRegP(eRegP reg) %{
4391 constraint(ALLOC_IN_RC(esi_reg));
4392 match(reg);
4393 format %{ "ESI" %}
4394 interface(REG_INTER);
4395 %}
4396
4397 // Used in rep stosw
4398 operand eDIRegP(eRegP reg) %{
4399 constraint(ALLOC_IN_RC(edi_reg));
4400 match(reg);
4401 format %{ "EDI" %}
4402 interface(REG_INTER);
4403 %}
4404
4405 operand eBPRegP() %{
4406 constraint(ALLOC_IN_RC(ebp_reg));
4407 match(RegP);
4408 format %{ "EBP" %}
4409 interface(REG_INTER);
4410 %}
4411
4412 operand eRegL() %{
4413 constraint(ALLOC_IN_RC(long_reg));
4414 match(RegL);
4415 match(eADXRegL);
4416
4417 format %{ %}
4418 interface(REG_INTER);
4419 %}
4420
4421 operand eADXRegL( eRegL reg ) %{
4422 constraint(ALLOC_IN_RC(eadx_reg));
4423 match(reg);
4424
4425 format %{ "EDX:EAX" %}
4426 interface(REG_INTER);
4427 %}
4428
4429 operand eBCXRegL( eRegL reg ) %{
4430 constraint(ALLOC_IN_RC(ebcx_reg));
4431 match(reg);
4432
4433 format %{ "EBX:ECX" %}
4434 interface(REG_INTER);
4435 %}
4436
4437 // Special case for integer high multiply
4438 operand eADXRegL_low_only() %{
4439 constraint(ALLOC_IN_RC(eadx_reg));
4440 match(RegL);
4441
4442 format %{ "EAX" %}
4443 interface(REG_INTER);
4444 %}
4445
4446 // Flags register, used as output of compare instructions
4447 operand eFlagsReg() %{
4448 constraint(ALLOC_IN_RC(int_flags));
4449 match(RegFlags);
4450
4451 format %{ "EFLAGS" %}
4452 interface(REG_INTER);
4453 %}
4454
4455 // Flags register, used as output of FLOATING POINT compare instructions
4456 operand eFlagsRegU() %{
4457 constraint(ALLOC_IN_RC(int_flags));
4458 match(RegFlags);
4459
4460 format %{ "EFLAGS_U" %}
4461 interface(REG_INTER);
4462 %}
4463
4464 operand eFlagsRegUCF() %{
4465 constraint(ALLOC_IN_RC(int_flags));
4466 match(RegFlags);
4467 predicate(false);
4468
4469 format %{ "EFLAGS_U_CF" %}
4470 interface(REG_INTER);
4471 %}
4472
4473 // Condition Code Register used by long compare
4474 operand flagsReg_long_LTGE() %{
4475 constraint(ALLOC_IN_RC(int_flags));
4476 match(RegFlags);
4477 format %{ "FLAGS_LTGE" %}
4478 interface(REG_INTER);
4479 %}
4480 operand flagsReg_long_EQNE() %{
4481 constraint(ALLOC_IN_RC(int_flags));
4482 match(RegFlags);
4483 format %{ "FLAGS_EQNE" %}
4484 interface(REG_INTER);
4485 %}
4486 operand flagsReg_long_LEGT() %{
4487 constraint(ALLOC_IN_RC(int_flags));
4488 match(RegFlags);
4489 format %{ "FLAGS_LEGT" %}
4490 interface(REG_INTER);
4491 %}
4492
4493 // Float register operands
4494 operand regDPR() %{
4495 predicate( UseSSE < 2 );
4496 constraint(ALLOC_IN_RC(fp_dbl_reg));
4497 match(RegD);
4498 match(regDPR1);
4499 match(regDPR2);
4500 format %{ %}
4501 interface(REG_INTER);
4502 %}
4503
4504 operand regDPR1(regDPR reg) %{
4505 predicate( UseSSE < 2 );
4506 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4507 match(reg);
4508 format %{ "FPR1" %}
4509 interface(REG_INTER);
4510 %}
4511
4512 operand regDPR2(regDPR reg) %{
4513 predicate( UseSSE < 2 );
4514 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4515 match(reg);
4516 format %{ "FPR2" %}
4517 interface(REG_INTER);
4518 %}
4519
4520 operand regnotDPR1(regDPR reg) %{
4521 predicate( UseSSE < 2 );
4522 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4523 match(reg);
4524 format %{ %}
4525 interface(REG_INTER);
4526 %}
4527
4528 // Float register operands
4529 operand regFPR() %{
4530 predicate( UseSSE < 2 );
4531 constraint(ALLOC_IN_RC(fp_flt_reg));
4532 match(RegF);
4533 match(regFPR1);
4534 format %{ %}
4535 interface(REG_INTER);
4536 %}
4537
4538 // Float register operands
4539 operand regFPR1(regFPR reg) %{
4540 predicate( UseSSE < 2 );
4541 constraint(ALLOC_IN_RC(fp_flt_reg0));
4542 match(reg);
4543 format %{ "FPR1" %}
4544 interface(REG_INTER);
4545 %}
4546
4547 // XMM Float register operands
4548 operand regF() %{
4549 predicate( UseSSE>=1 );
4550 constraint(ALLOC_IN_RC(float_reg));
4551 match(RegF);
4552 format %{ %}
4553 interface(REG_INTER);
4554 %}
4555
4556 // XMM Double register operands
4557 operand regD() %{
4558 predicate( UseSSE>=2 );
4559 constraint(ALLOC_IN_RC(double_reg));
4560 match(RegD);
4561 format %{ %}
4562 interface(REG_INTER);
4563 %}
4564
4565
4566 //----------Memory Operands----------------------------------------------------
4567 // Direct Memory Operand
4568 operand direct(immP addr) %{
4569 match(addr);
4570
4571 format %{ "[$addr]" %}
4572 interface(MEMORY_INTER) %{
4573 base(0xFFFFFFFF);
4574 index(0x4);
4575 scale(0x0);
4576 disp($addr);
4577 %}
4578 %}
4579
4580 // Indirect Memory Operand
4581 operand indirect(eRegP reg) %{
4582 constraint(ALLOC_IN_RC(int_reg));
4583 match(reg);
4584
4585 format %{ "[$reg]" %}
4586 interface(MEMORY_INTER) %{
4587 base($reg);
4588 index(0x4);
4589 scale(0x0);
4590 disp(0x0);
4591 %}
4592 %}
4593
4594 // Indirect Memory Plus Short Offset Operand
4595 operand indOffset8(eRegP reg, immI8 off) %{
4596 match(AddP reg off);
4597
4598 format %{ "[$reg + $off]" %}
4599 interface(MEMORY_INTER) %{
4600 base($reg);
4601 index(0x4);
4602 scale(0x0);
4603 disp($off);
4604 %}
4605 %}
4606
4607 // Indirect Memory Plus Long Offset Operand
4608 operand indOffset32(eRegP reg, immI off) %{
4609 match(AddP reg off);
4610
4611 format %{ "[$reg + $off]" %}
4612 interface(MEMORY_INTER) %{
4613 base($reg);
4614 index(0x4);
4615 scale(0x0);
4616 disp($off);
4617 %}
4618 %}
4619
4620 // Indirect Memory Plus Long Offset Operand
4621 operand indOffset32X(rRegI reg, immP off) %{
4622 match(AddP off reg);
4623
4624 format %{ "[$reg + $off]" %}
4625 interface(MEMORY_INTER) %{
4626 base($reg);
4627 index(0x4);
4628 scale(0x0);
4629 disp($off);
4630 %}
4631 %}
4632
4633 // Indirect Memory Plus Index Register Plus Offset Operand
4634 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4635 match(AddP (AddP reg ireg) off);
4636
4637 op_cost(10);
4638 format %{"[$reg + $off + $ireg]" %}
4639 interface(MEMORY_INTER) %{
4640 base($reg);
4641 index($ireg);
4642 scale(0x0);
4643 disp($off);
4644 %}
4645 %}
4646
4647 // Indirect Memory Plus Index Register Plus Offset Operand
4648 operand indIndex(eRegP reg, rRegI ireg) %{
4649 match(AddP reg ireg);
4650
4651 op_cost(10);
4652 format %{"[$reg + $ireg]" %}
4653 interface(MEMORY_INTER) %{
4654 base($reg);
4655 index($ireg);
4656 scale(0x0);
4657 disp(0x0);
4658 %}
4659 %}
4660
4661 // // -------------------------------------------------------------------------
4662 // // 486 architecture doesn't support "scale * index + offset" with out a base
4663 // // -------------------------------------------------------------------------
4664 // // Scaled Memory Operands
4665 // // Indirect Memory Times Scale Plus Offset Operand
4666 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4667 // match(AddP off (LShiftI ireg scale));
4668 //
4669 // op_cost(10);
4670 // format %{"[$off + $ireg << $scale]" %}
4671 // interface(MEMORY_INTER) %{
4672 // base(0x4);
4673 // index($ireg);
4674 // scale($scale);
4675 // disp($off);
4676 // %}
4677 // %}
4678
4679 // Indirect Memory Times Scale Plus Index Register
4680 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4681 match(AddP reg (LShiftI ireg scale));
4682
4683 op_cost(10);
4684 format %{"[$reg + $ireg << $scale]" %}
4685 interface(MEMORY_INTER) %{
4686 base($reg);
4687 index($ireg);
4688 scale($scale);
4689 disp(0x0);
4690 %}
4691 %}
4692
4693 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4694 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4695 match(AddP (AddP reg (LShiftI ireg scale)) off);
4696
4697 op_cost(10);
4698 format %{"[$reg + $off + $ireg << $scale]" %}
4699 interface(MEMORY_INTER) %{
4700 base($reg);
4701 index($ireg);
4702 scale($scale);
4703 disp($off);
4704 %}
4705 %}
4706
4707 //----------Load Long Memory Operands------------------------------------------
4708 // The load-long idiom will use it's address expression again after loading
4709 // the first word of the long. If the load-long destination overlaps with
4710 // registers used in the addressing expression, the 2nd half will be loaded
4711 // from a clobbered address. Fix this by requiring that load-long use
4712 // address registers that do not overlap with the load-long target.
4713
4714 // load-long support
4715 operand load_long_RegP() %{
4716 constraint(ALLOC_IN_RC(esi_reg));
4717 match(RegP);
4718 match(eSIRegP);
4719 op_cost(100);
4720 format %{ %}
4721 interface(REG_INTER);
4722 %}
4723
4724 // Indirect Memory Operand Long
4725 operand load_long_indirect(load_long_RegP reg) %{
4726 constraint(ALLOC_IN_RC(esi_reg));
4727 match(reg);
4728
4729 format %{ "[$reg]" %}
4730 interface(MEMORY_INTER) %{
4731 base($reg);
4732 index(0x4);
4733 scale(0x0);
4734 disp(0x0);
4735 %}
4736 %}
4737
4738 // Indirect Memory Plus Long Offset Operand
4739 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4740 match(AddP reg off);
4741
4742 format %{ "[$reg + $off]" %}
4743 interface(MEMORY_INTER) %{
4744 base($reg);
4745 index(0x4);
4746 scale(0x0);
4747 disp($off);
4748 %}
4749 %}
4750
4751 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4752
4753
4754 //----------Special Memory Operands--------------------------------------------
4755 // Stack Slot Operand - This operand is used for loading and storing temporary
4756 // values on the stack where a match requires a value to
4757 // flow through memory.
4758 operand stackSlotP(sRegP reg) %{
4759 constraint(ALLOC_IN_RC(stack_slots));
4760 // No match rule because this operand is only generated in matching
4761 format %{ "[$reg]" %}
4762 interface(MEMORY_INTER) %{
4763 base(0x4); // ESP
4764 index(0x4); // No Index
4765 scale(0x0); // No Scale
4766 disp($reg); // Stack Offset
4767 %}
4768 %}
4769
4770 operand stackSlotI(sRegI reg) %{
4771 constraint(ALLOC_IN_RC(stack_slots));
4772 // No match rule because this operand is only generated in matching
4773 format %{ "[$reg]" %}
4774 interface(MEMORY_INTER) %{
4775 base(0x4); // ESP
4776 index(0x4); // No Index
4777 scale(0x0); // No Scale
4778 disp($reg); // Stack Offset
4779 %}
4780 %}
4781
4782 operand stackSlotF(sRegF reg) %{
4783 constraint(ALLOC_IN_RC(stack_slots));
4784 // No match rule because this operand is only generated in matching
4785 format %{ "[$reg]" %}
4786 interface(MEMORY_INTER) %{
4787 base(0x4); // ESP
4788 index(0x4); // No Index
4789 scale(0x0); // No Scale
4790 disp($reg); // Stack Offset
4791 %}
4792 %}
4793
4794 operand stackSlotD(sRegD reg) %{
4795 constraint(ALLOC_IN_RC(stack_slots));
4796 // No match rule because this operand is only generated in matching
4797 format %{ "[$reg]" %}
4798 interface(MEMORY_INTER) %{
4799 base(0x4); // ESP
4800 index(0x4); // No Index
4801 scale(0x0); // No Scale
4802 disp($reg); // Stack Offset
4803 %}
4804 %}
4805
4806 operand stackSlotL(sRegL reg) %{
4807 constraint(ALLOC_IN_RC(stack_slots));
4808 // No match rule because this operand is only generated in matching
4809 format %{ "[$reg]" %}
4810 interface(MEMORY_INTER) %{
4811 base(0x4); // ESP
4812 index(0x4); // No Index
4813 scale(0x0); // No Scale
4814 disp($reg); // Stack Offset
4815 %}
4816 %}
4817
4818 //----------Memory Operands - Win95 Implicit Null Variants----------------
4819 // Indirect Memory Operand
4820 operand indirect_win95_safe(eRegP_no_EBP reg)
4821 %{
4822 constraint(ALLOC_IN_RC(int_reg));
4823 match(reg);
4824
4825 op_cost(100);
4826 format %{ "[$reg]" %}
4827 interface(MEMORY_INTER) %{
4828 base($reg);
4829 index(0x4);
4830 scale(0x0);
4831 disp(0x0);
4832 %}
4833 %}
4834
4835 // Indirect Memory Plus Short Offset Operand
4836 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4837 %{
4838 match(AddP reg off);
4839
4840 op_cost(100);
4841 format %{ "[$reg + $off]" %}
4842 interface(MEMORY_INTER) %{
4843 base($reg);
4844 index(0x4);
4845 scale(0x0);
4846 disp($off);
4847 %}
4848 %}
4849
4850 // Indirect Memory Plus Long Offset Operand
4851 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4852 %{
4853 match(AddP reg off);
4854
4855 op_cost(100);
4856 format %{ "[$reg + $off]" %}
4857 interface(MEMORY_INTER) %{
4858 base($reg);
4859 index(0x4);
4860 scale(0x0);
4861 disp($off);
4862 %}
4863 %}
4864
4865 // Indirect Memory Plus Index Register Plus Offset Operand
4866 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4867 %{
4868 match(AddP (AddP reg ireg) off);
4869
4870 op_cost(100);
4871 format %{"[$reg + $off + $ireg]" %}
4872 interface(MEMORY_INTER) %{
4873 base($reg);
4874 index($ireg);
4875 scale(0x0);
4876 disp($off);
4877 %}
4878 %}
4879
4880 // Indirect Memory Times Scale Plus Index Register
4881 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4882 %{
4883 match(AddP reg (LShiftI ireg scale));
4884
4885 op_cost(100);
4886 format %{"[$reg + $ireg << $scale]" %}
4887 interface(MEMORY_INTER) %{
4888 base($reg);
4889 index($ireg);
4890 scale($scale);
4891 disp(0x0);
4892 %}
4893 %}
4894
4895 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4896 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4897 %{
4898 match(AddP (AddP reg (LShiftI ireg scale)) off);
4899
4900 op_cost(100);
4901 format %{"[$reg + $off + $ireg << $scale]" %}
4902 interface(MEMORY_INTER) %{
4903 base($reg);
4904 index($ireg);
4905 scale($scale);
4906 disp($off);
4907 %}
4908 %}
4909
4910 //----------Conditional Branch Operands----------------------------------------
4911 // Comparison Op - This is the operation of the comparison, and is limited to
4912 // the following set of codes:
4913 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4914 //
4915 // Other attributes of the comparison, such as unsignedness, are specified
4916 // by the comparison instruction that sets a condition code flags register.
4917 // That result is represented by a flags operand whose subtype is appropriate
4918 // to the unsignedness (etc.) of the comparison.
4919 //
4920 // Later, the instruction which matches both the Comparison Op (a Bool) and
4921 // the flags (produced by the Cmp) specifies the coding of the comparison op
4922 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4923
4924 // Comparision Code
4925 operand cmpOp() %{
4926 match(Bool);
4927
4928 format %{ "" %}
4929 interface(COND_INTER) %{
4930 equal(0x4, "e");
4931 not_equal(0x5, "ne");
4932 less(0xC, "l");
4933 greater_equal(0xD, "ge");
4934 less_equal(0xE, "le");
4935 greater(0xF, "g");
4936 overflow(0x0, "o");
4937 no_overflow(0x1, "no");
4938 %}
4939 %}
4940
4941 // Comparison Code, unsigned compare. Used by FP also, with
4942 // C2 (unordered) turned into GT or LT already. The other bits
4943 // C0 and C3 are turned into Carry & Zero flags.
4944 operand cmpOpU() %{
4945 match(Bool);
4946
4947 format %{ "" %}
4948 interface(COND_INTER) %{
4949 equal(0x4, "e");
4950 not_equal(0x5, "ne");
4951 less(0x2, "b");
4952 greater_equal(0x3, "nb");
4953 less_equal(0x6, "be");
4954 greater(0x7, "nbe");
4955 overflow(0x0, "o");
4956 no_overflow(0x1, "no");
4957 %}
4958 %}
4959
4960 // Floating comparisons that don't require any fixup for the unordered case
4961 operand cmpOpUCF() %{
4962 match(Bool);
4963 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4964 n->as_Bool()->_test._test == BoolTest::ge ||
4965 n->as_Bool()->_test._test == BoolTest::le ||
4966 n->as_Bool()->_test._test == BoolTest::gt);
4967 format %{ "" %}
4968 interface(COND_INTER) %{
4969 equal(0x4, "e");
4970 not_equal(0x5, "ne");
4971 less(0x2, "b");
4972 greater_equal(0x3, "nb");
4973 less_equal(0x6, "be");
4974 greater(0x7, "nbe");
4975 overflow(0x0, "o");
4976 no_overflow(0x1, "no");
4977 %}
4978 %}
4979
4980
4981 // Floating comparisons that can be fixed up with extra conditional jumps
4982 operand cmpOpUCF2() %{
4983 match(Bool);
4984 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4985 n->as_Bool()->_test._test == BoolTest::eq);
4986 format %{ "" %}
4987 interface(COND_INTER) %{
4988 equal(0x4, "e");
4989 not_equal(0x5, "ne");
4990 less(0x2, "b");
4991 greater_equal(0x3, "nb");
4992 less_equal(0x6, "be");
4993 greater(0x7, "nbe");
4994 overflow(0x0, "o");
4995 no_overflow(0x1, "no");
4996 %}
4997 %}
4998
4999 // Comparison Code for FP conditional move
5000 operand cmpOp_fcmov() %{
5001 match(Bool);
5002
5003 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5004 n->as_Bool()->_test._test != BoolTest::no_overflow);
5005 format %{ "" %}
5006 interface(COND_INTER) %{
5007 equal (0x0C8);
5008 not_equal (0x1C8);
5009 less (0x0C0);
5010 greater_equal(0x1C0);
5011 less_equal (0x0D0);
5012 greater (0x1D0);
5013 overflow(0x0, "o"); // not really supported by the instruction
5014 no_overflow(0x1, "no"); // not really supported by the instruction
5015 %}
5016 %}
5017
5018 // Comparision Code used in long compares
5019 operand cmpOp_commute() %{
5020 match(Bool);
5021
5022 format %{ "" %}
5023 interface(COND_INTER) %{
5024 equal(0x4, "e");
5025 not_equal(0x5, "ne");
5026 less(0xF, "g");
5027 greater_equal(0xE, "le");
5028 less_equal(0xD, "ge");
5029 greater(0xC, "l");
5030 overflow(0x0, "o");
5031 no_overflow(0x1, "no");
5032 %}
5033 %}
5034
5035 //----------OPERAND CLASSES----------------------------------------------------
5036 // Operand Classes are groups of operands that are used as to simplify
5037 // instruction definitions by not requiring the AD writer to specify separate
5038 // instructions for every form of operand when the instruction accepts
5039 // multiple operand types with the same basic encoding and format. The classic
5040 // case of this is memory operands.
5041
5042 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5043 indIndex, indIndexScale, indIndexScaleOffset);
5044
5045 // Long memory operations are encoded in 2 instructions and a +4 offset.
5046 // This means some kind of offset is always required and you cannot use
5047 // an oop as the offset (done when working on static globals).
5048 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5049 indIndex, indIndexScale, indIndexScaleOffset);
5050
5051
5052 //----------PIPELINE-----------------------------------------------------------
5053 // Rules which define the behavior of the target architectures pipeline.
5054 pipeline %{
5055
5056 //----------ATTRIBUTES---------------------------------------------------------
5057 attributes %{
5058 variable_size_instructions; // Fixed size instructions
5059 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5060 instruction_unit_size = 1; // An instruction is 1 bytes long
5061 instruction_fetch_unit_size = 16; // The processor fetches one line
5062 instruction_fetch_units = 1; // of 16 bytes
5063
5064 // List of nop instructions
5065 nops( MachNop );
5066 %}
5067
5068 //----------RESOURCES----------------------------------------------------------
5069 // Resources are the functional units available to the machine
5070
5071 // Generic P2/P3 pipeline
5072 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5073 // 3 instructions decoded per cycle.
5074 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5075 // 2 ALU op, only ALU0 handles mul/div instructions.
5076 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5077 MS0, MS1, MEM = MS0 | MS1,
5078 BR, FPU,
5079 ALU0, ALU1, ALU = ALU0 | ALU1 );
5080
5081 //----------PIPELINE DESCRIPTION-----------------------------------------------
5082 // Pipeline Description specifies the stages in the machine's pipeline
5083
5084 // Generic P2/P3 pipeline
5085 pipe_desc(S0, S1, S2, S3, S4, S5);
5086
5087 //----------PIPELINE CLASSES---------------------------------------------------
5088 // Pipeline Classes describe the stages in which input and output are
5089 // referenced by the hardware pipeline.
5090
5091 // Naming convention: ialu or fpu
5092 // Then: _reg
5093 // Then: _reg if there is a 2nd register
5094 // Then: _long if it's a pair of instructions implementing a long
5095 // Then: _fat if it requires the big decoder
5096 // Or: _mem if it requires the big decoder and a memory unit.
5097
5098 // Integer ALU reg operation
5099 pipe_class ialu_reg(rRegI dst) %{
5100 single_instruction;
5101 dst : S4(write);
5102 dst : S3(read);
5103 DECODE : S0; // any decoder
5104 ALU : S3; // any alu
5105 %}
5106
5107 // Long ALU reg operation
5108 pipe_class ialu_reg_long(eRegL dst) %{
5109 instruction_count(2);
5110 dst : S4(write);
5111 dst : S3(read);
5112 DECODE : S0(2); // any 2 decoders
5113 ALU : S3(2); // both alus
5114 %}
5115
5116 // Integer ALU reg operation using big decoder
5117 pipe_class ialu_reg_fat(rRegI dst) %{
5118 single_instruction;
5119 dst : S4(write);
5120 dst : S3(read);
5121 D0 : S0; // big decoder only
5122 ALU : S3; // any alu
5123 %}
5124
5125 // Long ALU reg operation using big decoder
5126 pipe_class ialu_reg_long_fat(eRegL dst) %{
5127 instruction_count(2);
5128 dst : S4(write);
5129 dst : S3(read);
5130 D0 : S0(2); // big decoder only; twice
5131 ALU : S3(2); // any 2 alus
5132 %}
5133
5134 // Integer ALU reg-reg operation
5135 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5136 single_instruction;
5137 dst : S4(write);
5138 src : S3(read);
5139 DECODE : S0; // any decoder
5140 ALU : S3; // any alu
5141 %}
5142
5143 // Long ALU reg-reg operation
5144 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5145 instruction_count(2);
5146 dst : S4(write);
5147 src : S3(read);
5148 DECODE : S0(2); // any 2 decoders
5149 ALU : S3(2); // both alus
5150 %}
5151
5152 // Integer ALU reg-reg operation
5153 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5154 single_instruction;
5155 dst : S4(write);
5156 src : S3(read);
5157 D0 : S0; // big decoder only
5158 ALU : S3; // any alu
5159 %}
5160
5161 // Long ALU reg-reg operation
5162 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5163 instruction_count(2);
5164 dst : S4(write);
5165 src : S3(read);
5166 D0 : S0(2); // big decoder only; twice
5167 ALU : S3(2); // both alus
5168 %}
5169
5170 // Integer ALU reg-mem operation
5171 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5172 single_instruction;
5173 dst : S5(write);
5174 mem : S3(read);
5175 D0 : S0; // big decoder only
5176 ALU : S4; // any alu
5177 MEM : S3; // any mem
5178 %}
5179
5180 // Long ALU reg-mem operation
5181 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5182 instruction_count(2);
5183 dst : S5(write);
5184 mem : S3(read);
5185 D0 : S0(2); // big decoder only; twice
5186 ALU : S4(2); // any 2 alus
5187 MEM : S3(2); // both mems
5188 %}
5189
5190 // Integer mem operation (prefetch)
5191 pipe_class ialu_mem(memory mem)
5192 %{
5193 single_instruction;
5194 mem : S3(read);
5195 D0 : S0; // big decoder only
5196 MEM : S3; // any mem
5197 %}
5198
5199 // Integer Store to Memory
5200 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5201 single_instruction;
5202 mem : S3(read);
5203 src : S5(read);
5204 D0 : S0; // big decoder only
5205 ALU : S4; // any alu
5206 MEM : S3;
5207 %}
5208
5209 // Long Store to Memory
5210 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5211 instruction_count(2);
5212 mem : S3(read);
5213 src : S5(read);
5214 D0 : S0(2); // big decoder only; twice
5215 ALU : S4(2); // any 2 alus
5216 MEM : S3(2); // Both mems
5217 %}
5218
5219 // Integer Store to Memory
5220 pipe_class ialu_mem_imm(memory mem) %{
5221 single_instruction;
5222 mem : S3(read);
5223 D0 : S0; // big decoder only
5224 ALU : S4; // any alu
5225 MEM : S3;
5226 %}
5227
5228 // Integer ALU0 reg-reg operation
5229 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5230 single_instruction;
5231 dst : S4(write);
5232 src : S3(read);
5233 D0 : S0; // Big decoder only
5234 ALU0 : S3; // only alu0
5235 %}
5236
5237 // Integer ALU0 reg-mem operation
5238 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5239 single_instruction;
5240 dst : S5(write);
5241 mem : S3(read);
5242 D0 : S0; // big decoder only
5243 ALU0 : S4; // ALU0 only
5244 MEM : S3; // any mem
5245 %}
5246
5247 // Integer ALU reg-reg operation
5248 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5249 single_instruction;
5250 cr : S4(write);
5251 src1 : S3(read);
5252 src2 : S3(read);
5253 DECODE : S0; // any decoder
5254 ALU : S3; // any alu
5255 %}
5256
5257 // Integer ALU reg-imm operation
5258 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5259 single_instruction;
5260 cr : S4(write);
5261 src1 : S3(read);
5262 DECODE : S0; // any decoder
5263 ALU : S3; // any alu
5264 %}
5265
5266 // Integer ALU reg-mem operation
5267 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5268 single_instruction;
5269 cr : S4(write);
5270 src1 : S3(read);
5271 src2 : S3(read);
5272 D0 : S0; // big decoder only
5273 ALU : S4; // any alu
5274 MEM : S3;
5275 %}
5276
5277 // Conditional move reg-reg
5278 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5279 instruction_count(4);
5280 y : S4(read);
5281 q : S3(read);
5282 p : S3(read);
5283 DECODE : S0(4); // any decoder
5284 %}
5285
5286 // Conditional move reg-reg
5287 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5288 single_instruction;
5289 dst : S4(write);
5290 src : S3(read);
5291 cr : S3(read);
5292 DECODE : S0; // any decoder
5293 %}
5294
5295 // Conditional move reg-mem
5296 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5297 single_instruction;
5298 dst : S4(write);
5299 src : S3(read);
5300 cr : S3(read);
5301 DECODE : S0; // any decoder
5302 MEM : S3;
5303 %}
5304
5305 // Conditional move reg-reg long
5306 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5307 single_instruction;
5308 dst : S4(write);
5309 src : S3(read);
5310 cr : S3(read);
5311 DECODE : S0(2); // any 2 decoders
5312 %}
5313
5314 // Conditional move double reg-reg
5315 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5316 single_instruction;
5317 dst : S4(write);
5318 src : S3(read);
5319 cr : S3(read);
5320 DECODE : S0; // any decoder
5321 %}
5322
5323 // Float reg-reg operation
5324 pipe_class fpu_reg(regDPR dst) %{
5325 instruction_count(2);
5326 dst : S3(read);
5327 DECODE : S0(2); // any 2 decoders
5328 FPU : S3;
5329 %}
5330
5331 // Float reg-reg operation
5332 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5333 instruction_count(2);
5334 dst : S4(write);
5335 src : S3(read);
5336 DECODE : S0(2); // any 2 decoders
5337 FPU : S3;
5338 %}
5339
5340 // Float reg-reg operation
5341 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5342 instruction_count(3);
5343 dst : S4(write);
5344 src1 : S3(read);
5345 src2 : S3(read);
5346 DECODE : S0(3); // any 3 decoders
5347 FPU : S3(2);
5348 %}
5349
5350 // Float reg-reg operation
5351 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5352 instruction_count(4);
5353 dst : S4(write);
5354 src1 : S3(read);
5355 src2 : S3(read);
5356 src3 : S3(read);
5357 DECODE : S0(4); // any 3 decoders
5358 FPU : S3(2);
5359 %}
5360
5361 // Float reg-reg operation
5362 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5363 instruction_count(4);
5364 dst : S4(write);
5365 src1 : S3(read);
5366 src2 : S3(read);
5367 src3 : S3(read);
5368 DECODE : S1(3); // any 3 decoders
5369 D0 : S0; // Big decoder only
5370 FPU : S3(2);
5371 MEM : S3;
5372 %}
5373
5374 // Float reg-mem operation
5375 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5376 instruction_count(2);
5377 dst : S5(write);
5378 mem : S3(read);
5379 D0 : S0; // big decoder only
5380 DECODE : S1; // any decoder for FPU POP
5381 FPU : S4;
5382 MEM : S3; // any mem
5383 %}
5384
5385 // Float reg-mem operation
5386 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5387 instruction_count(3);
5388 dst : S5(write);
5389 src1 : S3(read);
5390 mem : S3(read);
5391 D0 : S0; // big decoder only
5392 DECODE : S1(2); // any decoder for FPU POP
5393 FPU : S4;
5394 MEM : S3; // any mem
5395 %}
5396
5397 // Float mem-reg operation
5398 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5399 instruction_count(2);
5400 src : S5(read);
5401 mem : S3(read);
5402 DECODE : S0; // any decoder for FPU PUSH
5403 D0 : S1; // big decoder only
5404 FPU : S4;
5405 MEM : S3; // any mem
5406 %}
5407
5408 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5409 instruction_count(3);
5410 src1 : S3(read);
5411 src2 : S3(read);
5412 mem : S3(read);
5413 DECODE : S0(2); // any decoder for FPU PUSH
5414 D0 : S1; // big decoder only
5415 FPU : S4;
5416 MEM : S3; // any mem
5417 %}
5418
5419 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5420 instruction_count(3);
5421 src1 : S3(read);
5422 src2 : S3(read);
5423 mem : S4(read);
5424 DECODE : S0; // any decoder for FPU PUSH
5425 D0 : S0(2); // big decoder only
5426 FPU : S4;
5427 MEM : S3(2); // any mem
5428 %}
5429
5430 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5431 instruction_count(2);
5432 src1 : S3(read);
5433 dst : S4(read);
5434 D0 : S0(2); // big decoder only
5435 MEM : S3(2); // any mem
5436 %}
5437
5438 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5439 instruction_count(3);
5440 src1 : S3(read);
5441 src2 : S3(read);
5442 dst : S4(read);
5443 D0 : S0(3); // big decoder only
5444 FPU : S4;
5445 MEM : S3(3); // any mem
5446 %}
5447
5448 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5449 instruction_count(3);
5450 src1 : S4(read);
5451 mem : S4(read);
5452 DECODE : S0; // any decoder for FPU PUSH
5453 D0 : S0(2); // big decoder only
5454 FPU : S4;
5455 MEM : S3(2); // any mem
5456 %}
5457
5458 // Float load constant
5459 pipe_class fpu_reg_con(regDPR dst) %{
5460 instruction_count(2);
5461 dst : S5(write);
5462 D0 : S0; // big decoder only for the load
5463 DECODE : S1; // any decoder for FPU POP
5464 FPU : S4;
5465 MEM : S3; // any mem
5466 %}
5467
5468 // Float load constant
5469 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5470 instruction_count(3);
5471 dst : S5(write);
5472 src : S3(read);
5473 D0 : S0; // big decoder only for the load
5474 DECODE : S1(2); // any decoder for FPU POP
5475 FPU : S4;
5476 MEM : S3; // any mem
5477 %}
5478
5479 // UnConditional branch
5480 pipe_class pipe_jmp( label labl ) %{
5481 single_instruction;
5482 BR : S3;
5483 %}
5484
5485 // Conditional branch
5486 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5487 single_instruction;
5488 cr : S1(read);
5489 BR : S3;
5490 %}
5491
5492 // Allocation idiom
5493 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5494 instruction_count(1); force_serialization;
5495 fixed_latency(6);
5496 heap_ptr : S3(read);
5497 DECODE : S0(3);
5498 D0 : S2;
5499 MEM : S3;
5500 ALU : S3(2);
5501 dst : S5(write);
5502 BR : S5;
5503 %}
5504
5505 // Generic big/slow expanded idiom
5506 pipe_class pipe_slow( ) %{
5507 instruction_count(10); multiple_bundles; force_serialization;
5508 fixed_latency(100);
5509 D0 : S0(2);
5510 MEM : S3(2);
5511 %}
5512
5513 // The real do-nothing guy
5514 pipe_class empty( ) %{
5515 instruction_count(0);
5516 %}
5517
5518 // Define the class for the Nop node
5519 define %{
5520 MachNop = empty;
5521 %}
5522
5523 %}
5524
5525 //----------INSTRUCTIONS-------------------------------------------------------
5526 //
5527 // match -- States which machine-independent subtree may be replaced
5528 // by this instruction.
5529 // ins_cost -- The estimated cost of this instruction is used by instruction
5530 // selection to identify a minimum cost tree of machine
5531 // instructions that matches a tree of machine-independent
5532 // instructions.
5533 // format -- A string providing the disassembly for this instruction.
5534 // The value of an instruction's operand may be inserted
5535 // by referring to it with a '$' prefix.
5536 // opcode -- Three instruction opcodes may be provided. These are referred
5537 // to within an encode class as $primary, $secondary, and $tertiary
5538 // respectively. The primary opcode is commonly used to
5539 // indicate the type of machine instruction, while secondary
5540 // and tertiary are often used for prefix options or addressing
5541 // modes.
5542 // ins_encode -- A list of encode classes with parameters. The encode class
5543 // name must have been defined in an 'enc_class' specification
5544 // in the encode section of the architecture description.
5545
5546 //----------BSWAP-Instruction--------------------------------------------------
5547 instruct bytes_reverse_int(rRegI dst) %{
5548 match(Set dst (ReverseBytesI dst));
5549
5550 format %{ "BSWAP $dst" %}
5551 opcode(0x0F, 0xC8);
5552 ins_encode( OpcP, OpcSReg(dst) );
5553 ins_pipe( ialu_reg );
5554 %}
5555
5556 instruct bytes_reverse_long(eRegL dst) %{
5557 match(Set dst (ReverseBytesL dst));
5558
5559 format %{ "BSWAP $dst.lo\n\t"
5560 "BSWAP $dst.hi\n\t"
5561 "XCHG $dst.lo $dst.hi" %}
5562
5563 ins_cost(125);
5564 ins_encode( bswap_long_bytes(dst) );
5565 ins_pipe( ialu_reg_reg);
5566 %}
5567
5568 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5569 match(Set dst (ReverseBytesUS dst));
5570 effect(KILL cr);
5571
5572 format %{ "BSWAP $dst\n\t"
5573 "SHR $dst,16\n\t" %}
5574 ins_encode %{
5575 __ bswapl($dst$$Register);
5576 __ shrl($dst$$Register, 16);
5577 %}
5578 ins_pipe( ialu_reg );
5579 %}
5580
5581 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5582 match(Set dst (ReverseBytesS dst));
5583 effect(KILL cr);
5584
5585 format %{ "BSWAP $dst\n\t"
5586 "SAR $dst,16\n\t" %}
5587 ins_encode %{
5588 __ bswapl($dst$$Register);
5589 __ sarl($dst$$Register, 16);
5590 %}
5591 ins_pipe( ialu_reg );
5592 %}
5593
5594
5595 //---------- Zeros Count Instructions ------------------------------------------
5596
5597 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5598 predicate(UseCountLeadingZerosInstruction);
5599 match(Set dst (CountLeadingZerosI src));
5600 effect(KILL cr);
5601
5602 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5603 ins_encode %{
5604 __ lzcntl($dst$$Register, $src$$Register);
5605 %}
5606 ins_pipe(ialu_reg);
5607 %}
5608
5609 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5610 predicate(!UseCountLeadingZerosInstruction);
5611 match(Set dst (CountLeadingZerosI src));
5612 effect(KILL cr);
5613
5614 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5615 "JNZ skip\n\t"
5616 "MOV $dst, -1\n"
5617 "skip:\n\t"
5618 "NEG $dst\n\t"
5619 "ADD $dst, 31" %}
5620 ins_encode %{
5621 Register Rdst = $dst$$Register;
5622 Register Rsrc = $src$$Register;
5623 Label skip;
5624 __ bsrl(Rdst, Rsrc);
5625 __ jccb(Assembler::notZero, skip);
5626 __ movl(Rdst, -1);
5627 __ bind(skip);
5628 __ negl(Rdst);
5629 __ addl(Rdst, BitsPerInt - 1);
5630 %}
5631 ins_pipe(ialu_reg);
5632 %}
5633
5634 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5635 predicate(UseCountLeadingZerosInstruction);
5636 match(Set dst (CountLeadingZerosL src));
5637 effect(TEMP dst, KILL cr);
5638
5639 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5640 "JNC done\n\t"
5641 "LZCNT $dst, $src.lo\n\t"
5642 "ADD $dst, 32\n"
5643 "done:" %}
5644 ins_encode %{
5645 Register Rdst = $dst$$Register;
5646 Register Rsrc = $src$$Register;
5647 Label done;
5648 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5649 __ jccb(Assembler::carryClear, done);
5650 __ lzcntl(Rdst, Rsrc);
5651 __ addl(Rdst, BitsPerInt);
5652 __ bind(done);
5653 %}
5654 ins_pipe(ialu_reg);
5655 %}
5656
5657 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5658 predicate(!UseCountLeadingZerosInstruction);
5659 match(Set dst (CountLeadingZerosL src));
5660 effect(TEMP dst, KILL cr);
5661
5662 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5663 "JZ msw_is_zero\n\t"
5664 "ADD $dst, 32\n\t"
5665 "JMP not_zero\n"
5666 "msw_is_zero:\n\t"
5667 "BSR $dst, $src.lo\n\t"
5668 "JNZ not_zero\n\t"
5669 "MOV $dst, -1\n"
5670 "not_zero:\n\t"
5671 "NEG $dst\n\t"
5672 "ADD $dst, 63\n" %}
5673 ins_encode %{
5674 Register Rdst = $dst$$Register;
5675 Register Rsrc = $src$$Register;
5676 Label msw_is_zero;
5677 Label not_zero;
5678 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5679 __ jccb(Assembler::zero, msw_is_zero);
5680 __ addl(Rdst, BitsPerInt);
5681 __ jmpb(not_zero);
5682 __ bind(msw_is_zero);
5683 __ bsrl(Rdst, Rsrc);
5684 __ jccb(Assembler::notZero, not_zero);
5685 __ movl(Rdst, -1);
5686 __ bind(not_zero);
5687 __ negl(Rdst);
5688 __ addl(Rdst, BitsPerLong - 1);
5689 %}
5690 ins_pipe(ialu_reg);
5691 %}
5692
5693 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5694 match(Set dst (CountTrailingZerosI src));
5695 effect(KILL cr);
5696
5697 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5698 "JNZ done\n\t"
5699 "MOV $dst, 32\n"
5700 "done:" %}
5701 ins_encode %{
5702 Register Rdst = $dst$$Register;
5703 Label done;
5704 __ bsfl(Rdst, $src$$Register);
5705 __ jccb(Assembler::notZero, done);
5706 __ movl(Rdst, BitsPerInt);
5707 __ bind(done);
5708 %}
5709 ins_pipe(ialu_reg);
5710 %}
5711
5712 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5713 match(Set dst (CountTrailingZerosL src));
5714 effect(TEMP dst, KILL cr);
5715
5716 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5717 "JNZ done\n\t"
5718 "BSF $dst, $src.hi\n\t"
5719 "JNZ msw_not_zero\n\t"
5720 "MOV $dst, 32\n"
5721 "msw_not_zero:\n\t"
5722 "ADD $dst, 32\n"
5723 "done:" %}
5724 ins_encode %{
5725 Register Rdst = $dst$$Register;
5726 Register Rsrc = $src$$Register;
5727 Label msw_not_zero;
5728 Label done;
5729 __ bsfl(Rdst, Rsrc);
5730 __ jccb(Assembler::notZero, done);
5731 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5732 __ jccb(Assembler::notZero, msw_not_zero);
5733 __ movl(Rdst, BitsPerInt);
5734 __ bind(msw_not_zero);
5735 __ addl(Rdst, BitsPerInt);
5736 __ bind(done);
5737 %}
5738 ins_pipe(ialu_reg);
5739 %}
5740
5741
5742 //---------- Population Count Instructions -------------------------------------
5743
5744 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5745 predicate(UsePopCountInstruction);
5746 match(Set dst (PopCountI src));
5747 effect(KILL cr);
5748
5749 format %{ "POPCNT $dst, $src" %}
5750 ins_encode %{
5751 __ popcntl($dst$$Register, $src$$Register);
5752 %}
5753 ins_pipe(ialu_reg);
5754 %}
5755
5756 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5757 predicate(UsePopCountInstruction);
5758 match(Set dst (PopCountI (LoadI mem)));
5759 effect(KILL cr);
5760
5761 format %{ "POPCNT $dst, $mem" %}
5762 ins_encode %{
5763 __ popcntl($dst$$Register, $mem$$Address);
5764 %}
5765 ins_pipe(ialu_reg);
5766 %}
5767
5768 // Note: Long.bitCount(long) returns an int.
5769 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5770 predicate(UsePopCountInstruction);
5771 match(Set dst (PopCountL src));
5772 effect(KILL cr, TEMP tmp, TEMP dst);
5773
5774 format %{ "POPCNT $dst, $src.lo\n\t"
5775 "POPCNT $tmp, $src.hi\n\t"
5776 "ADD $dst, $tmp" %}
5777 ins_encode %{
5778 __ popcntl($dst$$Register, $src$$Register);
5779 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5780 __ addl($dst$$Register, $tmp$$Register);
5781 %}
5782 ins_pipe(ialu_reg);
5783 %}
5784
5785 // Note: Long.bitCount(long) returns an int.
5786 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5787 predicate(UsePopCountInstruction);
5788 match(Set dst (PopCountL (LoadL mem)));
5789 effect(KILL cr, TEMP tmp, TEMP dst);
5790
5791 format %{ "POPCNT $dst, $mem\n\t"
5792 "POPCNT $tmp, $mem+4\n\t"
5793 "ADD $dst, $tmp" %}
5794 ins_encode %{
5795 //__ popcntl($dst$$Register, $mem$$Address$$first);
5796 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5797 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5798 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5799 __ addl($dst$$Register, $tmp$$Register);
5800 %}
5801 ins_pipe(ialu_reg);
5802 %}
5803
5804
5805 //----------Load/Store/Move Instructions---------------------------------------
5806 //----------Load Instructions--------------------------------------------------
5807 // Load Byte (8bit signed)
5808 instruct loadB(xRegI dst, memory mem) %{
5809 match(Set dst (LoadB mem));
5810
5811 ins_cost(125);
5812 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5813
5814 ins_encode %{
5815 __ movsbl($dst$$Register, $mem$$Address);
5816 %}
5817
5818 ins_pipe(ialu_reg_mem);
5819 %}
5820
5821 // Load Byte (8bit signed) into Long Register
5822 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5823 match(Set dst (ConvI2L (LoadB mem)));
5824 effect(KILL cr);
5825
5826 ins_cost(375);
5827 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5828 "MOV $dst.hi,$dst.lo\n\t"
5829 "SAR $dst.hi,7" %}
5830
5831 ins_encode %{
5832 __ movsbl($dst$$Register, $mem$$Address);
5833 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5834 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5835 %}
5836
5837 ins_pipe(ialu_reg_mem);
5838 %}
5839
5840 // Load Unsigned Byte (8bit UNsigned)
5841 instruct loadUB(xRegI dst, memory mem) %{
5842 match(Set dst (LoadUB mem));
5843
5844 ins_cost(125);
5845 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5846
5847 ins_encode %{
5848 __ movzbl($dst$$Register, $mem$$Address);
5849 %}
5850
5851 ins_pipe(ialu_reg_mem);
5852 %}
5853
5854 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5855 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5856 match(Set dst (ConvI2L (LoadUB mem)));
5857 effect(KILL cr);
5858
5859 ins_cost(250);
5860 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5861 "XOR $dst.hi,$dst.hi" %}
5862
5863 ins_encode %{
5864 Register Rdst = $dst$$Register;
5865 __ movzbl(Rdst, $mem$$Address);
5866 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5867 %}
5868
5869 ins_pipe(ialu_reg_mem);
5870 %}
5871
5872 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5873 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5874 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5875 effect(KILL cr);
5876
5877 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5878 "XOR $dst.hi,$dst.hi\n\t"
5879 "AND $dst.lo,$mask" %}
5880 ins_encode %{
5881 Register Rdst = $dst$$Register;
5882 __ movzbl(Rdst, $mem$$Address);
5883 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5884 __ andl(Rdst, $mask$$constant);
5885 %}
5886 ins_pipe(ialu_reg_mem);
5887 %}
5888
5889 // Load Short (16bit signed)
5890 instruct loadS(rRegI dst, memory mem) %{
5891 match(Set dst (LoadS mem));
5892
5893 ins_cost(125);
5894 format %{ "MOVSX $dst,$mem\t# short" %}
5895
5896 ins_encode %{
5897 __ movswl($dst$$Register, $mem$$Address);
5898 %}
5899
5900 ins_pipe(ialu_reg_mem);
5901 %}
5902
5903 // Load Short (16 bit signed) to Byte (8 bit signed)
5904 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5905 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5906
5907 ins_cost(125);
5908 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5909 ins_encode %{
5910 __ movsbl($dst$$Register, $mem$$Address);
5911 %}
5912 ins_pipe(ialu_reg_mem);
5913 %}
5914
5915 // Load Short (16bit signed) into Long Register
5916 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5917 match(Set dst (ConvI2L (LoadS mem)));
5918 effect(KILL cr);
5919
5920 ins_cost(375);
5921 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5922 "MOV $dst.hi,$dst.lo\n\t"
5923 "SAR $dst.hi,15" %}
5924
5925 ins_encode %{
5926 __ movswl($dst$$Register, $mem$$Address);
5927 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5928 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5929 %}
5930
5931 ins_pipe(ialu_reg_mem);
5932 %}
5933
5934 // Load Unsigned Short/Char (16bit unsigned)
5935 instruct loadUS(rRegI dst, memory mem) %{
5936 match(Set dst (LoadUS mem));
5937
5938 ins_cost(125);
5939 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5940
5941 ins_encode %{
5942 __ movzwl($dst$$Register, $mem$$Address);
5943 %}
5944
5945 ins_pipe(ialu_reg_mem);
5946 %}
5947
5948 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5949 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5950 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5951
5952 ins_cost(125);
5953 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5954 ins_encode %{
5955 __ movsbl($dst$$Register, $mem$$Address);
5956 %}
5957 ins_pipe(ialu_reg_mem);
5958 %}
5959
5960 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5961 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5962 match(Set dst (ConvI2L (LoadUS mem)));
5963 effect(KILL cr);
5964
5965 ins_cost(250);
5966 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5967 "XOR $dst.hi,$dst.hi" %}
5968
5969 ins_encode %{
5970 __ movzwl($dst$$Register, $mem$$Address);
5971 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5972 %}
5973
5974 ins_pipe(ialu_reg_mem);
5975 %}
5976
5977 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5978 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5979 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5980 effect(KILL cr);
5981
5982 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5983 "XOR $dst.hi,$dst.hi" %}
5984 ins_encode %{
5985 Register Rdst = $dst$$Register;
5986 __ movzbl(Rdst, $mem$$Address);
5987 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5988 %}
5989 ins_pipe(ialu_reg_mem);
5990 %}
5991
5992 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5993 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5994 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5995 effect(KILL cr);
5996
5997 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5998 "XOR $dst.hi,$dst.hi\n\t"
5999 "AND $dst.lo,$mask" %}
6000 ins_encode %{
6001 Register Rdst = $dst$$Register;
6002 __ movzwl(Rdst, $mem$$Address);
6003 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6004 __ andl(Rdst, $mask$$constant);
6005 %}
6006 ins_pipe(ialu_reg_mem);
6007 %}
6008
6009 // Load Integer
6010 instruct loadI(rRegI dst, memory mem) %{
6011 match(Set dst (LoadI mem));
6012
6013 ins_cost(125);
6014 format %{ "MOV $dst,$mem\t# int" %}
6015
6016 ins_encode %{
6017 __ movl($dst$$Register, $mem$$Address);
6018 %}
6019
6020 ins_pipe(ialu_reg_mem);
6021 %}
6022
6023 // Load Integer (32 bit signed) to Byte (8 bit signed)
6024 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6025 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6026
6027 ins_cost(125);
6028 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6029 ins_encode %{
6030 __ movsbl($dst$$Register, $mem$$Address);
6031 %}
6032 ins_pipe(ialu_reg_mem);
6033 %}
6034
6035 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6036 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6037 match(Set dst (AndI (LoadI mem) mask));
6038
6039 ins_cost(125);
6040 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6041 ins_encode %{
6042 __ movzbl($dst$$Register, $mem$$Address);
6043 %}
6044 ins_pipe(ialu_reg_mem);
6045 %}
6046
6047 // Load Integer (32 bit signed) to Short (16 bit signed)
6048 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6049 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6050
6051 ins_cost(125);
6052 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6053 ins_encode %{
6054 __ movswl($dst$$Register, $mem$$Address);
6055 %}
6056 ins_pipe(ialu_reg_mem);
6057 %}
6058
6059 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6060 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6061 match(Set dst (AndI (LoadI mem) mask));
6062
6063 ins_cost(125);
6064 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6065 ins_encode %{
6066 __ movzwl($dst$$Register, $mem$$Address);
6067 %}
6068 ins_pipe(ialu_reg_mem);
6069 %}
6070
6071 // Load Integer into Long Register
6072 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6073 match(Set dst (ConvI2L (LoadI mem)));
6074 effect(KILL cr);
6075
6076 ins_cost(375);
6077 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6078 "MOV $dst.hi,$dst.lo\n\t"
6079 "SAR $dst.hi,31" %}
6080
6081 ins_encode %{
6082 __ movl($dst$$Register, $mem$$Address);
6083 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6084 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6085 %}
6086
6087 ins_pipe(ialu_reg_mem);
6088 %}
6089
6090 // Load Integer with mask 0xFF into Long Register
6091 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6092 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6093 effect(KILL cr);
6094
6095 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6096 "XOR $dst.hi,$dst.hi" %}
6097 ins_encode %{
6098 Register Rdst = $dst$$Register;
6099 __ movzbl(Rdst, $mem$$Address);
6100 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6101 %}
6102 ins_pipe(ialu_reg_mem);
6103 %}
6104
6105 // Load Integer with mask 0xFFFF into Long Register
6106 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6107 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6108 effect(KILL cr);
6109
6110 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6111 "XOR $dst.hi,$dst.hi" %}
6112 ins_encode %{
6113 Register Rdst = $dst$$Register;
6114 __ movzwl(Rdst, $mem$$Address);
6115 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6116 %}
6117 ins_pipe(ialu_reg_mem);
6118 %}
6119
6120 // Load Integer with 31-bit mask into Long Register
6121 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6122 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6123 effect(KILL cr);
6124
6125 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6126 "XOR $dst.hi,$dst.hi\n\t"
6127 "AND $dst.lo,$mask" %}
6128 ins_encode %{
6129 Register Rdst = $dst$$Register;
6130 __ movl(Rdst, $mem$$Address);
6131 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6132 __ andl(Rdst, $mask$$constant);
6133 %}
6134 ins_pipe(ialu_reg_mem);
6135 %}
6136
6137 // Load Unsigned Integer into Long Register
6138 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6139 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6140 effect(KILL cr);
6141
6142 ins_cost(250);
6143 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6144 "XOR $dst.hi,$dst.hi" %}
6145
6146 ins_encode %{
6147 __ movl($dst$$Register, $mem$$Address);
6148 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6149 %}
6150
6151 ins_pipe(ialu_reg_mem);
6152 %}
6153
6154 // Load Long. Cannot clobber address while loading, so restrict address
6155 // register to ESI
6156 instruct loadL(eRegL dst, load_long_memory mem) %{
6157 predicate(!((LoadLNode*)n)->require_atomic_access());
6158 match(Set dst (LoadL mem));
6159
6160 ins_cost(250);
6161 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6162 "MOV $dst.hi,$mem+4" %}
6163
6164 ins_encode %{
6165 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6166 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6167 __ movl($dst$$Register, Amemlo);
6168 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6169 %}
6170
6171 ins_pipe(ialu_reg_long_mem);
6172 %}
6173
6174 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6175 // then store it down to the stack and reload on the int
6176 // side.
6177 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6178 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6179 match(Set dst (LoadL mem));
6180
6181 ins_cost(200);
6182 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6183 "FISTp $dst" %}
6184 ins_encode(enc_loadL_volatile(mem,dst));
6185 ins_pipe( fpu_reg_mem );
6186 %}
6187
6188 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6189 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6190 match(Set dst (LoadL mem));
6191 effect(TEMP tmp);
6192 ins_cost(180);
6193 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6194 "MOVSD $dst,$tmp" %}
6195 ins_encode %{
6196 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6197 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6198 %}
6199 ins_pipe( pipe_slow );
6200 %}
6201
6202 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6203 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6204 match(Set dst (LoadL mem));
6205 effect(TEMP tmp);
6206 ins_cost(160);
6207 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6208 "MOVD $dst.lo,$tmp\n\t"
6209 "PSRLQ $tmp,32\n\t"
6210 "MOVD $dst.hi,$tmp" %}
6211 ins_encode %{
6212 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6213 __ movdl($dst$$Register, $tmp$$XMMRegister);
6214 __ psrlq($tmp$$XMMRegister, 32);
6215 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6216 %}
6217 ins_pipe( pipe_slow );
6218 %}
6219
6220 // Load Range
6221 instruct loadRange(rRegI dst, memory mem) %{
6222 match(Set dst (LoadRange mem));
6223
6224 ins_cost(125);
6225 format %{ "MOV $dst,$mem" %}
6226 opcode(0x8B);
6227 ins_encode( OpcP, RegMem(dst,mem));
6228 ins_pipe( ialu_reg_mem );
6229 %}
6230
6231
6232 // Load Pointer
6233 instruct loadP(eRegP dst, memory mem) %{
6234 match(Set dst (LoadP mem));
6235
6236 ins_cost(125);
6237 format %{ "MOV $dst,$mem" %}
6238 opcode(0x8B);
6239 ins_encode( OpcP, RegMem(dst,mem));
6240 ins_pipe( ialu_reg_mem );
6241 %}
6242
6243 // Load Klass Pointer
6244 instruct loadKlass(eRegP dst, memory mem) %{
6245 match(Set dst (LoadKlass mem));
6246
6247 ins_cost(125);
6248 format %{ "MOV $dst,$mem" %}
6249 opcode(0x8B);
6250 ins_encode( OpcP, RegMem(dst,mem));
6251 ins_pipe( ialu_reg_mem );
6252 %}
6253
6254 // Load Double
6255 instruct loadDPR(regDPR dst, memory mem) %{
6256 predicate(UseSSE<=1);
6257 match(Set dst (LoadD mem));
6258
6259 ins_cost(150);
6260 format %{ "FLD_D ST,$mem\n\t"
6261 "FSTP $dst" %}
6262 opcode(0xDD); /* DD /0 */
6263 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6264 Pop_Reg_DPR(dst) );
6265 ins_pipe( fpu_reg_mem );
6266 %}
6267
6268 // Load Double to XMM
6269 instruct loadD(regD dst, memory mem) %{
6270 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6271 match(Set dst (LoadD mem));
6272 ins_cost(145);
6273 format %{ "MOVSD $dst,$mem" %}
6274 ins_encode %{
6275 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6276 %}
6277 ins_pipe( pipe_slow );
6278 %}
6279
6280 instruct loadD_partial(regD dst, memory mem) %{
6281 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6282 match(Set dst (LoadD mem));
6283 ins_cost(145);
6284 format %{ "MOVLPD $dst,$mem" %}
6285 ins_encode %{
6286 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6287 %}
6288 ins_pipe( pipe_slow );
6289 %}
6290
6291 // Load to XMM register (single-precision floating point)
6292 // MOVSS instruction
6293 instruct loadF(regF dst, memory mem) %{
6294 predicate(UseSSE>=1);
6295 match(Set dst (LoadF mem));
6296 ins_cost(145);
6297 format %{ "MOVSS $dst,$mem" %}
6298 ins_encode %{
6299 __ movflt ($dst$$XMMRegister, $mem$$Address);
6300 %}
6301 ins_pipe( pipe_slow );
6302 %}
6303
6304 // Load Float
6305 instruct loadFPR(regFPR dst, memory mem) %{
6306 predicate(UseSSE==0);
6307 match(Set dst (LoadF mem));
6308
6309 ins_cost(150);
6310 format %{ "FLD_S ST,$mem\n\t"
6311 "FSTP $dst" %}
6312 opcode(0xD9); /* D9 /0 */
6313 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6314 Pop_Reg_FPR(dst) );
6315 ins_pipe( fpu_reg_mem );
6316 %}
6317
6318 // Load Effective Address
6319 instruct leaP8(eRegP dst, indOffset8 mem) %{
6320 match(Set dst mem);
6321
6322 ins_cost(110);
6323 format %{ "LEA $dst,$mem" %}
6324 opcode(0x8D);
6325 ins_encode( OpcP, RegMem(dst,mem));
6326 ins_pipe( ialu_reg_reg_fat );
6327 %}
6328
6329 instruct leaP32(eRegP dst, indOffset32 mem) %{
6330 match(Set dst mem);
6331
6332 ins_cost(110);
6333 format %{ "LEA $dst,$mem" %}
6334 opcode(0x8D);
6335 ins_encode( OpcP, RegMem(dst,mem));
6336 ins_pipe( ialu_reg_reg_fat );
6337 %}
6338
6339 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6340 match(Set dst mem);
6341
6342 ins_cost(110);
6343 format %{ "LEA $dst,$mem" %}
6344 opcode(0x8D);
6345 ins_encode( OpcP, RegMem(dst,mem));
6346 ins_pipe( ialu_reg_reg_fat );
6347 %}
6348
6349 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6350 match(Set dst mem);
6351
6352 ins_cost(110);
6353 format %{ "LEA $dst,$mem" %}
6354 opcode(0x8D);
6355 ins_encode( OpcP, RegMem(dst,mem));
6356 ins_pipe( ialu_reg_reg_fat );
6357 %}
6358
6359 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6360 match(Set dst mem);
6361
6362 ins_cost(110);
6363 format %{ "LEA $dst,$mem" %}
6364 opcode(0x8D);
6365 ins_encode( OpcP, RegMem(dst,mem));
6366 ins_pipe( ialu_reg_reg_fat );
6367 %}
6368
6369 // Load Constant
6370 instruct loadConI(rRegI dst, immI src) %{
6371 match(Set dst src);
6372
6373 format %{ "MOV $dst,$src" %}
6374 ins_encode( LdImmI(dst, src) );
6375 ins_pipe( ialu_reg_fat );
6376 %}
6377
6378 // Load Constant zero
6379 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6380 match(Set dst src);
6381 effect(KILL cr);
6382
6383 ins_cost(50);
6384 format %{ "XOR $dst,$dst" %}
6385 opcode(0x33); /* + rd */
6386 ins_encode( OpcP, RegReg( dst, dst ) );
6387 ins_pipe( ialu_reg );
6388 %}
6389
6390 instruct loadConP(eRegP dst, immP src) %{
6391 match(Set dst src);
6392
6393 format %{ "MOV $dst,$src" %}
6394 opcode(0xB8); /* + rd */
6395 ins_encode( LdImmP(dst, src) );
6396 ins_pipe( ialu_reg_fat );
6397 %}
6398
6399 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6400 match(Set dst src);
6401 effect(KILL cr);
6402 ins_cost(200);
6403 format %{ "MOV $dst.lo,$src.lo\n\t"
6404 "MOV $dst.hi,$src.hi" %}
6405 opcode(0xB8);
6406 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6407 ins_pipe( ialu_reg_long_fat );
6408 %}
6409
6410 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6411 match(Set dst src);
6412 effect(KILL cr);
6413 ins_cost(150);
6414 format %{ "XOR $dst.lo,$dst.lo\n\t"
6415 "XOR $dst.hi,$dst.hi" %}
6416 opcode(0x33,0x33);
6417 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6418 ins_pipe( ialu_reg_long );
6419 %}
6420
6421 // The instruction usage is guarded by predicate in operand immFPR().
6422 instruct loadConFPR(regFPR dst, immFPR con) %{
6423 match(Set dst con);
6424 ins_cost(125);
6425 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6426 "FSTP $dst" %}
6427 ins_encode %{
6428 __ fld_s($constantaddress($con));
6429 __ fstp_d($dst$$reg);
6430 %}
6431 ins_pipe(fpu_reg_con);
6432 %}
6433
6434 // The instruction usage is guarded by predicate in operand immFPR0().
6435 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6436 match(Set dst con);
6437 ins_cost(125);
6438 format %{ "FLDZ ST\n\t"
6439 "FSTP $dst" %}
6440 ins_encode %{
6441 __ fldz();
6442 __ fstp_d($dst$$reg);
6443 %}
6444 ins_pipe(fpu_reg_con);
6445 %}
6446
6447 // The instruction usage is guarded by predicate in operand immFPR1().
6448 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6449 match(Set dst con);
6450 ins_cost(125);
6451 format %{ "FLD1 ST\n\t"
6452 "FSTP $dst" %}
6453 ins_encode %{
6454 __ fld1();
6455 __ fstp_d($dst$$reg);
6456 %}
6457 ins_pipe(fpu_reg_con);
6458 %}
6459
6460 // The instruction usage is guarded by predicate in operand immF().
6461 instruct loadConF(regF dst, immF con) %{
6462 match(Set dst con);
6463 ins_cost(125);
6464 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6465 ins_encode %{
6466 __ movflt($dst$$XMMRegister, $constantaddress($con));
6467 %}
6468 ins_pipe(pipe_slow);
6469 %}
6470
6471 // The instruction usage is guarded by predicate in operand immF0().
6472 instruct loadConF0(regF dst, immF0 src) %{
6473 match(Set dst src);
6474 ins_cost(100);
6475 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6476 ins_encode %{
6477 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6478 %}
6479 ins_pipe(pipe_slow);
6480 %}
6481
6482 // The instruction usage is guarded by predicate in operand immDPR().
6483 instruct loadConDPR(regDPR dst, immDPR con) %{
6484 match(Set dst con);
6485 ins_cost(125);
6486
6487 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6488 "FSTP $dst" %}
6489 ins_encode %{
6490 __ fld_d($constantaddress($con));
6491 __ fstp_d($dst$$reg);
6492 %}
6493 ins_pipe(fpu_reg_con);
6494 %}
6495
6496 // The instruction usage is guarded by predicate in operand immDPR0().
6497 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6498 match(Set dst con);
6499 ins_cost(125);
6500
6501 format %{ "FLDZ ST\n\t"
6502 "FSTP $dst" %}
6503 ins_encode %{
6504 __ fldz();
6505 __ fstp_d($dst$$reg);
6506 %}
6507 ins_pipe(fpu_reg_con);
6508 %}
6509
6510 // The instruction usage is guarded by predicate in operand immDPR1().
6511 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6512 match(Set dst con);
6513 ins_cost(125);
6514
6515 format %{ "FLD1 ST\n\t"
6516 "FSTP $dst" %}
6517 ins_encode %{
6518 __ fld1();
6519 __ fstp_d($dst$$reg);
6520 %}
6521 ins_pipe(fpu_reg_con);
6522 %}
6523
6524 // The instruction usage is guarded by predicate in operand immD().
6525 instruct loadConD(regD dst, immD con) %{
6526 match(Set dst con);
6527 ins_cost(125);
6528 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6529 ins_encode %{
6530 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6531 %}
6532 ins_pipe(pipe_slow);
6533 %}
6534
6535 // The instruction usage is guarded by predicate in operand immD0().
6536 instruct loadConD0(regD dst, immD0 src) %{
6537 match(Set dst src);
6538 ins_cost(100);
6539 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6540 ins_encode %{
6541 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6542 %}
6543 ins_pipe( pipe_slow );
6544 %}
6545
6546 // Load Stack Slot
6547 instruct loadSSI(rRegI dst, stackSlotI src) %{
6548 match(Set dst src);
6549 ins_cost(125);
6550
6551 format %{ "MOV $dst,$src" %}
6552 opcode(0x8B);
6553 ins_encode( OpcP, RegMem(dst,src));
6554 ins_pipe( ialu_reg_mem );
6555 %}
6556
6557 instruct loadSSL(eRegL dst, stackSlotL src) %{
6558 match(Set dst src);
6559
6560 ins_cost(200);
6561 format %{ "MOV $dst,$src.lo\n\t"
6562 "MOV $dst+4,$src.hi" %}
6563 opcode(0x8B, 0x8B);
6564 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6565 ins_pipe( ialu_mem_long_reg );
6566 %}
6567
6568 // Load Stack Slot
6569 instruct loadSSP(eRegP dst, stackSlotP src) %{
6570 match(Set dst src);
6571 ins_cost(125);
6572
6573 format %{ "MOV $dst,$src" %}
6574 opcode(0x8B);
6575 ins_encode( OpcP, RegMem(dst,src));
6576 ins_pipe( ialu_reg_mem );
6577 %}
6578
6579 // Load Stack Slot
6580 instruct loadSSF(regFPR dst, stackSlotF src) %{
6581 match(Set dst src);
6582 ins_cost(125);
6583
6584 format %{ "FLD_S $src\n\t"
6585 "FSTP $dst" %}
6586 opcode(0xD9); /* D9 /0, FLD m32real */
6587 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6588 Pop_Reg_FPR(dst) );
6589 ins_pipe( fpu_reg_mem );
6590 %}
6591
6592 // Load Stack Slot
6593 instruct loadSSD(regDPR dst, stackSlotD src) %{
6594 match(Set dst src);
6595 ins_cost(125);
6596
6597 format %{ "FLD_D $src\n\t"
6598 "FSTP $dst" %}
6599 opcode(0xDD); /* DD /0, FLD m64real */
6600 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6601 Pop_Reg_DPR(dst) );
6602 ins_pipe( fpu_reg_mem );
6603 %}
6604
6605 // Prefetch instructions.
6606 // Must be safe to execute with invalid address (cannot fault).
6607
6608 instruct prefetchr0( memory mem ) %{
6609 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6610 match(PrefetchRead mem);
6611 ins_cost(0);
6612 size(0);
6613 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6614 ins_encode();
6615 ins_pipe(empty);
6616 %}
6617
6618 instruct prefetchr( memory mem ) %{
6619 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6620 match(PrefetchRead mem);
6621 ins_cost(100);
6622
6623 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6624 ins_encode %{
6625 __ prefetchr($mem$$Address);
6626 %}
6627 ins_pipe(ialu_mem);
6628 %}
6629
6630 instruct prefetchrNTA( memory mem ) %{
6631 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6632 match(PrefetchRead mem);
6633 ins_cost(100);
6634
6635 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6636 ins_encode %{
6637 __ prefetchnta($mem$$Address);
6638 %}
6639 ins_pipe(ialu_mem);
6640 %}
6641
6642 instruct prefetchrT0( memory mem ) %{
6643 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6644 match(PrefetchRead mem);
6645 ins_cost(100);
6646
6647 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6648 ins_encode %{
6649 __ prefetcht0($mem$$Address);
6650 %}
6651 ins_pipe(ialu_mem);
6652 %}
6653
6654 instruct prefetchrT2( memory mem ) %{
6655 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6656 match(PrefetchRead mem);
6657 ins_cost(100);
6658
6659 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6660 ins_encode %{
6661 __ prefetcht2($mem$$Address);
6662 %}
6663 ins_pipe(ialu_mem);
6664 %}
6665
6666 instruct prefetchw0( memory mem ) %{
6667 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6668 match(PrefetchWrite mem);
6669 ins_cost(0);
6670 size(0);
6671 format %{ "Prefetch (non-SSE is empty encoding)" %}
6672 ins_encode();
6673 ins_pipe(empty);
6674 %}
6675
6676 instruct prefetchw( memory mem ) %{
6677 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6678 match( PrefetchWrite mem );
6679 ins_cost(100);
6680
6681 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6682 ins_encode %{
6683 __ prefetchw($mem$$Address);
6684 %}
6685 ins_pipe(ialu_mem);
6686 %}
6687
6688 instruct prefetchwNTA( memory mem ) %{
6689 predicate(UseSSE>=1);
6690 match(PrefetchWrite mem);
6691 ins_cost(100);
6692
6693 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6694 ins_encode %{
6695 __ prefetchnta($mem$$Address);
6696 %}
6697 ins_pipe(ialu_mem);
6698 %}
6699
6700 // Prefetch instructions for allocation.
6701
6702 instruct prefetchAlloc0( memory mem ) %{
6703 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6704 match(PrefetchAllocation mem);
6705 ins_cost(0);
6706 size(0);
6707 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6708 ins_encode();
6709 ins_pipe(empty);
6710 %}
6711
6712 instruct prefetchAlloc( memory mem ) %{
6713 predicate(AllocatePrefetchInstr==3);
6714 match( PrefetchAllocation mem );
6715 ins_cost(100);
6716
6717 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6718 ins_encode %{
6719 __ prefetchw($mem$$Address);
6720 %}
6721 ins_pipe(ialu_mem);
6722 %}
6723
6724 instruct prefetchAllocNTA( memory mem ) %{
6725 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6726 match(PrefetchAllocation mem);
6727 ins_cost(100);
6728
6729 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6730 ins_encode %{
6731 __ prefetchnta($mem$$Address);
6732 %}
6733 ins_pipe(ialu_mem);
6734 %}
6735
6736 instruct prefetchAllocT0( memory mem ) %{
6737 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6738 match(PrefetchAllocation mem);
6739 ins_cost(100);
6740
6741 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6742 ins_encode %{
6743 __ prefetcht0($mem$$Address);
6744 %}
6745 ins_pipe(ialu_mem);
6746 %}
6747
6748 instruct prefetchAllocT2( memory mem ) %{
6749 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6750 match(PrefetchAllocation mem);
6751 ins_cost(100);
6752
6753 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6754 ins_encode %{
6755 __ prefetcht2($mem$$Address);
6756 %}
6757 ins_pipe(ialu_mem);
6758 %}
6759
6760 //----------Store Instructions-------------------------------------------------
6761
6762 // Store Byte
6763 instruct storeB(memory mem, xRegI src) %{
6764 match(Set mem (StoreB mem src));
6765
6766 ins_cost(125);
6767 format %{ "MOV8 $mem,$src" %}
6768 opcode(0x88);
6769 ins_encode( OpcP, RegMem( src, mem ) );
6770 ins_pipe( ialu_mem_reg );
6771 %}
6772
6773 // Store Char/Short
6774 instruct storeC(memory mem, rRegI src) %{
6775 match(Set mem (StoreC mem src));
6776
6777 ins_cost(125);
6778 format %{ "MOV16 $mem,$src" %}
6779 opcode(0x89, 0x66);
6780 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6781 ins_pipe( ialu_mem_reg );
6782 %}
6783
6784 // Store Integer
6785 instruct storeI(memory mem, rRegI src) %{
6786 match(Set mem (StoreI mem src));
6787
6788 ins_cost(125);
6789 format %{ "MOV $mem,$src" %}
6790 opcode(0x89);
6791 ins_encode( OpcP, RegMem( src, mem ) );
6792 ins_pipe( ialu_mem_reg );
6793 %}
6794
6795 // Store Long
6796 instruct storeL(long_memory mem, eRegL src) %{
6797 predicate(!((StoreLNode*)n)->require_atomic_access());
6798 match(Set mem (StoreL mem src));
6799
6800 ins_cost(200);
6801 format %{ "MOV $mem,$src.lo\n\t"
6802 "MOV $mem+4,$src.hi" %}
6803 opcode(0x89, 0x89);
6804 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6805 ins_pipe( ialu_mem_long_reg );
6806 %}
6807
6808 // Store Long to Integer
6809 instruct storeL2I(memory mem, eRegL src) %{
6810 match(Set mem (StoreI mem (ConvL2I src)));
6811
6812 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6813 ins_encode %{
6814 __ movl($mem$$Address, $src$$Register);
6815 %}
6816 ins_pipe(ialu_mem_reg);
6817 %}
6818
6819 // Volatile Store Long. Must be atomic, so move it into
6820 // the FP TOS and then do a 64-bit FIST. Has to probe the
6821 // target address before the store (for null-ptr checks)
6822 // so the memory operand is used twice in the encoding.
6823 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6824 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6825 match(Set mem (StoreL mem src));
6826 effect( KILL cr );
6827 ins_cost(400);
6828 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6829 "FILD $src\n\t"
6830 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6831 opcode(0x3B);
6832 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6833 ins_pipe( fpu_reg_mem );
6834 %}
6835
6836 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6837 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6838 match(Set mem (StoreL mem src));
6839 effect( TEMP tmp, KILL cr );
6840 ins_cost(380);
6841 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6842 "MOVSD $tmp,$src\n\t"
6843 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6844 ins_encode %{
6845 __ cmpl(rax, $mem$$Address);
6846 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6847 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6848 %}
6849 ins_pipe( pipe_slow );
6850 %}
6851
6852 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6853 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6854 match(Set mem (StoreL mem src));
6855 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6856 ins_cost(360);
6857 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6858 "MOVD $tmp,$src.lo\n\t"
6859 "MOVD $tmp2,$src.hi\n\t"
6860 "PUNPCKLDQ $tmp,$tmp2\n\t"
6861 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6862 ins_encode %{
6863 __ cmpl(rax, $mem$$Address);
6864 __ movdl($tmp$$XMMRegister, $src$$Register);
6865 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6866 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6867 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6868 %}
6869 ins_pipe( pipe_slow );
6870 %}
6871
6872 // Store Pointer; for storing unknown oops and raw pointers
6873 instruct storeP(memory mem, anyRegP src) %{
6874 match(Set mem (StoreP mem src));
6875
6876 ins_cost(125);
6877 format %{ "MOV $mem,$src" %}
6878 opcode(0x89);
6879 ins_encode( OpcP, RegMem( src, mem ) );
6880 ins_pipe( ialu_mem_reg );
6881 %}
6882
6883 // Store Integer Immediate
6884 instruct storeImmI(memory mem, immI src) %{
6885 match(Set mem (StoreI mem src));
6886
6887 ins_cost(150);
6888 format %{ "MOV $mem,$src" %}
6889 opcode(0xC7); /* C7 /0 */
6890 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6891 ins_pipe( ialu_mem_imm );
6892 %}
6893
6894 // Store Short/Char Immediate
6895 instruct storeImmI16(memory mem, immI16 src) %{
6896 predicate(UseStoreImmI16);
6897 match(Set mem (StoreC mem src));
6898
6899 ins_cost(150);
6900 format %{ "MOV16 $mem,$src" %}
6901 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6902 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6903 ins_pipe( ialu_mem_imm );
6904 %}
6905
6906 // Store Pointer Immediate; null pointers or constant oops that do not
6907 // need card-mark barriers.
6908 instruct storeImmP(memory mem, immP src) %{
6909 match(Set mem (StoreP mem src));
6910
6911 ins_cost(150);
6912 format %{ "MOV $mem,$src" %}
6913 opcode(0xC7); /* C7 /0 */
6914 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6915 ins_pipe( ialu_mem_imm );
6916 %}
6917
6918 // Store Byte Immediate
6919 instruct storeImmB(memory mem, immI8 src) %{
6920 match(Set mem (StoreB mem src));
6921
6922 ins_cost(150);
6923 format %{ "MOV8 $mem,$src" %}
6924 opcode(0xC6); /* C6 /0 */
6925 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6926 ins_pipe( ialu_mem_imm );
6927 %}
6928
6929 // Store CMS card-mark Immediate
6930 instruct storeImmCM(memory mem, immI8 src) %{
6931 match(Set mem (StoreCM mem src));
6932
6933 ins_cost(150);
6934 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6935 opcode(0xC6); /* C6 /0 */
6936 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6937 ins_pipe( ialu_mem_imm );
6938 %}
6939
6940 // Store Double
6941 instruct storeDPR( memory mem, regDPR1 src) %{
6942 predicate(UseSSE<=1);
6943 match(Set mem (StoreD mem src));
6944
6945 ins_cost(100);
6946 format %{ "FST_D $mem,$src" %}
6947 opcode(0xDD); /* DD /2 */
6948 ins_encode( enc_FPR_store(mem,src) );
6949 ins_pipe( fpu_mem_reg );
6950 %}
6951
6952 // Store double does rounding on x86
6953 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6954 predicate(UseSSE<=1);
6955 match(Set mem (StoreD mem (RoundDouble src)));
6956
6957 ins_cost(100);
6958 format %{ "FST_D $mem,$src\t# round" %}
6959 opcode(0xDD); /* DD /2 */
6960 ins_encode( enc_FPR_store(mem,src) );
6961 ins_pipe( fpu_mem_reg );
6962 %}
6963
6964 // Store XMM register to memory (double-precision floating points)
6965 // MOVSD instruction
6966 instruct storeD(memory mem, regD src) %{
6967 predicate(UseSSE>=2);
6968 match(Set mem (StoreD mem src));
6969 ins_cost(95);
6970 format %{ "MOVSD $mem,$src" %}
6971 ins_encode %{
6972 __ movdbl($mem$$Address, $src$$XMMRegister);
6973 %}
6974 ins_pipe( pipe_slow );
6975 %}
6976
6977 // Store XMM register to memory (single-precision floating point)
6978 // MOVSS instruction
6979 instruct storeF(memory mem, regF src) %{
6980 predicate(UseSSE>=1);
6981 match(Set mem (StoreF mem src));
6982 ins_cost(95);
6983 format %{ "MOVSS $mem,$src" %}
6984 ins_encode %{
6985 __ movflt($mem$$Address, $src$$XMMRegister);
6986 %}
6987 ins_pipe( pipe_slow );
6988 %}
6989
6990 // Store Float
6991 instruct storeFPR( memory mem, regFPR1 src) %{
6992 predicate(UseSSE==0);
6993 match(Set mem (StoreF mem src));
6994
6995 ins_cost(100);
6996 format %{ "FST_S $mem,$src" %}
6997 opcode(0xD9); /* D9 /2 */
6998 ins_encode( enc_FPR_store(mem,src) );
6999 ins_pipe( fpu_mem_reg );
7000 %}
7001
7002 // Store Float does rounding on x86
7003 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7004 predicate(UseSSE==0);
7005 match(Set mem (StoreF mem (RoundFloat src)));
7006
7007 ins_cost(100);
7008 format %{ "FST_S $mem,$src\t# round" %}
7009 opcode(0xD9); /* D9 /2 */
7010 ins_encode( enc_FPR_store(mem,src) );
7011 ins_pipe( fpu_mem_reg );
7012 %}
7013
7014 // Store Float does rounding on x86
7015 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7016 predicate(UseSSE<=1);
7017 match(Set mem (StoreF mem (ConvD2F src)));
7018
7019 ins_cost(100);
7020 format %{ "FST_S $mem,$src\t# D-round" %}
7021 opcode(0xD9); /* D9 /2 */
7022 ins_encode( enc_FPR_store(mem,src) );
7023 ins_pipe( fpu_mem_reg );
7024 %}
7025
7026 // Store immediate Float value (it is faster than store from FPU register)
7027 // The instruction usage is guarded by predicate in operand immFPR().
7028 instruct storeFPR_imm( memory mem, immFPR src) %{
7029 match(Set mem (StoreF mem src));
7030
7031 ins_cost(50);
7032 format %{ "MOV $mem,$src\t# store float" %}
7033 opcode(0xC7); /* C7 /0 */
7034 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7035 ins_pipe( ialu_mem_imm );
7036 %}
7037
7038 // Store immediate Float value (it is faster than store from XMM register)
7039 // The instruction usage is guarded by predicate in operand immF().
7040 instruct storeF_imm( memory mem, immF src) %{
7041 match(Set mem (StoreF mem src));
7042
7043 ins_cost(50);
7044 format %{ "MOV $mem,$src\t# store float" %}
7045 opcode(0xC7); /* C7 /0 */
7046 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7047 ins_pipe( ialu_mem_imm );
7048 %}
7049
7050 // Store Integer to stack slot
7051 instruct storeSSI(stackSlotI dst, rRegI src) %{
7052 match(Set dst src);
7053
7054 ins_cost(100);
7055 format %{ "MOV $dst,$src" %}
7056 opcode(0x89);
7057 ins_encode( OpcPRegSS( dst, src ) );
7058 ins_pipe( ialu_mem_reg );
7059 %}
7060
7061 // Store Integer to stack slot
7062 instruct storeSSP(stackSlotP dst, eRegP src) %{
7063 match(Set dst src);
7064
7065 ins_cost(100);
7066 format %{ "MOV $dst,$src" %}
7067 opcode(0x89);
7068 ins_encode( OpcPRegSS( dst, src ) );
7069 ins_pipe( ialu_mem_reg );
7070 %}
7071
7072 // Store Long to stack slot
7073 instruct storeSSL(stackSlotL dst, eRegL src) %{
7074 match(Set dst src);
7075
7076 ins_cost(200);
7077 format %{ "MOV $dst,$src.lo\n\t"
7078 "MOV $dst+4,$src.hi" %}
7079 opcode(0x89, 0x89);
7080 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7081 ins_pipe( ialu_mem_long_reg );
7082 %}
7083
7084 //----------MemBar Instructions-----------------------------------------------
7085 // Memory barrier flavors
7086
7087 instruct membar_acquire() %{
7088 match(MemBarAcquire);
7089 ins_cost(400);
7090
7091 size(0);
7092 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7093 ins_encode();
7094 ins_pipe(empty);
7095 %}
7096
7097 instruct membar_acquire_lock() %{
7098 match(MemBarAcquireLock);
7099 ins_cost(0);
7100
7101 size(0);
7102 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7103 ins_encode( );
7104 ins_pipe(empty);
7105 %}
7106
7107 instruct membar_release() %{
7108 match(MemBarRelease);
7109 ins_cost(400);
7110
7111 size(0);
7112 format %{ "MEMBAR-release ! (empty encoding)" %}
7113 ins_encode( );
7114 ins_pipe(empty);
7115 %}
7116
7117 instruct membar_release_lock() %{
7118 match(MemBarReleaseLock);
7119 ins_cost(0);
7120
7121 size(0);
7122 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7123 ins_encode( );
7124 ins_pipe(empty);
7125 %}
7126
7127 instruct membar_volatile(eFlagsReg cr) %{
7128 match(MemBarVolatile);
7129 effect(KILL cr);
7130 ins_cost(400);
7131
7132 format %{
7133 $$template
7134 if (os::is_MP()) {
7135 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7136 } else {
7137 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7138 }
7139 %}
7140 ins_encode %{
7141 __ membar(Assembler::StoreLoad);
7142 %}
7143 ins_pipe(pipe_slow);
7144 %}
7145
7146 instruct unnecessary_membar_volatile() %{
7147 match(MemBarVolatile);
7148 predicate(Matcher::post_store_load_barrier(n));
7149 ins_cost(0);
7150
7151 size(0);
7152 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7153 ins_encode( );
7154 ins_pipe(empty);
7155 %}
7156
7157 instruct membar_storestore() %{
7158 match(MemBarStoreStore);
7159 ins_cost(0);
7160
7161 size(0);
7162 format %{ "MEMBAR-storestore (empty encoding)" %}
7163 ins_encode( );
7164 ins_pipe(empty);
7165 %}
7166
7167 //----------Move Instructions--------------------------------------------------
7168 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7169 match(Set dst (CastX2P src));
7170 format %{ "# X2P $dst, $src" %}
7171 ins_encode( /*empty encoding*/ );
7172 ins_cost(0);
7173 ins_pipe(empty);
7174 %}
7175
7176 instruct castP2X(rRegI dst, eRegP src ) %{
7177 match(Set dst (CastP2X src));
7178 ins_cost(50);
7179 format %{ "MOV $dst, $src\t# CastP2X" %}
7180 ins_encode( enc_Copy( dst, src) );
7181 ins_pipe( ialu_reg_reg );
7182 %}
7183
7184 //----------Conditional Move---------------------------------------------------
7185 // Conditional move
7186 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7187 predicate(!VM_Version::supports_cmov() );
7188 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7189 ins_cost(200);
7190 format %{ "J$cop,us skip\t# signed cmove\n\t"
7191 "MOV $dst,$src\n"
7192 "skip:" %}
7193 ins_encode %{
7194 Label Lskip;
7195 // Invert sense of branch from sense of CMOV
7196 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7197 __ movl($dst$$Register, $src$$Register);
7198 __ bind(Lskip);
7199 %}
7200 ins_pipe( pipe_cmov_reg );
7201 %}
7202
7203 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7204 predicate(!VM_Version::supports_cmov() );
7205 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7206 ins_cost(200);
7207 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7208 "MOV $dst,$src\n"
7209 "skip:" %}
7210 ins_encode %{
7211 Label Lskip;
7212 // Invert sense of branch from sense of CMOV
7213 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7214 __ movl($dst$$Register, $src$$Register);
7215 __ bind(Lskip);
7216 %}
7217 ins_pipe( pipe_cmov_reg );
7218 %}
7219
7220 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7221 predicate(VM_Version::supports_cmov() );
7222 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7223 ins_cost(200);
7224 format %{ "CMOV$cop $dst,$src" %}
7225 opcode(0x0F,0x40);
7226 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7227 ins_pipe( pipe_cmov_reg );
7228 %}
7229
7230 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7231 predicate(VM_Version::supports_cmov() );
7232 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7233 ins_cost(200);
7234 format %{ "CMOV$cop $dst,$src" %}
7235 opcode(0x0F,0x40);
7236 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7237 ins_pipe( pipe_cmov_reg );
7238 %}
7239
7240 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7241 predicate(VM_Version::supports_cmov() );
7242 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7243 ins_cost(200);
7244 expand %{
7245 cmovI_regU(cop, cr, dst, src);
7246 %}
7247 %}
7248
7249 // Conditional move
7250 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7251 predicate(VM_Version::supports_cmov() );
7252 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7253 ins_cost(250);
7254 format %{ "CMOV$cop $dst,$src" %}
7255 opcode(0x0F,0x40);
7256 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7257 ins_pipe( pipe_cmov_mem );
7258 %}
7259
7260 // Conditional move
7261 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7262 predicate(VM_Version::supports_cmov() );
7263 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7264 ins_cost(250);
7265 format %{ "CMOV$cop $dst,$src" %}
7266 opcode(0x0F,0x40);
7267 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7268 ins_pipe( pipe_cmov_mem );
7269 %}
7270
7271 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7272 predicate(VM_Version::supports_cmov() );
7273 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7274 ins_cost(250);
7275 expand %{
7276 cmovI_memU(cop, cr, dst, src);
7277 %}
7278 %}
7279
7280 // Conditional move
7281 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7282 predicate(VM_Version::supports_cmov() );
7283 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7284 ins_cost(200);
7285 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7286 opcode(0x0F,0x40);
7287 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7288 ins_pipe( pipe_cmov_reg );
7289 %}
7290
7291 // Conditional move (non-P6 version)
7292 // Note: a CMoveP is generated for stubs and native wrappers
7293 // regardless of whether we are on a P6, so we
7294 // emulate a cmov here
7295 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7296 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7297 ins_cost(300);
7298 format %{ "Jn$cop skip\n\t"
7299 "MOV $dst,$src\t# pointer\n"
7300 "skip:" %}
7301 opcode(0x8b);
7302 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7303 ins_pipe( pipe_cmov_reg );
7304 %}
7305
7306 // Conditional move
7307 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7308 predicate(VM_Version::supports_cmov() );
7309 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7310 ins_cost(200);
7311 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7312 opcode(0x0F,0x40);
7313 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7314 ins_pipe( pipe_cmov_reg );
7315 %}
7316
7317 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7318 predicate(VM_Version::supports_cmov() );
7319 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7320 ins_cost(200);
7321 expand %{
7322 cmovP_regU(cop, cr, dst, src);
7323 %}
7324 %}
7325
7326 // DISABLED: Requires the ADLC to emit a bottom_type call that
7327 // correctly meets the two pointer arguments; one is an incoming
7328 // register but the other is a memory operand. ALSO appears to
7329 // be buggy with implicit null checks.
7330 //
7331 //// Conditional move
7332 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7333 // predicate(VM_Version::supports_cmov() );
7334 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7335 // ins_cost(250);
7336 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7337 // opcode(0x0F,0x40);
7338 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7339 // ins_pipe( pipe_cmov_mem );
7340 //%}
7341 //
7342 //// Conditional move
7343 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7344 // predicate(VM_Version::supports_cmov() );
7345 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7346 // ins_cost(250);
7347 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7348 // opcode(0x0F,0x40);
7349 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7350 // ins_pipe( pipe_cmov_mem );
7351 //%}
7352
7353 // Conditional move
7354 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7355 predicate(UseSSE<=1);
7356 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7357 ins_cost(200);
7358 format %{ "FCMOV$cop $dst,$src\t# double" %}
7359 opcode(0xDA);
7360 ins_encode( enc_cmov_dpr(cop,src) );
7361 ins_pipe( pipe_cmovDPR_reg );
7362 %}
7363
7364 // Conditional move
7365 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7366 predicate(UseSSE==0);
7367 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7368 ins_cost(200);
7369 format %{ "FCMOV$cop $dst,$src\t# float" %}
7370 opcode(0xDA);
7371 ins_encode( enc_cmov_dpr(cop,src) );
7372 ins_pipe( pipe_cmovDPR_reg );
7373 %}
7374
7375 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7376 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7377 predicate(UseSSE<=1);
7378 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7379 ins_cost(200);
7380 format %{ "Jn$cop skip\n\t"
7381 "MOV $dst,$src\t# double\n"
7382 "skip:" %}
7383 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7384 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7385 ins_pipe( pipe_cmovDPR_reg );
7386 %}
7387
7388 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7389 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7390 predicate(UseSSE==0);
7391 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7392 ins_cost(200);
7393 format %{ "Jn$cop skip\n\t"
7394 "MOV $dst,$src\t# float\n"
7395 "skip:" %}
7396 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7397 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7398 ins_pipe( pipe_cmovDPR_reg );
7399 %}
7400
7401 // No CMOVE with SSE/SSE2
7402 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7403 predicate (UseSSE>=1);
7404 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7405 ins_cost(200);
7406 format %{ "Jn$cop skip\n\t"
7407 "MOVSS $dst,$src\t# float\n"
7408 "skip:" %}
7409 ins_encode %{
7410 Label skip;
7411 // Invert sense of branch from sense of CMOV
7412 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7413 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7414 __ bind(skip);
7415 %}
7416 ins_pipe( pipe_slow );
7417 %}
7418
7419 // No CMOVE with SSE/SSE2
7420 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7421 predicate (UseSSE>=2);
7422 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7423 ins_cost(200);
7424 format %{ "Jn$cop skip\n\t"
7425 "MOVSD $dst,$src\t# float\n"
7426 "skip:" %}
7427 ins_encode %{
7428 Label skip;
7429 // Invert sense of branch from sense of CMOV
7430 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7431 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7432 __ bind(skip);
7433 %}
7434 ins_pipe( pipe_slow );
7435 %}
7436
7437 // unsigned version
7438 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7439 predicate (UseSSE>=1);
7440 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7441 ins_cost(200);
7442 format %{ "Jn$cop skip\n\t"
7443 "MOVSS $dst,$src\t# float\n"
7444 "skip:" %}
7445 ins_encode %{
7446 Label skip;
7447 // Invert sense of branch from sense of CMOV
7448 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7449 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7450 __ bind(skip);
7451 %}
7452 ins_pipe( pipe_slow );
7453 %}
7454
7455 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7456 predicate (UseSSE>=1);
7457 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7458 ins_cost(200);
7459 expand %{
7460 fcmovF_regU(cop, cr, dst, src);
7461 %}
7462 %}
7463
7464 // unsigned version
7465 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7466 predicate (UseSSE>=2);
7467 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7468 ins_cost(200);
7469 format %{ "Jn$cop skip\n\t"
7470 "MOVSD $dst,$src\t# float\n"
7471 "skip:" %}
7472 ins_encode %{
7473 Label skip;
7474 // Invert sense of branch from sense of CMOV
7475 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7476 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7477 __ bind(skip);
7478 %}
7479 ins_pipe( pipe_slow );
7480 %}
7481
7482 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7483 predicate (UseSSE>=2);
7484 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7485 ins_cost(200);
7486 expand %{
7487 fcmovD_regU(cop, cr, dst, src);
7488 %}
7489 %}
7490
7491 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7492 predicate(VM_Version::supports_cmov() );
7493 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7494 ins_cost(200);
7495 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7496 "CMOV$cop $dst.hi,$src.hi" %}
7497 opcode(0x0F,0x40);
7498 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7499 ins_pipe( pipe_cmov_reg_long );
7500 %}
7501
7502 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7503 predicate(VM_Version::supports_cmov() );
7504 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7505 ins_cost(200);
7506 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7507 "CMOV$cop $dst.hi,$src.hi" %}
7508 opcode(0x0F,0x40);
7509 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7510 ins_pipe( pipe_cmov_reg_long );
7511 %}
7512
7513 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7514 predicate(VM_Version::supports_cmov() );
7515 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7516 ins_cost(200);
7517 expand %{
7518 cmovL_regU(cop, cr, dst, src);
7519 %}
7520 %}
7521
7522 //----------Arithmetic Instructions--------------------------------------------
7523 //----------Addition Instructions----------------------------------------------
7524
7525 // Integer Addition Instructions
7526 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7527 match(Set dst (AddI dst src));
7528 effect(KILL cr);
7529
7530 size(2);
7531 format %{ "ADD $dst,$src" %}
7532 opcode(0x03);
7533 ins_encode( OpcP, RegReg( dst, src) );
7534 ins_pipe( ialu_reg_reg );
7535 %}
7536
7537 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7538 match(Set dst (AddI dst src));
7539 effect(KILL cr);
7540
7541 format %{ "ADD $dst,$src" %}
7542 opcode(0x81, 0x00); /* /0 id */
7543 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7544 ins_pipe( ialu_reg );
7545 %}
7546
7547 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7548 predicate(UseIncDec);
7549 match(Set dst (AddI dst src));
7550 effect(KILL cr);
7551
7552 size(1);
7553 format %{ "INC $dst" %}
7554 opcode(0x40); /* */
7555 ins_encode( Opc_plus( primary, dst ) );
7556 ins_pipe( ialu_reg );
7557 %}
7558
7559 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7560 match(Set dst (AddI src0 src1));
7561 ins_cost(110);
7562
7563 format %{ "LEA $dst,[$src0 + $src1]" %}
7564 opcode(0x8D); /* 0x8D /r */
7565 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7566 ins_pipe( ialu_reg_reg );
7567 %}
7568
7569 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7570 match(Set dst (AddP src0 src1));
7571 ins_cost(110);
7572
7573 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7574 opcode(0x8D); /* 0x8D /r */
7575 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7576 ins_pipe( ialu_reg_reg );
7577 %}
7578
7579 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7580 predicate(UseIncDec);
7581 match(Set dst (AddI dst src));
7582 effect(KILL cr);
7583
7584 size(1);
7585 format %{ "DEC $dst" %}
7586 opcode(0x48); /* */
7587 ins_encode( Opc_plus( primary, dst ) );
7588 ins_pipe( ialu_reg );
7589 %}
7590
7591 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7592 match(Set dst (AddP dst src));
7593 effect(KILL cr);
7594
7595 size(2);
7596 format %{ "ADD $dst,$src" %}
7597 opcode(0x03);
7598 ins_encode( OpcP, RegReg( dst, src) );
7599 ins_pipe( ialu_reg_reg );
7600 %}
7601
7602 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7603 match(Set dst (AddP dst src));
7604 effect(KILL cr);
7605
7606 format %{ "ADD $dst,$src" %}
7607 opcode(0x81,0x00); /* Opcode 81 /0 id */
7608 // ins_encode( RegImm( dst, src) );
7609 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7610 ins_pipe( ialu_reg );
7611 %}
7612
7613 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7614 match(Set dst (AddI dst (LoadI src)));
7615 effect(KILL cr);
7616
7617 ins_cost(125);
7618 format %{ "ADD $dst,$src" %}
7619 opcode(0x03);
7620 ins_encode( OpcP, RegMem( dst, src) );
7621 ins_pipe( ialu_reg_mem );
7622 %}
7623
7624 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7625 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7626 effect(KILL cr);
7627
7628 ins_cost(150);
7629 format %{ "ADD $dst,$src" %}
7630 opcode(0x01); /* Opcode 01 /r */
7631 ins_encode( OpcP, RegMem( src, dst ) );
7632 ins_pipe( ialu_mem_reg );
7633 %}
7634
7635 // Add Memory with Immediate
7636 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7637 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7638 effect(KILL cr);
7639
7640 ins_cost(125);
7641 format %{ "ADD $dst,$src" %}
7642 opcode(0x81); /* Opcode 81 /0 id */
7643 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7644 ins_pipe( ialu_mem_imm );
7645 %}
7646
7647 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7648 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7649 effect(KILL cr);
7650
7651 ins_cost(125);
7652 format %{ "INC $dst" %}
7653 opcode(0xFF); /* Opcode FF /0 */
7654 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7655 ins_pipe( ialu_mem_imm );
7656 %}
7657
7658 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7659 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7660 effect(KILL cr);
7661
7662 ins_cost(125);
7663 format %{ "DEC $dst" %}
7664 opcode(0xFF); /* Opcode FF /1 */
7665 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7666 ins_pipe( ialu_mem_imm );
7667 %}
7668
7669
7670 instruct checkCastPP( eRegP dst ) %{
7671 match(Set dst (CheckCastPP dst));
7672
7673 size(0);
7674 format %{ "#checkcastPP of $dst" %}
7675 ins_encode( /*empty encoding*/ );
7676 ins_pipe( empty );
7677 %}
7678
7679 instruct castPP( eRegP dst ) %{
7680 match(Set dst (CastPP dst));
7681 format %{ "#castPP of $dst" %}
7682 ins_encode( /*empty encoding*/ );
7683 ins_pipe( empty );
7684 %}
7685
7686 instruct castII( rRegI dst ) %{
7687 match(Set dst (CastII dst));
7688 format %{ "#castII of $dst" %}
7689 ins_encode( /*empty encoding*/ );
7690 ins_cost(0);
7691 ins_pipe( empty );
7692 %}
7693
7694
7695 // Load-locked - same as a regular pointer load when used with compare-swap
7696 instruct loadPLocked(eRegP dst, memory mem) %{
7697 match(Set dst (LoadPLocked mem));
7698
7699 ins_cost(125);
7700 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7701 opcode(0x8B);
7702 ins_encode( OpcP, RegMem(dst,mem));
7703 ins_pipe( ialu_reg_mem );
7704 %}
7705
7706 // Conditional-store of the updated heap-top.
7707 // Used during allocation of the shared heap.
7708 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7709 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7710 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7711 // EAX is killed if there is contention, but then it's also unused.
7712 // In the common case of no contention, EAX holds the new oop address.
7713 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7714 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7715 ins_pipe( pipe_cmpxchg );
7716 %}
7717
7718 // Conditional-store of an int value.
7719 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7720 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7721 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7722 effect(KILL oldval);
7723 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7724 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7725 ins_pipe( pipe_cmpxchg );
7726 %}
7727
7728 // Conditional-store of a long value.
7729 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7730 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7731 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7732 effect(KILL oldval);
7733 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7734 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7735 "XCHG EBX,ECX"
7736 %}
7737 ins_encode %{
7738 // Note: we need to swap rbx, and rcx before and after the
7739 // cmpxchg8 instruction because the instruction uses
7740 // rcx as the high order word of the new value to store but
7741 // our register encoding uses rbx.
7742 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7743 if( os::is_MP() )
7744 __ lock();
7745 __ cmpxchg8($mem$$Address);
7746 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7747 %}
7748 ins_pipe( pipe_cmpxchg );
7749 %}
7750
7751 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7752
7753 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7754 predicate(VM_Version::supports_cx8());
7755 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7756 effect(KILL cr, KILL oldval);
7757 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7758 "MOV $res,0\n\t"
7759 "JNE,s fail\n\t"
7760 "MOV $res,1\n"
7761 "fail:" %}
7762 ins_encode( enc_cmpxchg8(mem_ptr),
7763 enc_flags_ne_to_boolean(res) );
7764 ins_pipe( pipe_cmpxchg );
7765 %}
7766
7767 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7768 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7769 effect(KILL cr, KILL oldval);
7770 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7771 "MOV $res,0\n\t"
7772 "JNE,s fail\n\t"
7773 "MOV $res,1\n"
7774 "fail:" %}
7775 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7776 ins_pipe( pipe_cmpxchg );
7777 %}
7778
7779 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7780 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7781 effect(KILL cr, KILL oldval);
7782 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7783 "MOV $res,0\n\t"
7784 "JNE,s fail\n\t"
7785 "MOV $res,1\n"
7786 "fail:" %}
7787 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7788 ins_pipe( pipe_cmpxchg );
7789 %}
7790
7791 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7792 predicate(n->as_LoadStore()->result_not_used());
7793 match(Set dummy (GetAndAddI mem add));
7794 effect(KILL cr);
7795 format %{ "ADDL [$mem],$add" %}
7796 ins_encode %{
7797 if (os::is_MP()) { __ lock(); }
7798 __ addl($mem$$Address, $add$$constant);
7799 %}
7800 ins_pipe( pipe_cmpxchg );
7801 %}
7802
7803 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7804 match(Set newval (GetAndAddI mem newval));
7805 effect(KILL cr);
7806 format %{ "XADDL [$mem],$newval" %}
7807 ins_encode %{
7808 if (os::is_MP()) { __ lock(); }
7809 __ xaddl($mem$$Address, $newval$$Register);
7810 %}
7811 ins_pipe( pipe_cmpxchg );
7812 %}
7813
7814 instruct xchgI( memory mem, rRegI newval) %{
7815 match(Set newval (GetAndSetI mem newval));
7816 format %{ "XCHGL $newval,[$mem]" %}
7817 ins_encode %{
7818 __ xchgl($newval$$Register, $mem$$Address);
7819 %}
7820 ins_pipe( pipe_cmpxchg );
7821 %}
7822
7823 instruct xchgP( memory mem, pRegP newval) %{
7824 match(Set newval (GetAndSetP mem newval));
7825 format %{ "XCHGL $newval,[$mem]" %}
7826 ins_encode %{
7827 __ xchgl($newval$$Register, $mem$$Address);
7828 %}
7829 ins_pipe( pipe_cmpxchg );
7830 %}
7831
7832 //----------Subtraction Instructions-------------------------------------------
7833
7834 // Integer Subtraction Instructions
7835 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7836 match(Set dst (SubI dst src));
7837 effect(KILL cr);
7838
7839 size(2);
7840 format %{ "SUB $dst,$src" %}
7841 opcode(0x2B);
7842 ins_encode( OpcP, RegReg( dst, src) );
7843 ins_pipe( ialu_reg_reg );
7844 %}
7845
7846 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7847 match(Set dst (SubI dst src));
7848 effect(KILL cr);
7849
7850 format %{ "SUB $dst,$src" %}
7851 opcode(0x81,0x05); /* Opcode 81 /5 */
7852 // ins_encode( RegImm( dst, src) );
7853 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7854 ins_pipe( ialu_reg );
7855 %}
7856
7857 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7858 match(Set dst (SubI dst (LoadI src)));
7859 effect(KILL cr);
7860
7861 ins_cost(125);
7862 format %{ "SUB $dst,$src" %}
7863 opcode(0x2B);
7864 ins_encode( OpcP, RegMem( dst, src) );
7865 ins_pipe( ialu_reg_mem );
7866 %}
7867
7868 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7869 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7870 effect(KILL cr);
7871
7872 ins_cost(150);
7873 format %{ "SUB $dst,$src" %}
7874 opcode(0x29); /* Opcode 29 /r */
7875 ins_encode( OpcP, RegMem( src, dst ) );
7876 ins_pipe( ialu_mem_reg );
7877 %}
7878
7879 // Subtract from a pointer
7880 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7881 match(Set dst (AddP dst (SubI zero src)));
7882 effect(KILL cr);
7883
7884 size(2);
7885 format %{ "SUB $dst,$src" %}
7886 opcode(0x2B);
7887 ins_encode( OpcP, RegReg( dst, src) );
7888 ins_pipe( ialu_reg_reg );
7889 %}
7890
7891 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7892 match(Set dst (SubI zero dst));
7893 effect(KILL cr);
7894
7895 size(2);
7896 format %{ "NEG $dst" %}
7897 opcode(0xF7,0x03); // Opcode F7 /3
7898 ins_encode( OpcP, RegOpc( dst ) );
7899 ins_pipe( ialu_reg );
7900 %}
7901
7902 //----------Multiplication/Division Instructions-------------------------------
7903 // Integer Multiplication Instructions
7904 // Multiply Register
7905 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7906 match(Set dst (MulI dst src));
7907 effect(KILL cr);
7908
7909 size(3);
7910 ins_cost(300);
7911 format %{ "IMUL $dst,$src" %}
7912 opcode(0xAF, 0x0F);
7913 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7914 ins_pipe( ialu_reg_reg_alu0 );
7915 %}
7916
7917 // Multiply 32-bit Immediate
7918 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7919 match(Set dst (MulI src imm));
7920 effect(KILL cr);
7921
7922 ins_cost(300);
7923 format %{ "IMUL $dst,$src,$imm" %}
7924 opcode(0x69); /* 69 /r id */
7925 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7926 ins_pipe( ialu_reg_reg_alu0 );
7927 %}
7928
7929 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7930 match(Set dst src);
7931 effect(KILL cr);
7932
7933 // Note that this is artificially increased to make it more expensive than loadConL
7934 ins_cost(250);
7935 format %{ "MOV EAX,$src\t// low word only" %}
7936 opcode(0xB8);
7937 ins_encode( LdImmL_Lo(dst, src) );
7938 ins_pipe( ialu_reg_fat );
7939 %}
7940
7941 // Multiply by 32-bit Immediate, taking the shifted high order results
7942 // (special case for shift by 32)
7943 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7944 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7945 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7946 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7947 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7948 effect(USE src1, KILL cr);
7949
7950 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7951 ins_cost(0*100 + 1*400 - 150);
7952 format %{ "IMUL EDX:EAX,$src1" %}
7953 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7954 ins_pipe( pipe_slow );
7955 %}
7956
7957 // Multiply by 32-bit Immediate, taking the shifted high order results
7958 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7959 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7960 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7961 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7962 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7963 effect(USE src1, KILL cr);
7964
7965 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7966 ins_cost(1*100 + 1*400 - 150);
7967 format %{ "IMUL EDX:EAX,$src1\n\t"
7968 "SAR EDX,$cnt-32" %}
7969 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7970 ins_pipe( pipe_slow );
7971 %}
7972
7973 // Multiply Memory 32-bit Immediate
7974 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7975 match(Set dst (MulI (LoadI src) imm));
7976 effect(KILL cr);
7977
7978 ins_cost(300);
7979 format %{ "IMUL $dst,$src,$imm" %}
7980 opcode(0x69); /* 69 /r id */
7981 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7982 ins_pipe( ialu_reg_mem_alu0 );
7983 %}
7984
7985 // Multiply Memory
7986 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7987 match(Set dst (MulI dst (LoadI src)));
7988 effect(KILL cr);
7989
7990 ins_cost(350);
7991 format %{ "IMUL $dst,$src" %}
7992 opcode(0xAF, 0x0F);
7993 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7994 ins_pipe( ialu_reg_mem_alu0 );
7995 %}
7996
7997 // Multiply Register Int to Long
7998 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7999 // Basic Idea: long = (long)int * (long)int
8000 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8001 effect(DEF dst, USE src, USE src1, KILL flags);
8002
8003 ins_cost(300);
8004 format %{ "IMUL $dst,$src1" %}
8005
8006 ins_encode( long_int_multiply( dst, src1 ) );
8007 ins_pipe( ialu_reg_reg_alu0 );
8008 %}
8009
8010 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8011 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8012 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8013 effect(KILL flags);
8014
8015 ins_cost(300);
8016 format %{ "MUL $dst,$src1" %}
8017
8018 ins_encode( long_uint_multiply(dst, src1) );
8019 ins_pipe( ialu_reg_reg_alu0 );
8020 %}
8021
8022 // Multiply Register Long
8023 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8024 match(Set dst (MulL dst src));
8025 effect(KILL cr, TEMP tmp);
8026 ins_cost(4*100+3*400);
8027 // Basic idea: lo(result) = lo(x_lo * y_lo)
8028 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8029 format %{ "MOV $tmp,$src.lo\n\t"
8030 "IMUL $tmp,EDX\n\t"
8031 "MOV EDX,$src.hi\n\t"
8032 "IMUL EDX,EAX\n\t"
8033 "ADD $tmp,EDX\n\t"
8034 "MUL EDX:EAX,$src.lo\n\t"
8035 "ADD EDX,$tmp" %}
8036 ins_encode( long_multiply( dst, src, tmp ) );
8037 ins_pipe( pipe_slow );
8038 %}
8039
8040 // Multiply Register Long where the left operand's high 32 bits are zero
8041 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8042 predicate(is_operand_hi32_zero(n->in(1)));
8043 match(Set dst (MulL dst src));
8044 effect(KILL cr, TEMP tmp);
8045 ins_cost(2*100+2*400);
8046 // Basic idea: lo(result) = lo(x_lo * y_lo)
8047 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8048 format %{ "MOV $tmp,$src.hi\n\t"
8049 "IMUL $tmp,EAX\n\t"
8050 "MUL EDX:EAX,$src.lo\n\t"
8051 "ADD EDX,$tmp" %}
8052 ins_encode %{
8053 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8054 __ imull($tmp$$Register, rax);
8055 __ mull($src$$Register);
8056 __ addl(rdx, $tmp$$Register);
8057 %}
8058 ins_pipe( pipe_slow );
8059 %}
8060
8061 // Multiply Register Long where the right operand's high 32 bits are zero
8062 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8063 predicate(is_operand_hi32_zero(n->in(2)));
8064 match(Set dst (MulL dst src));
8065 effect(KILL cr, TEMP tmp);
8066 ins_cost(2*100+2*400);
8067 // Basic idea: lo(result) = lo(x_lo * y_lo)
8068 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8069 format %{ "MOV $tmp,$src.lo\n\t"
8070 "IMUL $tmp,EDX\n\t"
8071 "MUL EDX:EAX,$src.lo\n\t"
8072 "ADD EDX,$tmp" %}
8073 ins_encode %{
8074 __ movl($tmp$$Register, $src$$Register);
8075 __ imull($tmp$$Register, rdx);
8076 __ mull($src$$Register);
8077 __ addl(rdx, $tmp$$Register);
8078 %}
8079 ins_pipe( pipe_slow );
8080 %}
8081
8082 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8083 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8084 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8085 match(Set dst (MulL dst src));
8086 effect(KILL cr);
8087 ins_cost(1*400);
8088 // Basic idea: lo(result) = lo(x_lo * y_lo)
8089 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8090 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8091 ins_encode %{
8092 __ mull($src$$Register);
8093 %}
8094 ins_pipe( pipe_slow );
8095 %}
8096
8097 // Multiply Register Long by small constant
8098 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8099 match(Set dst (MulL dst src));
8100 effect(KILL cr, TEMP tmp);
8101 ins_cost(2*100+2*400);
8102 size(12);
8103 // Basic idea: lo(result) = lo(src * EAX)
8104 // hi(result) = hi(src * EAX) + lo(src * EDX)
8105 format %{ "IMUL $tmp,EDX,$src\n\t"
8106 "MOV EDX,$src\n\t"
8107 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8108 "ADD EDX,$tmp" %}
8109 ins_encode( long_multiply_con( dst, src, tmp ) );
8110 ins_pipe( pipe_slow );
8111 %}
8112
8113 // Integer DIV with Register
8114 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8115 match(Set rax (DivI rax div));
8116 effect(KILL rdx, KILL cr);
8117 size(26);
8118 ins_cost(30*100+10*100);
8119 format %{ "CMP EAX,0x80000000\n\t"
8120 "JNE,s normal\n\t"
8121 "XOR EDX,EDX\n\t"
8122 "CMP ECX,-1\n\t"
8123 "JE,s done\n"
8124 "normal: CDQ\n\t"
8125 "IDIV $div\n\t"
8126 "done:" %}
8127 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8128 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8129 ins_pipe( ialu_reg_reg_alu0 );
8130 %}
8131
8132 // Divide Register Long
8133 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8134 match(Set dst (DivL src1 src2));
8135 effect( KILL cr, KILL cx, KILL bx );
8136 ins_cost(10000);
8137 format %{ "PUSH $src1.hi\n\t"
8138 "PUSH $src1.lo\n\t"
8139 "PUSH $src2.hi\n\t"
8140 "PUSH $src2.lo\n\t"
8141 "CALL SharedRuntime::ldiv\n\t"
8142 "ADD ESP,16" %}
8143 ins_encode( long_div(src1,src2) );
8144 ins_pipe( pipe_slow );
8145 %}
8146
8147 // Integer DIVMOD with Register, both quotient and mod results
8148 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8149 match(DivModI rax div);
8150 effect(KILL cr);
8151 size(26);
8152 ins_cost(30*100+10*100);
8153 format %{ "CMP EAX,0x80000000\n\t"
8154 "JNE,s normal\n\t"
8155 "XOR EDX,EDX\n\t"
8156 "CMP ECX,-1\n\t"
8157 "JE,s done\n"
8158 "normal: CDQ\n\t"
8159 "IDIV $div\n\t"
8160 "done:" %}
8161 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8162 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8163 ins_pipe( pipe_slow );
8164 %}
8165
8166 // Integer MOD with Register
8167 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8168 match(Set rdx (ModI rax div));
8169 effect(KILL rax, KILL cr);
8170
8171 size(26);
8172 ins_cost(300);
8173 format %{ "CDQ\n\t"
8174 "IDIV $div" %}
8175 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8176 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8177 ins_pipe( ialu_reg_reg_alu0 );
8178 %}
8179
8180 // Remainder Register Long
8181 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8182 match(Set dst (ModL src1 src2));
8183 effect( KILL cr, KILL cx, KILL bx );
8184 ins_cost(10000);
8185 format %{ "PUSH $src1.hi\n\t"
8186 "PUSH $src1.lo\n\t"
8187 "PUSH $src2.hi\n\t"
8188 "PUSH $src2.lo\n\t"
8189 "CALL SharedRuntime::lrem\n\t"
8190 "ADD ESP,16" %}
8191 ins_encode( long_mod(src1,src2) );
8192 ins_pipe( pipe_slow );
8193 %}
8194
8195 // Divide Register Long (no special case since divisor != -1)
8196 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8197 match(Set dst (DivL dst imm));
8198 effect( TEMP tmp, TEMP tmp2, KILL cr );
8199 ins_cost(1000);
8200 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8201 "XOR $tmp2,$tmp2\n\t"
8202 "CMP $tmp,EDX\n\t"
8203 "JA,s fast\n\t"
8204 "MOV $tmp2,EAX\n\t"
8205 "MOV EAX,EDX\n\t"
8206 "MOV EDX,0\n\t"
8207 "JLE,s pos\n\t"
8208 "LNEG EAX : $tmp2\n\t"
8209 "DIV $tmp # unsigned division\n\t"
8210 "XCHG EAX,$tmp2\n\t"
8211 "DIV $tmp\n\t"
8212 "LNEG $tmp2 : EAX\n\t"
8213 "JMP,s done\n"
8214 "pos:\n\t"
8215 "DIV $tmp\n\t"
8216 "XCHG EAX,$tmp2\n"
8217 "fast:\n\t"
8218 "DIV $tmp\n"
8219 "done:\n\t"
8220 "MOV EDX,$tmp2\n\t"
8221 "NEG EDX:EAX # if $imm < 0" %}
8222 ins_encode %{
8223 int con = (int)$imm$$constant;
8224 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8225 int pcon = (con > 0) ? con : -con;
8226 Label Lfast, Lpos, Ldone;
8227
8228 __ movl($tmp$$Register, pcon);
8229 __ xorl($tmp2$$Register,$tmp2$$Register);
8230 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8231 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8232
8233 __ movl($tmp2$$Register, $dst$$Register); // save
8234 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8235 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8236 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8237
8238 // Negative dividend.
8239 // convert value to positive to use unsigned division
8240 __ lneg($dst$$Register, $tmp2$$Register);
8241 __ divl($tmp$$Register);
8242 __ xchgl($dst$$Register, $tmp2$$Register);
8243 __ divl($tmp$$Register);
8244 // revert result back to negative
8245 __ lneg($tmp2$$Register, $dst$$Register);
8246 __ jmpb(Ldone);
8247
8248 __ bind(Lpos);
8249 __ divl($tmp$$Register); // Use unsigned division
8250 __ xchgl($dst$$Register, $tmp2$$Register);
8251 // Fallthrow for final divide, tmp2 has 32 bit hi result
8252
8253 __ bind(Lfast);
8254 // fast path: src is positive
8255 __ divl($tmp$$Register); // Use unsigned division
8256
8257 __ bind(Ldone);
8258 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8259 if (con < 0) {
8260 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8261 }
8262 %}
8263 ins_pipe( pipe_slow );
8264 %}
8265
8266 // Remainder Register Long (remainder fit into 32 bits)
8267 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8268 match(Set dst (ModL dst imm));
8269 effect( TEMP tmp, TEMP tmp2, KILL cr );
8270 ins_cost(1000);
8271 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8272 "CMP $tmp,EDX\n\t"
8273 "JA,s fast\n\t"
8274 "MOV $tmp2,EAX\n\t"
8275 "MOV EAX,EDX\n\t"
8276 "MOV EDX,0\n\t"
8277 "JLE,s pos\n\t"
8278 "LNEG EAX : $tmp2\n\t"
8279 "DIV $tmp # unsigned division\n\t"
8280 "MOV EAX,$tmp2\n\t"
8281 "DIV $tmp\n\t"
8282 "NEG EDX\n\t"
8283 "JMP,s done\n"
8284 "pos:\n\t"
8285 "DIV $tmp\n\t"
8286 "MOV EAX,$tmp2\n"
8287 "fast:\n\t"
8288 "DIV $tmp\n"
8289 "done:\n\t"
8290 "MOV EAX,EDX\n\t"
8291 "SAR EDX,31\n\t" %}
8292 ins_encode %{
8293 int con = (int)$imm$$constant;
8294 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8295 int pcon = (con > 0) ? con : -con;
8296 Label Lfast, Lpos, Ldone;
8297
8298 __ movl($tmp$$Register, pcon);
8299 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8300 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8301
8302 __ movl($tmp2$$Register, $dst$$Register); // save
8303 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8304 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8305 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8306
8307 // Negative dividend.
8308 // convert value to positive to use unsigned division
8309 __ lneg($dst$$Register, $tmp2$$Register);
8310 __ divl($tmp$$Register);
8311 __ movl($dst$$Register, $tmp2$$Register);
8312 __ divl($tmp$$Register);
8313 // revert remainder back to negative
8314 __ negl(HIGH_FROM_LOW($dst$$Register));
8315 __ jmpb(Ldone);
8316
8317 __ bind(Lpos);
8318 __ divl($tmp$$Register);
8319 __ movl($dst$$Register, $tmp2$$Register);
8320
8321 __ bind(Lfast);
8322 // fast path: src is positive
8323 __ divl($tmp$$Register);
8324
8325 __ bind(Ldone);
8326 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8327 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8328
8329 %}
8330 ins_pipe( pipe_slow );
8331 %}
8332
8333 // Integer Shift Instructions
8334 // Shift Left by one
8335 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8336 match(Set dst (LShiftI dst shift));
8337 effect(KILL cr);
8338
8339 size(2);
8340 format %{ "SHL $dst,$shift" %}
8341 opcode(0xD1, 0x4); /* D1 /4 */
8342 ins_encode( OpcP, RegOpc( dst ) );
8343 ins_pipe( ialu_reg );
8344 %}
8345
8346 // Shift Left by 8-bit immediate
8347 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8348 match(Set dst (LShiftI dst shift));
8349 effect(KILL cr);
8350
8351 size(3);
8352 format %{ "SHL $dst,$shift" %}
8353 opcode(0xC1, 0x4); /* C1 /4 ib */
8354 ins_encode( RegOpcImm( dst, shift) );
8355 ins_pipe( ialu_reg );
8356 %}
8357
8358 // Shift Left by variable
8359 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8360 match(Set dst (LShiftI dst shift));
8361 effect(KILL cr);
8362
8363 size(2);
8364 format %{ "SHL $dst,$shift" %}
8365 opcode(0xD3, 0x4); /* D3 /4 */
8366 ins_encode( OpcP, RegOpc( dst ) );
8367 ins_pipe( ialu_reg_reg );
8368 %}
8369
8370 // Arithmetic shift right by one
8371 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8372 match(Set dst (RShiftI dst shift));
8373 effect(KILL cr);
8374
8375 size(2);
8376 format %{ "SAR $dst,$shift" %}
8377 opcode(0xD1, 0x7); /* D1 /7 */
8378 ins_encode( OpcP, RegOpc( dst ) );
8379 ins_pipe( ialu_reg );
8380 %}
8381
8382 // Arithmetic shift right by one
8383 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8384 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8385 effect(KILL cr);
8386 format %{ "SAR $dst,$shift" %}
8387 opcode(0xD1, 0x7); /* D1 /7 */
8388 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8389 ins_pipe( ialu_mem_imm );
8390 %}
8391
8392 // Arithmetic Shift Right by 8-bit immediate
8393 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8394 match(Set dst (RShiftI dst shift));
8395 effect(KILL cr);
8396
8397 size(3);
8398 format %{ "SAR $dst,$shift" %}
8399 opcode(0xC1, 0x7); /* C1 /7 ib */
8400 ins_encode( RegOpcImm( dst, shift ) );
8401 ins_pipe( ialu_mem_imm );
8402 %}
8403
8404 // Arithmetic Shift Right by 8-bit immediate
8405 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8406 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8407 effect(KILL cr);
8408
8409 format %{ "SAR $dst,$shift" %}
8410 opcode(0xC1, 0x7); /* C1 /7 ib */
8411 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8412 ins_pipe( ialu_mem_imm );
8413 %}
8414
8415 // Arithmetic Shift Right by variable
8416 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8417 match(Set dst (RShiftI dst shift));
8418 effect(KILL cr);
8419
8420 size(2);
8421 format %{ "SAR $dst,$shift" %}
8422 opcode(0xD3, 0x7); /* D3 /7 */
8423 ins_encode( OpcP, RegOpc( dst ) );
8424 ins_pipe( ialu_reg_reg );
8425 %}
8426
8427 // Logical shift right by one
8428 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8429 match(Set dst (URShiftI dst shift));
8430 effect(KILL cr);
8431
8432 size(2);
8433 format %{ "SHR $dst,$shift" %}
8434 opcode(0xD1, 0x5); /* D1 /5 */
8435 ins_encode( OpcP, RegOpc( dst ) );
8436 ins_pipe( ialu_reg );
8437 %}
8438
8439 // Logical Shift Right by 8-bit immediate
8440 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8441 match(Set dst (URShiftI dst shift));
8442 effect(KILL cr);
8443
8444 size(3);
8445 format %{ "SHR $dst,$shift" %}
8446 opcode(0xC1, 0x5); /* C1 /5 ib */
8447 ins_encode( RegOpcImm( dst, shift) );
8448 ins_pipe( ialu_reg );
8449 %}
8450
8451
8452 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8453 // This idiom is used by the compiler for the i2b bytecode.
8454 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8455 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8456
8457 size(3);
8458 format %{ "MOVSX $dst,$src :8" %}
8459 ins_encode %{
8460 __ movsbl($dst$$Register, $src$$Register);
8461 %}
8462 ins_pipe(ialu_reg_reg);
8463 %}
8464
8465 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8466 // This idiom is used by the compiler the i2s bytecode.
8467 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8468 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8469
8470 size(3);
8471 format %{ "MOVSX $dst,$src :16" %}
8472 ins_encode %{
8473 __ movswl($dst$$Register, $src$$Register);
8474 %}
8475 ins_pipe(ialu_reg_reg);
8476 %}
8477
8478
8479 // Logical Shift Right by variable
8480 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8481 match(Set dst (URShiftI dst shift));
8482 effect(KILL cr);
8483
8484 size(2);
8485 format %{ "SHR $dst,$shift" %}
8486 opcode(0xD3, 0x5); /* D3 /5 */
8487 ins_encode( OpcP, RegOpc( dst ) );
8488 ins_pipe( ialu_reg_reg );
8489 %}
8490
8491
8492 //----------Logical Instructions-----------------------------------------------
8493 //----------Integer Logical Instructions---------------------------------------
8494 // And Instructions
8495 // And Register with Register
8496 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8497 match(Set dst (AndI dst src));
8498 effect(KILL cr);
8499
8500 size(2);
8501 format %{ "AND $dst,$src" %}
8502 opcode(0x23);
8503 ins_encode( OpcP, RegReg( dst, src) );
8504 ins_pipe( ialu_reg_reg );
8505 %}
8506
8507 // And Register with Immediate
8508 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8509 match(Set dst (AndI dst src));
8510 effect(KILL cr);
8511
8512 format %{ "AND $dst,$src" %}
8513 opcode(0x81,0x04); /* Opcode 81 /4 */
8514 // ins_encode( RegImm( dst, src) );
8515 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8516 ins_pipe( ialu_reg );
8517 %}
8518
8519 // And Register with Memory
8520 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8521 match(Set dst (AndI dst (LoadI src)));
8522 effect(KILL cr);
8523
8524 ins_cost(125);
8525 format %{ "AND $dst,$src" %}
8526 opcode(0x23);
8527 ins_encode( OpcP, RegMem( dst, src) );
8528 ins_pipe( ialu_reg_mem );
8529 %}
8530
8531 // And Memory with Register
8532 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8533 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8534 effect(KILL cr);
8535
8536 ins_cost(150);
8537 format %{ "AND $dst,$src" %}
8538 opcode(0x21); /* Opcode 21 /r */
8539 ins_encode( OpcP, RegMem( src, dst ) );
8540 ins_pipe( ialu_mem_reg );
8541 %}
8542
8543 // And Memory with Immediate
8544 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8545 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8546 effect(KILL cr);
8547
8548 ins_cost(125);
8549 format %{ "AND $dst,$src" %}
8550 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8551 // ins_encode( MemImm( dst, src) );
8552 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8553 ins_pipe( ialu_mem_imm );
8554 %}
8555
8556 // Or Instructions
8557 // Or Register with Register
8558 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8559 match(Set dst (OrI dst src));
8560 effect(KILL cr);
8561
8562 size(2);
8563 format %{ "OR $dst,$src" %}
8564 opcode(0x0B);
8565 ins_encode( OpcP, RegReg( dst, src) );
8566 ins_pipe( ialu_reg_reg );
8567 %}
8568
8569 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8570 match(Set dst (OrI dst (CastP2X src)));
8571 effect(KILL cr);
8572
8573 size(2);
8574 format %{ "OR $dst,$src" %}
8575 opcode(0x0B);
8576 ins_encode( OpcP, RegReg( dst, src) );
8577 ins_pipe( ialu_reg_reg );
8578 %}
8579
8580
8581 // Or Register with Immediate
8582 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8583 match(Set dst (OrI dst src));
8584 effect(KILL cr);
8585
8586 format %{ "OR $dst,$src" %}
8587 opcode(0x81,0x01); /* Opcode 81 /1 id */
8588 // ins_encode( RegImm( dst, src) );
8589 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8590 ins_pipe( ialu_reg );
8591 %}
8592
8593 // Or Register with Memory
8594 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8595 match(Set dst (OrI dst (LoadI src)));
8596 effect(KILL cr);
8597
8598 ins_cost(125);
8599 format %{ "OR $dst,$src" %}
8600 opcode(0x0B);
8601 ins_encode( OpcP, RegMem( dst, src) );
8602 ins_pipe( ialu_reg_mem );
8603 %}
8604
8605 // Or Memory with Register
8606 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8607 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8608 effect(KILL cr);
8609
8610 ins_cost(150);
8611 format %{ "OR $dst,$src" %}
8612 opcode(0x09); /* Opcode 09 /r */
8613 ins_encode( OpcP, RegMem( src, dst ) );
8614 ins_pipe( ialu_mem_reg );
8615 %}
8616
8617 // Or Memory with Immediate
8618 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8619 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8620 effect(KILL cr);
8621
8622 ins_cost(125);
8623 format %{ "OR $dst,$src" %}
8624 opcode(0x81,0x1); /* Opcode 81 /1 id */
8625 // ins_encode( MemImm( dst, src) );
8626 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8627 ins_pipe( ialu_mem_imm );
8628 %}
8629
8630 // ROL/ROR
8631 // ROL expand
8632 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8633 effect(USE_DEF dst, USE shift, KILL cr);
8634
8635 format %{ "ROL $dst, $shift" %}
8636 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8637 ins_encode( OpcP, RegOpc( dst ));
8638 ins_pipe( ialu_reg );
8639 %}
8640
8641 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8642 effect(USE_DEF dst, USE shift, KILL cr);
8643
8644 format %{ "ROL $dst, $shift" %}
8645 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8646 ins_encode( RegOpcImm(dst, shift) );
8647 ins_pipe(ialu_reg);
8648 %}
8649
8650 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8651 effect(USE_DEF dst, USE shift, KILL cr);
8652
8653 format %{ "ROL $dst, $shift" %}
8654 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8655 ins_encode(OpcP, RegOpc(dst));
8656 ins_pipe( ialu_reg_reg );
8657 %}
8658 // end of ROL expand
8659
8660 // ROL 32bit by one once
8661 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8662 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8663
8664 expand %{
8665 rolI_eReg_imm1(dst, lshift, cr);
8666 %}
8667 %}
8668
8669 // ROL 32bit var by imm8 once
8670 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8671 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8672 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8673
8674 expand %{
8675 rolI_eReg_imm8(dst, lshift, cr);
8676 %}
8677 %}
8678
8679 // ROL 32bit var by var once
8680 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8681 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8682
8683 expand %{
8684 rolI_eReg_CL(dst, shift, cr);
8685 %}
8686 %}
8687
8688 // ROL 32bit var by var once
8689 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8690 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8691
8692 expand %{
8693 rolI_eReg_CL(dst, shift, cr);
8694 %}
8695 %}
8696
8697 // ROR expand
8698 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8699 effect(USE_DEF dst, USE shift, KILL cr);
8700
8701 format %{ "ROR $dst, $shift" %}
8702 opcode(0xD1,0x1); /* Opcode D1 /1 */
8703 ins_encode( OpcP, RegOpc( dst ) );
8704 ins_pipe( ialu_reg );
8705 %}
8706
8707 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8708 effect (USE_DEF dst, USE shift, KILL cr);
8709
8710 format %{ "ROR $dst, $shift" %}
8711 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8712 ins_encode( RegOpcImm(dst, shift) );
8713 ins_pipe( ialu_reg );
8714 %}
8715
8716 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8717 effect(USE_DEF dst, USE shift, KILL cr);
8718
8719 format %{ "ROR $dst, $shift" %}
8720 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8721 ins_encode(OpcP, RegOpc(dst));
8722 ins_pipe( ialu_reg_reg );
8723 %}
8724 // end of ROR expand
8725
8726 // ROR right once
8727 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8728 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8729
8730 expand %{
8731 rorI_eReg_imm1(dst, rshift, cr);
8732 %}
8733 %}
8734
8735 // ROR 32bit by immI8 once
8736 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8737 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8738 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8739
8740 expand %{
8741 rorI_eReg_imm8(dst, rshift, cr);
8742 %}
8743 %}
8744
8745 // ROR 32bit var by var once
8746 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8747 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8748
8749 expand %{
8750 rorI_eReg_CL(dst, shift, cr);
8751 %}
8752 %}
8753
8754 // ROR 32bit var by var once
8755 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8756 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8757
8758 expand %{
8759 rorI_eReg_CL(dst, shift, cr);
8760 %}
8761 %}
8762
8763 // Xor Instructions
8764 // Xor Register with Register
8765 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8766 match(Set dst (XorI dst src));
8767 effect(KILL cr);
8768
8769 size(2);
8770 format %{ "XOR $dst,$src" %}
8771 opcode(0x33);
8772 ins_encode( OpcP, RegReg( dst, src) );
8773 ins_pipe( ialu_reg_reg );
8774 %}
8775
8776 // Xor Register with Immediate -1
8777 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8778 match(Set dst (XorI dst imm));
8779
8780 size(2);
8781 format %{ "NOT $dst" %}
8782 ins_encode %{
8783 __ notl($dst$$Register);
8784 %}
8785 ins_pipe( ialu_reg );
8786 %}
8787
8788 // Xor Register with Immediate
8789 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8790 match(Set dst (XorI dst src));
8791 effect(KILL cr);
8792
8793 format %{ "XOR $dst,$src" %}
8794 opcode(0x81,0x06); /* Opcode 81 /6 id */
8795 // ins_encode( RegImm( dst, src) );
8796 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8797 ins_pipe( ialu_reg );
8798 %}
8799
8800 // Xor Register with Memory
8801 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8802 match(Set dst (XorI dst (LoadI src)));
8803 effect(KILL cr);
8804
8805 ins_cost(125);
8806 format %{ "XOR $dst,$src" %}
8807 opcode(0x33);
8808 ins_encode( OpcP, RegMem(dst, src) );
8809 ins_pipe( ialu_reg_mem );
8810 %}
8811
8812 // Xor Memory with Register
8813 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8814 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8815 effect(KILL cr);
8816
8817 ins_cost(150);
8818 format %{ "XOR $dst,$src" %}
8819 opcode(0x31); /* Opcode 31 /r */
8820 ins_encode( OpcP, RegMem( src, dst ) );
8821 ins_pipe( ialu_mem_reg );
8822 %}
8823
8824 // Xor Memory with Immediate
8825 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8826 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8827 effect(KILL cr);
8828
8829 ins_cost(125);
8830 format %{ "XOR $dst,$src" %}
8831 opcode(0x81,0x6); /* Opcode 81 /6 id */
8832 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8833 ins_pipe( ialu_mem_imm );
8834 %}
8835
8836 //----------Convert Int to Boolean---------------------------------------------
8837
8838 instruct movI_nocopy(rRegI dst, rRegI src) %{
8839 effect( DEF dst, USE src );
8840 format %{ "MOV $dst,$src" %}
8841 ins_encode( enc_Copy( dst, src) );
8842 ins_pipe( ialu_reg_reg );
8843 %}
8844
8845 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8846 effect( USE_DEF dst, USE src, KILL cr );
8847
8848 size(4);
8849 format %{ "NEG $dst\n\t"
8850 "ADC $dst,$src" %}
8851 ins_encode( neg_reg(dst),
8852 OpcRegReg(0x13,dst,src) );
8853 ins_pipe( ialu_reg_reg_long );
8854 %}
8855
8856 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8857 match(Set dst (Conv2B src));
8858
8859 expand %{
8860 movI_nocopy(dst,src);
8861 ci2b(dst,src,cr);
8862 %}
8863 %}
8864
8865 instruct movP_nocopy(rRegI dst, eRegP src) %{
8866 effect( DEF dst, USE src );
8867 format %{ "MOV $dst,$src" %}
8868 ins_encode( enc_Copy( dst, src) );
8869 ins_pipe( ialu_reg_reg );
8870 %}
8871
8872 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8873 effect( USE_DEF dst, USE src, KILL cr );
8874 format %{ "NEG $dst\n\t"
8875 "ADC $dst,$src" %}
8876 ins_encode( neg_reg(dst),
8877 OpcRegReg(0x13,dst,src) );
8878 ins_pipe( ialu_reg_reg_long );
8879 %}
8880
8881 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8882 match(Set dst (Conv2B src));
8883
8884 expand %{
8885 movP_nocopy(dst,src);
8886 cp2b(dst,src,cr);
8887 %}
8888 %}
8889
8890 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8891 match(Set dst (CmpLTMask p q));
8892 effect(KILL cr);
8893 ins_cost(400);
8894
8895 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8896 format %{ "XOR $dst,$dst\n\t"
8897 "CMP $p,$q\n\t"
8898 "SETlt $dst\n\t"
8899 "NEG $dst" %}
8900 ins_encode %{
8901 Register Rp = $p$$Register;
8902 Register Rq = $q$$Register;
8903 Register Rd = $dst$$Register;
8904 Label done;
8905 __ xorl(Rd, Rd);
8906 __ cmpl(Rp, Rq);
8907 __ setb(Assembler::less, Rd);
8908 __ negl(Rd);
8909 %}
8910
8911 ins_pipe(pipe_slow);
8912 %}
8913
8914 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8915 match(Set dst (CmpLTMask dst zero));
8916 effect(DEF dst, KILL cr);
8917 ins_cost(100);
8918
8919 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8920 ins_encode %{
8921 __ sarl($dst$$Register, 31);
8922 %}
8923 ins_pipe(ialu_reg);
8924 %}
8925
8926 /* better to save a register than avoid a branch */
8927 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8928 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8929 effect(KILL cr);
8930 ins_cost(400);
8931 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8932 "JGE done\n\t"
8933 "ADD $p,$y\n"
8934 "done: " %}
8935 ins_encode %{
8936 Register Rp = $p$$Register;
8937 Register Rq = $q$$Register;
8938 Register Ry = $y$$Register;
8939 Label done;
8940 __ subl(Rp, Rq);
8941 __ jccb(Assembler::greaterEqual, done);
8942 __ addl(Rp, Ry);
8943 __ bind(done);
8944 %}
8945
8946 ins_pipe(pipe_cmplt);
8947 %}
8948
8949 /* better to save a register than avoid a branch */
8950 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8951 match(Set y (AndI (CmpLTMask p q) y));
8952 effect(KILL cr);
8953
8954 ins_cost(300);
8955
8956 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8957 "JLT done\n\t"
8958 "XORL $y, $y\n"
8959 "done: " %}
8960 ins_encode %{
8961 Register Rp = $p$$Register;
8962 Register Rq = $q$$Register;
8963 Register Ry = $y$$Register;
8964 Label done;
8965 __ cmpl(Rp, Rq);
8966 __ jccb(Assembler::less, done);
8967 __ xorl(Ry, Ry);
8968 __ bind(done);
8969 %}
8970
8971 ins_pipe(pipe_cmplt);
8972 %}
8973
8974 /* If I enable this, I encourage spilling in the inner loop of compress.
8975 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8976 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8977 */
8978 //----------Overflow Math Instructions-----------------------------------------
8979
8980 instruct addofI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8981 %{
8982 match(Set cr (OverflowAddI op1 op2));
8983 effect(DEF cr, USE_KILL op1, USE op2);
8984
8985 format %{ "ADD $op1, $op2 #overflow check int" %}
8986
8987 ins_encode %{
8988 __ addl($op1$$Register, $op2$$Register);
8989 %}
8990 ins_pipe(ialu_reg_reg);
8991 %}
8992
8993 instruct addofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8994 %{
8995 match(Set cr (OverflowAddI op1 op2));
8996 effect(DEF cr, USE_KILL op1, USE op2);
8997
8998 format %{ "ADD $op1, $op2 #overflow check int" %}
8999
9000 ins_encode %{
9001 __ addl($op1$$Register, $op2$$constant);
9002 %}
9003 ins_pipe(ialu_reg_reg);
9004 %}
9005
9006 instruct subofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9007 %{
9008 match(Set cr (OverflowSubI op1 op2));
9009 effect(DEF cr, USE_KILL op1, USE op2);
9010
9011 format %{ "SUB $op1, $op2 #overflow check int" %}
9012 ins_encode %{
9013 __ subl($op1$$Register, $op2$$Register);
9014 %}
9015 ins_pipe(ialu_reg_reg);
9016 %}
9017
9018 instruct subofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
9019 %{
9020 match(Set cr (OverflowSubI op1 op2));
9021 effect(DEF cr, USE_KILL op1, USE op2);
9022
9023 format %{ "SUB $op1, $op2 #overflow check int" %}
9024 ins_encode %{
9025 __ subl($op1$$Register, $op2$$constant);
9026 %}
9027 ins_pipe(ialu_reg_reg);
9028 %}
9029
9030 instruct negofI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
9031 %{
9032 match(Set cr (OverflowSubI zero op2));
9033 effect(DEF cr, USE_KILL op2);
9034
9035 format %{ "NEG $op2 #overflow check int" %}
9036 ins_encode %{
9037 __ negl($op2$$Register);
9038 %}
9039 ins_pipe(ialu_reg_reg);
9040 %}
9041
9042 instruct mulofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9043 %{
9044 match(Set cr (OverflowMulI op1 op2));
9045 effect(DEF cr, USE_KILL op1, USE op2);
9046
9047 format %{ "IMUL $op1, $op2 #overflow check int" %}
9048 ins_encode %{
9049 __ imull($op1$$Register, $op2$$Register);
9050 %}
9051 ins_pipe(ialu_reg_reg);
9052 %}
9053
9054 instruct mulofI_rReg_imm(eFlagsReg cr, eAXRegI op1, rRegI op2, immI op3)
9055 %{
9056 match(Set cr (OverflowMulI op2 op3));
9057 effect(DEF cr, KILL op1, USE op2, USE op3);
9058
9059 format %{ "IMUL $op1, $op2 #overflow check int" %}
9060 ins_encode %{
9061 __ imull($op1$$Register, $op2$$Register, $op3$$constant);
9062 %}
9063 ins_pipe(ialu_reg_reg);
9064 %}
9065
9066 //----------Long Instructions------------------------------------------------
9067 // Add Long Register with Register
9068 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9069 match(Set dst (AddL dst src));
9070 effect(KILL cr);
9071 ins_cost(200);
9072 format %{ "ADD $dst.lo,$src.lo\n\t"
9073 "ADC $dst.hi,$src.hi" %}
9074 opcode(0x03, 0x13);
9075 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9076 ins_pipe( ialu_reg_reg_long );
9077 %}
9078
9079 // Add Long Register with Immediate
9080 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9081 match(Set dst (AddL dst src));
9082 effect(KILL cr);
9083 format %{ "ADD $dst.lo,$src.lo\n\t"
9084 "ADC $dst.hi,$src.hi" %}
9085 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9086 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9087 ins_pipe( ialu_reg_long );
9088 %}
9089
9090 // Add Long Register with Memory
9091 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9092 match(Set dst (AddL dst (LoadL mem)));
9093 effect(KILL cr);
9094 ins_cost(125);
9095 format %{ "ADD $dst.lo,$mem\n\t"
9096 "ADC $dst.hi,$mem+4" %}
9097 opcode(0x03, 0x13);
9098 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9099 ins_pipe( ialu_reg_long_mem );
9100 %}
9101
9102 // Subtract Long Register with Register.
9103 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9104 match(Set dst (SubL dst src));
9105 effect(KILL cr);
9106 ins_cost(200);
9107 format %{ "SUB $dst.lo,$src.lo\n\t"
9108 "SBB $dst.hi,$src.hi" %}
9109 opcode(0x2B, 0x1B);
9110 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9111 ins_pipe( ialu_reg_reg_long );
9112 %}
9113
9114 // Subtract Long Register with Immediate
9115 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9116 match(Set dst (SubL dst src));
9117 effect(KILL cr);
9118 format %{ "SUB $dst.lo,$src.lo\n\t"
9119 "SBB $dst.hi,$src.hi" %}
9120 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9121 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9122 ins_pipe( ialu_reg_long );
9123 %}
9124
9125 // Subtract Long Register with Memory
9126 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9127 match(Set dst (SubL dst (LoadL mem)));
9128 effect(KILL cr);
9129 ins_cost(125);
9130 format %{ "SUB $dst.lo,$mem\n\t"
9131 "SBB $dst.hi,$mem+4" %}
9132 opcode(0x2B, 0x1B);
9133 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9134 ins_pipe( ialu_reg_long_mem );
9135 %}
9136
9137 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9138 match(Set dst (SubL zero dst));
9139 effect(KILL cr);
9140 ins_cost(300);
9141 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9142 ins_encode( neg_long(dst) );
9143 ins_pipe( ialu_reg_reg_long );
9144 %}
9145
9146 // And Long Register with Register
9147 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9148 match(Set dst (AndL dst src));
9149 effect(KILL cr);
9150 format %{ "AND $dst.lo,$src.lo\n\t"
9151 "AND $dst.hi,$src.hi" %}
9152 opcode(0x23,0x23);
9153 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9154 ins_pipe( ialu_reg_reg_long );
9155 %}
9156
9157 // And Long Register with Immediate
9158 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9159 match(Set dst (AndL dst src));
9160 effect(KILL cr);
9161 format %{ "AND $dst.lo,$src.lo\n\t"
9162 "AND $dst.hi,$src.hi" %}
9163 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9164 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9165 ins_pipe( ialu_reg_long );
9166 %}
9167
9168 // And Long Register with Memory
9169 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9170 match(Set dst (AndL dst (LoadL mem)));
9171 effect(KILL cr);
9172 ins_cost(125);
9173 format %{ "AND $dst.lo,$mem\n\t"
9174 "AND $dst.hi,$mem+4" %}
9175 opcode(0x23, 0x23);
9176 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9177 ins_pipe( ialu_reg_long_mem );
9178 %}
9179
9180 // Or Long Register with Register
9181 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9182 match(Set dst (OrL dst src));
9183 effect(KILL cr);
9184 format %{ "OR $dst.lo,$src.lo\n\t"
9185 "OR $dst.hi,$src.hi" %}
9186 opcode(0x0B,0x0B);
9187 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9188 ins_pipe( ialu_reg_reg_long );
9189 %}
9190
9191 // Or Long Register with Immediate
9192 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9193 match(Set dst (OrL dst src));
9194 effect(KILL cr);
9195 format %{ "OR $dst.lo,$src.lo\n\t"
9196 "OR $dst.hi,$src.hi" %}
9197 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9198 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9199 ins_pipe( ialu_reg_long );
9200 %}
9201
9202 // Or Long Register with Memory
9203 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9204 match(Set dst (OrL dst (LoadL mem)));
9205 effect(KILL cr);
9206 ins_cost(125);
9207 format %{ "OR $dst.lo,$mem\n\t"
9208 "OR $dst.hi,$mem+4" %}
9209 opcode(0x0B,0x0B);
9210 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9211 ins_pipe( ialu_reg_long_mem );
9212 %}
9213
9214 // Xor Long Register with Register
9215 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9216 match(Set dst (XorL dst src));
9217 effect(KILL cr);
9218 format %{ "XOR $dst.lo,$src.lo\n\t"
9219 "XOR $dst.hi,$src.hi" %}
9220 opcode(0x33,0x33);
9221 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9222 ins_pipe( ialu_reg_reg_long );
9223 %}
9224
9225 // Xor Long Register with Immediate -1
9226 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9227 match(Set dst (XorL dst imm));
9228 format %{ "NOT $dst.lo\n\t"
9229 "NOT $dst.hi" %}
9230 ins_encode %{
9231 __ notl($dst$$Register);
9232 __ notl(HIGH_FROM_LOW($dst$$Register));
9233 %}
9234 ins_pipe( ialu_reg_long );
9235 %}
9236
9237 // Xor Long Register with Immediate
9238 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9239 match(Set dst (XorL dst src));
9240 effect(KILL cr);
9241 format %{ "XOR $dst.lo,$src.lo\n\t"
9242 "XOR $dst.hi,$src.hi" %}
9243 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9244 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9245 ins_pipe( ialu_reg_long );
9246 %}
9247
9248 // Xor Long Register with Memory
9249 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9250 match(Set dst (XorL dst (LoadL mem)));
9251 effect(KILL cr);
9252 ins_cost(125);
9253 format %{ "XOR $dst.lo,$mem\n\t"
9254 "XOR $dst.hi,$mem+4" %}
9255 opcode(0x33,0x33);
9256 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9257 ins_pipe( ialu_reg_long_mem );
9258 %}
9259
9260 // Shift Left Long by 1
9261 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9262 predicate(UseNewLongLShift);
9263 match(Set dst (LShiftL dst cnt));
9264 effect(KILL cr);
9265 ins_cost(100);
9266 format %{ "ADD $dst.lo,$dst.lo\n\t"
9267 "ADC $dst.hi,$dst.hi" %}
9268 ins_encode %{
9269 __ addl($dst$$Register,$dst$$Register);
9270 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9271 %}
9272 ins_pipe( ialu_reg_long );
9273 %}
9274
9275 // Shift Left Long by 2
9276 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9277 predicate(UseNewLongLShift);
9278 match(Set dst (LShiftL dst cnt));
9279 effect(KILL cr);
9280 ins_cost(100);
9281 format %{ "ADD $dst.lo,$dst.lo\n\t"
9282 "ADC $dst.hi,$dst.hi\n\t"
9283 "ADD $dst.lo,$dst.lo\n\t"
9284 "ADC $dst.hi,$dst.hi" %}
9285 ins_encode %{
9286 __ addl($dst$$Register,$dst$$Register);
9287 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9288 __ addl($dst$$Register,$dst$$Register);
9289 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9290 %}
9291 ins_pipe( ialu_reg_long );
9292 %}
9293
9294 // Shift Left Long by 3
9295 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9296 predicate(UseNewLongLShift);
9297 match(Set dst (LShiftL dst cnt));
9298 effect(KILL cr);
9299 ins_cost(100);
9300 format %{ "ADD $dst.lo,$dst.lo\n\t"
9301 "ADC $dst.hi,$dst.hi\n\t"
9302 "ADD $dst.lo,$dst.lo\n\t"
9303 "ADC $dst.hi,$dst.hi\n\t"
9304 "ADD $dst.lo,$dst.lo\n\t"
9305 "ADC $dst.hi,$dst.hi" %}
9306 ins_encode %{
9307 __ addl($dst$$Register,$dst$$Register);
9308 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9309 __ addl($dst$$Register,$dst$$Register);
9310 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9311 __ addl($dst$$Register,$dst$$Register);
9312 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9313 %}
9314 ins_pipe( ialu_reg_long );
9315 %}
9316
9317 // Shift Left Long by 1-31
9318 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9319 match(Set dst (LShiftL dst cnt));
9320 effect(KILL cr);
9321 ins_cost(200);
9322 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9323 "SHL $dst.lo,$cnt" %}
9324 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9325 ins_encode( move_long_small_shift(dst,cnt) );
9326 ins_pipe( ialu_reg_long );
9327 %}
9328
9329 // Shift Left Long by 32-63
9330 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9331 match(Set dst (LShiftL dst cnt));
9332 effect(KILL cr);
9333 ins_cost(300);
9334 format %{ "MOV $dst.hi,$dst.lo\n"
9335 "\tSHL $dst.hi,$cnt-32\n"
9336 "\tXOR $dst.lo,$dst.lo" %}
9337 opcode(0xC1, 0x4); /* C1 /4 ib */
9338 ins_encode( move_long_big_shift_clr(dst,cnt) );
9339 ins_pipe( ialu_reg_long );
9340 %}
9341
9342 // Shift Left Long by variable
9343 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9344 match(Set dst (LShiftL dst shift));
9345 effect(KILL cr);
9346 ins_cost(500+200);
9347 size(17);
9348 format %{ "TEST $shift,32\n\t"
9349 "JEQ,s small\n\t"
9350 "MOV $dst.hi,$dst.lo\n\t"
9351 "XOR $dst.lo,$dst.lo\n"
9352 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9353 "SHL $dst.lo,$shift" %}
9354 ins_encode( shift_left_long( dst, shift ) );
9355 ins_pipe( pipe_slow );
9356 %}
9357
9358 // Shift Right Long by 1-31
9359 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9360 match(Set dst (URShiftL dst cnt));
9361 effect(KILL cr);
9362 ins_cost(200);
9363 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9364 "SHR $dst.hi,$cnt" %}
9365 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9366 ins_encode( move_long_small_shift(dst,cnt) );
9367 ins_pipe( ialu_reg_long );
9368 %}
9369
9370 // Shift Right Long by 32-63
9371 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9372 match(Set dst (URShiftL dst cnt));
9373 effect(KILL cr);
9374 ins_cost(300);
9375 format %{ "MOV $dst.lo,$dst.hi\n"
9376 "\tSHR $dst.lo,$cnt-32\n"
9377 "\tXOR $dst.hi,$dst.hi" %}
9378 opcode(0xC1, 0x5); /* C1 /5 ib */
9379 ins_encode( move_long_big_shift_clr(dst,cnt) );
9380 ins_pipe( ialu_reg_long );
9381 %}
9382
9383 // Shift Right Long by variable
9384 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9385 match(Set dst (URShiftL dst shift));
9386 effect(KILL cr);
9387 ins_cost(600);
9388 size(17);
9389 format %{ "TEST $shift,32\n\t"
9390 "JEQ,s small\n\t"
9391 "MOV $dst.lo,$dst.hi\n\t"
9392 "XOR $dst.hi,$dst.hi\n"
9393 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9394 "SHR $dst.hi,$shift" %}
9395 ins_encode( shift_right_long( dst, shift ) );
9396 ins_pipe( pipe_slow );
9397 %}
9398
9399 // Shift Right Long by 1-31
9400 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9401 match(Set dst (RShiftL dst cnt));
9402 effect(KILL cr);
9403 ins_cost(200);
9404 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9405 "SAR $dst.hi,$cnt" %}
9406 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9407 ins_encode( move_long_small_shift(dst,cnt) );
9408 ins_pipe( ialu_reg_long );
9409 %}
9410
9411 // Shift Right Long by 32-63
9412 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9413 match(Set dst (RShiftL dst cnt));
9414 effect(KILL cr);
9415 ins_cost(300);
9416 format %{ "MOV $dst.lo,$dst.hi\n"
9417 "\tSAR $dst.lo,$cnt-32\n"
9418 "\tSAR $dst.hi,31" %}
9419 opcode(0xC1, 0x7); /* C1 /7 ib */
9420 ins_encode( move_long_big_shift_sign(dst,cnt) );
9421 ins_pipe( ialu_reg_long );
9422 %}
9423
9424 // Shift Right arithmetic Long by variable
9425 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9426 match(Set dst (RShiftL dst shift));
9427 effect(KILL cr);
9428 ins_cost(600);
9429 size(18);
9430 format %{ "TEST $shift,32\n\t"
9431 "JEQ,s small\n\t"
9432 "MOV $dst.lo,$dst.hi\n\t"
9433 "SAR $dst.hi,31\n"
9434 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9435 "SAR $dst.hi,$shift" %}
9436 ins_encode( shift_right_arith_long( dst, shift ) );
9437 ins_pipe( pipe_slow );
9438 %}
9439
9440
9441 //----------Double Instructions------------------------------------------------
9442 // Double Math
9443
9444 // Compare & branch
9445
9446 // P6 version of float compare, sets condition codes in EFLAGS
9447 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9448 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9449 match(Set cr (CmpD src1 src2));
9450 effect(KILL rax);
9451 ins_cost(150);
9452 format %{ "FLD $src1\n\t"
9453 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9454 "JNP exit\n\t"
9455 "MOV ah,1 // saw a NaN, set CF\n\t"
9456 "SAHF\n"
9457 "exit:\tNOP // avoid branch to branch" %}
9458 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9459 ins_encode( Push_Reg_DPR(src1),
9460 OpcP, RegOpc(src2),
9461 cmpF_P6_fixup );
9462 ins_pipe( pipe_slow );
9463 %}
9464
9465 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9466 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9467 match(Set cr (CmpD src1 src2));
9468 ins_cost(150);
9469 format %{ "FLD $src1\n\t"
9470 "FUCOMIP ST,$src2 // P6 instruction" %}
9471 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9472 ins_encode( Push_Reg_DPR(src1),
9473 OpcP, RegOpc(src2));
9474 ins_pipe( pipe_slow );
9475 %}
9476
9477 // Compare & branch
9478 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9479 predicate(UseSSE<=1);
9480 match(Set cr (CmpD src1 src2));
9481 effect(KILL rax);
9482 ins_cost(200);
9483 format %{ "FLD $src1\n\t"
9484 "FCOMp $src2\n\t"
9485 "FNSTSW AX\n\t"
9486 "TEST AX,0x400\n\t"
9487 "JZ,s flags\n\t"
9488 "MOV AH,1\t# unordered treat as LT\n"
9489 "flags:\tSAHF" %}
9490 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9491 ins_encode( Push_Reg_DPR(src1),
9492 OpcP, RegOpc(src2),
9493 fpu_flags);
9494 ins_pipe( pipe_slow );
9495 %}
9496
9497 // Compare vs zero into -1,0,1
9498 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9499 predicate(UseSSE<=1);
9500 match(Set dst (CmpD3 src1 zero));
9501 effect(KILL cr, KILL rax);
9502 ins_cost(280);
9503 format %{ "FTSTD $dst,$src1" %}
9504 opcode(0xE4, 0xD9);
9505 ins_encode( Push_Reg_DPR(src1),
9506 OpcS, OpcP, PopFPU,
9507 CmpF_Result(dst));
9508 ins_pipe( pipe_slow );
9509 %}
9510
9511 // Compare into -1,0,1
9512 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9513 predicate(UseSSE<=1);
9514 match(Set dst (CmpD3 src1 src2));
9515 effect(KILL cr, KILL rax);
9516 ins_cost(300);
9517 format %{ "FCMPD $dst,$src1,$src2" %}
9518 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9519 ins_encode( Push_Reg_DPR(src1),
9520 OpcP, RegOpc(src2),
9521 CmpF_Result(dst));
9522 ins_pipe( pipe_slow );
9523 %}
9524
9525 // float compare and set condition codes in EFLAGS by XMM regs
9526 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9527 predicate(UseSSE>=2);
9528 match(Set cr (CmpD src1 src2));
9529 ins_cost(145);
9530 format %{ "UCOMISD $src1,$src2\n\t"
9531 "JNP,s exit\n\t"
9532 "PUSHF\t# saw NaN, set CF\n\t"
9533 "AND [rsp], #0xffffff2b\n\t"
9534 "POPF\n"
9535 "exit:" %}
9536 ins_encode %{
9537 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9538 emit_cmpfp_fixup(_masm);
9539 %}
9540 ins_pipe( pipe_slow );
9541 %}
9542
9543 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9544 predicate(UseSSE>=2);
9545 match(Set cr (CmpD src1 src2));
9546 ins_cost(100);
9547 format %{ "UCOMISD $src1,$src2" %}
9548 ins_encode %{
9549 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9550 %}
9551 ins_pipe( pipe_slow );
9552 %}
9553
9554 // float compare and set condition codes in EFLAGS by XMM regs
9555 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9556 predicate(UseSSE>=2);
9557 match(Set cr (CmpD src1 (LoadD src2)));
9558 ins_cost(145);
9559 format %{ "UCOMISD $src1,$src2\n\t"
9560 "JNP,s exit\n\t"
9561 "PUSHF\t# saw NaN, set CF\n\t"
9562 "AND [rsp], #0xffffff2b\n\t"
9563 "POPF\n"
9564 "exit:" %}
9565 ins_encode %{
9566 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9567 emit_cmpfp_fixup(_masm);
9568 %}
9569 ins_pipe( pipe_slow );
9570 %}
9571
9572 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9573 predicate(UseSSE>=2);
9574 match(Set cr (CmpD src1 (LoadD src2)));
9575 ins_cost(100);
9576 format %{ "UCOMISD $src1,$src2" %}
9577 ins_encode %{
9578 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9579 %}
9580 ins_pipe( pipe_slow );
9581 %}
9582
9583 // Compare into -1,0,1 in XMM
9584 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9585 predicate(UseSSE>=2);
9586 match(Set dst (CmpD3 src1 src2));
9587 effect(KILL cr);
9588 ins_cost(255);
9589 format %{ "UCOMISD $src1, $src2\n\t"
9590 "MOV $dst, #-1\n\t"
9591 "JP,s done\n\t"
9592 "JB,s done\n\t"
9593 "SETNE $dst\n\t"
9594 "MOVZB $dst, $dst\n"
9595 "done:" %}
9596 ins_encode %{
9597 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9598 emit_cmpfp3(_masm, $dst$$Register);
9599 %}
9600 ins_pipe( pipe_slow );
9601 %}
9602
9603 // Compare into -1,0,1 in XMM and memory
9604 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9605 predicate(UseSSE>=2);
9606 match(Set dst (CmpD3 src1 (LoadD src2)));
9607 effect(KILL cr);
9608 ins_cost(275);
9609 format %{ "UCOMISD $src1, $src2\n\t"
9610 "MOV $dst, #-1\n\t"
9611 "JP,s done\n\t"
9612 "JB,s done\n\t"
9613 "SETNE $dst\n\t"
9614 "MOVZB $dst, $dst\n"
9615 "done:" %}
9616 ins_encode %{
9617 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9618 emit_cmpfp3(_masm, $dst$$Register);
9619 %}
9620 ins_pipe( pipe_slow );
9621 %}
9622
9623
9624 instruct subDPR_reg(regDPR dst, regDPR src) %{
9625 predicate (UseSSE <=1);
9626 match(Set dst (SubD dst src));
9627
9628 format %{ "FLD $src\n\t"
9629 "DSUBp $dst,ST" %}
9630 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9631 ins_cost(150);
9632 ins_encode( Push_Reg_DPR(src),
9633 OpcP, RegOpc(dst) );
9634 ins_pipe( fpu_reg_reg );
9635 %}
9636
9637 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9638 predicate (UseSSE <=1);
9639 match(Set dst (RoundDouble (SubD src1 src2)));
9640 ins_cost(250);
9641
9642 format %{ "FLD $src2\n\t"
9643 "DSUB ST,$src1\n\t"
9644 "FSTP_D $dst\t# D-round" %}
9645 opcode(0xD8, 0x5);
9646 ins_encode( Push_Reg_DPR(src2),
9647 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9648 ins_pipe( fpu_mem_reg_reg );
9649 %}
9650
9651
9652 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9653 predicate (UseSSE <=1);
9654 match(Set dst (SubD dst (LoadD src)));
9655 ins_cost(150);
9656
9657 format %{ "FLD $src\n\t"
9658 "DSUBp $dst,ST" %}
9659 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9660 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9661 OpcP, RegOpc(dst) );
9662 ins_pipe( fpu_reg_mem );
9663 %}
9664
9665 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9666 predicate (UseSSE<=1);
9667 match(Set dst (AbsD src));
9668 ins_cost(100);
9669 format %{ "FABS" %}
9670 opcode(0xE1, 0xD9);
9671 ins_encode( OpcS, OpcP );
9672 ins_pipe( fpu_reg_reg );
9673 %}
9674
9675 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9676 predicate(UseSSE<=1);
9677 match(Set dst (NegD src));
9678 ins_cost(100);
9679 format %{ "FCHS" %}
9680 opcode(0xE0, 0xD9);
9681 ins_encode( OpcS, OpcP );
9682 ins_pipe( fpu_reg_reg );
9683 %}
9684
9685 instruct addDPR_reg(regDPR dst, regDPR src) %{
9686 predicate(UseSSE<=1);
9687 match(Set dst (AddD dst src));
9688 format %{ "FLD $src\n\t"
9689 "DADD $dst,ST" %}
9690 size(4);
9691 ins_cost(150);
9692 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9693 ins_encode( Push_Reg_DPR(src),
9694 OpcP, RegOpc(dst) );
9695 ins_pipe( fpu_reg_reg );
9696 %}
9697
9698
9699 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9700 predicate(UseSSE<=1);
9701 match(Set dst (RoundDouble (AddD src1 src2)));
9702 ins_cost(250);
9703
9704 format %{ "FLD $src2\n\t"
9705 "DADD ST,$src1\n\t"
9706 "FSTP_D $dst\t# D-round" %}
9707 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9708 ins_encode( Push_Reg_DPR(src2),
9709 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9710 ins_pipe( fpu_mem_reg_reg );
9711 %}
9712
9713
9714 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9715 predicate(UseSSE<=1);
9716 match(Set dst (AddD dst (LoadD src)));
9717 ins_cost(150);
9718
9719 format %{ "FLD $src\n\t"
9720 "DADDp $dst,ST" %}
9721 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9722 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9723 OpcP, RegOpc(dst) );
9724 ins_pipe( fpu_reg_mem );
9725 %}
9726
9727 // add-to-memory
9728 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9729 predicate(UseSSE<=1);
9730 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9731 ins_cost(150);
9732
9733 format %{ "FLD_D $dst\n\t"
9734 "DADD ST,$src\n\t"
9735 "FST_D $dst" %}
9736 opcode(0xDD, 0x0);
9737 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9738 Opcode(0xD8), RegOpc(src),
9739 set_instruction_start,
9740 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9741 ins_pipe( fpu_reg_mem );
9742 %}
9743
9744 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9745 predicate(UseSSE<=1);
9746 match(Set dst (AddD dst con));
9747 ins_cost(125);
9748 format %{ "FLD1\n\t"
9749 "DADDp $dst,ST" %}
9750 ins_encode %{
9751 __ fld1();
9752 __ faddp($dst$$reg);
9753 %}
9754 ins_pipe(fpu_reg);
9755 %}
9756
9757 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9758 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9759 match(Set dst (AddD dst con));
9760 ins_cost(200);
9761 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9762 "DADDp $dst,ST" %}
9763 ins_encode %{
9764 __ fld_d($constantaddress($con));
9765 __ faddp($dst$$reg);
9766 %}
9767 ins_pipe(fpu_reg_mem);
9768 %}
9769
9770 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9771 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9772 match(Set dst (RoundDouble (AddD src con)));
9773 ins_cost(200);
9774 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9775 "DADD ST,$src\n\t"
9776 "FSTP_D $dst\t# D-round" %}
9777 ins_encode %{
9778 __ fld_d($constantaddress($con));
9779 __ fadd($src$$reg);
9780 __ fstp_d(Address(rsp, $dst$$disp));
9781 %}
9782 ins_pipe(fpu_mem_reg_con);
9783 %}
9784
9785 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9786 predicate(UseSSE<=1);
9787 match(Set dst (MulD dst src));
9788 format %{ "FLD $src\n\t"
9789 "DMULp $dst,ST" %}
9790 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9791 ins_cost(150);
9792 ins_encode( Push_Reg_DPR(src),
9793 OpcP, RegOpc(dst) );
9794 ins_pipe( fpu_reg_reg );
9795 %}
9796
9797 // Strict FP instruction biases argument before multiply then
9798 // biases result to avoid double rounding of subnormals.
9799 //
9800 // scale arg1 by multiplying arg1 by 2^(-15360)
9801 // load arg2
9802 // multiply scaled arg1 by arg2
9803 // rescale product by 2^(15360)
9804 //
9805 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9806 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9807 match(Set dst (MulD dst src));
9808 ins_cost(1); // Select this instruction for all strict FP double multiplies
9809
9810 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9811 "DMULp $dst,ST\n\t"
9812 "FLD $src\n\t"
9813 "DMULp $dst,ST\n\t"
9814 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9815 "DMULp $dst,ST\n\t" %}
9816 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9817 ins_encode( strictfp_bias1(dst),
9818 Push_Reg_DPR(src),
9819 OpcP, RegOpc(dst),
9820 strictfp_bias2(dst) );
9821 ins_pipe( fpu_reg_reg );
9822 %}
9823
9824 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9825 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9826 match(Set dst (MulD dst con));
9827 ins_cost(200);
9828 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9829 "DMULp $dst,ST" %}
9830 ins_encode %{
9831 __ fld_d($constantaddress($con));
9832 __ fmulp($dst$$reg);
9833 %}
9834 ins_pipe(fpu_reg_mem);
9835 %}
9836
9837
9838 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9839 predicate( UseSSE<=1 );
9840 match(Set dst (MulD dst (LoadD src)));
9841 ins_cost(200);
9842 format %{ "FLD_D $src\n\t"
9843 "DMULp $dst,ST" %}
9844 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9845 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9846 OpcP, RegOpc(dst) );
9847 ins_pipe( fpu_reg_mem );
9848 %}
9849
9850 //
9851 // Cisc-alternate to reg-reg multiply
9852 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9853 predicate( UseSSE<=1 );
9854 match(Set dst (MulD src (LoadD mem)));
9855 ins_cost(250);
9856 format %{ "FLD_D $mem\n\t"
9857 "DMUL ST,$src\n\t"
9858 "FSTP_D $dst" %}
9859 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9860 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9861 OpcReg_FPR(src),
9862 Pop_Reg_DPR(dst) );
9863 ins_pipe( fpu_reg_reg_mem );
9864 %}
9865
9866
9867 // MACRO3 -- addDPR a mulDPR
9868 // This instruction is a '2-address' instruction in that the result goes
9869 // back to src2. This eliminates a move from the macro; possibly the
9870 // register allocator will have to add it back (and maybe not).
9871 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9872 predicate( UseSSE<=1 );
9873 match(Set src2 (AddD (MulD src0 src1) src2));
9874 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9875 "DMUL ST,$src1\n\t"
9876 "DADDp $src2,ST" %}
9877 ins_cost(250);
9878 opcode(0xDD); /* LoadD DD /0 */
9879 ins_encode( Push_Reg_FPR(src0),
9880 FMul_ST_reg(src1),
9881 FAddP_reg_ST(src2) );
9882 ins_pipe( fpu_reg_reg_reg );
9883 %}
9884
9885
9886 // MACRO3 -- subDPR a mulDPR
9887 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9888 predicate( UseSSE<=1 );
9889 match(Set src2 (SubD (MulD src0 src1) src2));
9890 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9891 "DMUL ST,$src1\n\t"
9892 "DSUBRp $src2,ST" %}
9893 ins_cost(250);
9894 ins_encode( Push_Reg_FPR(src0),
9895 FMul_ST_reg(src1),
9896 Opcode(0xDE), Opc_plus(0xE0,src2));
9897 ins_pipe( fpu_reg_reg_reg );
9898 %}
9899
9900
9901 instruct divDPR_reg(regDPR dst, regDPR src) %{
9902 predicate( UseSSE<=1 );
9903 match(Set dst (DivD dst src));
9904
9905 format %{ "FLD $src\n\t"
9906 "FDIVp $dst,ST" %}
9907 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9908 ins_cost(150);
9909 ins_encode( Push_Reg_DPR(src),
9910 OpcP, RegOpc(dst) );
9911 ins_pipe( fpu_reg_reg );
9912 %}
9913
9914 // Strict FP instruction biases argument before division then
9915 // biases result, to avoid double rounding of subnormals.
9916 //
9917 // scale dividend by multiplying dividend by 2^(-15360)
9918 // load divisor
9919 // divide scaled dividend by divisor
9920 // rescale quotient by 2^(15360)
9921 //
9922 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9923 predicate (UseSSE<=1);
9924 match(Set dst (DivD dst src));
9925 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9926 ins_cost(01);
9927
9928 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9929 "DMULp $dst,ST\n\t"
9930 "FLD $src\n\t"
9931 "FDIVp $dst,ST\n\t"
9932 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9933 "DMULp $dst,ST\n\t" %}
9934 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9935 ins_encode( strictfp_bias1(dst),
9936 Push_Reg_DPR(src),
9937 OpcP, RegOpc(dst),
9938 strictfp_bias2(dst) );
9939 ins_pipe( fpu_reg_reg );
9940 %}
9941
9942 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9943 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9944 match(Set dst (RoundDouble (DivD src1 src2)));
9945
9946 format %{ "FLD $src1\n\t"
9947 "FDIV ST,$src2\n\t"
9948 "FSTP_D $dst\t# D-round" %}
9949 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9950 ins_encode( Push_Reg_DPR(src1),
9951 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9952 ins_pipe( fpu_mem_reg_reg );
9953 %}
9954
9955
9956 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9957 predicate(UseSSE<=1);
9958 match(Set dst (ModD dst src));
9959 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9960
9961 format %{ "DMOD $dst,$src" %}
9962 ins_cost(250);
9963 ins_encode(Push_Reg_Mod_DPR(dst, src),
9964 emitModDPR(),
9965 Push_Result_Mod_DPR(src),
9966 Pop_Reg_DPR(dst));
9967 ins_pipe( pipe_slow );
9968 %}
9969
9970 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9971 predicate(UseSSE>=2);
9972 match(Set dst (ModD src0 src1));
9973 effect(KILL rax, KILL cr);
9974
9975 format %{ "SUB ESP,8\t # DMOD\n"
9976 "\tMOVSD [ESP+0],$src1\n"
9977 "\tFLD_D [ESP+0]\n"
9978 "\tMOVSD [ESP+0],$src0\n"
9979 "\tFLD_D [ESP+0]\n"
9980 "loop:\tFPREM\n"
9981 "\tFWAIT\n"
9982 "\tFNSTSW AX\n"
9983 "\tSAHF\n"
9984 "\tJP loop\n"
9985 "\tFSTP_D [ESP+0]\n"
9986 "\tMOVSD $dst,[ESP+0]\n"
9987 "\tADD ESP,8\n"
9988 "\tFSTP ST0\t # Restore FPU Stack"
9989 %}
9990 ins_cost(250);
9991 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9992 ins_pipe( pipe_slow );
9993 %}
9994
9995 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9996 predicate (UseSSE<=1);
9997 match(Set dst (SinD src));
9998 ins_cost(1800);
9999 format %{ "DSIN $dst" %}
10000 opcode(0xD9, 0xFE);
10001 ins_encode( OpcP, OpcS );
10002 ins_pipe( pipe_slow );
10003 %}
10004
10005 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10006 predicate (UseSSE>=2);
10007 match(Set dst (SinD dst));
10008 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10009 ins_cost(1800);
10010 format %{ "DSIN $dst" %}
10011 opcode(0xD9, 0xFE);
10012 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10013 ins_pipe( pipe_slow );
10014 %}
10015
10016 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10017 predicate (UseSSE<=1);
10018 match(Set dst (CosD src));
10019 ins_cost(1800);
10020 format %{ "DCOS $dst" %}
10021 opcode(0xD9, 0xFF);
10022 ins_encode( OpcP, OpcS );
10023 ins_pipe( pipe_slow );
10024 %}
10025
10026 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10027 predicate (UseSSE>=2);
10028 match(Set dst (CosD dst));
10029 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10030 ins_cost(1800);
10031 format %{ "DCOS $dst" %}
10032 opcode(0xD9, 0xFF);
10033 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10034 ins_pipe( pipe_slow );
10035 %}
10036
10037 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10038 predicate (UseSSE<=1);
10039 match(Set dst(TanD src));
10040 format %{ "DTAN $dst" %}
10041 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10042 Opcode(0xDD), Opcode(0xD8)); // fstp st
10043 ins_pipe( pipe_slow );
10044 %}
10045
10046 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10047 predicate (UseSSE>=2);
10048 match(Set dst(TanD dst));
10049 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10050 format %{ "DTAN $dst" %}
10051 ins_encode( Push_SrcD(dst),
10052 Opcode(0xD9), Opcode(0xF2), // fptan
10053 Opcode(0xDD), Opcode(0xD8), // fstp st
10054 Push_ResultD(dst) );
10055 ins_pipe( pipe_slow );
10056 %}
10057
10058 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10059 predicate (UseSSE<=1);
10060 match(Set dst(AtanD dst src));
10061 format %{ "DATA $dst,$src" %}
10062 opcode(0xD9, 0xF3);
10063 ins_encode( Push_Reg_DPR(src),
10064 OpcP, OpcS, RegOpc(dst) );
10065 ins_pipe( pipe_slow );
10066 %}
10067
10068 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10069 predicate (UseSSE>=2);
10070 match(Set dst(AtanD dst src));
10071 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10072 format %{ "DATA $dst,$src" %}
10073 opcode(0xD9, 0xF3);
10074 ins_encode( Push_SrcD(src),
10075 OpcP, OpcS, Push_ResultD(dst) );
10076 ins_pipe( pipe_slow );
10077 %}
10078
10079 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10080 predicate (UseSSE<=1);
10081 match(Set dst (SqrtD src));
10082 format %{ "DSQRT $dst,$src" %}
10083 opcode(0xFA, 0xD9);
10084 ins_encode( Push_Reg_DPR(src),
10085 OpcS, OpcP, Pop_Reg_DPR(dst) );
10086 ins_pipe( pipe_slow );
10087 %}
10088
10089 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10090 predicate (UseSSE<=1);
10091 match(Set Y (PowD X Y)); // Raise X to the Yth power
10092 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10093 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10094 ins_encode %{
10095 __ subptr(rsp, 8);
10096 __ fld_s($X$$reg - 1);
10097 __ fast_pow();
10098 __ addptr(rsp, 8);
10099 %}
10100 ins_pipe( pipe_slow );
10101 %}
10102
10103 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10104 predicate (UseSSE>=2);
10105 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10106 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10107 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10108 ins_encode %{
10109 __ subptr(rsp, 8);
10110 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10111 __ fld_d(Address(rsp, 0));
10112 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10113 __ fld_d(Address(rsp, 0));
10114 __ fast_pow();
10115 __ fstp_d(Address(rsp, 0));
10116 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10117 __ addptr(rsp, 8);
10118 %}
10119 ins_pipe( pipe_slow );
10120 %}
10121
10122
10123 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10124 predicate (UseSSE<=1);
10125 match(Set dpr1 (ExpD dpr1));
10126 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10127 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10128 ins_encode %{
10129 __ fast_exp();
10130 %}
10131 ins_pipe( pipe_slow );
10132 %}
10133
10134 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10135 predicate (UseSSE>=2);
10136 match(Set dst (ExpD src));
10137 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10138 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10139 ins_encode %{
10140 __ subptr(rsp, 8);
10141 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10142 __ fld_d(Address(rsp, 0));
10143 __ fast_exp();
10144 __ fstp_d(Address(rsp, 0));
10145 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10146 __ addptr(rsp, 8);
10147 %}
10148 ins_pipe( pipe_slow );
10149 %}
10150
10151 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10152 predicate (UseSSE<=1);
10153 // The source Double operand on FPU stack
10154 match(Set dst (Log10D src));
10155 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10156 // fxch ; swap ST(0) with ST(1)
10157 // fyl2x ; compute log_10(2) * log_2(x)
10158 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10159 "FXCH \n\t"
10160 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10161 %}
10162 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10163 Opcode(0xD9), Opcode(0xC9), // fxch
10164 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10165
10166 ins_pipe( pipe_slow );
10167 %}
10168
10169 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10170 predicate (UseSSE>=2);
10171 effect(KILL cr);
10172 match(Set dst (Log10D src));
10173 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10174 // fyl2x ; compute log_10(2) * log_2(x)
10175 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10176 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10177 %}
10178 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10179 Push_SrcD(src),
10180 Opcode(0xD9), Opcode(0xF1), // fyl2x
10181 Push_ResultD(dst));
10182
10183 ins_pipe( pipe_slow );
10184 %}
10185
10186 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10187 predicate (UseSSE<=1);
10188 // The source Double operand on FPU stack
10189 match(Set dst (LogD src));
10190 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10191 // fxch ; swap ST(0) with ST(1)
10192 // fyl2x ; compute log_e(2) * log_2(x)
10193 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10194 "FXCH \n\t"
10195 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10196 %}
10197 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10198 Opcode(0xD9), Opcode(0xC9), // fxch
10199 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10200
10201 ins_pipe( pipe_slow );
10202 %}
10203
10204 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10205 predicate (UseSSE>=2);
10206 effect(KILL cr);
10207 // The source and result Double operands in XMM registers
10208 match(Set dst (LogD src));
10209 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10210 // fyl2x ; compute log_e(2) * log_2(x)
10211 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10212 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10213 %}
10214 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10215 Push_SrcD(src),
10216 Opcode(0xD9), Opcode(0xF1), // fyl2x
10217 Push_ResultD(dst));
10218 ins_pipe( pipe_slow );
10219 %}
10220
10221 //-------------Float Instructions-------------------------------
10222 // Float Math
10223
10224 // Code for float compare:
10225 // fcompp();
10226 // fwait(); fnstsw_ax();
10227 // sahf();
10228 // movl(dst, unordered_result);
10229 // jcc(Assembler::parity, exit);
10230 // movl(dst, less_result);
10231 // jcc(Assembler::below, exit);
10232 // movl(dst, equal_result);
10233 // jcc(Assembler::equal, exit);
10234 // movl(dst, greater_result);
10235 // exit:
10236
10237 // P6 version of float compare, sets condition codes in EFLAGS
10238 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10239 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10240 match(Set cr (CmpF src1 src2));
10241 effect(KILL rax);
10242 ins_cost(150);
10243 format %{ "FLD $src1\n\t"
10244 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10245 "JNP exit\n\t"
10246 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10247 "SAHF\n"
10248 "exit:\tNOP // avoid branch to branch" %}
10249 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10250 ins_encode( Push_Reg_DPR(src1),
10251 OpcP, RegOpc(src2),
10252 cmpF_P6_fixup );
10253 ins_pipe( pipe_slow );
10254 %}
10255
10256 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10257 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10258 match(Set cr (CmpF src1 src2));
10259 ins_cost(100);
10260 format %{ "FLD $src1\n\t"
10261 "FUCOMIP ST,$src2 // P6 instruction" %}
10262 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10263 ins_encode( Push_Reg_DPR(src1),
10264 OpcP, RegOpc(src2));
10265 ins_pipe( pipe_slow );
10266 %}
10267
10268
10269 // Compare & branch
10270 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10271 predicate(UseSSE == 0);
10272 match(Set cr (CmpF src1 src2));
10273 effect(KILL rax);
10274 ins_cost(200);
10275 format %{ "FLD $src1\n\t"
10276 "FCOMp $src2\n\t"
10277 "FNSTSW AX\n\t"
10278 "TEST AX,0x400\n\t"
10279 "JZ,s flags\n\t"
10280 "MOV AH,1\t# unordered treat as LT\n"
10281 "flags:\tSAHF" %}
10282 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10283 ins_encode( Push_Reg_DPR(src1),
10284 OpcP, RegOpc(src2),
10285 fpu_flags);
10286 ins_pipe( pipe_slow );
10287 %}
10288
10289 // Compare vs zero into -1,0,1
10290 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10291 predicate(UseSSE == 0);
10292 match(Set dst (CmpF3 src1 zero));
10293 effect(KILL cr, KILL rax);
10294 ins_cost(280);
10295 format %{ "FTSTF $dst,$src1" %}
10296 opcode(0xE4, 0xD9);
10297 ins_encode( Push_Reg_DPR(src1),
10298 OpcS, OpcP, PopFPU,
10299 CmpF_Result(dst));
10300 ins_pipe( pipe_slow );
10301 %}
10302
10303 // Compare into -1,0,1
10304 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10305 predicate(UseSSE == 0);
10306 match(Set dst (CmpF3 src1 src2));
10307 effect(KILL cr, KILL rax);
10308 ins_cost(300);
10309 format %{ "FCMPF $dst,$src1,$src2" %}
10310 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10311 ins_encode( Push_Reg_DPR(src1),
10312 OpcP, RegOpc(src2),
10313 CmpF_Result(dst));
10314 ins_pipe( pipe_slow );
10315 %}
10316
10317 // float compare and set condition codes in EFLAGS by XMM regs
10318 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10319 predicate(UseSSE>=1);
10320 match(Set cr (CmpF src1 src2));
10321 ins_cost(145);
10322 format %{ "UCOMISS $src1,$src2\n\t"
10323 "JNP,s exit\n\t"
10324 "PUSHF\t# saw NaN, set CF\n\t"
10325 "AND [rsp], #0xffffff2b\n\t"
10326 "POPF\n"
10327 "exit:" %}
10328 ins_encode %{
10329 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10330 emit_cmpfp_fixup(_masm);
10331 %}
10332 ins_pipe( pipe_slow );
10333 %}
10334
10335 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10336 predicate(UseSSE>=1);
10337 match(Set cr (CmpF src1 src2));
10338 ins_cost(100);
10339 format %{ "UCOMISS $src1,$src2" %}
10340 ins_encode %{
10341 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10342 %}
10343 ins_pipe( pipe_slow );
10344 %}
10345
10346 // float compare and set condition codes in EFLAGS by XMM regs
10347 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10348 predicate(UseSSE>=1);
10349 match(Set cr (CmpF src1 (LoadF src2)));
10350 ins_cost(165);
10351 format %{ "UCOMISS $src1,$src2\n\t"
10352 "JNP,s exit\n\t"
10353 "PUSHF\t# saw NaN, set CF\n\t"
10354 "AND [rsp], #0xffffff2b\n\t"
10355 "POPF\n"
10356 "exit:" %}
10357 ins_encode %{
10358 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10359 emit_cmpfp_fixup(_masm);
10360 %}
10361 ins_pipe( pipe_slow );
10362 %}
10363
10364 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10365 predicate(UseSSE>=1);
10366 match(Set cr (CmpF src1 (LoadF src2)));
10367 ins_cost(100);
10368 format %{ "UCOMISS $src1,$src2" %}
10369 ins_encode %{
10370 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10371 %}
10372 ins_pipe( pipe_slow );
10373 %}
10374
10375 // Compare into -1,0,1 in XMM
10376 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10377 predicate(UseSSE>=1);
10378 match(Set dst (CmpF3 src1 src2));
10379 effect(KILL cr);
10380 ins_cost(255);
10381 format %{ "UCOMISS $src1, $src2\n\t"
10382 "MOV $dst, #-1\n\t"
10383 "JP,s done\n\t"
10384 "JB,s done\n\t"
10385 "SETNE $dst\n\t"
10386 "MOVZB $dst, $dst\n"
10387 "done:" %}
10388 ins_encode %{
10389 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10390 emit_cmpfp3(_masm, $dst$$Register);
10391 %}
10392 ins_pipe( pipe_slow );
10393 %}
10394
10395 // Compare into -1,0,1 in XMM and memory
10396 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10397 predicate(UseSSE>=1);
10398 match(Set dst (CmpF3 src1 (LoadF src2)));
10399 effect(KILL cr);
10400 ins_cost(275);
10401 format %{ "UCOMISS $src1, $src2\n\t"
10402 "MOV $dst, #-1\n\t"
10403 "JP,s done\n\t"
10404 "JB,s done\n\t"
10405 "SETNE $dst\n\t"
10406 "MOVZB $dst, $dst\n"
10407 "done:" %}
10408 ins_encode %{
10409 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10410 emit_cmpfp3(_masm, $dst$$Register);
10411 %}
10412 ins_pipe( pipe_slow );
10413 %}
10414
10415 // Spill to obtain 24-bit precision
10416 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10417 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10418 match(Set dst (SubF src1 src2));
10419
10420 format %{ "FSUB $dst,$src1 - $src2" %}
10421 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10422 ins_encode( Push_Reg_FPR(src1),
10423 OpcReg_FPR(src2),
10424 Pop_Mem_FPR(dst) );
10425 ins_pipe( fpu_mem_reg_reg );
10426 %}
10427 //
10428 // This instruction does not round to 24-bits
10429 instruct subFPR_reg(regFPR dst, regFPR src) %{
10430 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10431 match(Set dst (SubF dst src));
10432
10433 format %{ "FSUB $dst,$src" %}
10434 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10435 ins_encode( Push_Reg_FPR(src),
10436 OpcP, RegOpc(dst) );
10437 ins_pipe( fpu_reg_reg );
10438 %}
10439
10440 // Spill to obtain 24-bit precision
10441 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10442 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10443 match(Set dst (AddF src1 src2));
10444
10445 format %{ "FADD $dst,$src1,$src2" %}
10446 opcode(0xD8, 0x0); /* D8 C0+i */
10447 ins_encode( Push_Reg_FPR(src2),
10448 OpcReg_FPR(src1),
10449 Pop_Mem_FPR(dst) );
10450 ins_pipe( fpu_mem_reg_reg );
10451 %}
10452 //
10453 // This instruction does not round to 24-bits
10454 instruct addFPR_reg(regFPR dst, regFPR src) %{
10455 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10456 match(Set dst (AddF dst src));
10457
10458 format %{ "FLD $src\n\t"
10459 "FADDp $dst,ST" %}
10460 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10461 ins_encode( Push_Reg_FPR(src),
10462 OpcP, RegOpc(dst) );
10463 ins_pipe( fpu_reg_reg );
10464 %}
10465
10466 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10467 predicate(UseSSE==0);
10468 match(Set dst (AbsF src));
10469 ins_cost(100);
10470 format %{ "FABS" %}
10471 opcode(0xE1, 0xD9);
10472 ins_encode( OpcS, OpcP );
10473 ins_pipe( fpu_reg_reg );
10474 %}
10475
10476 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10477 predicate(UseSSE==0);
10478 match(Set dst (NegF src));
10479 ins_cost(100);
10480 format %{ "FCHS" %}
10481 opcode(0xE0, 0xD9);
10482 ins_encode( OpcS, OpcP );
10483 ins_pipe( fpu_reg_reg );
10484 %}
10485
10486 // Cisc-alternate to addFPR_reg
10487 // Spill to obtain 24-bit precision
10488 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10489 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10490 match(Set dst (AddF src1 (LoadF src2)));
10491
10492 format %{ "FLD $src2\n\t"
10493 "FADD ST,$src1\n\t"
10494 "FSTP_S $dst" %}
10495 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10496 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10497 OpcReg_FPR(src1),
10498 Pop_Mem_FPR(dst) );
10499 ins_pipe( fpu_mem_reg_mem );
10500 %}
10501 //
10502 // Cisc-alternate to addFPR_reg
10503 // This instruction does not round to 24-bits
10504 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10505 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10506 match(Set dst (AddF dst (LoadF src)));
10507
10508 format %{ "FADD $dst,$src" %}
10509 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10510 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10511 OpcP, RegOpc(dst) );
10512 ins_pipe( fpu_reg_mem );
10513 %}
10514
10515 // // Following two instructions for _222_mpegaudio
10516 // Spill to obtain 24-bit precision
10517 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10518 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10519 match(Set dst (AddF src1 src2));
10520
10521 format %{ "FADD $dst,$src1,$src2" %}
10522 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10523 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10524 OpcReg_FPR(src2),
10525 Pop_Mem_FPR(dst) );
10526 ins_pipe( fpu_mem_reg_mem );
10527 %}
10528
10529 // Cisc-spill variant
10530 // Spill to obtain 24-bit precision
10531 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10532 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10533 match(Set dst (AddF src1 (LoadF src2)));
10534
10535 format %{ "FADD $dst,$src1,$src2 cisc" %}
10536 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10537 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10538 set_instruction_start,
10539 OpcP, RMopc_Mem(secondary,src1),
10540 Pop_Mem_FPR(dst) );
10541 ins_pipe( fpu_mem_mem_mem );
10542 %}
10543
10544 // Spill to obtain 24-bit precision
10545 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10546 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10547 match(Set dst (AddF src1 src2));
10548
10549 format %{ "FADD $dst,$src1,$src2" %}
10550 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10551 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10552 set_instruction_start,
10553 OpcP, RMopc_Mem(secondary,src1),
10554 Pop_Mem_FPR(dst) );
10555 ins_pipe( fpu_mem_mem_mem );
10556 %}
10557
10558
10559 // Spill to obtain 24-bit precision
10560 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10561 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10562 match(Set dst (AddF src con));
10563 format %{ "FLD $src\n\t"
10564 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10565 "FSTP_S $dst" %}
10566 ins_encode %{
10567 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10568 __ fadd_s($constantaddress($con));
10569 __ fstp_s(Address(rsp, $dst$$disp));
10570 %}
10571 ins_pipe(fpu_mem_reg_con);
10572 %}
10573 //
10574 // This instruction does not round to 24-bits
10575 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10576 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10577 match(Set dst (AddF src con));
10578 format %{ "FLD $src\n\t"
10579 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10580 "FSTP $dst" %}
10581 ins_encode %{
10582 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10583 __ fadd_s($constantaddress($con));
10584 __ fstp_d($dst$$reg);
10585 %}
10586 ins_pipe(fpu_reg_reg_con);
10587 %}
10588
10589 // Spill to obtain 24-bit precision
10590 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10591 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10592 match(Set dst (MulF src1 src2));
10593
10594 format %{ "FLD $src1\n\t"
10595 "FMUL $src2\n\t"
10596 "FSTP_S $dst" %}
10597 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10598 ins_encode( Push_Reg_FPR(src1),
10599 OpcReg_FPR(src2),
10600 Pop_Mem_FPR(dst) );
10601 ins_pipe( fpu_mem_reg_reg );
10602 %}
10603 //
10604 // This instruction does not round to 24-bits
10605 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10606 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10607 match(Set dst (MulF src1 src2));
10608
10609 format %{ "FLD $src1\n\t"
10610 "FMUL $src2\n\t"
10611 "FSTP_S $dst" %}
10612 opcode(0xD8, 0x1); /* D8 C8+i */
10613 ins_encode( Push_Reg_FPR(src2),
10614 OpcReg_FPR(src1),
10615 Pop_Reg_FPR(dst) );
10616 ins_pipe( fpu_reg_reg_reg );
10617 %}
10618
10619
10620 // Spill to obtain 24-bit precision
10621 // Cisc-alternate to reg-reg multiply
10622 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10623 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10624 match(Set dst (MulF src1 (LoadF src2)));
10625
10626 format %{ "FLD_S $src2\n\t"
10627 "FMUL $src1\n\t"
10628 "FSTP_S $dst" %}
10629 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10630 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10631 OpcReg_FPR(src1),
10632 Pop_Mem_FPR(dst) );
10633 ins_pipe( fpu_mem_reg_mem );
10634 %}
10635 //
10636 // This instruction does not round to 24-bits
10637 // Cisc-alternate to reg-reg multiply
10638 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10639 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10640 match(Set dst (MulF src1 (LoadF src2)));
10641
10642 format %{ "FMUL $dst,$src1,$src2" %}
10643 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10644 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10645 OpcReg_FPR(src1),
10646 Pop_Reg_FPR(dst) );
10647 ins_pipe( fpu_reg_reg_mem );
10648 %}
10649
10650 // Spill to obtain 24-bit precision
10651 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10652 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10653 match(Set dst (MulF src1 src2));
10654
10655 format %{ "FMUL $dst,$src1,$src2" %}
10656 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10657 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10658 set_instruction_start,
10659 OpcP, RMopc_Mem(secondary,src1),
10660 Pop_Mem_FPR(dst) );
10661 ins_pipe( fpu_mem_mem_mem );
10662 %}
10663
10664 // Spill to obtain 24-bit precision
10665 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10666 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10667 match(Set dst (MulF src con));
10668
10669 format %{ "FLD $src\n\t"
10670 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10671 "FSTP_S $dst" %}
10672 ins_encode %{
10673 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10674 __ fmul_s($constantaddress($con));
10675 __ fstp_s(Address(rsp, $dst$$disp));
10676 %}
10677 ins_pipe(fpu_mem_reg_con);
10678 %}
10679 //
10680 // This instruction does not round to 24-bits
10681 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10682 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10683 match(Set dst (MulF src con));
10684
10685 format %{ "FLD $src\n\t"
10686 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10687 "FSTP $dst" %}
10688 ins_encode %{
10689 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10690 __ fmul_s($constantaddress($con));
10691 __ fstp_d($dst$$reg);
10692 %}
10693 ins_pipe(fpu_reg_reg_con);
10694 %}
10695
10696
10697 //
10698 // MACRO1 -- subsume unshared load into mulFPR
10699 // This instruction does not round to 24-bits
10700 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10701 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10702 match(Set dst (MulF (LoadF mem1) src));
10703
10704 format %{ "FLD $mem1 ===MACRO1===\n\t"
10705 "FMUL ST,$src\n\t"
10706 "FSTP $dst" %}
10707 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10708 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10709 OpcReg_FPR(src),
10710 Pop_Reg_FPR(dst) );
10711 ins_pipe( fpu_reg_reg_mem );
10712 %}
10713 //
10714 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10715 // This instruction does not round to 24-bits
10716 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10717 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10718 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10719 ins_cost(95);
10720
10721 format %{ "FLD $mem1 ===MACRO2===\n\t"
10722 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10723 "FADD ST,$src2\n\t"
10724 "FSTP $dst" %}
10725 opcode(0xD9); /* LoadF D9 /0 */
10726 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10727 FMul_ST_reg(src1),
10728 FAdd_ST_reg(src2),
10729 Pop_Reg_FPR(dst) );
10730 ins_pipe( fpu_reg_mem_reg_reg );
10731 %}
10732
10733 // MACRO3 -- addFPR a mulFPR
10734 // This instruction does not round to 24-bits. It is a '2-address'
10735 // instruction in that the result goes back to src2. This eliminates
10736 // a move from the macro; possibly the register allocator will have
10737 // to add it back (and maybe not).
10738 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10739 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10740 match(Set src2 (AddF (MulF src0 src1) src2));
10741
10742 format %{ "FLD $src0 ===MACRO3===\n\t"
10743 "FMUL ST,$src1\n\t"
10744 "FADDP $src2,ST" %}
10745 opcode(0xD9); /* LoadF D9 /0 */
10746 ins_encode( Push_Reg_FPR(src0),
10747 FMul_ST_reg(src1),
10748 FAddP_reg_ST(src2) );
10749 ins_pipe( fpu_reg_reg_reg );
10750 %}
10751
10752 // MACRO4 -- divFPR subFPR
10753 // This instruction does not round to 24-bits
10754 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10755 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10756 match(Set dst (DivF (SubF src2 src1) src3));
10757
10758 format %{ "FLD $src2 ===MACRO4===\n\t"
10759 "FSUB ST,$src1\n\t"
10760 "FDIV ST,$src3\n\t"
10761 "FSTP $dst" %}
10762 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10763 ins_encode( Push_Reg_FPR(src2),
10764 subFPR_divFPR_encode(src1,src3),
10765 Pop_Reg_FPR(dst) );
10766 ins_pipe( fpu_reg_reg_reg_reg );
10767 %}
10768
10769 // Spill to obtain 24-bit precision
10770 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10771 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10772 match(Set dst (DivF src1 src2));
10773
10774 format %{ "FDIV $dst,$src1,$src2" %}
10775 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10776 ins_encode( Push_Reg_FPR(src1),
10777 OpcReg_FPR(src2),
10778 Pop_Mem_FPR(dst) );
10779 ins_pipe( fpu_mem_reg_reg );
10780 %}
10781 //
10782 // This instruction does not round to 24-bits
10783 instruct divFPR_reg(regFPR dst, regFPR src) %{
10784 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10785 match(Set dst (DivF dst src));
10786
10787 format %{ "FDIV $dst,$src" %}
10788 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10789 ins_encode( Push_Reg_FPR(src),
10790 OpcP, RegOpc(dst) );
10791 ins_pipe( fpu_reg_reg );
10792 %}
10793
10794
10795 // Spill to obtain 24-bit precision
10796 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10797 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10798 match(Set dst (ModF src1 src2));
10799 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10800
10801 format %{ "FMOD $dst,$src1,$src2" %}
10802 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10803 emitModDPR(),
10804 Push_Result_Mod_DPR(src2),
10805 Pop_Mem_FPR(dst));
10806 ins_pipe( pipe_slow );
10807 %}
10808 //
10809 // This instruction does not round to 24-bits
10810 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10811 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10812 match(Set dst (ModF dst src));
10813 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10814
10815 format %{ "FMOD $dst,$src" %}
10816 ins_encode(Push_Reg_Mod_DPR(dst, src),
10817 emitModDPR(),
10818 Push_Result_Mod_DPR(src),
10819 Pop_Reg_FPR(dst));
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10824 predicate(UseSSE>=1);
10825 match(Set dst (ModF src0 src1));
10826 effect(KILL rax, KILL cr);
10827 format %{ "SUB ESP,4\t # FMOD\n"
10828 "\tMOVSS [ESP+0],$src1\n"
10829 "\tFLD_S [ESP+0]\n"
10830 "\tMOVSS [ESP+0],$src0\n"
10831 "\tFLD_S [ESP+0]\n"
10832 "loop:\tFPREM\n"
10833 "\tFWAIT\n"
10834 "\tFNSTSW AX\n"
10835 "\tSAHF\n"
10836 "\tJP loop\n"
10837 "\tFSTP_S [ESP+0]\n"
10838 "\tMOVSS $dst,[ESP+0]\n"
10839 "\tADD ESP,4\n"
10840 "\tFSTP ST0\t # Restore FPU Stack"
10841 %}
10842 ins_cost(250);
10843 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10844 ins_pipe( pipe_slow );
10845 %}
10846
10847
10848 //----------Arithmetic Conversion Instructions---------------------------------
10849 // The conversions operations are all Alpha sorted. Please keep it that way!
10850
10851 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10852 predicate(UseSSE==0);
10853 match(Set dst (RoundFloat src));
10854 ins_cost(125);
10855 format %{ "FST_S $dst,$src\t# F-round" %}
10856 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10857 ins_pipe( fpu_mem_reg );
10858 %}
10859
10860 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10861 predicate(UseSSE<=1);
10862 match(Set dst (RoundDouble src));
10863 ins_cost(125);
10864 format %{ "FST_D $dst,$src\t# D-round" %}
10865 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10866 ins_pipe( fpu_mem_reg );
10867 %}
10868
10869 // Force rounding to 24-bit precision and 6-bit exponent
10870 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10871 predicate(UseSSE==0);
10872 match(Set dst (ConvD2F src));
10873 format %{ "FST_S $dst,$src\t# F-round" %}
10874 expand %{
10875 roundFloat_mem_reg(dst,src);
10876 %}
10877 %}
10878
10879 // Force rounding to 24-bit precision and 6-bit exponent
10880 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10881 predicate(UseSSE==1);
10882 match(Set dst (ConvD2F src));
10883 effect( KILL cr );
10884 format %{ "SUB ESP,4\n\t"
10885 "FST_S [ESP],$src\t# F-round\n\t"
10886 "MOVSS $dst,[ESP]\n\t"
10887 "ADD ESP,4" %}
10888 ins_encode %{
10889 __ subptr(rsp, 4);
10890 if ($src$$reg != FPR1L_enc) {
10891 __ fld_s($src$$reg-1);
10892 __ fstp_s(Address(rsp, 0));
10893 } else {
10894 __ fst_s(Address(rsp, 0));
10895 }
10896 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10897 __ addptr(rsp, 4);
10898 %}
10899 ins_pipe( pipe_slow );
10900 %}
10901
10902 // Force rounding double precision to single precision
10903 instruct convD2F_reg(regF dst, regD src) %{
10904 predicate(UseSSE>=2);
10905 match(Set dst (ConvD2F src));
10906 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10907 ins_encode %{
10908 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10909 %}
10910 ins_pipe( pipe_slow );
10911 %}
10912
10913 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10914 predicate(UseSSE==0);
10915 match(Set dst (ConvF2D src));
10916 format %{ "FST_S $dst,$src\t# D-round" %}
10917 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10918 ins_pipe( fpu_reg_reg );
10919 %}
10920
10921 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10922 predicate(UseSSE==1);
10923 match(Set dst (ConvF2D src));
10924 format %{ "FST_D $dst,$src\t# D-round" %}
10925 expand %{
10926 roundDouble_mem_reg(dst,src);
10927 %}
10928 %}
10929
10930 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10931 predicate(UseSSE==1);
10932 match(Set dst (ConvF2D src));
10933 effect( KILL cr );
10934 format %{ "SUB ESP,4\n\t"
10935 "MOVSS [ESP] $src\n\t"
10936 "FLD_S [ESP]\n\t"
10937 "ADD ESP,4\n\t"
10938 "FSTP $dst\t# D-round" %}
10939 ins_encode %{
10940 __ subptr(rsp, 4);
10941 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10942 __ fld_s(Address(rsp, 0));
10943 __ addptr(rsp, 4);
10944 __ fstp_d($dst$$reg);
10945 %}
10946 ins_pipe( pipe_slow );
10947 %}
10948
10949 instruct convF2D_reg(regD dst, regF src) %{
10950 predicate(UseSSE>=2);
10951 match(Set dst (ConvF2D src));
10952 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10953 ins_encode %{
10954 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10955 %}
10956 ins_pipe( pipe_slow );
10957 %}
10958
10959 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10960 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10961 predicate(UseSSE<=1);
10962 match(Set dst (ConvD2I src));
10963 effect( KILL tmp, KILL cr );
10964 format %{ "FLD $src\t# Convert double to int \n\t"
10965 "FLDCW trunc mode\n\t"
10966 "SUB ESP,4\n\t"
10967 "FISTp [ESP + #0]\n\t"
10968 "FLDCW std/24-bit mode\n\t"
10969 "POP EAX\n\t"
10970 "CMP EAX,0x80000000\n\t"
10971 "JNE,s fast\n\t"
10972 "FLD_D $src\n\t"
10973 "CALL d2i_wrapper\n"
10974 "fast:" %}
10975 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10976 ins_pipe( pipe_slow );
10977 %}
10978
10979 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10980 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10981 predicate(UseSSE>=2);
10982 match(Set dst (ConvD2I src));
10983 effect( KILL tmp, KILL cr );
10984 format %{ "CVTTSD2SI $dst, $src\n\t"
10985 "CMP $dst,0x80000000\n\t"
10986 "JNE,s fast\n\t"
10987 "SUB ESP, 8\n\t"
10988 "MOVSD [ESP], $src\n\t"
10989 "FLD_D [ESP]\n\t"
10990 "ADD ESP, 8\n\t"
10991 "CALL d2i_wrapper\n"
10992 "fast:" %}
10993 ins_encode %{
10994 Label fast;
10995 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10996 __ cmpl($dst$$Register, 0x80000000);
10997 __ jccb(Assembler::notEqual, fast);
10998 __ subptr(rsp, 8);
10999 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11000 __ fld_d(Address(rsp, 0));
11001 __ addptr(rsp, 8);
11002 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11003 __ bind(fast);
11004 %}
11005 ins_pipe( pipe_slow );
11006 %}
11007
11008 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11009 predicate(UseSSE<=1);
11010 match(Set dst (ConvD2L src));
11011 effect( KILL cr );
11012 format %{ "FLD $src\t# Convert double to long\n\t"
11013 "FLDCW trunc mode\n\t"
11014 "SUB ESP,8\n\t"
11015 "FISTp [ESP + #0]\n\t"
11016 "FLDCW std/24-bit mode\n\t"
11017 "POP EAX\n\t"
11018 "POP EDX\n\t"
11019 "CMP EDX,0x80000000\n\t"
11020 "JNE,s fast\n\t"
11021 "TEST EAX,EAX\n\t"
11022 "JNE,s fast\n\t"
11023 "FLD $src\n\t"
11024 "CALL d2l_wrapper\n"
11025 "fast:" %}
11026 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11031 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11032 predicate (UseSSE>=2);
11033 match(Set dst (ConvD2L src));
11034 effect( KILL cr );
11035 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11036 "MOVSD [ESP],$src\n\t"
11037 "FLD_D [ESP]\n\t"
11038 "FLDCW trunc mode\n\t"
11039 "FISTp [ESP + #0]\n\t"
11040 "FLDCW std/24-bit mode\n\t"
11041 "POP EAX\n\t"
11042 "POP EDX\n\t"
11043 "CMP EDX,0x80000000\n\t"
11044 "JNE,s fast\n\t"
11045 "TEST EAX,EAX\n\t"
11046 "JNE,s fast\n\t"
11047 "SUB ESP,8\n\t"
11048 "MOVSD [ESP],$src\n\t"
11049 "FLD_D [ESP]\n\t"
11050 "ADD ESP,8\n\t"
11051 "CALL d2l_wrapper\n"
11052 "fast:" %}
11053 ins_encode %{
11054 Label fast;
11055 __ subptr(rsp, 8);
11056 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11057 __ fld_d(Address(rsp, 0));
11058 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11059 __ fistp_d(Address(rsp, 0));
11060 // Restore the rounding mode, mask the exception
11061 if (Compile::current()->in_24_bit_fp_mode()) {
11062 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11063 } else {
11064 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11065 }
11066 // Load the converted long, adjust CPU stack
11067 __ pop(rax);
11068 __ pop(rdx);
11069 __ cmpl(rdx, 0x80000000);
11070 __ jccb(Assembler::notEqual, fast);
11071 __ testl(rax, rax);
11072 __ jccb(Assembler::notEqual, fast);
11073 __ subptr(rsp, 8);
11074 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11075 __ fld_d(Address(rsp, 0));
11076 __ addptr(rsp, 8);
11077 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11078 __ bind(fast);
11079 %}
11080 ins_pipe( pipe_slow );
11081 %}
11082
11083 // Convert a double to an int. Java semantics require we do complex
11084 // manglations in the corner cases. So we set the rounding mode to
11085 // 'zero', store the darned double down as an int, and reset the
11086 // rounding mode to 'nearest'. The hardware stores a flag value down
11087 // if we would overflow or converted a NAN; we check for this and
11088 // and go the slow path if needed.
11089 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11090 predicate(UseSSE==0);
11091 match(Set dst (ConvF2I src));
11092 effect( KILL tmp, KILL cr );
11093 format %{ "FLD $src\t# Convert float to int \n\t"
11094 "FLDCW trunc mode\n\t"
11095 "SUB ESP,4\n\t"
11096 "FISTp [ESP + #0]\n\t"
11097 "FLDCW std/24-bit mode\n\t"
11098 "POP EAX\n\t"
11099 "CMP EAX,0x80000000\n\t"
11100 "JNE,s fast\n\t"
11101 "FLD $src\n\t"
11102 "CALL d2i_wrapper\n"
11103 "fast:" %}
11104 // DPR2I_encoding works for FPR2I
11105 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11106 ins_pipe( pipe_slow );
11107 %}
11108
11109 // Convert a float in xmm to an int reg.
11110 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11111 predicate(UseSSE>=1);
11112 match(Set dst (ConvF2I src));
11113 effect( KILL tmp, KILL cr );
11114 format %{ "CVTTSS2SI $dst, $src\n\t"
11115 "CMP $dst,0x80000000\n\t"
11116 "JNE,s fast\n\t"
11117 "SUB ESP, 4\n\t"
11118 "MOVSS [ESP], $src\n\t"
11119 "FLD [ESP]\n\t"
11120 "ADD ESP, 4\n\t"
11121 "CALL d2i_wrapper\n"
11122 "fast:" %}
11123 ins_encode %{
11124 Label fast;
11125 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11126 __ cmpl($dst$$Register, 0x80000000);
11127 __ jccb(Assembler::notEqual, fast);
11128 __ subptr(rsp, 4);
11129 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11130 __ fld_s(Address(rsp, 0));
11131 __ addptr(rsp, 4);
11132 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11133 __ bind(fast);
11134 %}
11135 ins_pipe( pipe_slow );
11136 %}
11137
11138 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11139 predicate(UseSSE==0);
11140 match(Set dst (ConvF2L src));
11141 effect( KILL cr );
11142 format %{ "FLD $src\t# Convert float to long\n\t"
11143 "FLDCW trunc mode\n\t"
11144 "SUB ESP,8\n\t"
11145 "FISTp [ESP + #0]\n\t"
11146 "FLDCW std/24-bit mode\n\t"
11147 "POP EAX\n\t"
11148 "POP EDX\n\t"
11149 "CMP EDX,0x80000000\n\t"
11150 "JNE,s fast\n\t"
11151 "TEST EAX,EAX\n\t"
11152 "JNE,s fast\n\t"
11153 "FLD $src\n\t"
11154 "CALL d2l_wrapper\n"
11155 "fast:" %}
11156 // DPR2L_encoding works for FPR2L
11157 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11158 ins_pipe( pipe_slow );
11159 %}
11160
11161 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11162 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11163 predicate (UseSSE>=1);
11164 match(Set dst (ConvF2L src));
11165 effect( KILL cr );
11166 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11167 "MOVSS [ESP],$src\n\t"
11168 "FLD_S [ESP]\n\t"
11169 "FLDCW trunc mode\n\t"
11170 "FISTp [ESP + #0]\n\t"
11171 "FLDCW std/24-bit mode\n\t"
11172 "POP EAX\n\t"
11173 "POP EDX\n\t"
11174 "CMP EDX,0x80000000\n\t"
11175 "JNE,s fast\n\t"
11176 "TEST EAX,EAX\n\t"
11177 "JNE,s fast\n\t"
11178 "SUB ESP,4\t# Convert float to long\n\t"
11179 "MOVSS [ESP],$src\n\t"
11180 "FLD_S [ESP]\n\t"
11181 "ADD ESP,4\n\t"
11182 "CALL d2l_wrapper\n"
11183 "fast:" %}
11184 ins_encode %{
11185 Label fast;
11186 __ subptr(rsp, 8);
11187 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11188 __ fld_s(Address(rsp, 0));
11189 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11190 __ fistp_d(Address(rsp, 0));
11191 // Restore the rounding mode, mask the exception
11192 if (Compile::current()->in_24_bit_fp_mode()) {
11193 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11194 } else {
11195 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11196 }
11197 // Load the converted long, adjust CPU stack
11198 __ pop(rax);
11199 __ pop(rdx);
11200 __ cmpl(rdx, 0x80000000);
11201 __ jccb(Assembler::notEqual, fast);
11202 __ testl(rax, rax);
11203 __ jccb(Assembler::notEqual, fast);
11204 __ subptr(rsp, 4);
11205 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11206 __ fld_s(Address(rsp, 0));
11207 __ addptr(rsp, 4);
11208 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11209 __ bind(fast);
11210 %}
11211 ins_pipe( pipe_slow );
11212 %}
11213
11214 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11215 predicate( UseSSE<=1 );
11216 match(Set dst (ConvI2D src));
11217 format %{ "FILD $src\n\t"
11218 "FSTP $dst" %}
11219 opcode(0xDB, 0x0); /* DB /0 */
11220 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11221 ins_pipe( fpu_reg_mem );
11222 %}
11223
11224 instruct convI2D_reg(regD dst, rRegI src) %{
11225 predicate( UseSSE>=2 && !UseXmmI2D );
11226 match(Set dst (ConvI2D src));
11227 format %{ "CVTSI2SD $dst,$src" %}
11228 ins_encode %{
11229 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11230 %}
11231 ins_pipe( pipe_slow );
11232 %}
11233
11234 instruct convI2D_mem(regD dst, memory mem) %{
11235 predicate( UseSSE>=2 );
11236 match(Set dst (ConvI2D (LoadI mem)));
11237 format %{ "CVTSI2SD $dst,$mem" %}
11238 ins_encode %{
11239 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11240 %}
11241 ins_pipe( pipe_slow );
11242 %}
11243
11244 instruct convXI2D_reg(regD dst, rRegI src)
11245 %{
11246 predicate( UseSSE>=2 && UseXmmI2D );
11247 match(Set dst (ConvI2D src));
11248
11249 format %{ "MOVD $dst,$src\n\t"
11250 "CVTDQ2PD $dst,$dst\t# i2d" %}
11251 ins_encode %{
11252 __ movdl($dst$$XMMRegister, $src$$Register);
11253 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11254 %}
11255 ins_pipe(pipe_slow); // XXX
11256 %}
11257
11258 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11259 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11260 match(Set dst (ConvI2D (LoadI mem)));
11261 format %{ "FILD $mem\n\t"
11262 "FSTP $dst" %}
11263 opcode(0xDB); /* DB /0 */
11264 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11265 Pop_Reg_DPR(dst));
11266 ins_pipe( fpu_reg_mem );
11267 %}
11268
11269 // Convert a byte to a float; no rounding step needed.
11270 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11271 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11272 match(Set dst (ConvI2F src));
11273 format %{ "FILD $src\n\t"
11274 "FSTP $dst" %}
11275
11276 opcode(0xDB, 0x0); /* DB /0 */
11277 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11278 ins_pipe( fpu_reg_mem );
11279 %}
11280
11281 // In 24-bit mode, force exponent rounding by storing back out
11282 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11283 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11284 match(Set dst (ConvI2F src));
11285 ins_cost(200);
11286 format %{ "FILD $src\n\t"
11287 "FSTP_S $dst" %}
11288 opcode(0xDB, 0x0); /* DB /0 */
11289 ins_encode( Push_Mem_I(src),
11290 Pop_Mem_FPR(dst));
11291 ins_pipe( fpu_mem_mem );
11292 %}
11293
11294 // In 24-bit mode, force exponent rounding by storing back out
11295 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11296 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11297 match(Set dst (ConvI2F (LoadI mem)));
11298 ins_cost(200);
11299 format %{ "FILD $mem\n\t"
11300 "FSTP_S $dst" %}
11301 opcode(0xDB); /* DB /0 */
11302 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11303 Pop_Mem_FPR(dst));
11304 ins_pipe( fpu_mem_mem );
11305 %}
11306
11307 // This instruction does not round to 24-bits
11308 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11309 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11310 match(Set dst (ConvI2F src));
11311 format %{ "FILD $src\n\t"
11312 "FSTP $dst" %}
11313 opcode(0xDB, 0x0); /* DB /0 */
11314 ins_encode( Push_Mem_I(src),
11315 Pop_Reg_FPR(dst));
11316 ins_pipe( fpu_reg_mem );
11317 %}
11318
11319 // This instruction does not round to 24-bits
11320 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11321 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11322 match(Set dst (ConvI2F (LoadI mem)));
11323 format %{ "FILD $mem\n\t"
11324 "FSTP $dst" %}
11325 opcode(0xDB); /* DB /0 */
11326 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11327 Pop_Reg_FPR(dst));
11328 ins_pipe( fpu_reg_mem );
11329 %}
11330
11331 // Convert an int to a float in xmm; no rounding step needed.
11332 instruct convI2F_reg(regF dst, rRegI src) %{
11333 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11334 match(Set dst (ConvI2F src));
11335 format %{ "CVTSI2SS $dst, $src" %}
11336 ins_encode %{
11337 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11338 %}
11339 ins_pipe( pipe_slow );
11340 %}
11341
11342 instruct convXI2F_reg(regF dst, rRegI src)
11343 %{
11344 predicate( UseSSE>=2 && UseXmmI2F );
11345 match(Set dst (ConvI2F src));
11346
11347 format %{ "MOVD $dst,$src\n\t"
11348 "CVTDQ2PS $dst,$dst\t# i2f" %}
11349 ins_encode %{
11350 __ movdl($dst$$XMMRegister, $src$$Register);
11351 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11352 %}
11353 ins_pipe(pipe_slow); // XXX
11354 %}
11355
11356 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11357 match(Set dst (ConvI2L src));
11358 effect(KILL cr);
11359 ins_cost(375);
11360 format %{ "MOV $dst.lo,$src\n\t"
11361 "MOV $dst.hi,$src\n\t"
11362 "SAR $dst.hi,31" %}
11363 ins_encode(convert_int_long(dst,src));
11364 ins_pipe( ialu_reg_reg_long );
11365 %}
11366
11367 // Zero-extend convert int to long
11368 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11369 match(Set dst (AndL (ConvI2L src) mask) );
11370 effect( KILL flags );
11371 ins_cost(250);
11372 format %{ "MOV $dst.lo,$src\n\t"
11373 "XOR $dst.hi,$dst.hi" %}
11374 opcode(0x33); // XOR
11375 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11376 ins_pipe( ialu_reg_reg_long );
11377 %}
11378
11379 // Zero-extend long
11380 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11381 match(Set dst (AndL src mask) );
11382 effect( KILL flags );
11383 ins_cost(250);
11384 format %{ "MOV $dst.lo,$src.lo\n\t"
11385 "XOR $dst.hi,$dst.hi\n\t" %}
11386 opcode(0x33); // XOR
11387 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11388 ins_pipe( ialu_reg_reg_long );
11389 %}
11390
11391 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11392 predicate (UseSSE<=1);
11393 match(Set dst (ConvL2D src));
11394 effect( KILL cr );
11395 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11396 "PUSH $src.lo\n\t"
11397 "FILD ST,[ESP + #0]\n\t"
11398 "ADD ESP,8\n\t"
11399 "FSTP_D $dst\t# D-round" %}
11400 opcode(0xDF, 0x5); /* DF /5 */
11401 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11402 ins_pipe( pipe_slow );
11403 %}
11404
11405 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11406 predicate (UseSSE>=2);
11407 match(Set dst (ConvL2D src));
11408 effect( KILL cr );
11409 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11410 "PUSH $src.lo\n\t"
11411 "FILD_D [ESP]\n\t"
11412 "FSTP_D [ESP]\n\t"
11413 "MOVSD $dst,[ESP]\n\t"
11414 "ADD ESP,8" %}
11415 opcode(0xDF, 0x5); /* DF /5 */
11416 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11417 ins_pipe( pipe_slow );
11418 %}
11419
11420 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11421 predicate (UseSSE>=1);
11422 match(Set dst (ConvL2F src));
11423 effect( KILL cr );
11424 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11425 "PUSH $src.lo\n\t"
11426 "FILD_D [ESP]\n\t"
11427 "FSTP_S [ESP]\n\t"
11428 "MOVSS $dst,[ESP]\n\t"
11429 "ADD ESP,8" %}
11430 opcode(0xDF, 0x5); /* DF /5 */
11431 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11432 ins_pipe( pipe_slow );
11433 %}
11434
11435 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11436 match(Set dst (ConvL2F src));
11437 effect( KILL cr );
11438 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11439 "PUSH $src.lo\n\t"
11440 "FILD ST,[ESP + #0]\n\t"
11441 "ADD ESP,8\n\t"
11442 "FSTP_S $dst\t# F-round" %}
11443 opcode(0xDF, 0x5); /* DF /5 */
11444 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11445 ins_pipe( pipe_slow );
11446 %}
11447
11448 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11449 match(Set dst (ConvL2I src));
11450 effect( DEF dst, USE src );
11451 format %{ "MOV $dst,$src.lo" %}
11452 ins_encode(enc_CopyL_Lo(dst,src));
11453 ins_pipe( ialu_reg_reg );
11454 %}
11455
11456
11457 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11458 match(Set dst (MoveF2I src));
11459 effect( DEF dst, USE src );
11460 ins_cost(100);
11461 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11462 ins_encode %{
11463 __ movl($dst$$Register, Address(rsp, $src$$disp));
11464 %}
11465 ins_pipe( ialu_reg_mem );
11466 %}
11467
11468 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11469 predicate(UseSSE==0);
11470 match(Set dst (MoveF2I src));
11471 effect( DEF dst, USE src );
11472
11473 ins_cost(125);
11474 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11475 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11476 ins_pipe( fpu_mem_reg );
11477 %}
11478
11479 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11480 predicate(UseSSE>=1);
11481 match(Set dst (MoveF2I src));
11482 effect( DEF dst, USE src );
11483
11484 ins_cost(95);
11485 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11486 ins_encode %{
11487 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11488 %}
11489 ins_pipe( pipe_slow );
11490 %}
11491
11492 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11493 predicate(UseSSE>=2);
11494 match(Set dst (MoveF2I src));
11495 effect( DEF dst, USE src );
11496 ins_cost(85);
11497 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11498 ins_encode %{
11499 __ movdl($dst$$Register, $src$$XMMRegister);
11500 %}
11501 ins_pipe( pipe_slow );
11502 %}
11503
11504 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11505 match(Set dst (MoveI2F src));
11506 effect( DEF dst, USE src );
11507
11508 ins_cost(100);
11509 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11510 ins_encode %{
11511 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11512 %}
11513 ins_pipe( ialu_mem_reg );
11514 %}
11515
11516
11517 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11518 predicate(UseSSE==0);
11519 match(Set dst (MoveI2F src));
11520 effect(DEF dst, USE src);
11521
11522 ins_cost(125);
11523 format %{ "FLD_S $src\n\t"
11524 "FSTP $dst\t# MoveI2F_stack_reg" %}
11525 opcode(0xD9); /* D9 /0, FLD m32real */
11526 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11527 Pop_Reg_FPR(dst) );
11528 ins_pipe( fpu_reg_mem );
11529 %}
11530
11531 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11532 predicate(UseSSE>=1);
11533 match(Set dst (MoveI2F src));
11534 effect( DEF dst, USE src );
11535
11536 ins_cost(95);
11537 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11538 ins_encode %{
11539 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11540 %}
11541 ins_pipe( pipe_slow );
11542 %}
11543
11544 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11545 predicate(UseSSE>=2);
11546 match(Set dst (MoveI2F src));
11547 effect( DEF dst, USE src );
11548
11549 ins_cost(85);
11550 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11551 ins_encode %{
11552 __ movdl($dst$$XMMRegister, $src$$Register);
11553 %}
11554 ins_pipe( pipe_slow );
11555 %}
11556
11557 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11558 match(Set dst (MoveD2L src));
11559 effect(DEF dst, USE src);
11560
11561 ins_cost(250);
11562 format %{ "MOV $dst.lo,$src\n\t"
11563 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11564 opcode(0x8B, 0x8B);
11565 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11566 ins_pipe( ialu_mem_long_reg );
11567 %}
11568
11569 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11570 predicate(UseSSE<=1);
11571 match(Set dst (MoveD2L src));
11572 effect(DEF dst, USE src);
11573
11574 ins_cost(125);
11575 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11576 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11577 ins_pipe( fpu_mem_reg );
11578 %}
11579
11580 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11581 predicate(UseSSE>=2);
11582 match(Set dst (MoveD2L src));
11583 effect(DEF dst, USE src);
11584 ins_cost(95);
11585 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11586 ins_encode %{
11587 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11588 %}
11589 ins_pipe( pipe_slow );
11590 %}
11591
11592 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11593 predicate(UseSSE>=2);
11594 match(Set dst (MoveD2L src));
11595 effect(DEF dst, USE src, TEMP tmp);
11596 ins_cost(85);
11597 format %{ "MOVD $dst.lo,$src\n\t"
11598 "PSHUFLW $tmp,$src,0x4E\n\t"
11599 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11600 ins_encode %{
11601 __ movdl($dst$$Register, $src$$XMMRegister);
11602 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11603 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11604 %}
11605 ins_pipe( pipe_slow );
11606 %}
11607
11608 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11609 match(Set dst (MoveL2D src));
11610 effect(DEF dst, USE src);
11611
11612 ins_cost(200);
11613 format %{ "MOV $dst,$src.lo\n\t"
11614 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11615 opcode(0x89, 0x89);
11616 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11617 ins_pipe( ialu_mem_long_reg );
11618 %}
11619
11620
11621 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11622 predicate(UseSSE<=1);
11623 match(Set dst (MoveL2D src));
11624 effect(DEF dst, USE src);
11625 ins_cost(125);
11626
11627 format %{ "FLD_D $src\n\t"
11628 "FSTP $dst\t# MoveL2D_stack_reg" %}
11629 opcode(0xDD); /* DD /0, FLD m64real */
11630 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11631 Pop_Reg_DPR(dst) );
11632 ins_pipe( fpu_reg_mem );
11633 %}
11634
11635
11636 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11637 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11638 match(Set dst (MoveL2D src));
11639 effect(DEF dst, USE src);
11640
11641 ins_cost(95);
11642 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11643 ins_encode %{
11644 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11645 %}
11646 ins_pipe( pipe_slow );
11647 %}
11648
11649 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11650 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11651 match(Set dst (MoveL2D src));
11652 effect(DEF dst, USE src);
11653
11654 ins_cost(95);
11655 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11656 ins_encode %{
11657 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11658 %}
11659 ins_pipe( pipe_slow );
11660 %}
11661
11662 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11663 predicate(UseSSE>=2);
11664 match(Set dst (MoveL2D src));
11665 effect(TEMP dst, USE src, TEMP tmp);
11666 ins_cost(85);
11667 format %{ "MOVD $dst,$src.lo\n\t"
11668 "MOVD $tmp,$src.hi\n\t"
11669 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11670 ins_encode %{
11671 __ movdl($dst$$XMMRegister, $src$$Register);
11672 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11673 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11674 %}
11675 ins_pipe( pipe_slow );
11676 %}
11677
11678
11679 // =======================================================================
11680 // fast clearing of an array
11681 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11682 predicate(!UseFastStosb);
11683 match(Set dummy (ClearArray cnt base));
11684 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11685 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11686 "SHL ECX,1\t# Convert doublewords to words\n\t"
11687 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11688 ins_encode %{
11689 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11690 %}
11691 ins_pipe( pipe_slow );
11692 %}
11693
11694 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11695 predicate(UseFastStosb);
11696 match(Set dummy (ClearArray cnt base));
11697 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11698 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11699 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11700 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11701 ins_encode %{
11702 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11703 %}
11704 ins_pipe( pipe_slow );
11705 %}
11706
11707 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11708 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11709 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11710 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11711
11712 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11713 ins_encode %{
11714 __ string_compare($str1$$Register, $str2$$Register,
11715 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11716 $tmp1$$XMMRegister);
11717 %}
11718 ins_pipe( pipe_slow );
11719 %}
11720
11721 // fast string equals
11722 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11723 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11724 match(Set result (StrEquals (Binary str1 str2) cnt));
11725 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11726
11727 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11728 ins_encode %{
11729 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11730 $cnt$$Register, $result$$Register, $tmp3$$Register,
11731 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11732 %}
11733 ins_pipe( pipe_slow );
11734 %}
11735
11736 // fast search of substring with known size.
11737 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11738 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11739 predicate(UseSSE42Intrinsics);
11740 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11741 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11742
11743 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11744 ins_encode %{
11745 int icnt2 = (int)$int_cnt2$$constant;
11746 if (icnt2 >= 8) {
11747 // IndexOf for constant substrings with size >= 8 elements
11748 // which don't need to be loaded through stack.
11749 __ string_indexofC8($str1$$Register, $str2$$Register,
11750 $cnt1$$Register, $cnt2$$Register,
11751 icnt2, $result$$Register,
11752 $vec$$XMMRegister, $tmp$$Register);
11753 } else {
11754 // Small strings are loaded through stack if they cross page boundary.
11755 __ string_indexof($str1$$Register, $str2$$Register,
11756 $cnt1$$Register, $cnt2$$Register,
11757 icnt2, $result$$Register,
11758 $vec$$XMMRegister, $tmp$$Register);
11759 }
11760 %}
11761 ins_pipe( pipe_slow );
11762 %}
11763
11764 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11765 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11766 predicate(UseSSE42Intrinsics);
11767 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11768 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11769
11770 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11771 ins_encode %{
11772 __ string_indexof($str1$$Register, $str2$$Register,
11773 $cnt1$$Register, $cnt2$$Register,
11774 (-1), $result$$Register,
11775 $vec$$XMMRegister, $tmp$$Register);
11776 %}
11777 ins_pipe( pipe_slow );
11778 %}
11779
11780 // fast array equals
11781 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11782 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11783 %{
11784 match(Set result (AryEq ary1 ary2));
11785 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11786 //ins_cost(300);
11787
11788 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11789 ins_encode %{
11790 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11791 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11792 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11793 %}
11794 ins_pipe( pipe_slow );
11795 %}
11796
11797 // encode char[] to byte[] in ISO_8859_1
11798 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11799 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11800 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11801 match(Set result (EncodeISOArray src (Binary dst len)));
11802 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11803
11804 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11805 ins_encode %{
11806 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11807 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11808 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11809 %}
11810 ins_pipe( pipe_slow );
11811 %}
11812
11813
11814 //----------Control Flow Instructions------------------------------------------
11815 // Signed compare Instructions
11816 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11817 match(Set cr (CmpI op1 op2));
11818 effect( DEF cr, USE op1, USE op2 );
11819 format %{ "CMP $op1,$op2" %}
11820 opcode(0x3B); /* Opcode 3B /r */
11821 ins_encode( OpcP, RegReg( op1, op2) );
11822 ins_pipe( ialu_cr_reg_reg );
11823 %}
11824
11825 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11826 match(Set cr (CmpI op1 op2));
11827 effect( DEF cr, USE op1 );
11828 format %{ "CMP $op1,$op2" %}
11829 opcode(0x81,0x07); /* Opcode 81 /7 */
11830 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11831 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11832 ins_pipe( ialu_cr_reg_imm );
11833 %}
11834
11835 // Cisc-spilled version of cmpI_eReg
11836 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11837 match(Set cr (CmpI op1 (LoadI op2)));
11838
11839 format %{ "CMP $op1,$op2" %}
11840 ins_cost(500);
11841 opcode(0x3B); /* Opcode 3B /r */
11842 ins_encode( OpcP, RegMem( op1, op2) );
11843 ins_pipe( ialu_cr_reg_mem );
11844 %}
11845
11846 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11847 match(Set cr (CmpI src zero));
11848 effect( DEF cr, USE src );
11849
11850 format %{ "TEST $src,$src" %}
11851 opcode(0x85);
11852 ins_encode( OpcP, RegReg( src, src ) );
11853 ins_pipe( ialu_cr_reg_imm );
11854 %}
11855
11856 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11857 match(Set cr (CmpI (AndI src con) zero));
11858
11859 format %{ "TEST $src,$con" %}
11860 opcode(0xF7,0x00);
11861 ins_encode( OpcP, RegOpc(src), Con32(con) );
11862 ins_pipe( ialu_cr_reg_imm );
11863 %}
11864
11865 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11866 match(Set cr (CmpI (AndI src mem) zero));
11867
11868 format %{ "TEST $src,$mem" %}
11869 opcode(0x85);
11870 ins_encode( OpcP, RegMem( src, mem ) );
11871 ins_pipe( ialu_cr_reg_mem );
11872 %}
11873
11874 // Unsigned compare Instructions; really, same as signed except they
11875 // produce an eFlagsRegU instead of eFlagsReg.
11876 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11877 match(Set cr (CmpU op1 op2));
11878
11879 format %{ "CMPu $op1,$op2" %}
11880 opcode(0x3B); /* Opcode 3B /r */
11881 ins_encode( OpcP, RegReg( op1, op2) );
11882 ins_pipe( ialu_cr_reg_reg );
11883 %}
11884
11885 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11886 match(Set cr (CmpU op1 op2));
11887
11888 format %{ "CMPu $op1,$op2" %}
11889 opcode(0x81,0x07); /* Opcode 81 /7 */
11890 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11891 ins_pipe( ialu_cr_reg_imm );
11892 %}
11893
11894 // // Cisc-spilled version of cmpU_eReg
11895 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11896 match(Set cr (CmpU op1 (LoadI op2)));
11897
11898 format %{ "CMPu $op1,$op2" %}
11899 ins_cost(500);
11900 opcode(0x3B); /* Opcode 3B /r */
11901 ins_encode( OpcP, RegMem( op1, op2) );
11902 ins_pipe( ialu_cr_reg_mem );
11903 %}
11904
11905 // // Cisc-spilled version of cmpU_eReg
11906 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11907 // match(Set cr (CmpU (LoadI op1) op2));
11908 //
11909 // format %{ "CMPu $op1,$op2" %}
11910 // ins_cost(500);
11911 // opcode(0x39); /* Opcode 39 /r */
11912 // ins_encode( OpcP, RegMem( op1, op2) );
11913 //%}
11914
11915 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11916 match(Set cr (CmpU src zero));
11917
11918 format %{ "TESTu $src,$src" %}
11919 opcode(0x85);
11920 ins_encode( OpcP, RegReg( src, src ) );
11921 ins_pipe( ialu_cr_reg_imm );
11922 %}
11923
11924 // Unsigned pointer compare Instructions
11925 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11926 match(Set cr (CmpP op1 op2));
11927
11928 format %{ "CMPu $op1,$op2" %}
11929 opcode(0x3B); /* Opcode 3B /r */
11930 ins_encode( OpcP, RegReg( op1, op2) );
11931 ins_pipe( ialu_cr_reg_reg );
11932 %}
11933
11934 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11935 match(Set cr (CmpP op1 op2));
11936
11937 format %{ "CMPu $op1,$op2" %}
11938 opcode(0x81,0x07); /* Opcode 81 /7 */
11939 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11940 ins_pipe( ialu_cr_reg_imm );
11941 %}
11942
11943 // // Cisc-spilled version of cmpP_eReg
11944 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11945 match(Set cr (CmpP op1 (LoadP op2)));
11946
11947 format %{ "CMPu $op1,$op2" %}
11948 ins_cost(500);
11949 opcode(0x3B); /* Opcode 3B /r */
11950 ins_encode( OpcP, RegMem( op1, op2) );
11951 ins_pipe( ialu_cr_reg_mem );
11952 %}
11953
11954 // // Cisc-spilled version of cmpP_eReg
11955 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11956 // match(Set cr (CmpP (LoadP op1) op2));
11957 //
11958 // format %{ "CMPu $op1,$op2" %}
11959 // ins_cost(500);
11960 // opcode(0x39); /* Opcode 39 /r */
11961 // ins_encode( OpcP, RegMem( op1, op2) );
11962 //%}
11963
11964 // Compare raw pointer (used in out-of-heap check).
11965 // Only works because non-oop pointers must be raw pointers
11966 // and raw pointers have no anti-dependencies.
11967 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11968 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11969 match(Set cr (CmpP op1 (LoadP op2)));
11970
11971 format %{ "CMPu $op1,$op2" %}
11972 opcode(0x3B); /* Opcode 3B /r */
11973 ins_encode( OpcP, RegMem( op1, op2) );
11974 ins_pipe( ialu_cr_reg_mem );
11975 %}
11976
11977 //
11978 // This will generate a signed flags result. This should be ok
11979 // since any compare to a zero should be eq/neq.
11980 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11981 match(Set cr (CmpP src zero));
11982
11983 format %{ "TEST $src,$src" %}
11984 opcode(0x85);
11985 ins_encode( OpcP, RegReg( src, src ) );
11986 ins_pipe( ialu_cr_reg_imm );
11987 %}
11988
11989 // Cisc-spilled version of testP_reg
11990 // This will generate a signed flags result. This should be ok
11991 // since any compare to a zero should be eq/neq.
11992 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11993 match(Set cr (CmpP (LoadP op) zero));
11994
11995 format %{ "TEST $op,0xFFFFFFFF" %}
11996 ins_cost(500);
11997 opcode(0xF7); /* Opcode F7 /0 */
11998 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11999 ins_pipe( ialu_cr_reg_imm );
12000 %}
12001
12002 // Yanked all unsigned pointer compare operations.
12003 // Pointer compares are done with CmpP which is already unsigned.
12004
12005 //----------Max and Min--------------------------------------------------------
12006 // Min Instructions
12007 ////
12008 // *** Min and Max using the conditional move are slower than the
12009 // *** branch version on a Pentium III.
12010 // // Conditional move for min
12011 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12012 // effect( USE_DEF op2, USE op1, USE cr );
12013 // format %{ "CMOVlt $op2,$op1\t! min" %}
12014 // opcode(0x4C,0x0F);
12015 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12016 // ins_pipe( pipe_cmov_reg );
12017 //%}
12018 //
12019 //// Min Register with Register (P6 version)
12020 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12021 // predicate(VM_Version::supports_cmov() );
12022 // match(Set op2 (MinI op1 op2));
12023 // ins_cost(200);
12024 // expand %{
12025 // eFlagsReg cr;
12026 // compI_eReg(cr,op1,op2);
12027 // cmovI_reg_lt(op2,op1,cr);
12028 // %}
12029 //%}
12030
12031 // Min Register with Register (generic version)
12032 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12033 match(Set dst (MinI dst src));
12034 effect(KILL flags);
12035 ins_cost(300);
12036
12037 format %{ "MIN $dst,$src" %}
12038 opcode(0xCC);
12039 ins_encode( min_enc(dst,src) );
12040 ins_pipe( pipe_slow );
12041 %}
12042
12043 // Max Register with Register
12044 // *** Min and Max using the conditional move are slower than the
12045 // *** branch version on a Pentium III.
12046 // // Conditional move for max
12047 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12048 // effect( USE_DEF op2, USE op1, USE cr );
12049 // format %{ "CMOVgt $op2,$op1\t! max" %}
12050 // opcode(0x4F,0x0F);
12051 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12052 // ins_pipe( pipe_cmov_reg );
12053 //%}
12054 //
12055 // // Max Register with Register (P6 version)
12056 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12057 // predicate(VM_Version::supports_cmov() );
12058 // match(Set op2 (MaxI op1 op2));
12059 // ins_cost(200);
12060 // expand %{
12061 // eFlagsReg cr;
12062 // compI_eReg(cr,op1,op2);
12063 // cmovI_reg_gt(op2,op1,cr);
12064 // %}
12065 //%}
12066
12067 // Max Register with Register (generic version)
12068 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12069 match(Set dst (MaxI dst src));
12070 effect(KILL flags);
12071 ins_cost(300);
12072
12073 format %{ "MAX $dst,$src" %}
12074 opcode(0xCC);
12075 ins_encode( max_enc(dst,src) );
12076 ins_pipe( pipe_slow );
12077 %}
12078
12079 // ============================================================================
12080 // Counted Loop limit node which represents exact final iterator value.
12081 // Note: the resulting value should fit into integer range since
12082 // counted loops have limit check on overflow.
12083 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12084 match(Set limit (LoopLimit (Binary init limit) stride));
12085 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12086 ins_cost(300);
12087
12088 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12089 ins_encode %{
12090 int strd = (int)$stride$$constant;
12091 assert(strd != 1 && strd != -1, "sanity");
12092 int m1 = (strd > 0) ? 1 : -1;
12093 // Convert limit to long (EAX:EDX)
12094 __ cdql();
12095 // Convert init to long (init:tmp)
12096 __ movl($tmp$$Register, $init$$Register);
12097 __ sarl($tmp$$Register, 31);
12098 // $limit - $init
12099 __ subl($limit$$Register, $init$$Register);
12100 __ sbbl($limit_hi$$Register, $tmp$$Register);
12101 // + ($stride - 1)
12102 if (strd > 0) {
12103 __ addl($limit$$Register, (strd - 1));
12104 __ adcl($limit_hi$$Register, 0);
12105 __ movl($tmp$$Register, strd);
12106 } else {
12107 __ addl($limit$$Register, (strd + 1));
12108 __ adcl($limit_hi$$Register, -1);
12109 __ lneg($limit_hi$$Register, $limit$$Register);
12110 __ movl($tmp$$Register, -strd);
12111 }
12112 // signed devision: (EAX:EDX) / pos_stride
12113 __ idivl($tmp$$Register);
12114 if (strd < 0) {
12115 // restore sign
12116 __ negl($tmp$$Register);
12117 }
12118 // (EAX) * stride
12119 __ mull($tmp$$Register);
12120 // + init (ignore upper bits)
12121 __ addl($limit$$Register, $init$$Register);
12122 %}
12123 ins_pipe( pipe_slow );
12124 %}
12125
12126 // ============================================================================
12127 // Branch Instructions
12128 // Jump Table
12129 instruct jumpXtnd(rRegI switch_val) %{
12130 match(Jump switch_val);
12131 ins_cost(350);
12132 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12133 ins_encode %{
12134 // Jump to Address(table_base + switch_reg)
12135 Address index(noreg, $switch_val$$Register, Address::times_1);
12136 __ jump(ArrayAddress($constantaddress, index));
12137 %}
12138 ins_pipe(pipe_jmp);
12139 %}
12140
12141 // Jump Direct - Label defines a relative address from JMP+1
12142 instruct jmpDir(label labl) %{
12143 match(Goto);
12144 effect(USE labl);
12145
12146 ins_cost(300);
12147 format %{ "JMP $labl" %}
12148 size(5);
12149 ins_encode %{
12150 Label* L = $labl$$label;
12151 __ jmp(*L, false); // Always long jump
12152 %}
12153 ins_pipe( pipe_jmp );
12154 %}
12155
12156 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12157 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12158 match(If cop cr);
12159 effect(USE labl);
12160
12161 ins_cost(300);
12162 format %{ "J$cop $labl" %}
12163 size(6);
12164 ins_encode %{
12165 Label* L = $labl$$label;
12166 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12167 %}
12168 ins_pipe( pipe_jcc );
12169 %}
12170
12171 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12172 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12173 match(CountedLoopEnd cop cr);
12174 effect(USE labl);
12175
12176 ins_cost(300);
12177 format %{ "J$cop $labl\t# Loop end" %}
12178 size(6);
12179 ins_encode %{
12180 Label* L = $labl$$label;
12181 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12182 %}
12183 ins_pipe( pipe_jcc );
12184 %}
12185
12186 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12187 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12188 match(CountedLoopEnd cop cmp);
12189 effect(USE labl);
12190
12191 ins_cost(300);
12192 format %{ "J$cop,u $labl\t# Loop end" %}
12193 size(6);
12194 ins_encode %{
12195 Label* L = $labl$$label;
12196 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12197 %}
12198 ins_pipe( pipe_jcc );
12199 %}
12200
12201 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12202 match(CountedLoopEnd cop cmp);
12203 effect(USE labl);
12204
12205 ins_cost(200);
12206 format %{ "J$cop,u $labl\t# Loop end" %}
12207 size(6);
12208 ins_encode %{
12209 Label* L = $labl$$label;
12210 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12211 %}
12212 ins_pipe( pipe_jcc );
12213 %}
12214
12215 // Jump Direct Conditional - using unsigned comparison
12216 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12217 match(If cop cmp);
12218 effect(USE labl);
12219
12220 ins_cost(300);
12221 format %{ "J$cop,u $labl" %}
12222 size(6);
12223 ins_encode %{
12224 Label* L = $labl$$label;
12225 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12226 %}
12227 ins_pipe(pipe_jcc);
12228 %}
12229
12230 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12231 match(If cop cmp);
12232 effect(USE labl);
12233
12234 ins_cost(200);
12235 format %{ "J$cop,u $labl" %}
12236 size(6);
12237 ins_encode %{
12238 Label* L = $labl$$label;
12239 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12240 %}
12241 ins_pipe(pipe_jcc);
12242 %}
12243
12244 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12245 match(If cop cmp);
12246 effect(USE labl);
12247
12248 ins_cost(200);
12249 format %{ $$template
12250 if ($cop$$cmpcode == Assembler::notEqual) {
12251 $$emit$$"JP,u $labl\n\t"
12252 $$emit$$"J$cop,u $labl"
12253 } else {
12254 $$emit$$"JP,u done\n\t"
12255 $$emit$$"J$cop,u $labl\n\t"
12256 $$emit$$"done:"
12257 }
12258 %}
12259 ins_encode %{
12260 Label* l = $labl$$label;
12261 if ($cop$$cmpcode == Assembler::notEqual) {
12262 __ jcc(Assembler::parity, *l, false);
12263 __ jcc(Assembler::notEqual, *l, false);
12264 } else if ($cop$$cmpcode == Assembler::equal) {
12265 Label done;
12266 __ jccb(Assembler::parity, done);
12267 __ jcc(Assembler::equal, *l, false);
12268 __ bind(done);
12269 } else {
12270 ShouldNotReachHere();
12271 }
12272 %}
12273 ins_pipe(pipe_jcc);
12274 %}
12275
12276 // ============================================================================
12277 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12278 // array for an instance of the superklass. Set a hidden internal cache on a
12279 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12280 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12281 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12282 match(Set result (PartialSubtypeCheck sub super));
12283 effect( KILL rcx, KILL cr );
12284
12285 ins_cost(1100); // slightly larger than the next version
12286 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12287 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12288 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12289 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12290 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12291 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12292 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12293 "miss:\t" %}
12294
12295 opcode(0x1); // Force a XOR of EDI
12296 ins_encode( enc_PartialSubtypeCheck() );
12297 ins_pipe( pipe_slow );
12298 %}
12299
12300 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12301 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12302 effect( KILL rcx, KILL result );
12303
12304 ins_cost(1000);
12305 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12306 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12307 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12308 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12309 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12310 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12311 "miss:\t" %}
12312
12313 opcode(0x0); // No need to XOR EDI
12314 ins_encode( enc_PartialSubtypeCheck() );
12315 ins_pipe( pipe_slow );
12316 %}
12317
12318 // ============================================================================
12319 // Branch Instructions -- short offset versions
12320 //
12321 // These instructions are used to replace jumps of a long offset (the default
12322 // match) with jumps of a shorter offset. These instructions are all tagged
12323 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12324 // match rules in general matching. Instead, the ADLC generates a conversion
12325 // method in the MachNode which can be used to do in-place replacement of the
12326 // long variant with the shorter variant. The compiler will determine if a
12327 // branch can be taken by the is_short_branch_offset() predicate in the machine
12328 // specific code section of the file.
12329
12330 // Jump Direct - Label defines a relative address from JMP+1
12331 instruct jmpDir_short(label labl) %{
12332 match(Goto);
12333 effect(USE labl);
12334
12335 ins_cost(300);
12336 format %{ "JMP,s $labl" %}
12337 size(2);
12338 ins_encode %{
12339 Label* L = $labl$$label;
12340 __ jmpb(*L);
12341 %}
12342 ins_pipe( pipe_jmp );
12343 ins_short_branch(1);
12344 %}
12345
12346 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12347 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12348 match(If cop cr);
12349 effect(USE labl);
12350
12351 ins_cost(300);
12352 format %{ "J$cop,s $labl" %}
12353 size(2);
12354 ins_encode %{
12355 Label* L = $labl$$label;
12356 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12357 %}
12358 ins_pipe( pipe_jcc );
12359 ins_short_branch(1);
12360 %}
12361
12362 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12363 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12364 match(CountedLoopEnd cop cr);
12365 effect(USE labl);
12366
12367 ins_cost(300);
12368 format %{ "J$cop,s $labl\t# Loop end" %}
12369 size(2);
12370 ins_encode %{
12371 Label* L = $labl$$label;
12372 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12373 %}
12374 ins_pipe( pipe_jcc );
12375 ins_short_branch(1);
12376 %}
12377
12378 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12379 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12380 match(CountedLoopEnd cop cmp);
12381 effect(USE labl);
12382
12383 ins_cost(300);
12384 format %{ "J$cop,us $labl\t# Loop end" %}
12385 size(2);
12386 ins_encode %{
12387 Label* L = $labl$$label;
12388 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12389 %}
12390 ins_pipe( pipe_jcc );
12391 ins_short_branch(1);
12392 %}
12393
12394 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12395 match(CountedLoopEnd cop cmp);
12396 effect(USE labl);
12397
12398 ins_cost(300);
12399 format %{ "J$cop,us $labl\t# Loop end" %}
12400 size(2);
12401 ins_encode %{
12402 Label* L = $labl$$label;
12403 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12404 %}
12405 ins_pipe( pipe_jcc );
12406 ins_short_branch(1);
12407 %}
12408
12409 // Jump Direct Conditional - using unsigned comparison
12410 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12411 match(If cop cmp);
12412 effect(USE labl);
12413
12414 ins_cost(300);
12415 format %{ "J$cop,us $labl" %}
12416 size(2);
12417 ins_encode %{
12418 Label* L = $labl$$label;
12419 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12420 %}
12421 ins_pipe( pipe_jcc );
12422 ins_short_branch(1);
12423 %}
12424
12425 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12426 match(If cop cmp);
12427 effect(USE labl);
12428
12429 ins_cost(300);
12430 format %{ "J$cop,us $labl" %}
12431 size(2);
12432 ins_encode %{
12433 Label* L = $labl$$label;
12434 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12435 %}
12436 ins_pipe( pipe_jcc );
12437 ins_short_branch(1);
12438 %}
12439
12440 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12441 match(If cop cmp);
12442 effect(USE labl);
12443
12444 ins_cost(300);
12445 format %{ $$template
12446 if ($cop$$cmpcode == Assembler::notEqual) {
12447 $$emit$$"JP,u,s $labl\n\t"
12448 $$emit$$"J$cop,u,s $labl"
12449 } else {
12450 $$emit$$"JP,u,s done\n\t"
12451 $$emit$$"J$cop,u,s $labl\n\t"
12452 $$emit$$"done:"
12453 }
12454 %}
12455 size(4);
12456 ins_encode %{
12457 Label* l = $labl$$label;
12458 if ($cop$$cmpcode == Assembler::notEqual) {
12459 __ jccb(Assembler::parity, *l);
12460 __ jccb(Assembler::notEqual, *l);
12461 } else if ($cop$$cmpcode == Assembler::equal) {
12462 Label done;
12463 __ jccb(Assembler::parity, done);
12464 __ jccb(Assembler::equal, *l);
12465 __ bind(done);
12466 } else {
12467 ShouldNotReachHere();
12468 }
12469 %}
12470 ins_pipe(pipe_jcc);
12471 ins_short_branch(1);
12472 %}
12473
12474 // ============================================================================
12475 // Long Compare
12476 //
12477 // Currently we hold longs in 2 registers. Comparing such values efficiently
12478 // is tricky. The flavor of compare used depends on whether we are testing
12479 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12480 // The GE test is the negated LT test. The LE test can be had by commuting
12481 // the operands (yielding a GE test) and then negating; negate again for the
12482 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12483 // NE test is negated from that.
12484
12485 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12486 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12487 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12488 // are collapsed internally in the ADLC's dfa-gen code. The match for
12489 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12490 // foo match ends up with the wrong leaf. One fix is to not match both
12491 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12492 // both forms beat the trinary form of long-compare and both are very useful
12493 // on Intel which has so few registers.
12494
12495 // Manifest a CmpL result in an integer register. Very painful.
12496 // This is the test to avoid.
12497 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12498 match(Set dst (CmpL3 src1 src2));
12499 effect( KILL flags );
12500 ins_cost(1000);
12501 format %{ "XOR $dst,$dst\n\t"
12502 "CMP $src1.hi,$src2.hi\n\t"
12503 "JLT,s m_one\n\t"
12504 "JGT,s p_one\n\t"
12505 "CMP $src1.lo,$src2.lo\n\t"
12506 "JB,s m_one\n\t"
12507 "JEQ,s done\n"
12508 "p_one:\tINC $dst\n\t"
12509 "JMP,s done\n"
12510 "m_one:\tDEC $dst\n"
12511 "done:" %}
12512 ins_encode %{
12513 Label p_one, m_one, done;
12514 __ xorptr($dst$$Register, $dst$$Register);
12515 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12516 __ jccb(Assembler::less, m_one);
12517 __ jccb(Assembler::greater, p_one);
12518 __ cmpl($src1$$Register, $src2$$Register);
12519 __ jccb(Assembler::below, m_one);
12520 __ jccb(Assembler::equal, done);
12521 __ bind(p_one);
12522 __ incrementl($dst$$Register);
12523 __ jmpb(done);
12524 __ bind(m_one);
12525 __ decrementl($dst$$Register);
12526 __ bind(done);
12527 %}
12528 ins_pipe( pipe_slow );
12529 %}
12530
12531 //======
12532 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12533 // compares. Can be used for LE or GT compares by reversing arguments.
12534 // NOT GOOD FOR EQ/NE tests.
12535 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12536 match( Set flags (CmpL src zero ));
12537 ins_cost(100);
12538 format %{ "TEST $src.hi,$src.hi" %}
12539 opcode(0x85);
12540 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12541 ins_pipe( ialu_cr_reg_reg );
12542 %}
12543
12544 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12545 // compares. Can be used for LE or GT compares by reversing arguments.
12546 // NOT GOOD FOR EQ/NE tests.
12547 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12548 match( Set flags (CmpL src1 src2 ));
12549 effect( TEMP tmp );
12550 ins_cost(300);
12551 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12552 "MOV $tmp,$src1.hi\n\t"
12553 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12554 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12555 ins_pipe( ialu_cr_reg_reg );
12556 %}
12557
12558 // Long compares reg < zero/req OR reg >= zero/req.
12559 // Just a wrapper for a normal branch, plus the predicate test.
12560 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12561 match(If cmp flags);
12562 effect(USE labl);
12563 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12564 expand %{
12565 jmpCon(cmp,flags,labl); // JLT or JGE...
12566 %}
12567 %}
12568
12569 // Compare 2 longs and CMOVE longs.
12570 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12571 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12572 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12573 ins_cost(400);
12574 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12575 "CMOV$cmp $dst.hi,$src.hi" %}
12576 opcode(0x0F,0x40);
12577 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12578 ins_pipe( pipe_cmov_reg_long );
12579 %}
12580
12581 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12582 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12583 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12584 ins_cost(500);
12585 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12586 "CMOV$cmp $dst.hi,$src.hi" %}
12587 opcode(0x0F,0x40);
12588 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12589 ins_pipe( pipe_cmov_reg_long );
12590 %}
12591
12592 // Compare 2 longs and CMOVE ints.
12593 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12594 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12595 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12596 ins_cost(200);
12597 format %{ "CMOV$cmp $dst,$src" %}
12598 opcode(0x0F,0x40);
12599 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12600 ins_pipe( pipe_cmov_reg );
12601 %}
12602
12603 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12604 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12605 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12606 ins_cost(250);
12607 format %{ "CMOV$cmp $dst,$src" %}
12608 opcode(0x0F,0x40);
12609 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12610 ins_pipe( pipe_cmov_mem );
12611 %}
12612
12613 // Compare 2 longs and CMOVE ints.
12614 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12615 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12616 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12617 ins_cost(200);
12618 format %{ "CMOV$cmp $dst,$src" %}
12619 opcode(0x0F,0x40);
12620 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12621 ins_pipe( pipe_cmov_reg );
12622 %}
12623
12624 // Compare 2 longs and CMOVE doubles
12625 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12626 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12627 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12628 ins_cost(200);
12629 expand %{
12630 fcmovDPR_regS(cmp,flags,dst,src);
12631 %}
12632 %}
12633
12634 // Compare 2 longs and CMOVE doubles
12635 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12636 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12637 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12638 ins_cost(200);
12639 expand %{
12640 fcmovD_regS(cmp,flags,dst,src);
12641 %}
12642 %}
12643
12644 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12645 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12646 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12647 ins_cost(200);
12648 expand %{
12649 fcmovFPR_regS(cmp,flags,dst,src);
12650 %}
12651 %}
12652
12653 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12654 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12655 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12656 ins_cost(200);
12657 expand %{
12658 fcmovF_regS(cmp,flags,dst,src);
12659 %}
12660 %}
12661
12662 //======
12663 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12664 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12665 match( Set flags (CmpL src zero ));
12666 effect(TEMP tmp);
12667 ins_cost(200);
12668 format %{ "MOV $tmp,$src.lo\n\t"
12669 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12670 ins_encode( long_cmp_flags0( src, tmp ) );
12671 ins_pipe( ialu_reg_reg_long );
12672 %}
12673
12674 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12675 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12676 match( Set flags (CmpL src1 src2 ));
12677 ins_cost(200+300);
12678 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12679 "JNE,s skip\n\t"
12680 "CMP $src1.hi,$src2.hi\n\t"
12681 "skip:\t" %}
12682 ins_encode( long_cmp_flags1( src1, src2 ) );
12683 ins_pipe( ialu_cr_reg_reg );
12684 %}
12685
12686 // Long compare reg == zero/reg OR reg != zero/reg
12687 // Just a wrapper for a normal branch, plus the predicate test.
12688 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12689 match(If cmp flags);
12690 effect(USE labl);
12691 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12692 expand %{
12693 jmpCon(cmp,flags,labl); // JEQ or JNE...
12694 %}
12695 %}
12696
12697 // Compare 2 longs and CMOVE longs.
12698 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12699 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12700 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12701 ins_cost(400);
12702 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12703 "CMOV$cmp $dst.hi,$src.hi" %}
12704 opcode(0x0F,0x40);
12705 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12706 ins_pipe( pipe_cmov_reg_long );
12707 %}
12708
12709 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12710 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12712 ins_cost(500);
12713 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12714 "CMOV$cmp $dst.hi,$src.hi" %}
12715 opcode(0x0F,0x40);
12716 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12717 ins_pipe( pipe_cmov_reg_long );
12718 %}
12719
12720 // Compare 2 longs and CMOVE ints.
12721 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12722 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12723 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12724 ins_cost(200);
12725 format %{ "CMOV$cmp $dst,$src" %}
12726 opcode(0x0F,0x40);
12727 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12728 ins_pipe( pipe_cmov_reg );
12729 %}
12730
12731 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12732 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12733 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12734 ins_cost(250);
12735 format %{ "CMOV$cmp $dst,$src" %}
12736 opcode(0x0F,0x40);
12737 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12738 ins_pipe( pipe_cmov_mem );
12739 %}
12740
12741 // Compare 2 longs and CMOVE ints.
12742 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12743 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12744 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12745 ins_cost(200);
12746 format %{ "CMOV$cmp $dst,$src" %}
12747 opcode(0x0F,0x40);
12748 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12749 ins_pipe( pipe_cmov_reg );
12750 %}
12751
12752 // Compare 2 longs and CMOVE doubles
12753 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12754 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12755 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12756 ins_cost(200);
12757 expand %{
12758 fcmovDPR_regS(cmp,flags,dst,src);
12759 %}
12760 %}
12761
12762 // Compare 2 longs and CMOVE doubles
12763 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12764 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12765 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12766 ins_cost(200);
12767 expand %{
12768 fcmovD_regS(cmp,flags,dst,src);
12769 %}
12770 %}
12771
12772 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12773 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12774 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12775 ins_cost(200);
12776 expand %{
12777 fcmovFPR_regS(cmp,flags,dst,src);
12778 %}
12779 %}
12780
12781 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12782 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12783 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12784 ins_cost(200);
12785 expand %{
12786 fcmovF_regS(cmp,flags,dst,src);
12787 %}
12788 %}
12789
12790 //======
12791 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12792 // Same as cmpL_reg_flags_LEGT except must negate src
12793 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12794 match( Set flags (CmpL src zero ));
12795 effect( TEMP tmp );
12796 ins_cost(300);
12797 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12798 "CMP $tmp,$src.lo\n\t"
12799 "SBB $tmp,$src.hi\n\t" %}
12800 ins_encode( long_cmp_flags3(src, tmp) );
12801 ins_pipe( ialu_reg_reg_long );
12802 %}
12803
12804 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12805 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12806 // requires a commuted test to get the same result.
12807 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12808 match( Set flags (CmpL src1 src2 ));
12809 effect( TEMP tmp );
12810 ins_cost(300);
12811 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12812 "MOV $tmp,$src2.hi\n\t"
12813 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12814 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12815 ins_pipe( ialu_cr_reg_reg );
12816 %}
12817
12818 // Long compares reg < zero/req OR reg >= zero/req.
12819 // Just a wrapper for a normal branch, plus the predicate test
12820 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12821 match(If cmp flags);
12822 effect(USE labl);
12823 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12824 ins_cost(300);
12825 expand %{
12826 jmpCon(cmp,flags,labl); // JGT or JLE...
12827 %}
12828 %}
12829
12830 // Compare 2 longs and CMOVE longs.
12831 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12832 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12833 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12834 ins_cost(400);
12835 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12836 "CMOV$cmp $dst.hi,$src.hi" %}
12837 opcode(0x0F,0x40);
12838 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12839 ins_pipe( pipe_cmov_reg_long );
12840 %}
12841
12842 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12843 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12844 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12845 ins_cost(500);
12846 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12847 "CMOV$cmp $dst.hi,$src.hi+4" %}
12848 opcode(0x0F,0x40);
12849 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12850 ins_pipe( pipe_cmov_reg_long );
12851 %}
12852
12853 // Compare 2 longs and CMOVE ints.
12854 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12855 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12856 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12857 ins_cost(200);
12858 format %{ "CMOV$cmp $dst,$src" %}
12859 opcode(0x0F,0x40);
12860 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12861 ins_pipe( pipe_cmov_reg );
12862 %}
12863
12864 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12865 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12866 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12867 ins_cost(250);
12868 format %{ "CMOV$cmp $dst,$src" %}
12869 opcode(0x0F,0x40);
12870 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12871 ins_pipe( pipe_cmov_mem );
12872 %}
12873
12874 // Compare 2 longs and CMOVE ptrs.
12875 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12876 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12877 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12878 ins_cost(200);
12879 format %{ "CMOV$cmp $dst,$src" %}
12880 opcode(0x0F,0x40);
12881 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12882 ins_pipe( pipe_cmov_reg );
12883 %}
12884
12885 // Compare 2 longs and CMOVE doubles
12886 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12887 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12888 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12889 ins_cost(200);
12890 expand %{
12891 fcmovDPR_regS(cmp,flags,dst,src);
12892 %}
12893 %}
12894
12895 // Compare 2 longs and CMOVE doubles
12896 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12897 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12898 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12899 ins_cost(200);
12900 expand %{
12901 fcmovD_regS(cmp,flags,dst,src);
12902 %}
12903 %}
12904
12905 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12906 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12907 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12908 ins_cost(200);
12909 expand %{
12910 fcmovFPR_regS(cmp,flags,dst,src);
12911 %}
12912 %}
12913
12914
12915 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12916 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12917 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12918 ins_cost(200);
12919 expand %{
12920 fcmovF_regS(cmp,flags,dst,src);
12921 %}
12922 %}
12923
12924
12925 // ============================================================================
12926 // Procedure Call/Return Instructions
12927 // Call Java Static Instruction
12928 // Note: If this code changes, the corresponding ret_addr_offset() and
12929 // compute_padding() functions will have to be adjusted.
12930 instruct CallStaticJavaDirect(method meth) %{
12931 match(CallStaticJava);
12932 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12933 effect(USE meth);
12934
12935 ins_cost(300);
12936 format %{ "CALL,static " %}
12937 opcode(0xE8); /* E8 cd */
12938 ins_encode( pre_call_resets,
12939 Java_Static_Call( meth ),
12940 call_epilog,
12941 post_call_FPU );
12942 ins_pipe( pipe_slow );
12943 ins_alignment(4);
12944 %}
12945
12946 // Call Java Static Instruction (method handle version)
12947 // Note: If this code changes, the corresponding ret_addr_offset() and
12948 // compute_padding() functions will have to be adjusted.
12949 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12950 match(CallStaticJava);
12951 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12952 effect(USE meth);
12953 // EBP is saved by all callees (for interpreter stack correction).
12954 // We use it here for a similar purpose, in {preserve,restore}_SP.
12955
12956 ins_cost(300);
12957 format %{ "CALL,static/MethodHandle " %}
12958 opcode(0xE8); /* E8 cd */
12959 ins_encode( pre_call_resets,
12960 preserve_SP,
12961 Java_Static_Call( meth ),
12962 restore_SP,
12963 call_epilog,
12964 post_call_FPU );
12965 ins_pipe( pipe_slow );
12966 ins_alignment(4);
12967 %}
12968
12969 // Call Java Dynamic Instruction
12970 // Note: If this code changes, the corresponding ret_addr_offset() and
12971 // compute_padding() functions will have to be adjusted.
12972 instruct CallDynamicJavaDirect(method meth) %{
12973 match(CallDynamicJava);
12974 effect(USE meth);
12975
12976 ins_cost(300);
12977 format %{ "MOV EAX,(oop)-1\n\t"
12978 "CALL,dynamic" %}
12979 opcode(0xE8); /* E8 cd */
12980 ins_encode( pre_call_resets,
12981 Java_Dynamic_Call( meth ),
12982 call_epilog,
12983 post_call_FPU );
12984 ins_pipe( pipe_slow );
12985 ins_alignment(4);
12986 %}
12987
12988 // Call Runtime Instruction
12989 instruct CallRuntimeDirect(method meth) %{
12990 match(CallRuntime );
12991 effect(USE meth);
12992
12993 ins_cost(300);
12994 format %{ "CALL,runtime " %}
12995 opcode(0xE8); /* E8 cd */
12996 // Use FFREEs to clear entries in float stack
12997 ins_encode( pre_call_resets,
12998 FFree_Float_Stack_All,
12999 Java_To_Runtime( meth ),
13000 post_call_FPU );
13001 ins_pipe( pipe_slow );
13002 %}
13003
13004 // Call runtime without safepoint
13005 instruct CallLeafDirect(method meth) %{
13006 match(CallLeaf);
13007 effect(USE meth);
13008
13009 ins_cost(300);
13010 format %{ "CALL_LEAF,runtime " %}
13011 opcode(0xE8); /* E8 cd */
13012 ins_encode( pre_call_resets,
13013 FFree_Float_Stack_All,
13014 Java_To_Runtime( meth ),
13015 Verify_FPU_For_Leaf, post_call_FPU );
13016 ins_pipe( pipe_slow );
13017 %}
13018
13019 instruct CallLeafNoFPDirect(method meth) %{
13020 match(CallLeafNoFP);
13021 effect(USE meth);
13022
13023 ins_cost(300);
13024 format %{ "CALL_LEAF_NOFP,runtime " %}
13025 opcode(0xE8); /* E8 cd */
13026 ins_encode(Java_To_Runtime(meth));
13027 ins_pipe( pipe_slow );
13028 %}
13029
13030
13031 // Return Instruction
13032 // Remove the return address & jump to it.
13033 instruct Ret() %{
13034 match(Return);
13035 format %{ "RET" %}
13036 opcode(0xC3);
13037 ins_encode(OpcP);
13038 ins_pipe( pipe_jmp );
13039 %}
13040
13041 // Tail Call; Jump from runtime stub to Java code.
13042 // Also known as an 'interprocedural jump'.
13043 // Target of jump will eventually return to caller.
13044 // TailJump below removes the return address.
13045 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13046 match(TailCall jump_target method_oop );
13047 ins_cost(300);
13048 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13049 opcode(0xFF, 0x4); /* Opcode FF /4 */
13050 ins_encode( OpcP, RegOpc(jump_target) );
13051 ins_pipe( pipe_jmp );
13052 %}
13053
13054
13055 // Tail Jump; remove the return address; jump to target.
13056 // TailCall above leaves the return address around.
13057 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13058 match( TailJump jump_target ex_oop );
13059 ins_cost(300);
13060 format %{ "POP EDX\t# pop return address into dummy\n\t"
13061 "JMP $jump_target " %}
13062 opcode(0xFF, 0x4); /* Opcode FF /4 */
13063 ins_encode( enc_pop_rdx,
13064 OpcP, RegOpc(jump_target) );
13065 ins_pipe( pipe_jmp );
13066 %}
13067
13068 // Create exception oop: created by stack-crawling runtime code.
13069 // Created exception is now available to this handler, and is setup
13070 // just prior to jumping to this handler. No code emitted.
13071 instruct CreateException( eAXRegP ex_oop )
13072 %{
13073 match(Set ex_oop (CreateEx));
13074
13075 size(0);
13076 // use the following format syntax
13077 format %{ "# exception oop is in EAX; no code emitted" %}
13078 ins_encode();
13079 ins_pipe( empty );
13080 %}
13081
13082
13083 // Rethrow exception:
13084 // The exception oop will come in the first argument position.
13085 // Then JUMP (not call) to the rethrow stub code.
13086 instruct RethrowException()
13087 %{
13088 match(Rethrow);
13089
13090 // use the following format syntax
13091 format %{ "JMP rethrow_stub" %}
13092 ins_encode(enc_rethrow);
13093 ins_pipe( pipe_jmp );
13094 %}
13095
13096 // inlined locking and unlocking
13097
13098
13099 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13100 match( Set cr (FastLock object box) );
13101 effect( TEMP tmp, TEMP scr, USE_KILL box );
13102 ins_cost(300);
13103 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13104 ins_encode( Fast_Lock(object,box,tmp,scr) );
13105 ins_pipe( pipe_slow );
13106 %}
13107
13108 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13109 match( Set cr (FastUnlock object box) );
13110 effect( TEMP tmp, USE_KILL box );
13111 ins_cost(300);
13112 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13113 ins_encode( Fast_Unlock(object,box,tmp) );
13114 ins_pipe( pipe_slow );
13115 %}
13116
13117
13118
13119 // ============================================================================
13120 // Safepoint Instruction
13121 instruct safePoint_poll(eFlagsReg cr) %{
13122 match(SafePoint);
13123 effect(KILL cr);
13124
13125 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13126 // On SPARC that might be acceptable as we can generate the address with
13127 // just a sethi, saving an or. By polling at offset 0 we can end up
13128 // putting additional pressure on the index-0 in the D$. Because of
13129 // alignment (just like the situation at hand) the lower indices tend
13130 // to see more traffic. It'd be better to change the polling address
13131 // to offset 0 of the last $line in the polling page.
13132
13133 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13134 ins_cost(125);
13135 size(6) ;
13136 ins_encode( Safepoint_Poll() );
13137 ins_pipe( ialu_reg_mem );
13138 %}
13139
13140
13141 // ============================================================================
13142 // This name is KNOWN by the ADLC and cannot be changed.
13143 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13144 // for this guy.
13145 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13146 match(Set dst (ThreadLocal));
13147 effect(DEF dst, KILL cr);
13148
13149 format %{ "MOV $dst, Thread::current()" %}
13150 ins_encode %{
13151 Register dstReg = as_Register($dst$$reg);
13152 __ get_thread(dstReg);
13153 %}
13154 ins_pipe( ialu_reg_fat );
13155 %}
13156
13157
13158
13159 //----------PEEPHOLE RULES-----------------------------------------------------
13160 // These must follow all instruction definitions as they use the names
13161 // defined in the instructions definitions.
13162 //
13163 // peepmatch ( root_instr_name [preceding_instruction]* );
13164 //
13165 // peepconstraint %{
13166 // (instruction_number.operand_name relational_op instruction_number.operand_name
13167 // [, ...] );
13168 // // instruction numbers are zero-based using left to right order in peepmatch
13169 //
13170 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13171 // // provide an instruction_number.operand_name for each operand that appears
13172 // // in the replacement instruction's match rule
13173 //
13174 // ---------VM FLAGS---------------------------------------------------------
13175 //
13176 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13177 //
13178 // Each peephole rule is given an identifying number starting with zero and
13179 // increasing by one in the order seen by the parser. An individual peephole
13180 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13181 // on the command-line.
13182 //
13183 // ---------CURRENT LIMITATIONS----------------------------------------------
13184 //
13185 // Only match adjacent instructions in same basic block
13186 // Only equality constraints
13187 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13188 // Only one replacement instruction
13189 //
13190 // ---------EXAMPLE----------------------------------------------------------
13191 //
13192 // // pertinent parts of existing instructions in architecture description
13193 // instruct movI(rRegI dst, rRegI src) %{
13194 // match(Set dst (CopyI src));
13195 // %}
13196 //
13197 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13198 // match(Set dst (AddI dst src));
13199 // effect(KILL cr);
13200 // %}
13201 //
13202 // // Change (inc mov) to lea
13203 // peephole %{
13204 // // increment preceeded by register-register move
13205 // peepmatch ( incI_eReg movI );
13206 // // require that the destination register of the increment
13207 // // match the destination register of the move
13208 // peepconstraint ( 0.dst == 1.dst );
13209 // // construct a replacement instruction that sets
13210 // // the destination to ( move's source register + one )
13211 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13212 // %}
13213 //
13214 // Implementation no longer uses movX instructions since
13215 // machine-independent system no longer uses CopyX nodes.
13216 //
13217 // peephole %{
13218 // peepmatch ( incI_eReg movI );
13219 // peepconstraint ( 0.dst == 1.dst );
13220 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13221 // %}
13222 //
13223 // peephole %{
13224 // peepmatch ( decI_eReg movI );
13225 // peepconstraint ( 0.dst == 1.dst );
13226 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13227 // %}
13228 //
13229 // peephole %{
13230 // peepmatch ( addI_eReg_imm movI );
13231 // peepconstraint ( 0.dst == 1.dst );
13232 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13233 // %}
13234 //
13235 // peephole %{
13236 // peepmatch ( addP_eReg_imm movP );
13237 // peepconstraint ( 0.dst == 1.dst );
13238 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13239 // %}
13240
13241 // // Change load of spilled value to only a spill
13242 // instruct storeI(memory mem, rRegI src) %{
13243 // match(Set mem (StoreI mem src));
13244 // %}
13245 //
13246 // instruct loadI(rRegI dst, memory mem) %{
13247 // match(Set dst (LoadI mem));
13248 // %}
13249 //
13250 peephole %{
13251 peepmatch ( loadI storeI );
13252 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13253 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13254 %}
13255
13256 //----------SMARTSPILL RULES---------------------------------------------------
13257 // These must follow all instruction definitions as they use the names
13258 // defined in the instructions definitions.