1632
1633 // Register for MODI projection of divmodI
1634 RegMask Matcher::modI_proj_mask() {
1635 return INT_RDX_REG_mask();
1636 }
1637
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1642
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1651
1652 const RegMask Matcher::mathExactI_result_proj_mask() {
1653 return INT_RAX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::mathExactL_result_proj_mask() {
1657 return LONG_RAX_REG_mask();
1658 }
1659
1660 const RegMask Matcher::mathExactI_flags_proj_mask() {
1661 return INT_FLAGS_mask();
1662 }
1663
1664 %}
1665
1666 //----------ENCODING BLOCK-----------------------------------------------------
1667 // This block specifies the encoding classes used by the compiler to
1668 // output byte streams. Encoding classes are parameterized macros
1669 // used by Machine Instruction Nodes in order to generate the bit
1670 // encoding of the instruction. Operands specify their base encoding
1671 // interface with the interface keyword. There are currently
1672 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1673 // COND_INTER. REG_INTER causes an operand to generate a function
1674 // which returns its register number when queried. CONST_INTER causes
1675 // an operand to generate a function which returns the value of the
1676 // constant when queried. MEMORY_INTER causes an operand to generate
1677 // four functions which return the Base Register, the Index Register,
1678 // the Scale Value, and the Offset Value of the operand when queried.
1679 // COND_INTER causes an operand to generate six functions which return
1680 // the encoding code (ie - encoding bits for the instruction)
1681 // associated with each basic boolean condition for a conditional
1682 // instruction.
1683 //
6936 Label Lskip;
6937 // Invert sense of branch from sense of CMOV
6938 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6939 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6940 __ bind(Lskip);
6941 %}
6942 ins_pipe(pipe_slow);
6943 %}
6944
6945 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6946 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6947 ins_cost(200);
6948 expand %{
6949 cmovD_regU(cop, cr, dst, src);
6950 %}
6951 %}
6952
6953 //----------Arithmetic Instructions--------------------------------------------
6954 //----------Addition Instructions----------------------------------------------
6955
6956 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
6957 %{
6958 match(AddExactI dst src);
6959 effect(DEF cr);
6960
6961 format %{ "addl $dst, $src\t# addExact int" %}
6962 ins_encode %{
6963 __ addl($dst$$Register, $src$$Register);
6964 %}
6965 ins_pipe(ialu_reg_reg);
6966 %}
6967
6968 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6969 %{
6970 match(AddExactI dst src);
6971 effect(DEF cr);
6972
6973 format %{ "addl $dst, $src\t# addExact int" %}
6974 ins_encode %{
6975 __ addl($dst$$Register, $src$$constant);
6976 %}
6977 ins_pipe(ialu_reg_reg);
6978 %}
6979
6980 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6981 %{
6982 match(AddExactI dst (LoadI src));
6983 effect(DEF cr);
6984
6985 ins_cost(125); // XXX
6986 format %{ "addl $dst, $src\t# addExact int" %}
6987 ins_encode %{
6988 __ addl($dst$$Register, $src$$Address);
6989 %}
6990
6991 ins_pipe(ialu_reg_mem);
6992 %}
6993
6994 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
6995 %{
6996 match(AddExactL dst src);
6997 effect(DEF cr);
6998
6999 format %{ "addq $dst, $src\t# addExact long" %}
7000 ins_encode %{
7001 __ addq($dst$$Register, $src$$Register);
7002 %}
7003 ins_pipe(ialu_reg_reg);
7004 %}
7005
7006 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7007 %{
7008 match(AddExactL dst src);
7009 effect(DEF cr);
7010
7011 format %{ "addq $dst, $src\t# addExact long" %}
7012 ins_encode %{
7013 __ addq($dst$$Register, $src$$constant);
7014 %}
7015 ins_pipe(ialu_reg_reg);
7016 %}
7017
7018 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7019 %{
7020 match(AddExactL dst (LoadL src));
7021 effect(DEF cr);
7022
7023 ins_cost(125); // XXX
7024 format %{ "addq $dst, $src\t# addExact long" %}
7025 ins_encode %{
7026 __ addq($dst$$Register, $src$$Address);
7027 %}
7028
7029 ins_pipe(ialu_reg_mem);
7030 %}
7031
7032 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7033 %{
7034 match(Set dst (AddI dst src));
7035 effect(KILL cr);
7036
7037 format %{ "addl $dst, $src\t# int" %}
7038 opcode(0x03);
7039 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7040 ins_pipe(ialu_reg_reg);
7041 %}
7042
7043 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7044 %{
7045 match(Set dst (AddI dst src));
7046 effect(KILL cr);
7047
7048 format %{ "addl $dst, $src\t# int" %}
7049 opcode(0x81, 0x00); /* /0 id */
7050 ins_encode(OpcSErm(dst, src), Con8or32(src));
7051 ins_pipe( ialu_reg );
7624
7625 ins_cost(150);
7626 format %{ "subl $dst, $src\t# int" %}
7627 opcode(0x29); /* Opcode 29 /r */
7628 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7629 ins_pipe(ialu_mem_reg);
7630 %}
7631
7632 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7633 %{
7634 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7635 effect(KILL cr);
7636
7637 ins_cost(125); // XXX
7638 format %{ "subl $dst, $src\t# int" %}
7639 opcode(0x81); /* Opcode 81 /5 id */
7640 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7641 ins_pipe(ialu_mem_imm);
7642 %}
7643
7644 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7645 %{
7646 match(SubExactI dst src);
7647 effect(DEF cr);
7648
7649 format %{ "subl $dst, $src\t# subExact int" %}
7650 ins_encode %{
7651 __ subl($dst$$Register, $src$$Register);
7652 %}
7653 ins_pipe(ialu_reg_reg);
7654 %}
7655
7656 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7657 %{
7658 match(SubExactI dst src);
7659 effect(DEF cr);
7660
7661 format %{ "subl $dst, $src\t# subExact int" %}
7662 ins_encode %{
7663 __ subl($dst$$Register, $src$$constant);
7664 %}
7665 ins_pipe(ialu_reg_reg);
7666 %}
7667
7668 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7669 %{
7670 match(SubExactI dst (LoadI src));
7671 effect(DEF cr);
7672
7673 ins_cost(125);
7674 format %{ "subl $dst, $src\t# subExact int" %}
7675 ins_encode %{
7676 __ subl($dst$$Register, $src$$Address);
7677 %}
7678 ins_pipe(ialu_reg_mem);
7679 %}
7680
7681 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7682 %{
7683 match(SubExactL dst src);
7684 effect(DEF cr);
7685
7686 format %{ "subq $dst, $src\t# subExact long" %}
7687 ins_encode %{
7688 __ subq($dst$$Register, $src$$Register);
7689 %}
7690 ins_pipe(ialu_reg_reg);
7691 %}
7692
7693 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7694 %{
7695 match(SubExactL dst (LoadL src));
7696 effect(DEF cr);
7697
7698 format %{ "subq $dst, $src\t# subExact long" %}
7699 ins_encode %{
7700 __ subq($dst$$Register, $src$$constant);
7701 %}
7702 ins_pipe(ialu_reg_reg);
7703 %}
7704
7705 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7706 %{
7707 match(SubExactI dst src);
7708 effect(DEF cr);
7709
7710 ins_cost(125);
7711 format %{ "subq $dst, $src\t# subExact long" %}
7712 ins_encode %{
7713 __ subq($dst$$Register, $src$$Address);
7714 %}
7715 ins_pipe(ialu_reg_mem);
7716 %}
7717
7718 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7719 %{
7720 match(Set dst (SubL dst src));
7721 effect(KILL cr);
7722
7723 format %{ "subq $dst, $src\t# long" %}
7724 opcode(0x2B);
7725 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7726 ins_pipe(ialu_reg_reg);
7727 %}
7728
7729 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7730 %{
7731 match(Set dst (SubL dst src));
7732 effect(KILL cr);
7733
7734 format %{ "subq $dst, $src\t# long" %}
7735 opcode(0x81, 0x05); /* Opcode 81 /5 */
7736 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7737 ins_pipe(ialu_reg);
7814 match(Set dst (SubL zero dst));
7815 effect(KILL cr);
7816
7817 format %{ "negq $dst\t# long" %}
7818 opcode(0xF7, 0x03); // Opcode F7 /3
7819 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7820 ins_pipe(ialu_reg);
7821 %}
7822
7823 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7824 %{
7825 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7826 effect(KILL cr);
7827
7828 format %{ "negq $dst\t# long" %}
7829 opcode(0xF7, 0x03); // Opcode F7 /3
7830 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7831 ins_pipe(ialu_reg);
7832 %}
7833
7834 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7835 %{
7836 match(NegExactI dst);
7837 effect(KILL cr);
7838
7839 format %{ "negl $dst\t# negExact int" %}
7840 ins_encode %{
7841 __ negl($dst$$Register);
7842 %}
7843 ins_pipe(ialu_reg);
7844 %}
7845
7846 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7847 %{
7848 match(NegExactL dst);
7849 effect(KILL cr);
7850
7851 format %{ "negq $dst\t# negExact long" %}
7852 ins_encode %{
7853 __ negq($dst$$Register);
7854 %}
7855 ins_pipe(ialu_reg);
7856 %}
7857
7858
7859 //----------Multiplication/Division Instructions-------------------------------
7860 // Integer Multiplication Instructions
7861 // Multiply Register
7862
7863 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7864 %{
7865 match(Set dst (MulI dst src));
7866 effect(KILL cr);
7867
7868 ins_cost(300);
7869 format %{ "imull $dst, $src\t# int" %}
7870 opcode(0x0F, 0xAF);
7871 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7872 ins_pipe(ialu_reg_reg_alu0);
7873 %}
7874
7875 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7876 %{
7877 match(Set dst (MulI src imm));
7878 effect(KILL cr);
7955 ins_cost(300);
7956 format %{ "imulq $dst, $src, $imm\t# long" %}
7957 opcode(0x69); /* 69 /r id */
7958 ins_encode(REX_reg_mem_wide(dst, src),
7959 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7960 ins_pipe(ialu_reg_mem_alu0);
7961 %}
7962
7963 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7964 %{
7965 match(Set dst (MulHiL src rax));
7966 effect(USE_KILL rax, KILL cr);
7967
7968 ins_cost(300);
7969 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7970 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7971 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7972 ins_pipe(ialu_reg_reg_alu0);
7973 %}
7974
7975
7976 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7977 %{
7978 match(MulExactI dst src);
7979 effect(DEF cr);
7980
7981 ins_cost(300);
7982 format %{ "imull $dst, $src\t# mulExact int" %}
7983 ins_encode %{
7984 __ imull($dst$$Register, $src$$Register);
7985 %}
7986 ins_pipe(ialu_reg_reg_alu0);
7987 %}
7988
7989
7990 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
7991 %{
7992 match(MulExactI src imm);
7993 effect(DEF cr);
7994
7995 ins_cost(300);
7996 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
7997 ins_encode %{
7998 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7999 %}
8000 ins_pipe(ialu_reg_reg_alu0);
8001 %}
8002
8003 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
8004 %{
8005 match(MulExactI dst (LoadI src));
8006 effect(DEF cr);
8007
8008 ins_cost(350);
8009 format %{ "imull $dst, $src\t# mulExact int" %}
8010 ins_encode %{
8011 __ imull($dst$$Register, $src$$Address);
8012 %}
8013 ins_pipe(ialu_reg_mem_alu0);
8014 %}
8015
8016 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
8017 %{
8018 match(MulExactL dst src);
8019 effect(DEF cr);
8020
8021 ins_cost(300);
8022 format %{ "imulq $dst, $src\t# mulExact long" %}
8023 ins_encode %{
8024 __ imulq($dst$$Register, $src$$Register);
8025 %}
8026 ins_pipe(ialu_reg_reg_alu0);
8027 %}
8028
8029 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8030 %{
8031 match(MulExactL src imm);
8032 effect(DEF cr);
8033
8034 ins_cost(300);
8035 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
8036 ins_encode %{
8037 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8038 %}
8039 ins_pipe(ialu_reg_reg_alu0);
8040 %}
8041
8042 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
8043 %{
8044 match(MulExactL dst (LoadL src));
8045 effect(DEF cr);
8046
8047 ins_cost(350);
8048 format %{ "imulq $dst, $src\t# mulExact long" %}
8049 ins_encode %{
8050 __ imulq($dst$$Register, $src$$Address);
8051 %}
8052 ins_pipe(ialu_reg_mem_alu0);
8053 %}
8054
8055 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8056 rFlagsReg cr)
8057 %{
8058 match(Set rax (DivI rax div));
8059 effect(KILL rdx, KILL cr);
8060
8061 ins_cost(30*100+10*100); // XXX
8062 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8063 "jne,s normal\n\t"
8064 "xorl rdx, rdx\n\t"
8065 "cmpl $div, -1\n\t"
8066 "je,s done\n"
8067 "normal: cdql\n\t"
8068 "idivl $div\n"
8069 "done:" %}
8070 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8071 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8072 ins_pipe(ialu_reg_reg_alu0);
8073 %}
8074
10641 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10642 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10643 %}
10644 ins_pipe( pipe_slow );
10645 %}
10646
10647 // encode char[] to byte[] in ISO_8859_1
10648 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10649 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10650 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10651 match(Set result (EncodeISOArray src (Binary dst len)));
10652 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10653
10654 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10655 ins_encode %{
10656 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10657 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10658 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10659 %}
10660 ins_pipe( pipe_slow );
10661 %}
10662
10663
10664 //----------Control Flow Instructions------------------------------------------
10665 // Signed compare Instructions
10666
10667 // XXX more variants!!
10668 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10669 %{
10670 match(Set cr (CmpI op1 op2));
10671 effect(DEF cr, USE op1, USE op2);
10672
10673 format %{ "cmpl $op1, $op2" %}
10674 opcode(0x3B); /* Opcode 3B /r */
10675 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10676 ins_pipe(ialu_cr_reg_reg);
10677 %}
10678
10679 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10680 %{
|
1632
1633 // Register for MODI projection of divmodI
1634 RegMask Matcher::modI_proj_mask() {
1635 return INT_RDX_REG_mask();
1636 }
1637
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1642
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1651
1652 %}
1653
1654 //----------ENCODING BLOCK-----------------------------------------------------
1655 // This block specifies the encoding classes used by the compiler to
1656 // output byte streams. Encoding classes are parameterized macros
1657 // used by Machine Instruction Nodes in order to generate the bit
1658 // encoding of the instruction. Operands specify their base encoding
1659 // interface with the interface keyword. There are currently
1660 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1661 // COND_INTER. REG_INTER causes an operand to generate a function
1662 // which returns its register number when queried. CONST_INTER causes
1663 // an operand to generate a function which returns the value of the
1664 // constant when queried. MEMORY_INTER causes an operand to generate
1665 // four functions which return the Base Register, the Index Register,
1666 // the Scale Value, and the Offset Value of the operand when queried.
1667 // COND_INTER causes an operand to generate six functions which return
1668 // the encoding code (ie - encoding bits for the instruction)
1669 // associated with each basic boolean condition for a conditional
1670 // instruction.
1671 //
6924 Label Lskip;
6925 // Invert sense of branch from sense of CMOV
6926 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6927 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6928 __ bind(Lskip);
6929 %}
6930 ins_pipe(pipe_slow);
6931 %}
6932
6933 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6934 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6935 ins_cost(200);
6936 expand %{
6937 cmovD_regU(cop, cr, dst, src);
6938 %}
6939 %}
6940
6941 //----------Arithmetic Instructions--------------------------------------------
6942 //----------Addition Instructions----------------------------------------------
6943
6944 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6945 %{
6946 match(Set dst (AddI dst src));
6947 effect(KILL cr);
6948
6949 format %{ "addl $dst, $src\t# int" %}
6950 opcode(0x03);
6951 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6952 ins_pipe(ialu_reg_reg);
6953 %}
6954
6955 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6956 %{
6957 match(Set dst (AddI dst src));
6958 effect(KILL cr);
6959
6960 format %{ "addl $dst, $src\t# int" %}
6961 opcode(0x81, 0x00); /* /0 id */
6962 ins_encode(OpcSErm(dst, src), Con8or32(src));
6963 ins_pipe( ialu_reg );
7536
7537 ins_cost(150);
7538 format %{ "subl $dst, $src\t# int" %}
7539 opcode(0x29); /* Opcode 29 /r */
7540 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7541 ins_pipe(ialu_mem_reg);
7542 %}
7543
7544 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7545 %{
7546 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7547 effect(KILL cr);
7548
7549 ins_cost(125); // XXX
7550 format %{ "subl $dst, $src\t# int" %}
7551 opcode(0x81); /* Opcode 81 /5 id */
7552 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7553 ins_pipe(ialu_mem_imm);
7554 %}
7555
7556 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7557 %{
7558 match(Set dst (SubL dst src));
7559 effect(KILL cr);
7560
7561 format %{ "subq $dst, $src\t# long" %}
7562 opcode(0x2B);
7563 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7564 ins_pipe(ialu_reg_reg);
7565 %}
7566
7567 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7568 %{
7569 match(Set dst (SubL dst src));
7570 effect(KILL cr);
7571
7572 format %{ "subq $dst, $src\t# long" %}
7573 opcode(0x81, 0x05); /* Opcode 81 /5 */
7574 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7575 ins_pipe(ialu_reg);
7652 match(Set dst (SubL zero dst));
7653 effect(KILL cr);
7654
7655 format %{ "negq $dst\t# long" %}
7656 opcode(0xF7, 0x03); // Opcode F7 /3
7657 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7658 ins_pipe(ialu_reg);
7659 %}
7660
7661 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7662 %{
7663 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7664 effect(KILL cr);
7665
7666 format %{ "negq $dst\t# long" %}
7667 opcode(0xF7, 0x03); // Opcode F7 /3
7668 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7669 ins_pipe(ialu_reg);
7670 %}
7671
7672 //----------Multiplication/Division Instructions-------------------------------
7673 // Integer Multiplication Instructions
7674 // Multiply Register
7675
7676 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7677 %{
7678 match(Set dst (MulI dst src));
7679 effect(KILL cr);
7680
7681 ins_cost(300);
7682 format %{ "imull $dst, $src\t# int" %}
7683 opcode(0x0F, 0xAF);
7684 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7685 ins_pipe(ialu_reg_reg_alu0);
7686 %}
7687
7688 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7689 %{
7690 match(Set dst (MulI src imm));
7691 effect(KILL cr);
7768 ins_cost(300);
7769 format %{ "imulq $dst, $src, $imm\t# long" %}
7770 opcode(0x69); /* 69 /r id */
7771 ins_encode(REX_reg_mem_wide(dst, src),
7772 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7773 ins_pipe(ialu_reg_mem_alu0);
7774 %}
7775
7776 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7777 %{
7778 match(Set dst (MulHiL src rax));
7779 effect(USE_KILL rax, KILL cr);
7780
7781 ins_cost(300);
7782 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7783 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7784 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7785 ins_pipe(ialu_reg_reg_alu0);
7786 %}
7787
7788 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7789 rFlagsReg cr)
7790 %{
7791 match(Set rax (DivI rax div));
7792 effect(KILL rdx, KILL cr);
7793
7794 ins_cost(30*100+10*100); // XXX
7795 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7796 "jne,s normal\n\t"
7797 "xorl rdx, rdx\n\t"
7798 "cmpl $div, -1\n\t"
7799 "je,s done\n"
7800 "normal: cdql\n\t"
7801 "idivl $div\n"
7802 "done:" %}
7803 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7804 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7805 ins_pipe(ialu_reg_reg_alu0);
7806 %}
7807
10374 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10375 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10376 %}
10377 ins_pipe( pipe_slow );
10378 %}
10379
10380 // encode char[] to byte[] in ISO_8859_1
10381 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10382 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10383 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10384 match(Set result (EncodeISOArray src (Binary dst len)));
10385 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10386
10387 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10388 ins_encode %{
10389 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10390 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10391 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10392 %}
10393 ins_pipe( pipe_slow );
10394 %}
10395
10396 //----------Overflow Math Instructions-----------------------------------------
10397
10398 instruct addofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10399 %{
10400 match(Set cr (OverflowAddI op1 op2));
10401 effect(DEF cr, USE_KILL op1, USE op2);
10402
10403 format %{ "addl $op1, $op2 #overflow check int" %}
10404
10405 ins_encode %{
10406 __ addl($op1$$Register, $op2$$Register);
10407 %}
10408 ins_pipe(ialu_reg_reg);
10409 %}
10410
10411 instruct addofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10412 %{
10413 match(Set cr (OverflowAddI op1 op2));
10414 effect(DEF cr, USE_KILL op1, USE op2);
10415
10416 format %{ "addl $op1, $op2 #overflow check int" %}
10417
10418 ins_encode %{
10419 __ addl($op1$$Register, $op2$$constant);
10420 %}
10421 ins_pipe(ialu_reg_reg);
10422 %}
10423
10424 instruct addofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10425 %{
10426 match(Set cr (OverflowAddL op1 op2));
10427 effect(DEF cr, USE_KILL op1, USE op2);
10428
10429 format %{ "addq $op1, $op2 #overflow check long" %}
10430 ins_encode %{
10431 __ addq($op1$$Register, $op2$$Register);
10432 %}
10433 ins_pipe(ialu_reg_reg);
10434 %}
10435
10436 instruct addofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10437 %{
10438 match(Set cr (OverflowAddL op1 op2));
10439 effect(DEF cr, USE_KILL op1, USE op2);
10440 ins_encode %{
10441 __ addq($op1$$Register, $op2$$constant);
10442 %}
10443 ins_pipe(ialu_reg_reg);
10444 %}
10445
10446 instruct subofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10447 %{
10448 match(Set cr (OverflowSubI op1 op2));
10449 effect(DEF cr, USE_KILL op1, USE op2);
10450
10451 format %{ "subl $op1, $op2 #overflow check int" %}
10452 ins_encode %{
10453 __ subl($op1$$Register, $op2$$Register);
10454 %}
10455 ins_pipe(ialu_reg_reg);
10456 %}
10457
10458 instruct subofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10459 %{
10460 match(Set cr (OverflowSubI op1 op2));
10461 effect(DEF cr, USE_KILL op1, USE op2);
10462
10463 format %{ "subl $op1, $op2 #overflow check int" %}
10464 ins_encode %{
10465 __ subl($op1$$Register, $op2$$constant);
10466 %}
10467 ins_pipe(ialu_reg_reg);
10468 %}
10469
10470 instruct subofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10471 %{
10472 match(Set cr (OverflowSubL op1 op2));
10473 effect(DEF cr, USE_KILL op1, USE op2);
10474
10475 format %{ "subq $op1, $op2 #overflow check long" %}
10476 ins_encode %{
10477 __ subq($op1$$Register, $op2$$Register);
10478 %}
10479 ins_pipe(ialu_reg_reg);
10480 %}
10481
10482 instruct subofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10483 %{
10484 match(Set cr (OverflowSubL op1 op2));
10485 effect(DEF cr, USE_KILL op1, USE op2);
10486
10487 format %{ "subq $op1, $op2 #overflow check long" %}
10488 ins_encode %{
10489 __ subq($op1$$Register, $op2$$constant);
10490 %}
10491 ins_pipe(ialu_reg_reg);
10492 %}
10493
10494 instruct negofI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10495 %{
10496 match(Set cr (OverflowSubI zero op2));
10497 effect(DEF cr, USE_KILL op2);
10498
10499 format %{ "negl $op2 #overflow check int" %}
10500 ins_encode %{
10501 __ negl($op2$$Register);
10502 %}
10503 ins_pipe(ialu_reg_reg);
10504 %}
10505
10506 instruct negofL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10507 %{
10508 match(Set cr (OverflowSubL zero op2));
10509 effect(DEF cr, USE_KILL op2);
10510
10511 format %{ "negq $op2 #overflow check long" %}
10512 ins_encode %{
10513 __ negq($op2$$Register);
10514 %}
10515 ins_pipe(ialu_reg_reg);
10516 %}
10517
10518 instruct mulofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10519 %{
10520 match(Set cr (OverflowMulI op1 op2));
10521 effect(DEF cr, USE_KILL op1, USE op2);
10522
10523 format %{ "imull $op1, $op2 #overflow check int" %}
10524 ins_encode %{
10525 __ imull($op1$$Register, $op2$$Register);
10526 %}
10527 ins_pipe(ialu_reg_reg);
10528 %}
10529
10530 instruct mulofI_rReg_imm(rFlagsReg cr, rax_RegI op1, rRegI op2, immI op3)
10531 %{
10532 match(Set cr (OverflowMulI op2 op3));
10533 effect(DEF cr, KILL op1, USE op2, USE op3);
10534
10535 format %{ "imull $op1, $op2 #overflow check int" %}
10536 ins_encode %{
10537 __ imull($op1$$Register, $op2$$Register, $op3$$constant);
10538 %}
10539 ins_pipe(ialu_reg_reg);
10540 %}
10541
10542 instruct mulofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10543 %{
10544 match(Set cr (OverflowMulL op1 op2));
10545 effect(DEF cr, USE_KILL op1, USE op2);
10546
10547 format %{ "imulq $op1, $op2 #overflow check long" %}
10548 ins_encode %{
10549 __ imulq($op1$$Register, $op2$$Register);
10550 %}
10551 ins_pipe(ialu_reg_reg);
10552 %}
10553
10554
10555 //----------Control Flow Instructions------------------------------------------
10556 // Signed compare Instructions
10557
10558 // XXX more variants!!
10559 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10560 %{
10561 match(Set cr (CmpI op1 op2));
10562 effect(DEF cr, USE op1, USE op2);
10563
10564 format %{ "cmpl $op1, $op2" %}
10565 opcode(0x3B); /* Opcode 3B /r */
10566 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10567 ins_pipe(ialu_cr_reg_reg);
10568 %}
10569
10570 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10571 %{
|