1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #ifdef TARGET_ARCH_MODEL_x86_32
42 # include "adfiles/ad_x86_32.hpp"
43 #endif
44 #ifdef TARGET_ARCH_MODEL_x86_64
45 # include "adfiles/ad_x86_64.hpp"
46 #endif
47 #ifdef TARGET_ARCH_MODEL_sparc
48 # include "adfiles/ad_sparc.hpp"
49 #endif
50 #ifdef TARGET_ARCH_MODEL_zero
51 # include "adfiles/ad_zero.hpp"
52 #endif
53 #ifdef TARGET_ARCH_MODEL_arm
54 # include "adfiles/ad_arm.hpp"
55 #endif
56 #ifdef TARGET_ARCH_MODEL_ppc
57 # include "adfiles/ad_ppc.hpp"
58 #endif
59
60 OptoReg::Name OptoReg::c_frame_pointer;
61
62 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
63 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
64 RegMask Matcher::STACK_ONLY_mask;
65 RegMask Matcher::c_frame_ptr_mask;
66 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
67 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
68
69 //---------------------------Matcher-------------------------------------------
70 Matcher::Matcher()
71 : PhaseTransform( Phase::Ins_Select ),
72 #ifdef ASSERT
73 _old2new_map(C->comp_arena()),
74 _new2old_map(C->comp_arena()),
75 #endif
76 _shared_nodes(C->comp_arena()),
77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
78 _swallowed(swallowed),
79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
80 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
81 _must_clone(must_clone),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type),
85 _ruleName(ruleName),
86 _allocation_started(false),
87 _states_arena(Chunk::medium_size),
88 _visited(&_states_arena),
89 _shared(&_states_arena),
90 _dontcare(&_states_arena) {
91 C->set_matcher(this);
92
93 idealreg2spillmask [Op_RegI] = NULL;
94 idealreg2spillmask [Op_RegN] = NULL;
95 idealreg2spillmask [Op_RegL] = NULL;
96 idealreg2spillmask [Op_RegF] = NULL;
97 idealreg2spillmask [Op_RegD] = NULL;
98 idealreg2spillmask [Op_RegP] = NULL;
99 idealreg2spillmask [Op_VecS] = NULL;
100 idealreg2spillmask [Op_VecD] = NULL;
101 idealreg2spillmask [Op_VecX] = NULL;
102 idealreg2spillmask [Op_VecY] = NULL;
103
104 idealreg2debugmask [Op_RegI] = NULL;
105 idealreg2debugmask [Op_RegN] = NULL;
106 idealreg2debugmask [Op_RegL] = NULL;
107 idealreg2debugmask [Op_RegF] = NULL;
108 idealreg2debugmask [Op_RegD] = NULL;
109 idealreg2debugmask [Op_RegP] = NULL;
110 idealreg2debugmask [Op_VecS] = NULL;
111 idealreg2debugmask [Op_VecD] = NULL;
112 idealreg2debugmask [Op_VecX] = NULL;
113 idealreg2debugmask [Op_VecY] = NULL;
114
115 idealreg2mhdebugmask[Op_RegI] = NULL;
116 idealreg2mhdebugmask[Op_RegN] = NULL;
117 idealreg2mhdebugmask[Op_RegL] = NULL;
118 idealreg2mhdebugmask[Op_RegF] = NULL;
119 idealreg2mhdebugmask[Op_RegD] = NULL;
120 idealreg2mhdebugmask[Op_RegP] = NULL;
121 idealreg2mhdebugmask[Op_VecS] = NULL;
122 idealreg2mhdebugmask[Op_VecD] = NULL;
123 idealreg2mhdebugmask[Op_VecX] = NULL;
124 idealreg2mhdebugmask[Op_VecY] = NULL;
125
126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
127 }
128
129 //------------------------------warp_incoming_stk_arg------------------------
130 // This warps a VMReg into an OptoReg::Name
131 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
132 OptoReg::Name warped;
133 if( reg->is_stack() ) { // Stack slot argument?
134 warped = OptoReg::add(_old_SP, reg->reg2stack() );
135 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
136 if( warped >= _in_arg_limit )
137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
138 if (!RegMask::can_represent_arg(warped)) {
139 // the compiler cannot represent this method's calling sequence
140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
141 return OptoReg::Bad;
142 }
143 return warped;
144 }
145 return OptoReg::as_OptoReg(reg);
146 }
147
148 //---------------------------compute_old_SP------------------------------------
149 OptoReg::Name Compile::compute_old_SP() {
150 int fixed = fixed_slots();
151 int preserve = in_preserve_stack_slots();
152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
153 }
154
155
156
157 #ifdef ASSERT
158 void Matcher::verify_new_nodes_only(Node* xroot) {
159 // Make sure that the new graph only references new nodes
160 ResourceMark rm;
161 Unique_Node_List worklist;
162 VectorSet visited(Thread::current()->resource_area());
163 worklist.push(xroot);
164 while (worklist.size() > 0) {
165 Node* n = worklist.pop();
166 visited <<= n->_idx;
167 assert(C->node_arena()->contains(n), "dead node");
168 for (uint j = 0; j < n->req(); j++) {
169 Node* in = n->in(j);
170 if (in != NULL) {
171 assert(C->node_arena()->contains(in), "dead node");
172 if (!visited.test(in->_idx)) {
173 worklist.push(in);
174 }
175 }
176 }
177 }
178 }
179 #endif
180
181
182 //---------------------------match---------------------------------------------
183 void Matcher::match( ) {
184 if( MaxLabelRootDepth < 100 ) { // Too small?
185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
186 MaxLabelRootDepth = 100;
187 }
188 // One-time initialization of some register masks.
189 init_spill_mask( C->root()->in(1) );
190 _return_addr_mask = return_addr();
191 #ifdef _LP64
192 // Pointers take 2 slots in 64-bit land
193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
194 #endif
195
196 // Map a Java-signature return type into return register-value
197 // machine registers for 0, 1 and 2 returned values.
198 const TypeTuple *range = C->tf()->range();
199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
200 // Get ideal-register return type
201 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
202 // Get machine return register
203 uint sop = C->start()->Opcode();
204 OptoRegPair regs = return_value(ireg, false);
205
206 // And mask for same
207 _return_value_mask = RegMask(regs.first());
208 if( OptoReg::is_valid(regs.second()) )
209 _return_value_mask.Insert(regs.second());
210 }
211
212 // ---------------
213 // Frame Layout
214
215 // Need the method signature to determine the incoming argument types,
216 // because the types determine which registers the incoming arguments are
217 // in, and this affects the matched code.
218 const TypeTuple *domain = C->tf()->domain();
219 uint argcnt = domain->cnt() - TypeFunc::Parms;
220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
224 uint i;
225 for( i = 0; i<argcnt; i++ ) {
226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
227 }
228
229 // Pass array of ideal registers and length to USER code (from the AD file)
230 // that will convert this to an array of register numbers.
231 const StartNode *start = C->start();
232 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
233 #ifdef ASSERT
234 // Sanity check users' calling convention. Real handy while trying to
235 // get the initial port correct.
236 { for (uint i = 0; i<argcnt; i++) {
237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
239 _parm_regs[i].set_bad();
240 continue;
241 }
242 VMReg parm_reg = vm_parm_regs[i].first();
243 assert(parm_reg->is_valid(), "invalid arg?");
244 if (parm_reg->is_reg()) {
245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
246 assert(can_be_java_arg(opto_parm_reg) ||
247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
248 opto_parm_reg == inline_cache_reg(),
249 "parameters in register must be preserved by runtime stubs");
250 }
251 for (uint j = 0; j < i; j++) {
252 assert(parm_reg != vm_parm_regs[j].first(),
253 "calling conv. must produce distinct regs");
254 }
255 }
256 }
257 #endif
258
259 // Do some initial frame layout.
260
261 // Compute the old incoming SP (may be called FP) as
262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
263 _old_SP = C->compute_old_SP();
264 assert( is_even(_old_SP), "must be even" );
265
266 // Compute highest incoming stack argument as
267 // _old_SP + out_preserve_stack_slots + incoming argument size.
268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
269 assert( is_even(_in_arg_limit), "out_preserve must be even" );
270 for( i = 0; i < argcnt; i++ ) {
271 // Permit args to have no register
272 _calling_convention_mask[i].Clear();
273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
274 continue;
275 }
276 // calling_convention returns stack arguments as a count of
277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
278 // the allocators point of view, taking into account all the
279 // preserve area, locks & pad2.
280
281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
282 if( OptoReg::is_valid(reg1))
283 _calling_convention_mask[i].Insert(reg1);
284
285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
286 if( OptoReg::is_valid(reg2))
287 _calling_convention_mask[i].Insert(reg2);
288
289 // Saved biased stack-slot register number
290 _parm_regs[i].set_pair(reg2, reg1);
291 }
292
293 // Finally, make sure the incoming arguments take up an even number of
294 // words, in case the arguments or locals need to contain doubleword stack
295 // slots. The rest of the system assumes that stack slot pairs (in
296 // particular, in the spill area) which look aligned will in fact be
297 // aligned relative to the stack pointer in the target machine. Double
298 // stack slots will always be allocated aligned.
299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
300
301 // Compute highest outgoing stack argument as
302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
304 assert( is_even(_out_arg_limit), "out_preserve must be even" );
305
306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
307 // the compiler cannot represent this method's calling sequence
308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
309 }
310
311 if (C->failing()) return; // bailed out on incoming arg failure
312
313 // ---------------
314 // Collect roots of matcher trees. Every node for which
315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
316 // can be a valid interior of some tree.
317 find_shared( C->root() );
318 find_shared( C->top() );
319
320 C->print_method(PHASE_BEFORE_MATCHING);
321
322 // Create new ideal node ConP #NULL even if it does exist in old space
323 // to avoid false sharing if the corresponding mach node is not used.
324 // The corresponding mach node is only used in rare cases for derived
325 // pointers.
326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
327
328 // Swap out to old-space; emptying new-space
329 Arena *old = C->node_arena()->move_contents(C->old_arena());
330
331 // Save debug and profile information for nodes in old space:
332 _old_node_note_array = C->node_note_array();
333 if (_old_node_note_array != NULL) {
334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
335 (C->comp_arena(), _old_node_note_array->length(),
336 0, NULL));
337 }
338
339 // Pre-size the new_node table to avoid the need for range checks.
340 grow_new_node_array(C->unique());
341
342 // Reset node counter so MachNodes start with _idx at 0
343 int nodes = C->unique(); // save value
344 C->set_unique(0);
345 C->reset_dead_node_list();
346
347 // Recursively match trees from old space into new space.
348 // Correct leaves of new-space Nodes; they point to old-space.
349 _visited.Clear(); // Clear visit bits for xform call
350 C->set_cached_top_node(xform( C->top(), nodes ));
351 if (!C->failing()) {
352 Node* xroot = xform( C->root(), 1 );
353 if (xroot == NULL) {
354 Matcher::soft_match_failure(); // recursive matching process failed
355 C->record_method_not_compilable("instruction match failed");
356 } else {
357 // During matching shared constants were attached to C->root()
358 // because xroot wasn't available yet, so transfer the uses to
359 // the xroot.
360 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
361 Node* n = C->root()->fast_out(j);
362 if (C->node_arena()->contains(n)) {
363 assert(n->in(0) == C->root(), "should be control user");
364 n->set_req(0, xroot);
365 --j;
366 --jmax;
367 }
368 }
369
370 // Generate new mach node for ConP #NULL
371 assert(new_ideal_null != NULL, "sanity");
372 _mach_null = match_tree(new_ideal_null);
373 // Don't set control, it will confuse GCM since there are no uses.
374 // The control will be set when this node is used first time
375 // in find_base_for_derived().
376 assert(_mach_null != NULL, "");
377
378 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
379
380 #ifdef ASSERT
381 verify_new_nodes_only(xroot);
382 #endif
383 }
384 }
385 if (C->top() == NULL || C->root() == NULL) {
386 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
387 }
388 if (C->failing()) {
389 // delete old;
390 old->destruct_contents();
391 return;
392 }
393 assert( C->top(), "" );
394 assert( C->root(), "" );
395 validate_null_checks();
396
397 // Now smoke old-space
398 NOT_DEBUG( old->destruct_contents() );
399
400 // ------------------------
401 // Set up save-on-entry registers
402 Fixup_Save_On_Entry( );
403 }
404
405
406 //------------------------------Fixup_Save_On_Entry----------------------------
407 // The stated purpose of this routine is to take care of save-on-entry
408 // registers. However, the overall goal of the Match phase is to convert into
409 // machine-specific instructions which have RegMasks to guide allocation.
410 // So what this procedure really does is put a valid RegMask on each input
411 // to the machine-specific variations of all Return, TailCall and Halt
412 // instructions. It also adds edgs to define the save-on-entry values (and of
413 // course gives them a mask).
414
415 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
416 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
417 // Do all the pre-defined register masks
418 rms[TypeFunc::Control ] = RegMask::Empty;
419 rms[TypeFunc::I_O ] = RegMask::Empty;
420 rms[TypeFunc::Memory ] = RegMask::Empty;
421 rms[TypeFunc::ReturnAdr] = ret_adr;
422 rms[TypeFunc::FramePtr ] = fp;
423 return rms;
424 }
425
426 //---------------------------init_first_stack_mask-----------------------------
427 // Create the initial stack mask used by values spilling to the stack.
428 // Disallow any debug info in outgoing argument areas by setting the
429 // initial mask accordingly.
430 void Matcher::init_first_stack_mask() {
431
432 // Allocate storage for spill masks as masks for the appropriate load type.
433 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
434
435 idealreg2spillmask [Op_RegN] = &rms[0];
436 idealreg2spillmask [Op_RegI] = &rms[1];
437 idealreg2spillmask [Op_RegL] = &rms[2];
438 idealreg2spillmask [Op_RegF] = &rms[3];
439 idealreg2spillmask [Op_RegD] = &rms[4];
440 idealreg2spillmask [Op_RegP] = &rms[5];
441
442 idealreg2debugmask [Op_RegN] = &rms[6];
443 idealreg2debugmask [Op_RegI] = &rms[7];
444 idealreg2debugmask [Op_RegL] = &rms[8];
445 idealreg2debugmask [Op_RegF] = &rms[9];
446 idealreg2debugmask [Op_RegD] = &rms[10];
447 idealreg2debugmask [Op_RegP] = &rms[11];
448
449 idealreg2mhdebugmask[Op_RegN] = &rms[12];
450 idealreg2mhdebugmask[Op_RegI] = &rms[13];
451 idealreg2mhdebugmask[Op_RegL] = &rms[14];
452 idealreg2mhdebugmask[Op_RegF] = &rms[15];
453 idealreg2mhdebugmask[Op_RegD] = &rms[16];
454 idealreg2mhdebugmask[Op_RegP] = &rms[17];
455
456 idealreg2spillmask [Op_VecS] = &rms[18];
457 idealreg2spillmask [Op_VecD] = &rms[19];
458 idealreg2spillmask [Op_VecX] = &rms[20];
459 idealreg2spillmask [Op_VecY] = &rms[21];
460
461 OptoReg::Name i;
462
463 // At first, start with the empty mask
464 C->FIRST_STACK_mask().Clear();
465
466 // Add in the incoming argument area
467 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
468 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
469 C->FIRST_STACK_mask().Insert(i);
470 }
471 // Add in all bits past the outgoing argument area
472 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
473 "must be able to represent all call arguments in reg mask");
474 OptoReg::Name init = _out_arg_limit;
475 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
476 C->FIRST_STACK_mask().Insert(i);
477 }
478 // Finally, set the "infinite stack" bit.
479 C->FIRST_STACK_mask().set_AllStack();
480
481 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
482 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
483 // Keep spill masks aligned.
484 aligned_stack_mask.clear_to_pairs();
485 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
486
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
488 #ifdef _LP64
489 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
490 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
491 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
492 #else
493 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
494 #endif
495 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
496 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
497 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
498 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
499 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
500 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
501 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
502 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
503
504 if (Matcher::vector_size_supported(T_BYTE,4)) {
505 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
506 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
507 }
508 if (Matcher::vector_size_supported(T_FLOAT,2)) {
509 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
510 // RA guarantees such alignment since it is needed for Double and Long values.
511 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
512 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
513 }
514 if (Matcher::vector_size_supported(T_FLOAT,4)) {
515 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
516 //
517 // RA can use input arguments stack slots for spills but until RA
518 // we don't know frame size and offset of input arg stack slots.
519 //
520 // Exclude last input arg stack slots to avoid spilling vectors there
521 // otherwise vector spills could stomp over stack slots in caller frame.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
530 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,8)) {
533 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
542 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
550 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
551 #ifdef _LP64
552 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
554 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
556 #else
557 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
562 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
571 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
572 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
573 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
574 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
575 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
576
577 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [Op_RegN]->Remove(i);
594 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
596 idealreg2debugmask [Op_RegF]->Remove(i); // masks
597 idealreg2debugmask [Op_RegD]->Remove(i);
598 idealreg2debugmask [Op_RegP]->Remove(i);
599
600 idealreg2mhdebugmask[Op_RegN]->Remove(i);
601 idealreg2mhdebugmask[Op_RegI]->Remove(i);
602 idealreg2mhdebugmask[Op_RegL]->Remove(i);
603 idealreg2mhdebugmask[Op_RegF]->Remove(i);
604 idealreg2mhdebugmask[Op_RegD]->Remove(i);
605 idealreg2mhdebugmask[Op_RegP]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
638 // Find the procedure Start Node
639 StartNode *start = C->start();
640 assert( start, "Expect a start node" );
641
642 // Save argument registers in the trampolining stubs
643 if( C->save_argument_registers() )
644 for( i = 0; i < _last_Mach_Reg; i++ )
645 if( is_spillable_arg(i) )
646 soe_cnt++;
647
648 // Input RegMask array shared by all Returns.
649 // The type for doubles and longs has a count of 2, but
650 // there is only 1 returned value
651 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
652 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
653 // Returns have 0 or 1 returned values depending on call signature.
654 // Return register is specified by return_value in the AD file.
655 if (ret_edge_cnt > TypeFunc::Parms)
656 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
657
658 // Input RegMask array shared by all Rethrows.
659 uint reth_edge_cnt = TypeFunc::Parms+1;
660 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
661 // Rethrow takes exception oop only, but in the argument 0 slot.
662 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
663 #ifdef _LP64
664 // Need two slots for ptrs in 64-bit land
665 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
666 #endif
667
668 // Input RegMask array shared by all TailCalls
669 uint tail_call_edge_cnt = TypeFunc::Parms+2;
670 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
671
672 // Input RegMask array shared by all TailJumps
673 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
674 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
675
676 // TailCalls have 2 returned values (target & moop), whose masks come
677 // from the usual MachNode/MachOper mechanism. Find a sample
678 // TailCall to extract these masks and put the correct masks into
679 // the tail_call_rms array.
680 for( i=1; i < root->req(); i++ ) {
681 MachReturnNode *m = root->in(i)->as_MachReturn();
682 if( m->ideal_Opcode() == Op_TailCall ) {
683 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
684 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
685 break;
686 }
687 }
688
689 // TailJumps have 2 returned values (target & ex_oop), whose masks come
690 // from the usual MachNode/MachOper mechanism. Find a sample
691 // TailJump to extract these masks and put the correct masks into
692 // the tail_jump_rms array.
693 for( i=1; i < root->req(); i++ ) {
694 MachReturnNode *m = root->in(i)->as_MachReturn();
695 if( m->ideal_Opcode() == Op_TailJump ) {
696 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
697 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
698 break;
699 }
700 }
701
702 // Input RegMask array shared by all Halts
703 uint halt_edge_cnt = TypeFunc::Parms;
704 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
705
706 // Capture the return input masks into each exit flavor
707 for( i=1; i < root->req(); i++ ) {
708 MachReturnNode *exit = root->in(i)->as_MachReturn();
709 switch( exit->ideal_Opcode() ) {
710 case Op_Return : exit->_in_rms = ret_rms; break;
711 case Op_Rethrow : exit->_in_rms = reth_rms; break;
712 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
713 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
714 case Op_Halt : exit->_in_rms = halt_rms; break;
715 default : ShouldNotReachHere();
716 }
717 }
718
719 // Next unused projection number from Start.
720 int proj_cnt = C->tf()->domain()->cnt();
721
722 // Do all the save-on-entry registers. Make projections from Start for
723 // them, and give them a use at the exit points. To the allocator, they
724 // look like incoming register arguments.
725 for( i = 0; i < _last_Mach_Reg; i++ ) {
726 if( is_save_on_entry(i) ) {
727
728 // Add the save-on-entry to the mask array
729 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
730 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
731 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
732 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
733 // Halts need the SOE registers, but only in the stack as debug info.
734 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
735 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
736
737 Node *mproj;
738
739 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
740 // into a single RegD.
741 if( (i&1) == 0 &&
742 _register_save_type[i ] == Op_RegF &&
743 _register_save_type[i+1] == Op_RegF &&
744 is_save_on_entry(i+1) ) {
745 // Add other bit for double
746 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
747 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
748 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
749 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
750 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
751 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
752 proj_cnt += 2; // Skip 2 for doubles
753 }
754 else if( (i&1) == 1 && // Else check for high half of double
755 _register_save_type[i-1] == Op_RegF &&
756 _register_save_type[i ] == Op_RegF &&
757 is_save_on_entry(i-1) ) {
758 ret_rms [ ret_edge_cnt] = RegMask::Empty;
759 reth_rms [ reth_edge_cnt] = RegMask::Empty;
760 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
761 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
762 halt_rms [ halt_edge_cnt] = RegMask::Empty;
763 mproj = C->top();
764 }
765 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
766 // into a single RegL.
767 else if( (i&1) == 0 &&
768 _register_save_type[i ] == Op_RegI &&
769 _register_save_type[i+1] == Op_RegI &&
770 is_save_on_entry(i+1) ) {
771 // Add other bit for long
772 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
773 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
774 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
775 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
776 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
777 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
778 proj_cnt += 2; // Skip 2 for longs
779 }
780 else if( (i&1) == 1 && // Else check for high half of long
781 _register_save_type[i-1] == Op_RegI &&
782 _register_save_type[i ] == Op_RegI &&
783 is_save_on_entry(i-1) ) {
784 ret_rms [ ret_edge_cnt] = RegMask::Empty;
785 reth_rms [ reth_edge_cnt] = RegMask::Empty;
786 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
787 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
788 halt_rms [ halt_edge_cnt] = RegMask::Empty;
789 mproj = C->top();
790 } else {
791 // Make a projection for it off the Start
792 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
793 }
794
795 ret_edge_cnt ++;
796 reth_edge_cnt ++;
797 tail_call_edge_cnt ++;
798 tail_jump_edge_cnt ++;
799 halt_edge_cnt ++;
800
801 // Add a use of the SOE register to all exit paths
802 for( uint j=1; j < root->req(); j++ )
803 root->in(j)->add_req(mproj);
804 } // End of if a save-on-entry register
805 } // End of for all machine registers
806 }
807
808 //------------------------------init_spill_mask--------------------------------
809 void Matcher::init_spill_mask( Node *ret ) {
810 if( idealreg2regmask[Op_RegI] ) return; // One time only init
811
812 OptoReg::c_frame_pointer = c_frame_pointer();
813 c_frame_ptr_mask = c_frame_pointer();
814 #ifdef _LP64
815 // pointers are twice as big
816 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
817 #endif
818
819 // Start at OptoReg::stack0()
820 STACK_ONLY_mask.Clear();
821 OptoReg::Name init = OptoReg::stack2reg(0);
822 // STACK_ONLY_mask is all stack bits
823 OptoReg::Name i;
824 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
825 STACK_ONLY_mask.Insert(i);
826 // Also set the "infinite stack" bit.
827 STACK_ONLY_mask.set_AllStack();
828
829 // Copy the register names over into the shared world
830 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
831 // SharedInfo::regName[i] = regName[i];
832 // Handy RegMasks per machine register
833 mreg2regmask[i].Insert(i);
834 }
835
836 // Grab the Frame Pointer
837 Node *fp = ret->in(TypeFunc::FramePtr);
838 Node *mem = ret->in(TypeFunc::Memory);
839 const TypePtr* atp = TypePtr::BOTTOM;
840 // Share frame pointer while making spill ops
841 set_shared(fp);
842
843 // Compute generic short-offset Loads
844 #ifdef _LP64
845 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
846 #endif
847 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp));
848 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp));
849 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp));
850 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp));
851 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
852 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
853 spillD != NULL && spillP != NULL, "");
854
855 // Get the ADLC notion of the right regmask, for each basic type.
856 #ifdef _LP64
857 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
858 #endif
859 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
860 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
861 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
862 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
863 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
864
865 // Vector regmasks.
866 if (Matcher::vector_size_supported(T_BYTE,4)) {
867 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
868 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
869 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
870 }
871 if (Matcher::vector_size_supported(T_FLOAT,2)) {
872 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
873 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
874 }
875 if (Matcher::vector_size_supported(T_FLOAT,4)) {
876 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
877 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
878 }
879 if (Matcher::vector_size_supported(T_FLOAT,8)) {
880 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
881 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
882 }
883 }
884
885 #ifdef ASSERT
886 static void match_alias_type(Compile* C, Node* n, Node* m) {
887 if (!VerifyAliases) return; // do not go looking for trouble by default
888 const TypePtr* nat = n->adr_type();
889 const TypePtr* mat = m->adr_type();
890 int nidx = C->get_alias_index(nat);
891 int midx = C->get_alias_index(mat);
892 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
893 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
894 for (uint i = 1; i < n->req(); i++) {
895 Node* n1 = n->in(i);
896 const TypePtr* n1at = n1->adr_type();
897 if (n1at != NULL) {
898 nat = n1at;
899 nidx = C->get_alias_index(n1at);
900 }
901 }
902 }
903 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
904 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
905 switch (n->Opcode()) {
906 case Op_PrefetchRead:
907 case Op_PrefetchWrite:
908 case Op_PrefetchAllocation:
909 nidx = Compile::AliasIdxRaw;
910 nat = TypeRawPtr::BOTTOM;
911 break;
912 }
913 }
914 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
915 switch (n->Opcode()) {
916 case Op_ClearArray:
917 midx = Compile::AliasIdxRaw;
918 mat = TypeRawPtr::BOTTOM;
919 break;
920 }
921 }
922 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
923 switch (n->Opcode()) {
924 case Op_Return:
925 case Op_Rethrow:
926 case Op_Halt:
927 case Op_TailCall:
928 case Op_TailJump:
929 nidx = Compile::AliasIdxBot;
930 nat = TypePtr::BOTTOM;
931 break;
932 }
933 }
934 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
935 switch (n->Opcode()) {
936 case Op_StrComp:
937 case Op_StrEquals:
938 case Op_StrIndexOf:
939 case Op_AryEq:
940 case Op_MemBarVolatile:
941 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
942 case Op_EncodeISOArray:
943 nidx = Compile::AliasIdxTop;
944 nat = NULL;
945 break;
946 }
947 }
948 if (nidx != midx) {
949 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
950 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
951 n->dump();
952 m->dump();
953 }
954 assert(C->subsume_loads() && C->must_alias(nat, midx),
955 "must not lose alias info when matching");
956 }
957 }
958 #endif
959
960
961 //------------------------------MStack-----------------------------------------
962 // State and MStack class used in xform() and find_shared() iterative methods.
963 enum Node_State { Pre_Visit, // node has to be pre-visited
964 Visit, // visit node
965 Post_Visit, // post-visit node
966 Alt_Post_Visit // alternative post-visit path
967 };
968
969 class MStack: public Node_Stack {
970 public:
971 MStack(int size) : Node_Stack(size) { }
972
973 void push(Node *n, Node_State ns) {
974 Node_Stack::push(n, (uint)ns);
975 }
976 void push(Node *n, Node_State ns, Node *parent, int indx) {
977 ++_inode_top;
978 if ((_inode_top + 1) >= _inode_max) grow();
979 _inode_top->node = parent;
980 _inode_top->indx = (uint)indx;
981 ++_inode_top;
982 _inode_top->node = n;
983 _inode_top->indx = (uint)ns;
984 }
985 Node *parent() {
986 pop();
987 return node();
988 }
989 Node_State state() const {
990 return (Node_State)index();
991 }
992 void set_state(Node_State ns) {
993 set_index((uint)ns);
994 }
995 };
996
997
998 //------------------------------xform------------------------------------------
999 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1000 // Node in new-space. Given a new-space Node, recursively walk his children.
1001 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1002 Node *Matcher::xform( Node *n, int max_stack ) {
1003 // Use one stack to keep both: child's node/state and parent's node/index
1004 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
1005 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1006
1007 while (mstack.is_nonempty()) {
1008 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1009 if (C->failing()) return NULL;
1010 n = mstack.node(); // Leave node on stack
1011 Node_State nstate = mstack.state();
1012 if (nstate == Visit) {
1013 mstack.set_state(Post_Visit);
1014 Node *oldn = n;
1015 // Old-space or new-space check
1016 if (!C->node_arena()->contains(n)) {
1017 // Old space!
1018 Node* m;
1019 if (has_new_node(n)) { // Not yet Label/Reduced
1020 m = new_node(n);
1021 } else {
1022 if (!is_dontcare(n)) { // Matcher can match this guy
1023 // Calls match special. They match alone with no children.
1024 // Their children, the incoming arguments, match normally.
1025 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1026 if (C->failing()) return NULL;
1027 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1028 } else { // Nothing the matcher cares about
1029 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1030 // Convert to machine-dependent projection
1031 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1032 #ifdef ASSERT
1033 _new2old_map.map(m->_idx, n);
1034 #endif
1035 if (m->in(0) != NULL) // m might be top
1036 collect_null_checks(m, n);
1037 } else { // Else just a regular 'ol guy
1038 m = n->clone(); // So just clone into new-space
1039 #ifdef ASSERT
1040 _new2old_map.map(m->_idx, n);
1041 #endif
1042 // Def-Use edges will be added incrementally as Uses
1043 // of this node are matched.
1044 assert(m->outcnt() == 0, "no Uses of this clone yet");
1045 }
1046 }
1047
1048 set_new_node(n, m); // Map old to new
1049 if (_old_node_note_array != NULL) {
1050 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1051 n->_idx);
1052 C->set_node_notes_at(m->_idx, nn);
1053 }
1054 debug_only(match_alias_type(C, n, m));
1055 }
1056 n = m; // n is now a new-space node
1057 mstack.set_node(n);
1058 }
1059
1060 // New space!
1061 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1062
1063 int i;
1064 // Put precedence edges on stack first (match them last).
1065 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1066 Node *m = oldn->in(i);
1067 if (m == NULL) break;
1068 // set -1 to call add_prec() instead of set_req() during Step1
1069 mstack.push(m, Visit, n, -1);
1070 }
1071
1072 // For constant debug info, I'd rather have unmatched constants.
1073 int cnt = n->req();
1074 JVMState* jvms = n->jvms();
1075 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1076
1077 // Now do only debug info. Clone constants rather than matching.
1078 // Constants are represented directly in the debug info without
1079 // the need for executable machine instructions.
1080 // Monitor boxes are also represented directly.
1081 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1082 Node *m = n->in(i); // Get input
1083 int op = m->Opcode();
1084 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1085 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1086 op == Op_ConF || op == Op_ConD || op == Op_ConL
1087 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1088 ) {
1089 m = m->clone();
1090 #ifdef ASSERT
1091 _new2old_map.map(m->_idx, n);
1092 #endif
1093 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1094 mstack.push(m->in(0), Visit, m, 0);
1095 } else {
1096 mstack.push(m, Visit, n, i);
1097 }
1098 }
1099
1100 // And now walk his children, and convert his inputs to new-space.
1101 for( ; i >= 0; --i ) { // For all normal inputs do
1102 Node *m = n->in(i); // Get input
1103 if(m != NULL)
1104 mstack.push(m, Visit, n, i);
1105 }
1106
1107 }
1108 else if (nstate == Post_Visit) {
1109 // Set xformed input
1110 Node *p = mstack.parent();
1111 if (p != NULL) { // root doesn't have parent
1112 int i = (int)mstack.index();
1113 if (i >= 0)
1114 p->set_req(i, n); // required input
1115 else if (i == -1)
1116 p->add_prec(n); // precedence input
1117 else
1118 ShouldNotReachHere();
1119 }
1120 mstack.pop(); // remove processed node from stack
1121 }
1122 else {
1123 ShouldNotReachHere();
1124 }
1125 } // while (mstack.is_nonempty())
1126 return n; // Return new-space Node
1127 }
1128
1129 //------------------------------warp_outgoing_stk_arg------------------------
1130 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1131 // Convert outgoing argument location to a pre-biased stack offset
1132 if (reg->is_stack()) {
1133 OptoReg::Name warped = reg->reg2stack();
1134 // Adjust the stack slot offset to be the register number used
1135 // by the allocator.
1136 warped = OptoReg::add(begin_out_arg_area, warped);
1137 // Keep track of the largest numbered stack slot used for an arg.
1138 // Largest used slot per call-site indicates the amount of stack
1139 // that is killed by the call.
1140 if( warped >= out_arg_limit_per_call )
1141 out_arg_limit_per_call = OptoReg::add(warped,1);
1142 if (!RegMask::can_represent_arg(warped)) {
1143 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1144 return OptoReg::Bad;
1145 }
1146 return warped;
1147 }
1148 return OptoReg::as_OptoReg(reg);
1149 }
1150
1151
1152 //------------------------------match_sfpt-------------------------------------
1153 // Helper function to match call instructions. Calls match special.
1154 // They match alone with no children. Their children, the incoming
1155 // arguments, match normally.
1156 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1157 MachSafePointNode *msfpt = NULL;
1158 MachCallNode *mcall = NULL;
1159 uint cnt;
1160 // Split out case for SafePoint vs Call
1161 CallNode *call;
1162 const TypeTuple *domain;
1163 ciMethod* method = NULL;
1164 bool is_method_handle_invoke = false; // for special kill effects
1165 if( sfpt->is_Call() ) {
1166 call = sfpt->as_Call();
1167 domain = call->tf()->domain();
1168 cnt = domain->cnt();
1169
1170 // Match just the call, nothing else
1171 MachNode *m = match_tree(call);
1172 if (C->failing()) return NULL;
1173 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1174
1175 // Copy data from the Ideal SafePoint to the machine version
1176 mcall = m->as_MachCall();
1177
1178 mcall->set_tf( call->tf());
1179 mcall->set_entry_point(call->entry_point());
1180 mcall->set_cnt( call->cnt());
1181
1182 if( mcall->is_MachCallJava() ) {
1183 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1184 const CallJavaNode *call_java = call->as_CallJava();
1185 method = call_java->method();
1186 mcall_java->_method = method;
1187 mcall_java->_bci = call_java->_bci;
1188 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1189 is_method_handle_invoke = call_java->is_method_handle_invoke();
1190 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1191 if (is_method_handle_invoke) {
1192 C->set_has_method_handle_invokes(true);
1193 }
1194 if( mcall_java->is_MachCallStaticJava() )
1195 mcall_java->as_MachCallStaticJava()->_name =
1196 call_java->as_CallStaticJava()->_name;
1197 if( mcall_java->is_MachCallDynamicJava() )
1198 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1199 call_java->as_CallDynamicJava()->_vtable_index;
1200 }
1201 else if( mcall->is_MachCallRuntime() ) {
1202 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1203 }
1204 msfpt = mcall;
1205 }
1206 // This is a non-call safepoint
1207 else {
1208 call = NULL;
1209 domain = NULL;
1210 MachNode *mn = match_tree(sfpt);
1211 if (C->failing()) return NULL;
1212 msfpt = mn->as_MachSafePoint();
1213 cnt = TypeFunc::Parms;
1214 }
1215
1216 // Advertise the correct memory effects (for anti-dependence computation).
1217 msfpt->set_adr_type(sfpt->adr_type());
1218
1219 // Allocate a private array of RegMasks. These RegMasks are not shared.
1220 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1221 // Empty them all.
1222 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1223
1224 // Do all the pre-defined non-Empty register masks
1225 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1226 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1227
1228 // Place first outgoing argument can possibly be put.
1229 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1230 assert( is_even(begin_out_arg_area), "" );
1231 // Compute max outgoing register number per call site.
1232 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1233 // Calls to C may hammer extra stack slots above and beyond any arguments.
1234 // These are usually backing store for register arguments for varargs.
1235 if( call != NULL && call->is_CallRuntime() )
1236 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1237
1238
1239 // Do the normal argument list (parameters) register masks
1240 int argcnt = cnt - TypeFunc::Parms;
1241 if( argcnt > 0 ) { // Skip it all if we have no args
1242 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1243 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1244 int i;
1245 for( i = 0; i < argcnt; i++ ) {
1246 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1247 }
1248 // V-call to pick proper calling convention
1249 call->calling_convention( sig_bt, parm_regs, argcnt );
1250
1251 #ifdef ASSERT
1252 // Sanity check users' calling convention. Really handy during
1253 // the initial porting effort. Fairly expensive otherwise.
1254 { for (int i = 0; i<argcnt; i++) {
1255 if( !parm_regs[i].first()->is_valid() &&
1256 !parm_regs[i].second()->is_valid() ) continue;
1257 VMReg reg1 = parm_regs[i].first();
1258 VMReg reg2 = parm_regs[i].second();
1259 for (int j = 0; j < i; j++) {
1260 if( !parm_regs[j].first()->is_valid() &&
1261 !parm_regs[j].second()->is_valid() ) continue;
1262 VMReg reg3 = parm_regs[j].first();
1263 VMReg reg4 = parm_regs[j].second();
1264 if( !reg1->is_valid() ) {
1265 assert( !reg2->is_valid(), "valid halvsies" );
1266 } else if( !reg3->is_valid() ) {
1267 assert( !reg4->is_valid(), "valid halvsies" );
1268 } else {
1269 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1270 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1271 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1272 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1273 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1274 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1275 }
1276 }
1277 }
1278 }
1279 #endif
1280
1281 // Visit each argument. Compute its outgoing register mask.
1282 // Return results now can have 2 bits returned.
1283 // Compute max over all outgoing arguments both per call-site
1284 // and over the entire method.
1285 for( i = 0; i < argcnt; i++ ) {
1286 // Address of incoming argument mask to fill in
1287 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1288 if( !parm_regs[i].first()->is_valid() &&
1289 !parm_regs[i].second()->is_valid() ) {
1290 continue; // Avoid Halves
1291 }
1292 // Grab first register, adjust stack slots and insert in mask.
1293 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1294 if (OptoReg::is_valid(reg1))
1295 rm->Insert( reg1 );
1296 // Grab second register (if any), adjust stack slots and insert in mask.
1297 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1298 if (OptoReg::is_valid(reg2))
1299 rm->Insert( reg2 );
1300 } // End of for all arguments
1301
1302 // Compute number of stack slots needed to restore stack in case of
1303 // Pascal-style argument popping.
1304 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1305 }
1306
1307 // Compute the max stack slot killed by any call. These will not be
1308 // available for debug info, and will be used to adjust FIRST_STACK_mask
1309 // after all call sites have been visited.
1310 if( _out_arg_limit < out_arg_limit_per_call)
1311 _out_arg_limit = out_arg_limit_per_call;
1312
1313 if (mcall) {
1314 // Kill the outgoing argument area, including any non-argument holes and
1315 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1316 // Since the max-per-method covers the max-per-call-site and debug info
1317 // is excluded on the max-per-method basis, debug info cannot land in
1318 // this killed area.
1319 uint r_cnt = mcall->tf()->range()->cnt();
1320 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1321 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1322 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1323 } else {
1324 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1325 proj->_rout.Insert(OptoReg::Name(i));
1326 }
1327 if (proj->_rout.is_NotEmpty()) {
1328 push_projection(proj);
1329 }
1330 }
1331 // Transfer the safepoint information from the call to the mcall
1332 // Move the JVMState list
1333 msfpt->set_jvms(sfpt->jvms());
1334 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1335 jvms->set_map(sfpt);
1336 }
1337
1338 // Debug inputs begin just after the last incoming parameter
1339 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1340 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1341
1342 // Move the OopMap
1343 msfpt->_oop_map = sfpt->_oop_map;
1344
1345 // Registers killed by the call are set in the local scheduling pass
1346 // of Global Code Motion.
1347 return msfpt;
1348 }
1349
1350 //---------------------------match_tree----------------------------------------
1351 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1352 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1353 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1354 // a Load's result RegMask for memoization in idealreg2regmask[]
1355 MachNode *Matcher::match_tree( const Node *n ) {
1356 assert( n->Opcode() != Op_Phi, "cannot match" );
1357 assert( !n->is_block_start(), "cannot match" );
1358 // Set the mark for all locally allocated State objects.
1359 // When this call returns, the _states_arena arena will be reset
1360 // freeing all State objects.
1361 ResourceMark rm( &_states_arena );
1362
1363 LabelRootDepth = 0;
1364
1365 // StoreNodes require their Memory input to match any LoadNodes
1366 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1367 #ifdef ASSERT
1368 Node* save_mem_node = _mem_node;
1369 _mem_node = n->is_Store() ? (Node*)n : NULL;
1370 #endif
1371 // State object for root node of match tree
1372 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1373 State *s = new (&_states_arena) State;
1374 s->_kids[0] = NULL;
1375 s->_kids[1] = NULL;
1376 s->_leaf = (Node*)n;
1377 // Label the input tree, allocating labels from top-level arena
1378 Label_Root( n, s, n->in(0), mem );
1379 if (C->failing()) return NULL;
1380
1381 // The minimum cost match for the whole tree is found at the root State
1382 uint mincost = max_juint;
1383 uint cost = max_juint;
1384 uint i;
1385 for( i = 0; i < NUM_OPERANDS; i++ ) {
1386 if( s->valid(i) && // valid entry and
1387 s->_cost[i] < cost && // low cost and
1388 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1389 cost = s->_cost[mincost=i];
1390 }
1391 if (mincost == max_juint) {
1392 #ifndef PRODUCT
1393 tty->print("No matching rule for:");
1394 s->dump();
1395 #endif
1396 Matcher::soft_match_failure();
1397 return NULL;
1398 }
1399 // Reduce input tree based upon the state labels to machine Nodes
1400 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1401 #ifdef ASSERT
1402 _old2new_map.map(n->_idx, m);
1403 _new2old_map.map(m->_idx, (Node*)n);
1404 #endif
1405
1406 // Add any Matcher-ignored edges
1407 uint cnt = n->req();
1408 uint start = 1;
1409 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1410 if( n->is_AddP() ) {
1411 assert( mem == (Node*)1, "" );
1412 start = AddPNode::Base+1;
1413 }
1414 for( i = start; i < cnt; i++ ) {
1415 if( !n->match_edge(i) ) {
1416 if( i < m->req() )
1417 m->ins_req( i, n->in(i) );
1418 else
1419 m->add_req( n->in(i) );
1420 }
1421 }
1422
1423 debug_only( _mem_node = save_mem_node; )
1424 return m;
1425 }
1426
1427
1428 //------------------------------match_into_reg---------------------------------
1429 // Choose to either match this Node in a register or part of the current
1430 // match tree. Return true for requiring a register and false for matching
1431 // as part of the current match tree.
1432 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1433
1434 const Type *t = m->bottom_type();
1435
1436 if (t->singleton()) {
1437 // Never force constants into registers. Allow them to match as
1438 // constants or registers. Copies of the same value will share
1439 // the same register. See find_shared_node.
1440 return false;
1441 } else { // Not a constant
1442 // Stop recursion if they have different Controls.
1443 Node* m_control = m->in(0);
1444 // Control of load's memory can post-dominates load's control.
1445 // So use it since load can't float above its memory.
1446 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1447 if (control && m_control && control != m_control && control != mem_control) {
1448
1449 // Actually, we can live with the most conservative control we
1450 // find, if it post-dominates the others. This allows us to
1451 // pick up load/op/store trees where the load can float a little
1452 // above the store.
1453 Node *x = control;
1454 const uint max_scan = 6; // Arbitrary scan cutoff
1455 uint j;
1456 for (j=0; j<max_scan; j++) {
1457 if (x->is_Region()) // Bail out at merge points
1458 return true;
1459 x = x->in(0);
1460 if (x == m_control) // Does 'control' post-dominate
1461 break; // m->in(0)? If so, we can use it
1462 if (x == mem_control) // Does 'control' post-dominate
1463 break; // mem_control? If so, we can use it
1464 }
1465 if (j == max_scan) // No post-domination before scan end?
1466 return true; // Then break the match tree up
1467 }
1468 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1469 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1470 // These are commonly used in address expressions and can
1471 // efficiently fold into them on X64 in some cases.
1472 return false;
1473 }
1474 }
1475
1476 // Not forceable cloning. If shared, put it into a register.
1477 return shared;
1478 }
1479
1480
1481 //------------------------------Instruction Selection--------------------------
1482 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1483 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1484 // things the Matcher does not match (e.g., Memory), and things with different
1485 // Controls (hence forced into different blocks). We pass in the Control
1486 // selected for this entire State tree.
1487
1488 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1489 // Store and the Load must have identical Memories (as well as identical
1490 // pointers). Since the Matcher does not have anything for Memory (and
1491 // does not handle DAGs), I have to match the Memory input myself. If the
1492 // Tree root is a Store, I require all Loads to have the identical memory.
1493 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1494 // Since Label_Root is a recursive function, its possible that we might run
1495 // out of stack space. See bugs 6272980 & 6227033 for more info.
1496 LabelRootDepth++;
1497 if (LabelRootDepth > MaxLabelRootDepth) {
1498 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1499 return NULL;
1500 }
1501 uint care = 0; // Edges matcher cares about
1502 uint cnt = n->req();
1503 uint i = 0;
1504
1505 // Examine children for memory state
1506 // Can only subsume a child into your match-tree if that child's memory state
1507 // is not modified along the path to another input.
1508 // It is unsafe even if the other inputs are separate roots.
1509 Node *input_mem = NULL;
1510 for( i = 1; i < cnt; i++ ) {
1511 if( !n->match_edge(i) ) continue;
1512 Node *m = n->in(i); // Get ith input
1513 assert( m, "expect non-null children" );
1514 if( m->is_Load() ) {
1515 if( input_mem == NULL ) {
1516 input_mem = m->in(MemNode::Memory);
1517 } else if( input_mem != m->in(MemNode::Memory) ) {
1518 input_mem = NodeSentinel;
1519 }
1520 }
1521 }
1522
1523 for( i = 1; i < cnt; i++ ){// For my children
1524 if( !n->match_edge(i) ) continue;
1525 Node *m = n->in(i); // Get ith input
1526 // Allocate states out of a private arena
1527 State *s = new (&_states_arena) State;
1528 svec->_kids[care++] = s;
1529 assert( care <= 2, "binary only for now" );
1530
1531 // Recursively label the State tree.
1532 s->_kids[0] = NULL;
1533 s->_kids[1] = NULL;
1534 s->_leaf = m;
1535
1536 // Check for leaves of the State Tree; things that cannot be a part of
1537 // the current tree. If it finds any, that value is matched as a
1538 // register operand. If not, then the normal matching is used.
1539 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1540 //
1541 // Stop recursion if this is LoadNode and the root of this tree is a
1542 // StoreNode and the load & store have different memories.
1543 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1544 // Can NOT include the match of a subtree when its memory state
1545 // is used by any of the other subtrees
1546 (input_mem == NodeSentinel) ) {
1547 #ifndef PRODUCT
1548 // Print when we exclude matching due to different memory states at input-loads
1549 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1550 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1551 tty->print_cr("invalid input_mem");
1552 }
1553 #endif
1554 // Switch to a register-only opcode; this value must be in a register
1555 // and cannot be subsumed as part of a larger instruction.
1556 s->DFA( m->ideal_reg(), m );
1557
1558 } else {
1559 // If match tree has no control and we do, adopt it for entire tree
1560 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1561 control = m->in(0); // Pick up control
1562 // Else match as a normal part of the match tree.
1563 control = Label_Root(m,s,control,mem);
1564 if (C->failing()) return NULL;
1565 }
1566 }
1567
1568
1569 // Call DFA to match this node, and return
1570 svec->DFA( n->Opcode(), n );
1571
1572 #ifdef ASSERT
1573 uint x;
1574 for( x = 0; x < _LAST_MACH_OPER; x++ )
1575 if( svec->valid(x) )
1576 break;
1577
1578 if (x >= _LAST_MACH_OPER) {
1579 n->dump();
1580 svec->dump();
1581 assert( false, "bad AD file" );
1582 }
1583 #endif
1584 return control;
1585 }
1586
1587
1588 // Con nodes reduced using the same rule can share their MachNode
1589 // which reduces the number of copies of a constant in the final
1590 // program. The register allocator is free to split uses later to
1591 // split live ranges.
1592 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1593 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1594
1595 // See if this Con has already been reduced using this rule.
1596 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1597 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1598 if (last != NULL && rule == last->rule()) {
1599 // Don't expect control change for DecodeN
1600 if (leaf->is_DecodeNarrowPtr())
1601 return last;
1602 // Get the new space root.
1603 Node* xroot = new_node(C->root());
1604 if (xroot == NULL) {
1605 // This shouldn't happen give the order of matching.
1606 return NULL;
1607 }
1608
1609 // Shared constants need to have their control be root so they
1610 // can be scheduled properly.
1611 Node* control = last->in(0);
1612 if (control != xroot) {
1613 if (control == NULL || control == C->root()) {
1614 last->set_req(0, xroot);
1615 } else {
1616 assert(false, "unexpected control");
1617 return NULL;
1618 }
1619 }
1620 return last;
1621 }
1622 return NULL;
1623 }
1624
1625
1626 //------------------------------ReduceInst-------------------------------------
1627 // Reduce a State tree (with given Control) into a tree of MachNodes.
1628 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1629 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1630 // Each MachNode has a number of complicated MachOper operands; each
1631 // MachOper also covers a further tree of Ideal Nodes.
1632
1633 // The root of the Ideal match tree is always an instruction, so we enter
1634 // the recursion here. After building the MachNode, we need to recurse
1635 // the tree checking for these cases:
1636 // (1) Child is an instruction -
1637 // Build the instruction (recursively), add it as an edge.
1638 // Build a simple operand (register) to hold the result of the instruction.
1639 // (2) Child is an interior part of an instruction -
1640 // Skip over it (do nothing)
1641 // (3) Child is the start of a operand -
1642 // Build the operand, place it inside the instruction
1643 // Call ReduceOper.
1644 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1645 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1646
1647 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1648 if (shared_node != NULL) {
1649 return shared_node;
1650 }
1651
1652 // Build the object to represent this state & prepare for recursive calls
1653 MachNode *mach = s->MachNodeGenerator( rule, C );
1654 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1655 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1656 Node *leaf = s->_leaf;
1657 // Check for instruction or instruction chain rule
1658 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1659 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1660 "duplicating node that's already been matched");
1661 // Instruction
1662 mach->add_req( leaf->in(0) ); // Set initial control
1663 // Reduce interior of complex instruction
1664 ReduceInst_Interior( s, rule, mem, mach, 1 );
1665 } else {
1666 // Instruction chain rules are data-dependent on their inputs
1667 mach->add_req(0); // Set initial control to none
1668 ReduceInst_Chain_Rule( s, rule, mem, mach );
1669 }
1670
1671 // If a Memory was used, insert a Memory edge
1672 if( mem != (Node*)1 ) {
1673 mach->ins_req(MemNode::Memory,mem);
1674 #ifdef ASSERT
1675 // Verify adr type after matching memory operation
1676 const MachOper* oper = mach->memory_operand();
1677 if (oper != NULL && oper != (MachOper*)-1) {
1678 // It has a unique memory operand. Find corresponding ideal mem node.
1679 Node* m = NULL;
1680 if (leaf->is_Mem()) {
1681 m = leaf;
1682 } else {
1683 m = _mem_node;
1684 assert(m != NULL && m->is_Mem(), "expecting memory node");
1685 }
1686 const Type* mach_at = mach->adr_type();
1687 // DecodeN node consumed by an address may have different type
1688 // then its input. Don't compare types for such case.
1689 if (m->adr_type() != mach_at &&
1690 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1691 m->in(MemNode::Address)->is_AddP() &&
1692 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1693 m->in(MemNode::Address)->is_AddP() &&
1694 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1695 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1696 mach_at = m->adr_type();
1697 }
1698 if (m->adr_type() != mach_at) {
1699 m->dump();
1700 tty->print_cr("mach:");
1701 mach->dump(1);
1702 }
1703 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1704 }
1705 #endif
1706 }
1707
1708 // If the _leaf is an AddP, insert the base edge
1709 if (leaf->is_AddP()) {
1710 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1711 }
1712
1713 uint number_of_projections_prior = number_of_projections();
1714
1715 // Perform any 1-to-many expansions required
1716 MachNode *ex = mach->Expand(s, _projection_list, mem);
1717 if (ex != mach) {
1718 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1719 if( ex->in(1)->is_Con() )
1720 ex->in(1)->set_req(0, C->root());
1721 // Remove old node from the graph
1722 for( uint i=0; i<mach->req(); i++ ) {
1723 mach->set_req(i,NULL);
1724 }
1725 #ifdef ASSERT
1726 _new2old_map.map(ex->_idx, s->_leaf);
1727 #endif
1728 }
1729
1730 // PhaseChaitin::fixup_spills will sometimes generate spill code
1731 // via the matcher. By the time, nodes have been wired into the CFG,
1732 // and any further nodes generated by expand rules will be left hanging
1733 // in space, and will not get emitted as output code. Catch this.
1734 // Also, catch any new register allocation constraints ("projections")
1735 // generated belatedly during spill code generation.
1736 if (_allocation_started) {
1737 guarantee(ex == mach, "no expand rules during spill generation");
1738 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1739 }
1740
1741 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1742 // Record the con for sharing
1743 _shared_nodes.map(leaf->_idx, ex);
1744 }
1745
1746 return ex;
1747 }
1748
1749 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1750 // 'op' is what I am expecting to receive
1751 int op = _leftOp[rule];
1752 // Operand type to catch childs result
1753 // This is what my child will give me.
1754 int opnd_class_instance = s->_rule[op];
1755 // Choose between operand class or not.
1756 // This is what I will receive.
1757 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1758 // New rule for child. Chase operand classes to get the actual rule.
1759 int newrule = s->_rule[catch_op];
1760
1761 if( newrule < NUM_OPERANDS ) {
1762 // Chain from operand or operand class, may be output of shared node
1763 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1764 "Bad AD file: Instruction chain rule must chain from operand");
1765 // Insert operand into array of operands for this instruction
1766 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1767
1768 ReduceOper( s, newrule, mem, mach );
1769 } else {
1770 // Chain from the result of an instruction
1771 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1772 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1773 Node *mem1 = (Node*)1;
1774 debug_only(Node *save_mem_node = _mem_node;)
1775 mach->add_req( ReduceInst(s, newrule, mem1) );
1776 debug_only(_mem_node = save_mem_node;)
1777 }
1778 return;
1779 }
1780
1781
1782 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1783 if( s->_leaf->is_Load() ) {
1784 Node *mem2 = s->_leaf->in(MemNode::Memory);
1785 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1786 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1787 mem = mem2;
1788 }
1789 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1790 if( mach->in(0) == NULL )
1791 mach->set_req(0, s->_leaf->in(0));
1792 }
1793
1794 // Now recursively walk the state tree & add operand list.
1795 for( uint i=0; i<2; i++ ) { // binary tree
1796 State *newstate = s->_kids[i];
1797 if( newstate == NULL ) break; // Might only have 1 child
1798 // 'op' is what I am expecting to receive
1799 int op;
1800 if( i == 0 ) {
1801 op = _leftOp[rule];
1802 } else {
1803 op = _rightOp[rule];
1804 }
1805 // Operand type to catch childs result
1806 // This is what my child will give me.
1807 int opnd_class_instance = newstate->_rule[op];
1808 // Choose between operand class or not.
1809 // This is what I will receive.
1810 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1811 // New rule for child. Chase operand classes to get the actual rule.
1812 int newrule = newstate->_rule[catch_op];
1813
1814 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1815 // Operand/operandClass
1816 // Insert operand into array of operands for this instruction
1817 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1818 ReduceOper( newstate, newrule, mem, mach );
1819
1820 } else { // Child is internal operand or new instruction
1821 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1822 // internal operand --> call ReduceInst_Interior
1823 // Interior of complex instruction. Do nothing but recurse.
1824 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1825 } else {
1826 // instruction --> call build operand( ) to catch result
1827 // --> ReduceInst( newrule )
1828 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1829 Node *mem1 = (Node*)1;
1830 debug_only(Node *save_mem_node = _mem_node;)
1831 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1832 debug_only(_mem_node = save_mem_node;)
1833 }
1834 }
1835 assert( mach->_opnds[num_opnds-1], "" );
1836 }
1837 return num_opnds;
1838 }
1839
1840 // This routine walks the interior of possible complex operands.
1841 // At each point we check our children in the match tree:
1842 // (1) No children -
1843 // We are a leaf; add _leaf field as an input to the MachNode
1844 // (2) Child is an internal operand -
1845 // Skip over it ( do nothing )
1846 // (3) Child is an instruction -
1847 // Call ReduceInst recursively and
1848 // and instruction as an input to the MachNode
1849 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1850 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1851 State *kid = s->_kids[0];
1852 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1853
1854 // Leaf? And not subsumed?
1855 if( kid == NULL && !_swallowed[rule] ) {
1856 mach->add_req( s->_leaf ); // Add leaf pointer
1857 return; // Bail out
1858 }
1859
1860 if( s->_leaf->is_Load() ) {
1861 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1862 mem = s->_leaf->in(MemNode::Memory);
1863 debug_only(_mem_node = s->_leaf;)
1864 }
1865 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1866 if( !mach->in(0) )
1867 mach->set_req(0,s->_leaf->in(0));
1868 else {
1869 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1870 }
1871 }
1872
1873 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1874 int newrule;
1875 if( i == 0)
1876 newrule = kid->_rule[_leftOp[rule]];
1877 else
1878 newrule = kid->_rule[_rightOp[rule]];
1879
1880 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1881 // Internal operand; recurse but do nothing else
1882 ReduceOper( kid, newrule, mem, mach );
1883
1884 } else { // Child is a new instruction
1885 // Reduce the instruction, and add a direct pointer from this
1886 // machine instruction to the newly reduced one.
1887 Node *mem1 = (Node*)1;
1888 debug_only(Node *save_mem_node = _mem_node;)
1889 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1890 debug_only(_mem_node = save_mem_node;)
1891 }
1892 }
1893 }
1894
1895
1896 // -------------------------------------------------------------------------
1897 // Java-Java calling convention
1898 // (what you use when Java calls Java)
1899
1900 //------------------------------find_receiver----------------------------------
1901 // For a given signature, return the OptoReg for parameter 0.
1902 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1903 VMRegPair regs;
1904 BasicType sig_bt = T_OBJECT;
1905 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1906 // Return argument 0 register. In the LP64 build pointers
1907 // take 2 registers, but the VM wants only the 'main' name.
1908 return OptoReg::as_OptoReg(regs.first());
1909 }
1910
1911 // A method-klass-holder may be passed in the inline_cache_reg
1912 // and then expanded into the inline_cache_reg and a method_oop register
1913 // defined in ad_<arch>.cpp
1914
1915
1916 //------------------------------find_shared------------------------------------
1917 // Set bits if Node is shared or otherwise a root
1918 void Matcher::find_shared( Node *n ) {
1919 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1920 MStack mstack(C->unique() * 2);
1921 // Mark nodes as address_visited if they are inputs to an address expression
1922 VectorSet address_visited(Thread::current()->resource_area());
1923 mstack.push(n, Visit); // Don't need to pre-visit root node
1924 while (mstack.is_nonempty()) {
1925 n = mstack.node(); // Leave node on stack
1926 Node_State nstate = mstack.state();
1927 uint nop = n->Opcode();
1928 if (nstate == Pre_Visit) {
1929 if (address_visited.test(n->_idx)) { // Visited in address already?
1930 // Flag as visited and shared now.
1931 set_visited(n);
1932 }
1933 if (is_visited(n)) { // Visited already?
1934 // Node is shared and has no reason to clone. Flag it as shared.
1935 // This causes it to match into a register for the sharing.
1936 set_shared(n); // Flag as shared and
1937 mstack.pop(); // remove node from stack
1938 continue;
1939 }
1940 nstate = Visit; // Not already visited; so visit now
1941 }
1942 if (nstate == Visit) {
1943 mstack.set_state(Post_Visit);
1944 set_visited(n); // Flag as visited now
1945 bool mem_op = false;
1946
1947 switch( nop ) { // Handle some opcodes special
1948 case Op_Phi: // Treat Phis as shared roots
1949 case Op_Parm:
1950 case Op_Proj: // All handled specially during matching
1951 case Op_SafePointScalarObject:
1952 set_shared(n);
1953 set_dontcare(n);
1954 break;
1955 case Op_If:
1956 case Op_CountedLoopEnd:
1957 mstack.set_state(Alt_Post_Visit); // Alternative way
1958 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1959 // with matching cmp/branch in 1 instruction. The Matcher needs the
1960 // Bool and CmpX side-by-side, because it can only get at constants
1961 // that are at the leaves of Match trees, and the Bool's condition acts
1962 // as a constant here.
1963 mstack.push(n->in(1), Visit); // Clone the Bool
1964 mstack.push(n->in(0), Pre_Visit); // Visit control input
1965 continue; // while (mstack.is_nonempty())
1966 case Op_ConvI2D: // These forms efficiently match with a prior
1967 case Op_ConvI2F: // Load but not a following Store
1968 if( n->in(1)->is_Load() && // Prior load
1969 n->outcnt() == 1 && // Not already shared
1970 n->unique_out()->is_Store() ) // Following store
1971 set_shared(n); // Force it to be a root
1972 break;
1973 case Op_ReverseBytesI:
1974 case Op_ReverseBytesL:
1975 if( n->in(1)->is_Load() && // Prior load
1976 n->outcnt() == 1 ) // Not already shared
1977 set_shared(n); // Force it to be a root
1978 break;
1979 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1980 case Op_IfFalse:
1981 case Op_IfTrue:
1982 case Op_MachProj:
1983 case Op_MergeMem:
1984 case Op_Catch:
1985 case Op_CatchProj:
1986 case Op_CProj:
1987 case Op_JumpProj:
1988 case Op_JProj:
1989 case Op_NeverBranch:
1990 set_dontcare(n);
1991 break;
1992 case Op_Jump:
1993 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
1994 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1995 continue; // while (mstack.is_nonempty())
1996 case Op_StrComp:
1997 case Op_StrEquals:
1998 case Op_StrIndexOf:
1999 case Op_AryEq:
2000 case Op_EncodeISOArray:
2001 set_shared(n); // Force result into register (it will be anyways)
2002 break;
2003 case Op_ConP: { // Convert pointers above the centerline to NUL
2004 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2005 const TypePtr* tp = tn->type()->is_ptr();
2006 if (tp->_ptr == TypePtr::AnyNull) {
2007 tn->set_type(TypePtr::NULL_PTR);
2008 }
2009 break;
2010 }
2011 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2012 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2013 const TypePtr* tp = tn->type()->make_ptr();
2014 if (tp && tp->_ptr == TypePtr::AnyNull) {
2015 tn->set_type(TypeNarrowOop::NULL_PTR);
2016 }
2017 break;
2018 }
2019 case Op_Binary: // These are introduced in the Post_Visit state.
2020 ShouldNotReachHere();
2021 break;
2022 case Op_ClearArray:
2023 case Op_SafePoint:
2024 mem_op = true;
2025 break;
2026 default:
2027 if( n->is_Store() ) {
2028 // Do match stores, despite no ideal reg
2029 mem_op = true;
2030 break;
2031 }
2032 if( n->is_Mem() ) { // Loads and LoadStores
2033 mem_op = true;
2034 // Loads must be root of match tree due to prior load conflict
2035 if( C->subsume_loads() == false )
2036 set_shared(n);
2037 }
2038 // Fall into default case
2039 if( !n->ideal_reg() )
2040 set_dontcare(n); // Unmatchable Nodes
2041 } // end_switch
2042
2043 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2044 Node *m = n->in(i); // Get ith input
2045 if (m == NULL) continue; // Ignore NULLs
2046 uint mop = m->Opcode();
2047
2048 // Must clone all producers of flags, or we will not match correctly.
2049 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2050 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2051 // are also there, so we may match a float-branch to int-flags and
2052 // expect the allocator to haul the flags from the int-side to the
2053 // fp-side. No can do.
2054 if( _must_clone[mop] ) {
2055 mstack.push(m, Visit);
2056 continue; // for(int i = ...)
2057 }
2058
2059 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2060 // Bases used in addresses must be shared but since
2061 // they are shared through a DecodeN they may appear
2062 // to have a single use so force sharing here.
2063 set_shared(m->in(AddPNode::Base)->in(1));
2064 }
2065
2066 // Clone addressing expressions as they are "free" in memory access instructions
2067 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2068 // Some inputs for address expression are not put on stack
2069 // to avoid marking them as shared and forcing them into register
2070 // if they are used only in address expressions.
2071 // But they should be marked as shared if there are other uses
2072 // besides address expressions.
2073
2074 Node *off = m->in(AddPNode::Offset);
2075 if( off->is_Con() &&
2076 // When there are other uses besides address expressions
2077 // put it on stack and mark as shared.
2078 !is_visited(m) ) {
2079 address_visited.test_set(m->_idx); // Flag as address_visited
2080 Node *adr = m->in(AddPNode::Address);
2081
2082 // Intel, ARM and friends can handle 2 adds in addressing mode
2083 if( clone_shift_expressions && adr->is_AddP() &&
2084 // AtomicAdd is not an addressing expression.
2085 // Cheap to find it by looking for screwy base.
2086 !adr->in(AddPNode::Base)->is_top() &&
2087 // Are there other uses besides address expressions?
2088 !is_visited(adr) ) {
2089 address_visited.set(adr->_idx); // Flag as address_visited
2090 Node *shift = adr->in(AddPNode::Offset);
2091 // Check for shift by small constant as well
2092 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2093 shift->in(2)->get_int() <= 3 &&
2094 // Are there other uses besides address expressions?
2095 !is_visited(shift) ) {
2096 address_visited.set(shift->_idx); // Flag as address_visited
2097 mstack.push(shift->in(2), Visit);
2098 Node *conv = shift->in(1);
2099 #ifdef _LP64
2100 // Allow Matcher to match the rule which bypass
2101 // ConvI2L operation for an array index on LP64
2102 // if the index value is positive.
2103 if( conv->Opcode() == Op_ConvI2L &&
2104 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2105 // Are there other uses besides address expressions?
2106 !is_visited(conv) ) {
2107 address_visited.set(conv->_idx); // Flag as address_visited
2108 mstack.push(conv->in(1), Pre_Visit);
2109 } else
2110 #endif
2111 mstack.push(conv, Pre_Visit);
2112 } else {
2113 mstack.push(shift, Pre_Visit);
2114 }
2115 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2116 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2117 } else { // Sparc, Alpha, PPC and friends
2118 mstack.push(adr, Pre_Visit);
2119 }
2120
2121 // Clone X+offset as it also folds into most addressing expressions
2122 mstack.push(off, Visit);
2123 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2124 continue; // for(int i = ...)
2125 } // if( off->is_Con() )
2126 } // if( mem_op &&
2127 mstack.push(m, Pre_Visit);
2128 } // for(int i = ...)
2129 }
2130 else if (nstate == Alt_Post_Visit) {
2131 mstack.pop(); // Remove node from stack
2132 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2133 // shared and all users of the Bool need to move the Cmp in parallel.
2134 // This leaves both the Bool and the If pointing at the Cmp. To
2135 // prevent the Matcher from trying to Match the Cmp along both paths
2136 // BoolNode::match_edge always returns a zero.
2137
2138 // We reorder the Op_If in a pre-order manner, so we can visit without
2139 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2140 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2141 }
2142 else if (nstate == Post_Visit) {
2143 mstack.pop(); // Remove node from stack
2144
2145 // Now hack a few special opcodes
2146 switch( n->Opcode() ) { // Handle some opcodes special
2147 case Op_StorePConditional:
2148 case Op_StoreIConditional:
2149 case Op_StoreLConditional:
2150 case Op_CompareAndSwapI:
2151 case Op_CompareAndSwapL:
2152 case Op_CompareAndSwapP:
2153 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2154 Node *newval = n->in(MemNode::ValueIn );
2155 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2156 Node *pair = new (C) BinaryNode( oldval, newval );
2157 n->set_req(MemNode::ValueIn,pair);
2158 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2159 break;
2160 }
2161 case Op_CMoveD: // Convert trinary to binary-tree
2162 case Op_CMoveF:
2163 case Op_CMoveI:
2164 case Op_CMoveL:
2165 case Op_CMoveN:
2166 case Op_CMoveP: {
2167 // Restructure into a binary tree for Matching. It's possible that
2168 // we could move this code up next to the graph reshaping for IfNodes
2169 // or vice-versa, but I do not want to debug this for Ladybird.
2170 // 10/2/2000 CNC.
2171 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2172 n->set_req(1,pair1);
2173 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2174 n->set_req(2,pair2);
2175 n->del_req(3);
2176 break;
2177 }
2178 case Op_LoopLimit: {
2179 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2180 n->set_req(1,pair1);
2181 n->set_req(2,n->in(3));
2182 n->del_req(3);
2183 break;
2184 }
2185 case Op_StrEquals: {
2186 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2187 n->set_req(2,pair1);
2188 n->set_req(3,n->in(4));
2189 n->del_req(4);
2190 break;
2191 }
2192 case Op_StrComp:
2193 case Op_StrIndexOf: {
2194 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2195 n->set_req(2,pair1);
2196 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2197 n->set_req(3,pair2);
2198 n->del_req(5);
2199 n->del_req(4);
2200 break;
2201 }
2202 case Op_EncodeISOArray: {
2203 // Restructure into a binary tree for Matching.
2204 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2205 n->set_req(3, pair);
2206 n->del_req(4);
2207 break;
2208 }
2209 default:
2210 break;
2211 }
2212 }
2213 else {
2214 ShouldNotReachHere();
2215 }
2216 } // end of while (mstack.is_nonempty())
2217 }
2218
2219 #ifdef ASSERT
2220 // machine-independent root to machine-dependent root
2221 void Matcher::dump_old2new_map() {
2222 _old2new_map.dump();
2223 }
2224 #endif
2225
2226 //---------------------------collect_null_checks-------------------------------
2227 // Find null checks in the ideal graph; write a machine-specific node for
2228 // it. Used by later implicit-null-check handling. Actually collects
2229 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2230 // value being tested.
2231 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2232 Node *iff = proj->in(0);
2233 if( iff->Opcode() == Op_If ) {
2234 // During matching If's have Bool & Cmp side-by-side
2235 BoolNode *b = iff->in(1)->as_Bool();
2236 Node *cmp = iff->in(2);
2237 int opc = cmp->Opcode();
2238 if (opc != Op_CmpP && opc != Op_CmpN) return;
2239
2240 const Type* ct = cmp->in(2)->bottom_type();
2241 if (ct == TypePtr::NULL_PTR ||
2242 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2243
2244 bool push_it = false;
2245 if( proj->Opcode() == Op_IfTrue ) {
2246 extern int all_null_checks_found;
2247 all_null_checks_found++;
2248 if( b->_test._test == BoolTest::ne ) {
2249 push_it = true;
2250 }
2251 } else {
2252 assert( proj->Opcode() == Op_IfFalse, "" );
2253 if( b->_test._test == BoolTest::eq ) {
2254 push_it = true;
2255 }
2256 }
2257 if( push_it ) {
2258 _null_check_tests.push(proj);
2259 Node* val = cmp->in(1);
2260 #ifdef _LP64
2261 if (val->bottom_type()->isa_narrowoop() &&
2262 !Matcher::narrow_oop_use_complex_address()) {
2263 //
2264 // Look for DecodeN node which should be pinned to orig_proj.
2265 // On platforms (Sparc) which can not handle 2 adds
2266 // in addressing mode we have to keep a DecodeN node and
2267 // use it to do implicit NULL check in address.
2268 //
2269 // DecodeN node was pinned to non-null path (orig_proj) during
2270 // CastPP transformation in final_graph_reshaping_impl().
2271 //
2272 uint cnt = orig_proj->outcnt();
2273 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2274 Node* d = orig_proj->raw_out(i);
2275 if (d->is_DecodeN() && d->in(1) == val) {
2276 val = d;
2277 val->set_req(0, NULL); // Unpin now.
2278 // Mark this as special case to distinguish from
2279 // a regular case: CmpP(DecodeN, NULL).
2280 val = (Node*)(((intptr_t)val) | 1);
2281 break;
2282 }
2283 }
2284 }
2285 #endif
2286 _null_check_tests.push(val);
2287 }
2288 }
2289 }
2290 }
2291
2292 //---------------------------validate_null_checks------------------------------
2293 // Its possible that the value being NULL checked is not the root of a match
2294 // tree. If so, I cannot use the value in an implicit null check.
2295 void Matcher::validate_null_checks( ) {
2296 uint cnt = _null_check_tests.size();
2297 for( uint i=0; i < cnt; i+=2 ) {
2298 Node *test = _null_check_tests[i];
2299 Node *val = _null_check_tests[i+1];
2300 bool is_decoden = ((intptr_t)val) & 1;
2301 val = (Node*)(((intptr_t)val) & ~1);
2302 if (has_new_node(val)) {
2303 Node* new_val = new_node(val);
2304 if (is_decoden) {
2305 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2306 // Note: new_val may have a control edge if
2307 // the original ideal node DecodeN was matched before
2308 // it was unpinned in Matcher::collect_null_checks().
2309 // Unpin the mach node and mark it.
2310 new_val->set_req(0, NULL);
2311 new_val = (Node*)(((intptr_t)new_val) | 1);
2312 }
2313 // Is a match-tree root, so replace with the matched value
2314 _null_check_tests.map(i+1, new_val);
2315 } else {
2316 // Yank from candidate list
2317 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2318 _null_check_tests.map(i,_null_check_tests[--cnt]);
2319 _null_check_tests.pop();
2320 _null_check_tests.pop();
2321 i-=2;
2322 }
2323 }
2324 }
2325
2326 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2327 // atomic instruction acting as a store_load barrier without any
2328 // intervening volatile load, and thus we don't need a barrier here.
2329 // We retain the Node to act as a compiler ordering barrier.
2330 bool Matcher::post_store_load_barrier(const Node* vmb) {
2331 Compile* C = Compile::current();
2332 assert(vmb->is_MemBar(), "");
2333 assert(vmb->Opcode() != Op_MemBarAcquire, "");
2334 const MemBarNode* membar = vmb->as_MemBar();
2335
2336 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2337 Node* ctrl = NULL;
2338 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2339 Node* p = membar->fast_out(i);
2340 assert(p->is_Proj(), "only projections here");
2341 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2342 !C->node_arena()->contains(p)) { // Unmatched old-space only
2343 ctrl = p;
2344 break;
2345 }
2346 }
2347 assert((ctrl != NULL), "missing control projection");
2348
2349 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2350 Node *x = ctrl->fast_out(j);
2351 int xop = x->Opcode();
2352
2353 // We don't need current barrier if we see another or a lock
2354 // before seeing volatile load.
2355 //
2356 // Op_Fastunlock previously appeared in the Op_* list below.
2357 // With the advent of 1-0 lock operations we're no longer guaranteed
2358 // that a monitor exit operation contains a serializing instruction.
2359
2360 if (xop == Op_MemBarVolatile ||
2361 xop == Op_CompareAndSwapL ||
2362 xop == Op_CompareAndSwapP ||
2363 xop == Op_CompareAndSwapN ||
2364 xop == Op_CompareAndSwapI) {
2365 return true;
2366 }
2367
2368 // Op_FastLock previously appeared in the Op_* list above.
2369 // With biased locking we're no longer guaranteed that a monitor
2370 // enter operation contains a serializing instruction.
2371 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2372 return true;
2373 }
2374
2375 if (x->is_MemBar()) {
2376 // We must retain this membar if there is an upcoming volatile
2377 // load, which will be followed by acquire membar.
2378 if (xop == Op_MemBarAcquire) {
2379 return false;
2380 } else {
2381 // For other kinds of barriers, check by pretending we
2382 // are them, and seeing if we can be removed.
2383 return post_store_load_barrier(x->as_MemBar());
2384 }
2385 }
2386
2387 // probably not necessary to check for these
2388 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2389 return false;
2390 }
2391 }
2392 return false;
2393 }
2394
2395 //=============================================================================
2396 //---------------------------State---------------------------------------------
2397 State::State(void) {
2398 #ifdef ASSERT
2399 _id = 0;
2400 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2401 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2402 //memset(_cost, -1, sizeof(_cost));
2403 //memset(_rule, -1, sizeof(_rule));
2404 #endif
2405 memset(_valid, 0, sizeof(_valid));
2406 }
2407
2408 #ifdef ASSERT
2409 State::~State() {
2410 _id = 99;
2411 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2412 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2413 memset(_cost, -3, sizeof(_cost));
2414 memset(_rule, -3, sizeof(_rule));
2415 }
2416 #endif
2417
2418 #ifndef PRODUCT
2419 //---------------------------dump----------------------------------------------
2420 void State::dump() {
2421 tty->print("\n");
2422 dump(0);
2423 }
2424
2425 void State::dump(int depth) {
2426 for( int j = 0; j < depth; j++ )
2427 tty->print(" ");
2428 tty->print("--N: ");
2429 _leaf->dump();
2430 uint i;
2431 for( i = 0; i < _LAST_MACH_OPER; i++ )
2432 // Check for valid entry
2433 if( valid(i) ) {
2434 for( int j = 0; j < depth; j++ )
2435 tty->print(" ");
2436 assert(_cost[i] != max_juint, "cost must be a valid value");
2437 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2438 tty->print_cr("%s %d %s",
2439 ruleName[i], _cost[i], ruleName[_rule[i]] );
2440 }
2441 tty->print_cr("");
2442
2443 for( i=0; i<2; i++ )
2444 if( _kids[i] )
2445 _kids[i]->dump(depth+1);
2446 }
2447 #endif