1 /*
2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/safepointMechanism.inline.hpp"
39 #include "runtime/sharedRuntime.hpp"
40
41 #define __ _masm->
42
43
44 //------------------------------------------------------------
45
46
47 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
48 if (opr->is_constant()) {
49 LIR_Const* constant = opr->as_constant_ptr();
50 switch (constant->type()) {
51 case T_INT: {
52 jint value = constant->as_jint();
53 return Assembler::is_simm13(value);
54 }
55
56 default:
57 return false;
58 }
59 }
60 return false;
61 }
62
63
64 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
65 switch (op->code()) {
66 case lir_null_check:
67 return true;
68
69
70 case lir_add:
71 case lir_ushr:
72 case lir_shr:
73 case lir_shl:
74 // integer shifts and adds are always one instruction
75 return op->result_opr()->is_single_cpu();
76
77
78 case lir_move: {
79 LIR_Op1* op1 = op->as_Op1();
80 LIR_Opr src = op1->in_opr();
81 LIR_Opr dst = op1->result_opr();
82
83 if (src == dst) {
84 NEEDS_CLEANUP;
85 // this works around a problem where moves with the same src and dst
86 // end up in the delay slot and then the assembler swallows the mov
87 // since it has no effect and then it complains because the delay slot
88 // is empty. returning false stops the optimizer from putting this in
89 // the delay slot
90 return false;
91 }
92
93 // don't put moves involving oops into the delay slot since the VerifyOops code
94 // will make it much larger than a single instruction.
95 if (VerifyOops) {
96 return false;
97 }
98
99 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
100 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
101 return false;
102 }
103
104 if (UseCompressedOops) {
105 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
106 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
107 }
108
109 if (UseCompressedClassPointers) {
110 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
111 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
112 }
113
114 if (dst->is_register()) {
115 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
116 return !PatchALot;
117 } else if (src->is_single_stack()) {
118 return true;
119 }
120 }
121
122 if (src->is_register()) {
123 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
124 return !PatchALot;
125 } else if (dst->is_single_stack()) {
126 return true;
127 }
128 }
129
130 if (dst->is_register() &&
131 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
132 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
133 return true;
134 }
135
136 return false;
137 }
138
139 default:
140 return false;
141 }
142 ShouldNotReachHere();
143 }
144
145
146 LIR_Opr LIR_Assembler::receiverOpr() {
147 return FrameMap::O0_oop_opr;
148 }
149
150
151 LIR_Opr LIR_Assembler::osrBufferPointer() {
152 return FrameMap::I0_opr;
153 }
154
155
156 int LIR_Assembler::initial_frame_size_in_bytes() const {
157 return in_bytes(frame_map()->framesize_in_bytes());
158 }
159
160
161 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
162 // we fetch the class of the receiver (O0) and compare it with the cached class.
163 // If they do not match we jump to slow case.
164 int LIR_Assembler::check_icache() {
165 int offset = __ offset();
166 __ inline_cache_check(O0, G5_inline_cache_reg);
167 return offset;
168 }
169
170
171 void LIR_Assembler::osr_entry() {
172 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
173 //
174 // 1. Create a new compiled activation.
175 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
176 // at the osr_bci; it is not initialized.
177 // 3. Jump to the continuation address in compiled code to resume execution.
178
179 // OSR entry point
180 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
181 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
182 ValueStack* entry_state = osr_entry->end()->state();
183 int number_of_locks = entry_state->locks_size();
184
185 // Create a frame for the compiled activation.
186 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
187
188 // OSR buffer is
189 //
190 // locals[nlocals-1..0]
191 // monitors[number_of_locks-1..0]
192 //
193 // locals is a direct copy of the interpreter frame so in the osr buffer
194 // so first slot in the local array is the last local from the interpreter
195 // and last slot is local[0] (receiver) from the interpreter
196 //
197 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
198 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
199 // in the interpreter frame (the method lock if a sync method)
200
201 // Initialize monitors in the compiled activation.
202 // I0: pointer to osr buffer
203 //
204 // All other registers are dead at this point and the locals will be
205 // copied into place by code emitted in the IR.
206
207 Register OSR_buf = osrBufferPointer()->as_register();
208 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
209 int monitor_offset = BytesPerWord * method()->max_locals() +
210 (2 * BytesPerWord) * (number_of_locks - 1);
211 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
212 // the OSR buffer using 2 word entries: first the lock and then
213 // the oop.
214 for (int i = 0; i < number_of_locks; i++) {
215 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
216 #ifdef ASSERT
217 // verify the interpreter's monitor has a non-null object
218 {
219 Label L;
220 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
221 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
222 __ stop("locked object is NULL");
223 __ bind(L);
224 }
225 #endif // ASSERT
226 // Copy the lock field into the compiled activation.
227 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
228 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
229 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
230 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
231 }
232 }
233 }
234
235
236 // --------------------------------------------------------------------------------------------
237
238 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
239 if (!GenerateSynchronizationCode) return;
240
241 Register obj_reg = obj_opr->as_register();
242 Register lock_reg = lock_opr->as_register();
243
244 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
245 Register reg = mon_addr.base();
246 int offset = mon_addr.disp();
247 // compute pointer to BasicLock
248 if (mon_addr.is_simm13()) {
249 __ add(reg, offset, lock_reg);
250 }
251 else {
252 __ set(offset, lock_reg);
253 __ add(reg, lock_reg, lock_reg);
254 }
255 // unlock object
256 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
257 // _slow_case_stubs->append(slow_case);
258 // temporary fix: must be created after exceptionhandler, therefore as call stub
259 _slow_case_stubs->append(slow_case);
260 if (UseFastLocking) {
261 // try inlined fast unlocking first, revert to slow locking if it fails
262 // note: lock_reg points to the displaced header since the displaced header offset is 0!
263 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
264 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
265 } else {
266 // always do slow unlocking
267 // note: the slow unlocking code could be inlined here, however if we use
268 // slow unlocking, speed doesn't matter anyway and this solution is
269 // simpler and requires less duplicated code - additionally, the
270 // slow unlocking code is the same in either case which simplifies
271 // debugging
272 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
273 __ delayed()->nop();
274 }
275 // done
276 __ bind(*slow_case->continuation());
277 }
278
279
280 int LIR_Assembler::emit_exception_handler() {
281 // if the last instruction is a call (typically to do a throw which
282 // is coming at the end after block reordering) the return address
283 // must still point into the code area in order to avoid assertion
284 // failures when searching for the corresponding bci => add a nop
285 // (was bug 5/14/1999 - gri)
286 __ nop();
287
288 // generate code for exception handler
289 ciMethod* method = compilation()->method();
290
291 address handler_base = __ start_a_stub(exception_handler_size());
292
293 if (handler_base == NULL) {
294 // not enough space left for the handler
295 bailout("exception handler overflow");
296 return -1;
297 }
298
299 int offset = code_offset();
300
301 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
302 __ delayed()->nop();
303 __ should_not_reach_here();
304 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
305 __ end_a_stub();
306
307 return offset;
308 }
309
310
311 // Emit the code to remove the frame from the stack in the exception
312 // unwind path.
313 int LIR_Assembler::emit_unwind_handler() {
314 #ifndef PRODUCT
315 if (CommentedAssembly) {
316 _masm->block_comment("Unwind handler");
317 }
318 #endif
319
320 int offset = code_offset();
321
322 // Fetch the exception from TLS and clear out exception related thread state
323 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
324 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
325 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
326
327 __ bind(_unwind_handler_entry);
328 __ verify_not_null_oop(O0);
329 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
330 __ mov(O0, I0); // Preserve the exception
331 }
332
333 // Preform needed unlocking
334 MonitorExitStub* stub = NULL;
335 if (method()->is_synchronized()) {
336 monitor_address(0, FrameMap::I1_opr);
337 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
338 __ unlock_object(I3, I2, I1, *stub->entry());
339 __ bind(*stub->continuation());
340 }
341
342 if (compilation()->env()->dtrace_method_probes()) {
343 __ mov(G2_thread, O0);
344 __ save_thread(I1); // need to preserve thread in G2 across
345 // runtime call
346 metadata2reg(method()->constant_encoding(), O1);
347 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
348 __ delayed()->nop();
349 __ restore_thread(I1);
350 }
351
352 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
353 __ mov(I0, O0); // Restore the exception
354 }
355
356 // dispatch to the unwind logic
357 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
358 __ delayed()->nop();
359
360 // Emit the slow path assembly
361 if (stub != NULL) {
362 stub->emit_code(this);
363 }
364
365 return offset;
366 }
367
368
369 int LIR_Assembler::emit_deopt_handler() {
370 // if the last instruction is a call (typically to do a throw which
371 // is coming at the end after block reordering) the return address
372 // must still point into the code area in order to avoid assertion
373 // failures when searching for the corresponding bci => add a nop
374 // (was bug 5/14/1999 - gri)
375 __ nop();
376
377 // generate code for deopt handler
378 ciMethod* method = compilation()->method();
379 address handler_base = __ start_a_stub(deopt_handler_size());
380 if (handler_base == NULL) {
381 // not enough space left for the handler
382 bailout("deopt handler overflow");
383 return -1;
384 }
385
386 int offset = code_offset();
387 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
388 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
389 __ delayed()->nop();
390 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
391 __ end_a_stub();
392
393 return offset;
394 }
395
396
397 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
398 if (o == NULL) {
399 __ set(NULL_WORD, reg);
400 } else {
401 int oop_index = __ oop_recorder()->find_index(o);
402 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
403 RelocationHolder rspec = oop_Relocation::spec(oop_index);
404 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
405 }
406 }
407
408
409 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
410 // Allocate a new index in table to hold the object once it's been patched
411 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
412 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
413
414 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
415 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
416 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
417 // NULL will be dynamically patched later and the patched value may be large. We must
418 // therefore generate the sethi/add as a placeholders
419 __ patchable_set(addrlit, reg);
420
421 patching_epilog(patch, lir_patch_normal, reg, info);
422 }
423
424
425 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
426 __ set_metadata_constant(o, reg);
427 }
428
429 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
430 // Allocate a new index in table to hold the klass once it's been patched
431 int index = __ oop_recorder()->allocate_metadata_index(NULL);
432 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
433 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
434 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
435 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
436 // NULL will be dynamically patched later and the patched value may be large. We must
437 // therefore generate the sethi/add as a placeholders
438 __ patchable_set(addrlit, reg);
439
440 patching_epilog(patch, lir_patch_normal, reg, info);
441 }
442
443 void LIR_Assembler::emit_op3(LIR_Op3* op) {
444 switch (op->code()) {
445 case lir_idiv:
446 case lir_irem: // Both idiv & irem are handled after the switch (below).
447 break;
448 case lir_fmaf:
449 __ fmadd(FloatRegisterImpl::S,
450 op->in_opr1()->as_float_reg(),
451 op->in_opr2()->as_float_reg(),
452 op->in_opr3()->as_float_reg(),
453 op->result_opr()->as_float_reg());
454 return;
455 case lir_fmad:
456 __ fmadd(FloatRegisterImpl::D,
457 op->in_opr1()->as_double_reg(),
458 op->in_opr2()->as_double_reg(),
459 op->in_opr3()->as_double_reg(),
460 op->result_opr()->as_double_reg());
461 return;
462 default:
463 ShouldNotReachHere();
464 break;
465 }
466
467 // Handle idiv & irem:
468
469 Register Rdividend = op->in_opr1()->as_register();
470 Register Rdivisor = noreg;
471 Register Rscratch = op->in_opr3()->as_register();
472 Register Rresult = op->result_opr()->as_register();
473 int divisor = -1;
474
475 if (op->in_opr2()->is_register()) {
476 Rdivisor = op->in_opr2()->as_register();
477 } else {
478 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
479 assert(Assembler::is_simm13(divisor), "can only handle simm13");
480 }
481
482 assert(Rdividend != Rscratch, "");
483 assert(Rdivisor != Rscratch, "");
484 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
485
486 if (Rdivisor == noreg && is_power_of_2(divisor)) {
487 // convert division by a power of two into some shifts and logical operations
488 if (op->code() == lir_idiv) {
489 if (divisor == 2) {
490 __ srl(Rdividend, 31, Rscratch);
491 } else {
492 __ sra(Rdividend, 31, Rscratch);
493 __ and3(Rscratch, divisor - 1, Rscratch);
494 }
495 __ add(Rdividend, Rscratch, Rscratch);
496 __ sra(Rscratch, log2_intptr(divisor), Rresult);
497 return;
498 } else {
499 if (divisor == 2) {
500 __ srl(Rdividend, 31, Rscratch);
501 } else {
502 __ sra(Rdividend, 31, Rscratch);
503 __ and3(Rscratch, divisor - 1,Rscratch);
504 }
505 __ add(Rdividend, Rscratch, Rscratch);
506 __ andn(Rscratch, divisor - 1,Rscratch);
507 __ sub(Rdividend, Rscratch, Rresult);
508 return;
509 }
510 }
511
512 __ sra(Rdividend, 31, Rscratch);
513 __ wry(Rscratch);
514
515 add_debug_info_for_div0_here(op->info());
516
517 if (Rdivisor != noreg) {
518 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
519 } else {
520 assert(Assembler::is_simm13(divisor), "can only handle simm13");
521 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
522 }
523
524 Label skip;
525 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
526 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
527 __ bind(skip);
528
529 if (op->code() == lir_irem) {
530 if (Rdivisor != noreg) {
531 __ smul(Rscratch, Rdivisor, Rscratch);
532 } else {
533 __ smul(Rscratch, divisor, Rscratch);
534 }
535 __ sub(Rdividend, Rscratch, Rresult);
536 }
537 }
538
539
540 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
541 #ifdef ASSERT
542 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
543 if (op->block() != NULL) _branch_target_blocks.append(op->block());
544 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
545 #endif
546 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
547
548 if (op->cond() == lir_cond_always) {
549 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
550 } else if (op->code() == lir_cond_float_branch) {
551 assert(op->ublock() != NULL, "must have unordered successor");
552 bool is_unordered = (op->ublock() == op->block());
553 Assembler::Condition acond;
554 switch (op->cond()) {
555 case lir_cond_equal: acond = Assembler::f_equal; break;
556 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
557 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
558 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
559 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
560 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
561 default : ShouldNotReachHere();
562 }
563 __ fb( acond, false, Assembler::pn, *(op->label()));
564 } else {
565 assert (op->code() == lir_branch, "just checking");
566
567 Assembler::Condition acond;
568 switch (op->cond()) {
569 case lir_cond_equal: acond = Assembler::equal; break;
570 case lir_cond_notEqual: acond = Assembler::notEqual; break;
571 case lir_cond_less: acond = Assembler::less; break;
572 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
573 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
574 case lir_cond_greater: acond = Assembler::greater; break;
575 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
576 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
577 default: ShouldNotReachHere();
578 };
579
580 // sparc has different condition codes for testing 32-bit
581 // vs. 64-bit values. We could always test xcc is we could
582 // guarantee that 32-bit loads always sign extended but that isn't
583 // true and since sign extension isn't free, it would impose a
584 // slight cost.
585 if (op->type() == T_INT) {
586 __ br(acond, false, Assembler::pn, *(op->label()));
587 } else
588 __ brx(acond, false, Assembler::pn, *(op->label()));
589 }
590 // The peephole pass fills the delay slot
591 }
592
593
594 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
595 Bytecodes::Code code = op->bytecode();
596 LIR_Opr dst = op->result_opr();
597
598 switch(code) {
599 case Bytecodes::_i2l: {
600 Register rlo = dst->as_register_lo();
601 Register rhi = dst->as_register_hi();
602 Register rval = op->in_opr()->as_register();
603 __ sra(rval, 0, rlo);
604 break;
605 }
606 case Bytecodes::_i2d:
607 case Bytecodes::_i2f: {
608 bool is_double = (code == Bytecodes::_i2d);
609 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
610 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
611 FloatRegister rsrc = op->in_opr()->as_float_reg();
612 if (rsrc != rdst) {
613 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
614 }
615 __ fitof(w, rdst, rdst);
616 break;
617 }
618 case Bytecodes::_f2i:{
619 FloatRegister rsrc = op->in_opr()->as_float_reg();
620 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
621 Label L;
622 // result must be 0 if value is NaN; test by comparing value to itself
623 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
624 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
625 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
626 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
627 // move integer result from float register to int register
628 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
629 __ bind (L);
630 break;
631 }
632 case Bytecodes::_l2i: {
633 Register rlo = op->in_opr()->as_register_lo();
634 Register rhi = op->in_opr()->as_register_hi();
635 Register rdst = dst->as_register();
636 __ sra(rlo, 0, rdst);
637 break;
638 }
639 case Bytecodes::_d2f:
640 case Bytecodes::_f2d: {
641 bool is_double = (code == Bytecodes::_f2d);
642 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
643 LIR_Opr val = op->in_opr();
644 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
645 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
646 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
647 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
648 __ ftof(vw, dw, rval, rdst);
649 break;
650 }
651 case Bytecodes::_i2s:
652 case Bytecodes::_i2b: {
653 Register rval = op->in_opr()->as_register();
654 Register rdst = dst->as_register();
655 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
656 __ sll (rval, shift, rdst);
657 __ sra (rdst, shift, rdst);
658 break;
659 }
660 case Bytecodes::_i2c: {
661 Register rval = op->in_opr()->as_register();
662 Register rdst = dst->as_register();
663 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
664 __ sll (rval, shift, rdst);
665 __ srl (rdst, shift, rdst);
666 break;
667 }
668
669 default: ShouldNotReachHere();
670 }
671 }
672
673
674 void LIR_Assembler::align_call(LIR_Code) {
675 // do nothing since all instructions are word aligned on sparc
676 }
677
678
679 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
680 __ call(op->addr(), rtype);
681 // The peephole pass fills the delay slot, add_call_info is done in
682 // LIR_Assembler::emit_delay.
683 }
684
685
686 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
687 __ ic_call(op->addr(), false);
688 // The peephole pass fills the delay slot, add_call_info is done in
689 // LIR_Assembler::emit_delay.
690 }
691
692
693 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
694 add_debug_info_for_null_check_here(op->info());
695 __ load_klass(O0, G3_scratch);
696 if (Assembler::is_simm13(op->vtable_offset())) {
697 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
698 } else {
699 // This will generate 2 instructions
700 __ set(op->vtable_offset(), G5_method);
701 // ld_ptr, set_hi, set
702 __ ld_ptr(G3_scratch, G5_method, G5_method);
703 }
704 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
705 __ callr(G3_scratch, G0);
706 // the peephole pass fills the delay slot
707 }
708
709 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
710 int store_offset;
711 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
712 assert(base != O7, "destroying register");
713 assert(!unaligned, "can't handle this");
714 // for offsets larger than a simm13 we setup the offset in O7
715 __ set(offset, O7);
716 store_offset = store(from_reg, base, O7, type, wide);
717 } else {
718 if (type == T_ARRAY || type == T_OBJECT) {
719 __ verify_oop(from_reg->as_register());
720 }
721 store_offset = code_offset();
722 switch (type) {
723 case T_BOOLEAN: // fall through
724 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
725 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
726 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
727 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
728 case T_LONG :
729 if (unaligned || PatchALot) {
730 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
731 assert(G3_scratch != base, "can't handle this");
732 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
733 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
734 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
735 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
736 } else {
737 __ stx(from_reg->as_register_lo(), base, offset);
738 }
739 break;
740 case T_ADDRESS:
741 case T_METADATA:
742 __ st_ptr(from_reg->as_register(), base, offset);
743 break;
744 case T_ARRAY : // fall through
745 case T_OBJECT:
746 {
747 if (UseCompressedOops && !wide) {
748 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
749 store_offset = code_offset();
750 __ stw(G3_scratch, base, offset);
751 } else {
752 __ st_ptr(from_reg->as_register(), base, offset);
753 }
754 break;
755 }
756
757 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
758 case T_DOUBLE:
759 {
760 FloatRegister reg = from_reg->as_double_reg();
761 // split unaligned stores
762 if (unaligned || PatchALot) {
763 assert(Assembler::is_simm13(offset + 4), "must be");
764 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
765 __ stf(FloatRegisterImpl::S, reg, base, offset);
766 } else {
767 __ stf(FloatRegisterImpl::D, reg, base, offset);
768 }
769 break;
770 }
771 default : ShouldNotReachHere();
772 }
773 }
774 return store_offset;
775 }
776
777
778 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
779 if (type == T_ARRAY || type == T_OBJECT) {
780 __ verify_oop(from_reg->as_register());
781 }
782 int store_offset = code_offset();
783 switch (type) {
784 case T_BOOLEAN: // fall through
785 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
786 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
787 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
788 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
789 case T_LONG :
790 __ stx(from_reg->as_register_lo(), base, disp);
791 break;
792 case T_ADDRESS:
793 __ st_ptr(from_reg->as_register(), base, disp);
794 break;
795 case T_ARRAY : // fall through
796 case T_OBJECT:
797 {
798 if (UseCompressedOops && !wide) {
799 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
800 store_offset = code_offset();
801 __ stw(G3_scratch, base, disp);
802 } else {
803 __ st_ptr(from_reg->as_register(), base, disp);
804 }
805 break;
806 }
807 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
808 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
809 default : ShouldNotReachHere();
810 }
811 return store_offset;
812 }
813
814
815 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
816 int load_offset;
817 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
818 assert(base != O7, "destroying register");
819 assert(!unaligned, "can't handle this");
820 // for offsets larger than a simm13 we setup the offset in O7
821 __ set(offset, O7);
822 load_offset = load(base, O7, to_reg, type, wide);
823 } else {
824 load_offset = code_offset();
825 switch(type) {
826 case T_BOOLEAN: // fall through
827 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
828 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
829 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
830 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
831 case T_LONG :
832 if (!unaligned && !PatchALot) {
833 __ ldx(base, offset, to_reg->as_register_lo());
834 } else {
835 assert(base != to_reg->as_register_lo(), "can't handle this");
836 assert(O7 != to_reg->as_register_lo(), "can't handle this");
837 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
838 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
839 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
840 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
841 }
842 break;
843 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
844 case T_ADDRESS:
845 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
846 __ lduw(base, offset, to_reg->as_register());
847 __ decode_klass_not_null(to_reg->as_register());
848 } else
849 {
850 __ ld_ptr(base, offset, to_reg->as_register());
851 }
852 break;
853 case T_ARRAY : // fall through
854 case T_OBJECT:
855 {
856 if (UseCompressedOops && !wide) {
857 __ lduw(base, offset, to_reg->as_register());
858 __ decode_heap_oop(to_reg->as_register());
859 } else {
860 __ ld_ptr(base, offset, to_reg->as_register());
861 }
862 break;
863 }
864 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
865 case T_DOUBLE:
866 {
867 FloatRegister reg = to_reg->as_double_reg();
868 // split unaligned loads
869 if (unaligned || PatchALot) {
870 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
871 __ ldf(FloatRegisterImpl::S, base, offset, reg);
872 } else {
873 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
874 }
875 break;
876 }
877 default : ShouldNotReachHere();
878 }
879 if (type == T_ARRAY || type == T_OBJECT) {
880 __ verify_oop(to_reg->as_register());
881 }
882 }
883 return load_offset;
884 }
885
886
887 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
888 int load_offset = code_offset();
889 switch(type) {
890 case T_BOOLEAN: // fall through
891 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
892 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
893 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
894 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
895 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
896 case T_ARRAY : // fall through
897 case T_OBJECT:
898 {
899 if (UseCompressedOops && !wide) {
900 __ lduw(base, disp, to_reg->as_register());
901 __ decode_heap_oop(to_reg->as_register());
902 } else {
903 __ ld_ptr(base, disp, to_reg->as_register());
904 }
905 break;
906 }
907 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
908 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
909 case T_LONG :
910 __ ldx(base, disp, to_reg->as_register_lo());
911 break;
912 default : ShouldNotReachHere();
913 }
914 if (type == T_ARRAY || type == T_OBJECT) {
915 __ verify_oop(to_reg->as_register());
916 }
917 return load_offset;
918 }
919
920 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
921 LIR_Const* c = src->as_constant_ptr();
922 switch (c->type()) {
923 case T_INT:
924 case T_FLOAT: {
925 Register src_reg = O7;
926 int value = c->as_jint_bits();
927 if (value == 0) {
928 src_reg = G0;
929 } else {
930 __ set(value, O7);
931 }
932 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
933 __ stw(src_reg, addr.base(), addr.disp());
934 break;
935 }
936 case T_ADDRESS: {
937 Register src_reg = O7;
938 int value = c->as_jint_bits();
939 if (value == 0) {
940 src_reg = G0;
941 } else {
942 __ set(value, O7);
943 }
944 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
945 __ st_ptr(src_reg, addr.base(), addr.disp());
946 break;
947 }
948 case T_OBJECT: {
949 Register src_reg = O7;
950 jobject2reg(c->as_jobject(), src_reg);
951 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
952 __ st_ptr(src_reg, addr.base(), addr.disp());
953 break;
954 }
955 case T_LONG:
956 case T_DOUBLE: {
957 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
958
959 Register tmp = O7;
960 int value_lo = c->as_jint_lo_bits();
961 if (value_lo == 0) {
962 tmp = G0;
963 } else {
964 __ set(value_lo, O7);
965 }
966 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
967 int value_hi = c->as_jint_hi_bits();
968 if (value_hi == 0) {
969 tmp = G0;
970 } else {
971 __ set(value_hi, O7);
972 }
973 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
974 break;
975 }
976 default:
977 Unimplemented();
978 }
979 }
980
981
982 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
983 LIR_Const* c = src->as_constant_ptr();
984 LIR_Address* addr = dest->as_address_ptr();
985 Register base = addr->base()->as_pointer_register();
986 int offset = -1;
987
988 switch (c->type()) {
989 case T_INT:
990 case T_FLOAT:
991 case T_ADDRESS: {
992 LIR_Opr tmp = FrameMap::O7_opr;
993 int value = c->as_jint_bits();
994 if (value == 0) {
995 tmp = FrameMap::G0_opr;
996 } else if (Assembler::is_simm13(value)) {
997 __ set(value, O7);
998 }
999 if (addr->index()->is_valid()) {
1000 assert(addr->disp() == 0, "must be zero");
1001 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1002 } else {
1003 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1004 offset = store(tmp, base, addr->disp(), type, wide, false);
1005 }
1006 break;
1007 }
1008 case T_LONG:
1009 case T_DOUBLE: {
1010 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1011 assert(Assembler::is_simm13(addr->disp()) &&
1012 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1013
1014 LIR_Opr tmp = FrameMap::O7_opr;
1015 int value_lo = c->as_jint_lo_bits();
1016 if (value_lo == 0) {
1017 tmp = FrameMap::G0_opr;
1018 } else {
1019 __ set(value_lo, O7);
1020 }
1021 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1022 int value_hi = c->as_jint_hi_bits();
1023 if (value_hi == 0) {
1024 tmp = FrameMap::G0_opr;
1025 } else {
1026 __ set(value_hi, O7);
1027 }
1028 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1029 break;
1030 }
1031 case T_OBJECT: {
1032 jobject obj = c->as_jobject();
1033 LIR_Opr tmp;
1034 if (obj == NULL) {
1035 tmp = FrameMap::G0_opr;
1036 } else {
1037 tmp = FrameMap::O7_opr;
1038 jobject2reg(c->as_jobject(), O7);
1039 }
1040 // handle either reg+reg or reg+disp address
1041 if (addr->index()->is_valid()) {
1042 assert(addr->disp() == 0, "must be zero");
1043 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1044 } else {
1045 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1046 offset = store(tmp, base, addr->disp(), type, wide, false);
1047 }
1048
1049 break;
1050 }
1051 default:
1052 Unimplemented();
1053 }
1054 if (info != NULL) {
1055 assert(offset != -1, "offset should've been set");
1056 add_debug_info_for_null_check(offset, info);
1057 }
1058 }
1059
1060
1061 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1062 LIR_Const* c = src->as_constant_ptr();
1063 LIR_Opr to_reg = dest;
1064
1065 switch (c->type()) {
1066 case T_INT:
1067 case T_ADDRESS:
1068 {
1069 jint con = c->as_jint();
1070 if (to_reg->is_single_cpu()) {
1071 assert(patch_code == lir_patch_none, "no patching handled here");
1072 __ set(con, to_reg->as_register());
1073 } else {
1074 ShouldNotReachHere();
1075 assert(to_reg->is_single_fpu(), "wrong register kind");
1076
1077 __ set(con, O7);
1078 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1079 __ st(O7, temp_slot);
1080 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1081 }
1082 }
1083 break;
1084
1085 case T_LONG:
1086 {
1087 jlong con = c->as_jlong();
1088
1089 if (to_reg->is_double_cpu()) {
1090 __ set(con, to_reg->as_register_lo());
1091 } else if (to_reg->is_single_cpu()) {
1092 __ set(con, to_reg->as_register());
1093 } else {
1094 ShouldNotReachHere();
1095 assert(to_reg->is_double_fpu(), "wrong register kind");
1096 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1097 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1098 __ set(low(con), O7);
1099 __ st(O7, temp_slot_lo);
1100 __ set(high(con), O7);
1101 __ st(O7, temp_slot_hi);
1102 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1103 }
1104 }
1105 break;
1106
1107 case T_OBJECT:
1108 {
1109 if (patch_code == lir_patch_none) {
1110 jobject2reg(c->as_jobject(), to_reg->as_register());
1111 } else {
1112 jobject2reg_with_patching(to_reg->as_register(), info);
1113 }
1114 }
1115 break;
1116
1117 case T_METADATA:
1118 {
1119 if (patch_code == lir_patch_none) {
1120 metadata2reg(c->as_metadata(), to_reg->as_register());
1121 } else {
1122 klass2reg_with_patching(to_reg->as_register(), info);
1123 }
1124 }
1125 break;
1126
1127 case T_FLOAT:
1128 {
1129 address const_addr = __ float_constant(c->as_jfloat());
1130 if (const_addr == NULL) {
1131 bailout("const section overflow");
1132 break;
1133 }
1134 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1135 AddressLiteral const_addrlit(const_addr, rspec);
1136 if (to_reg->is_single_fpu()) {
1137 __ patchable_sethi(const_addrlit, O7);
1138 __ relocate(rspec);
1139 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1140
1141 } else {
1142 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1143
1144 __ set(const_addrlit, O7);
1145 __ ld(O7, 0, to_reg->as_register());
1146 }
1147 }
1148 break;
1149
1150 case T_DOUBLE:
1151 {
1152 address const_addr = __ double_constant(c->as_jdouble());
1153 if (const_addr == NULL) {
1154 bailout("const section overflow");
1155 break;
1156 }
1157 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1158
1159 if (to_reg->is_double_fpu()) {
1160 AddressLiteral const_addrlit(const_addr, rspec);
1161 __ patchable_sethi(const_addrlit, O7);
1162 __ relocate(rspec);
1163 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1164 } else {
1165 assert(to_reg->is_double_cpu(), "Must be a long register.");
1166 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1167 }
1168
1169 }
1170 break;
1171
1172 default:
1173 ShouldNotReachHere();
1174 }
1175 }
1176
1177 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1178 Register reg = addr->base()->as_pointer_register();
1179 LIR_Opr index = addr->index();
1180 if (index->is_illegal()) {
1181 return Address(reg, addr->disp());
1182 } else {
1183 assert (addr->disp() == 0, "unsupported address mode");
1184 return Address(reg, index->as_pointer_register());
1185 }
1186 }
1187
1188
1189 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1190 switch (type) {
1191 case T_INT:
1192 case T_FLOAT: {
1193 Register tmp = O7;
1194 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1195 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1196 __ lduw(from.base(), from.disp(), tmp);
1197 __ stw(tmp, to.base(), to.disp());
1198 break;
1199 }
1200 case T_OBJECT: {
1201 Register tmp = O7;
1202 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1203 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1204 __ ld_ptr(from.base(), from.disp(), tmp);
1205 __ st_ptr(tmp, to.base(), to.disp());
1206 break;
1207 }
1208 case T_LONG:
1209 case T_DOUBLE: {
1210 Register tmp = O7;
1211 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1212 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1213 __ lduw(from.base(), from.disp(), tmp);
1214 __ stw(tmp, to.base(), to.disp());
1215 __ lduw(from.base(), from.disp() + 4, tmp);
1216 __ stw(tmp, to.base(), to.disp() + 4);
1217 break;
1218 }
1219
1220 default:
1221 ShouldNotReachHere();
1222 }
1223 }
1224
1225
1226 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1227 Address base = as_Address(addr);
1228 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1229 }
1230
1231
1232 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1233 Address base = as_Address(addr);
1234 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1235 }
1236
1237
1238 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1239 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1240
1241 assert(type != T_METADATA, "load of metadata ptr not supported");
1242 LIR_Address* addr = src_opr->as_address_ptr();
1243 LIR_Opr to_reg = dest;
1244
1245 Register src = addr->base()->as_pointer_register();
1246 Register disp_reg = noreg;
1247 int disp_value = addr->disp();
1248 bool needs_patching = (patch_code != lir_patch_none);
1249
1250 if (addr->base()->type() == T_OBJECT) {
1251 __ verify_oop(src);
1252 }
1253
1254 PatchingStub* patch = NULL;
1255 if (needs_patching) {
1256 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1257 assert(!to_reg->is_double_cpu() ||
1258 patch_code == lir_patch_none ||
1259 patch_code == lir_patch_normal, "patching doesn't match register");
1260 }
1261
1262 if (addr->index()->is_illegal()) {
1263 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1264 if (needs_patching) {
1265 __ patchable_set(0, O7);
1266 } else {
1267 __ set(disp_value, O7);
1268 }
1269 disp_reg = O7;
1270 }
1271 } else if (unaligned || PatchALot) {
1272 __ add(src, addr->index()->as_pointer_register(), O7);
1273 src = O7;
1274 } else {
1275 disp_reg = addr->index()->as_pointer_register();
1276 assert(disp_value == 0, "can't handle 3 operand addresses");
1277 }
1278
1279 // remember the offset of the load. The patching_epilog must be done
1280 // before the call to add_debug_info, otherwise the PcDescs don't get
1281 // entered in increasing order.
1282 int offset = code_offset();
1283
1284 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1285 if (disp_reg == noreg) {
1286 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1287 } else {
1288 assert(!unaligned, "can't handle this");
1289 offset = load(src, disp_reg, to_reg, type, wide);
1290 }
1291
1292 if (patch != NULL) {
1293 patching_epilog(patch, patch_code, src, info);
1294 }
1295 if (info != NULL) add_debug_info_for_null_check(offset, info);
1296 }
1297
1298
1299 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1300 Address addr;
1301 if (src->is_single_word()) {
1302 addr = frame_map()->address_for_slot(src->single_stack_ix());
1303 } else if (src->is_double_word()) {
1304 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1305 }
1306
1307 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1308 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1309 }
1310
1311
1312 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1313 Address addr;
1314 if (dest->is_single_word()) {
1315 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1316 } else if (dest->is_double_word()) {
1317 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1318 }
1319 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1320 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1321 }
1322
1323
1324 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1325 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1326 if (from_reg->is_double_fpu()) {
1327 // double to double moves
1328 assert(to_reg->is_double_fpu(), "should match");
1329 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1330 } else {
1331 // float to float moves
1332 assert(to_reg->is_single_fpu(), "should match");
1333 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1334 }
1335 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1336 if (from_reg->is_double_cpu()) {
1337 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1338 } else if (to_reg->is_double_cpu()) {
1339 // int to int moves
1340 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1341 } else {
1342 // int to int moves
1343 __ mov(from_reg->as_register(), to_reg->as_register());
1344 }
1345 } else {
1346 ShouldNotReachHere();
1347 }
1348 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1349 __ verify_oop(to_reg->as_register());
1350 }
1351 }
1352
1353
1354 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1355 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1356 bool wide, bool unaligned) {
1357 assert(type != T_METADATA, "store of metadata ptr not supported");
1358 LIR_Address* addr = dest->as_address_ptr();
1359
1360 Register src = addr->base()->as_pointer_register();
1361 Register disp_reg = noreg;
1362 int disp_value = addr->disp();
1363 bool needs_patching = (patch_code != lir_patch_none);
1364
1365 if (addr->base()->is_oop_register()) {
1366 __ verify_oop(src);
1367 }
1368
1369 PatchingStub* patch = NULL;
1370 if (needs_patching) {
1371 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1372 assert(!from_reg->is_double_cpu() ||
1373 patch_code == lir_patch_none ||
1374 patch_code == lir_patch_normal, "patching doesn't match register");
1375 }
1376
1377 if (addr->index()->is_illegal()) {
1378 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1379 if (needs_patching) {
1380 __ patchable_set(0, O7);
1381 } else {
1382 __ set(disp_value, O7);
1383 }
1384 disp_reg = O7;
1385 }
1386 } else if (unaligned || PatchALot) {
1387 __ add(src, addr->index()->as_pointer_register(), O7);
1388 src = O7;
1389 } else {
1390 disp_reg = addr->index()->as_pointer_register();
1391 assert(disp_value == 0, "can't handle 3 operand addresses");
1392 }
1393
1394 // remember the offset of the store. The patching_epilog must be done
1395 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1396 // entered in increasing order.
1397 int offset;
1398
1399 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1400 if (disp_reg == noreg) {
1401 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1402 } else {
1403 assert(!unaligned, "can't handle this");
1404 offset = store(from_reg, src, disp_reg, type, wide);
1405 }
1406
1407 if (patch != NULL) {
1408 patching_epilog(patch, patch_code, src, info);
1409 }
1410
1411 if (info != NULL) add_debug_info_for_null_check(offset, info);
1412 }
1413
1414
1415 void LIR_Assembler::return_op(LIR_Opr result) {
1416 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1417 __ reserved_stack_check();
1418 }
1419 if (SafepointMechanism::uses_thread_local_poll()) {
1420 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0);
1421 } else {
1422 __ set((intptr_t)os::get_polling_page(), L0);
1423 }
1424 __ relocate(relocInfo::poll_return_type);
1425 __ ld_ptr(L0, 0, G0);
1426 __ ret();
1427 __ delayed()->restore();
1428 }
1429
1430
1431 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1432 if (SafepointMechanism::uses_thread_local_poll()) {
1433 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register());
1434 } else {
1435 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1436 }
1437 if (info != NULL) {
1438 add_debug_info_for_branch(info);
1439 }
1440 int offset = __ offset();
1441
1442 __ relocate(relocInfo::poll_type);
1443 __ ld_ptr(tmp->as_register(), 0, G0);
1444 return offset;
1445 }
1446
1447
1448 void LIR_Assembler::emit_static_call_stub() {
1449 address call_pc = __ pc();
1450 address stub = __ start_a_stub(call_stub_size());
1451 if (stub == NULL) {
1452 bailout("static call stub overflow");
1453 return;
1454 }
1455
1456 int start = __ offset();
1457 __ relocate(static_stub_Relocation::spec(call_pc));
1458
1459 __ set_metadata(NULL, G5);
1460 // must be set to -1 at code generation time
1461 AddressLiteral addrlit(-1);
1462 __ jump_to(addrlit, G3);
1463 __ delayed()->nop();
1464
1465 assert(__ offset() - start <= call_stub_size(), "stub too big");
1466 __ end_a_stub();
1467 }
1468
1469
1470 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1471 if (opr1->is_single_fpu()) {
1472 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1473 } else if (opr1->is_double_fpu()) {
1474 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1475 } else if (opr1->is_single_cpu()) {
1476 if (opr2->is_constant()) {
1477 switch (opr2->as_constant_ptr()->type()) {
1478 case T_INT:
1479 { jint con = opr2->as_constant_ptr()->as_jint();
1480 if (Assembler::is_simm13(con)) {
1481 __ cmp(opr1->as_register(), con);
1482 } else {
1483 __ set(con, O7);
1484 __ cmp(opr1->as_register(), O7);
1485 }
1486 }
1487 break;
1488
1489 case T_OBJECT:
1490 // there are only equal/notequal comparisions on objects
1491 { jobject con = opr2->as_constant_ptr()->as_jobject();
1492 if (con == NULL) {
1493 __ cmp(opr1->as_register(), 0);
1494 } else {
1495 jobject2reg(con, O7);
1496 __ cmp(opr1->as_register(), O7);
1497 }
1498 }
1499 break;
1500
1501 default:
1502 ShouldNotReachHere();
1503 break;
1504 }
1505 } else {
1506 if (opr2->is_address()) {
1507 LIR_Address * addr = opr2->as_address_ptr();
1508 BasicType type = addr->type();
1509 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1510 else __ ld(as_Address(addr), O7);
1511 __ cmp(opr1->as_register(), O7);
1512 } else {
1513 __ cmp(opr1->as_register(), opr2->as_register());
1514 }
1515 }
1516 } else if (opr1->is_double_cpu()) {
1517 Register xlo = opr1->as_register_lo();
1518 Register xhi = opr1->as_register_hi();
1519 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1520 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1521 __ orcc(xhi, G0, G0);
1522 } else if (opr2->is_register()) {
1523 Register ylo = opr2->as_register_lo();
1524 Register yhi = opr2->as_register_hi();
1525 __ cmp(xlo, ylo);
1526 } else {
1527 ShouldNotReachHere();
1528 }
1529 } else if (opr1->is_address()) {
1530 LIR_Address * addr = opr1->as_address_ptr();
1531 BasicType type = addr->type();
1532 assert (opr2->is_constant(), "Checking");
1533 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1534 else __ ld(as_Address(addr), O7);
1535 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1536 } else {
1537 ShouldNotReachHere();
1538 }
1539 }
1540
1541
1542 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1543 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1544 bool is_unordered_less = (code == lir_ucmp_fd2i);
1545 if (left->is_single_fpu()) {
1546 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1547 } else if (left->is_double_fpu()) {
1548 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1549 } else {
1550 ShouldNotReachHere();
1551 }
1552 } else if (code == lir_cmp_l2i) {
1553 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1554 } else {
1555 ShouldNotReachHere();
1556 }
1557 }
1558
1559
1560 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1561 Assembler::Condition acond;
1562 switch (condition) {
1563 case lir_cond_equal: acond = Assembler::equal; break;
1564 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1565 case lir_cond_less: acond = Assembler::less; break;
1566 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1567 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1568 case lir_cond_greater: acond = Assembler::greater; break;
1569 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1570 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1571 default: ShouldNotReachHere();
1572 };
1573
1574 if (opr1->is_constant() && opr1->type() == T_INT) {
1575 Register dest = result->as_register();
1576 // load up first part of constant before branch
1577 // and do the rest in the delay slot.
1578 if (!Assembler::is_simm13(opr1->as_jint())) {
1579 __ sethi(opr1->as_jint(), dest);
1580 }
1581 } else if (opr1->is_constant()) {
1582 const2reg(opr1, result, lir_patch_none, NULL);
1583 } else if (opr1->is_register()) {
1584 reg2reg(opr1, result);
1585 } else if (opr1->is_stack()) {
1586 stack2reg(opr1, result, result->type());
1587 } else {
1588 ShouldNotReachHere();
1589 }
1590 Label skip;
1591 if (type == T_INT) {
1592 __ br(acond, false, Assembler::pt, skip);
1593 } else {
1594 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1595 }
1596 if (opr1->is_constant() && opr1->type() == T_INT) {
1597 Register dest = result->as_register();
1598 if (Assembler::is_simm13(opr1->as_jint())) {
1599 __ delayed()->or3(G0, opr1->as_jint(), dest);
1600 } else {
1601 // the sethi has been done above, so just put in the low 10 bits
1602 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1603 }
1604 } else {
1605 // can't do anything useful in the delay slot
1606 __ delayed()->nop();
1607 }
1608 if (opr2->is_constant()) {
1609 const2reg(opr2, result, lir_patch_none, NULL);
1610 } else if (opr2->is_register()) {
1611 reg2reg(opr2, result);
1612 } else if (opr2->is_stack()) {
1613 stack2reg(opr2, result, result->type());
1614 } else {
1615 ShouldNotReachHere();
1616 }
1617 __ bind(skip);
1618 }
1619
1620
1621 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1622 assert(info == NULL, "unused on this code path");
1623 assert(left->is_register(), "wrong items state");
1624 assert(dest->is_register(), "wrong items state");
1625
1626 if (right->is_register()) {
1627 if (dest->is_float_kind()) {
1628
1629 FloatRegister lreg, rreg, res;
1630 FloatRegisterImpl::Width w;
1631 if (right->is_single_fpu()) {
1632 w = FloatRegisterImpl::S;
1633 lreg = left->as_float_reg();
1634 rreg = right->as_float_reg();
1635 res = dest->as_float_reg();
1636 } else {
1637 w = FloatRegisterImpl::D;
1638 lreg = left->as_double_reg();
1639 rreg = right->as_double_reg();
1640 res = dest->as_double_reg();
1641 }
1642
1643 switch (code) {
1644 case lir_add: __ fadd(w, lreg, rreg, res); break;
1645 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1646 case lir_mul: // fall through
1647 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1648 case lir_div: // fall through
1649 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1650 default: ShouldNotReachHere();
1651 }
1652
1653 } else if (dest->is_double_cpu()) {
1654 Register dst_lo = dest->as_register_lo();
1655 Register op1_lo = left->as_pointer_register();
1656 Register op2_lo = right->as_pointer_register();
1657
1658 switch (code) {
1659 case lir_add:
1660 __ add(op1_lo, op2_lo, dst_lo);
1661 break;
1662
1663 case lir_sub:
1664 __ sub(op1_lo, op2_lo, dst_lo);
1665 break;
1666
1667 default: ShouldNotReachHere();
1668 }
1669 } else {
1670 assert (right->is_single_cpu(), "Just Checking");
1671
1672 Register lreg = left->as_register();
1673 Register res = dest->as_register();
1674 Register rreg = right->as_register();
1675 switch (code) {
1676 case lir_add: __ add (lreg, rreg, res); break;
1677 case lir_sub: __ sub (lreg, rreg, res); break;
1678 case lir_mul: __ mulx (lreg, rreg, res); break;
1679 default: ShouldNotReachHere();
1680 }
1681 }
1682 } else {
1683 assert (right->is_constant(), "must be constant");
1684
1685 if (dest->is_single_cpu()) {
1686 Register lreg = left->as_register();
1687 Register res = dest->as_register();
1688 int simm13 = right->as_constant_ptr()->as_jint();
1689
1690 switch (code) {
1691 case lir_add: __ add (lreg, simm13, res); break;
1692 case lir_sub: __ sub (lreg, simm13, res); break;
1693 case lir_mul: __ mulx (lreg, simm13, res); break;
1694 default: ShouldNotReachHere();
1695 }
1696 } else {
1697 Register lreg = left->as_pointer_register();
1698 Register res = dest->as_register_lo();
1699 long con = right->as_constant_ptr()->as_jlong();
1700 assert(Assembler::is_simm13(con), "must be simm13");
1701
1702 switch (code) {
1703 case lir_add: __ add (lreg, (int)con, res); break;
1704 case lir_sub: __ sub (lreg, (int)con, res); break;
1705 case lir_mul: __ mulx (lreg, (int)con, res); break;
1706 default: ShouldNotReachHere();
1707 }
1708 }
1709 }
1710 }
1711
1712
1713 void LIR_Assembler::fpop() {
1714 // do nothing
1715 }
1716
1717
1718 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1719 switch (code) {
1720 case lir_tan: {
1721 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1722 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1723 break;
1724 }
1725 case lir_sqrt: {
1726 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1727 FloatRegister src_reg = value->as_double_reg();
1728 FloatRegister dst_reg = dest->as_double_reg();
1729 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1730 break;
1731 }
1732 case lir_abs: {
1733 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1734 FloatRegister src_reg = value->as_double_reg();
1735 FloatRegister dst_reg = dest->as_double_reg();
1736 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1737 break;
1738 }
1739 default: {
1740 ShouldNotReachHere();
1741 break;
1742 }
1743 }
1744 }
1745
1746
1747 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1748 if (right->is_constant()) {
1749 if (dest->is_single_cpu()) {
1750 int simm13 = right->as_constant_ptr()->as_jint();
1751 switch (code) {
1752 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1753 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1754 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1755 default: ShouldNotReachHere();
1756 }
1757 } else {
1758 long c = right->as_constant_ptr()->as_jlong();
1759 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1760 int simm13 = (int)c;
1761 switch (code) {
1762 case lir_logic_and:
1763 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1764 break;
1765
1766 case lir_logic_or:
1767 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1768 break;
1769
1770 case lir_logic_xor:
1771 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1772 break;
1773
1774 default: ShouldNotReachHere();
1775 }
1776 }
1777 } else {
1778 assert(right->is_register(), "right should be in register");
1779
1780 if (dest->is_single_cpu()) {
1781 switch (code) {
1782 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1783 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1784 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1785 default: ShouldNotReachHere();
1786 }
1787 } else {
1788 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1789 left->as_register_lo();
1790 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1791 right->as_register_lo();
1792
1793 switch (code) {
1794 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1795 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1796 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1797 default: ShouldNotReachHere();
1798 }
1799 }
1800 }
1801 }
1802
1803
1804 int LIR_Assembler::shift_amount(BasicType t) {
1805 int elem_size = type2aelembytes(t);
1806 switch (elem_size) {
1807 case 1 : return 0;
1808 case 2 : return 1;
1809 case 4 : return 2;
1810 case 8 : return 3;
1811 }
1812 ShouldNotReachHere();
1813 return -1;
1814 }
1815
1816
1817 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1818 assert(exceptionOop->as_register() == Oexception, "should match");
1819 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1820
1821 info->add_register_oop(exceptionOop);
1822
1823 // reuse the debug info from the safepoint poll for the throw op itself
1824 address pc_for_athrow = __ pc();
1825 int pc_for_athrow_offset = __ offset();
1826 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1827 __ set(pc_for_athrow, Oissuing_pc, rspec);
1828 add_call_info(pc_for_athrow_offset, info); // for exception handler
1829
1830 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1831 __ delayed()->nop();
1832 }
1833
1834
1835 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1836 assert(exceptionOop->as_register() == Oexception, "should match");
1837
1838 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1839 __ delayed()->nop();
1840 }
1841
1842 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1843 Register src = op->src()->as_register();
1844 Register dst = op->dst()->as_register();
1845 Register src_pos = op->src_pos()->as_register();
1846 Register dst_pos = op->dst_pos()->as_register();
1847 Register length = op->length()->as_register();
1848 Register tmp = op->tmp()->as_register();
1849 Register tmp2 = O7;
1850
1851 int flags = op->flags();
1852 ciArrayKlass* default_type = op->expected_type();
1853 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1854 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1855
1856 // higher 32bits must be null
1857 __ sra(dst_pos, 0, dst_pos);
1858 __ sra(src_pos, 0, src_pos);
1859 __ sra(length, 0, length);
1860
1861 // set up the arraycopy stub information
1862 ArrayCopyStub* stub = op->stub();
1863
1864 // always do stub if no type information is available. it's ok if
1865 // the known type isn't loaded since the code sanity checks
1866 // in debug mode and the type isn't required when we know the exact type
1867 // also check that the type is an array type.
1868 if (op->expected_type() == NULL) {
1869 __ mov(src, O0);
1870 __ mov(src_pos, O1);
1871 __ mov(dst, O2);
1872 __ mov(dst_pos, O3);
1873 __ mov(length, O4);
1874 address copyfunc_addr = StubRoutines::generic_arraycopy();
1875
1876 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1877 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1878 } else {
1879 #ifndef PRODUCT
1880 if (PrintC1Statistics) {
1881 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1882 __ inc_counter(counter, G1, G3);
1883 }
1884 #endif
1885 __ call_VM_leaf(tmp, copyfunc_addr);
1886 }
1887
1888 if (copyfunc_addr != NULL) {
1889 __ xor3(O0, -1, tmp);
1890 __ sub(length, tmp, length);
1891 __ add(src_pos, tmp, src_pos);
1892 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1893 __ delayed()->add(dst_pos, tmp, dst_pos);
1894 } else {
1895 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1896 __ delayed()->nop();
1897 }
1898 __ bind(*stub->continuation());
1899 return;
1900 }
1901
1902 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1903
1904 // make sure src and dst are non-null and load array length
1905 if (flags & LIR_OpArrayCopy::src_null_check) {
1906 __ tst(src);
1907 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1908 __ delayed()->nop();
1909 }
1910
1911 if (flags & LIR_OpArrayCopy::dst_null_check) {
1912 __ tst(dst);
1913 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1914 __ delayed()->nop();
1915 }
1916
1917 // If the compiler was not able to prove that exact type of the source or the destination
1918 // of the arraycopy is an array type, check at runtime if the source or the destination is
1919 // an instance type.
1920 if (flags & LIR_OpArrayCopy::type_check) {
1921 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1922 __ load_klass(dst, tmp);
1923 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1924 __ cmp(tmp2, Klass::_lh_neutral_value);
1925 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1926 __ delayed()->nop();
1927 }
1928
1929 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1930 __ load_klass(src, tmp);
1931 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1932 __ cmp(tmp2, Klass::_lh_neutral_value);
1933 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1934 __ delayed()->nop();
1935 }
1936 }
1937
1938 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1939 // test src_pos register
1940 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1941 __ delayed()->nop();
1942 }
1943
1944 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1945 // test dst_pos register
1946 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1947 __ delayed()->nop();
1948 }
1949
1950 if (flags & LIR_OpArrayCopy::length_positive_check) {
1951 // make sure length isn't negative
1952 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1953 __ delayed()->nop();
1954 }
1955
1956 if (flags & LIR_OpArrayCopy::src_range_check) {
1957 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1958 __ add(length, src_pos, tmp);
1959 __ cmp(tmp2, tmp);
1960 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1961 __ delayed()->nop();
1962 }
1963
1964 if (flags & LIR_OpArrayCopy::dst_range_check) {
1965 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1966 __ add(length, dst_pos, tmp);
1967 __ cmp(tmp2, tmp);
1968 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1969 __ delayed()->nop();
1970 }
1971
1972 int shift = shift_amount(basic_type);
1973
1974 if (flags & LIR_OpArrayCopy::type_check) {
1975 // We don't know the array types are compatible
1976 if (basic_type != T_OBJECT) {
1977 // Simple test for basic type arrays
1978 if (UseCompressedClassPointers) {
1979 // We don't need decode because we just need to compare
1980 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1981 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1982 __ cmp(tmp, tmp2);
1983 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1984 } else {
1985 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1986 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1987 __ cmp(tmp, tmp2);
1988 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1989 }
1990 __ delayed()->nop();
1991 } else {
1992 // For object arrays, if src is a sub class of dst then we can
1993 // safely do the copy.
1994 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1995
1996 Label cont, slow;
1997 assert_different_registers(tmp, tmp2, G3, G1);
1998
1999 __ load_klass(src, G3);
2000 __ load_klass(dst, G1);
2001
2002 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2003
2004 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2005 __ delayed()->nop();
2006
2007 __ cmp(G3, 0);
2008 if (copyfunc_addr != NULL) { // use stub if available
2009 // src is not a sub class of dst so we have to do a
2010 // per-element check.
2011 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2012 __ delayed()->nop();
2013
2014 __ bind(slow);
2015
2016 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2017 if ((flags & mask) != mask) {
2018 // Check that at least both of them object arrays.
2019 assert(flags & mask, "one of the two should be known to be an object array");
2020
2021 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2022 __ load_klass(src, tmp);
2023 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2024 __ load_klass(dst, tmp);
2025 }
2026 int lh_offset = in_bytes(Klass::layout_helper_offset());
2027
2028 __ lduw(tmp, lh_offset, tmp2);
2029
2030 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2031 __ set(objArray_lh, tmp);
2032 __ cmp(tmp, tmp2);
2033 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2034 __ delayed()->nop();
2035 }
2036
2037 Register src_ptr = O0;
2038 Register dst_ptr = O1;
2039 Register len = O2;
2040 Register chk_off = O3;
2041 Register super_k = O4;
2042
2043 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2044 if (shift == 0) {
2045 __ add(src_ptr, src_pos, src_ptr);
2046 } else {
2047 __ sll(src_pos, shift, tmp);
2048 __ add(src_ptr, tmp, src_ptr);
2049 }
2050
2051 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2052 if (shift == 0) {
2053 __ add(dst_ptr, dst_pos, dst_ptr);
2054 } else {
2055 __ sll(dst_pos, shift, tmp);
2056 __ add(dst_ptr, tmp, dst_ptr);
2057 }
2058 __ mov(length, len);
2059 __ load_klass(dst, tmp);
2060
2061 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2062 __ ld_ptr(tmp, ek_offset, super_k);
2063
2064 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2065 __ lduw(super_k, sco_offset, chk_off);
2066
2067 __ call_VM_leaf(tmp, copyfunc_addr);
2068
2069 #ifndef PRODUCT
2070 if (PrintC1Statistics) {
2071 Label failed;
2072 __ br_notnull_short(O0, Assembler::pn, failed);
2073 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2074 __ bind(failed);
2075 }
2076 #endif
2077
2078 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2079 __ delayed()->xor3(O0, -1, tmp);
2080
2081 #ifndef PRODUCT
2082 if (PrintC1Statistics) {
2083 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2084 }
2085 #endif
2086
2087 __ sub(length, tmp, length);
2088 __ add(src_pos, tmp, src_pos);
2089 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2090 __ delayed()->add(dst_pos, tmp, dst_pos);
2091
2092 __ bind(cont);
2093 } else {
2094 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2095 __ delayed()->nop();
2096 __ bind(cont);
2097 }
2098 }
2099 }
2100
2101 #ifdef ASSERT
2102 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2103 // Sanity check the known type with the incoming class. For the
2104 // primitive case the types must match exactly with src.klass and
2105 // dst.klass each exactly matching the default type. For the
2106 // object array case, if no type check is needed then either the
2107 // dst type is exactly the expected type and the src type is a
2108 // subtype which we can't check or src is the same array as dst
2109 // but not necessarily exactly of type default_type.
2110 Label known_ok, halt;
2111 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2112 if (UseCompressedClassPointers) {
2113 // tmp holds the default type. It currently comes uncompressed after the
2114 // load of a constant, so encode it.
2115 __ encode_klass_not_null(tmp);
2116 // load the raw value of the dst klass, since we will be comparing
2117 // uncompressed values directly.
2118 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2119 if (basic_type != T_OBJECT) {
2120 __ cmp(tmp, tmp2);
2121 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2122 // load the raw value of the src klass.
2123 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2124 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2125 } else {
2126 __ cmp(tmp, tmp2);
2127 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2128 __ delayed()->cmp(src, dst);
2129 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2130 __ delayed()->nop();
2131 }
2132 } else {
2133 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2134 if (basic_type != T_OBJECT) {
2135 __ cmp(tmp, tmp2);
2136 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2137 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2138 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2139 } else {
2140 __ cmp(tmp, tmp2);
2141 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2142 __ delayed()->cmp(src, dst);
2143 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2144 __ delayed()->nop();
2145 }
2146 }
2147 __ bind(halt);
2148 __ stop("incorrect type information in arraycopy");
2149 __ bind(known_ok);
2150 }
2151 #endif
2152
2153 #ifndef PRODUCT
2154 if (PrintC1Statistics) {
2155 address counter = Runtime1::arraycopy_count_address(basic_type);
2156 __ inc_counter(counter, G1, G3);
2157 }
2158 #endif
2159
2160 Register src_ptr = O0;
2161 Register dst_ptr = O1;
2162 Register len = O2;
2163
2164 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2165 if (shift == 0) {
2166 __ add(src_ptr, src_pos, src_ptr);
2167 } else {
2168 __ sll(src_pos, shift, tmp);
2169 __ add(src_ptr, tmp, src_ptr);
2170 }
2171
2172 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2173 if (shift == 0) {
2174 __ add(dst_ptr, dst_pos, dst_ptr);
2175 } else {
2176 __ sll(dst_pos, shift, tmp);
2177 __ add(dst_ptr, tmp, dst_ptr);
2178 }
2179
2180 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2181 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2182 const char *name;
2183 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2184
2185 // arraycopy stubs takes a length in number of elements, so don't scale it.
2186 __ mov(length, len);
2187 __ call_VM_leaf(tmp, entry);
2188
2189 __ bind(*stub->continuation());
2190 }
2191
2192
2193 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2194 if (dest->is_single_cpu()) {
2195 if (left->type() == T_OBJECT) {
2196 switch (code) {
2197 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2198 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2199 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2200 default: ShouldNotReachHere();
2201 }
2202 } else
2203 switch (code) {
2204 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2205 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2206 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2207 default: ShouldNotReachHere();
2208 }
2209 } else {
2210 switch (code) {
2211 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2212 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2213 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2214 default: ShouldNotReachHere();
2215 }
2216 }
2217 }
2218
2219
2220 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2221 if (left->type() == T_OBJECT) {
2222 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2223 Register l = left->as_register();
2224 Register d = dest->as_register_lo();
2225 switch (code) {
2226 case lir_shl: __ sllx (l, count, d); break;
2227 case lir_shr: __ srax (l, count, d); break;
2228 case lir_ushr: __ srlx (l, count, d); break;
2229 default: ShouldNotReachHere();
2230 }
2231 return;
2232 }
2233
2234 if (dest->is_single_cpu()) {
2235 count = count & 0x1F; // Java spec
2236 switch (code) {
2237 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2238 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2239 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2240 default: ShouldNotReachHere();
2241 }
2242 } else if (dest->is_double_cpu()) {
2243 count = count & 63; // Java spec
2244 switch (code) {
2245 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2246 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2247 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2248 default: ShouldNotReachHere();
2249 }
2250 } else {
2251 ShouldNotReachHere();
2252 }
2253 }
2254
2255
2256 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2257 assert(op->tmp1()->as_register() == G1 &&
2258 op->tmp2()->as_register() == G3 &&
2259 op->tmp3()->as_register() == G4 &&
2260 op->obj()->as_register() == O0 &&
2261 op->klass()->as_register() == G5, "must be");
2262 if (op->init_check()) {
2263 __ ldub(op->klass()->as_register(),
2264 in_bytes(InstanceKlass::init_state_offset()),
2265 op->tmp1()->as_register());
2266 add_debug_info_for_null_check_here(op->stub()->info());
2267 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2268 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2269 __ delayed()->nop();
2270 }
2271 __ allocate_object(op->obj()->as_register(),
2272 op->tmp1()->as_register(),
2273 op->tmp2()->as_register(),
2274 op->tmp3()->as_register(),
2275 op->header_size(),
2276 op->object_size(),
2277 op->klass()->as_register(),
2278 *op->stub()->entry());
2279 __ bind(*op->stub()->continuation());
2280 __ verify_oop(op->obj()->as_register());
2281 }
2282
2283
2284 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2285 assert(op->tmp1()->as_register() == G1 &&
2286 op->tmp2()->as_register() == G3 &&
2287 op->tmp3()->as_register() == G4 &&
2288 op->tmp4()->as_register() == O1 &&
2289 op->klass()->as_register() == G5, "must be");
2290
2291 __ signx(op->len()->as_register());
2292 if (UseSlowPath ||
2293 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2294 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2295 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2296 __ delayed()->nop();
2297 } else {
2298 __ allocate_array(op->obj()->as_register(),
2299 op->len()->as_register(),
2300 op->tmp1()->as_register(),
2301 op->tmp2()->as_register(),
2302 op->tmp3()->as_register(),
2303 arrayOopDesc::header_size(op->type()),
2304 type2aelembytes(op->type()),
2305 op->klass()->as_register(),
2306 *op->stub()->entry());
2307 }
2308 __ bind(*op->stub()->continuation());
2309 }
2310
2311
2312 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2313 ciMethodData *md, ciProfileData *data,
2314 Register recv, Register tmp1, Label* update_done) {
2315 uint i;
2316 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2317 Label next_test;
2318 // See if the receiver is receiver[n].
2319 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2320 mdo_offset_bias);
2321 __ ld_ptr(receiver_addr, tmp1);
2322 __ verify_klass_ptr(tmp1);
2323 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2324 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2325 mdo_offset_bias);
2326 __ ld_ptr(data_addr, tmp1);
2327 __ add(tmp1, DataLayout::counter_increment, tmp1);
2328 __ st_ptr(tmp1, data_addr);
2329 __ ba(*update_done);
2330 __ delayed()->nop();
2331 __ bind(next_test);
2332 }
2333
2334 // Didn't find receiver; find next empty slot and fill it in
2335 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2336 Label next_test;
2337 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2338 mdo_offset_bias);
2339 __ ld_ptr(recv_addr, tmp1);
2340 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2341 __ st_ptr(recv, recv_addr);
2342 __ set(DataLayout::counter_increment, tmp1);
2343 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2344 mdo_offset_bias);
2345 __ ba(*update_done);
2346 __ delayed()->nop();
2347 __ bind(next_test);
2348 }
2349 }
2350
2351
2352 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2353 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2354 md = method->method_data_or_null();
2355 assert(md != NULL, "Sanity");
2356 data = md->bci_to_data(bci);
2357 assert(data != NULL, "need data for checkcast");
2358 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2359 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2360 // The offset is large so bias the mdo by the base of the slot so
2361 // that the ld can use simm13s to reference the slots of the data
2362 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2363 }
2364 }
2365
2366 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2367 // we always need a stub for the failure case.
2368 CodeStub* stub = op->stub();
2369 Register obj = op->object()->as_register();
2370 Register k_RInfo = op->tmp1()->as_register();
2371 Register klass_RInfo = op->tmp2()->as_register();
2372 Register dst = op->result_opr()->as_register();
2373 Register Rtmp1 = op->tmp3()->as_register();
2374 ciKlass* k = op->klass();
2375
2376
2377 if (obj == k_RInfo) {
2378 k_RInfo = klass_RInfo;
2379 klass_RInfo = obj;
2380 }
2381
2382 ciMethodData* md;
2383 ciProfileData* data;
2384 int mdo_offset_bias = 0;
2385 if (op->should_profile()) {
2386 ciMethod* method = op->profiled_method();
2387 assert(method != NULL, "Should have method");
2388 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2389
2390 Label not_null;
2391 __ br_notnull_short(obj, Assembler::pn, not_null);
2392 Register mdo = k_RInfo;
2393 Register data_val = Rtmp1;
2394 metadata2reg(md->constant_encoding(), mdo);
2395 if (mdo_offset_bias > 0) {
2396 __ set(mdo_offset_bias, data_val);
2397 __ add(mdo, data_val, mdo);
2398 }
2399 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2400 __ ldub(flags_addr, data_val);
2401 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2402 __ stb(data_val, flags_addr);
2403 __ ba(*obj_is_null);
2404 __ delayed()->nop();
2405 __ bind(not_null);
2406 } else {
2407 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2408 __ delayed()->nop();
2409 }
2410
2411 Label profile_cast_failure, profile_cast_success;
2412 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2413 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2414
2415 // patching may screw with our temporaries on sparc,
2416 // so let's do it before loading the class
2417 if (k->is_loaded()) {
2418 metadata2reg(k->constant_encoding(), k_RInfo);
2419 } else {
2420 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2421 }
2422 assert(obj != k_RInfo, "must be different");
2423
2424 // get object class
2425 // not a safepoint as obj null check happens earlier
2426 __ load_klass(obj, klass_RInfo);
2427 if (op->fast_check()) {
2428 assert_different_registers(klass_RInfo, k_RInfo);
2429 __ cmp(k_RInfo, klass_RInfo);
2430 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2431 __ delayed()->nop();
2432 } else {
2433 bool need_slow_path = true;
2434 if (k->is_loaded()) {
2435 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2436 need_slow_path = false;
2437 // perform the fast part of the checking logic
2438 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2439 (need_slow_path ? success_target : NULL),
2440 failure_target, NULL,
2441 RegisterOrConstant(k->super_check_offset()));
2442 } else {
2443 // perform the fast part of the checking logic
2444 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2445 failure_target, NULL);
2446 }
2447 if (need_slow_path) {
2448 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2449 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2450 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2451 __ delayed()->nop();
2452 __ cmp(G3, 0);
2453 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2454 __ delayed()->nop();
2455 // Fall through to success case
2456 }
2457 }
2458
2459 if (op->should_profile()) {
2460 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2461 assert_different_registers(obj, mdo, recv, tmp1);
2462 __ bind(profile_cast_success);
2463 metadata2reg(md->constant_encoding(), mdo);
2464 if (mdo_offset_bias > 0) {
2465 __ set(mdo_offset_bias, tmp1);
2466 __ add(mdo, tmp1, mdo);
2467 }
2468 __ load_klass(obj, recv);
2469 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2470 // Jump over the failure case
2471 __ ba(*success);
2472 __ delayed()->nop();
2473 // Cast failure case
2474 __ bind(profile_cast_failure);
2475 metadata2reg(md->constant_encoding(), mdo);
2476 if (mdo_offset_bias > 0) {
2477 __ set(mdo_offset_bias, tmp1);
2478 __ add(mdo, tmp1, mdo);
2479 }
2480 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2481 __ ld_ptr(data_addr, tmp1);
2482 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2483 __ st_ptr(tmp1, data_addr);
2484 __ ba(*failure);
2485 __ delayed()->nop();
2486 }
2487 __ ba(*success);
2488 __ delayed()->nop();
2489 }
2490
2491 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2492 LIR_Code code = op->code();
2493 if (code == lir_store_check) {
2494 Register value = op->object()->as_register();
2495 Register array = op->array()->as_register();
2496 Register k_RInfo = op->tmp1()->as_register();
2497 Register klass_RInfo = op->tmp2()->as_register();
2498 Register Rtmp1 = op->tmp3()->as_register();
2499
2500 __ verify_oop(value);
2501 CodeStub* stub = op->stub();
2502 // check if it needs to be profiled
2503 ciMethodData* md;
2504 ciProfileData* data;
2505 int mdo_offset_bias = 0;
2506 if (op->should_profile()) {
2507 ciMethod* method = op->profiled_method();
2508 assert(method != NULL, "Should have method");
2509 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2510 }
2511 Label profile_cast_success, profile_cast_failure, done;
2512 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2513 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2514
2515 if (op->should_profile()) {
2516 Label not_null;
2517 __ br_notnull_short(value, Assembler::pn, not_null);
2518 Register mdo = k_RInfo;
2519 Register data_val = Rtmp1;
2520 metadata2reg(md->constant_encoding(), mdo);
2521 if (mdo_offset_bias > 0) {
2522 __ set(mdo_offset_bias, data_val);
2523 __ add(mdo, data_val, mdo);
2524 }
2525 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2526 __ ldub(flags_addr, data_val);
2527 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2528 __ stb(data_val, flags_addr);
2529 __ ba_short(done);
2530 __ bind(not_null);
2531 } else {
2532 __ br_null_short(value, Assembler::pn, done);
2533 }
2534 add_debug_info_for_null_check_here(op->info_for_exception());
2535 __ load_klass(array, k_RInfo);
2536 __ load_klass(value, klass_RInfo);
2537
2538 // get instance klass
2539 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2540 // perform the fast part of the checking logic
2541 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2542
2543 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2544 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2545 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2546 __ delayed()->nop();
2547 __ cmp(G3, 0);
2548 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2549 __ delayed()->nop();
2550 // fall through to the success case
2551
2552 if (op->should_profile()) {
2553 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2554 assert_different_registers(value, mdo, recv, tmp1);
2555 __ bind(profile_cast_success);
2556 metadata2reg(md->constant_encoding(), mdo);
2557 if (mdo_offset_bias > 0) {
2558 __ set(mdo_offset_bias, tmp1);
2559 __ add(mdo, tmp1, mdo);
2560 }
2561 __ load_klass(value, recv);
2562 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2563 __ ba_short(done);
2564 // Cast failure case
2565 __ bind(profile_cast_failure);
2566 metadata2reg(md->constant_encoding(), mdo);
2567 if (mdo_offset_bias > 0) {
2568 __ set(mdo_offset_bias, tmp1);
2569 __ add(mdo, tmp1, mdo);
2570 }
2571 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2572 __ ld_ptr(data_addr, tmp1);
2573 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2574 __ st_ptr(tmp1, data_addr);
2575 __ ba(*stub->entry());
2576 __ delayed()->nop();
2577 }
2578 __ bind(done);
2579 } else if (code == lir_checkcast) {
2580 Register obj = op->object()->as_register();
2581 Register dst = op->result_opr()->as_register();
2582 Label success;
2583 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2584 __ bind(success);
2585 __ mov(obj, dst);
2586 } else if (code == lir_instanceof) {
2587 Register obj = op->object()->as_register();
2588 Register dst = op->result_opr()->as_register();
2589 Label success, failure, done;
2590 emit_typecheck_helper(op, &success, &failure, &failure);
2591 __ bind(failure);
2592 __ set(0, dst);
2593 __ ba_short(done);
2594 __ bind(success);
2595 __ set(1, dst);
2596 __ bind(done);
2597 } else {
2598 ShouldNotReachHere();
2599 }
2600
2601 }
2602
2603
2604 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2605 if (op->code() == lir_cas_long) {
2606 assert(VM_Version::supports_cx8(), "wrong machine");
2607 Register addr = op->addr()->as_pointer_register();
2608 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2609 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2610 Register new_value_lo = op->new_value()->as_register_lo();
2611 Register new_value_hi = op->new_value()->as_register_hi();
2612 Register t1 = op->tmp1()->as_register();
2613 Register t2 = op->tmp2()->as_register();
2614 __ mov(cmp_value_lo, t1);
2615 __ mov(new_value_lo, t2);
2616 // perform the compare and swap operation
2617 __ casx(addr, t1, t2);
2618 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2619 // overwritten with the original value in "addr" and will be equal to t1.
2620 __ cmp(t1, t2);
2621 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2622 Register addr = op->addr()->as_pointer_register();
2623 Register cmp_value = op->cmp_value()->as_register();
2624 Register new_value = op->new_value()->as_register();
2625 Register t1 = op->tmp1()->as_register();
2626 Register t2 = op->tmp2()->as_register();
2627 __ mov(cmp_value, t1);
2628 __ mov(new_value, t2);
2629 if (op->code() == lir_cas_obj) {
2630 if (UseCompressedOops) {
2631 __ encode_heap_oop(t1);
2632 __ encode_heap_oop(t2);
2633 __ cas(addr, t1, t2);
2634 } else {
2635 __ cas_ptr(addr, t1, t2);
2636 }
2637 } else {
2638 __ cas(addr, t1, t2);
2639 }
2640 __ cmp(t1, t2);
2641 } else {
2642 Unimplemented();
2643 }
2644 }
2645
2646 void LIR_Assembler::set_24bit_FPU() {
2647 Unimplemented();
2648 }
2649
2650
2651 void LIR_Assembler::reset_FPU() {
2652 Unimplemented();
2653 }
2654
2655
2656 void LIR_Assembler::breakpoint() {
2657 __ breakpoint_trap();
2658 }
2659
2660
2661 void LIR_Assembler::push(LIR_Opr opr) {
2662 Unimplemented();
2663 }
2664
2665
2666 void LIR_Assembler::pop(LIR_Opr opr) {
2667 Unimplemented();
2668 }
2669
2670
2671 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2672 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2673 Register dst = dst_opr->as_register();
2674 Register reg = mon_addr.base();
2675 int offset = mon_addr.disp();
2676 // compute pointer to BasicLock
2677 if (mon_addr.is_simm13()) {
2678 __ add(reg, offset, dst);
2679 } else {
2680 __ set(offset, dst);
2681 __ add(dst, reg, dst);
2682 }
2683 }
2684
2685 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2686 assert(op->crc()->is_single_cpu(), "crc must be register");
2687 assert(op->val()->is_single_cpu(), "byte value must be register");
2688 assert(op->result_opr()->is_single_cpu(), "result must be register");
2689 Register crc = op->crc()->as_register();
2690 Register val = op->val()->as_register();
2691 Register table = op->result_opr()->as_register();
2692 Register res = op->result_opr()->as_register();
2693
2694 assert_different_registers(val, crc, table);
2695
2696 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2697 __ not1(crc);
2698 __ clruwu(crc);
2699 __ update_byte_crc32(crc, val, table);
2700 __ not1(crc);
2701
2702 __ mov(crc, res);
2703 }
2704
2705 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2706 Register obj = op->obj_opr()->as_register();
2707 Register hdr = op->hdr_opr()->as_register();
2708 Register lock = op->lock_opr()->as_register();
2709
2710 // obj may not be an oop
2711 if (op->code() == lir_lock) {
2712 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2713 if (UseFastLocking) {
2714 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2715 // add debug info for NullPointerException only if one is possible
2716 if (op->info() != NULL) {
2717 add_debug_info_for_null_check_here(op->info());
2718 }
2719 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2720 } else {
2721 // always do slow locking
2722 // note: the slow locking code could be inlined here, however if we use
2723 // slow locking, speed doesn't matter anyway and this solution is
2724 // simpler and requires less duplicated code - additionally, the
2725 // slow locking code is the same in either case which simplifies
2726 // debugging
2727 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2728 __ delayed()->nop();
2729 }
2730 } else {
2731 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2732 if (UseFastLocking) {
2733 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2734 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2735 } else {
2736 // always do slow unlocking
2737 // note: the slow unlocking code could be inlined here, however if we use
2738 // slow unlocking, speed doesn't matter anyway and this solution is
2739 // simpler and requires less duplicated code - additionally, the
2740 // slow unlocking code is the same in either case which simplifies
2741 // debugging
2742 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2743 __ delayed()->nop();
2744 }
2745 }
2746 __ bind(*op->stub()->continuation());
2747 }
2748
2749
2750 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2751 ciMethod* method = op->profiled_method();
2752 int bci = op->profiled_bci();
2753 ciMethod* callee = op->profiled_callee();
2754
2755 // Update counter for all call types
2756 ciMethodData* md = method->method_data_or_null();
2757 assert(md != NULL, "Sanity");
2758 ciProfileData* data = md->bci_to_data(bci);
2759 assert(data->is_CounterData(), "need CounterData for calls");
2760 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2761 Register mdo = op->mdo()->as_register();
2762 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2763 Register tmp1 = op->tmp1()->as_register_lo();
2764 metadata2reg(md->constant_encoding(), mdo);
2765 int mdo_offset_bias = 0;
2766 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2767 data->size_in_bytes())) {
2768 // The offset is large so bias the mdo by the base of the slot so
2769 // that the ld can use simm13s to reference the slots of the data
2770 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2771 __ set(mdo_offset_bias, O7);
2772 __ add(mdo, O7, mdo);
2773 }
2774
2775 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2776 Bytecodes::Code bc = method->java_code_at_bci(bci);
2777 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2778 // Perform additional virtual call profiling for invokevirtual and
2779 // invokeinterface bytecodes
2780 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2781 !callee_is_static && // required for optimized MH invokes
2782 C1ProfileVirtualCalls) {
2783 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2784 Register recv = op->recv()->as_register();
2785 assert_different_registers(mdo, tmp1, recv);
2786 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2787 ciKlass* known_klass = op->known_holder();
2788 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2789 // We know the type that will be seen at this call site; we can
2790 // statically update the MethodData* rather than needing to do
2791 // dynamic tests on the receiver type
2792
2793 // NOTE: we should probably put a lock around this search to
2794 // avoid collisions by concurrent compilations
2795 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2796 uint i;
2797 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2798 ciKlass* receiver = vc_data->receiver(i);
2799 if (known_klass->equals(receiver)) {
2800 Address data_addr(mdo, md->byte_offset_of_slot(data,
2801 VirtualCallData::receiver_count_offset(i)) -
2802 mdo_offset_bias);
2803 __ ld_ptr(data_addr, tmp1);
2804 __ add(tmp1, DataLayout::counter_increment, tmp1);
2805 __ st_ptr(tmp1, data_addr);
2806 return;
2807 }
2808 }
2809
2810 // Receiver type not found in profile data; select an empty slot
2811
2812 // Note that this is less efficient than it should be because it
2813 // always does a write to the receiver part of the
2814 // VirtualCallData rather than just the first time
2815 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2816 ciKlass* receiver = vc_data->receiver(i);
2817 if (receiver == NULL) {
2818 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2819 mdo_offset_bias);
2820 metadata2reg(known_klass->constant_encoding(), tmp1);
2821 __ st_ptr(tmp1, recv_addr);
2822 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2823 mdo_offset_bias);
2824 __ ld_ptr(data_addr, tmp1);
2825 __ add(tmp1, DataLayout::counter_increment, tmp1);
2826 __ st_ptr(tmp1, data_addr);
2827 return;
2828 }
2829 }
2830 } else {
2831 __ load_klass(recv, recv);
2832 Label update_done;
2833 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2834 // Receiver did not match any saved receiver and there is no empty row for it.
2835 // Increment total counter to indicate polymorphic case.
2836 __ ld_ptr(counter_addr, tmp1);
2837 __ add(tmp1, DataLayout::counter_increment, tmp1);
2838 __ st_ptr(tmp1, counter_addr);
2839
2840 __ bind(update_done);
2841 }
2842 } else {
2843 // Static call
2844 __ ld_ptr(counter_addr, tmp1);
2845 __ add(tmp1, DataLayout::counter_increment, tmp1);
2846 __ st_ptr(tmp1, counter_addr);
2847 }
2848 }
2849
2850 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2851 Register obj = op->obj()->as_register();
2852 Register tmp1 = op->tmp()->as_pointer_register();
2853 Register tmp2 = G1;
2854 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2855 ciKlass* exact_klass = op->exact_klass();
2856 intptr_t current_klass = op->current_klass();
2857 bool not_null = op->not_null();
2858 bool no_conflict = op->no_conflict();
2859
2860 Label update, next, none;
2861
2862 bool do_null = !not_null;
2863 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2864 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2865
2866 assert(do_null || do_update, "why are we here?");
2867 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2868
2869 __ verify_oop(obj);
2870
2871 if (tmp1 != obj) {
2872 __ mov(obj, tmp1);
2873 }
2874 if (do_null) {
2875 __ br_notnull_short(tmp1, Assembler::pt, update);
2876 if (!TypeEntries::was_null_seen(current_klass)) {
2877 __ ld_ptr(mdo_addr, tmp1);
2878 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2879 __ st_ptr(tmp1, mdo_addr);
2880 }
2881 if (do_update) {
2882 __ ba(next);
2883 __ delayed()->nop();
2884 }
2885 #ifdef ASSERT
2886 } else {
2887 __ br_notnull_short(tmp1, Assembler::pt, update);
2888 __ stop("unexpect null obj");
2889 #endif
2890 }
2891
2892 __ bind(update);
2893
2894 if (do_update) {
2895 #ifdef ASSERT
2896 if (exact_klass != NULL) {
2897 Label ok;
2898 __ load_klass(tmp1, tmp1);
2899 metadata2reg(exact_klass->constant_encoding(), tmp2);
2900 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2901 __ stop("exact klass and actual klass differ");
2902 __ bind(ok);
2903 }
2904 #endif
2905
2906 Label do_update;
2907 __ ld_ptr(mdo_addr, tmp2);
2908
2909 if (!no_conflict) {
2910 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2911 if (exact_klass != NULL) {
2912 metadata2reg(exact_klass->constant_encoding(), tmp1);
2913 } else {
2914 __ load_klass(tmp1, tmp1);
2915 }
2916
2917 __ xor3(tmp1, tmp2, tmp1);
2918 __ btst(TypeEntries::type_klass_mask, tmp1);
2919 // klass seen before, nothing to do. The unknown bit may have been
2920 // set already but no need to check.
2921 __ brx(Assembler::zero, false, Assembler::pt, next);
2922 __ delayed()->
2923
2924 btst(TypeEntries::type_unknown, tmp1);
2925 // already unknown. Nothing to do anymore.
2926 __ brx(Assembler::notZero, false, Assembler::pt, next);
2927
2928 if (TypeEntries::is_type_none(current_klass)) {
2929 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2930 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2931 // first time here. Set profile type.
2932 __ delayed()->or3(tmp2, tmp1, tmp2);
2933 } else {
2934 __ delayed()->nop();
2935 }
2936 } else {
2937 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2938 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2939
2940 __ btst(TypeEntries::type_unknown, tmp2);
2941 // already unknown. Nothing to do anymore.
2942 __ brx(Assembler::notZero, false, Assembler::pt, next);
2943 __ delayed()->nop();
2944 }
2945
2946 // different than before. Cannot keep accurate profile.
2947 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2948 } else {
2949 // There's a single possible klass at this profile point
2950 assert(exact_klass != NULL, "should be");
2951 if (TypeEntries::is_type_none(current_klass)) {
2952 metadata2reg(exact_klass->constant_encoding(), tmp1);
2953 __ xor3(tmp1, tmp2, tmp1);
2954 __ btst(TypeEntries::type_klass_mask, tmp1);
2955 __ brx(Assembler::zero, false, Assembler::pt, next);
2956 #ifdef ASSERT
2957
2958 {
2959 Label ok;
2960 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2961 __ brx(Assembler::zero, true, Assembler::pt, ok);
2962 __ delayed()->nop();
2963
2964 __ stop("unexpected profiling mismatch");
2965 __ bind(ok);
2966 }
2967 // first time here. Set profile type.
2968 __ or3(tmp2, tmp1, tmp2);
2969 #else
2970 // first time here. Set profile type.
2971 __ delayed()->or3(tmp2, tmp1, tmp2);
2972 #endif
2973
2974 } else {
2975 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2976 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2977
2978 // already unknown. Nothing to do anymore.
2979 __ btst(TypeEntries::type_unknown, tmp2);
2980 __ brx(Assembler::notZero, false, Assembler::pt, next);
2981 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2982 }
2983 }
2984
2985 __ bind(do_update);
2986 __ st_ptr(tmp2, mdo_addr);
2987
2988 __ bind(next);
2989 }
2990 }
2991
2992 void LIR_Assembler::align_backward_branch_target() {
2993 __ align(OptoLoopAlignment);
2994 }
2995
2996
2997 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2998 // make sure we are expecting a delay
2999 // this has the side effect of clearing the delay state
3000 // so we can use _masm instead of _masm->delayed() to do the
3001 // code generation.
3002 __ delayed();
3003
3004 // make sure we only emit one instruction
3005 int offset = code_offset();
3006 op->delay_op()->emit_code(this);
3007 #ifdef ASSERT
3008 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3009 op->delay_op()->print();
3010 }
3011 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3012 "only one instruction can go in a delay slot");
3013 #endif
3014
3015 // we may also be emitting the call info for the instruction
3016 // which we are the delay slot of.
3017 CodeEmitInfo* call_info = op->call_info();
3018 if (call_info) {
3019 add_call_info(code_offset(), call_info);
3020 }
3021
3022 if (VerifyStackAtCalls) {
3023 _masm->sub(FP, SP, O7);
3024 _masm->cmp(O7, initial_frame_size_in_bytes());
3025 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3026 }
3027 }
3028
3029
3030 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3031 assert(left->is_register(), "can only handle registers");
3032
3033 if (left->is_single_cpu()) {
3034 __ neg(left->as_register(), dest->as_register());
3035 } else if (left->is_single_fpu()) {
3036 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3037 } else if (left->is_double_fpu()) {
3038 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3039 } else {
3040 assert (left->is_double_cpu(), "Must be a long");
3041 Register Rlow = left->as_register_lo();
3042 Register Rhi = left->as_register_hi();
3043 __ sub(G0, Rlow, dest->as_register_lo());
3044 }
3045 }
3046
3047
3048 void LIR_Assembler::fxch(int i) {
3049 Unimplemented();
3050 }
3051
3052 void LIR_Assembler::fld(int i) {
3053 Unimplemented();
3054 }
3055
3056 void LIR_Assembler::ffree(int i) {
3057 Unimplemented();
3058 }
3059
3060 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3061 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3062
3063 // if tmp is invalid, then the function being called doesn't destroy the thread
3064 if (tmp->is_valid()) {
3065 __ save_thread(tmp->as_pointer_register());
3066 }
3067 __ call(dest, relocInfo::runtime_call_type);
3068 __ delayed()->nop();
3069 if (info != NULL) {
3070 add_call_info_here(info);
3071 }
3072 if (tmp->is_valid()) {
3073 __ restore_thread(tmp->as_pointer_register());
3074 }
3075
3076 #ifdef ASSERT
3077 __ verify_thread();
3078 #endif // ASSERT
3079 }
3080
3081
3082 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3083 ShouldNotReachHere();
3084
3085 NEEDS_CLEANUP;
3086 if (type == T_LONG) {
3087 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3088
3089 // (extended to allow indexed as well as constant displaced for JSR-166)
3090 Register idx = noreg; // contains either constant offset or index
3091
3092 int disp = mem_addr->disp();
3093 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3094 if (!Assembler::is_simm13(disp)) {
3095 idx = O7;
3096 __ set(disp, idx);
3097 }
3098 } else {
3099 assert(disp == 0, "not both indexed and disp");
3100 idx = mem_addr->index()->as_register();
3101 }
3102
3103 int null_check_offset = -1;
3104
3105 Register base = mem_addr->base()->as_register();
3106 if (src->is_register() && dest->is_address()) {
3107 // G4 is high half, G5 is low half
3108 // clear the top bits of G5, and scale up G4
3109 __ srl (src->as_register_lo(), 0, G5);
3110 __ sllx(src->as_register_hi(), 32, G4);
3111 // combine the two halves into the 64 bits of G4
3112 __ or3(G4, G5, G4);
3113 null_check_offset = __ offset();
3114 if (idx == noreg) {
3115 __ stx(G4, base, disp);
3116 } else {
3117 __ stx(G4, base, idx);
3118 }
3119 } else if (src->is_address() && dest->is_register()) {
3120 null_check_offset = __ offset();
3121 if (idx == noreg) {
3122 __ ldx(base, disp, G5);
3123 } else {
3124 __ ldx(base, idx, G5);
3125 }
3126 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3127 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3128 } else {
3129 Unimplemented();
3130 }
3131 if (info != NULL) {
3132 add_debug_info_for_null_check(null_check_offset, info);
3133 }
3134
3135 } else {
3136 // use normal move for all other volatiles since they don't need
3137 // special handling to remain atomic.
3138 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3139 }
3140 }
3141
3142 void LIR_Assembler::membar() {
3143 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3144 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3145 }
3146
3147 void LIR_Assembler::membar_acquire() {
3148 // no-op on TSO
3149 }
3150
3151 void LIR_Assembler::membar_release() {
3152 // no-op on TSO
3153 }
3154
3155 void LIR_Assembler::membar_loadload() {
3156 // no-op
3157 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3158 }
3159
3160 void LIR_Assembler::membar_storestore() {
3161 // no-op
3162 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3163 }
3164
3165 void LIR_Assembler::membar_loadstore() {
3166 // no-op
3167 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3168 }
3169
3170 void LIR_Assembler::membar_storeload() {
3171 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3172 }
3173
3174 void LIR_Assembler::on_spin_wait() {
3175 Unimplemented();
3176 }
3177
3178 // Pack two sequential registers containing 32 bit values
3179 // into a single 64 bit register.
3180 // src and src->successor() are packed into dst
3181 // src and dst may be the same register.
3182 // Note: src is destroyed
3183 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3184 Register rs = src->as_register();
3185 Register rd = dst->as_register_lo();
3186 __ sllx(rs, 32, rs);
3187 __ srl(rs->successor(), 0, rs->successor());
3188 __ or3(rs, rs->successor(), rd);
3189 }
3190
3191 // Unpack a 64 bit value in a register into
3192 // two sequential registers.
3193 // src is unpacked into dst and dst->successor()
3194 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3195 Register rs = src->as_register_lo();
3196 Register rd = dst->as_register_hi();
3197 assert_different_registers(rs, rd, rd->successor());
3198 __ srlx(rs, 32, rd);
3199 __ srl (rs, 0, rd->successor());
3200 }
3201
3202 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3203 const LIR_Address* addr = addr_opr->as_address_ptr();
3204 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3205 const Register dest_reg = dest->as_pointer_register();
3206 const Register base_reg = addr->base()->as_pointer_register();
3207
3208 if (Assembler::is_simm13(addr->disp())) {
3209 if (addr->index()->is_valid()) {
3210 const Register index_reg = addr->index()->as_pointer_register();
3211 assert(index_reg != G3_scratch, "invariant");
3212 __ add(base_reg, addr->disp(), G3_scratch);
3213 __ add(index_reg, G3_scratch, dest_reg);
3214 } else {
3215 __ add(base_reg, addr->disp(), dest_reg);
3216 }
3217 } else {
3218 __ set(addr->disp(), G3_scratch);
3219 if (addr->index()->is_valid()) {
3220 const Register index_reg = addr->index()->as_pointer_register();
3221 assert(index_reg != G3_scratch, "invariant");
3222 __ add(index_reg, G3_scratch, G3_scratch);
3223 }
3224 __ add(base_reg, G3_scratch, dest_reg);
3225 }
3226 }
3227
3228
3229 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3230 assert(result_reg->is_register(), "check");
3231 __ mov(G2_thread, result_reg->as_register());
3232 }
3233
3234 #ifdef ASSERT
3235 // emit run-time assertion
3236 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3237 assert(op->code() == lir_assert, "must be");
3238
3239 if (op->in_opr1()->is_valid()) {
3240 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3241 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3242 } else {
3243 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3244 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3245 }
3246
3247 Label ok;
3248 if (op->condition() != lir_cond_always) {
3249 Assembler::Condition acond;
3250 switch (op->condition()) {
3251 case lir_cond_equal: acond = Assembler::equal; break;
3252 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3253 case lir_cond_less: acond = Assembler::less; break;
3254 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3255 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3256 case lir_cond_greater: acond = Assembler::greater; break;
3257 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3258 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3259 default: ShouldNotReachHere();
3260 };
3261 __ br(acond, false, Assembler::pt, ok);
3262 __ delayed()->nop();
3263 }
3264 if (op->halt()) {
3265 const char* str = __ code_string(op->msg());
3266 __ stop(str);
3267 } else {
3268 breakpoint();
3269 }
3270 __ bind(ok);
3271 }
3272 #endif
3273
3274 void LIR_Assembler::peephole(LIR_List* lir) {
3275 LIR_OpList* inst = lir->instructions_list();
3276 for (int i = 0; i < inst->length(); i++) {
3277 LIR_Op* op = inst->at(i);
3278 switch (op->code()) {
3279 case lir_cond_float_branch:
3280 case lir_branch: {
3281 LIR_OpBranch* branch = op->as_OpBranch();
3282 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3283 LIR_Op* delay_op = NULL;
3284 // we'd like to be able to pull following instructions into
3285 // this slot but we don't know enough to do it safely yet so
3286 // only optimize block to block control flow.
3287 if (LIRFillDelaySlots && branch->block()) {
3288 LIR_Op* prev = inst->at(i - 1);
3289 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3290 // swap previous instruction into delay slot
3291 inst->at_put(i - 1, op);
3292 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3293 #ifndef PRODUCT
3294 if (LIRTracePeephole) {
3295 tty->print_cr("delayed");
3296 inst->at(i - 1)->print();
3297 inst->at(i)->print();
3298 tty->cr();
3299 }
3300 #endif
3301 continue;
3302 }
3303 }
3304
3305 if (!delay_op) {
3306 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3307 }
3308 inst->insert_before(i + 1, delay_op);
3309 break;
3310 }
3311 case lir_static_call:
3312 case lir_virtual_call:
3313 case lir_icvirtual_call:
3314 case lir_optvirtual_call:
3315 case lir_dynamic_call: {
3316 LIR_Op* prev = inst->at(i - 1);
3317 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3318 (op->code() != lir_virtual_call ||
3319 !prev->result_opr()->is_single_cpu() ||
3320 prev->result_opr()->as_register() != O0) &&
3321 LIR_Assembler::is_single_instruction(prev)) {
3322 // Only moves without info can be put into the delay slot.
3323 // Also don't allow the setup of the receiver in the delay
3324 // slot for vtable calls.
3325 inst->at_put(i - 1, op);
3326 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3327 #ifndef PRODUCT
3328 if (LIRTracePeephole) {
3329 tty->print_cr("delayed");
3330 inst->at(i - 1)->print();
3331 inst->at(i)->print();
3332 tty->cr();
3333 }
3334 #endif
3335 } else {
3336 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3337 inst->insert_before(i + 1, delay_op);
3338 i++;
3339 }
3340 break;
3341 }
3342 }
3343 }
3344 }
3345
3346 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3347 LIR_Address* addr = src->as_address_ptr();
3348
3349 assert(data == dest, "swap uses only 2 operands");
3350 assert (code == lir_xchg, "no xadd on sparc");
3351
3352 if (data->type() == T_INT) {
3353 __ swap(as_Address(addr), data->as_register());
3354 } else if (data->is_oop()) {
3355 Register obj = data->as_register();
3356 Register narrow = tmp->as_register();
3357 assert(UseCompressedOops, "swap is 32bit only");
3358 __ encode_heap_oop(obj, narrow);
3359 __ swap(as_Address(addr), narrow);
3360 __ decode_heap_oop(narrow, obj);
3361 } else {
3362 ShouldNotReachHere();
3363 }
3364 }
3365
3366 #undef __