375
376 // Consider checking _owner's schedctl state, if OFFPROC abort spin.
377 // If the owner is OFFPROC then it's unlike that the lock will be dropped
378 // in a timely fashion, which suggests that spinning would not be fruitful
379 // or profitable.
380
381 // Stall for "Delay" time units - iterations in the current implementation.
382 // Avoid generating coherency traffic while stalled.
383 // Possible ways to delay:
384 // PAUSE, SLEEP, MEMBAR #sync, MEMBAR #halt,
385 // wr %g0,%asi, gethrtime, rdstick, rdtick, rdtsc, etc. ...
386 // Note that on Niagara-class systems we want to minimize STs in the
387 // spin loop. N1 and brethren write-around the L1$ over the xbar into the L2$.
388 // Furthermore, they don't have a W$ like traditional SPARC processors.
389 // We currently use a Marsaglia Shift-Xor RNG loop.
390 Steps += Delay;
391 if (Self != NULL) {
392 jint rv = Self->rng[0];
393 for (int k = Delay; --k >= 0;) {
394 rv = MarsagliaXORV(rv);
395 if ((flgs & 4) == 0 && SafepointMechanism::poll()) return 0;
396 }
397 Self->rng[0] = rv;
398 } else {
399 Stall(Delay);
400 }
401 }
402 }
403
404 static int ParkCommon(ParkEvent * ev, jlong timo) {
405 // Diagnostic support - periodically unwedge blocked threads
406 intx nmt = NativeMonitorTimeout;
407 if (nmt > 0 && (nmt < timo || timo <= 0)) {
408 timo = nmt;
409 }
410 int err = OS_OK;
411 if (0 == timo) {
412 ev->park();
413 } else {
414 err = ev->park(timo);
415 }
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375
376 // Consider checking _owner's schedctl state, if OFFPROC abort spin.
377 // If the owner is OFFPROC then it's unlike that the lock will be dropped
378 // in a timely fashion, which suggests that spinning would not be fruitful
379 // or profitable.
380
381 // Stall for "Delay" time units - iterations in the current implementation.
382 // Avoid generating coherency traffic while stalled.
383 // Possible ways to delay:
384 // PAUSE, SLEEP, MEMBAR #sync, MEMBAR #halt,
385 // wr %g0,%asi, gethrtime, rdstick, rdtick, rdtsc, etc. ...
386 // Note that on Niagara-class systems we want to minimize STs in the
387 // spin loop. N1 and brethren write-around the L1$ over the xbar into the L2$.
388 // Furthermore, they don't have a W$ like traditional SPARC processors.
389 // We currently use a Marsaglia Shift-Xor RNG loop.
390 Steps += Delay;
391 if (Self != NULL) {
392 jint rv = Self->rng[0];
393 for (int k = Delay; --k >= 0;) {
394 rv = MarsagliaXORV(rv);
395 if ((flgs & 4) == 0 && SafepointMechanism::poll(Self)) return 0;
396 }
397 Self->rng[0] = rv;
398 } else {
399 Stall(Delay);
400 }
401 }
402 }
403
404 static int ParkCommon(ParkEvent * ev, jlong timo) {
405 // Diagnostic support - periodically unwedge blocked threads
406 intx nmt = NativeMonitorTimeout;
407 if (nmt > 0 && (nmt < timo || timo <= 0)) {
408 timo = nmt;
409 }
410 int err = OS_OK;
411 if (0 == timo) {
412 ev->park();
413 } else {
414 err = ev->park(timo);
415 }
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