1 //
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 // 64-bit build means 64-bit pointers means hi/lo pairs
315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
319 // Lock encodings use G3 and G4 internally
320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
324 // Special class for storeP instructions, which can store SP or RPC to TLS.
325 // It is also used for memory addressing, allowing direct TLS addressing.
326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
330 // R_L7 is the lowest-priority callee-save (i.e., NS) register
331 // We use it to save R_G2 across calls out of Java.
332 reg_class l7_regP(R_L7H,R_L7);
333
334 // Other special pointer regs
335 reg_class g1_regP(R_G1H,R_G1);
336 reg_class g2_regP(R_G2H,R_G2);
337 reg_class g3_regP(R_G3H,R_G3);
338 reg_class g4_regP(R_G4H,R_G4);
339 reg_class g5_regP(R_G5H,R_G5);
340 reg_class i0_regP(R_I0H,R_I0);
341 reg_class o0_regP(R_O0H,R_O0);
342 reg_class o1_regP(R_O1H,R_O1);
343 reg_class o2_regP(R_O2H,R_O2);
344 reg_class o7_regP(R_O7H,R_O7);
345
346
347 // ----------------------------
348 // Long Register Classes
349 // ----------------------------
350 // Longs in 1 register. Aligned adjacent hi/lo pairs.
351 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
354 // 64-bit, longs in 1 register: use all 64-bit integer registers
355 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
356 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
357 );
358
359 reg_class g1_regL(R_G1H,R_G1);
360 reg_class g3_regL(R_G3H,R_G3);
361 reg_class o2_regL(R_O2H,R_O2);
362 reg_class o7_regL(R_O7H,R_O7);
363
364 // ----------------------------
365 // Special Class for Condition Code Flags Register
366 reg_class int_flags(CCR);
367 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
368 reg_class float_flag0(FCC0);
369
370
371 // ----------------------------
372 // Float Point Register Classes
373 // ----------------------------
374 // Skip F30/F31, they are reserved for mem-mem copies
375 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
376
377 // Paired floating point registers--they show up in the same order as the floats,
378 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
379 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
380 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
381 /* Use extra V9 double registers; this AD file does not support V8 */
382 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
383 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
384 );
385
386 // Paired floating point registers--they show up in the same order as the floats,
387 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
388 // This class is usable for mis-aligned loads as happen in I2C adapters.
389 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
390 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
391 %}
392
393 //----------DEFINITION BLOCK---------------------------------------------------
394 // Define name --> value mappings to inform the ADLC of an integer valued name
395 // Current support includes integer values in the range [0, 0x7FFFFFFF]
396 // Format:
397 // int_def <name> ( <int_value>, <expression>);
398 // Generated Code in ad_<arch>.hpp
399 // #define <name> (<expression>)
400 // // value == <int_value>
401 // Generated code in ad_<arch>.cpp adlc_verification()
402 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
403 //
404 definitions %{
405 // The default cost (of an ALU instruction).
406 int_def DEFAULT_COST ( 100, 100);
407 int_def HUGE_COST (1000000, 1000000);
408
409 // Memory refs are twice as expensive as run-of-the-mill.
410 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
411
412 // Branches are even more expensive.
413 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
414 int_def CALL_COST ( 300, DEFAULT_COST * 3);
415 %}
416
417
418 //----------SOURCE BLOCK-------------------------------------------------------
419 // This is a block of C++ code which provides values, functions, and
420 // definitions necessary in the rest of the architecture description
421 source_hpp %{
422 // Header information of the source block.
423 // Method declarations/definitions which are used outside
424 // the ad-scope can conveniently be defined here.
425 //
426 // To keep related declarations/definitions/uses close together,
427 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
428
429 // Must be visible to the DFA in dfa_sparc.cpp
430 extern bool can_branch_register( Node *bol, Node *cmp );
431
432 extern bool use_block_zeroing(Node* count);
433
434 // Macros to extract hi & lo halves from a long pair.
435 // G0 is not part of any long pair, so assert on that.
436 // Prevents accidentally using G1 instead of G0.
437 #define LONG_HI_REG(x) (x)
438 #define LONG_LO_REG(x) (x)
439
440 class CallStubImpl {
441
442 //--------------------------------------------------------------
443 //---< Used for optimization in Compile::Shorten_branches >---
444 //--------------------------------------------------------------
445
446 public:
447 // Size of call trampoline stub.
448 static uint size_call_trampoline() {
449 return 0; // no call trampolines on this platform
450 }
451
452 // number of relocations needed by a call trampoline stub
453 static uint reloc_call_trampoline() {
454 return 0; // no call trampolines on this platform
455 }
456 };
457
458 class HandlerImpl {
459
460 public:
461
462 static int emit_exception_handler(CodeBuffer &cbuf);
463 static int emit_deopt_handler(CodeBuffer& cbuf);
464
465 static uint size_exception_handler() {
466 return ( NativeJump::instruction_size ); // sethi;jmp;nop
467 }
468
469 static uint size_deopt_handler() {
470 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
471 }
472 };
473
474 %}
475
476 source %{
477 #define __ _masm.
478
479 // tertiary op of a LoadP or StoreP encoding
480 #define REGP_OP true
481
482 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
483 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
484 static Register reg_to_register_object(int register_encoding);
485
486 // Used by the DFA in dfa_sparc.cpp.
487 // Check for being able to use a V9 branch-on-register. Requires a
488 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
489 // extended. Doesn't work following an integer ADD, for example, because of
490 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
491 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
492 // replace them with zero, which could become sign-extension in a different OS
493 // release. There's no obvious reason why an interrupt will ever fill these
494 // bits with non-zero junk (the registers are reloaded with standard LD
495 // instructions which either zero-fill or sign-fill).
496 bool can_branch_register( Node *bol, Node *cmp ) {
497 if( !BranchOnRegister ) return false;
498 if( cmp->Opcode() == Op_CmpP )
499 return true; // No problems with pointer compares
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 bool use_block_zeroing(Node* count) {
528 // Use BIS for zeroing if count is not constant
529 // or it is >= BlockZeroingLowLimit.
530 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
531 }
532
533 // ****************************************************************************
534
535 // REQUIRED FUNCTIONALITY
536
537 // !!!!! Special hack to get all type of calls to specify the byte offset
538 // from the start of the call to the point where the return address
539 // will point.
540 // The "return address" is the address of the call instruction, plus 8.
541
542 int MachCallStaticJavaNode::ret_addr_offset() {
543 int offset = NativeCall::instruction_size; // call; delay slot
544 if (_method_handle_invoke)
545 offset += 4; // restore SP
546 return offset;
547 }
548
549 int MachCallDynamicJavaNode::ret_addr_offset() {
550 int vtable_index = this->_vtable_index;
551 if (vtable_index < 0) {
552 // must be invalid_vtable_index, not nonvirtual_vtable_index
553 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
554 return (NativeMovConstReg::instruction_size +
555 NativeCall::instruction_size); // sethi; setlo; call; delay slot
556 } else {
557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
558 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
559 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
560 int klass_load_size;
561 if (UseCompressedClassPointers) {
562 assert(Universe::heap() != NULL, "java heap should be initialized");
563 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
564 } else {
565 klass_load_size = 1*BytesPerInstWord;
566 }
567 if (Assembler::is_simm13(v_off)) {
568 return klass_load_size +
569 (2*BytesPerInstWord + // ld_ptr, ld_ptr
570 NativeCall::instruction_size); // call; delay slot
571 } else {
572 return klass_load_size +
573 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
574 NativeCall::instruction_size); // call; delay slot
575 }
576 }
577 }
578
579 int MachCallRuntimeNode::ret_addr_offset() {
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 }
586
587 // Indicate if the safepoint node needs the polling page as an input.
588 // Since Sparc does not have absolute addressing, it does.
589 bool SafePointNode::needs_polling_address_input() {
590 return true;
591 }
592
593 // emit an interrupt that is caught by the debugger (for debugging compiler)
594 void emit_break(CodeBuffer &cbuf) {
595 MacroAssembler _masm(&cbuf);
596 __ breakpoint_trap();
597 }
598
599 #ifndef PRODUCT
600 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
601 st->print("TA");
602 }
603 #endif
604
605 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
606 emit_break(cbuf);
607 }
608
609 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_);
611 }
612
613 // Traceable jump
614 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
615 MacroAssembler _masm(&cbuf);
616 Register rdest = reg_to_register_object(jump_target);
617 __ JMP(rdest, 0);
618 __ delayed()->nop();
619 }
620
621 // Traceable jump and set exception pc
622 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
623 MacroAssembler _masm(&cbuf);
624 Register rdest = reg_to_register_object(jump_target);
625 __ JMP(rdest, 0);
626 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
627 }
628
629 void emit_nop(CodeBuffer &cbuf) {
630 MacroAssembler _masm(&cbuf);
631 __ nop();
632 }
633
634 void emit_illtrap(CodeBuffer &cbuf) {
635 MacroAssembler _masm(&cbuf);
636 __ illtrap(0);
637 }
638
639
640 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
641 assert(n->rule() != loadUB_rule, "");
642
643 intptr_t offset = 0;
644 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
645 const Node* addr = n->get_base_and_disp(offset, adr_type);
646 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
647 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
648 assert(addr->bottom_type()->isa_oopptr() == atype, "");
649 atype = atype->add_offset(offset);
650 assert(disp32 == offset, "wrong disp32");
651 return atype->_offset;
652 }
653
654
655 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
656 assert(n->rule() != loadUB_rule, "");
657
658 intptr_t offset = 0;
659 Node* addr = n->in(2);
660 assert(addr->bottom_type()->isa_oopptr() == atype, "");
661 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
662 Node* a = addr->in(2/*AddPNode::Address*/);
663 Node* o = addr->in(3/*AddPNode::Offset*/);
664 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
665 atype = a->bottom_type()->is_ptr()->add_offset(offset);
666 assert(atype->isa_oop_ptr(), "still an oop");
667 }
668 offset = atype->is_ptr()->_offset;
669 if (offset != Type::OffsetBot) offset += disp32;
670 return offset;
671 }
672
673 static inline jlong replicate_immI(int con, int count, int width) {
674 // Load a constant replicated "count" times with width "width"
675 assert(count*width == 8 && width <= 4, "sanity");
676 int bit_width = width * 8;
677 jlong val = con;
678 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
679 for (int i = 0; i < count - 1; i++) {
680 val |= (val << bit_width);
681 }
682 return val;
683 }
684
685 static inline jlong replicate_immF(float con) {
686 // Replicate float con 2 times and pack into vector.
687 int val = *((int*)&con);
688 jlong lval = val;
689 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
690 return lval;
691 }
692
693 // Standard Sparc opcode form2 field breakdown
694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
695 f0 &= (1<<19)-1; // Mask displacement to 19 bits
696 int op = (f30 << 30) |
697 (f29 << 29) |
698 (f25 << 25) |
699 (f22 << 22) |
700 (f20 << 20) |
701 (f19 << 19) |
702 (f0 << 0);
703 cbuf.insts()->emit_int32(op);
704 }
705
706 // Standard Sparc opcode form2 field breakdown
707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
708 f0 >>= 10; // Drop 10 bits
709 f0 &= (1<<22)-1; // Mask displacement to 22 bits
710 int op = (f30 << 30) |
711 (f25 << 25) |
712 (f22 << 22) |
713 (f0 << 0);
714 cbuf.insts()->emit_int32(op);
715 }
716
717 // Standard Sparc opcode form3 field breakdown
718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
719 int op = (f30 << 30) |
720 (f25 << 25) |
721 (f19 << 19) |
722 (f14 << 14) |
723 (f5 << 5) |
724 (f0 << 0);
725 cbuf.insts()->emit_int32(op);
726 }
727
728 // Standard Sparc opcode form3 field breakdown
729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
730 simm13 &= (1<<13)-1; // Mask to 13 bits
731 int op = (f30 << 30) |
732 (f25 << 25) |
733 (f19 << 19) |
734 (f14 << 14) |
735 (1 << 13) | // bit to indicate immediate-mode
736 (simm13<<0);
737 cbuf.insts()->emit_int32(op);
738 }
739
740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
741 simm10 &= (1<<10)-1; // Mask to 10 bits
742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
743 }
744
745 #ifdef ASSERT
746 // Helper function for VerifyOops in emit_form3_mem_reg
747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
748 warning("VerifyOops encountered unexpected instruction:");
749 n->dump(2);
750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
751 }
752 #endif
753
754
755 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
756 int src1_enc, int disp32, int src2_enc, int dst_enc) {
757
758 #ifdef ASSERT
759 // The following code implements the +VerifyOops feature.
760 // It verifies oop values which are loaded into or stored out of
761 // the current method activation. +VerifyOops complements techniques
762 // like ScavengeALot, because it eagerly inspects oops in transit,
763 // as they enter or leave the stack, as opposed to ScavengeALot,
764 // which inspects oops "at rest", in the stack or heap, at safepoints.
765 // For this reason, +VerifyOops can sometimes detect bugs very close
766 // to their point of creation. It can also serve as a cross-check
767 // on the validity of oop maps, when used toegether with ScavengeALot.
768
769 // It would be good to verify oops at other points, especially
770 // when an oop is used as a base pointer for a load or store.
771 // This is presently difficult, because it is hard to know when
772 // a base address is biased or not. (If we had such information,
773 // it would be easy and useful to make a two-argument version of
774 // verify_oop which unbiases the base, and performs verification.)
775
776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
777 bool is_verified_oop_base = false;
778 bool is_verified_oop_load = false;
779 bool is_verified_oop_store = false;
780 int tmp_enc = -1;
781 if (VerifyOops && src1_enc != R_SP_enc) {
782 // classify the op, mainly for an assert check
783 int st_op = 0, ld_op = 0;
784 switch (primary) {
785 case Assembler::stb_op3: st_op = Op_StoreB; break;
786 case Assembler::sth_op3: st_op = Op_StoreC; break;
787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
788 case Assembler::stw_op3: st_op = Op_StoreI; break;
789 case Assembler::std_op3: st_op = Op_StoreL; break;
790 case Assembler::stf_op3: st_op = Op_StoreF; break;
791 case Assembler::stdf_op3: st_op = Op_StoreD; break;
792
793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
794 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
795 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
796 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
797 case Assembler::ldx_op3: // may become LoadP or stay LoadI
798 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
799 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
800 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
801 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
802 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
804
805 default: ShouldNotReachHere();
806 }
807 if (tertiary == REGP_OP) {
808 if (st_op == Op_StoreI) st_op = Op_StoreP;
809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
810 else ShouldNotReachHere();
811 if (st_op) {
812 // a store
813 // inputs are (0:control, 1:memory, 2:address, 3:value)
814 Node* n2 = n->in(3);
815 if (n2 != NULL) {
816 const Type* t = n2->bottom_type();
817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 } else {
820 // a load
821 const Type* t = n->bottom_type();
822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 }
825
826 if (ld_op) {
827 // a Load
828 // inputs are (0:control, 1:memory, 2:address)
829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
830 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
831 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
832 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
833 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
835 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
836 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
838 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
842 !(n->rule() == loadUB_rule)) {
843 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
844 }
845 } else if (st_op) {
846 // a Store
847 // inputs are (0:control, 1:memory, 2:address, 3:value)
848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
854 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
855 verify_oops_warning(n, n->ideal_Opcode(), st_op);
856 }
857 }
858
859 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
860 Node* addr = n->in(2);
861 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
862 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
863 if (atype != NULL) {
864 intptr_t offset = get_offset_from_base(n, atype, disp32);
865 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
866 if (offset != offset_2) {
867 get_offset_from_base(n, atype, disp32);
868 get_offset_from_base_2(n, atype, disp32);
869 }
870 assert(offset == offset_2, "different offsets");
871 if (offset == disp32) {
872 // we now know that src1 is a true oop pointer
873 is_verified_oop_base = true;
874 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
875 if( primary == Assembler::ldd_op3 ) {
876 is_verified_oop_base = false; // Cannot 'ldd' into O7
877 } else {
878 tmp_enc = dst_enc;
879 dst_enc = R_O7_enc; // Load into O7; preserve source oop
880 assert(src1_enc != dst_enc, "");
881 }
882 }
883 }
884 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
885 || offset == oopDesc::mark_offset_in_bytes())) {
886 // loading the mark should not be allowed either, but
887 // we don't check this since it conflicts with InlineObjectHash
888 // usage of LoadINode to get the mark. We could keep the
889 // check if we create a new LoadMarkNode
890 // but do not verify the object before its header is initialized
891 ShouldNotReachHere();
892 }
893 }
894 }
895 }
896 }
897 #endif
898
899 uint instr = (Assembler::ldst_op << 30)
900 | (dst_enc << 25)
901 | (primary << 19)
902 | (src1_enc << 14);
903
904 uint index = src2_enc;
905 int disp = disp32;
906
907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
908 disp += STACK_BIAS;
909 // Check that stack offset fits, load into O7 if not
910 if (!Assembler::is_simm13(disp)) {
911 MacroAssembler _masm(&cbuf);
912 __ set(disp, O7);
913 if (index != R_G0_enc) {
914 __ add(O7, reg_to_register_object(index), O7);
915 }
916 index = R_O7_enc;
917 disp = 0;
918 }
919 }
920
921 if( disp == 0 ) {
922 // use reg-reg form
923 // bit 13 is already zero
924 instr |= index;
925 } else {
926 // use reg-imm form
927 instr |= 0x00002000; // set bit 13 to one
928 instr |= disp & 0x1FFF;
929 }
930
931 cbuf.insts()->emit_int32(instr);
932
933 #ifdef ASSERT
934 if (VerifyOops) {
935 MacroAssembler _masm(&cbuf);
936 if (is_verified_oop_base) {
937 __ verify_oop(reg_to_register_object(src1_enc));
938 }
939 if (is_verified_oop_store) {
940 __ verify_oop(reg_to_register_object(dst_enc));
941 }
942 if (tmp_enc != -1) {
943 __ mov(O7, reg_to_register_object(tmp_enc));
944 }
945 if (is_verified_oop_load) {
946 __ verify_oop(reg_to_register_object(dst_enc));
947 }
948 }
949 #endif
950 }
951
952 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
953 // The method which records debug information at every safepoint
954 // expects the call to be the first instruction in the snippet as
955 // it creates a PcDesc structure which tracks the offset of a call
956 // from the start of the codeBlob. This offset is computed as
957 // code_end() - code_begin() of the code which has been emitted
958 // so far.
959 // In this particular case we have skirted around the problem by
960 // putting the "mov" instruction in the delay slot but the problem
961 // may bite us again at some other point and a cleaner/generic
962 // solution using relocations would be needed.
963 MacroAssembler _masm(&cbuf);
964 __ set_inst_mark();
965
966 // We flush the current window just so that there is a valid stack copy
967 // the fact that the current window becomes active again instantly is
968 // not a problem there is nothing live in it.
969
970 #ifdef ASSERT
971 int startpos = __ offset();
972 #endif /* ASSERT */
973
974 __ call((address)entry_point, rspec);
975
976 if (preserve_g2) __ delayed()->mov(G2, L7);
977 else __ delayed()->nop();
978
979 if (preserve_g2) __ mov(L7, G2);
980
981 #ifdef ASSERT
982 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
983 // Trash argument dump slots.
984 __ set(0xb0b8ac0db0b8ac0d, G1);
985 __ mov(G1, G5);
986 __ stx(G1, SP, STACK_BIAS + 0x80);
987 __ stx(G1, SP, STACK_BIAS + 0x88);
988 __ stx(G1, SP, STACK_BIAS + 0x90);
989 __ stx(G1, SP, STACK_BIAS + 0x98);
990 __ stx(G1, SP, STACK_BIAS + 0xA0);
991 __ stx(G1, SP, STACK_BIAS + 0xA8);
992 }
993 #endif /*ASSERT*/
994 }
995
996 //=============================================================================
997 // REQUIRED FUNCTIONALITY for encoding
998 void emit_lo(CodeBuffer &cbuf, int val) { }
999 void emit_hi(CodeBuffer &cbuf, int val) { }
1000
1001
1002 //=============================================================================
1003 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1004
1005 int Compile::ConstantTable::calculate_table_base_offset() const {
1006 if (UseRDPCForConstantTableBase) {
1007 // The table base offset might be less but then it fits into
1008 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1009 return Assembler::min_simm13();
1010 } else {
1011 int offset = -(size() / 2);
1012 if (!Assembler::is_simm13(offset)) {
1013 offset = Assembler::min_simm13();
1014 }
1015 return offset;
1016 }
1017 }
1018
1019 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1020 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1021 ShouldNotReachHere();
1022 }
1023
1024 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1025 Compile* C = ra_->C;
1026 Compile::ConstantTable& constant_table = C->constant_table();
1027 MacroAssembler _masm(&cbuf);
1028
1029 Register r = as_Register(ra_->get_encode(this));
1030 CodeSection* consts_section = __ code()->consts();
1031 int consts_size = consts_section->align_at_start(consts_section->size());
1032 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1033
1034 if (UseRDPCForConstantTableBase) {
1035 // For the following RDPC logic to work correctly the consts
1036 // section must be allocated right before the insts section. This
1037 // assert checks for that. The layout and the SECT_* constants
1038 // are defined in src/share/vm/asm/codeBuffer.hpp.
1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1040 int insts_offset = __ offset();
1041
1042 // Layout:
1043 //
1044 // |----------- consts section ------------|----------- insts section -----------...
1045 // |------ constant table -----|- padding -|------------------x----
1046 // \ current PC (RDPC instruction)
1047 // |<------------- consts_size ----------->|<- insts_offset ->|
1048 // \ table base
1049 // The table base offset is later added to the load displacement
1050 // so it has to be negative.
1051 int table_base_offset = -(consts_size + insts_offset);
1052 int disp;
1053
1054 // If the displacement from the current PC to the constant table
1055 // base fits into simm13 we set the constant table base to the
1056 // current PC.
1057 if (Assembler::is_simm13(table_base_offset)) {
1058 constant_table.set_table_base_offset(table_base_offset);
1059 disp = 0;
1060 } else {
1061 // Otherwise we set the constant table base offset to the
1062 // maximum negative displacement of load instructions to keep
1063 // the disp as small as possible:
1064 //
1065 // |<------------- consts_size ----------->|<- insts_offset ->|
1066 // |<--------- min_simm13 --------->|<-------- disp --------->|
1067 // \ table base
1068 table_base_offset = Assembler::min_simm13();
1069 constant_table.set_table_base_offset(table_base_offset);
1070 disp = (consts_size + insts_offset) + table_base_offset;
1071 }
1072
1073 __ rdpc(r);
1074
1075 if (disp == 0) {
1076 // Emitting an additional 'nop' instruction in order not to cause a code
1077 // size adjustment in the code following the table setup (if the instruction
1078 // immediately following after this section is a CTI).
1079 __ nop();
1080 }
1081 else {
1082 assert(r != O7, "need temporary");
1083 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1084 }
1085 }
1086 else {
1087 // Materialize the constant table base.
1088 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1089 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1090 AddressLiteral base(baseaddr, rspec);
1091 __ set(base, r);
1092 }
1093 }
1094
1095 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1096 if (UseRDPCForConstantTableBase) {
1097 // This is really the worst case but generally it's only 1 instruction.
1098 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1099 } else {
1100 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1101 }
1102 }
1103
1104 #ifndef PRODUCT
1105 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1106 char reg[128];
1107 ra_->dump_register(this, reg);
1108 if (UseRDPCForConstantTableBase) {
1109 st->print("RDPC %s\t! constant table base", reg);
1110 } else {
1111 st->print("SET &constanttable,%s\t! constant table base", reg);
1112 }
1113 }
1114 #endif
1115
1116
1117 //=============================================================================
1118
1119 #ifndef PRODUCT
1120 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1121 Compile* C = ra_->C;
1122
1123 for (int i = 0; i < OptoPrologueNops; i++) {
1124 st->print_cr("NOP"); st->print("\t");
1125 }
1126
1127 if( VerifyThread ) {
1128 st->print_cr("Verify_Thread"); st->print("\t");
1129 }
1130
1131 size_t framesize = C->frame_size_in_bytes();
1132 int bangsize = C->bang_size_in_bytes();
1133
1134 // Calls to C2R adapters often do not accept exceptional returns.
1135 // We require that their callers must bang for them. But be careful, because
1136 // some VM calls (such as call site linkage) can use several kilobytes of
1137 // stack. But the stack safety zone should account for that.
1138 // See bugs 4446381, 4468289, 4497237.
1139 if (C->need_stack_bang(bangsize)) {
1140 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1141 }
1142
1143 if (Assembler::is_simm13(-framesize)) {
1144 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1145 } else {
1146 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1147 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1148 st->print ("SAVE R_SP,R_G3,R_SP");
1149 }
1150
1151 }
1152 #endif
1153
1154 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1155 Compile* C = ra_->C;
1156 MacroAssembler _masm(&cbuf);
1157
1158 for (int i = 0; i < OptoPrologueNops; i++) {
1159 __ nop();
1160 }
1161
1162 __ verify_thread();
1163
1164 size_t framesize = C->frame_size_in_bytes();
1165 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1166 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1167 int bangsize = C->bang_size_in_bytes();
1168
1169 // Calls to C2R adapters often do not accept exceptional returns.
1170 // We require that their callers must bang for them. But be careful, because
1171 // some VM calls (such as call site linkage) can use several kilobytes of
1172 // stack. But the stack safety zone should account for that.
1173 // See bugs 4446381, 4468289, 4497237.
1174 if (C->need_stack_bang(bangsize)) {
1175 __ generate_stack_overflow_check(bangsize);
1176 }
1177
1178 if (Assembler::is_simm13(-framesize)) {
1179 __ save(SP, -framesize, SP);
1180 } else {
1181 __ sethi(-framesize & ~0x3ff, G3);
1182 __ add(G3, -framesize & 0x3ff, G3);
1183 __ save(SP, G3, SP);
1184 }
1185 C->set_frame_complete( __ offset() );
1186
1187 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1188 // NOTE: We set the table base offset here because users might be
1189 // emitted before MachConstantBaseNode.
1190 Compile::ConstantTable& constant_table = C->constant_table();
1191 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1192 }
1193 }
1194
1195 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1196 return MachNode::size(ra_);
1197 }
1198
1199 int MachPrologNode::reloc() const {
1200 return 10; // a large enough number
1201 }
1202
1203 //=============================================================================
1204 #ifndef PRODUCT
1205 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1206 Compile* C = ra_->C;
1207
1208 if(do_polling() && ra_->C->is_method_compilation()) {
1209 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1210 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1211 }
1212
1213 if(do_polling()) {
1214 if (UseCBCond && !ra_->C->is_method_compilation()) {
1215 st->print("NOP\n\t");
1216 }
1217 st->print("RET\n\t");
1218 }
1219
1220 st->print("RESTORE");
1221 }
1222 #endif
1223
1224 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1225 MacroAssembler _masm(&cbuf);
1226 Compile* C = ra_->C;
1227
1228 __ verify_thread();
1229
1230 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1231 __ reserved_stack_check();
1232 }
1233
1234 // If this does safepoint polling, then do it here
1235 if(do_polling() && ra_->C->is_method_compilation()) {
1236 AddressLiteral polling_page(os::get_polling_page());
1237 __ sethi(polling_page, L0);
1238 __ relocate(relocInfo::poll_return_type);
1239 __ ld_ptr(L0, 0, G0);
1240 }
1241
1242 // If this is a return, then stuff the restore in the delay slot
1243 if(do_polling()) {
1244 if (UseCBCond && !ra_->C->is_method_compilation()) {
1245 // Insert extra padding for the case when the epilogue is preceded by
1246 // a cbcond jump, which can't be followed by a CTI instruction
1247 __ nop();
1248 }
1249 __ ret();
1250 __ delayed()->restore();
1251 } else {
1252 __ restore();
1253 }
1254 }
1255
1256 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1257 return MachNode::size(ra_);
1258 }
1259
1260 int MachEpilogNode::reloc() const {
1261 return 16; // a large enough number
1262 }
1263
1264 const Pipeline * MachEpilogNode::pipeline() const {
1265 return MachNode::pipeline_class();
1266 }
1267
1268 int MachEpilogNode::safepoint_offset() const {
1269 assert( do_polling(), "no return for this epilog node");
1270 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1271 }
1272
1273 //=============================================================================
1274
1275 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1276 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1277 static enum RC rc_class( OptoReg::Name reg ) {
1278 if (!OptoReg::is_valid(reg)) return rc_bad;
1279 if (OptoReg::is_stack(reg)) return rc_stack;
1280 VMReg r = OptoReg::as_VMReg(reg);
1281 if (r->is_Register()) return rc_int;
1282 assert(r->is_FloatRegister(), "must be");
1283 return rc_float;
1284 }
1285
1286 #ifndef PRODUCT
1287 ATTRIBUTE_PRINTF(2, 3)
1288 static void print_helper(outputStream* st, const char* format, ...) {
1289 if (st->position() > 0) {
1290 st->cr();
1291 st->sp();
1292 }
1293 va_list ap;
1294 va_start(ap, format);
1295 st->vprint(format, ap);
1296 va_end(ap);
1297 }
1298 #endif // !PRODUCT
1299
1300 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1301 if (cbuf) {
1302 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1303 }
1304 #ifndef PRODUCT
1305 else {
1306 if (is_load) {
1307 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1308 } else {
1309 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1310 }
1311 }
1312 #endif
1313 }
1314
1315 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1316 if (cbuf) {
1317 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1318 }
1319 #ifndef PRODUCT
1320 else {
1321 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1322 }
1323 #endif
1324 }
1325
1326 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1327 CodeBuffer *cbuf,
1328 PhaseRegAlloc *ra_,
1329 outputStream* st) {
1330 // Get registers to move
1331 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1332 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1333 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1334 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1335
1336 enum RC src_second_rc = rc_class(src_second);
1337 enum RC src_first_rc = rc_class(src_first);
1338 enum RC dst_second_rc = rc_class(dst_second);
1339 enum RC dst_first_rc = rc_class(dst_first);
1340
1341 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1342
1343 if (src_first == dst_first && src_second == dst_second) {
1344 return; // Self copy, no move
1345 }
1346
1347 // --------------------------------------
1348 // Check for mem-mem move. Load into unused float registers and fall into
1349 // the float-store case.
1350 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1351 int offset = ra_->reg2offset(src_first);
1352 // Further check for aligned-adjacent pair, so we can use a double load
1353 if ((src_first&1) == 0 && src_first+1 == src_second) {
1354 src_second = OptoReg::Name(R_F31_num);
1355 src_second_rc = rc_float;
1356 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1357 } else {
1358 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1359 }
1360 src_first = OptoReg::Name(R_F30_num);
1361 src_first_rc = rc_float;
1362 }
1363
1364 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1365 int offset = ra_->reg2offset(src_second);
1366 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1367 src_second = OptoReg::Name(R_F31_num);
1368 src_second_rc = rc_float;
1369 }
1370
1371 // --------------------------------------
1372 // Check for float->int copy; requires a trip through memory
1373 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1374 int offset = frame::register_save_words*wordSize;
1375 if (cbuf) {
1376 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1377 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1378 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1379 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1380 }
1381 #ifndef PRODUCT
1382 else {
1383 print_helper(st, "SUB R_SP,16,R_SP");
1384 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1385 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1386 print_helper(st, "ADD R_SP,16,R_SP");
1387 }
1388 #endif
1389 }
1390
1391 // Check for float->int copy on T4
1392 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1393 // Further check for aligned-adjacent pair, so we can use a double move
1394 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1395 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1396 return;
1397 }
1398 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1399 }
1400 // Check for int->float copy on T4
1401 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1402 // Further check for aligned-adjacent pair, so we can use a double move
1403 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1404 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1405 return;
1406 }
1407 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1408 }
1409
1410 // --------------------------------------
1411 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1412 // In such cases, I have to do the big-endian swap. For aligned targets, the
1413 // hardware does the flop for me. Doubles are always aligned, so no problem
1414 // there. Misaligned sources only come from native-long-returns (handled
1415 // special below).
1416
1417 // --------------------------------------
1418 // Check for integer reg-reg copy
1419 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1420 // Else normal reg-reg copy
1421 assert(src_second != dst_first, "smashed second before evacuating it");
1422 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1423 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1424 // This moves an aligned adjacent pair.
1425 // See if we are done.
1426 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1427 return;
1428 }
1429 }
1430
1431 // Check for integer store
1432 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1433 int offset = ra_->reg2offset(dst_first);
1434 // Further check for aligned-adjacent pair, so we can use a double store
1435 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1436 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1437 return;
1438 }
1439 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1440 }
1441
1442 // Check for integer load
1443 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1444 int offset = ra_->reg2offset(src_first);
1445 // Further check for aligned-adjacent pair, so we can use a double load
1446 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1447 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1448 return;
1449 }
1450 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1451 }
1452
1453 // Check for float reg-reg copy
1454 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1455 // Further check for aligned-adjacent pair, so we can use a double move
1456 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1457 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1458 return;
1459 }
1460 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1461 }
1462
1463 // Check for float store
1464 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1465 int offset = ra_->reg2offset(dst_first);
1466 // Further check for aligned-adjacent pair, so we can use a double store
1467 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1468 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1469 return;
1470 }
1471 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1472 }
1473
1474 // Check for float load
1475 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1476 int offset = ra_->reg2offset(src_first);
1477 // Further check for aligned-adjacent pair, so we can use a double load
1478 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1479 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1480 return;
1481 }
1482 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1483 }
1484
1485 // --------------------------------------------------------------------
1486 // Check for hi bits still needing moving. Only happens for misaligned
1487 // arguments to native calls.
1488 if (src_second == dst_second) {
1489 return; // Self copy; no move
1490 }
1491 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1492
1493 Unimplemented();
1494 }
1495
1496 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1497 PhaseRegAlloc *ra_,
1498 bool do_size,
1499 outputStream* st) const {
1500 assert(!do_size, "not supported");
1501 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1502 return 0;
1503 }
1504
1505 #ifndef PRODUCT
1506 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1507 implementation( NULL, ra_, false, st );
1508 }
1509 #endif
1510
1511 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1512 implementation( &cbuf, ra_, false, NULL );
1513 }
1514
1515 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1516 return MachNode::size(ra_);
1517 }
1518
1519 //=============================================================================
1520 #ifndef PRODUCT
1521 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1522 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1523 }
1524 #endif
1525
1526 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1527 MacroAssembler _masm(&cbuf);
1528 for (int i = 0; i < _count; i += 1) {
1529 __ nop();
1530 }
1531 }
1532
1533 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1534 return 4 * _count;
1535 }
1536
1537
1538 //=============================================================================
1539 #ifndef PRODUCT
1540 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 int reg = ra_->get_reg_first(this);
1543 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1544 }
1545 #endif
1546
1547 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1548 MacroAssembler _masm(&cbuf);
1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1550 int reg = ra_->get_encode(this);
1551
1552 if (Assembler::is_simm13(offset)) {
1553 __ add(SP, offset, reg_to_register_object(reg));
1554 } else {
1555 __ set(offset, O7);
1556 __ add(SP, O7, reg_to_register_object(reg));
1557 }
1558 }
1559
1560 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1561 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1562 assert(ra_ == ra_->C->regalloc(), "sanity");
1563 return ra_->C->scratch_emit_size(this);
1564 }
1565
1566 //=============================================================================
1567 #ifndef PRODUCT
1568 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1569 st->print_cr("\nUEP:");
1570 if (UseCompressedClassPointers) {
1571 assert(Universe::heap() != NULL, "java heap should be initialized");
1572 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1573 if (Universe::narrow_klass_base() != 0) {
1574 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1575 if (Universe::narrow_klass_shift() != 0) {
1576 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1577 }
1578 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1579 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1580 } else {
1581 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1582 }
1583 } else {
1584 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1585 }
1586 st->print_cr("\tCMP R_G5,R_G3" );
1587 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1588 }
1589 #endif
1590
1591 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1592 MacroAssembler _masm(&cbuf);
1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1594 Register temp_reg = G3;
1595 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1596
1597 // Load klass from receiver
1598 __ load_klass(O0, temp_reg);
1599 // Compare against expected klass
1600 __ cmp(temp_reg, G5_ic_reg);
1601 // Branch to miss code, checks xcc or icc depending
1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1603 }
1604
1605 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1606 return MachNode::size(ra_);
1607 }
1608
1609
1610 //=============================================================================
1611
1612
1613 // Emit exception handler code.
1614 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1615 Register temp_reg = G3;
1616 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1617 MacroAssembler _masm(&cbuf);
1618
1619 address base = __ start_a_stub(size_exception_handler());
1620 if (base == NULL) {
1621 ciEnv::current()->record_failure("CodeCache is full");
1622 return 0; // CodeBuffer::expand failed
1623 }
1624
1625 int offset = __ offset();
1626
1627 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1628 __ delayed()->nop();
1629
1630 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1631
1632 __ end_a_stub();
1633
1634 return offset;
1635 }
1636
1637 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1638 // Can't use any of the current frame's registers as we may have deopted
1639 // at a poll and everything (including G3) can be live.
1640 Register temp_reg = L0;
1641 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1642 MacroAssembler _masm(&cbuf);
1643
1644 address base = __ start_a_stub(size_deopt_handler());
1645 if (base == NULL) {
1646 ciEnv::current()->record_failure("CodeCache is full");
1647 return 0; // CodeBuffer::expand failed
1648 }
1649
1650 int offset = __ offset();
1651 __ save_frame(0);
1652 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1653 __ delayed()->restore();
1654
1655 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1656
1657 __ end_a_stub();
1658 return offset;
1659
1660 }
1661
1662 // Given a register encoding, produce a Integer Register object
1663 static Register reg_to_register_object(int register_encoding) {
1664 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1665 return as_Register(register_encoding);
1666 }
1667
1668 // Given a register encoding, produce a single-precision Float Register object
1669 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1670 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1671 return as_SingleFloatRegister(register_encoding);
1672 }
1673
1674 // Given a register encoding, produce a double-precision Float Register object
1675 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1676 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1677 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1678 return as_DoubleFloatRegister(register_encoding);
1679 }
1680
1681 const bool Matcher::match_rule_supported(int opcode) {
1682 if (!has_match_rule(opcode))
1683 return false;
1684
1685 switch (opcode) {
1686 case Op_CountLeadingZerosI:
1687 case Op_CountLeadingZerosL:
1688 case Op_CountTrailingZerosI:
1689 case Op_CountTrailingZerosL:
1690 case Op_PopCountI:
1691 case Op_PopCountL:
1692 if (!UsePopCountInstruction)
1693 return false;
1694 case Op_CompareAndSwapL:
1695 case Op_CompareAndSwapP:
1696 if (!VM_Version::supports_cx8())
1697 return false;
1698 break;
1699 }
1700
1701 return true; // Per default match rules are supported.
1702 }
1703
1704 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1705
1706 // TODO
1707 // identify extra cases that we might want to provide match rules for
1708 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1709 bool ret_value = match_rule_supported(opcode);
1710 // Add rules here.
1711
1712 return ret_value; // Per default match rules are supported.
1713 }
1714
1715 const bool Matcher::has_predicated_vectors(void) {
1716 return false;
1717 }
1718
1719 const int Matcher::float_pressure(int default_pressure_threshold) {
1720 return default_pressure_threshold;
1721 }
1722
1723 int Matcher::regnum_to_fpu_offset(int regnum) {
1724 return regnum - 32; // The FP registers are in the second chunk
1725 }
1726
1727 #ifdef ASSERT
1728 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1729 #endif
1730
1731 // Vector width in bytes
1732 const int Matcher::vector_width_in_bytes(BasicType bt) {
1733 assert(MaxVectorSize == 8, "");
1734 return 8;
1735 }
1736
1737 // Vector ideal reg
1738 const uint Matcher::vector_ideal_reg(int size) {
1739 assert(MaxVectorSize == 8, "");
1740 return Op_RegD;
1741 }
1742
1743 const uint Matcher::vector_shift_count_ideal_reg(int size) {
1744 fatal("vector shift is not supported");
1745 return Node::NotAMachineReg;
1746 }
1747
1748 // Limits on vector size (number of elements) loaded into vector.
1749 const int Matcher::max_vector_size(const BasicType bt) {
1750 assert(is_java_primitive(bt), "only primitive type vectors");
1751 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1752 }
1753
1754 const int Matcher::min_vector_size(const BasicType bt) {
1755 return max_vector_size(bt); // Same as max.
1756 }
1757
1758 // SPARC doesn't support misaligned vectors store/load.
1759 const bool Matcher::misaligned_vectors_ok() {
1760 return false;
1761 }
1762
1763 // Current (2013) SPARC platforms need to read original key
1764 // to construct decryption expanded key
1765 const bool Matcher::pass_original_key_for_aes() {
1766 return true;
1767 }
1768
1769 // NOTE: All currently supported SPARC HW provides fast conversion.
1770 const bool Matcher::convL2FSupported(void) { return true; }
1771
1772 // Is this branch offset short enough that a short branch can be used?
1773 //
1774 // NOTE: If the platform does not provide any short branch variants, then
1775 // this method should return false for offset 0.
1776 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1777 // The passed offset is relative to address of the branch.
1778 // Don't need to adjust the offset.
1779 return UseCBCond && Assembler::is_simm12(offset);
1780 }
1781
1782 const bool Matcher::isSimpleConstant64(jlong value) {
1783 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1784 // Depends on optimizations in MacroAssembler::setx.
1785 int hi = (int)(value >> 32);
1786 int lo = (int)(value & ~0);
1787 return (hi == 0) || (hi == -1) || (lo == 0);
1788 }
1789
1790 // No scaling for the parameter the ClearArray node.
1791 const bool Matcher::init_array_count_is_in_bytes = true;
1792
1793 // No additional cost for CMOVL.
1794 const int Matcher::long_cmove_cost() { return 0; }
1795
1796 // CMOVF/CMOVD are expensive on e.g., T4 and SPARC64.
1797 const int Matcher::float_cmove_cost() {
1798 return VM_Version::has_fast_cmove() ? 0 : ConditionalMoveLimit;
1799 }
1800
1801 // Does the CPU require late expand (see block.cpp for description of late expand)?
1802 const bool Matcher::require_postalloc_expand = false;
1803
1804 // Do we need to mask the count passed to shift instructions or does
1805 // the cpu only look at the lower 5/6 bits anyway?
1806 const bool Matcher::need_masked_shift_count = false;
1807
1808 bool Matcher::narrow_oop_use_complex_address() {
1809 assert(UseCompressedOops, "only for compressed oops code");
1810 return false;
1811 }
1812
1813 bool Matcher::narrow_klass_use_complex_address() {
1814 assert(UseCompressedClassPointers, "only for compressed klass code");
1815 return false;
1816 }
1817
1818 bool Matcher::const_oop_prefer_decode() {
1819 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1820 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1821 // return Universe::narrow_oop_base() == NULL;
1822 return true;
1823 }
1824
1825 bool Matcher::const_klass_prefer_decode() {
1826 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1827 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1828 // return Universe::narrow_klass_base() == NULL;
1829 return true;
1830 }
1831
1832 // Is it better to copy float constants, or load them directly from memory?
1833 // Intel can load a float constant from a direct address, requiring no
1834 // extra registers. Most RISCs will have to materialize an address into a
1835 // register first, so they would do better to copy the constant from stack.
1836 const bool Matcher::rematerialize_float_constants = false;
1837
1838 // If CPU can load and store mis-aligned doubles directly then no fixup is
1839 // needed. Else we split the double into 2 integer pieces and move it
1840 // piece-by-piece. Only happens when passing doubles into C code as the
1841 // Java calling convention forces doubles to be aligned.
1842 const bool Matcher::misaligned_doubles_ok = true;
1843
1844 // No-op on SPARC.
1845 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1846 }
1847
1848 // Advertise here if the CPU requires explicit rounding operations
1849 // to implement the UseStrictFP mode.
1850 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1851
1852 // Are floats converted to double when stored to stack during deoptimization?
1853 // Sparc does not handle callee-save floats.
1854 bool Matcher::float_in_double() { return false; }
1855
1856 // Do ints take an entire long register or just half?
1857 // Note that we if-def off of _LP64.
1858 // The relevant question is how the int is callee-saved. In _LP64
1859 // the whole long is written but de-opt'ing will have to extract
1860 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1861 const bool Matcher::int_in_long = true;
1862
1863 // Return whether or not this register is ever used as an argument. This
1864 // function is used on startup to build the trampoline stubs in generateOptoStub.
1865 // Registers not mentioned will be killed by the VM call in the trampoline, and
1866 // arguments in those registers not be available to the callee.
1867 bool Matcher::can_be_java_arg( int reg ) {
1868 // Standard sparc 6 args in registers
1869 if( reg == R_I0_num ||
1870 reg == R_I1_num ||
1871 reg == R_I2_num ||
1872 reg == R_I3_num ||
1873 reg == R_I4_num ||
1874 reg == R_I5_num ) return true;
1875 // 64-bit builds can pass 64-bit pointers and longs in
1876 // the high I registers
1877 if( reg == R_I0H_num ||
1878 reg == R_I1H_num ||
1879 reg == R_I2H_num ||
1880 reg == R_I3H_num ||
1881 reg == R_I4H_num ||
1882 reg == R_I5H_num ) return true;
1883
1884 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1885 return true;
1886 }
1887
1888 // A few float args in registers
1889 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1890
1891 return false;
1892 }
1893
1894 bool Matcher::is_spillable_arg( int reg ) {
1895 return can_be_java_arg(reg);
1896 }
1897
1898 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1899 // Use hardware SDIVX instruction when it is
1900 // faster than a code which use multiply.
1901 return VM_Version::has_fast_idiv();
1902 }
1903
1904 // Register for DIVI projection of divmodI
1905 RegMask Matcher::divI_proj_mask() {
1906 ShouldNotReachHere();
1907 return RegMask();
1908 }
1909
1910 // Register for MODI projection of divmodI
1911 RegMask Matcher::modI_proj_mask() {
1912 ShouldNotReachHere();
1913 return RegMask();
1914 }
1915
1916 // Register for DIVL projection of divmodL
1917 RegMask Matcher::divL_proj_mask() {
1918 ShouldNotReachHere();
1919 return RegMask();
1920 }
1921
1922 // Register for MODL projection of divmodL
1923 RegMask Matcher::modL_proj_mask() {
1924 ShouldNotReachHere();
1925 return RegMask();
1926 }
1927
1928 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1929 return L7_REGP_mask();
1930 }
1931
1932
1933 const bool Matcher::convi2l_type_required = true;
1934
1935 // Should the Matcher clone shifts on addressing modes, expecting them
1936 // to be subsumed into complex addressing expressions or compute them
1937 // into registers?
1938 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1939 return clone_base_plus_offset_address(m, mstack, address_visited);
1940 }
1941
1942 void Compile::reshape_address(AddPNode* addp) {
1943 }
1944
1945 %}
1946
1947
1948 // The intptr_t operand types, defined by textual substitution.
1949 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1950 #define immX immL
1951 #define immX13 immL13
1952 #define immX13m7 immL13m7
1953 #define iRegX iRegL
1954 #define g1RegX g1RegL
1955
1956 //----------ENCODING BLOCK-----------------------------------------------------
1957 // This block specifies the encoding classes used by the compiler to output
1958 // byte streams. Encoding classes are parameterized macros used by
1959 // Machine Instruction Nodes in order to generate the bit encoding of the
1960 // instruction. Operands specify their base encoding interface with the
1961 // interface keyword. There are currently supported four interfaces,
1962 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1963 // operand to generate a function which returns its register number when
1964 // queried. CONST_INTER causes an operand to generate a function which
1965 // returns the value of the constant when queried. MEMORY_INTER causes an
1966 // operand to generate four functions which return the Base Register, the
1967 // Index Register, the Scale Value, and the Offset Value of the operand when
1968 // queried. COND_INTER causes an operand to generate six functions which
1969 // return the encoding code (ie - encoding bits for the instruction)
1970 // associated with each basic boolean condition for a conditional instruction.
1971 //
1972 // Instructions specify two basic values for encoding. Again, a function
1973 // is available to check if the constant displacement is an oop. They use the
1974 // ins_encode keyword to specify their encoding classes (which must be
1975 // a sequence of enc_class names, and their parameters, specified in
1976 // the encoding block), and they use the
1977 // opcode keyword to specify, in order, their primary, secondary, and
1978 // tertiary opcode. Only the opcode sections which a particular instruction
1979 // needs for encoding need to be specified.
1980 encode %{
1981 enc_class enc_untested %{
1982 #ifdef ASSERT
1983 MacroAssembler _masm(&cbuf);
1984 __ untested("encoding");
1985 #endif
1986 %}
1987
1988 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1989 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
1990 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1991 %}
1992
1993 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1994 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1995 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1996 %}
1997
1998 enc_class form3_mem_prefetch_read( memory mem ) %{
1999 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2000 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2001 %}
2002
2003 enc_class form3_mem_prefetch_write( memory mem ) %{
2004 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2005 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2006 %}
2007
2008 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2009 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2010 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2011 guarantee($mem$$index == R_G0_enc, "double index?");
2012 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2013 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2014 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2015 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2016 %}
2017
2018 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2019 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2020 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2021 guarantee($mem$$index == R_G0_enc, "double index?");
2022 // Load long with 2 instructions
2023 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2024 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2025 %}
2026
2027 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2028 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2029 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2030 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2031 %}
2032
2033 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2034 // Encode a reg-reg copy. If it is useless, then empty encoding.
2035 if( $rs2$$reg != $rd$$reg )
2036 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2037 %}
2038
2039 // Target lo half of long
2040 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2041 // Encode a reg-reg copy. If it is useless, then empty encoding.
2042 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2043 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2044 %}
2045
2046 // Source lo half of long
2047 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2048 // Encode a reg-reg copy. If it is useless, then empty encoding.
2049 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2050 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2051 %}
2052
2053 // Target hi half of long
2054 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2055 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2056 %}
2057
2058 // Source lo half of long, and leave it sign extended.
2059 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2060 // Sign extend low half
2061 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2062 %}
2063
2064 // Source hi half of long, and leave it sign extended.
2065 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2066 // Shift high half to low half
2067 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2068 %}
2069
2070 // Source hi half of long
2071 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2072 // Encode a reg-reg copy. If it is useless, then empty encoding.
2073 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2074 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2075 %}
2076
2077 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2078 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2079 %}
2080
2081 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2082 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2083 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2084 %}
2085
2086 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2087 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2088 // clear if nothing else is happening
2089 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2090 // blt,a,pn done
2091 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2092 // mov dst,-1 in delay slot
2093 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2094 %}
2095
2096 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2097 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2098 %}
2099
2100 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2101 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2102 %}
2103
2104 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2105 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2106 %}
2107
2108 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2109 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2110 %}
2111
2112 enc_class move_return_pc_to_o1() %{
2113 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2114 %}
2115
2116 /* %%% merge with enc_to_bool */
2117 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2118 MacroAssembler _masm(&cbuf);
2119
2120 Register src_reg = reg_to_register_object($src$$reg);
2121 Register dst_reg = reg_to_register_object($dst$$reg);
2122 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2123 %}
2124
2125 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2126 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2127 MacroAssembler _masm(&cbuf);
2128
2129 Register p_reg = reg_to_register_object($p$$reg);
2130 Register q_reg = reg_to_register_object($q$$reg);
2131 Register y_reg = reg_to_register_object($y$$reg);
2132 Register tmp_reg = reg_to_register_object($tmp$$reg);
2133
2134 __ subcc( p_reg, q_reg, p_reg );
2135 __ add ( p_reg, y_reg, tmp_reg );
2136 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2137 %}
2138
2139 enc_class form_d2i_helper(regD src, regF dst) %{
2140 // fcmp %fcc0,$src,$src
2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2142 // branch %fcc0 not-nan, predict taken
2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2144 // fdtoi $src,$dst
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2146 // fitos $dst,$dst (if nan)
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2148 // clear $dst (if nan)
2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2150 // carry on here...
2151 %}
2152
2153 enc_class form_d2l_helper(regD src, regD dst) %{
2154 // fcmp %fcc0,$src,$src check for NAN
2155 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2156 // branch %fcc0 not-nan, predict taken
2157 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2158 // fdtox $src,$dst convert in delay slot
2159 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2160 // fxtod $dst,$dst (if nan)
2161 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2162 // clear $dst (if nan)
2163 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2164 // carry on here...
2165 %}
2166
2167 enc_class form_f2i_helper(regF src, regF dst) %{
2168 // fcmps %fcc0,$src,$src
2169 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2170 // branch %fcc0 not-nan, predict taken
2171 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2172 // fstoi $src,$dst
2173 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2174 // fitos $dst,$dst (if nan)
2175 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2176 // clear $dst (if nan)
2177 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2178 // carry on here...
2179 %}
2180
2181 enc_class form_f2l_helper(regF src, regD dst) %{
2182 // fcmps %fcc0,$src,$src
2183 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2184 // branch %fcc0 not-nan, predict taken
2185 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2186 // fstox $src,$dst
2187 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2188 // fxtod $dst,$dst (if nan)
2189 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2190 // clear $dst (if nan)
2191 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2192 // carry on here...
2193 %}
2194
2195 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2196 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2197 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2198 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2199
2200 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2201
2202 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2203 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2204
2205 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2206 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2207 %}
2208
2209 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2210 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2211 %}
2212
2213 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2214 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2215 %}
2216
2217 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2218 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2219 %}
2220
2221 enc_class form3_convI2F(regF rs2, regF rd) %{
2222 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2223 %}
2224
2225 // Encloding class for traceable jumps
2226 enc_class form_jmpl(g3RegP dest) %{
2227 emit_jmpl(cbuf, $dest$$reg);
2228 %}
2229
2230 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2231 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2232 %}
2233
2234 enc_class form2_nop() %{
2235 emit_nop(cbuf);
2236 %}
2237
2238 enc_class form2_illtrap() %{
2239 emit_illtrap(cbuf);
2240 %}
2241
2242
2243 // Compare longs and convert into -1, 0, 1.
2244 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2245 // CMP $src1,$src2
2246 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2247 // blt,a,pn done
2248 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2249 // mov dst,-1 in delay slot
2250 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2251 // bgt,a,pn done
2252 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2253 // mov dst,1 in delay slot
2254 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2255 // CLR $dst
2256 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2257 %}
2258
2259 enc_class enc_PartialSubtypeCheck() %{
2260 MacroAssembler _masm(&cbuf);
2261 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2262 __ delayed()->nop();
2263 %}
2264
2265 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2266 MacroAssembler _masm(&cbuf);
2267 Label* L = $labl$$label;
2268 Assembler::Predict predict_taken =
2269 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2270
2271 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2272 __ delayed()->nop();
2273 %}
2274
2275 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2276 MacroAssembler _masm(&cbuf);
2277 Label* L = $labl$$label;
2278 Assembler::Predict predict_taken =
2279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2280
2281 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2282 __ delayed()->nop();
2283 %}
2284
2285 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2286 int op = (Assembler::arith_op << 30) |
2287 ($dst$$reg << 25) |
2288 (Assembler::movcc_op3 << 19) |
2289 (1 << 18) | // cc2 bit for 'icc'
2290 ($cmp$$cmpcode << 14) |
2291 (0 << 13) | // select register move
2292 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2293 ($src$$reg << 0);
2294 cbuf.insts()->emit_int32(op);
2295 %}
2296
2297 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2298 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2299 int op = (Assembler::arith_op << 30) |
2300 ($dst$$reg << 25) |
2301 (Assembler::movcc_op3 << 19) |
2302 (1 << 18) | // cc2 bit for 'icc'
2303 ($cmp$$cmpcode << 14) |
2304 (1 << 13) | // select immediate move
2305 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2306 (simm11 << 0);
2307 cbuf.insts()->emit_int32(op);
2308 %}
2309
2310 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2311 int op = (Assembler::arith_op << 30) |
2312 ($dst$$reg << 25) |
2313 (Assembler::movcc_op3 << 19) |
2314 (0 << 18) | // cc2 bit for 'fccX'
2315 ($cmp$$cmpcode << 14) |
2316 (0 << 13) | // select register move
2317 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2318 ($src$$reg << 0);
2319 cbuf.insts()->emit_int32(op);
2320 %}
2321
2322 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2323 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2324 int op = (Assembler::arith_op << 30) |
2325 ($dst$$reg << 25) |
2326 (Assembler::movcc_op3 << 19) |
2327 (0 << 18) | // cc2 bit for 'fccX'
2328 ($cmp$$cmpcode << 14) |
2329 (1 << 13) | // select immediate move
2330 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2331 (simm11 << 0);
2332 cbuf.insts()->emit_int32(op);
2333 %}
2334
2335 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2336 int op = (Assembler::arith_op << 30) |
2337 ($dst$$reg << 25) |
2338 (Assembler::fpop2_op3 << 19) |
2339 (0 << 18) |
2340 ($cmp$$cmpcode << 14) |
2341 (1 << 13) | // select register move
2342 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2343 ($primary << 5) | // select single, double or quad
2344 ($src$$reg << 0);
2345 cbuf.insts()->emit_int32(op);
2346 %}
2347
2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2349 int op = (Assembler::arith_op << 30) |
2350 ($dst$$reg << 25) |
2351 (Assembler::fpop2_op3 << 19) |
2352 (0 << 18) |
2353 ($cmp$$cmpcode << 14) |
2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2355 ($primary << 5) | // select single, double or quad
2356 ($src$$reg << 0);
2357 cbuf.insts()->emit_int32(op);
2358 %}
2359
2360 // Used by the MIN/MAX encodings. Same as a CMOV, but
2361 // the condition comes from opcode-field instead of an argument.
2362 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2363 int op = (Assembler::arith_op << 30) |
2364 ($dst$$reg << 25) |
2365 (Assembler::movcc_op3 << 19) |
2366 (1 << 18) | // cc2 bit for 'icc'
2367 ($primary << 14) |
2368 (0 << 13) | // select register move
2369 (0 << 11) | // cc1, cc0 bits for 'icc'
2370 ($src$$reg << 0);
2371 cbuf.insts()->emit_int32(op);
2372 %}
2373
2374 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2375 int op = (Assembler::arith_op << 30) |
2376 ($dst$$reg << 25) |
2377 (Assembler::movcc_op3 << 19) |
2378 (6 << 16) | // cc2 bit for 'xcc'
2379 ($primary << 14) |
2380 (0 << 13) | // select register move
2381 (0 << 11) | // cc1, cc0 bits for 'icc'
2382 ($src$$reg << 0);
2383 cbuf.insts()->emit_int32(op);
2384 %}
2385
2386 enc_class Set13( immI13 src, iRegI rd ) %{
2387 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2388 %}
2389
2390 enc_class SetHi22( immI src, iRegI rd ) %{
2391 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2392 %}
2393
2394 enc_class Set32( immI src, iRegI rd ) %{
2395 MacroAssembler _masm(&cbuf);
2396 __ set($src$$constant, reg_to_register_object($rd$$reg));
2397 %}
2398
2399 enc_class call_epilog %{
2400 if( VerifyStackAtCalls ) {
2401 MacroAssembler _masm(&cbuf);
2402 int framesize = ra_->C->frame_size_in_bytes();
2403 Register temp_reg = G3;
2404 __ add(SP, framesize, temp_reg);
2405 __ cmp(temp_reg, FP);
2406 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2407 }
2408 %}
2409
2410 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2411 // to G1 so the register allocator will not have to deal with the misaligned register
2412 // pair.
2413 enc_class adjust_long_from_native_call %{
2414 %}
2415
2416 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2417 // CALL directly to the runtime
2418 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2419 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2420 %}
2421
2422 enc_class preserve_SP %{
2423 MacroAssembler _masm(&cbuf);
2424 __ mov(SP, L7_mh_SP_save);
2425 %}
2426
2427 enc_class restore_SP %{
2428 MacroAssembler _masm(&cbuf);
2429 __ mov(L7_mh_SP_save, SP);
2430 %}
2431
2432 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2433 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2434 // who we intended to call.
2435 if (!_method) {
2436 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2437 } else {
2438 int method_index = resolved_method_index(cbuf);
2439 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2440 : static_call_Relocation::spec(method_index);
2441 emit_call_reloc(cbuf, $meth$$method, rspec);
2442
2443 // Emit stub for static call.
2444 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2445 if (stub == NULL) {
2446 ciEnv::current()->record_failure("CodeCache is full");
2447 return;
2448 }
2449 }
2450 %}
2451
2452 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2453 MacroAssembler _masm(&cbuf);
2454 __ set_inst_mark();
2455 int vtable_index = this->_vtable_index;
2456 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2457 if (vtable_index < 0) {
2458 // must be invalid_vtable_index, not nonvirtual_vtable_index
2459 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2460 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2461 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2462 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2463 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2464 } else {
2465 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2466 // Just go thru the vtable
2467 // get receiver klass (receiver already checked for non-null)
2468 // If we end up going thru a c2i adapter interpreter expects method in G5
2469 int off = __ offset();
2470 __ load_klass(O0, G3_scratch);
2471 int klass_load_size;
2472 if (UseCompressedClassPointers) {
2473 assert(Universe::heap() != NULL, "java heap should be initialized");
2474 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2475 } else {
2476 klass_load_size = 1*BytesPerInstWord;
2477 }
2478 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2479 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2480 if (Assembler::is_simm13(v_off)) {
2481 __ ld_ptr(G3, v_off, G5_method);
2482 } else {
2483 // Generate 2 instructions
2484 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2485 __ or3(G5_method, v_off & 0x3ff, G5_method);
2486 // ld_ptr, set_hi, set
2487 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2488 "Unexpected instruction size(s)");
2489 __ ld_ptr(G3, G5_method, G5_method);
2490 }
2491 // NOTE: for vtable dispatches, the vtable entry will never be null.
2492 // However it may very well end up in handle_wrong_method if the
2493 // method is abstract for the particular class.
2494 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2495 // jump to target (either compiled code or c2iadapter)
2496 __ jmpl(G3_scratch, G0, O7);
2497 __ delayed()->nop();
2498 }
2499 %}
2500
2501 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2502 MacroAssembler _masm(&cbuf);
2503
2504 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2505 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2506 // we might be calling a C2I adapter which needs it.
2507
2508 assert(temp_reg != G5_ic_reg, "conflicting registers");
2509 // Load nmethod
2510 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2511
2512 // CALL to compiled java, indirect the contents of G3
2513 __ set_inst_mark();
2514 __ callr(temp_reg, G0);
2515 __ delayed()->nop();
2516 %}
2517
2518 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2519 MacroAssembler _masm(&cbuf);
2520 Register Rdividend = reg_to_register_object($src1$$reg);
2521 Register Rdivisor = reg_to_register_object($src2$$reg);
2522 Register Rresult = reg_to_register_object($dst$$reg);
2523
2524 __ sra(Rdivisor, 0, Rdivisor);
2525 __ sra(Rdividend, 0, Rdividend);
2526 __ sdivx(Rdividend, Rdivisor, Rresult);
2527 %}
2528
2529 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2530 MacroAssembler _masm(&cbuf);
2531
2532 Register Rdividend = reg_to_register_object($src1$$reg);
2533 int divisor = $imm$$constant;
2534 Register Rresult = reg_to_register_object($dst$$reg);
2535
2536 __ sra(Rdividend, 0, Rdividend);
2537 __ sdivx(Rdividend, divisor, Rresult);
2538 %}
2539
2540 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2541 MacroAssembler _masm(&cbuf);
2542 Register Rsrc1 = reg_to_register_object($src1$$reg);
2543 Register Rsrc2 = reg_to_register_object($src2$$reg);
2544 Register Rdst = reg_to_register_object($dst$$reg);
2545
2546 __ sra( Rsrc1, 0, Rsrc1 );
2547 __ sra( Rsrc2, 0, Rsrc2 );
2548 __ mulx( Rsrc1, Rsrc2, Rdst );
2549 __ srlx( Rdst, 32, Rdst );
2550 %}
2551
2552 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2553 MacroAssembler _masm(&cbuf);
2554 Register Rdividend = reg_to_register_object($src1$$reg);
2555 Register Rdivisor = reg_to_register_object($src2$$reg);
2556 Register Rresult = reg_to_register_object($dst$$reg);
2557 Register Rscratch = reg_to_register_object($scratch$$reg);
2558
2559 assert(Rdividend != Rscratch, "");
2560 assert(Rdivisor != Rscratch, "");
2561
2562 __ sra(Rdividend, 0, Rdividend);
2563 __ sra(Rdivisor, 0, Rdivisor);
2564 __ sdivx(Rdividend, Rdivisor, Rscratch);
2565 __ mulx(Rscratch, Rdivisor, Rscratch);
2566 __ sub(Rdividend, Rscratch, Rresult);
2567 %}
2568
2569 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2570 MacroAssembler _masm(&cbuf);
2571
2572 Register Rdividend = reg_to_register_object($src1$$reg);
2573 int divisor = $imm$$constant;
2574 Register Rresult = reg_to_register_object($dst$$reg);
2575 Register Rscratch = reg_to_register_object($scratch$$reg);
2576
2577 assert(Rdividend != Rscratch, "");
2578
2579 __ sra(Rdividend, 0, Rdividend);
2580 __ sdivx(Rdividend, divisor, Rscratch);
2581 __ mulx(Rscratch, divisor, Rscratch);
2582 __ sub(Rdividend, Rscratch, Rresult);
2583 %}
2584
2585 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2586 MacroAssembler _masm(&cbuf);
2587
2588 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2589 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2590
2591 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2592 %}
2593
2594 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2595 MacroAssembler _masm(&cbuf);
2596
2597 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2598 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2599
2600 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2601 %}
2602
2603 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2604 MacroAssembler _masm(&cbuf);
2605
2606 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2607 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2608
2609 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2610 %}
2611
2612 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2613 MacroAssembler _masm(&cbuf);
2614
2615 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2616 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2617
2618 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2619 %}
2620
2621 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2622 MacroAssembler _masm(&cbuf);
2623
2624 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2625 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2626
2627 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2628 %}
2629
2630
2631 enc_class fmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2632 MacroAssembler _masm(&cbuf);
2633
2634 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2635 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2636 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2637 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2638
2639 __ fmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2640 %}
2641
2642 enc_class fmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2643 MacroAssembler _masm(&cbuf);
2644
2645 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2646 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2647 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2648 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2649
2650 __ fmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2651 %}
2652
2653 enc_class fmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2654 MacroAssembler _masm(&cbuf);
2655
2656 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2657 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2658 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2659 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2660
2661 __ fmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2662 %}
2663
2664 enc_class fmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2665 MacroAssembler _masm(&cbuf);
2666
2667 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2668 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2669 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2670 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2671
2672 __ fmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2673 %}
2674
2675 enc_class fnmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2676 MacroAssembler _masm(&cbuf);
2677
2678 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2679 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2680 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2681 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2682
2683 __ fnmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2684 %}
2685
2686 enc_class fnmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2687 MacroAssembler _masm(&cbuf);
2688
2689 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2690 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2691 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2692 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2693
2694 __ fnmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2695 %}
2696
2697 enc_class fnmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2698 MacroAssembler _masm(&cbuf);
2699
2700 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2701 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2702 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2703 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2704
2705 __ fnmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2706 %}
2707
2708 enc_class fnmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2709 MacroAssembler _masm(&cbuf);
2710
2711 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2712 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2713 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2714 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2715
2716 __ fnmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2717 %}
2718
2719
2720 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2721 MacroAssembler _masm(&cbuf);
2722
2723 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2724 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2725
2726 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2727 %}
2728
2729 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2730 MacroAssembler _masm(&cbuf);
2731
2732 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2733 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2734
2735 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2736 %}
2737
2738 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2739 MacroAssembler _masm(&cbuf);
2740
2741 Register Roop = reg_to_register_object($oop$$reg);
2742 Register Rbox = reg_to_register_object($box$$reg);
2743 Register Rscratch = reg_to_register_object($scratch$$reg);
2744 Register Rmark = reg_to_register_object($scratch2$$reg);
2745
2746 assert(Roop != Rscratch, "");
2747 assert(Roop != Rmark, "");
2748 assert(Rbox != Rscratch, "");
2749 assert(Rbox != Rmark, "");
2750
2751 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2752 %}
2753
2754 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2755 MacroAssembler _masm(&cbuf);
2756
2757 Register Roop = reg_to_register_object($oop$$reg);
2758 Register Rbox = reg_to_register_object($box$$reg);
2759 Register Rscratch = reg_to_register_object($scratch$$reg);
2760 Register Rmark = reg_to_register_object($scratch2$$reg);
2761
2762 assert(Roop != Rscratch, "");
2763 assert(Roop != Rmark, "");
2764 assert(Rbox != Rscratch, "");
2765 assert(Rbox != Rmark, "");
2766
2767 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2768 %}
2769
2770 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2771 MacroAssembler _masm(&cbuf);
2772 Register Rmem = reg_to_register_object($mem$$reg);
2773 Register Rold = reg_to_register_object($old$$reg);
2774 Register Rnew = reg_to_register_object($new$$reg);
2775
2776 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2777 __ cmp( Rold, Rnew );
2778 %}
2779
2780 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2781 Register Rmem = reg_to_register_object($mem$$reg);
2782 Register Rold = reg_to_register_object($old$$reg);
2783 Register Rnew = reg_to_register_object($new$$reg);
2784
2785 MacroAssembler _masm(&cbuf);
2786 __ mov(Rnew, O7);
2787 __ casx(Rmem, Rold, O7);
2788 __ cmp( Rold, O7 );
2789 %}
2790
2791 // raw int cas, used for compareAndSwap
2792 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2793 Register Rmem = reg_to_register_object($mem$$reg);
2794 Register Rold = reg_to_register_object($old$$reg);
2795 Register Rnew = reg_to_register_object($new$$reg);
2796
2797 MacroAssembler _masm(&cbuf);
2798 __ mov(Rnew, O7);
2799 __ cas(Rmem, Rold, O7);
2800 __ cmp( Rold, O7 );
2801 %}
2802
2803 // raw int cas without using tmp register for compareAndExchange
2804 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{
2805 Register Rmem = reg_to_register_object($mem$$reg);
2806 Register Rold = reg_to_register_object($old$$reg);
2807 Register Rnew = reg_to_register_object($new$$reg);
2808
2809 MacroAssembler _masm(&cbuf);
2810 __ cas(Rmem, Rold, Rnew);
2811 %}
2812
2813 // 64-bit cas without using tmp register for compareAndExchange
2814 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{
2815 Register Rmem = reg_to_register_object($mem$$reg);
2816 Register Rold = reg_to_register_object($old$$reg);
2817 Register Rnew = reg_to_register_object($new$$reg);
2818
2819 MacroAssembler _masm(&cbuf);
2820 __ casx(Rmem, Rold, Rnew);
2821 %}
2822
2823 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2824 Register Rres = reg_to_register_object($res$$reg);
2825
2826 MacroAssembler _masm(&cbuf);
2827 __ mov(1, Rres);
2828 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2829 %}
2830
2831 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2832 Register Rres = reg_to_register_object($res$$reg);
2833
2834 MacroAssembler _masm(&cbuf);
2835 __ mov(1, Rres);
2836 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2837 %}
2838
2839 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2840 MacroAssembler _masm(&cbuf);
2841 Register Rdst = reg_to_register_object($dst$$reg);
2842 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2843 : reg_to_DoubleFloatRegister_object($src1$$reg);
2844 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2845 : reg_to_DoubleFloatRegister_object($src2$$reg);
2846
2847 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2848 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2849 %}
2850
2851 enc_class enc_rethrow() %{
2852 cbuf.set_insts_mark();
2853 Register temp_reg = G3;
2854 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2855 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2856 MacroAssembler _masm(&cbuf);
2857 #ifdef ASSERT
2858 __ save_frame(0);
2859 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2860 __ sethi(last_rethrow_addrlit, L1);
2861 Address addr(L1, last_rethrow_addrlit.low10());
2862 __ rdpc(L2);
2863 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2864 __ st_ptr(L2, addr);
2865 __ restore();
2866 #endif
2867 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2868 __ delayed()->nop();
2869 %}
2870
2871 enc_class emit_mem_nop() %{
2872 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2873 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2874 %}
2875
2876 enc_class emit_fadd_nop() %{
2877 // Generates the instruction FMOVS f31,f31
2878 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2879 %}
2880
2881 enc_class emit_br_nop() %{
2882 // Generates the instruction BPN,PN .
2883 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2884 %}
2885
2886 enc_class enc_membar_acquire %{
2887 MacroAssembler _masm(&cbuf);
2888 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2889 %}
2890
2891 enc_class enc_membar_release %{
2892 MacroAssembler _masm(&cbuf);
2893 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2894 %}
2895
2896 enc_class enc_membar_volatile %{
2897 MacroAssembler _masm(&cbuf);
2898 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2899 %}
2900
2901 %}
2902
2903 //----------FRAME--------------------------------------------------------------
2904 // Definition of frame structure and management information.
2905 //
2906 // S T A C K L A Y O U T Allocators stack-slot number
2907 // | (to get allocators register number
2908 // G Owned by | | v add VMRegImpl::stack0)
2909 // r CALLER | |
2910 // o | +--------+ pad to even-align allocators stack-slot
2911 // w V | pad0 | numbers; owned by CALLER
2912 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2913 // h ^ | in | 5
2914 // | | args | 4 Holes in incoming args owned by SELF
2915 // | | | | 3
2916 // | | +--------+
2917 // V | | old out| Empty on Intel, window on Sparc
2918 // | old |preserve| Must be even aligned.
2919 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2920 // | | in | 3 area for Intel ret address
2921 // Owned by |preserve| Empty on Sparc.
2922 // SELF +--------+
2923 // | | pad2 | 2 pad to align old SP
2924 // | +--------+ 1
2925 // | | locks | 0
2926 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
2927 // | | pad1 | 11 pad to align new SP
2928 // | +--------+
2929 // | | | 10
2930 // | | spills | 9 spills
2931 // V | | 8 (pad0 slot for callee)
2932 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2933 // ^ | out | 7
2934 // | | args | 6 Holes in outgoing args owned by CALLEE
2935 // Owned by +--------+
2936 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2937 // | new |preserve| Must be even-aligned.
2938 // | SP-+--------+----> Matcher::_new_SP, even aligned
2939 // | | |
2940 //
2941 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2942 // known from SELF's arguments and the Java calling convention.
2943 // Region 6-7 is determined per call site.
2944 // Note 2: If the calling convention leaves holes in the incoming argument
2945 // area, those holes are owned by SELF. Holes in the outgoing area
2946 // are owned by the CALLEE. Holes should not be nessecary in the
2947 // incoming area, as the Java calling convention is completely under
2948 // the control of the AD file. Doubles can be sorted and packed to
2949 // avoid holes. Holes in the outgoing arguments may be necessary for
2950 // varargs C calling conventions.
2951 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2952 // even aligned with pad0 as needed.
2953 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2954 // region 6-11 is even aligned; it may be padded out more so that
2955 // the region from SP to FP meets the minimum stack alignment.
2956
2957 frame %{
2958 // What direction does stack grow in (assumed to be same for native & Java)
2959 stack_direction(TOWARDS_LOW);
2960
2961 // These two registers define part of the calling convention
2962 // between compiled code and the interpreter.
2963 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
2964 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
2965
2966 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2967 cisc_spilling_operand_name(indOffset);
2968
2969 // Number of stack slots consumed by a Monitor enter
2970 sync_stack_slots(2);
2971
2972 // Compiled code's Frame Pointer
2973 frame_pointer(R_SP);
2974
2975 // Stack alignment requirement
2976 stack_alignment(StackAlignmentInBytes);
2977 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
2978 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
2979
2980 // Number of stack slots between incoming argument block and the start of
2981 // a new frame. The PROLOG must add this many slots to the stack. The
2982 // EPILOG must remove this many slots.
2983 in_preserve_stack_slots(0);
2984
2985 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2986 // for calls to C. Supports the var-args backing area for register parms.
2987 // ADLC doesn't support parsing expressions, so I folded the math by hand.
2988 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
2989 varargs_C_out_slots_killed(12);
2990
2991 // The after-PROLOG location of the return address. Location of
2992 // return address specifies a type (REG or STACK) and a number
2993 // representing the register number (i.e. - use a register name) or
2994 // stack slot.
2995 return_addr(REG R_I7); // Ret Addr is in register I7
2996
2997 // Body of function which returns an OptoRegs array locating
2998 // arguments either in registers or in stack slots for calling
2999 // java
3000 calling_convention %{
3001 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3002
3003 %}
3004
3005 // Body of function which returns an OptoRegs array locating
3006 // arguments either in registers or in stack slots for calling
3007 // C.
3008 c_calling_convention %{
3009 // This is obviously always outgoing
3010 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3011 %}
3012
3013 // Location of native (C/C++) and interpreter return values. This is specified to
3014 // be the same as Java. In the 32-bit VM, long values are actually returned from
3015 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3016 // to and from the register pairs is done by the appropriate call and epilog
3017 // opcodes. This simplifies the register allocator.
3018 c_return_value %{
3019 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3020 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3021 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3022 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3023 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3024 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3025 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3026 %}
3027
3028 // Location of compiled Java return values. Same as C
3029 return_value %{
3030 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3031 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3032 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3033 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3034 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3035 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3036 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3037 %}
3038
3039 %}
3040
3041
3042 //----------ATTRIBUTES---------------------------------------------------------
3043 //----------Operand Attributes-------------------------------------------------
3044 op_attrib op_cost(1); // Required cost attribute
3045
3046 //----------Instruction Attributes---------------------------------------------
3047 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3048 ins_attrib ins_size(32); // Required size attribute (in bits)
3049
3050 // avoid_back_to_back attribute is an expression that must return
3051 // one of the following values defined in MachNode:
3052 // AVOID_NONE - instruction can be placed anywhere
3053 // AVOID_BEFORE - instruction cannot be placed after an
3054 // instruction with MachNode::AVOID_AFTER
3055 // AVOID_AFTER - the next instruction cannot be the one
3056 // with MachNode::AVOID_BEFORE
3057 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3058 // the same time
3059 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3060
3061 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3062 // non-matching short branch variant of some
3063 // long branch?
3064
3065 //----------OPERANDS-----------------------------------------------------------
3066 // Operand definitions must precede instruction definitions for correct parsing
3067 // in the ADLC because operands constitute user defined types which are used in
3068 // instruction definitions.
3069
3070 //----------Simple Operands----------------------------------------------------
3071 // Immediate Operands
3072 // Integer Immediate: 32-bit
3073 operand immI() %{
3074 match(ConI);
3075
3076 op_cost(0);
3077 // formats are generated automatically for constants and base registers
3078 format %{ %}
3079 interface(CONST_INTER);
3080 %}
3081
3082 // Integer Immediate: 0-bit
3083 operand immI0() %{
3084 predicate(n->get_int() == 0);
3085 match(ConI);
3086 op_cost(0);
3087
3088 format %{ %}
3089 interface(CONST_INTER);
3090 %}
3091
3092 // Integer Immediate: 5-bit
3093 operand immI5() %{
3094 predicate(Assembler::is_simm5(n->get_int()));
3095 match(ConI);
3096 op_cost(0);
3097 format %{ %}
3098 interface(CONST_INTER);
3099 %}
3100
3101 // Integer Immediate: 8-bit
3102 operand immI8() %{
3103 predicate(Assembler::is_simm8(n->get_int()));
3104 match(ConI);
3105 op_cost(0);
3106 format %{ %}
3107 interface(CONST_INTER);
3108 %}
3109
3110 // Integer Immediate: the value 10
3111 operand immI10() %{
3112 predicate(n->get_int() == 10);
3113 match(ConI);
3114 op_cost(0);
3115
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3119
3120 // Integer Immediate: 11-bit
3121 operand immI11() %{
3122 predicate(Assembler::is_simm11(n->get_int()));
3123 match(ConI);
3124 op_cost(0);
3125 format %{ %}
3126 interface(CONST_INTER);
3127 %}
3128
3129 // Integer Immediate: 13-bit
3130 operand immI13() %{
3131 predicate(Assembler::is_simm13(n->get_int()));
3132 match(ConI);
3133 op_cost(0);
3134
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Integer Immediate: 13-bit minus 7
3140 operand immI13m7() %{
3141 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3142 match(ConI);
3143 op_cost(0);
3144
3145 format %{ %}
3146 interface(CONST_INTER);
3147 %}
3148
3149 // Integer Immediate: 16-bit
3150 operand immI16() %{
3151 predicate(Assembler::is_simm16(n->get_int()));
3152 match(ConI);
3153 op_cost(0);
3154 format %{ %}
3155 interface(CONST_INTER);
3156 %}
3157
3158 // Integer Immediate: the values 1-31
3159 operand immI_1_31() %{
3160 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3161 match(ConI);
3162 op_cost(0);
3163
3164 format %{ %}
3165 interface(CONST_INTER);
3166 %}
3167
3168 // Integer Immediate: the values 32-63
3169 operand immI_32_63() %{
3170 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3171 match(ConI);
3172 op_cost(0);
3173
3174 format %{ %}
3175 interface(CONST_INTER);
3176 %}
3177
3178 // Immediates for special shifts (sign extend)
3179
3180 // Integer Immediate: the value 16
3181 operand immI_16() %{
3182 predicate(n->get_int() == 16);
3183 match(ConI);
3184 op_cost(0);
3185
3186 format %{ %}
3187 interface(CONST_INTER);
3188 %}
3189
3190 // Integer Immediate: the value 24
3191 operand immI_24() %{
3192 predicate(n->get_int() == 24);
3193 match(ConI);
3194 op_cost(0);
3195
3196 format %{ %}
3197 interface(CONST_INTER);
3198 %}
3199 // Integer Immediate: the value 255
3200 operand immI_255() %{
3201 predicate( n->get_int() == 255 );
3202 match(ConI);
3203 op_cost(0);
3204
3205 format %{ %}
3206 interface(CONST_INTER);
3207 %}
3208
3209 // Integer Immediate: the value 65535
3210 operand immI_65535() %{
3211 predicate(n->get_int() == 65535);
3212 match(ConI);
3213 op_cost(0);
3214
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Integer Immediate: the values 0-31
3220 operand immU5() %{
3221 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3222 match(ConI);
3223 op_cost(0);
3224
3225 format %{ %}
3226 interface(CONST_INTER);
3227 %}
3228
3229 // Integer Immediate: 6-bit
3230 operand immU6() %{
3231 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3232 match(ConI);
3233 op_cost(0);
3234 format %{ %}
3235 interface(CONST_INTER);
3236 %}
3237
3238 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3239 operand immU12() %{
3240 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3241 match(ConI);
3242 op_cost(0);
3243
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 // Unsigned Long Immediate: 12-bit (non-negative that fits in simm13)
3249 operand immUL12() %{
3250 predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long()));
3251 match(ConL);
3252 op_cost(0);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 // Integer Immediate non-negative
3259 operand immU31()
3260 %{
3261 predicate(n->get_int() >= 0);
3262 match(ConI);
3263
3264 op_cost(0);
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 // Long Immediate: the value FF
3270 operand immL_FF() %{
3271 predicate( n->get_long() == 0xFFL );
3272 match(ConL);
3273 op_cost(0);
3274
3275 format %{ %}
3276 interface(CONST_INTER);
3277 %}
3278
3279 // Long Immediate: the value FFFF
3280 operand immL_FFFF() %{
3281 predicate( n->get_long() == 0xFFFFL );
3282 match(ConL);
3283 op_cost(0);
3284
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 // Pointer Immediate: 32 or 64-bit
3290 operand immP() %{
3291 match(ConP);
3292
3293 op_cost(5);
3294 // formats are generated automatically for constants and base registers
3295 format %{ %}
3296 interface(CONST_INTER);
3297 %}
3298
3299 // Pointer Immediate: 64-bit
3300 operand immP_set() %{
3301 predicate(!VM_Version::has_fast_ld());
3302 match(ConP);
3303
3304 op_cost(5);
3305 // formats are generated automatically for constants and base registers
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3309
3310 // Pointer Immediate: 64-bit
3311 // From Niagara2 processors on a load should be better than materializing.
3312 operand immP_load() %{
3313 predicate(VM_Version::has_fast_ld() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3314 match(ConP);
3315
3316 op_cost(5);
3317 // formats are generated automatically for constants and base registers
3318 format %{ %}
3319 interface(CONST_INTER);
3320 %}
3321
3322 // Pointer Immediate: 64-bit
3323 operand immP_no_oop_cheap() %{
3324 predicate(VM_Version::has_fast_ld() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3325 match(ConP);
3326
3327 op_cost(5);
3328 // formats are generated automatically for constants and base registers
3329 format %{ %}
3330 interface(CONST_INTER);
3331 %}
3332
3333 operand immP13() %{
3334 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3335 match(ConP);
3336 op_cost(0);
3337
3338 format %{ %}
3339 interface(CONST_INTER);
3340 %}
3341
3342 operand immP0() %{
3343 predicate(n->get_ptr() == 0);
3344 match(ConP);
3345 op_cost(0);
3346
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 operand immP_poll() %{
3352 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3353 match(ConP);
3354
3355 // formats are generated automatically for constants and base registers
3356 format %{ %}
3357 interface(CONST_INTER);
3358 %}
3359
3360 // Pointer Immediate
3361 operand immN()
3362 %{
3363 match(ConN);
3364
3365 op_cost(10);
3366 format %{ %}
3367 interface(CONST_INTER);
3368 %}
3369
3370 operand immNKlass()
3371 %{
3372 match(ConNKlass);
3373
3374 op_cost(10);
3375 format %{ %}
3376 interface(CONST_INTER);
3377 %}
3378
3379 // NULL Pointer Immediate
3380 operand immN0()
3381 %{
3382 predicate(n->get_narrowcon() == 0);
3383 match(ConN);
3384
3385 op_cost(0);
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 operand immL() %{
3391 match(ConL);
3392 op_cost(40);
3393 // formats are generated automatically for constants and base registers
3394 format %{ %}
3395 interface(CONST_INTER);
3396 %}
3397
3398 operand immL0() %{
3399 predicate(n->get_long() == 0L);
3400 match(ConL);
3401 op_cost(0);
3402 // formats are generated automatically for constants and base registers
3403 format %{ %}
3404 interface(CONST_INTER);
3405 %}
3406
3407 // Integer Immediate: 5-bit
3408 operand immL5() %{
3409 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3410 match(ConL);
3411 op_cost(0);
3412 format %{ %}
3413 interface(CONST_INTER);
3414 %}
3415
3416 // Long Immediate: 13-bit
3417 operand immL13() %{
3418 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3419 match(ConL);
3420 op_cost(0);
3421
3422 format %{ %}
3423 interface(CONST_INTER);
3424 %}
3425
3426 // Long Immediate: 13-bit minus 7
3427 operand immL13m7() %{
3428 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3429 match(ConL);
3430 op_cost(0);
3431
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3435
3436 // Long Immediate: low 32-bit mask
3437 operand immL_32bits() %{
3438 predicate(n->get_long() == 0xFFFFFFFFL);
3439 match(ConL);
3440 op_cost(0);
3441
3442 format %{ %}
3443 interface(CONST_INTER);
3444 %}
3445
3446 // Long Immediate: cheap (materialize in <= 3 instructions)
3447 operand immL_cheap() %{
3448 predicate(!VM_Version::has_fast_ld() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3449 match(ConL);
3450 op_cost(0);
3451
3452 format %{ %}
3453 interface(CONST_INTER);
3454 %}
3455
3456 // Long Immediate: expensive (materialize in > 3 instructions)
3457 operand immL_expensive() %{
3458 predicate(VM_Version::has_fast_ld() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3459 match(ConL);
3460 op_cost(0);
3461
3462 format %{ %}
3463 interface(CONST_INTER);
3464 %}
3465
3466 // Double Immediate
3467 operand immD() %{
3468 match(ConD);
3469
3470 op_cost(40);
3471 format %{ %}
3472 interface(CONST_INTER);
3473 %}
3474
3475 // Double Immediate: +0.0d
3476 operand immD0() %{
3477 predicate(jlong_cast(n->getd()) == 0);
3478 match(ConD);
3479
3480 op_cost(0);
3481 format %{ %}
3482 interface(CONST_INTER);
3483 %}
3484
3485 // Float Immediate
3486 operand immF() %{
3487 match(ConF);
3488
3489 op_cost(20);
3490 format %{ %}
3491 interface(CONST_INTER);
3492 %}
3493
3494 // Float Immediate: +0.0f
3495 operand immF0() %{
3496 predicate(jint_cast(n->getf()) == 0);
3497 match(ConF);
3498
3499 op_cost(0);
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3503
3504 // Integer Register Operands
3505 // Integer Register
3506 operand iRegI() %{
3507 constraint(ALLOC_IN_RC(int_reg));
3508 match(RegI);
3509
3510 match(notemp_iRegI);
3511 match(g1RegI);
3512 match(o0RegI);
3513 match(iRegIsafe);
3514
3515 format %{ %}
3516 interface(REG_INTER);
3517 %}
3518
3519 operand notemp_iRegI() %{
3520 constraint(ALLOC_IN_RC(notemp_int_reg));
3521 match(RegI);
3522
3523 match(o0RegI);
3524
3525 format %{ %}
3526 interface(REG_INTER);
3527 %}
3528
3529 operand o0RegI() %{
3530 constraint(ALLOC_IN_RC(o0_regI));
3531 match(iRegI);
3532
3533 format %{ %}
3534 interface(REG_INTER);
3535 %}
3536
3537 // Pointer Register
3538 operand iRegP() %{
3539 constraint(ALLOC_IN_RC(ptr_reg));
3540 match(RegP);
3541
3542 match(lock_ptr_RegP);
3543 match(g1RegP);
3544 match(g2RegP);
3545 match(g3RegP);
3546 match(g4RegP);
3547 match(i0RegP);
3548 match(o0RegP);
3549 match(o1RegP);
3550 match(l7RegP);
3551
3552 format %{ %}
3553 interface(REG_INTER);
3554 %}
3555
3556 operand sp_ptr_RegP() %{
3557 constraint(ALLOC_IN_RC(sp_ptr_reg));
3558 match(RegP);
3559 match(iRegP);
3560
3561 format %{ %}
3562 interface(REG_INTER);
3563 %}
3564
3565 operand lock_ptr_RegP() %{
3566 constraint(ALLOC_IN_RC(lock_ptr_reg));
3567 match(RegP);
3568 match(i0RegP);
3569 match(o0RegP);
3570 match(o1RegP);
3571 match(l7RegP);
3572
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 operand g1RegP() %{
3578 constraint(ALLOC_IN_RC(g1_regP));
3579 match(iRegP);
3580
3581 format %{ %}
3582 interface(REG_INTER);
3583 %}
3584
3585 operand g2RegP() %{
3586 constraint(ALLOC_IN_RC(g2_regP));
3587 match(iRegP);
3588
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3592
3593 operand g3RegP() %{
3594 constraint(ALLOC_IN_RC(g3_regP));
3595 match(iRegP);
3596
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 operand g1RegI() %{
3602 constraint(ALLOC_IN_RC(g1_regI));
3603 match(iRegI);
3604
3605 format %{ %}
3606 interface(REG_INTER);
3607 %}
3608
3609 operand g3RegI() %{
3610 constraint(ALLOC_IN_RC(g3_regI));
3611 match(iRegI);
3612
3613 format %{ %}
3614 interface(REG_INTER);
3615 %}
3616
3617 operand g4RegI() %{
3618 constraint(ALLOC_IN_RC(g4_regI));
3619 match(iRegI);
3620
3621 format %{ %}
3622 interface(REG_INTER);
3623 %}
3624
3625 operand g4RegP() %{
3626 constraint(ALLOC_IN_RC(g4_regP));
3627 match(iRegP);
3628
3629 format %{ %}
3630 interface(REG_INTER);
3631 %}
3632
3633 operand i0RegP() %{
3634 constraint(ALLOC_IN_RC(i0_regP));
3635 match(iRegP);
3636
3637 format %{ %}
3638 interface(REG_INTER);
3639 %}
3640
3641 operand o0RegP() %{
3642 constraint(ALLOC_IN_RC(o0_regP));
3643 match(iRegP);
3644
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 operand o1RegP() %{
3650 constraint(ALLOC_IN_RC(o1_regP));
3651 match(iRegP);
3652
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3656
3657 operand o2RegP() %{
3658 constraint(ALLOC_IN_RC(o2_regP));
3659 match(iRegP);
3660
3661 format %{ %}
3662 interface(REG_INTER);
3663 %}
3664
3665 operand o7RegP() %{
3666 constraint(ALLOC_IN_RC(o7_regP));
3667 match(iRegP);
3668
3669 format %{ %}
3670 interface(REG_INTER);
3671 %}
3672
3673 operand l7RegP() %{
3674 constraint(ALLOC_IN_RC(l7_regP));
3675 match(iRegP);
3676
3677 format %{ %}
3678 interface(REG_INTER);
3679 %}
3680
3681 operand o7RegI() %{
3682 constraint(ALLOC_IN_RC(o7_regI));
3683 match(iRegI);
3684
3685 format %{ %}
3686 interface(REG_INTER);
3687 %}
3688
3689 operand iRegN() %{
3690 constraint(ALLOC_IN_RC(int_reg));
3691 match(RegN);
3692
3693 format %{ %}
3694 interface(REG_INTER);
3695 %}
3696
3697 // Long Register
3698 operand iRegL() %{
3699 constraint(ALLOC_IN_RC(long_reg));
3700 match(RegL);
3701
3702 format %{ %}
3703 interface(REG_INTER);
3704 %}
3705
3706 operand o2RegL() %{
3707 constraint(ALLOC_IN_RC(o2_regL));
3708 match(iRegL);
3709
3710 format %{ %}
3711 interface(REG_INTER);
3712 %}
3713
3714 operand o7RegL() %{
3715 constraint(ALLOC_IN_RC(o7_regL));
3716 match(iRegL);
3717
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3721
3722 operand g1RegL() %{
3723 constraint(ALLOC_IN_RC(g1_regL));
3724 match(iRegL);
3725
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3729
3730 operand g3RegL() %{
3731 constraint(ALLOC_IN_RC(g3_regL));
3732 match(iRegL);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 // Int Register safe
3739 // This is 64bit safe
3740 operand iRegIsafe() %{
3741 constraint(ALLOC_IN_RC(long_reg));
3742
3743 match(iRegI);
3744
3745 format %{ %}
3746 interface(REG_INTER);
3747 %}
3748
3749 // Condition Code Flag Register
3750 operand flagsReg() %{
3751 constraint(ALLOC_IN_RC(int_flags));
3752 match(RegFlags);
3753
3754 format %{ "ccr" %} // both ICC and XCC
3755 interface(REG_INTER);
3756 %}
3757
3758 // Condition Code Register, unsigned comparisons.
3759 operand flagsRegU() %{
3760 constraint(ALLOC_IN_RC(int_flags));
3761 match(RegFlags);
3762
3763 format %{ "icc_U" %}
3764 interface(REG_INTER);
3765 %}
3766
3767 // Condition Code Register, pointer comparisons.
3768 operand flagsRegP() %{
3769 constraint(ALLOC_IN_RC(int_flags));
3770 match(RegFlags);
3771
3772 format %{ "xcc_P" %}
3773 interface(REG_INTER);
3774 %}
3775
3776 // Condition Code Register, long comparisons.
3777 operand flagsRegL() %{
3778 constraint(ALLOC_IN_RC(int_flags));
3779 match(RegFlags);
3780
3781 format %{ "xcc_L" %}
3782 interface(REG_INTER);
3783 %}
3784
3785 // Condition Code Register, unsigned long comparisons.
3786 operand flagsRegUL() %{
3787 constraint(ALLOC_IN_RC(int_flags));
3788 match(RegFlags);
3789
3790 format %{ "xcc_UL" %}
3791 interface(REG_INTER);
3792 %}
3793
3794 // Condition Code Register, floating comparisons, unordered same as "less".
3795 operand flagsRegF() %{
3796 constraint(ALLOC_IN_RC(float_flags));
3797 match(RegFlags);
3798 match(flagsRegF0);
3799
3800 format %{ %}
3801 interface(REG_INTER);
3802 %}
3803
3804 operand flagsRegF0() %{
3805 constraint(ALLOC_IN_RC(float_flag0));
3806 match(RegFlags);
3807
3808 format %{ %}
3809 interface(REG_INTER);
3810 %}
3811
3812
3813 // Condition Code Flag Register used by long compare
3814 operand flagsReg_long_LTGE() %{
3815 constraint(ALLOC_IN_RC(int_flags));
3816 match(RegFlags);
3817 format %{ "icc_LTGE" %}
3818 interface(REG_INTER);
3819 %}
3820 operand flagsReg_long_EQNE() %{
3821 constraint(ALLOC_IN_RC(int_flags));
3822 match(RegFlags);
3823 format %{ "icc_EQNE" %}
3824 interface(REG_INTER);
3825 %}
3826 operand flagsReg_long_LEGT() %{
3827 constraint(ALLOC_IN_RC(int_flags));
3828 match(RegFlags);
3829 format %{ "icc_LEGT" %}
3830 interface(REG_INTER);
3831 %}
3832
3833
3834 operand regD() %{
3835 constraint(ALLOC_IN_RC(dflt_reg));
3836 match(RegD);
3837
3838 match(regD_low);
3839
3840 format %{ %}
3841 interface(REG_INTER);
3842 %}
3843
3844 operand regF() %{
3845 constraint(ALLOC_IN_RC(sflt_reg));
3846 match(RegF);
3847
3848 format %{ %}
3849 interface(REG_INTER);
3850 %}
3851
3852 operand regD_low() %{
3853 constraint(ALLOC_IN_RC(dflt_low_reg));
3854 match(regD);
3855
3856 format %{ %}
3857 interface(REG_INTER);
3858 %}
3859
3860 // Special Registers
3861
3862 // Method Register
3863 operand inline_cache_regP(iRegP reg) %{
3864 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3865 match(reg);
3866 format %{ %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand interpreter_method_oop_regP(iRegP reg) %{
3871 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3872 match(reg);
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877
3878 //----------Complex Operands---------------------------------------------------
3879 // Indirect Memory Reference
3880 operand indirect(sp_ptr_RegP reg) %{
3881 constraint(ALLOC_IN_RC(sp_ptr_reg));
3882 match(reg);
3883
3884 op_cost(100);
3885 format %{ "[$reg]" %}
3886 interface(MEMORY_INTER) %{
3887 base($reg);
3888 index(0x0);
3889 scale(0x0);
3890 disp(0x0);
3891 %}
3892 %}
3893
3894 // Indirect with simm13 Offset
3895 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3896 constraint(ALLOC_IN_RC(sp_ptr_reg));
3897 match(AddP reg offset);
3898
3899 op_cost(100);
3900 format %{ "[$reg + $offset]" %}
3901 interface(MEMORY_INTER) %{
3902 base($reg);
3903 index(0x0);
3904 scale(0x0);
3905 disp($offset);
3906 %}
3907 %}
3908
3909 // Indirect with simm13 Offset minus 7
3910 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3911 constraint(ALLOC_IN_RC(sp_ptr_reg));
3912 match(AddP reg offset);
3913
3914 op_cost(100);
3915 format %{ "[$reg + $offset]" %}
3916 interface(MEMORY_INTER) %{
3917 base($reg);
3918 index(0x0);
3919 scale(0x0);
3920 disp($offset);
3921 %}
3922 %}
3923
3924 // Note: Intel has a swapped version also, like this:
3925 //operand indOffsetX(iRegI reg, immP offset) %{
3926 // constraint(ALLOC_IN_RC(int_reg));
3927 // match(AddP offset reg);
3928 //
3929 // op_cost(100);
3930 // format %{ "[$reg + $offset]" %}
3931 // interface(MEMORY_INTER) %{
3932 // base($reg);
3933 // index(0x0);
3934 // scale(0x0);
3935 // disp($offset);
3936 // %}
3937 //%}
3938 //// However, it doesn't make sense for SPARC, since
3939 // we have no particularly good way to embed oops in
3940 // single instructions.
3941
3942 // Indirect with Register Index
3943 operand indIndex(iRegP addr, iRegX index) %{
3944 constraint(ALLOC_IN_RC(ptr_reg));
3945 match(AddP addr index);
3946
3947 op_cost(100);
3948 format %{ "[$addr + $index]" %}
3949 interface(MEMORY_INTER) %{
3950 base($addr);
3951 index($index);
3952 scale(0x0);
3953 disp(0x0);
3954 %}
3955 %}
3956
3957 //----------Special Memory Operands--------------------------------------------
3958 // Stack Slot Operand - This operand is used for loading and storing temporary
3959 // values on the stack where a match requires a value to
3960 // flow through memory.
3961 operand stackSlotI(sRegI reg) %{
3962 constraint(ALLOC_IN_RC(stack_slots));
3963 op_cost(100);
3964 //match(RegI);
3965 format %{ "[$reg]" %}
3966 interface(MEMORY_INTER) %{
3967 base(0xE); // R_SP
3968 index(0x0);
3969 scale(0x0);
3970 disp($reg); // Stack Offset
3971 %}
3972 %}
3973
3974 operand stackSlotP(sRegP reg) %{
3975 constraint(ALLOC_IN_RC(stack_slots));
3976 op_cost(100);
3977 //match(RegP);
3978 format %{ "[$reg]" %}
3979 interface(MEMORY_INTER) %{
3980 base(0xE); // R_SP
3981 index(0x0);
3982 scale(0x0);
3983 disp($reg); // Stack Offset
3984 %}
3985 %}
3986
3987 operand stackSlotF(sRegF reg) %{
3988 constraint(ALLOC_IN_RC(stack_slots));
3989 op_cost(100);
3990 //match(RegF);
3991 format %{ "[$reg]" %}
3992 interface(MEMORY_INTER) %{
3993 base(0xE); // R_SP
3994 index(0x0);
3995 scale(0x0);
3996 disp($reg); // Stack Offset
3997 %}
3998 %}
3999 operand stackSlotD(sRegD reg) %{
4000 constraint(ALLOC_IN_RC(stack_slots));
4001 op_cost(100);
4002 //match(RegD);
4003 format %{ "[$reg]" %}
4004 interface(MEMORY_INTER) %{
4005 base(0xE); // R_SP
4006 index(0x0);
4007 scale(0x0);
4008 disp($reg); // Stack Offset
4009 %}
4010 %}
4011 operand stackSlotL(sRegL reg) %{
4012 constraint(ALLOC_IN_RC(stack_slots));
4013 op_cost(100);
4014 //match(RegL);
4015 format %{ "[$reg]" %}
4016 interface(MEMORY_INTER) %{
4017 base(0xE); // R_SP
4018 index(0x0);
4019 scale(0x0);
4020 disp($reg); // Stack Offset
4021 %}
4022 %}
4023
4024 // Operands for expressing Control Flow
4025 // NOTE: Label is a predefined operand which should not be redefined in
4026 // the AD file. It is generically handled within the ADLC.
4027
4028 //----------Conditional Branch Operands----------------------------------------
4029 // Comparison Op - This is the operation of the comparison, and is limited to
4030 // the following set of codes:
4031 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4032 //
4033 // Other attributes of the comparison, such as unsignedness, are specified
4034 // by the comparison instruction that sets a condition code flags register.
4035 // That result is represented by a flags operand whose subtype is appropriate
4036 // to the unsignedness (etc.) of the comparison.
4037 //
4038 // Later, the instruction which matches both the Comparison Op (a Bool) and
4039 // the flags (produced by the Cmp) specifies the coding of the comparison op
4040 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4041
4042 operand cmpOp() %{
4043 match(Bool);
4044
4045 format %{ "" %}
4046 interface(COND_INTER) %{
4047 equal(0x1);
4048 not_equal(0x9);
4049 less(0x3);
4050 greater_equal(0xB);
4051 less_equal(0x2);
4052 greater(0xA);
4053 overflow(0x7);
4054 no_overflow(0xF);
4055 %}
4056 %}
4057
4058 // Comparison Op, unsigned
4059 operand cmpOpU() %{
4060 match(Bool);
4061 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4062 n->as_Bool()->_test._test != BoolTest::no_overflow);
4063
4064 format %{ "u" %}
4065 interface(COND_INTER) %{
4066 equal(0x1);
4067 not_equal(0x9);
4068 less(0x5);
4069 greater_equal(0xD);
4070 less_equal(0x4);
4071 greater(0xC);
4072 overflow(0x7);
4073 no_overflow(0xF);
4074 %}
4075 %}
4076
4077 // Comparison Op, pointer (same as unsigned)
4078 operand cmpOpP() %{
4079 match(Bool);
4080 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4081 n->as_Bool()->_test._test != BoolTest::no_overflow);
4082
4083 format %{ "p" %}
4084 interface(COND_INTER) %{
4085 equal(0x1);
4086 not_equal(0x9);
4087 less(0x5);
4088 greater_equal(0xD);
4089 less_equal(0x4);
4090 greater(0xC);
4091 overflow(0x7);
4092 no_overflow(0xF);
4093 %}
4094 %}
4095
4096 // Comparison Op, branch-register encoding
4097 operand cmpOp_reg() %{
4098 match(Bool);
4099 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4100 n->as_Bool()->_test._test != BoolTest::no_overflow);
4101
4102 format %{ "" %}
4103 interface(COND_INTER) %{
4104 equal (0x1);
4105 not_equal (0x5);
4106 less (0x3);
4107 greater_equal(0x7);
4108 less_equal (0x2);
4109 greater (0x6);
4110 overflow(0x7); // not supported
4111 no_overflow(0xF); // not supported
4112 %}
4113 %}
4114
4115 // Comparison Code, floating, unordered same as less
4116 operand cmpOpF() %{
4117 match(Bool);
4118 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4119 n->as_Bool()->_test._test != BoolTest::no_overflow);
4120
4121 format %{ "fl" %}
4122 interface(COND_INTER) %{
4123 equal(0x9);
4124 not_equal(0x1);
4125 less(0x3);
4126 greater_equal(0xB);
4127 less_equal(0xE);
4128 greater(0x6);
4129
4130 overflow(0x7); // not supported
4131 no_overflow(0xF); // not supported
4132 %}
4133 %}
4134
4135 // Used by long compare
4136 operand cmpOp_commute() %{
4137 match(Bool);
4138 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4139 n->as_Bool()->_test._test != BoolTest::no_overflow);
4140
4141 format %{ "" %}
4142 interface(COND_INTER) %{
4143 equal(0x1);
4144 not_equal(0x9);
4145 less(0xA);
4146 greater_equal(0x2);
4147 less_equal(0xB);
4148 greater(0x3);
4149 overflow(0x7);
4150 no_overflow(0xF);
4151 %}
4152 %}
4153
4154 //----------OPERAND CLASSES----------------------------------------------------
4155 // Operand Classes are groups of operands that are used to simplify
4156 // instruction definitions by not requiring the AD writer to specify separate
4157 // instructions for every form of operand when the instruction accepts
4158 // multiple operand types with the same basic encoding and format. The classic
4159 // case of this is memory operands.
4160 opclass memory( indirect, indOffset13, indIndex );
4161 opclass indIndexMemory( indIndex );
4162
4163 //----------PIPELINE-----------------------------------------------------------
4164 pipeline %{
4165
4166 //----------ATTRIBUTES---------------------------------------------------------
4167 attributes %{
4168 fixed_size_instructions; // Fixed size instructions
4169 branch_has_delay_slot; // Branch has delay slot following
4170 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4171 instruction_unit_size = 4; // An instruction is 4 bytes long
4172 instruction_fetch_unit_size = 16; // The processor fetches one line
4173 instruction_fetch_units = 1; // of 16 bytes
4174
4175 // List of nop instructions
4176 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4177 %}
4178
4179 //----------RESOURCES----------------------------------------------------------
4180 // Resources are the functional units available to the machine
4181 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4182
4183 //----------PIPELINE DESCRIPTION-----------------------------------------------
4184 // Pipeline Description specifies the stages in the machine's pipeline
4185
4186 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4187
4188 //----------PIPELINE CLASSES---------------------------------------------------
4189 // Pipeline Classes describe the stages in which input and output are
4190 // referenced by the hardware pipeline.
4191
4192 // Integer ALU reg-reg operation
4193 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4194 single_instruction;
4195 dst : E(write);
4196 src1 : R(read);
4197 src2 : R(read);
4198 IALU : R;
4199 %}
4200
4201 // Integer ALU reg-reg long operation
4202 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4203 instruction_count(2);
4204 dst : E(write);
4205 src1 : R(read);
4206 src2 : R(read);
4207 IALU : R;
4208 IALU : R;
4209 %}
4210
4211 // Integer ALU reg-reg long dependent operation
4212 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4213 instruction_count(1); multiple_bundles;
4214 dst : E(write);
4215 src1 : R(read);
4216 src2 : R(read);
4217 cr : E(write);
4218 IALU : R(2);
4219 %}
4220
4221 // Integer ALU reg-imm operaion
4222 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4223 single_instruction;
4224 dst : E(write);
4225 src1 : R(read);
4226 IALU : R;
4227 %}
4228
4229 // Integer ALU reg-reg operation with condition code
4230 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4231 single_instruction;
4232 dst : E(write);
4233 cr : E(write);
4234 src1 : R(read);
4235 src2 : R(read);
4236 IALU : R;
4237 %}
4238
4239 // Integer ALU reg-imm operation with condition code
4240 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4241 single_instruction;
4242 dst : E(write);
4243 cr : E(write);
4244 src1 : R(read);
4245 IALU : R;
4246 %}
4247
4248 // Integer ALU zero-reg operation
4249 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4250 single_instruction;
4251 dst : E(write);
4252 src2 : R(read);
4253 IALU : R;
4254 %}
4255
4256 // Integer ALU zero-reg operation with condition code only
4257 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4258 single_instruction;
4259 cr : E(write);
4260 src : R(read);
4261 IALU : R;
4262 %}
4263
4264 // Integer ALU reg-reg operation with condition code only
4265 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4266 single_instruction;
4267 cr : E(write);
4268 src1 : R(read);
4269 src2 : R(read);
4270 IALU : R;
4271 %}
4272
4273 // Integer ALU reg-imm operation with condition code only
4274 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4275 single_instruction;
4276 cr : E(write);
4277 src1 : R(read);
4278 IALU : R;
4279 %}
4280
4281 // Integer ALU reg-reg-zero operation with condition code only
4282 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4283 single_instruction;
4284 cr : E(write);
4285 src1 : R(read);
4286 src2 : R(read);
4287 IALU : R;
4288 %}
4289
4290 // Integer ALU reg-imm-zero operation with condition code only
4291 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4292 single_instruction;
4293 cr : E(write);
4294 src1 : R(read);
4295 IALU : R;
4296 %}
4297
4298 // Integer ALU reg-reg operation with condition code, src1 modified
4299 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4300 single_instruction;
4301 cr : E(write);
4302 src1 : E(write);
4303 src1 : R(read);
4304 src2 : R(read);
4305 IALU : R;
4306 %}
4307
4308 // Integer ALU reg-imm operation with condition code, src1 modified
4309 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4310 single_instruction;
4311 cr : E(write);
4312 src1 : E(write);
4313 src1 : R(read);
4314 IALU : R;
4315 %}
4316
4317 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4318 multiple_bundles;
4319 dst : E(write)+4;
4320 cr : E(write);
4321 src1 : R(read);
4322 src2 : R(read);
4323 IALU : R(3);
4324 BR : R(2);
4325 %}
4326
4327 // Integer ALU operation
4328 pipe_class ialu_none(iRegI dst) %{
4329 single_instruction;
4330 dst : E(write);
4331 IALU : R;
4332 %}
4333
4334 // Integer ALU reg operation
4335 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4336 single_instruction; may_have_no_code;
4337 dst : E(write);
4338 src : R(read);
4339 IALU : R;
4340 %}
4341
4342 // Integer ALU reg conditional operation
4343 // This instruction has a 1 cycle stall, and cannot execute
4344 // in the same cycle as the instruction setting the condition
4345 // code. We kludge this by pretending to read the condition code
4346 // 1 cycle earlier, and by marking the functional units as busy
4347 // for 2 cycles with the result available 1 cycle later than
4348 // is really the case.
4349 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4350 single_instruction;
4351 op2_out : C(write);
4352 op1 : R(read);
4353 cr : R(read); // This is really E, with a 1 cycle stall
4354 BR : R(2);
4355 MS : R(2);
4356 %}
4357
4358 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4359 instruction_count(1); multiple_bundles;
4360 dst : C(write)+1;
4361 src : R(read)+1;
4362 IALU : R(1);
4363 BR : E(2);
4364 MS : E(2);
4365 %}
4366
4367 // Integer ALU reg operation
4368 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4369 single_instruction; may_have_no_code;
4370 dst : E(write);
4371 src : R(read);
4372 IALU : R;
4373 %}
4374 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4375 single_instruction; may_have_no_code;
4376 dst : E(write);
4377 src : R(read);
4378 IALU : R;
4379 %}
4380
4381 // Two integer ALU reg operations
4382 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4383 instruction_count(2);
4384 dst : E(write);
4385 src : R(read);
4386 A0 : R;
4387 A1 : R;
4388 %}
4389
4390 // Two integer ALU reg operations
4391 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4392 instruction_count(2); may_have_no_code;
4393 dst : E(write);
4394 src : R(read);
4395 A0 : R;
4396 A1 : R;
4397 %}
4398
4399 // Integer ALU imm operation
4400 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4401 single_instruction;
4402 dst : E(write);
4403 IALU : R;
4404 %}
4405
4406 // Integer ALU reg-reg with carry operation
4407 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4408 single_instruction;
4409 dst : E(write);
4410 src1 : R(read);
4411 src2 : R(read);
4412 IALU : R;
4413 %}
4414
4415 // Integer ALU cc operation
4416 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4417 single_instruction;
4418 dst : E(write);
4419 cc : R(read);
4420 IALU : R;
4421 %}
4422
4423 // Integer ALU cc / second IALU operation
4424 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4425 instruction_count(1); multiple_bundles;
4426 dst : E(write)+1;
4427 src : R(read);
4428 IALU : R;
4429 %}
4430
4431 // Integer ALU cc / second IALU operation
4432 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4433 instruction_count(1); multiple_bundles;
4434 dst : E(write)+1;
4435 p : R(read);
4436 q : R(read);
4437 IALU : R;
4438 %}
4439
4440 // Integer ALU hi-lo-reg operation
4441 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4442 instruction_count(1); multiple_bundles;
4443 dst : E(write)+1;
4444 IALU : R(2);
4445 %}
4446
4447 // Float ALU hi-lo-reg operation (with temp)
4448 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4449 instruction_count(1); multiple_bundles;
4450 dst : E(write)+1;
4451 IALU : R(2);
4452 %}
4453
4454 // Long Constant
4455 pipe_class loadConL( iRegL dst, immL src ) %{
4456 instruction_count(2); multiple_bundles;
4457 dst : E(write)+1;
4458 IALU : R(2);
4459 IALU : R(2);
4460 %}
4461
4462 // Pointer Constant
4463 pipe_class loadConP( iRegP dst, immP src ) %{
4464 instruction_count(0); multiple_bundles;
4465 fixed_latency(6);
4466 %}
4467
4468 // Polling Address
4469 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4470 instruction_count(0); multiple_bundles;
4471 fixed_latency(6);
4472 %}
4473
4474 // Long Constant small
4475 pipe_class loadConLlo( iRegL dst, immL src ) %{
4476 instruction_count(2);
4477 dst : E(write);
4478 IALU : R;
4479 IALU : R;
4480 %}
4481
4482 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4483 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4484 instruction_count(1); multiple_bundles;
4485 src : R(read);
4486 dst : M(write)+1;
4487 IALU : R;
4488 MS : E;
4489 %}
4490
4491 // Integer ALU nop operation
4492 pipe_class ialu_nop() %{
4493 single_instruction;
4494 IALU : R;
4495 %}
4496
4497 // Integer ALU nop operation
4498 pipe_class ialu_nop_A0() %{
4499 single_instruction;
4500 A0 : R;
4501 %}
4502
4503 // Integer ALU nop operation
4504 pipe_class ialu_nop_A1() %{
4505 single_instruction;
4506 A1 : R;
4507 %}
4508
4509 // Integer Multiply reg-reg operation
4510 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4511 single_instruction;
4512 dst : E(write);
4513 src1 : R(read);
4514 src2 : R(read);
4515 MS : R(5);
4516 %}
4517
4518 // Integer Multiply reg-imm operation
4519 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4520 single_instruction;
4521 dst : E(write);
4522 src1 : R(read);
4523 MS : R(5);
4524 %}
4525
4526 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4527 single_instruction;
4528 dst : E(write)+4;
4529 src1 : R(read);
4530 src2 : R(read);
4531 MS : R(6);
4532 %}
4533
4534 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4535 single_instruction;
4536 dst : E(write)+4;
4537 src1 : R(read);
4538 MS : R(6);
4539 %}
4540
4541 // Integer Divide reg-reg
4542 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4543 instruction_count(1); multiple_bundles;
4544 dst : E(write);
4545 temp : E(write);
4546 src1 : R(read);
4547 src2 : R(read);
4548 temp : R(read);
4549 MS : R(38);
4550 %}
4551
4552 // Integer Divide reg-imm
4553 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4554 instruction_count(1); multiple_bundles;
4555 dst : E(write);
4556 temp : E(write);
4557 src1 : R(read);
4558 temp : R(read);
4559 MS : R(38);
4560 %}
4561
4562 // Long Divide
4563 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4564 dst : E(write)+71;
4565 src1 : R(read);
4566 src2 : R(read)+1;
4567 MS : R(70);
4568 %}
4569
4570 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4571 dst : E(write)+71;
4572 src1 : R(read);
4573 MS : R(70);
4574 %}
4575
4576 // Floating Point Add Float
4577 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4578 single_instruction;
4579 dst : X(write);
4580 src1 : E(read);
4581 src2 : E(read);
4582 FA : R;
4583 %}
4584
4585 // Floating Point Add Double
4586 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4587 single_instruction;
4588 dst : X(write);
4589 src1 : E(read);
4590 src2 : E(read);
4591 FA : R;
4592 %}
4593
4594 // Floating Point Conditional Move based on integer flags
4595 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4596 single_instruction;
4597 dst : X(write);
4598 src : E(read);
4599 cr : R(read);
4600 FA : R(2);
4601 BR : R(2);
4602 %}
4603
4604 // Floating Point Conditional Move based on integer flags
4605 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4606 single_instruction;
4607 dst : X(write);
4608 src : E(read);
4609 cr : R(read);
4610 FA : R(2);
4611 BR : R(2);
4612 %}
4613
4614 // Floating Point Multiply Float
4615 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4616 single_instruction;
4617 dst : X(write);
4618 src1 : E(read);
4619 src2 : E(read);
4620 FM : R;
4621 %}
4622
4623 // Floating Point Multiply Double
4624 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4625 single_instruction;
4626 dst : X(write);
4627 src1 : E(read);
4628 src2 : E(read);
4629 FM : R;
4630 %}
4631
4632 // Floating Point Divide Float
4633 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4634 single_instruction;
4635 dst : X(write);
4636 src1 : E(read);
4637 src2 : E(read);
4638 FM : R;
4639 FDIV : C(14);
4640 %}
4641
4642 // Floating Point Divide Double
4643 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4644 single_instruction;
4645 dst : X(write);
4646 src1 : E(read);
4647 src2 : E(read);
4648 FM : R;
4649 FDIV : C(17);
4650 %}
4651
4652 // Fused floating-point multiply-add float.
4653 pipe_class fmaF_regx4(regF dst, regF src1, regF src2, regF src3) %{
4654 single_instruction;
4655 dst : X(write);
4656 src1 : E(read);
4657 src2 : E(read);
4658 src3 : E(read);
4659 FM : R;
4660 %}
4661
4662 // Fused gloating-point multiply-add double.
4663 pipe_class fmaD_regx4(regD dst, regD src1, regD src2, regD src3) %{
4664 single_instruction;
4665 dst : X(write);
4666 src1 : E(read);
4667 src2 : E(read);
4668 src3 : E(read);
4669 FM : R;
4670 %}
4671
4672 // Floating Point Move/Negate/Abs Float
4673 pipe_class faddF_reg(regF dst, regF src) %{
4674 single_instruction;
4675 dst : W(write);
4676 src : E(read);
4677 FA : R(1);
4678 %}
4679
4680 // Floating Point Move/Negate/Abs Double
4681 pipe_class faddD_reg(regD dst, regD src) %{
4682 single_instruction;
4683 dst : W(write);
4684 src : E(read);
4685 FA : R;
4686 %}
4687
4688 // Floating Point Convert F->D
4689 pipe_class fcvtF2D(regD dst, regF src) %{
4690 single_instruction;
4691 dst : X(write);
4692 src : E(read);
4693 FA : R;
4694 %}
4695
4696 // Floating Point Convert I->D
4697 pipe_class fcvtI2D(regD dst, regF src) %{
4698 single_instruction;
4699 dst : X(write);
4700 src : E(read);
4701 FA : R;
4702 %}
4703
4704 // Floating Point Convert LHi->D
4705 pipe_class fcvtLHi2D(regD dst, regD src) %{
4706 single_instruction;
4707 dst : X(write);
4708 src : E(read);
4709 FA : R;
4710 %}
4711
4712 // Floating Point Convert L->D
4713 pipe_class fcvtL2D(regD dst, regF src) %{
4714 single_instruction;
4715 dst : X(write);
4716 src : E(read);
4717 FA : R;
4718 %}
4719
4720 // Floating Point Convert L->F
4721 pipe_class fcvtL2F(regD dst, regF src) %{
4722 single_instruction;
4723 dst : X(write);
4724 src : E(read);
4725 FA : R;
4726 %}
4727
4728 // Floating Point Convert D->F
4729 pipe_class fcvtD2F(regD dst, regF src) %{
4730 single_instruction;
4731 dst : X(write);
4732 src : E(read);
4733 FA : R;
4734 %}
4735
4736 // Floating Point Convert I->L
4737 pipe_class fcvtI2L(regD dst, regF src) %{
4738 single_instruction;
4739 dst : X(write);
4740 src : E(read);
4741 FA : R;
4742 %}
4743
4744 // Floating Point Convert D->F
4745 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4746 instruction_count(1); multiple_bundles;
4747 dst : X(write)+6;
4748 src : E(read);
4749 FA : R;
4750 %}
4751
4752 // Floating Point Convert D->L
4753 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4754 instruction_count(1); multiple_bundles;
4755 dst : X(write)+6;
4756 src : E(read);
4757 FA : R;
4758 %}
4759
4760 // Floating Point Convert F->I
4761 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4762 instruction_count(1); multiple_bundles;
4763 dst : X(write)+6;
4764 src : E(read);
4765 FA : R;
4766 %}
4767
4768 // Floating Point Convert F->L
4769 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4770 instruction_count(1); multiple_bundles;
4771 dst : X(write)+6;
4772 src : E(read);
4773 FA : R;
4774 %}
4775
4776 // Floating Point Convert I->F
4777 pipe_class fcvtI2F(regF dst, regF src) %{
4778 single_instruction;
4779 dst : X(write);
4780 src : E(read);
4781 FA : R;
4782 %}
4783
4784 // Floating Point Compare
4785 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4786 single_instruction;
4787 cr : X(write);
4788 src1 : E(read);
4789 src2 : E(read);
4790 FA : R;
4791 %}
4792
4793 // Floating Point Compare
4794 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4795 single_instruction;
4796 cr : X(write);
4797 src1 : E(read);
4798 src2 : E(read);
4799 FA : R;
4800 %}
4801
4802 // Floating Add Nop
4803 pipe_class fadd_nop() %{
4804 single_instruction;
4805 FA : R;
4806 %}
4807
4808 // Integer Store to Memory
4809 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4810 single_instruction;
4811 mem : R(read);
4812 src : C(read);
4813 MS : R;
4814 %}
4815
4816 // Integer Store to Memory
4817 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4818 single_instruction;
4819 mem : R(read);
4820 src : C(read);
4821 MS : R;
4822 %}
4823
4824 // Integer Store Zero to Memory
4825 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4826 single_instruction;
4827 mem : R(read);
4828 MS : R;
4829 %}
4830
4831 // Special Stack Slot Store
4832 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4833 single_instruction;
4834 stkSlot : R(read);
4835 src : C(read);
4836 MS : R;
4837 %}
4838
4839 // Special Stack Slot Store
4840 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4841 instruction_count(2); multiple_bundles;
4842 stkSlot : R(read);
4843 src : C(read);
4844 MS : R(2);
4845 %}
4846
4847 // Float Store
4848 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4849 single_instruction;
4850 mem : R(read);
4851 src : C(read);
4852 MS : R;
4853 %}
4854
4855 // Float Store
4856 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4857 single_instruction;
4858 mem : R(read);
4859 MS : R;
4860 %}
4861
4862 // Double Store
4863 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4864 instruction_count(1);
4865 mem : R(read);
4866 src : C(read);
4867 MS : R;
4868 %}
4869
4870 // Double Store
4871 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4872 single_instruction;
4873 mem : R(read);
4874 MS : R;
4875 %}
4876
4877 // Special Stack Slot Float Store
4878 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4879 single_instruction;
4880 stkSlot : R(read);
4881 src : C(read);
4882 MS : R;
4883 %}
4884
4885 // Special Stack Slot Double Store
4886 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4887 single_instruction;
4888 stkSlot : R(read);
4889 src : C(read);
4890 MS : R;
4891 %}
4892
4893 // Integer Load (when sign bit propagation not needed)
4894 pipe_class iload_mem(iRegI dst, memory mem) %{
4895 single_instruction;
4896 mem : R(read);
4897 dst : C(write);
4898 MS : R;
4899 %}
4900
4901 // Integer Load from stack operand
4902 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4903 single_instruction;
4904 mem : R(read);
4905 dst : C(write);
4906 MS : R;
4907 %}
4908
4909 // Integer Load (when sign bit propagation or masking is needed)
4910 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4911 single_instruction;
4912 mem : R(read);
4913 dst : M(write);
4914 MS : R;
4915 %}
4916
4917 // Float Load
4918 pipe_class floadF_mem(regF dst, memory mem) %{
4919 single_instruction;
4920 mem : R(read);
4921 dst : M(write);
4922 MS : R;
4923 %}
4924
4925 // Float Load
4926 pipe_class floadD_mem(regD dst, memory mem) %{
4927 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4928 mem : R(read);
4929 dst : M(write);
4930 MS : R;
4931 %}
4932
4933 // Float Load
4934 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4935 single_instruction;
4936 stkSlot : R(read);
4937 dst : M(write);
4938 MS : R;
4939 %}
4940
4941 // Float Load
4942 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4943 single_instruction;
4944 stkSlot : R(read);
4945 dst : M(write);
4946 MS : R;
4947 %}
4948
4949 // Memory Nop
4950 pipe_class mem_nop() %{
4951 single_instruction;
4952 MS : R;
4953 %}
4954
4955 pipe_class sethi(iRegP dst, immI src) %{
4956 single_instruction;
4957 dst : E(write);
4958 IALU : R;
4959 %}
4960
4961 pipe_class loadPollP(iRegP poll) %{
4962 single_instruction;
4963 poll : R(read);
4964 MS : R;
4965 %}
4966
4967 pipe_class br(Universe br, label labl) %{
4968 single_instruction_with_delay_slot;
4969 BR : R;
4970 %}
4971
4972 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4973 single_instruction_with_delay_slot;
4974 cr : E(read);
4975 BR : R;
4976 %}
4977
4978 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4979 single_instruction_with_delay_slot;
4980 op1 : E(read);
4981 BR : R;
4982 MS : R;
4983 %}
4984
4985 // Compare and branch
4986 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
4987 instruction_count(2); has_delay_slot;
4988 cr : E(write);
4989 src1 : R(read);
4990 src2 : R(read);
4991 IALU : R;
4992 BR : R;
4993 %}
4994
4995 // Compare and branch
4996 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
4997 instruction_count(2); has_delay_slot;
4998 cr : E(write);
4999 src1 : R(read);
5000 IALU : R;
5001 BR : R;
5002 %}
5003
5004 // Compare and branch using cbcond
5005 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5006 single_instruction;
5007 src1 : E(read);
5008 src2 : E(read);
5009 IALU : R;
5010 BR : R;
5011 %}
5012
5013 // Compare and branch using cbcond
5014 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5015 single_instruction;
5016 src1 : E(read);
5017 IALU : R;
5018 BR : R;
5019 %}
5020
5021 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5022 single_instruction_with_delay_slot;
5023 cr : E(read);
5024 BR : R;
5025 %}
5026
5027 pipe_class br_nop() %{
5028 single_instruction;
5029 BR : R;
5030 %}
5031
5032 pipe_class simple_call(method meth) %{
5033 instruction_count(2); multiple_bundles; force_serialization;
5034 fixed_latency(100);
5035 BR : R(1);
5036 MS : R(1);
5037 A0 : R(1);
5038 %}
5039
5040 pipe_class compiled_call(method meth) %{
5041 instruction_count(1); multiple_bundles; force_serialization;
5042 fixed_latency(100);
5043 MS : R(1);
5044 %}
5045
5046 pipe_class call(method meth) %{
5047 instruction_count(0); multiple_bundles; force_serialization;
5048 fixed_latency(100);
5049 %}
5050
5051 pipe_class tail_call(Universe ignore, label labl) %{
5052 single_instruction; has_delay_slot;
5053 fixed_latency(100);
5054 BR : R(1);
5055 MS : R(1);
5056 %}
5057
5058 pipe_class ret(Universe ignore) %{
5059 single_instruction; has_delay_slot;
5060 BR : R(1);
5061 MS : R(1);
5062 %}
5063
5064 pipe_class ret_poll(g3RegP poll) %{
5065 instruction_count(3); has_delay_slot;
5066 poll : E(read);
5067 MS : R;
5068 %}
5069
5070 // The real do-nothing guy
5071 pipe_class empty( ) %{
5072 instruction_count(0);
5073 %}
5074
5075 pipe_class long_memory_op() %{
5076 instruction_count(0); multiple_bundles; force_serialization;
5077 fixed_latency(25);
5078 MS : R(1);
5079 %}
5080
5081 // Check-cast
5082 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5083 array : R(read);
5084 match : R(read);
5085 IALU : R(2);
5086 BR : R(2);
5087 MS : R;
5088 %}
5089
5090 // Convert FPU flags into +1,0,-1
5091 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5092 src1 : E(read);
5093 src2 : E(read);
5094 dst : E(write);
5095 FA : R;
5096 MS : R(2);
5097 BR : R(2);
5098 %}
5099
5100 // Compare for p < q, and conditionally add y
5101 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5102 p : E(read);
5103 q : E(read);
5104 y : E(read);
5105 IALU : R(3)
5106 %}
5107
5108 // Perform a compare, then move conditionally in a branch delay slot.
5109 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5110 src2 : E(read);
5111 srcdst : E(read);
5112 IALU : R;
5113 BR : R;
5114 %}
5115
5116 // Define the class for the Nop node
5117 define %{
5118 MachNop = ialu_nop;
5119 %}
5120
5121 %}
5122
5123 //----------INSTRUCTIONS-------------------------------------------------------
5124
5125 //------------Special Stack Slot instructions - no match rules-----------------
5126 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5127 // No match rule to avoid chain rule match.
5128 effect(DEF dst, USE src);
5129 ins_cost(MEMORY_REF_COST);
5130 format %{ "LDF $src,$dst\t! stkI to regF" %}
5131 opcode(Assembler::ldf_op3);
5132 ins_encode(simple_form3_mem_reg(src, dst));
5133 ins_pipe(floadF_stk);
5134 %}
5135
5136 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5137 // No match rule to avoid chain rule match.
5138 effect(DEF dst, USE src);
5139 ins_cost(MEMORY_REF_COST);
5140 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5141 opcode(Assembler::lddf_op3);
5142 ins_encode(simple_form3_mem_reg(src, dst));
5143 ins_pipe(floadD_stk);
5144 %}
5145
5146 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5147 // No match rule to avoid chain rule match.
5148 effect(DEF dst, USE src);
5149 ins_cost(MEMORY_REF_COST);
5150 format %{ "STF $src,$dst\t! regF to stkI" %}
5151 opcode(Assembler::stf_op3);
5152 ins_encode(simple_form3_mem_reg(dst, src));
5153 ins_pipe(fstoreF_stk_reg);
5154 %}
5155
5156 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5157 // No match rule to avoid chain rule match.
5158 effect(DEF dst, USE src);
5159 ins_cost(MEMORY_REF_COST);
5160 format %{ "STDF $src,$dst\t! regD to stkL" %}
5161 opcode(Assembler::stdf_op3);
5162 ins_encode(simple_form3_mem_reg(dst, src));
5163 ins_pipe(fstoreD_stk_reg);
5164 %}
5165
5166 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5167 effect(DEF dst, USE src);
5168 ins_cost(MEMORY_REF_COST*2);
5169 format %{ "STW $src,$dst.hi\t! long\n\t"
5170 "STW R_G0,$dst.lo" %}
5171 opcode(Assembler::stw_op3);
5172 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5173 ins_pipe(lstoreI_stk_reg);
5174 %}
5175
5176 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5177 // No match rule to avoid chain rule match.
5178 effect(DEF dst, USE src);
5179 ins_cost(MEMORY_REF_COST);
5180 format %{ "STX $src,$dst\t! regL to stkD" %}
5181 opcode(Assembler::stx_op3);
5182 ins_encode(simple_form3_mem_reg( dst, src ) );
5183 ins_pipe(istore_stk_reg);
5184 %}
5185
5186 //---------- Chain stack slots between similar types --------
5187
5188 // Load integer from stack slot
5189 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5190 match(Set dst src);
5191 ins_cost(MEMORY_REF_COST);
5192
5193 format %{ "LDUW $src,$dst\t!stk" %}
5194 opcode(Assembler::lduw_op3);
5195 ins_encode(simple_form3_mem_reg( src, dst ) );
5196 ins_pipe(iload_mem);
5197 %}
5198
5199 // Store integer to stack slot
5200 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5201 match(Set dst src);
5202 ins_cost(MEMORY_REF_COST);
5203
5204 format %{ "STW $src,$dst\t!stk" %}
5205 opcode(Assembler::stw_op3);
5206 ins_encode(simple_form3_mem_reg( dst, src ) );
5207 ins_pipe(istore_mem_reg);
5208 %}
5209
5210 // Load long from stack slot
5211 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5212 match(Set dst src);
5213
5214 ins_cost(MEMORY_REF_COST);
5215 format %{ "LDX $src,$dst\t! long" %}
5216 opcode(Assembler::ldx_op3);
5217 ins_encode(simple_form3_mem_reg( src, dst ) );
5218 ins_pipe(iload_mem);
5219 %}
5220
5221 // Store long to stack slot
5222 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5223 match(Set dst src);
5224
5225 ins_cost(MEMORY_REF_COST);
5226 format %{ "STX $src,$dst\t! long" %}
5227 opcode(Assembler::stx_op3);
5228 ins_encode(simple_form3_mem_reg( dst, src ) );
5229 ins_pipe(istore_mem_reg);
5230 %}
5231
5232 // Load pointer from stack slot, 64-bit encoding
5233 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5234 match(Set dst src);
5235 ins_cost(MEMORY_REF_COST);
5236 format %{ "LDX $src,$dst\t!ptr" %}
5237 opcode(Assembler::ldx_op3);
5238 ins_encode(simple_form3_mem_reg( src, dst ) );
5239 ins_pipe(iload_mem);
5240 %}
5241
5242 // Store pointer to stack slot
5243 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5244 match(Set dst src);
5245 ins_cost(MEMORY_REF_COST);
5246 format %{ "STX $src,$dst\t!ptr" %}
5247 opcode(Assembler::stx_op3);
5248 ins_encode(simple_form3_mem_reg( dst, src ) );
5249 ins_pipe(istore_mem_reg);
5250 %}
5251
5252 //------------Special Nop instructions for bundling - no match rules-----------
5253 // Nop using the A0 functional unit
5254 instruct Nop_A0() %{
5255 ins_cost(0);
5256
5257 format %{ "NOP ! Alu Pipeline" %}
5258 opcode(Assembler::or_op3, Assembler::arith_op);
5259 ins_encode( form2_nop() );
5260 ins_pipe(ialu_nop_A0);
5261 %}
5262
5263 // Nop using the A1 functional unit
5264 instruct Nop_A1( ) %{
5265 ins_cost(0);
5266
5267 format %{ "NOP ! Alu Pipeline" %}
5268 opcode(Assembler::or_op3, Assembler::arith_op);
5269 ins_encode( form2_nop() );
5270 ins_pipe(ialu_nop_A1);
5271 %}
5272
5273 // Nop using the memory functional unit
5274 instruct Nop_MS( ) %{
5275 ins_cost(0);
5276
5277 format %{ "NOP ! Memory Pipeline" %}
5278 ins_encode( emit_mem_nop );
5279 ins_pipe(mem_nop);
5280 %}
5281
5282 // Nop using the floating add functional unit
5283 instruct Nop_FA( ) %{
5284 ins_cost(0);
5285
5286 format %{ "NOP ! Floating Add Pipeline" %}
5287 ins_encode( emit_fadd_nop );
5288 ins_pipe(fadd_nop);
5289 %}
5290
5291 // Nop using the branch functional unit
5292 instruct Nop_BR( ) %{
5293 ins_cost(0);
5294
5295 format %{ "NOP ! Branch Pipeline" %}
5296 ins_encode( emit_br_nop );
5297 ins_pipe(br_nop);
5298 %}
5299
5300 //----------Load/Store/Move Instructions---------------------------------------
5301 //----------Load Instructions--------------------------------------------------
5302 // Load Byte (8bit signed)
5303 instruct loadB(iRegI dst, memory mem) %{
5304 match(Set dst (LoadB mem));
5305 ins_cost(MEMORY_REF_COST);
5306
5307 size(4);
5308 format %{ "LDSB $mem,$dst\t! byte" %}
5309 ins_encode %{
5310 __ ldsb($mem$$Address, $dst$$Register);
5311 %}
5312 ins_pipe(iload_mask_mem);
5313 %}
5314
5315 // Load Byte (8bit signed) into a Long Register
5316 instruct loadB2L(iRegL dst, memory mem) %{
5317 match(Set dst (ConvI2L (LoadB mem)));
5318 ins_cost(MEMORY_REF_COST);
5319
5320 size(4);
5321 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5322 ins_encode %{
5323 __ ldsb($mem$$Address, $dst$$Register);
5324 %}
5325 ins_pipe(iload_mask_mem);
5326 %}
5327
5328 // Load Unsigned Byte (8bit UNsigned) into an int reg
5329 instruct loadUB(iRegI dst, memory mem) %{
5330 match(Set dst (LoadUB mem));
5331 ins_cost(MEMORY_REF_COST);
5332
5333 size(4);
5334 format %{ "LDUB $mem,$dst\t! ubyte" %}
5335 ins_encode %{
5336 __ ldub($mem$$Address, $dst$$Register);
5337 %}
5338 ins_pipe(iload_mem);
5339 %}
5340
5341 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5342 instruct loadUB2L(iRegL dst, memory mem) %{
5343 match(Set dst (ConvI2L (LoadUB mem)));
5344 ins_cost(MEMORY_REF_COST);
5345
5346 size(4);
5347 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5348 ins_encode %{
5349 __ ldub($mem$$Address, $dst$$Register);
5350 %}
5351 ins_pipe(iload_mem);
5352 %}
5353
5354 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5355 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5356 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5357 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5358
5359 size(2*4);
5360 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5361 "AND $dst,right_n_bits($mask, 8),$dst" %}
5362 ins_encode %{
5363 __ ldub($mem$$Address, $dst$$Register);
5364 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5365 %}
5366 ins_pipe(iload_mem);
5367 %}
5368
5369 // Load Short (16bit signed)
5370 instruct loadS(iRegI dst, memory mem) %{
5371 match(Set dst (LoadS mem));
5372 ins_cost(MEMORY_REF_COST);
5373
5374 size(4);
5375 format %{ "LDSH $mem,$dst\t! short" %}
5376 ins_encode %{
5377 __ ldsh($mem$$Address, $dst$$Register);
5378 %}
5379 ins_pipe(iload_mask_mem);
5380 %}
5381
5382 // Load Short (16 bit signed) to Byte (8 bit signed)
5383 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5384 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5385 ins_cost(MEMORY_REF_COST);
5386
5387 size(4);
5388
5389 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5390 ins_encode %{
5391 __ ldsb($mem$$Address, $dst$$Register, 1);
5392 %}
5393 ins_pipe(iload_mask_mem);
5394 %}
5395
5396 // Load Short (16bit signed) into a Long Register
5397 instruct loadS2L(iRegL dst, memory mem) %{
5398 match(Set dst (ConvI2L (LoadS mem)));
5399 ins_cost(MEMORY_REF_COST);
5400
5401 size(4);
5402 format %{ "LDSH $mem,$dst\t! short -> long" %}
5403 ins_encode %{
5404 __ ldsh($mem$$Address, $dst$$Register);
5405 %}
5406 ins_pipe(iload_mask_mem);
5407 %}
5408
5409 // Load Unsigned Short/Char (16bit UNsigned)
5410 instruct loadUS(iRegI dst, memory mem) %{
5411 match(Set dst (LoadUS mem));
5412 ins_cost(MEMORY_REF_COST);
5413
5414 size(4);
5415 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5416 ins_encode %{
5417 __ lduh($mem$$Address, $dst$$Register);
5418 %}
5419 ins_pipe(iload_mem);
5420 %}
5421
5422 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5423 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5424 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5425 ins_cost(MEMORY_REF_COST);
5426
5427 size(4);
5428 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5429 ins_encode %{
5430 __ ldsb($mem$$Address, $dst$$Register, 1);
5431 %}
5432 ins_pipe(iload_mask_mem);
5433 %}
5434
5435 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5436 instruct loadUS2L(iRegL dst, memory mem) %{
5437 match(Set dst (ConvI2L (LoadUS mem)));
5438 ins_cost(MEMORY_REF_COST);
5439
5440 size(4);
5441 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5442 ins_encode %{
5443 __ lduh($mem$$Address, $dst$$Register);
5444 %}
5445 ins_pipe(iload_mem);
5446 %}
5447
5448 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5449 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5450 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5451 ins_cost(MEMORY_REF_COST);
5452
5453 size(4);
5454 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5455 ins_encode %{
5456 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5457 %}
5458 ins_pipe(iload_mem);
5459 %}
5460
5461 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5462 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5463 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5464 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5465
5466 size(2*4);
5467 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5468 "AND $dst,$mask,$dst" %}
5469 ins_encode %{
5470 Register Rdst = $dst$$Register;
5471 __ lduh($mem$$Address, Rdst);
5472 __ and3(Rdst, $mask$$constant, Rdst);
5473 %}
5474 ins_pipe(iload_mem);
5475 %}
5476
5477 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5478 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5479 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5480 effect(TEMP dst, TEMP tmp);
5481 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5482
5483 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5484 "SET right_n_bits($mask, 16),$tmp\n\t"
5485 "AND $dst,$tmp,$dst" %}
5486 ins_encode %{
5487 Register Rdst = $dst$$Register;
5488 Register Rtmp = $tmp$$Register;
5489 __ lduh($mem$$Address, Rdst);
5490 __ set($mask$$constant & right_n_bits(16), Rtmp);
5491 __ and3(Rdst, Rtmp, Rdst);
5492 %}
5493 ins_pipe(iload_mem);
5494 %}
5495
5496 // Load Integer
5497 instruct loadI(iRegI dst, memory mem) %{
5498 match(Set dst (LoadI mem));
5499 ins_cost(MEMORY_REF_COST);
5500
5501 size(4);
5502 format %{ "LDUW $mem,$dst\t! int" %}
5503 ins_encode %{
5504 __ lduw($mem$$Address, $dst$$Register);
5505 %}
5506 ins_pipe(iload_mem);
5507 %}
5508
5509 // Load Integer to Byte (8 bit signed)
5510 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5511 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5512 ins_cost(MEMORY_REF_COST);
5513
5514 size(4);
5515
5516 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5517 ins_encode %{
5518 __ ldsb($mem$$Address, $dst$$Register, 3);
5519 %}
5520 ins_pipe(iload_mask_mem);
5521 %}
5522
5523 // Load Integer to Unsigned Byte (8 bit UNsigned)
5524 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5525 match(Set dst (AndI (LoadI mem) mask));
5526 ins_cost(MEMORY_REF_COST);
5527
5528 size(4);
5529
5530 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5531 ins_encode %{
5532 __ ldub($mem$$Address, $dst$$Register, 3);
5533 %}
5534 ins_pipe(iload_mask_mem);
5535 %}
5536
5537 // Load Integer to Short (16 bit signed)
5538 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5539 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5540 ins_cost(MEMORY_REF_COST);
5541
5542 size(4);
5543
5544 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5545 ins_encode %{
5546 __ ldsh($mem$$Address, $dst$$Register, 2);
5547 %}
5548 ins_pipe(iload_mask_mem);
5549 %}
5550
5551 // Load Integer to Unsigned Short (16 bit UNsigned)
5552 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5553 match(Set dst (AndI (LoadI mem) mask));
5554 ins_cost(MEMORY_REF_COST);
5555
5556 size(4);
5557
5558 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5559 ins_encode %{
5560 __ lduh($mem$$Address, $dst$$Register, 2);
5561 %}
5562 ins_pipe(iload_mask_mem);
5563 %}
5564
5565 // Load Integer into a Long Register
5566 instruct loadI2L(iRegL dst, memory mem) %{
5567 match(Set dst (ConvI2L (LoadI mem)));
5568 ins_cost(MEMORY_REF_COST);
5569
5570 size(4);
5571 format %{ "LDSW $mem,$dst\t! int -> long" %}
5572 ins_encode %{
5573 __ ldsw($mem$$Address, $dst$$Register);
5574 %}
5575 ins_pipe(iload_mask_mem);
5576 %}
5577
5578 // Load Integer with mask 0xFF into a Long Register
5579 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5580 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5581 ins_cost(MEMORY_REF_COST);
5582
5583 size(4);
5584 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5585 ins_encode %{
5586 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5587 %}
5588 ins_pipe(iload_mem);
5589 %}
5590
5591 // Load Integer with mask 0xFFFF into a Long Register
5592 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5593 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5594 ins_cost(MEMORY_REF_COST);
5595
5596 size(4);
5597 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5598 ins_encode %{
5599 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5600 %}
5601 ins_pipe(iload_mem);
5602 %}
5603
5604 // Load Integer with a 12-bit mask into a Long Register
5605 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5606 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5607 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5608
5609 size(2*4);
5610 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5611 "AND $dst,$mask,$dst" %}
5612 ins_encode %{
5613 Register Rdst = $dst$$Register;
5614 __ lduw($mem$$Address, Rdst);
5615 __ and3(Rdst, $mask$$constant, Rdst);
5616 %}
5617 ins_pipe(iload_mem);
5618 %}
5619
5620 // Load Integer with a 31-bit mask into a Long Register
5621 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5622 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5623 effect(TEMP dst, TEMP tmp);
5624 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5625
5626 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5627 "SET $mask,$tmp\n\t"
5628 "AND $dst,$tmp,$dst" %}
5629 ins_encode %{
5630 Register Rdst = $dst$$Register;
5631 Register Rtmp = $tmp$$Register;
5632 __ lduw($mem$$Address, Rdst);
5633 __ set($mask$$constant, Rtmp);
5634 __ and3(Rdst, Rtmp, Rdst);
5635 %}
5636 ins_pipe(iload_mem);
5637 %}
5638
5639 // Load Unsigned Integer into a Long Register
5640 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5641 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5642 ins_cost(MEMORY_REF_COST);
5643
5644 size(4);
5645 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5646 ins_encode %{
5647 __ lduw($mem$$Address, $dst$$Register);
5648 %}
5649 ins_pipe(iload_mem);
5650 %}
5651
5652 // Load Long - aligned
5653 instruct loadL(iRegL dst, memory mem ) %{
5654 match(Set dst (LoadL mem));
5655 ins_cost(MEMORY_REF_COST);
5656
5657 size(4);
5658 format %{ "LDX $mem,$dst\t! long" %}
5659 ins_encode %{
5660 __ ldx($mem$$Address, $dst$$Register);
5661 %}
5662 ins_pipe(iload_mem);
5663 %}
5664
5665 // Load Long - UNaligned
5666 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5667 match(Set dst (LoadL_unaligned mem));
5668 effect(KILL tmp);
5669 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5670 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5671 "\tLDUW $mem ,$dst\n"
5672 "\tSLLX #32, $dst, $dst\n"
5673 "\tOR $dst, R_O7, $dst" %}
5674 opcode(Assembler::lduw_op3);
5675 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5676 ins_pipe(iload_mem);
5677 %}
5678
5679 // Load Range
5680 instruct loadRange(iRegI dst, memory mem) %{
5681 match(Set dst (LoadRange mem));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 format %{ "LDUW $mem,$dst\t! range" %}
5685 opcode(Assembler::lduw_op3);
5686 ins_encode(simple_form3_mem_reg( mem, dst ) );
5687 ins_pipe(iload_mem);
5688 %}
5689
5690 // Load Integer into %f register (for fitos/fitod)
5691 instruct loadI_freg(regF dst, memory mem) %{
5692 match(Set dst (LoadI mem));
5693 ins_cost(MEMORY_REF_COST);
5694
5695 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5696 opcode(Assembler::ldf_op3);
5697 ins_encode(simple_form3_mem_reg( mem, dst ) );
5698 ins_pipe(floadF_mem);
5699 %}
5700
5701 // Load Pointer
5702 instruct loadP(iRegP dst, memory mem) %{
5703 match(Set dst (LoadP mem));
5704 ins_cost(MEMORY_REF_COST);
5705 size(4);
5706
5707 format %{ "LDX $mem,$dst\t! ptr" %}
5708 ins_encode %{
5709 __ ldx($mem$$Address, $dst$$Register);
5710 %}
5711 ins_pipe(iload_mem);
5712 %}
5713
5714 // Load Compressed Pointer
5715 instruct loadN(iRegN dst, memory mem) %{
5716 match(Set dst (LoadN mem));
5717 ins_cost(MEMORY_REF_COST);
5718 size(4);
5719
5720 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5721 ins_encode %{
5722 __ lduw($mem$$Address, $dst$$Register);
5723 %}
5724 ins_pipe(iload_mem);
5725 %}
5726
5727 // Load Klass Pointer
5728 instruct loadKlass(iRegP dst, memory mem) %{
5729 match(Set dst (LoadKlass mem));
5730 ins_cost(MEMORY_REF_COST);
5731 size(4);
5732
5733 format %{ "LDX $mem,$dst\t! klass ptr" %}
5734 ins_encode %{
5735 __ ldx($mem$$Address, $dst$$Register);
5736 %}
5737 ins_pipe(iload_mem);
5738 %}
5739
5740 // Load narrow Klass Pointer
5741 instruct loadNKlass(iRegN dst, memory mem) %{
5742 match(Set dst (LoadNKlass mem));
5743 ins_cost(MEMORY_REF_COST);
5744 size(4);
5745
5746 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5747 ins_encode %{
5748 __ lduw($mem$$Address, $dst$$Register);
5749 %}
5750 ins_pipe(iload_mem);
5751 %}
5752
5753 // Load Double
5754 instruct loadD(regD dst, memory mem) %{
5755 match(Set dst (LoadD mem));
5756 ins_cost(MEMORY_REF_COST);
5757
5758 format %{ "LDDF $mem,$dst" %}
5759 opcode(Assembler::lddf_op3);
5760 ins_encode(simple_form3_mem_reg( mem, dst ) );
5761 ins_pipe(floadD_mem);
5762 %}
5763
5764 // Load Double - UNaligned
5765 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5766 match(Set dst (LoadD_unaligned mem));
5767 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5768 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5769 "\tLDF $mem+4,$dst.lo\t!" %}
5770 opcode(Assembler::ldf_op3);
5771 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5772 ins_pipe(iload_mem);
5773 %}
5774
5775 // Load Float
5776 instruct loadF(regF dst, memory mem) %{
5777 match(Set dst (LoadF mem));
5778 ins_cost(MEMORY_REF_COST);
5779
5780 format %{ "LDF $mem,$dst" %}
5781 opcode(Assembler::ldf_op3);
5782 ins_encode(simple_form3_mem_reg( mem, dst ) );
5783 ins_pipe(floadF_mem);
5784 %}
5785
5786 // Load Constant
5787 instruct loadConI( iRegI dst, immI src ) %{
5788 match(Set dst src);
5789 ins_cost(DEFAULT_COST * 3/2);
5790 format %{ "SET $src,$dst" %}
5791 ins_encode( Set32(src, dst) );
5792 ins_pipe(ialu_hi_lo_reg);
5793 %}
5794
5795 instruct loadConI13( iRegI dst, immI13 src ) %{
5796 match(Set dst src);
5797
5798 size(4);
5799 format %{ "MOV $src,$dst" %}
5800 ins_encode( Set13( src, dst ) );
5801 ins_pipe(ialu_imm);
5802 %}
5803
5804 instruct loadConP_set(iRegP dst, immP_set con) %{
5805 match(Set dst con);
5806 ins_cost(DEFAULT_COST * 3/2);
5807 format %{ "SET $con,$dst\t! ptr" %}
5808 ins_encode %{
5809 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5810 intptr_t val = $con$$constant;
5811 if (constant_reloc == relocInfo::oop_type) {
5812 __ set_oop_constant((jobject) val, $dst$$Register);
5813 } else if (constant_reloc == relocInfo::metadata_type) {
5814 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5815 } else { // non-oop pointers, e.g. card mark base, heap top
5816 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5817 __ set(val, $dst$$Register);
5818 }
5819 %}
5820 ins_pipe(loadConP);
5821 %}
5822
5823 instruct loadConP_load(iRegP dst, immP_load con) %{
5824 match(Set dst con);
5825 ins_cost(MEMORY_REF_COST);
5826 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5827 ins_encode %{
5828 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5829 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5830 %}
5831 ins_pipe(loadConP);
5832 %}
5833
5834 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5835 match(Set dst con);
5836 ins_cost(DEFAULT_COST * 3/2);
5837 format %{ "SET $con,$dst\t! non-oop ptr" %}
5838 ins_encode %{
5839 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5840 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5841 } else {
5842 __ set($con$$constant, $dst$$Register);
5843 }
5844 %}
5845 ins_pipe(loadConP);
5846 %}
5847
5848 instruct loadConP0(iRegP dst, immP0 src) %{
5849 match(Set dst src);
5850
5851 size(4);
5852 format %{ "CLR $dst\t!ptr" %}
5853 ins_encode %{
5854 __ clr($dst$$Register);
5855 %}
5856 ins_pipe(ialu_imm);
5857 %}
5858
5859 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5860 match(Set dst src);
5861 ins_cost(DEFAULT_COST);
5862 format %{ "SET $src,$dst\t!ptr" %}
5863 ins_encode %{
5864 AddressLiteral polling_page(os::get_polling_page());
5865 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5866 %}
5867 ins_pipe(loadConP_poll);
5868 %}
5869
5870 instruct loadConN0(iRegN dst, immN0 src) %{
5871 match(Set dst src);
5872
5873 size(4);
5874 format %{ "CLR $dst\t! compressed NULL ptr" %}
5875 ins_encode %{
5876 __ clr($dst$$Register);
5877 %}
5878 ins_pipe(ialu_imm);
5879 %}
5880
5881 instruct loadConN(iRegN dst, immN src) %{
5882 match(Set dst src);
5883 ins_cost(DEFAULT_COST * 3/2);
5884 format %{ "SET $src,$dst\t! compressed ptr" %}
5885 ins_encode %{
5886 Register dst = $dst$$Register;
5887 __ set_narrow_oop((jobject)$src$$constant, dst);
5888 %}
5889 ins_pipe(ialu_hi_lo_reg);
5890 %}
5891
5892 instruct loadConNKlass(iRegN dst, immNKlass src) %{
5893 match(Set dst src);
5894 ins_cost(DEFAULT_COST * 3/2);
5895 format %{ "SET $src,$dst\t! compressed klass ptr" %}
5896 ins_encode %{
5897 Register dst = $dst$$Register;
5898 __ set_narrow_klass((Klass*)$src$$constant, dst);
5899 %}
5900 ins_pipe(ialu_hi_lo_reg);
5901 %}
5902
5903 // Materialize long value (predicated by immL_cheap).
5904 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
5905 match(Set dst con);
5906 effect(KILL tmp);
5907 ins_cost(DEFAULT_COST * 3);
5908 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
5909 ins_encode %{
5910 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
5911 %}
5912 ins_pipe(loadConL);
5913 %}
5914
5915 // Load long value from constant table (predicated by immL_expensive).
5916 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
5917 match(Set dst con);
5918 ins_cost(MEMORY_REF_COST);
5919 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
5920 ins_encode %{
5921 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5922 __ ldx($constanttablebase, con_offset, $dst$$Register);
5923 %}
5924 ins_pipe(loadConL);
5925 %}
5926
5927 instruct loadConL0( iRegL dst, immL0 src ) %{
5928 match(Set dst src);
5929 ins_cost(DEFAULT_COST);
5930 size(4);
5931 format %{ "CLR $dst\t! long" %}
5932 ins_encode( Set13( src, dst ) );
5933 ins_pipe(ialu_imm);
5934 %}
5935
5936 instruct loadConL13( iRegL dst, immL13 src ) %{
5937 match(Set dst src);
5938 ins_cost(DEFAULT_COST * 2);
5939
5940 size(4);
5941 format %{ "MOV $src,$dst\t! long" %}
5942 ins_encode( Set13( src, dst ) );
5943 ins_pipe(ialu_imm);
5944 %}
5945
5946 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
5947 match(Set dst con);
5948 effect(KILL tmp);
5949 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
5950 ins_encode %{
5951 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5952 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
5953 %}
5954 ins_pipe(loadConFD);
5955 %}
5956
5957 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
5958 match(Set dst con);
5959 effect(KILL tmp);
5960 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
5961 ins_encode %{
5962 // XXX This is a quick fix for 6833573.
5963 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
5964 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5965 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
5966 %}
5967 ins_pipe(loadConFD);
5968 %}
5969
5970 // Prefetch instructions for allocation.
5971 // Must be safe to execute with invalid address (cannot fault).
5972
5973 instruct prefetchAlloc( memory mem ) %{
5974 predicate(AllocatePrefetchInstr == 0);
5975 match( PrefetchAllocation mem );
5976 ins_cost(MEMORY_REF_COST);
5977
5978 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
5979 opcode(Assembler::prefetch_op3);
5980 ins_encode( form3_mem_prefetch_write( mem ) );
5981 ins_pipe(iload_mem);
5982 %}
5983
5984 // Use BIS instruction to prefetch for allocation.
5985 // Could fault, need space at the end of TLAB.
5986 instruct prefetchAlloc_bis( iRegP dst ) %{
5987 predicate(AllocatePrefetchInstr == 1);
5988 match( PrefetchAllocation dst );
5989 ins_cost(MEMORY_REF_COST);
5990 size(4);
5991
5992 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
5993 ins_encode %{
5994 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
5995 %}
5996 ins_pipe(istore_mem_reg);
5997 %}
5998
5999 // Next code is used for finding next cache line address to prefetch.
6000 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6001 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6002 ins_cost(DEFAULT_COST);
6003 size(4);
6004
6005 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6006 ins_encode %{
6007 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6008 %}
6009 ins_pipe(ialu_reg_imm);
6010 %}
6011
6012 //----------Store Instructions-------------------------------------------------
6013 // Store Byte
6014 instruct storeB(memory mem, iRegI src) %{
6015 match(Set mem (StoreB mem src));
6016 ins_cost(MEMORY_REF_COST);
6017
6018 format %{ "STB $src,$mem\t! byte" %}
6019 opcode(Assembler::stb_op3);
6020 ins_encode(simple_form3_mem_reg( mem, src ) );
6021 ins_pipe(istore_mem_reg);
6022 %}
6023
6024 instruct storeB0(memory mem, immI0 src) %{
6025 match(Set mem (StoreB mem src));
6026 ins_cost(MEMORY_REF_COST);
6027
6028 format %{ "STB $src,$mem\t! byte" %}
6029 opcode(Assembler::stb_op3);
6030 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6031 ins_pipe(istore_mem_zero);
6032 %}
6033
6034 instruct storeCM0(memory mem, immI0 src) %{
6035 match(Set mem (StoreCM mem src));
6036 ins_cost(MEMORY_REF_COST);
6037
6038 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6039 opcode(Assembler::stb_op3);
6040 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6041 ins_pipe(istore_mem_zero);
6042 %}
6043
6044 // Store Char/Short
6045 instruct storeC(memory mem, iRegI src) %{
6046 match(Set mem (StoreC mem src));
6047 ins_cost(MEMORY_REF_COST);
6048
6049 format %{ "STH $src,$mem\t! short" %}
6050 opcode(Assembler::sth_op3);
6051 ins_encode(simple_form3_mem_reg( mem, src ) );
6052 ins_pipe(istore_mem_reg);
6053 %}
6054
6055 instruct storeC0(memory mem, immI0 src) %{
6056 match(Set mem (StoreC mem src));
6057 ins_cost(MEMORY_REF_COST);
6058
6059 format %{ "STH $src,$mem\t! short" %}
6060 opcode(Assembler::sth_op3);
6061 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6062 ins_pipe(istore_mem_zero);
6063 %}
6064
6065 // Store Integer
6066 instruct storeI(memory mem, iRegI src) %{
6067 match(Set mem (StoreI mem src));
6068 ins_cost(MEMORY_REF_COST);
6069
6070 format %{ "STW $src,$mem" %}
6071 opcode(Assembler::stw_op3);
6072 ins_encode(simple_form3_mem_reg( mem, src ) );
6073 ins_pipe(istore_mem_reg);
6074 %}
6075
6076 // Store Long
6077 instruct storeL(memory mem, iRegL src) %{
6078 match(Set mem (StoreL mem src));
6079 ins_cost(MEMORY_REF_COST);
6080 format %{ "STX $src,$mem\t! long" %}
6081 opcode(Assembler::stx_op3);
6082 ins_encode(simple_form3_mem_reg( mem, src ) );
6083 ins_pipe(istore_mem_reg);
6084 %}
6085
6086 instruct storeI0(memory mem, immI0 src) %{
6087 match(Set mem (StoreI mem src));
6088 ins_cost(MEMORY_REF_COST);
6089
6090 format %{ "STW $src,$mem" %}
6091 opcode(Assembler::stw_op3);
6092 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6093 ins_pipe(istore_mem_zero);
6094 %}
6095
6096 instruct storeL0(memory mem, immL0 src) %{
6097 match(Set mem (StoreL mem src));
6098 ins_cost(MEMORY_REF_COST);
6099
6100 format %{ "STX $src,$mem" %}
6101 opcode(Assembler::stx_op3);
6102 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6103 ins_pipe(istore_mem_zero);
6104 %}
6105
6106 // Store Integer from float register (used after fstoi)
6107 instruct storeI_Freg(memory mem, regF src) %{
6108 match(Set mem (StoreI mem src));
6109 ins_cost(MEMORY_REF_COST);
6110
6111 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6112 opcode(Assembler::stf_op3);
6113 ins_encode(simple_form3_mem_reg( mem, src ) );
6114 ins_pipe(fstoreF_mem_reg);
6115 %}
6116
6117 // Store Pointer
6118 instruct storeP(memory dst, sp_ptr_RegP src) %{
6119 match(Set dst (StoreP dst src));
6120 ins_cost(MEMORY_REF_COST);
6121
6122 format %{ "STX $src,$dst\t! ptr" %}
6123 opcode(Assembler::stx_op3, 0, REGP_OP);
6124 ins_encode( form3_mem_reg( dst, src ) );
6125 ins_pipe(istore_mem_spORreg);
6126 %}
6127
6128 instruct storeP0(memory dst, immP0 src) %{
6129 match(Set dst (StoreP dst src));
6130 ins_cost(MEMORY_REF_COST);
6131
6132 format %{ "STX $src,$dst\t! ptr" %}
6133 opcode(Assembler::stx_op3, 0, REGP_OP);
6134 ins_encode( form3_mem_reg( dst, R_G0 ) );
6135 ins_pipe(istore_mem_zero);
6136 %}
6137
6138 // Store Compressed Pointer
6139 instruct storeN(memory dst, iRegN src) %{
6140 match(Set dst (StoreN dst src));
6141 ins_cost(MEMORY_REF_COST);
6142 size(4);
6143
6144 format %{ "STW $src,$dst\t! compressed ptr" %}
6145 ins_encode %{
6146 Register base = as_Register($dst$$base);
6147 Register index = as_Register($dst$$index);
6148 Register src = $src$$Register;
6149 if (index != G0) {
6150 __ stw(src, base, index);
6151 } else {
6152 __ stw(src, base, $dst$$disp);
6153 }
6154 %}
6155 ins_pipe(istore_mem_spORreg);
6156 %}
6157
6158 instruct storeNKlass(memory dst, iRegN src) %{
6159 match(Set dst (StoreNKlass dst src));
6160 ins_cost(MEMORY_REF_COST);
6161 size(4);
6162
6163 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6164 ins_encode %{
6165 Register base = as_Register($dst$$base);
6166 Register index = as_Register($dst$$index);
6167 Register src = $src$$Register;
6168 if (index != G0) {
6169 __ stw(src, base, index);
6170 } else {
6171 __ stw(src, base, $dst$$disp);
6172 }
6173 %}
6174 ins_pipe(istore_mem_spORreg);
6175 %}
6176
6177 instruct storeN0(memory dst, immN0 src) %{
6178 match(Set dst (StoreN dst src));
6179 ins_cost(MEMORY_REF_COST);
6180 size(4);
6181
6182 format %{ "STW $src,$dst\t! compressed ptr" %}
6183 ins_encode %{
6184 Register base = as_Register($dst$$base);
6185 Register index = as_Register($dst$$index);
6186 if (index != G0) {
6187 __ stw(0, base, index);
6188 } else {
6189 __ stw(0, base, $dst$$disp);
6190 }
6191 %}
6192 ins_pipe(istore_mem_zero);
6193 %}
6194
6195 // Store Double
6196 instruct storeD( memory mem, regD src) %{
6197 match(Set mem (StoreD mem src));
6198 ins_cost(MEMORY_REF_COST);
6199
6200 format %{ "STDF $src,$mem" %}
6201 opcode(Assembler::stdf_op3);
6202 ins_encode(simple_form3_mem_reg( mem, src ) );
6203 ins_pipe(fstoreD_mem_reg);
6204 %}
6205
6206 instruct storeD0( memory mem, immD0 src) %{
6207 match(Set mem (StoreD mem src));
6208 ins_cost(MEMORY_REF_COST);
6209
6210 format %{ "STX $src,$mem" %}
6211 opcode(Assembler::stx_op3);
6212 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6213 ins_pipe(fstoreD_mem_zero);
6214 %}
6215
6216 // Store Float
6217 instruct storeF( memory mem, regF src) %{
6218 match(Set mem (StoreF mem src));
6219 ins_cost(MEMORY_REF_COST);
6220
6221 format %{ "STF $src,$mem" %}
6222 opcode(Assembler::stf_op3);
6223 ins_encode(simple_form3_mem_reg( mem, src ) );
6224 ins_pipe(fstoreF_mem_reg);
6225 %}
6226
6227 instruct storeF0( memory mem, immF0 src) %{
6228 match(Set mem (StoreF mem src));
6229 ins_cost(MEMORY_REF_COST);
6230
6231 format %{ "STW $src,$mem\t! storeF0" %}
6232 opcode(Assembler::stw_op3);
6233 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6234 ins_pipe(fstoreF_mem_zero);
6235 %}
6236
6237 // Convert oop pointer into compressed form
6238 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6239 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6240 match(Set dst (EncodeP src));
6241 format %{ "encode_heap_oop $src, $dst" %}
6242 ins_encode %{
6243 __ encode_heap_oop($src$$Register, $dst$$Register);
6244 %}
6245 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6246 ins_pipe(ialu_reg);
6247 %}
6248
6249 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6250 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6251 match(Set dst (EncodeP src));
6252 format %{ "encode_heap_oop_not_null $src, $dst" %}
6253 ins_encode %{
6254 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6255 %}
6256 ins_pipe(ialu_reg);
6257 %}
6258
6259 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6260 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6261 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6262 match(Set dst (DecodeN src));
6263 format %{ "decode_heap_oop $src, $dst" %}
6264 ins_encode %{
6265 __ decode_heap_oop($src$$Register, $dst$$Register);
6266 %}
6267 ins_pipe(ialu_reg);
6268 %}
6269
6270 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6271 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6272 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6273 match(Set dst (DecodeN src));
6274 format %{ "decode_heap_oop_not_null $src, $dst" %}
6275 ins_encode %{
6276 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6277 %}
6278 ins_pipe(ialu_reg);
6279 %}
6280
6281 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6282 match(Set dst (EncodePKlass src));
6283 format %{ "encode_klass_not_null $src, $dst" %}
6284 ins_encode %{
6285 __ encode_klass_not_null($src$$Register, $dst$$Register);
6286 %}
6287 ins_pipe(ialu_reg);
6288 %}
6289
6290 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6291 match(Set dst (DecodeNKlass src));
6292 format %{ "decode_klass_not_null $src, $dst" %}
6293 ins_encode %{
6294 __ decode_klass_not_null($src$$Register, $dst$$Register);
6295 %}
6296 ins_pipe(ialu_reg);
6297 %}
6298
6299 //----------MemBar Instructions-----------------------------------------------
6300 // Memory barrier flavors
6301
6302 instruct membar_acquire() %{
6303 match(MemBarAcquire);
6304 match(LoadFence);
6305 ins_cost(4*MEMORY_REF_COST);
6306
6307 size(0);
6308 format %{ "MEMBAR-acquire" %}
6309 ins_encode( enc_membar_acquire );
6310 ins_pipe(long_memory_op);
6311 %}
6312
6313 instruct membar_acquire_lock() %{
6314 match(MemBarAcquireLock);
6315 ins_cost(0);
6316
6317 size(0);
6318 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6319 ins_encode( );
6320 ins_pipe(empty);
6321 %}
6322
6323 instruct membar_release() %{
6324 match(MemBarRelease);
6325 match(StoreFence);
6326 ins_cost(4*MEMORY_REF_COST);
6327
6328 size(0);
6329 format %{ "MEMBAR-release" %}
6330 ins_encode( enc_membar_release );
6331 ins_pipe(long_memory_op);
6332 %}
6333
6334 instruct membar_release_lock() %{
6335 match(MemBarReleaseLock);
6336 ins_cost(0);
6337
6338 size(0);
6339 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6340 ins_encode( );
6341 ins_pipe(empty);
6342 %}
6343
6344 instruct membar_volatile() %{
6345 match(MemBarVolatile);
6346 ins_cost(4*MEMORY_REF_COST);
6347
6348 size(4);
6349 format %{ "MEMBAR-volatile" %}
6350 ins_encode( enc_membar_volatile );
6351 ins_pipe(long_memory_op);
6352 %}
6353
6354 instruct unnecessary_membar_volatile() %{
6355 match(MemBarVolatile);
6356 predicate(Matcher::post_store_load_barrier(n));
6357 ins_cost(0);
6358
6359 size(0);
6360 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6361 ins_encode( );
6362 ins_pipe(empty);
6363 %}
6364
6365 instruct membar_storestore() %{
6366 match(MemBarStoreStore);
6367 ins_cost(0);
6368
6369 size(0);
6370 format %{ "!MEMBAR-storestore (empty encoding)" %}
6371 ins_encode( );
6372 ins_pipe(empty);
6373 %}
6374
6375 //----------Register Move Instructions-----------------------------------------
6376 instruct roundDouble_nop(regD dst) %{
6377 match(Set dst (RoundDouble dst));
6378 ins_cost(0);
6379 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6380 ins_encode( );
6381 ins_pipe(empty);
6382 %}
6383
6384
6385 instruct roundFloat_nop(regF dst) %{
6386 match(Set dst (RoundFloat dst));
6387 ins_cost(0);
6388 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6389 ins_encode( );
6390 ins_pipe(empty);
6391 %}
6392
6393
6394 // Cast Index to Pointer for unsafe natives
6395 instruct castX2P(iRegX src, iRegP dst) %{
6396 match(Set dst (CastX2P src));
6397
6398 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6399 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6400 ins_pipe(ialu_reg);
6401 %}
6402
6403 // Cast Pointer to Index for unsafe natives
6404 instruct castP2X(iRegP src, iRegX dst) %{
6405 match(Set dst (CastP2X src));
6406
6407 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6408 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6409 ins_pipe(ialu_reg);
6410 %}
6411
6412 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6413 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6414 match(Set stkSlot src); // chain rule
6415 ins_cost(MEMORY_REF_COST);
6416 format %{ "STDF $src,$stkSlot\t!stk" %}
6417 opcode(Assembler::stdf_op3);
6418 ins_encode(simple_form3_mem_reg(stkSlot, src));
6419 ins_pipe(fstoreD_stk_reg);
6420 %}
6421
6422 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6423 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6424 match(Set dst stkSlot); // chain rule
6425 ins_cost(MEMORY_REF_COST);
6426 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6427 opcode(Assembler::lddf_op3);
6428 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6429 ins_pipe(floadD_stk);
6430 %}
6431
6432 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6433 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6434 match(Set stkSlot src); // chain rule
6435 ins_cost(MEMORY_REF_COST);
6436 format %{ "STF $src,$stkSlot\t!stk" %}
6437 opcode(Assembler::stf_op3);
6438 ins_encode(simple_form3_mem_reg(stkSlot, src));
6439 ins_pipe(fstoreF_stk_reg);
6440 %}
6441
6442 //----------Conditional Move---------------------------------------------------
6443 // Conditional move
6444 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6445 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6446 ins_cost(150);
6447 format %{ "MOV$cmp $pcc,$src,$dst" %}
6448 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6449 ins_pipe(ialu_reg);
6450 %}
6451
6452 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6453 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6454 ins_cost(140);
6455 format %{ "MOV$cmp $pcc,$src,$dst" %}
6456 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6457 ins_pipe(ialu_imm);
6458 %}
6459
6460 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6461 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6462 ins_cost(150);
6463 size(4);
6464 format %{ "MOV$cmp $icc,$src,$dst" %}
6465 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6466 ins_pipe(ialu_reg);
6467 %}
6468
6469 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6470 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6471 ins_cost(140);
6472 size(4);
6473 format %{ "MOV$cmp $icc,$src,$dst" %}
6474 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6475 ins_pipe(ialu_imm);
6476 %}
6477
6478 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6479 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6480 ins_cost(150);
6481 size(4);
6482 format %{ "MOV$cmp $icc,$src,$dst" %}
6483 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6484 ins_pipe(ialu_reg);
6485 %}
6486
6487 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6488 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6489 ins_cost(140);
6490 size(4);
6491 format %{ "MOV$cmp $icc,$src,$dst" %}
6492 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6493 ins_pipe(ialu_imm);
6494 %}
6495
6496 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6497 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6498 ins_cost(150);
6499 size(4);
6500 format %{ "MOV$cmp $fcc,$src,$dst" %}
6501 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6502 ins_pipe(ialu_reg);
6503 %}
6504
6505 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6506 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6507 ins_cost(140);
6508 size(4);
6509 format %{ "MOV$cmp $fcc,$src,$dst" %}
6510 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6511 ins_pipe(ialu_imm);
6512 %}
6513
6514 // Conditional move for RegN. Only cmov(reg,reg).
6515 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6516 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6517 ins_cost(150);
6518 format %{ "MOV$cmp $pcc,$src,$dst" %}
6519 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6520 ins_pipe(ialu_reg);
6521 %}
6522
6523 // This instruction also works with CmpN so we don't need cmovNN_reg.
6524 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6525 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6526 ins_cost(150);
6527 size(4);
6528 format %{ "MOV$cmp $icc,$src,$dst" %}
6529 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6530 ins_pipe(ialu_reg);
6531 %}
6532
6533 // This instruction also works with CmpN so we don't need cmovNN_reg.
6534 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6535 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6536 ins_cost(150);
6537 size(4);
6538 format %{ "MOV$cmp $icc,$src,$dst" %}
6539 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6540 ins_pipe(ialu_reg);
6541 %}
6542
6543 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6544 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6545 ins_cost(150);
6546 size(4);
6547 format %{ "MOV$cmp $fcc,$src,$dst" %}
6548 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6549 ins_pipe(ialu_reg);
6550 %}
6551
6552 // Conditional move
6553 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6554 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6555 ins_cost(150);
6556 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6557 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6558 ins_pipe(ialu_reg);
6559 %}
6560
6561 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6562 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6563 ins_cost(140);
6564 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6565 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6566 ins_pipe(ialu_imm);
6567 %}
6568
6569 // This instruction also works with CmpN so we don't need cmovPN_reg.
6570 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6571 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6572 ins_cost(150);
6573
6574 size(4);
6575 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6576 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6577 ins_pipe(ialu_reg);
6578 %}
6579
6580 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6581 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6582 ins_cost(150);
6583
6584 size(4);
6585 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6586 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6587 ins_pipe(ialu_reg);
6588 %}
6589
6590 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6591 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6592 ins_cost(140);
6593
6594 size(4);
6595 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6596 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6597 ins_pipe(ialu_imm);
6598 %}
6599
6600 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6601 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6602 ins_cost(140);
6603
6604 size(4);
6605 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6606 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6607 ins_pipe(ialu_imm);
6608 %}
6609
6610 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6611 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6612 ins_cost(150);
6613 size(4);
6614 format %{ "MOV$cmp $fcc,$src,$dst" %}
6615 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6616 ins_pipe(ialu_imm);
6617 %}
6618
6619 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6620 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6621 ins_cost(140);
6622 size(4);
6623 format %{ "MOV$cmp $fcc,$src,$dst" %}
6624 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6625 ins_pipe(ialu_imm);
6626 %}
6627
6628 // Conditional move
6629 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6630 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6631 ins_cost(150);
6632 opcode(0x101);
6633 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6634 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6635 ins_pipe(int_conditional_float_move);
6636 %}
6637
6638 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6639 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6640 ins_cost(150);
6641
6642 size(4);
6643 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6644 opcode(0x101);
6645 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6646 ins_pipe(int_conditional_float_move);
6647 %}
6648
6649 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6650 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6651 ins_cost(150);
6652
6653 size(4);
6654 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6655 opcode(0x101);
6656 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6657 ins_pipe(int_conditional_float_move);
6658 %}
6659
6660 // Conditional move,
6661 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6662 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6663 ins_cost(150);
6664 size(4);
6665 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6666 opcode(0x1);
6667 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6668 ins_pipe(int_conditional_double_move);
6669 %}
6670
6671 // Conditional move
6672 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6673 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6674 ins_cost(150);
6675 size(4);
6676 opcode(0x102);
6677 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6678 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6679 ins_pipe(int_conditional_double_move);
6680 %}
6681
6682 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6683 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6684 ins_cost(150);
6685
6686 size(4);
6687 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6688 opcode(0x102);
6689 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6690 ins_pipe(int_conditional_double_move);
6691 %}
6692
6693 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6694 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6695 ins_cost(150);
6696
6697 size(4);
6698 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6699 opcode(0x102);
6700 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6701 ins_pipe(int_conditional_double_move);
6702 %}
6703
6704 // Conditional move,
6705 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6706 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6707 ins_cost(150);
6708 size(4);
6709 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6710 opcode(0x2);
6711 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6712 ins_pipe(int_conditional_double_move);
6713 %}
6714
6715 // Conditional move
6716 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6717 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6718 ins_cost(150);
6719 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6720 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6721 ins_pipe(ialu_reg);
6722 %}
6723
6724 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6725 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6726 ins_cost(140);
6727 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6728 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6729 ins_pipe(ialu_imm);
6730 %}
6731
6732 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6733 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6734 ins_cost(150);
6735
6736 size(4);
6737 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6738 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6739 ins_pipe(ialu_reg);
6740 %}
6741
6742
6743 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6744 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6745 ins_cost(150);
6746
6747 size(4);
6748 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6749 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6750 ins_pipe(ialu_reg);
6751 %}
6752
6753
6754 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6755 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6756 ins_cost(150);
6757
6758 size(4);
6759 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6760 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6761 ins_pipe(ialu_reg);
6762 %}
6763
6764
6765
6766 //----------OS and Locking Instructions----------------------------------------
6767
6768 // This name is KNOWN by the ADLC and cannot be changed.
6769 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6770 // for this guy.
6771 instruct tlsLoadP(g2RegP dst) %{
6772 match(Set dst (ThreadLocal));
6773
6774 size(0);
6775 ins_cost(0);
6776 format %{ "# TLS is in G2" %}
6777 ins_encode( /*empty encoding*/ );
6778 ins_pipe(ialu_none);
6779 %}
6780
6781 instruct checkCastPP( iRegP dst ) %{
6782 match(Set dst (CheckCastPP dst));
6783
6784 size(0);
6785 format %{ "# checkcastPP of $dst" %}
6786 ins_encode( /*empty encoding*/ );
6787 ins_pipe(empty);
6788 %}
6789
6790
6791 instruct castPP( iRegP dst ) %{
6792 match(Set dst (CastPP dst));
6793 format %{ "# castPP of $dst" %}
6794 ins_encode( /*empty encoding*/ );
6795 ins_pipe(empty);
6796 %}
6797
6798 instruct castII( iRegI dst ) %{
6799 match(Set dst (CastII dst));
6800 format %{ "# castII of $dst" %}
6801 ins_encode( /*empty encoding*/ );
6802 ins_cost(0);
6803 ins_pipe(empty);
6804 %}
6805
6806 //----------Arithmetic Instructions--------------------------------------------
6807 // Addition Instructions
6808 // Register Addition
6809 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6810 match(Set dst (AddI src1 src2));
6811
6812 size(4);
6813 format %{ "ADD $src1,$src2,$dst" %}
6814 ins_encode %{
6815 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6816 %}
6817 ins_pipe(ialu_reg_reg);
6818 %}
6819
6820 // Immediate Addition
6821 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6822 match(Set dst (AddI src1 src2));
6823
6824 size(4);
6825 format %{ "ADD $src1,$src2,$dst" %}
6826 opcode(Assembler::add_op3, Assembler::arith_op);
6827 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6828 ins_pipe(ialu_reg_imm);
6829 %}
6830
6831 // Pointer Register Addition
6832 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6833 match(Set dst (AddP src1 src2));
6834
6835 size(4);
6836 format %{ "ADD $src1,$src2,$dst" %}
6837 opcode(Assembler::add_op3, Assembler::arith_op);
6838 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6839 ins_pipe(ialu_reg_reg);
6840 %}
6841
6842 // Pointer Immediate Addition
6843 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6844 match(Set dst (AddP src1 src2));
6845
6846 size(4);
6847 format %{ "ADD $src1,$src2,$dst" %}
6848 opcode(Assembler::add_op3, Assembler::arith_op);
6849 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6850 ins_pipe(ialu_reg_imm);
6851 %}
6852
6853 // Long Addition
6854 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6855 match(Set dst (AddL src1 src2));
6856
6857 size(4);
6858 format %{ "ADD $src1,$src2,$dst\t! long" %}
6859 opcode(Assembler::add_op3, Assembler::arith_op);
6860 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6861 ins_pipe(ialu_reg_reg);
6862 %}
6863
6864 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6865 match(Set dst (AddL src1 con));
6866
6867 size(4);
6868 format %{ "ADD $src1,$con,$dst" %}
6869 opcode(Assembler::add_op3, Assembler::arith_op);
6870 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6871 ins_pipe(ialu_reg_imm);
6872 %}
6873
6874 //----------Conditional_store--------------------------------------------------
6875 // Conditional-store of the updated heap-top.
6876 // Used during allocation of the shared heap.
6877 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6878
6879 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6880 instruct loadPLocked(iRegP dst, memory mem) %{
6881 match(Set dst (LoadPLocked mem));
6882 ins_cost(MEMORY_REF_COST);
6883
6884 format %{ "LDX $mem,$dst\t! ptr" %}
6885 opcode(Assembler::ldx_op3, 0, REGP_OP);
6886 ins_encode( form3_mem_reg( mem, dst ) );
6887 ins_pipe(iload_mem);
6888 %}
6889
6890 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6891 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6892 effect( KILL newval );
6893 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6894 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6895 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6896 ins_pipe( long_memory_op );
6897 %}
6898
6899 // Conditional-store of an int value.
6900 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6901 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6902 effect( KILL newval );
6903 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6904 "CMP $oldval,$newval\t\t! See if we made progress" %}
6905 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6906 ins_pipe( long_memory_op );
6907 %}
6908
6909 // Conditional-store of a long value.
6910 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6911 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6912 effect( KILL newval );
6913 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6914 "CMP $oldval,$newval\t\t! See if we made progress" %}
6915 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6916 ins_pipe( long_memory_op );
6917 %}
6918
6919 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6920
6921 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6922 predicate(VM_Version::supports_cx8());
6923 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6924 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
6925 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6926 format %{
6927 "MOV $newval,O7\n\t"
6928 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6929 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6930 "MOV 1,$res\n\t"
6931 "MOVne xcc,R_G0,$res"
6932 %}
6933 ins_encode( enc_casx(mem_ptr, oldval, newval),
6934 enc_lflags_ne_to_boolean(res) );
6935 ins_pipe( long_memory_op );
6936 %}
6937
6938
6939 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6940 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6941 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
6942 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6943 format %{
6944 "MOV $newval,O7\n\t"
6945 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6946 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6947 "MOV 1,$res\n\t"
6948 "MOVne icc,R_G0,$res"
6949 %}
6950 ins_encode( enc_casi(mem_ptr, oldval, newval),
6951 enc_iflags_ne_to_boolean(res) );
6952 ins_pipe( long_memory_op );
6953 %}
6954
6955 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6956 predicate(VM_Version::supports_cx8());
6957 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6958 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
6959 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6960 format %{
6961 "MOV $newval,O7\n\t"
6962 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6963 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6964 "MOV 1,$res\n\t"
6965 "MOVne xcc,R_G0,$res"
6966 %}
6967 ins_encode( enc_casx(mem_ptr, oldval, newval),
6968 enc_lflags_ne_to_boolean(res) );
6969 ins_pipe( long_memory_op );
6970 %}
6971
6972 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6973 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6974 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
6975 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6976 format %{
6977 "MOV $newval,O7\n\t"
6978 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6979 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6980 "MOV 1,$res\n\t"
6981 "MOVne icc,R_G0,$res"
6982 %}
6983 ins_encode( enc_casi(mem_ptr, oldval, newval),
6984 enc_iflags_ne_to_boolean(res) );
6985 ins_pipe( long_memory_op );
6986 %}
6987
6988 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval)
6989 %{
6990 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
6991 effect( USE mem_ptr );
6992
6993 format %{
6994 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6995 %}
6996 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
6997 ins_pipe( long_memory_op );
6998 %}
6999
7000 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval)
7001 %{
7002 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7003 effect( USE mem_ptr );
7004
7005 format %{
7006 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7007 %}
7008 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
7009 ins_pipe( long_memory_op );
7010 %}
7011
7012 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval)
7013 %{
7014 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7015 effect( USE mem_ptr );
7016
7017 format %{
7018 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7019 %}
7020 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
7021 ins_pipe( long_memory_op );
7022 %}
7023
7024 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval)
7025 %{
7026 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7027 effect( USE mem_ptr );
7028
7029 format %{
7030 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7031 %}
7032 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
7033 ins_pipe( long_memory_op );
7034 %}
7035
7036 instruct xchgI( memory mem, iRegI newval) %{
7037 match(Set newval (GetAndSetI mem newval));
7038 format %{ "SWAP [$mem],$newval" %}
7039 size(4);
7040 ins_encode %{
7041 __ swap($mem$$Address, $newval$$Register);
7042 %}
7043 ins_pipe( long_memory_op );
7044 %}
7045
7046
7047 instruct xchgN( memory mem, iRegN newval) %{
7048 match(Set newval (GetAndSetN mem newval));
7049 format %{ "SWAP [$mem],$newval" %}
7050 size(4);
7051 ins_encode %{
7052 __ swap($mem$$Address, $newval$$Register);
7053 %}
7054 ins_pipe( long_memory_op );
7055 %}
7056
7057 //---------------------
7058 // Subtraction Instructions
7059 // Register Subtraction
7060 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7061 match(Set dst (SubI src1 src2));
7062
7063 size(4);
7064 format %{ "SUB $src1,$src2,$dst" %}
7065 opcode(Assembler::sub_op3, Assembler::arith_op);
7066 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7067 ins_pipe(ialu_reg_reg);
7068 %}
7069
7070 // Immediate Subtraction
7071 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7072 match(Set dst (SubI src1 src2));
7073
7074 size(4);
7075 format %{ "SUB $src1,$src2,$dst" %}
7076 opcode(Assembler::sub_op3, Assembler::arith_op);
7077 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7078 ins_pipe(ialu_reg_imm);
7079 %}
7080
7081 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7082 match(Set dst (SubI zero src2));
7083
7084 size(4);
7085 format %{ "NEG $src2,$dst" %}
7086 opcode(Assembler::sub_op3, Assembler::arith_op);
7087 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7088 ins_pipe(ialu_zero_reg);
7089 %}
7090
7091 // Long subtraction
7092 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7093 match(Set dst (SubL src1 src2));
7094
7095 size(4);
7096 format %{ "SUB $src1,$src2,$dst\t! long" %}
7097 opcode(Assembler::sub_op3, Assembler::arith_op);
7098 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7099 ins_pipe(ialu_reg_reg);
7100 %}
7101
7102 // Immediate Subtraction
7103 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7104 match(Set dst (SubL src1 con));
7105
7106 size(4);
7107 format %{ "SUB $src1,$con,$dst\t! long" %}
7108 opcode(Assembler::sub_op3, Assembler::arith_op);
7109 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7110 ins_pipe(ialu_reg_imm);
7111 %}
7112
7113 // Long negation
7114 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7115 match(Set dst (SubL zero src2));
7116
7117 size(4);
7118 format %{ "NEG $src2,$dst\t! long" %}
7119 opcode(Assembler::sub_op3, Assembler::arith_op);
7120 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7121 ins_pipe(ialu_zero_reg);
7122 %}
7123
7124 // Multiplication Instructions
7125 // Integer Multiplication
7126 // Register Multiplication
7127 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7128 match(Set dst (MulI src1 src2));
7129
7130 size(4);
7131 format %{ "MULX $src1,$src2,$dst" %}
7132 opcode(Assembler::mulx_op3, Assembler::arith_op);
7133 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7134 ins_pipe(imul_reg_reg);
7135 %}
7136
7137 // Immediate Multiplication
7138 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7139 match(Set dst (MulI src1 src2));
7140
7141 size(4);
7142 format %{ "MULX $src1,$src2,$dst" %}
7143 opcode(Assembler::mulx_op3, Assembler::arith_op);
7144 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7145 ins_pipe(imul_reg_imm);
7146 %}
7147
7148 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7149 match(Set dst (MulL src1 src2));
7150 ins_cost(DEFAULT_COST * 5);
7151 size(4);
7152 format %{ "MULX $src1,$src2,$dst\t! long" %}
7153 opcode(Assembler::mulx_op3, Assembler::arith_op);
7154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7155 ins_pipe(mulL_reg_reg);
7156 %}
7157
7158 // Immediate Multiplication
7159 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7160 match(Set dst (MulL src1 src2));
7161 ins_cost(DEFAULT_COST * 5);
7162 size(4);
7163 format %{ "MULX $src1,$src2,$dst" %}
7164 opcode(Assembler::mulx_op3, Assembler::arith_op);
7165 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7166 ins_pipe(mulL_reg_imm);
7167 %}
7168
7169 // Integer Division
7170 // Register Division
7171 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7172 match(Set dst (DivI src1 src2));
7173 ins_cost((2+71)*DEFAULT_COST);
7174
7175 format %{ "SRA $src2,0,$src2\n\t"
7176 "SRA $src1,0,$src1\n\t"
7177 "SDIVX $src1,$src2,$dst" %}
7178 ins_encode( idiv_reg( src1, src2, dst ) );
7179 ins_pipe(sdiv_reg_reg);
7180 %}
7181
7182 // Immediate Division
7183 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7184 match(Set dst (DivI src1 src2));
7185 ins_cost((2+71)*DEFAULT_COST);
7186
7187 format %{ "SRA $src1,0,$src1\n\t"
7188 "SDIVX $src1,$src2,$dst" %}
7189 ins_encode( idiv_imm( src1, src2, dst ) );
7190 ins_pipe(sdiv_reg_imm);
7191 %}
7192
7193 //----------Div-By-10-Expansion------------------------------------------------
7194 // Extract hi bits of a 32x32->64 bit multiply.
7195 // Expand rule only, not matched
7196 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7197 effect( DEF dst, USE src1, USE src2 );
7198 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7199 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7200 ins_encode( enc_mul_hi(dst,src1,src2));
7201 ins_pipe(sdiv_reg_reg);
7202 %}
7203
7204 // Magic constant, reciprocal of 10
7205 instruct loadConI_x66666667(iRegIsafe dst) %{
7206 effect( DEF dst );
7207
7208 size(8);
7209 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7210 ins_encode( Set32(0x66666667, dst) );
7211 ins_pipe(ialu_hi_lo_reg);
7212 %}
7213
7214 // Register Shift Right Arithmetic Long by 32-63
7215 instruct sra_31( iRegI dst, iRegI src ) %{
7216 effect( DEF dst, USE src );
7217 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7218 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7219 ins_pipe(ialu_reg_reg);
7220 %}
7221
7222 // Arithmetic Shift Right by 8-bit immediate
7223 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7224 effect( DEF dst, USE src );
7225 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7226 opcode(Assembler::sra_op3, Assembler::arith_op);
7227 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7228 ins_pipe(ialu_reg_imm);
7229 %}
7230
7231 // Integer DIV with 10
7232 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7233 match(Set dst (DivI src div));
7234 ins_cost((6+6)*DEFAULT_COST);
7235 expand %{
7236 iRegIsafe tmp1; // Killed temps;
7237 iRegIsafe tmp2; // Killed temps;
7238 iRegI tmp3; // Killed temps;
7239 iRegI tmp4; // Killed temps;
7240 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7241 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7242 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7243 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7244 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7245 %}
7246 %}
7247
7248 // Register Long Division
7249 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7250 match(Set dst (DivL src1 src2));
7251 ins_cost(DEFAULT_COST*71);
7252 size(4);
7253 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7254 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7255 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7256 ins_pipe(divL_reg_reg);
7257 %}
7258
7259 // Register Long Division
7260 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7261 match(Set dst (DivL src1 src2));
7262 ins_cost(DEFAULT_COST*71);
7263 size(4);
7264 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7265 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7266 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7267 ins_pipe(divL_reg_imm);
7268 %}
7269
7270 // Integer Remainder
7271 // Register Remainder
7272 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7273 match(Set dst (ModI src1 src2));
7274 effect( KILL ccr, KILL temp);
7275
7276 format %{ "SREM $src1,$src2,$dst" %}
7277 ins_encode( irem_reg(src1, src2, dst, temp) );
7278 ins_pipe(sdiv_reg_reg);
7279 %}
7280
7281 // Immediate Remainder
7282 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7283 match(Set dst (ModI src1 src2));
7284 effect( KILL ccr, KILL temp);
7285
7286 format %{ "SREM $src1,$src2,$dst" %}
7287 ins_encode( irem_imm(src1, src2, dst, temp) );
7288 ins_pipe(sdiv_reg_imm);
7289 %}
7290
7291 // Register Long Remainder
7292 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7293 effect(DEF dst, USE src1, USE src2);
7294 size(4);
7295 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7296 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7297 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7298 ins_pipe(divL_reg_reg);
7299 %}
7300
7301 // Register Long Division
7302 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7303 effect(DEF dst, USE src1, USE src2);
7304 size(4);
7305 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7306 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7307 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7308 ins_pipe(divL_reg_imm);
7309 %}
7310
7311 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7312 effect(DEF dst, USE src1, USE src2);
7313 size(4);
7314 format %{ "MULX $src1,$src2,$dst\t! long" %}
7315 opcode(Assembler::mulx_op3, Assembler::arith_op);
7316 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7317 ins_pipe(mulL_reg_reg);
7318 %}
7319
7320 // Immediate Multiplication
7321 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7322 effect(DEF dst, USE src1, USE src2);
7323 size(4);
7324 format %{ "MULX $src1,$src2,$dst" %}
7325 opcode(Assembler::mulx_op3, Assembler::arith_op);
7326 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7327 ins_pipe(mulL_reg_imm);
7328 %}
7329
7330 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7331 effect(DEF dst, USE src1, USE src2);
7332 size(4);
7333 format %{ "SUB $src1,$src2,$dst\t! long" %}
7334 opcode(Assembler::sub_op3, Assembler::arith_op);
7335 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7336 ins_pipe(ialu_reg_reg);
7337 %}
7338
7339 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7340 effect(DEF dst, USE src1, USE src2);
7341 size(4);
7342 format %{ "SUB $src1,$src2,$dst\t! long" %}
7343 opcode(Assembler::sub_op3, Assembler::arith_op);
7344 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7345 ins_pipe(ialu_reg_reg);
7346 %}
7347
7348 // Register Long Remainder
7349 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7350 match(Set dst (ModL src1 src2));
7351 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7352 expand %{
7353 iRegL tmp1;
7354 iRegL tmp2;
7355 divL_reg_reg_1(tmp1, src1, src2);
7356 mulL_reg_reg_1(tmp2, tmp1, src2);
7357 subL_reg_reg_1(dst, src1, tmp2);
7358 %}
7359 %}
7360
7361 // Register Long Remainder
7362 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7363 match(Set dst (ModL src1 src2));
7364 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7365 expand %{
7366 iRegL tmp1;
7367 iRegL tmp2;
7368 divL_reg_imm13_1(tmp1, src1, src2);
7369 mulL_reg_imm13_1(tmp2, tmp1, src2);
7370 subL_reg_reg_2 (dst, src1, tmp2);
7371 %}
7372 %}
7373
7374 // Integer Shift Instructions
7375 // Register Shift Left
7376 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7377 match(Set dst (LShiftI src1 src2));
7378
7379 size(4);
7380 format %{ "SLL $src1,$src2,$dst" %}
7381 opcode(Assembler::sll_op3, Assembler::arith_op);
7382 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7383 ins_pipe(ialu_reg_reg);
7384 %}
7385
7386 // Register Shift Left Immediate
7387 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7388 match(Set dst (LShiftI src1 src2));
7389
7390 size(4);
7391 format %{ "SLL $src1,$src2,$dst" %}
7392 opcode(Assembler::sll_op3, Assembler::arith_op);
7393 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7394 ins_pipe(ialu_reg_imm);
7395 %}
7396
7397 // Register Shift Left
7398 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7399 match(Set dst (LShiftL src1 src2));
7400
7401 size(4);
7402 format %{ "SLLX $src1,$src2,$dst" %}
7403 opcode(Assembler::sllx_op3, Assembler::arith_op);
7404 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7405 ins_pipe(ialu_reg_reg);
7406 %}
7407
7408 // Register Shift Left Immediate
7409 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7410 match(Set dst (LShiftL src1 src2));
7411
7412 size(4);
7413 format %{ "SLLX $src1,$src2,$dst" %}
7414 opcode(Assembler::sllx_op3, Assembler::arith_op);
7415 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7416 ins_pipe(ialu_reg_imm);
7417 %}
7418
7419 // Register Arithmetic Shift Right
7420 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7421 match(Set dst (RShiftI src1 src2));
7422 size(4);
7423 format %{ "SRA $src1,$src2,$dst" %}
7424 opcode(Assembler::sra_op3, Assembler::arith_op);
7425 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7426 ins_pipe(ialu_reg_reg);
7427 %}
7428
7429 // Register Arithmetic Shift Right Immediate
7430 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7431 match(Set dst (RShiftI src1 src2));
7432
7433 size(4);
7434 format %{ "SRA $src1,$src2,$dst" %}
7435 opcode(Assembler::sra_op3, Assembler::arith_op);
7436 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7437 ins_pipe(ialu_reg_imm);
7438 %}
7439
7440 // Register Shift Right Arithmatic Long
7441 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7442 match(Set dst (RShiftL src1 src2));
7443
7444 size(4);
7445 format %{ "SRAX $src1,$src2,$dst" %}
7446 opcode(Assembler::srax_op3, Assembler::arith_op);
7447 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7448 ins_pipe(ialu_reg_reg);
7449 %}
7450
7451 // Register Shift Left Immediate
7452 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7453 match(Set dst (RShiftL src1 src2));
7454
7455 size(4);
7456 format %{ "SRAX $src1,$src2,$dst" %}
7457 opcode(Assembler::srax_op3, Assembler::arith_op);
7458 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7459 ins_pipe(ialu_reg_imm);
7460 %}
7461
7462 // Register Shift Right
7463 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7464 match(Set dst (URShiftI src1 src2));
7465
7466 size(4);
7467 format %{ "SRL $src1,$src2,$dst" %}
7468 opcode(Assembler::srl_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7470 ins_pipe(ialu_reg_reg);
7471 %}
7472
7473 // Register Shift Right Immediate
7474 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7475 match(Set dst (URShiftI src1 src2));
7476
7477 size(4);
7478 format %{ "SRL $src1,$src2,$dst" %}
7479 opcode(Assembler::srl_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7481 ins_pipe(ialu_reg_imm);
7482 %}
7483
7484 // Register Shift Right
7485 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7486 match(Set dst (URShiftL src1 src2));
7487
7488 size(4);
7489 format %{ "SRLX $src1,$src2,$dst" %}
7490 opcode(Assembler::srlx_op3, Assembler::arith_op);
7491 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7492 ins_pipe(ialu_reg_reg);
7493 %}
7494
7495 // Register Shift Right Immediate
7496 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7497 match(Set dst (URShiftL src1 src2));
7498
7499 size(4);
7500 format %{ "SRLX $src1,$src2,$dst" %}
7501 opcode(Assembler::srlx_op3, Assembler::arith_op);
7502 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7503 ins_pipe(ialu_reg_imm);
7504 %}
7505
7506 // Register Shift Right Immediate with a CastP2X
7507 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7508 match(Set dst (URShiftL (CastP2X src1) src2));
7509 size(4);
7510 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7511 opcode(Assembler::srlx_op3, Assembler::arith_op);
7512 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7513 ins_pipe(ialu_reg_imm);
7514 %}
7515
7516
7517 //----------Floating Point Arithmetic Instructions-----------------------------
7518
7519 // Add float single precision
7520 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7521 match(Set dst (AddF src1 src2));
7522
7523 size(4);
7524 format %{ "FADDS $src1,$src2,$dst" %}
7525 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7526 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7527 ins_pipe(faddF_reg_reg);
7528 %}
7529
7530 // Add float double precision
7531 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7532 match(Set dst (AddD src1 src2));
7533
7534 size(4);
7535 format %{ "FADDD $src1,$src2,$dst" %}
7536 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7537 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7538 ins_pipe(faddD_reg_reg);
7539 %}
7540
7541 // Sub float single precision
7542 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7543 match(Set dst (SubF src1 src2));
7544
7545 size(4);
7546 format %{ "FSUBS $src1,$src2,$dst" %}
7547 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7548 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7549 ins_pipe(faddF_reg_reg);
7550 %}
7551
7552 // Sub float double precision
7553 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7554 match(Set dst (SubD src1 src2));
7555
7556 size(4);
7557 format %{ "FSUBD $src1,$src2,$dst" %}
7558 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7559 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7560 ins_pipe(faddD_reg_reg);
7561 %}
7562
7563 // Mul float single precision
7564 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7565 match(Set dst (MulF src1 src2));
7566
7567 size(4);
7568 format %{ "FMULS $src1,$src2,$dst" %}
7569 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7570 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7571 ins_pipe(fmulF_reg_reg);
7572 %}
7573
7574 // Mul float double precision
7575 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7576 match(Set dst (MulD src1 src2));
7577
7578 size(4);
7579 format %{ "FMULD $src1,$src2,$dst" %}
7580 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7581 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7582 ins_pipe(fmulD_reg_reg);
7583 %}
7584
7585 // Div float single precision
7586 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7587 match(Set dst (DivF src1 src2));
7588
7589 size(4);
7590 format %{ "FDIVS $src1,$src2,$dst" %}
7591 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7592 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7593 ins_pipe(fdivF_reg_reg);
7594 %}
7595
7596 // Div float double precision
7597 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7598 match(Set dst (DivD src1 src2));
7599
7600 size(4);
7601 format %{ "FDIVD $src1,$src2,$dst" %}
7602 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7603 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7604 ins_pipe(fdivD_reg_reg);
7605 %}
7606
7607 // Absolute float double precision
7608 instruct absD_reg(regD dst, regD src) %{
7609 match(Set dst (AbsD src));
7610
7611 format %{ "FABSd $src,$dst" %}
7612 ins_encode(fabsd(dst, src));
7613 ins_pipe(faddD_reg);
7614 %}
7615
7616 // Absolute float single precision
7617 instruct absF_reg(regF dst, regF src) %{
7618 match(Set dst (AbsF src));
7619
7620 format %{ "FABSs $src,$dst" %}
7621 ins_encode(fabss(dst, src));
7622 ins_pipe(faddF_reg);
7623 %}
7624
7625 instruct negF_reg(regF dst, regF src) %{
7626 match(Set dst (NegF src));
7627
7628 size(4);
7629 format %{ "FNEGs $src,$dst" %}
7630 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7631 ins_encode(form3_opf_rs2F_rdF(src, dst));
7632 ins_pipe(faddF_reg);
7633 %}
7634
7635 instruct negD_reg(regD dst, regD src) %{
7636 match(Set dst (NegD src));
7637
7638 format %{ "FNEGd $src,$dst" %}
7639 ins_encode(fnegd(dst, src));
7640 ins_pipe(faddD_reg);
7641 %}
7642
7643 // Sqrt float double precision
7644 instruct sqrtF_reg_reg(regF dst, regF src) %{
7645 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7646
7647 size(4);
7648 format %{ "FSQRTS $src,$dst" %}
7649 ins_encode(fsqrts(dst, src));
7650 ins_pipe(fdivF_reg_reg);
7651 %}
7652
7653 // Sqrt float double precision
7654 instruct sqrtD_reg_reg(regD dst, regD src) %{
7655 match(Set dst (SqrtD src));
7656
7657 size(4);
7658 format %{ "FSQRTD $src,$dst" %}
7659 ins_encode(fsqrtd(dst, src));
7660 ins_pipe(fdivD_reg_reg);
7661 %}
7662
7663 // Single/Double precision fused floating-point multiply-add (d = a * b + c).
7664 instruct fmaF_regx4(regF dst, regF a, regF b, regF c) %{
7665 predicate(UseFMA);
7666 match(Set dst (FmaF c (Binary a b)));
7667 format %{ "fmadds $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7668 ins_encode(fmadds(dst, a, b, c));
7669 ins_pipe(fmaF_regx4);
7670 %}
7671
7672 instruct fmaD_regx4(regD dst, regD a, regD b, regD c) %{
7673 predicate(UseFMA);
7674 match(Set dst (FmaD c (Binary a b)));
7675 format %{ "fmaddd $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7676 ins_encode(fmaddd(dst, a, b, c));
7677 ins_pipe(fmaD_regx4);
7678 %}
7679
7680 // Additional patterns matching complement versions that we can map directly to
7681 // variants of the fused multiply-add instructions.
7682
7683 // Single/Double precision fused floating-point multiply-sub (d = a * b - c)
7684 instruct fmsubF_regx4(regF dst, regF a, regF b, regF c) %{
7685 predicate(UseFMA);
7686 match(Set dst (FmaF (NegF c) (Binary a b)));
7687 format %{ "fmsubs $a,$b,$c,$dst\t# $dst = $a * $b - $c" %}
7688 ins_encode(fmsubs(dst, a, b, c));
7689 ins_pipe(fmaF_regx4);
7690 %}
7691
7692 instruct fmsubD_regx4(regD dst, regD a, regD b, regD c) %{
7693 predicate(UseFMA);
7694 match(Set dst (FmaD (NegD c) (Binary a b)));
7695 format %{ "fmsubd $a,$b,$c,$dst\t# $dst = $a * $b - $c" %}
7696 ins_encode(fmsubd(dst, a, b, c));
7697 ins_pipe(fmaD_regx4);
7698 %}
7699
7700 // Single/Double precision fused floating-point neg. multiply-add,
7701 // d = -1 * a * b - c = -(a * b + c)
7702 instruct fnmaddF_regx4(regF dst, regF a, regF b, regF c) %{
7703 predicate(UseFMA);
7704 match(Set dst (FmaF (NegF c) (Binary (NegF a) b)));
7705 match(Set dst (FmaF (NegF c) (Binary a (NegF b))));
7706 format %{ "fnmadds $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %}
7707 ins_encode(fnmadds(dst, a, b, c));
7708 ins_pipe(fmaF_regx4);
7709 %}
7710
7711 instruct fnmaddD_regx4(regD dst, regD a, regD b, regD c) %{
7712 predicate(UseFMA);
7713 match(Set dst (FmaD (NegD c) (Binary (NegD a) b)));
7714 match(Set dst (FmaD (NegD c) (Binary a (NegD b))));
7715 format %{ "fnmaddd $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %}
7716 ins_encode(fnmaddd(dst, a, b, c));
7717 ins_pipe(fmaD_regx4);
7718 %}
7719
7720 // Single/Double precision fused floating-point neg. multiply-sub,
7721 // d = -1 * a * b + c = -(a * b - c)
7722 instruct fnmsubF_regx4(regF dst, regF a, regF b, regF c) %{
7723 predicate(UseFMA);
7724 match(Set dst (FmaF c (Binary (NegF a) b)));
7725 match(Set dst (FmaF c (Binary a (NegF b))));
7726 format %{ "fnmsubs $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %}
7727 ins_encode(fnmsubs(dst, a, b, c));
7728 ins_pipe(fmaF_regx4);
7729 %}
7730
7731 instruct fnmsubD_regx4(regD dst, regD a, regD b, regD c) %{
7732 predicate(UseFMA);
7733 match(Set dst (FmaD c (Binary (NegD a) b)));
7734 match(Set dst (FmaD c (Binary a (NegD b))));
7735 format %{ "fnmsubd $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %}
7736 ins_encode(fnmsubd(dst, a, b, c));
7737 ins_pipe(fmaD_regx4);
7738 %}
7739
7740 //----------Logical Instructions-----------------------------------------------
7741 // And Instructions
7742 // Register And
7743 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7744 match(Set dst (AndI src1 src2));
7745
7746 size(4);
7747 format %{ "AND $src1,$src2,$dst" %}
7748 opcode(Assembler::and_op3, Assembler::arith_op);
7749 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7750 ins_pipe(ialu_reg_reg);
7751 %}
7752
7753 // Immediate And
7754 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7755 match(Set dst (AndI src1 src2));
7756
7757 size(4);
7758 format %{ "AND $src1,$src2,$dst" %}
7759 opcode(Assembler::and_op3, Assembler::arith_op);
7760 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7761 ins_pipe(ialu_reg_imm);
7762 %}
7763
7764 // Register And Long
7765 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7766 match(Set dst (AndL src1 src2));
7767
7768 ins_cost(DEFAULT_COST);
7769 size(4);
7770 format %{ "AND $src1,$src2,$dst\t! long" %}
7771 opcode(Assembler::and_op3, Assembler::arith_op);
7772 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7773 ins_pipe(ialu_reg_reg);
7774 %}
7775
7776 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7777 match(Set dst (AndL src1 con));
7778
7779 ins_cost(DEFAULT_COST);
7780 size(4);
7781 format %{ "AND $src1,$con,$dst\t! long" %}
7782 opcode(Assembler::and_op3, Assembler::arith_op);
7783 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7784 ins_pipe(ialu_reg_imm);
7785 %}
7786
7787 // Or Instructions
7788 // Register Or
7789 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7790 match(Set dst (OrI src1 src2));
7791
7792 size(4);
7793 format %{ "OR $src1,$src2,$dst" %}
7794 opcode(Assembler::or_op3, Assembler::arith_op);
7795 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7796 ins_pipe(ialu_reg_reg);
7797 %}
7798
7799 // Immediate Or
7800 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7801 match(Set dst (OrI src1 src2));
7802
7803 size(4);
7804 format %{ "OR $src1,$src2,$dst" %}
7805 opcode(Assembler::or_op3, Assembler::arith_op);
7806 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7807 ins_pipe(ialu_reg_imm);
7808 %}
7809
7810 // Register Or Long
7811 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7812 match(Set dst (OrL src1 src2));
7813
7814 ins_cost(DEFAULT_COST);
7815 size(4);
7816 format %{ "OR $src1,$src2,$dst\t! long" %}
7817 opcode(Assembler::or_op3, Assembler::arith_op);
7818 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7819 ins_pipe(ialu_reg_reg);
7820 %}
7821
7822 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7823 match(Set dst (OrL src1 con));
7824 ins_cost(DEFAULT_COST*2);
7825
7826 ins_cost(DEFAULT_COST);
7827 size(4);
7828 format %{ "OR $src1,$con,$dst\t! long" %}
7829 opcode(Assembler::or_op3, Assembler::arith_op);
7830 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7831 ins_pipe(ialu_reg_imm);
7832 %}
7833
7834 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7835 match(Set dst (OrL src1 (CastP2X src2)));
7836
7837 ins_cost(DEFAULT_COST);
7838 size(4);
7839 format %{ "OR $src1,$src2,$dst\t! long" %}
7840 opcode(Assembler::or_op3, Assembler::arith_op);
7841 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7842 ins_pipe(ialu_reg_reg);
7843 %}
7844
7845 // Xor Instructions
7846 // Register Xor
7847 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7848 match(Set dst (XorI src1 src2));
7849
7850 size(4);
7851 format %{ "XOR $src1,$src2,$dst" %}
7852 opcode(Assembler::xor_op3, Assembler::arith_op);
7853 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7854 ins_pipe(ialu_reg_reg);
7855 %}
7856
7857 // Immediate Xor
7858 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7859 match(Set dst (XorI src1 src2));
7860
7861 size(4);
7862 format %{ "XOR $src1,$src2,$dst" %}
7863 opcode(Assembler::xor_op3, Assembler::arith_op);
7864 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7865 ins_pipe(ialu_reg_imm);
7866 %}
7867
7868 // Register Xor Long
7869 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7870 match(Set dst (XorL src1 src2));
7871
7872 ins_cost(DEFAULT_COST);
7873 size(4);
7874 format %{ "XOR $src1,$src2,$dst\t! long" %}
7875 opcode(Assembler::xor_op3, Assembler::arith_op);
7876 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7877 ins_pipe(ialu_reg_reg);
7878 %}
7879
7880 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7881 match(Set dst (XorL src1 con));
7882
7883 ins_cost(DEFAULT_COST);
7884 size(4);
7885 format %{ "XOR $src1,$con,$dst\t! long" %}
7886 opcode(Assembler::xor_op3, Assembler::arith_op);
7887 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7888 ins_pipe(ialu_reg_imm);
7889 %}
7890
7891 //----------Convert to Boolean-------------------------------------------------
7892 // Nice hack for 32-bit tests but doesn't work for
7893 // 64-bit pointers.
7894 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7895 match(Set dst (Conv2B src));
7896 effect( KILL ccr );
7897 ins_cost(DEFAULT_COST*2);
7898 format %{ "CMP R_G0,$src\n\t"
7899 "ADDX R_G0,0,$dst" %}
7900 ins_encode( enc_to_bool( src, dst ) );
7901 ins_pipe(ialu_reg_ialu);
7902 %}
7903
7904 instruct convP2B( iRegI dst, iRegP src ) %{
7905 match(Set dst (Conv2B src));
7906 ins_cost(DEFAULT_COST*2);
7907 format %{ "MOV $src,$dst\n\t"
7908 "MOVRNZ $src,1,$dst" %}
7909 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7910 ins_pipe(ialu_clr_and_mover);
7911 %}
7912
7913 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
7914 match(Set dst (CmpLTMask src zero));
7915 effect(KILL ccr);
7916 size(4);
7917 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
7918 ins_encode %{
7919 __ sra($src$$Register, 31, $dst$$Register);
7920 %}
7921 ins_pipe(ialu_reg_imm);
7922 %}
7923
7924 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7925 match(Set dst (CmpLTMask p q));
7926 effect( KILL ccr );
7927 ins_cost(DEFAULT_COST*4);
7928 format %{ "CMP $p,$q\n\t"
7929 "MOV #0,$dst\n\t"
7930 "BLT,a .+8\n\t"
7931 "MOV #-1,$dst" %}
7932 ins_encode( enc_ltmask(p,q,dst) );
7933 ins_pipe(ialu_reg_reg_ialu);
7934 %}
7935
7936 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7937 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7938 effect(KILL ccr, TEMP tmp);
7939 ins_cost(DEFAULT_COST*3);
7940
7941 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7942 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7943 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7944 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
7945 ins_pipe(cadd_cmpltmask);
7946 %}
7947
7948 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
7949 match(Set p (AndI (CmpLTMask p q) y));
7950 effect(KILL ccr);
7951 ins_cost(DEFAULT_COST*3);
7952
7953 format %{ "CMP $p,$q\n\t"
7954 "MOV $y,$p\n\t"
7955 "MOVge G0,$p" %}
7956 ins_encode %{
7957 __ cmp($p$$Register, $q$$Register);
7958 __ mov($y$$Register, $p$$Register);
7959 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
7960 %}
7961 ins_pipe(ialu_reg_reg_ialu);
7962 %}
7963
7964 //-----------------------------------------------------------------
7965 // Direct raw moves between float and general registers using VIS3.
7966
7967 // ins_pipe(faddF_reg);
7968 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
7969 predicate(UseVIS >= 3);
7970 match(Set dst (MoveF2I src));
7971
7972 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
7973 ins_encode %{
7974 __ movstouw($src$$FloatRegister, $dst$$Register);
7975 %}
7976 ins_pipe(ialu_reg_reg);
7977 %}
7978
7979 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
7980 predicate(UseVIS >= 3);
7981 match(Set dst (MoveI2F src));
7982
7983 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
7984 ins_encode %{
7985 __ movwtos($src$$Register, $dst$$FloatRegister);
7986 %}
7987 ins_pipe(ialu_reg_reg);
7988 %}
7989
7990 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
7991 predicate(UseVIS >= 3);
7992 match(Set dst (MoveD2L src));
7993
7994 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
7995 ins_encode %{
7996 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
7997 %}
7998 ins_pipe(ialu_reg_reg);
7999 %}
8000
8001 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8002 predicate(UseVIS >= 3);
8003 match(Set dst (MoveL2D src));
8004
8005 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8006 ins_encode %{
8007 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8008 %}
8009 ins_pipe(ialu_reg_reg);
8010 %}
8011
8012
8013 // Raw moves between float and general registers using stack.
8014
8015 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8016 match(Set dst (MoveF2I src));
8017 effect(DEF dst, USE src);
8018 ins_cost(MEMORY_REF_COST);
8019
8020 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8021 opcode(Assembler::lduw_op3);
8022 ins_encode(simple_form3_mem_reg( src, dst ) );
8023 ins_pipe(iload_mem);
8024 %}
8025
8026 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8027 match(Set dst (MoveI2F src));
8028 effect(DEF dst, USE src);
8029 ins_cost(MEMORY_REF_COST);
8030
8031 format %{ "LDF $src,$dst\t! MoveI2F" %}
8032 opcode(Assembler::ldf_op3);
8033 ins_encode(simple_form3_mem_reg(src, dst));
8034 ins_pipe(floadF_stk);
8035 %}
8036
8037 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8038 match(Set dst (MoveD2L src));
8039 effect(DEF dst, USE src);
8040 ins_cost(MEMORY_REF_COST);
8041
8042 format %{ "LDX $src,$dst\t! MoveD2L" %}
8043 opcode(Assembler::ldx_op3);
8044 ins_encode(simple_form3_mem_reg( src, dst ) );
8045 ins_pipe(iload_mem);
8046 %}
8047
8048 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8049 match(Set dst (MoveL2D src));
8050 effect(DEF dst, USE src);
8051 ins_cost(MEMORY_REF_COST);
8052
8053 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8054 opcode(Assembler::lddf_op3);
8055 ins_encode(simple_form3_mem_reg(src, dst));
8056 ins_pipe(floadD_stk);
8057 %}
8058
8059 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8060 match(Set dst (MoveF2I src));
8061 effect(DEF dst, USE src);
8062 ins_cost(MEMORY_REF_COST);
8063
8064 format %{ "STF $src,$dst\t! MoveF2I" %}
8065 opcode(Assembler::stf_op3);
8066 ins_encode(simple_form3_mem_reg(dst, src));
8067 ins_pipe(fstoreF_stk_reg);
8068 %}
8069
8070 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8071 match(Set dst (MoveI2F src));
8072 effect(DEF dst, USE src);
8073 ins_cost(MEMORY_REF_COST);
8074
8075 format %{ "STW $src,$dst\t! MoveI2F" %}
8076 opcode(Assembler::stw_op3);
8077 ins_encode(simple_form3_mem_reg( dst, src ) );
8078 ins_pipe(istore_mem_reg);
8079 %}
8080
8081 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8082 match(Set dst (MoveD2L src));
8083 effect(DEF dst, USE src);
8084 ins_cost(MEMORY_REF_COST);
8085
8086 format %{ "STDF $src,$dst\t! MoveD2L" %}
8087 opcode(Assembler::stdf_op3);
8088 ins_encode(simple_form3_mem_reg(dst, src));
8089 ins_pipe(fstoreD_stk_reg);
8090 %}
8091
8092 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8093 match(Set dst (MoveL2D src));
8094 effect(DEF dst, USE src);
8095 ins_cost(MEMORY_REF_COST);
8096
8097 format %{ "STX $src,$dst\t! MoveL2D" %}
8098 opcode(Assembler::stx_op3);
8099 ins_encode(simple_form3_mem_reg( dst, src ) );
8100 ins_pipe(istore_mem_reg);
8101 %}
8102
8103
8104 //----------Arithmetic Conversion Instructions---------------------------------
8105 // The conversions operations are all Alpha sorted. Please keep it that way!
8106
8107 instruct convD2F_reg(regF dst, regD src) %{
8108 match(Set dst (ConvD2F src));
8109 size(4);
8110 format %{ "FDTOS $src,$dst" %}
8111 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8112 ins_encode(form3_opf_rs2D_rdF(src, dst));
8113 ins_pipe(fcvtD2F);
8114 %}
8115
8116
8117 // Convert a double to an int in a float register.
8118 // If the double is a NAN, stuff a zero in instead.
8119 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8120 effect(DEF dst, USE src, KILL fcc0);
8121 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8122 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8123 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8124 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8125 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8126 "skip:" %}
8127 ins_encode(form_d2i_helper(src,dst));
8128 ins_pipe(fcvtD2I);
8129 %}
8130
8131 instruct convD2I_stk(stackSlotI dst, regD src) %{
8132 match(Set dst (ConvD2I src));
8133 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8134 expand %{
8135 regF tmp;
8136 convD2I_helper(tmp, src);
8137 regF_to_stkI(dst, tmp);
8138 %}
8139 %}
8140
8141 instruct convD2I_reg(iRegI dst, regD src) %{
8142 predicate(UseVIS >= 3);
8143 match(Set dst (ConvD2I src));
8144 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8145 expand %{
8146 regF tmp;
8147 convD2I_helper(tmp, src);
8148 MoveF2I_reg_reg(dst, tmp);
8149 %}
8150 %}
8151
8152
8153 // Convert a double to a long in a double register.
8154 // If the double is a NAN, stuff a zero in instead.
8155 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8156 effect(DEF dst, USE src, KILL fcc0);
8157 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8158 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8159 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8160 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8161 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8162 "skip:" %}
8163 ins_encode(form_d2l_helper(src,dst));
8164 ins_pipe(fcvtD2L);
8165 %}
8166
8167 instruct convD2L_stk(stackSlotL dst, regD src) %{
8168 match(Set dst (ConvD2L src));
8169 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8170 expand %{
8171 regD tmp;
8172 convD2L_helper(tmp, src);
8173 regD_to_stkL(dst, tmp);
8174 %}
8175 %}
8176
8177 instruct convD2L_reg(iRegL dst, regD src) %{
8178 predicate(UseVIS >= 3);
8179 match(Set dst (ConvD2L src));
8180 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8181 expand %{
8182 regD tmp;
8183 convD2L_helper(tmp, src);
8184 MoveD2L_reg_reg(dst, tmp);
8185 %}
8186 %}
8187
8188
8189 instruct convF2D_reg(regD dst, regF src) %{
8190 match(Set dst (ConvF2D src));
8191 format %{ "FSTOD $src,$dst" %}
8192 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8193 ins_encode(form3_opf_rs2F_rdD(src, dst));
8194 ins_pipe(fcvtF2D);
8195 %}
8196
8197
8198 // Convert a float to an int in a float register.
8199 // If the float is a NAN, stuff a zero in instead.
8200 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8201 effect(DEF dst, USE src, KILL fcc0);
8202 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8203 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8204 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8205 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8206 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8207 "skip:" %}
8208 ins_encode(form_f2i_helper(src,dst));
8209 ins_pipe(fcvtF2I);
8210 %}
8211
8212 instruct convF2I_stk(stackSlotI dst, regF src) %{
8213 match(Set dst (ConvF2I src));
8214 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8215 expand %{
8216 regF tmp;
8217 convF2I_helper(tmp, src);
8218 regF_to_stkI(dst, tmp);
8219 %}
8220 %}
8221
8222 instruct convF2I_reg(iRegI dst, regF src) %{
8223 predicate(UseVIS >= 3);
8224 match(Set dst (ConvF2I src));
8225 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8226 expand %{
8227 regF tmp;
8228 convF2I_helper(tmp, src);
8229 MoveF2I_reg_reg(dst, tmp);
8230 %}
8231 %}
8232
8233
8234 // Convert a float to a long in a float register.
8235 // If the float is a NAN, stuff a zero in instead.
8236 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8237 effect(DEF dst, USE src, KILL fcc0);
8238 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8239 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8240 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8241 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8242 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8243 "skip:" %}
8244 ins_encode(form_f2l_helper(src,dst));
8245 ins_pipe(fcvtF2L);
8246 %}
8247
8248 instruct convF2L_stk(stackSlotL dst, regF src) %{
8249 match(Set dst (ConvF2L src));
8250 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8251 expand %{
8252 regD tmp;
8253 convF2L_helper(tmp, src);
8254 regD_to_stkL(dst, tmp);
8255 %}
8256 %}
8257
8258 instruct convF2L_reg(iRegL dst, regF src) %{
8259 predicate(UseVIS >= 3);
8260 match(Set dst (ConvF2L src));
8261 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8262 expand %{
8263 regD tmp;
8264 convF2L_helper(tmp, src);
8265 MoveD2L_reg_reg(dst, tmp);
8266 %}
8267 %}
8268
8269
8270 instruct convI2D_helper(regD dst, regF tmp) %{
8271 effect(USE tmp, DEF dst);
8272 format %{ "FITOD $tmp,$dst" %}
8273 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8274 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8275 ins_pipe(fcvtI2D);
8276 %}
8277
8278 instruct convI2D_stk(stackSlotI src, regD dst) %{
8279 match(Set dst (ConvI2D src));
8280 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8281 expand %{
8282 regF tmp;
8283 stkI_to_regF(tmp, src);
8284 convI2D_helper(dst, tmp);
8285 %}
8286 %}
8287
8288 instruct convI2D_reg(regD_low dst, iRegI src) %{
8289 predicate(UseVIS >= 3);
8290 match(Set dst (ConvI2D src));
8291 expand %{
8292 regF tmp;
8293 MoveI2F_reg_reg(tmp, src);
8294 convI2D_helper(dst, tmp);
8295 %}
8296 %}
8297
8298 instruct convI2D_mem(regD_low dst, memory mem) %{
8299 match(Set dst (ConvI2D (LoadI mem)));
8300 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8301 format %{ "LDF $mem,$dst\n\t"
8302 "FITOD $dst,$dst" %}
8303 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8304 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8305 ins_pipe(floadF_mem);
8306 %}
8307
8308
8309 instruct convI2F_helper(regF dst, regF tmp) %{
8310 effect(DEF dst, USE tmp);
8311 format %{ "FITOS $tmp,$dst" %}
8312 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8313 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8314 ins_pipe(fcvtI2F);
8315 %}
8316
8317 instruct convI2F_stk(regF dst, stackSlotI src) %{
8318 match(Set dst (ConvI2F src));
8319 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8320 expand %{
8321 regF tmp;
8322 stkI_to_regF(tmp,src);
8323 convI2F_helper(dst, tmp);
8324 %}
8325 %}
8326
8327 instruct convI2F_reg(regF dst, iRegI src) %{
8328 predicate(UseVIS >= 3);
8329 match(Set dst (ConvI2F src));
8330 ins_cost(DEFAULT_COST);
8331 expand %{
8332 regF tmp;
8333 MoveI2F_reg_reg(tmp, src);
8334 convI2F_helper(dst, tmp);
8335 %}
8336 %}
8337
8338 instruct convI2F_mem( regF dst, memory mem ) %{
8339 match(Set dst (ConvI2F (LoadI mem)));
8340 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8341 format %{ "LDF $mem,$dst\n\t"
8342 "FITOS $dst,$dst" %}
8343 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8344 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8345 ins_pipe(floadF_mem);
8346 %}
8347
8348
8349 instruct convI2L_reg(iRegL dst, iRegI src) %{
8350 match(Set dst (ConvI2L src));
8351 size(4);
8352 format %{ "SRA $src,0,$dst\t! int->long" %}
8353 opcode(Assembler::sra_op3, Assembler::arith_op);
8354 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8355 ins_pipe(ialu_reg_reg);
8356 %}
8357
8358 // Zero-extend convert int to long
8359 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8360 match(Set dst (AndL (ConvI2L src) mask) );
8361 size(4);
8362 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8363 opcode(Assembler::srl_op3, Assembler::arith_op);
8364 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8365 ins_pipe(ialu_reg_reg);
8366 %}
8367
8368 // Zero-extend long
8369 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8370 match(Set dst (AndL src mask) );
8371 size(4);
8372 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8373 opcode(Assembler::srl_op3, Assembler::arith_op);
8374 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8375 ins_pipe(ialu_reg_reg);
8376 %}
8377
8378
8379 //-----------
8380 // Long to Double conversion using V8 opcodes.
8381 // Still useful because cheetah traps and becomes
8382 // amazingly slow for some common numbers.
8383
8384 // Magic constant, 0x43300000
8385 instruct loadConI_x43300000(iRegI dst) %{
8386 effect(DEF dst);
8387 size(4);
8388 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8389 ins_encode(SetHi22(0x43300000, dst));
8390 ins_pipe(ialu_none);
8391 %}
8392
8393 // Magic constant, 0x41f00000
8394 instruct loadConI_x41f00000(iRegI dst) %{
8395 effect(DEF dst);
8396 size(4);
8397 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8398 ins_encode(SetHi22(0x41f00000, dst));
8399 ins_pipe(ialu_none);
8400 %}
8401
8402 // Construct a double from two float halves
8403 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8404 effect(DEF dst, USE src1, USE src2);
8405 size(8);
8406 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8407 "FMOVS $src2.lo,$dst.lo" %}
8408 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8409 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8410 ins_pipe(faddD_reg_reg);
8411 %}
8412
8413 // Convert integer in high half of a double register (in the lower half of
8414 // the double register file) to double
8415 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8416 effect(DEF dst, USE src);
8417 size(4);
8418 format %{ "FITOD $src,$dst" %}
8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8420 ins_encode(form3_opf_rs2D_rdD(src, dst));
8421 ins_pipe(fcvtLHi2D);
8422 %}
8423
8424 // Add float double precision
8425 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8426 effect(DEF dst, USE src1, USE src2);
8427 size(4);
8428 format %{ "FADDD $src1,$src2,$dst" %}
8429 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8430 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8431 ins_pipe(faddD_reg_reg);
8432 %}
8433
8434 // Sub float double precision
8435 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8436 effect(DEF dst, USE src1, USE src2);
8437 size(4);
8438 format %{ "FSUBD $src1,$src2,$dst" %}
8439 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8440 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8441 ins_pipe(faddD_reg_reg);
8442 %}
8443
8444 // Mul float double precision
8445 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8446 effect(DEF dst, USE src1, USE src2);
8447 size(4);
8448 format %{ "FMULD $src1,$src2,$dst" %}
8449 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8450 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8451 ins_pipe(fmulD_reg_reg);
8452 %}
8453
8454 // Long to Double conversion using fast fxtof
8455 instruct convL2D_helper(regD dst, regD tmp) %{
8456 effect(DEF dst, USE tmp);
8457 size(4);
8458 format %{ "FXTOD $tmp,$dst" %}
8459 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8460 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8461 ins_pipe(fcvtL2D);
8462 %}
8463
8464 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8465 match(Set dst (ConvL2D src));
8466 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8467 expand %{
8468 regD tmp;
8469 stkL_to_regD(tmp, src);
8470 convL2D_helper(dst, tmp);
8471 %}
8472 %}
8473
8474 instruct convL2D_reg(regD dst, iRegL src) %{
8475 predicate(UseVIS >= 3);
8476 match(Set dst (ConvL2D src));
8477 expand %{
8478 regD tmp;
8479 MoveL2D_reg_reg(tmp, src);
8480 convL2D_helper(dst, tmp);
8481 %}
8482 %}
8483
8484 // Long to Float conversion using fast fxtof
8485 instruct convL2F_helper(regF dst, regD tmp) %{
8486 effect(DEF dst, USE tmp);
8487 size(4);
8488 format %{ "FXTOS $tmp,$dst" %}
8489 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8490 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8491 ins_pipe(fcvtL2F);
8492 %}
8493
8494 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8495 match(Set dst (ConvL2F src));
8496 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8497 expand %{
8498 regD tmp;
8499 stkL_to_regD(tmp, src);
8500 convL2F_helper(dst, tmp);
8501 %}
8502 %}
8503
8504 instruct convL2F_reg(regF dst, iRegL src) %{
8505 predicate(UseVIS >= 3);
8506 match(Set dst (ConvL2F src));
8507 ins_cost(DEFAULT_COST);
8508 expand %{
8509 regD tmp;
8510 MoveL2D_reg_reg(tmp, src);
8511 convL2F_helper(dst, tmp);
8512 %}
8513 %}
8514
8515 //-----------
8516
8517 instruct convL2I_reg(iRegI dst, iRegL src) %{
8518 match(Set dst (ConvL2I src));
8519 size(4);
8520 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8521 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8522 ins_pipe(ialu_reg);
8523 %}
8524
8525 // Register Shift Right Immediate
8526 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8527 match(Set dst (ConvL2I (RShiftL src cnt)));
8528
8529 size(4);
8530 format %{ "SRAX $src,$cnt,$dst" %}
8531 opcode(Assembler::srax_op3, Assembler::arith_op);
8532 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8533 ins_pipe(ialu_reg_imm);
8534 %}
8535
8536 //----------Control Flow Instructions------------------------------------------
8537 // Compare Instructions
8538 // Compare Integers
8539 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8540 match(Set icc (CmpI op1 op2));
8541 effect( DEF icc, USE op1, USE op2 );
8542
8543 size(4);
8544 format %{ "CMP $op1,$op2" %}
8545 opcode(Assembler::subcc_op3, Assembler::arith_op);
8546 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8547 ins_pipe(ialu_cconly_reg_reg);
8548 %}
8549
8550 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8551 match(Set icc (CmpU op1 op2));
8552
8553 size(4);
8554 format %{ "CMP $op1,$op2\t! unsigned" %}
8555 opcode(Assembler::subcc_op3, Assembler::arith_op);
8556 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8557 ins_pipe(ialu_cconly_reg_reg);
8558 %}
8559
8560 instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{
8561 match(Set xcc (CmpUL op1 op2));
8562 effect(DEF xcc, USE op1, USE op2);
8563
8564 size(4);
8565 format %{ "CMP $op1,$op2\t! unsigned long" %}
8566 opcode(Assembler::subcc_op3, Assembler::arith_op);
8567 ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0));
8568 ins_pipe(ialu_cconly_reg_reg);
8569 %}
8570
8571 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8572 match(Set icc (CmpI op1 op2));
8573 effect( DEF icc, USE op1 );
8574
8575 size(4);
8576 format %{ "CMP $op1,$op2" %}
8577 opcode(Assembler::subcc_op3, Assembler::arith_op);
8578 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8579 ins_pipe(ialu_cconly_reg_imm);
8580 %}
8581
8582 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8583 match(Set icc (CmpI (AndI op1 op2) zero));
8584
8585 size(4);
8586 format %{ "BTST $op2,$op1" %}
8587 opcode(Assembler::andcc_op3, Assembler::arith_op);
8588 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8589 ins_pipe(ialu_cconly_reg_reg_zero);
8590 %}
8591
8592 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8593 match(Set icc (CmpI (AndI op1 op2) zero));
8594
8595 size(4);
8596 format %{ "BTST $op2,$op1" %}
8597 opcode(Assembler::andcc_op3, Assembler::arith_op);
8598 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8599 ins_pipe(ialu_cconly_reg_imm_zero);
8600 %}
8601
8602 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8603 match(Set xcc (CmpL op1 op2));
8604 effect( DEF xcc, USE op1, USE op2 );
8605
8606 size(4);
8607 format %{ "CMP $op1,$op2\t\t! long" %}
8608 opcode(Assembler::subcc_op3, Assembler::arith_op);
8609 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8610 ins_pipe(ialu_cconly_reg_reg);
8611 %}
8612
8613 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8614 match(Set xcc (CmpL op1 con));
8615 effect( DEF xcc, USE op1, USE con );
8616
8617 size(4);
8618 format %{ "CMP $op1,$con\t\t! long" %}
8619 opcode(Assembler::subcc_op3, Assembler::arith_op);
8620 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8621 ins_pipe(ialu_cconly_reg_reg);
8622 %}
8623
8624 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8625 match(Set xcc (CmpL (AndL op1 op2) zero));
8626 effect( DEF xcc, USE op1, USE op2 );
8627
8628 size(4);
8629 format %{ "BTST $op1,$op2\t\t! long" %}
8630 opcode(Assembler::andcc_op3, Assembler::arith_op);
8631 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8632 ins_pipe(ialu_cconly_reg_reg);
8633 %}
8634
8635 // useful for checking the alignment of a pointer:
8636 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8637 match(Set xcc (CmpL (AndL op1 con) zero));
8638 effect( DEF xcc, USE op1, USE con );
8639
8640 size(4);
8641 format %{ "BTST $op1,$con\t\t! long" %}
8642 opcode(Assembler::andcc_op3, Assembler::arith_op);
8643 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8644 ins_pipe(ialu_cconly_reg_reg);
8645 %}
8646
8647 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8648 match(Set icc (CmpU op1 op2));
8649
8650 size(4);
8651 format %{ "CMP $op1,$op2\t! unsigned" %}
8652 opcode(Assembler::subcc_op3, Assembler::arith_op);
8653 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8654 ins_pipe(ialu_cconly_reg_imm);
8655 %}
8656
8657 instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{
8658 match(Set xcc (CmpUL op1 op2));
8659 effect(DEF xcc, USE op1, USE op2);
8660
8661 size(4);
8662 format %{ "CMP $op1,$op2\t! unsigned long" %}
8663 opcode(Assembler::subcc_op3, Assembler::arith_op);
8664 ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0));
8665 ins_pipe(ialu_cconly_reg_imm);
8666 %}
8667
8668 // Compare Pointers
8669 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8670 match(Set pcc (CmpP op1 op2));
8671
8672 size(4);
8673 format %{ "CMP $op1,$op2\t! ptr" %}
8674 opcode(Assembler::subcc_op3, Assembler::arith_op);
8675 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8676 ins_pipe(ialu_cconly_reg_reg);
8677 %}
8678
8679 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8680 match(Set pcc (CmpP op1 op2));
8681
8682 size(4);
8683 format %{ "CMP $op1,$op2\t! ptr" %}
8684 opcode(Assembler::subcc_op3, Assembler::arith_op);
8685 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8686 ins_pipe(ialu_cconly_reg_imm);
8687 %}
8688
8689 // Compare Narrow oops
8690 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8691 match(Set icc (CmpN op1 op2));
8692
8693 size(4);
8694 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8695 opcode(Assembler::subcc_op3, Assembler::arith_op);
8696 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8697 ins_pipe(ialu_cconly_reg_reg);
8698 %}
8699
8700 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8701 match(Set icc (CmpN op1 op2));
8702
8703 size(4);
8704 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8705 opcode(Assembler::subcc_op3, Assembler::arith_op);
8706 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8707 ins_pipe(ialu_cconly_reg_imm);
8708 %}
8709
8710 //----------Max and Min--------------------------------------------------------
8711 // Min Instructions
8712 // Conditional move for min
8713 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8714 effect( USE_DEF op2, USE op1, USE icc );
8715
8716 size(4);
8717 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8718 opcode(Assembler::less);
8719 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8720 ins_pipe(ialu_reg_flags);
8721 %}
8722
8723 // Min Register with Register.
8724 instruct minI_eReg(iRegI op1, iRegI op2) %{
8725 match(Set op2 (MinI op1 op2));
8726 ins_cost(DEFAULT_COST*2);
8727 expand %{
8728 flagsReg icc;
8729 compI_iReg(icc,op1,op2);
8730 cmovI_reg_lt(op2,op1,icc);
8731 %}
8732 %}
8733
8734 // Max Instructions
8735 // Conditional move for max
8736 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8737 effect( USE_DEF op2, USE op1, USE icc );
8738 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8739 opcode(Assembler::greater);
8740 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8741 ins_pipe(ialu_reg_flags);
8742 %}
8743
8744 // Max Register with Register
8745 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8746 match(Set op2 (MaxI op1 op2));
8747 ins_cost(DEFAULT_COST*2);
8748 expand %{
8749 flagsReg icc;
8750 compI_iReg(icc,op1,op2);
8751 cmovI_reg_gt(op2,op1,icc);
8752 %}
8753 %}
8754
8755
8756 //----------Float Compares----------------------------------------------------
8757 // Compare floating, generate condition code
8758 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8759 match(Set fcc (CmpF src1 src2));
8760
8761 size(4);
8762 format %{ "FCMPs $fcc,$src1,$src2" %}
8763 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8764 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8765 ins_pipe(faddF_fcc_reg_reg_zero);
8766 %}
8767
8768 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8769 match(Set fcc (CmpD src1 src2));
8770
8771 size(4);
8772 format %{ "FCMPd $fcc,$src1,$src2" %}
8773 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8774 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8775 ins_pipe(faddD_fcc_reg_reg_zero);
8776 %}
8777
8778
8779 // Compare floating, generate -1,0,1
8780 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8781 match(Set dst (CmpF3 src1 src2));
8782 effect(KILL fcc0);
8783 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8784 format %{ "fcmpl $dst,$src1,$src2" %}
8785 // Primary = float
8786 opcode( true );
8787 ins_encode( floating_cmp( dst, src1, src2 ) );
8788 ins_pipe( floating_cmp );
8789 %}
8790
8791 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8792 match(Set dst (CmpD3 src1 src2));
8793 effect(KILL fcc0);
8794 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8795 format %{ "dcmpl $dst,$src1,$src2" %}
8796 // Primary = double (not float)
8797 opcode( false );
8798 ins_encode( floating_cmp( dst, src1, src2 ) );
8799 ins_pipe( floating_cmp );
8800 %}
8801
8802 //----------Branches---------------------------------------------------------
8803 // Jump
8804 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8805 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8806 match(Jump switch_val);
8807 effect(TEMP table);
8808
8809 ins_cost(350);
8810
8811 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8812 "LD [O7 + $switch_val], O7\n\t"
8813 "JUMP O7" %}
8814 ins_encode %{
8815 // Calculate table address into a register.
8816 Register table_reg;
8817 Register label_reg = O7;
8818 // If we are calculating the size of this instruction don't trust
8819 // zero offsets because they might change when
8820 // MachConstantBaseNode decides to optimize the constant table
8821 // base.
8822 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8823 table_reg = $constanttablebase;
8824 } else {
8825 table_reg = O7;
8826 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8827 __ add($constanttablebase, con_offset, table_reg);
8828 }
8829
8830 // Jump to base address + switch value
8831 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8832 __ jmp(label_reg, G0);
8833 __ delayed()->nop();
8834 %}
8835 ins_pipe(ialu_reg_reg);
8836 %}
8837
8838 // Direct Branch. Use V8 version with longer range.
8839 instruct branch(label labl) %{
8840 match(Goto);
8841 effect(USE labl);
8842
8843 size(8);
8844 ins_cost(BRANCH_COST);
8845 format %{ "BA $labl" %}
8846 ins_encode %{
8847 Label* L = $labl$$label;
8848 __ ba(*L);
8849 __ delayed()->nop();
8850 %}
8851 ins_avoid_back_to_back(AVOID_BEFORE);
8852 ins_pipe(br);
8853 %}
8854
8855 // Direct Branch, short with no delay slot
8856 instruct branch_short(label labl) %{
8857 match(Goto);
8858 predicate(UseCBCond);
8859 effect(USE labl);
8860
8861 size(4); // Assuming no NOP inserted.
8862 ins_cost(BRANCH_COST);
8863 format %{ "BA $labl\t! short branch" %}
8864 ins_encode %{
8865 Label* L = $labl$$label;
8866 assert(__ use_cbcond(*L), "back to back cbcond");
8867 __ ba_short(*L);
8868 %}
8869 ins_short_branch(1);
8870 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8871 ins_pipe(cbcond_reg_imm);
8872 %}
8873
8874 // Conditional Direct Branch
8875 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8876 match(If cmp icc);
8877 effect(USE labl);
8878
8879 size(8);
8880 ins_cost(BRANCH_COST);
8881 format %{ "BP$cmp $icc,$labl" %}
8882 // Prim = bits 24-22, Secnd = bits 31-30
8883 ins_encode( enc_bp( labl, cmp, icc ) );
8884 ins_avoid_back_to_back(AVOID_BEFORE);
8885 ins_pipe(br_cc);
8886 %}
8887
8888 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8889 match(If cmp icc);
8890 effect(USE labl);
8891
8892 ins_cost(BRANCH_COST);
8893 format %{ "BP$cmp $icc,$labl" %}
8894 // Prim = bits 24-22, Secnd = bits 31-30
8895 ins_encode( enc_bp( labl, cmp, icc ) );
8896 ins_avoid_back_to_back(AVOID_BEFORE);
8897 ins_pipe(br_cc);
8898 %}
8899
8900 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8901 match(If cmp pcc);
8902 effect(USE labl);
8903
8904 size(8);
8905 ins_cost(BRANCH_COST);
8906 format %{ "BP$cmp $pcc,$labl" %}
8907 ins_encode %{
8908 Label* L = $labl$$label;
8909 Assembler::Predict predict_taken =
8910 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8911
8912 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8913 __ delayed()->nop();
8914 %}
8915 ins_avoid_back_to_back(AVOID_BEFORE);
8916 ins_pipe(br_cc);
8917 %}
8918
8919 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8920 match(If cmp fcc);
8921 effect(USE labl);
8922
8923 size(8);
8924 ins_cost(BRANCH_COST);
8925 format %{ "FBP$cmp $fcc,$labl" %}
8926 ins_encode %{
8927 Label* L = $labl$$label;
8928 Assembler::Predict predict_taken =
8929 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8930
8931 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
8932 __ delayed()->nop();
8933 %}
8934 ins_avoid_back_to_back(AVOID_BEFORE);
8935 ins_pipe(br_fcc);
8936 %}
8937
8938 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8939 match(CountedLoopEnd cmp icc);
8940 effect(USE labl);
8941
8942 size(8);
8943 ins_cost(BRANCH_COST);
8944 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8945 // Prim = bits 24-22, Secnd = bits 31-30
8946 ins_encode( enc_bp( labl, cmp, icc ) );
8947 ins_avoid_back_to_back(AVOID_BEFORE);
8948 ins_pipe(br_cc);
8949 %}
8950
8951 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8952 match(CountedLoopEnd cmp icc);
8953 effect(USE labl);
8954
8955 size(8);
8956 ins_cost(BRANCH_COST);
8957 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8958 // Prim = bits 24-22, Secnd = bits 31-30
8959 ins_encode( enc_bp( labl, cmp, icc ) );
8960 ins_avoid_back_to_back(AVOID_BEFORE);
8961 ins_pipe(br_cc);
8962 %}
8963
8964 // Compare and branch instructions
8965 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8966 match(If cmp (CmpI op1 op2));
8967 effect(USE labl, KILL icc);
8968
8969 size(12);
8970 ins_cost(BRANCH_COST);
8971 format %{ "CMP $op1,$op2\t! int\n\t"
8972 "BP$cmp $labl" %}
8973 ins_encode %{
8974 Label* L = $labl$$label;
8975 Assembler::Predict predict_taken =
8976 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8977 __ cmp($op1$$Register, $op2$$Register);
8978 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8979 __ delayed()->nop();
8980 %}
8981 ins_pipe(cmp_br_reg_reg);
8982 %}
8983
8984 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8985 match(If cmp (CmpI op1 op2));
8986 effect(USE labl, KILL icc);
8987
8988 size(12);
8989 ins_cost(BRANCH_COST);
8990 format %{ "CMP $op1,$op2\t! int\n\t"
8991 "BP$cmp $labl" %}
8992 ins_encode %{
8993 Label* L = $labl$$label;
8994 Assembler::Predict predict_taken =
8995 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8996 __ cmp($op1$$Register, $op2$$constant);
8997 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8998 __ delayed()->nop();
8999 %}
9000 ins_pipe(cmp_br_reg_imm);
9001 %}
9002
9003 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9004 match(If cmp (CmpU op1 op2));
9005 effect(USE labl, KILL icc);
9006
9007 size(12);
9008 ins_cost(BRANCH_COST);
9009 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9010 "BP$cmp $labl" %}
9011 ins_encode %{
9012 Label* L = $labl$$label;
9013 Assembler::Predict predict_taken =
9014 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9015 __ cmp($op1$$Register, $op2$$Register);
9016 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9017 __ delayed()->nop();
9018 %}
9019 ins_pipe(cmp_br_reg_reg);
9020 %}
9021
9022 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9023 match(If cmp (CmpU op1 op2));
9024 effect(USE labl, KILL icc);
9025
9026 size(12);
9027 ins_cost(BRANCH_COST);
9028 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9029 "BP$cmp $labl" %}
9030 ins_encode %{
9031 Label* L = $labl$$label;
9032 Assembler::Predict predict_taken =
9033 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9034 __ cmp($op1$$Register, $op2$$constant);
9035 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9036 __ delayed()->nop();
9037 %}
9038 ins_pipe(cmp_br_reg_imm);
9039 %}
9040
9041 instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
9042 match(If cmp (CmpUL op1 op2));
9043 effect(USE labl, KILL xcc);
9044
9045 size(12);
9046 ins_cost(BRANCH_COST);
9047 format %{ "CMP $op1,$op2\t! unsigned long\n\t"
9048 "BP$cmp $labl" %}
9049 ins_encode %{
9050 Label* L = $labl$$label;
9051 Assembler::Predict predict_taken =
9052 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9053 __ cmp($op1$$Register, $op2$$Register);
9054 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9055 __ delayed()->nop();
9056 %}
9057 ins_pipe(cmp_br_reg_reg);
9058 %}
9059
9060 instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
9061 match(If cmp (CmpUL op1 op2));
9062 effect(USE labl, KILL xcc);
9063
9064 size(12);
9065 ins_cost(BRANCH_COST);
9066 format %{ "CMP $op1,$op2\t! unsigned long\n\t"
9067 "BP$cmp $labl" %}
9068 ins_encode %{
9069 Label* L = $labl$$label;
9070 Assembler::Predict predict_taken =
9071 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9072 __ cmp($op1$$Register, $op2$$constant);
9073 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9074 __ delayed()->nop();
9075 %}
9076 ins_pipe(cmp_br_reg_imm);
9077 %}
9078
9079 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9080 match(If cmp (CmpL op1 op2));
9081 effect(USE labl, KILL xcc);
9082
9083 size(12);
9084 ins_cost(BRANCH_COST);
9085 format %{ "CMP $op1,$op2\t! long\n\t"
9086 "BP$cmp $labl" %}
9087 ins_encode %{
9088 Label* L = $labl$$label;
9089 Assembler::Predict predict_taken =
9090 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9091 __ cmp($op1$$Register, $op2$$Register);
9092 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9093 __ delayed()->nop();
9094 %}
9095 ins_pipe(cmp_br_reg_reg);
9096 %}
9097
9098 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9099 match(If cmp (CmpL op1 op2));
9100 effect(USE labl, KILL xcc);
9101
9102 size(12);
9103 ins_cost(BRANCH_COST);
9104 format %{ "CMP $op1,$op2\t! long\n\t"
9105 "BP$cmp $labl" %}
9106 ins_encode %{
9107 Label* L = $labl$$label;
9108 Assembler::Predict predict_taken =
9109 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9110 __ cmp($op1$$Register, $op2$$constant);
9111 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9112 __ delayed()->nop();
9113 %}
9114 ins_pipe(cmp_br_reg_imm);
9115 %}
9116
9117 // Compare Pointers and branch
9118 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9119 match(If cmp (CmpP op1 op2));
9120 effect(USE labl, KILL pcc);
9121
9122 size(12);
9123 ins_cost(BRANCH_COST);
9124 format %{ "CMP $op1,$op2\t! ptr\n\t"
9125 "B$cmp $labl" %}
9126 ins_encode %{
9127 Label* L = $labl$$label;
9128 Assembler::Predict predict_taken =
9129 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9130 __ cmp($op1$$Register, $op2$$Register);
9131 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9132 __ delayed()->nop();
9133 %}
9134 ins_pipe(cmp_br_reg_reg);
9135 %}
9136
9137 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9138 match(If cmp (CmpP op1 null));
9139 effect(USE labl, KILL pcc);
9140
9141 size(12);
9142 ins_cost(BRANCH_COST);
9143 format %{ "CMP $op1,0\t! ptr\n\t"
9144 "B$cmp $labl" %}
9145 ins_encode %{
9146 Label* L = $labl$$label;
9147 Assembler::Predict predict_taken =
9148 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9149 __ cmp($op1$$Register, G0);
9150 // bpr() is not used here since it has shorter distance.
9151 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9152 __ delayed()->nop();
9153 %}
9154 ins_pipe(cmp_br_reg_reg);
9155 %}
9156
9157 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9158 match(If cmp (CmpN op1 op2));
9159 effect(USE labl, KILL icc);
9160
9161 size(12);
9162 ins_cost(BRANCH_COST);
9163 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9164 "BP$cmp $labl" %}
9165 ins_encode %{
9166 Label* L = $labl$$label;
9167 Assembler::Predict predict_taken =
9168 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9169 __ cmp($op1$$Register, $op2$$Register);
9170 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9171 __ delayed()->nop();
9172 %}
9173 ins_pipe(cmp_br_reg_reg);
9174 %}
9175
9176 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9177 match(If cmp (CmpN op1 null));
9178 effect(USE labl, KILL icc);
9179
9180 size(12);
9181 ins_cost(BRANCH_COST);
9182 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9183 "BP$cmp $labl" %}
9184 ins_encode %{
9185 Label* L = $labl$$label;
9186 Assembler::Predict predict_taken =
9187 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9188 __ cmp($op1$$Register, G0);
9189 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9190 __ delayed()->nop();
9191 %}
9192 ins_pipe(cmp_br_reg_reg);
9193 %}
9194
9195 // Loop back branch
9196 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9197 match(CountedLoopEnd cmp (CmpI op1 op2));
9198 effect(USE labl, KILL icc);
9199
9200 size(12);
9201 ins_cost(BRANCH_COST);
9202 format %{ "CMP $op1,$op2\t! int\n\t"
9203 "BP$cmp $labl\t! Loop end" %}
9204 ins_encode %{
9205 Label* L = $labl$$label;
9206 Assembler::Predict predict_taken =
9207 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9208 __ cmp($op1$$Register, $op2$$Register);
9209 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9210 __ delayed()->nop();
9211 %}
9212 ins_pipe(cmp_br_reg_reg);
9213 %}
9214
9215 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9216 match(CountedLoopEnd cmp (CmpI op1 op2));
9217 effect(USE labl, KILL icc);
9218
9219 size(12);
9220 ins_cost(BRANCH_COST);
9221 format %{ "CMP $op1,$op2\t! int\n\t"
9222 "BP$cmp $labl\t! Loop end" %}
9223 ins_encode %{
9224 Label* L = $labl$$label;
9225 Assembler::Predict predict_taken =
9226 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9227 __ cmp($op1$$Register, $op2$$constant);
9228 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9229 __ delayed()->nop();
9230 %}
9231 ins_pipe(cmp_br_reg_imm);
9232 %}
9233
9234 // Short compare and branch instructions
9235 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9236 match(If cmp (CmpI op1 op2));
9237 predicate(UseCBCond);
9238 effect(USE labl, KILL icc);
9239
9240 size(4); // Assuming no NOP inserted.
9241 ins_cost(BRANCH_COST);
9242 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9243 ins_encode %{
9244 Label* L = $labl$$label;
9245 assert(__ use_cbcond(*L), "back to back cbcond");
9246 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9247 %}
9248 ins_short_branch(1);
9249 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9250 ins_pipe(cbcond_reg_reg);
9251 %}
9252
9253 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9254 match(If cmp (CmpI op1 op2));
9255 predicate(UseCBCond);
9256 effect(USE labl, KILL icc);
9257
9258 size(4); // Assuming no NOP inserted.
9259 ins_cost(BRANCH_COST);
9260 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9261 ins_encode %{
9262 Label* L = $labl$$label;
9263 assert(__ use_cbcond(*L), "back to back cbcond");
9264 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9265 %}
9266 ins_short_branch(1);
9267 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9268 ins_pipe(cbcond_reg_imm);
9269 %}
9270
9271 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9272 match(If cmp (CmpU op1 op2));
9273 predicate(UseCBCond);
9274 effect(USE labl, KILL icc);
9275
9276 size(4); // Assuming no NOP inserted.
9277 ins_cost(BRANCH_COST);
9278 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9279 ins_encode %{
9280 Label* L = $labl$$label;
9281 assert(__ use_cbcond(*L), "back to back cbcond");
9282 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9283 %}
9284 ins_short_branch(1);
9285 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9286 ins_pipe(cbcond_reg_reg);
9287 %}
9288
9289 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9290 match(If cmp (CmpU op1 op2));
9291 predicate(UseCBCond);
9292 effect(USE labl, KILL icc);
9293
9294 size(4); // Assuming no NOP inserted.
9295 ins_cost(BRANCH_COST);
9296 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9297 ins_encode %{
9298 Label* L = $labl$$label;
9299 assert(__ use_cbcond(*L), "back to back cbcond");
9300 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9301 %}
9302 ins_short_branch(1);
9303 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9304 ins_pipe(cbcond_reg_imm);
9305 %}
9306
9307 instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
9308 match(If cmp (CmpUL op1 op2));
9309 predicate(UseCBCond);
9310 effect(USE labl, KILL xcc);
9311
9312 size(4);
9313 ins_cost(BRANCH_COST);
9314 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
9315 ins_encode %{
9316 Label* L = $labl$$label;
9317 assert(__ use_cbcond(*L), "back to back cbcond");
9318 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9319 %}
9320 ins_short_branch(1);
9321 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9322 ins_pipe(cbcond_reg_reg);
9323 %}
9324
9325 instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
9326 match(If cmp (CmpUL op1 op2));
9327 predicate(UseCBCond);
9328 effect(USE labl, KILL xcc);
9329
9330 size(4);
9331 ins_cost(BRANCH_COST);
9332 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
9333 ins_encode %{
9334 Label* L = $labl$$label;
9335 assert(__ use_cbcond(*L), "back to back cbcond");
9336 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9337 %}
9338 ins_short_branch(1);
9339 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9340 ins_pipe(cbcond_reg_imm);
9341 %}
9342
9343 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9344 match(If cmp (CmpL op1 op2));
9345 predicate(UseCBCond);
9346 effect(USE labl, KILL xcc);
9347
9348 size(4); // Assuming no NOP inserted.
9349 ins_cost(BRANCH_COST);
9350 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9351 ins_encode %{
9352 Label* L = $labl$$label;
9353 assert(__ use_cbcond(*L), "back to back cbcond");
9354 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9355 %}
9356 ins_short_branch(1);
9357 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9358 ins_pipe(cbcond_reg_reg);
9359 %}
9360
9361 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9362 match(If cmp (CmpL op1 op2));
9363 predicate(UseCBCond);
9364 effect(USE labl, KILL xcc);
9365
9366 size(4); // Assuming no NOP inserted.
9367 ins_cost(BRANCH_COST);
9368 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9369 ins_encode %{
9370 Label* L = $labl$$label;
9371 assert(__ use_cbcond(*L), "back to back cbcond");
9372 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9373 %}
9374 ins_short_branch(1);
9375 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9376 ins_pipe(cbcond_reg_imm);
9377 %}
9378
9379 // Compare Pointers and branch
9380 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9381 match(If cmp (CmpP op1 op2));
9382 predicate(UseCBCond);
9383 effect(USE labl, KILL pcc);
9384
9385 size(4); // Assuming no NOP inserted.
9386 ins_cost(BRANCH_COST);
9387 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9388 ins_encode %{
9389 Label* L = $labl$$label;
9390 assert(__ use_cbcond(*L), "back to back cbcond");
9391 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9392 %}
9393 ins_short_branch(1);
9394 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9395 ins_pipe(cbcond_reg_reg);
9396 %}
9397
9398 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9399 match(If cmp (CmpP op1 null));
9400 predicate(UseCBCond);
9401 effect(USE labl, KILL pcc);
9402
9403 size(4); // Assuming no NOP inserted.
9404 ins_cost(BRANCH_COST);
9405 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9406 ins_encode %{
9407 Label* L = $labl$$label;
9408 assert(__ use_cbcond(*L), "back to back cbcond");
9409 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9410 %}
9411 ins_short_branch(1);
9412 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9413 ins_pipe(cbcond_reg_reg);
9414 %}
9415
9416 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9417 match(If cmp (CmpN op1 op2));
9418 predicate(UseCBCond);
9419 effect(USE labl, KILL icc);
9420
9421 size(4); // Assuming no NOP inserted.
9422 ins_cost(BRANCH_COST);
9423 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9424 ins_encode %{
9425 Label* L = $labl$$label;
9426 assert(__ use_cbcond(*L), "back to back cbcond");
9427 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9428 %}
9429 ins_short_branch(1);
9430 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9431 ins_pipe(cbcond_reg_reg);
9432 %}
9433
9434 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9435 match(If cmp (CmpN op1 null));
9436 predicate(UseCBCond);
9437 effect(USE labl, KILL icc);
9438
9439 size(4); // Assuming no NOP inserted.
9440 ins_cost(BRANCH_COST);
9441 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9442 ins_encode %{
9443 Label* L = $labl$$label;
9444 assert(__ use_cbcond(*L), "back to back cbcond");
9445 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9446 %}
9447 ins_short_branch(1);
9448 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9449 ins_pipe(cbcond_reg_reg);
9450 %}
9451
9452 // Loop back branch
9453 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9454 match(CountedLoopEnd cmp (CmpI op1 op2));
9455 predicate(UseCBCond);
9456 effect(USE labl, KILL icc);
9457
9458 size(4); // Assuming no NOP inserted.
9459 ins_cost(BRANCH_COST);
9460 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9461 ins_encode %{
9462 Label* L = $labl$$label;
9463 assert(__ use_cbcond(*L), "back to back cbcond");
9464 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9465 %}
9466 ins_short_branch(1);
9467 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9468 ins_pipe(cbcond_reg_reg);
9469 %}
9470
9471 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9472 match(CountedLoopEnd cmp (CmpI op1 op2));
9473 predicate(UseCBCond);
9474 effect(USE labl, KILL icc);
9475
9476 size(4); // Assuming no NOP inserted.
9477 ins_cost(BRANCH_COST);
9478 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9479 ins_encode %{
9480 Label* L = $labl$$label;
9481 assert(__ use_cbcond(*L), "back to back cbcond");
9482 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9483 %}
9484 ins_short_branch(1);
9485 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9486 ins_pipe(cbcond_reg_imm);
9487 %}
9488
9489 // Branch-on-register tests all 64 bits. We assume that values
9490 // in 64-bit registers always remains zero or sign extended
9491 // unless our code munges the high bits. Interrupts can chop
9492 // the high order bits to zero or sign at any time.
9493 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9494 match(If cmp (CmpI op1 zero));
9495 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9496 effect(USE labl);
9497
9498 size(8);
9499 ins_cost(BRANCH_COST);
9500 format %{ "BR$cmp $op1,$labl" %}
9501 ins_encode( enc_bpr( labl, cmp, op1 ) );
9502 ins_avoid_back_to_back(AVOID_BEFORE);
9503 ins_pipe(br_reg);
9504 %}
9505
9506 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9507 match(If cmp (CmpP op1 null));
9508 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9509 effect(USE labl);
9510
9511 size(8);
9512 ins_cost(BRANCH_COST);
9513 format %{ "BR$cmp $op1,$labl" %}
9514 ins_encode( enc_bpr( labl, cmp, op1 ) );
9515 ins_avoid_back_to_back(AVOID_BEFORE);
9516 ins_pipe(br_reg);
9517 %}
9518
9519 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9520 match(If cmp (CmpL op1 zero));
9521 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9522 effect(USE labl);
9523
9524 size(8);
9525 ins_cost(BRANCH_COST);
9526 format %{ "BR$cmp $op1,$labl" %}
9527 ins_encode( enc_bpr( labl, cmp, op1 ) );
9528 ins_avoid_back_to_back(AVOID_BEFORE);
9529 ins_pipe(br_reg);
9530 %}
9531
9532
9533 // ============================================================================
9534 // Long Compare
9535 //
9536 // Currently we hold longs in 2 registers. Comparing such values efficiently
9537 // is tricky. The flavor of compare used depends on whether we are testing
9538 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9539 // The GE test is the negated LT test. The LE test can be had by commuting
9540 // the operands (yielding a GE test) and then negating; negate again for the
9541 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9542 // NE test is negated from that.
9543
9544 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9545 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9546 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9547 // are collapsed internally in the ADLC's dfa-gen code. The match for
9548 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9549 // foo match ends up with the wrong leaf. One fix is to not match both
9550 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9551 // both forms beat the trinary form of long-compare and both are very useful
9552 // on Intel which has so few registers.
9553
9554 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9555 match(If cmp xcc);
9556 effect(USE labl);
9557
9558 size(8);
9559 ins_cost(BRANCH_COST);
9560 format %{ "BP$cmp $xcc,$labl" %}
9561 ins_encode %{
9562 Label* L = $labl$$label;
9563 Assembler::Predict predict_taken =
9564 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9565
9566 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9567 __ delayed()->nop();
9568 %}
9569 ins_avoid_back_to_back(AVOID_BEFORE);
9570 ins_pipe(br_cc);
9571 %}
9572
9573 instruct branchConU_long(cmpOpU cmp, flagsRegUL xcc, label labl) %{
9574 match(If cmp xcc);
9575 effect(USE labl);
9576
9577 size(8);
9578 ins_cost(BRANCH_COST);
9579 format %{ "BP$cmp $xcc,$labl" %}
9580 ins_encode %{
9581 Label* L = $labl$$label;
9582 Assembler::Predict predict_taken =
9583 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9584
9585 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9586 __ delayed()->nop();
9587 %}
9588 ins_avoid_back_to_back(AVOID_BEFORE);
9589 ins_pipe(br_cc);
9590 %}
9591
9592 // Manifest a CmpL3 result in an integer register. Very painful.
9593 // This is the test to avoid.
9594 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9595 match(Set dst (CmpL3 src1 src2) );
9596 effect( KILL ccr );
9597 ins_cost(6*DEFAULT_COST);
9598 size(24);
9599 format %{ "CMP $src1,$src2\t\t! long\n"
9600 "\tBLT,a,pn done\n"
9601 "\tMOV -1,$dst\t! delay slot\n"
9602 "\tBGT,a,pn done\n"
9603 "\tMOV 1,$dst\t! delay slot\n"
9604 "\tCLR $dst\n"
9605 "done:" %}
9606 ins_encode( cmpl_flag(src1,src2,dst) );
9607 ins_pipe(cmpL_reg);
9608 %}
9609
9610 // Conditional move
9611 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9612 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9613 ins_cost(150);
9614 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9615 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9616 ins_pipe(ialu_reg);
9617 %}
9618
9619 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9620 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9621 ins_cost(140);
9622 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9623 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9624 ins_pipe(ialu_imm);
9625 %}
9626
9627 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9628 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9629 ins_cost(150);
9630 format %{ "MOV$cmp $xcc,$src,$dst" %}
9631 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9632 ins_pipe(ialu_reg);
9633 %}
9634
9635 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9636 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9637 ins_cost(140);
9638 format %{ "MOV$cmp $xcc,$src,$dst" %}
9639 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9640 ins_pipe(ialu_imm);
9641 %}
9642
9643 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9644 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9645 ins_cost(150);
9646 format %{ "MOV$cmp $xcc,$src,$dst" %}
9647 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9648 ins_pipe(ialu_reg);
9649 %}
9650
9651 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9652 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9653 ins_cost(150);
9654 format %{ "MOV$cmp $xcc,$src,$dst" %}
9655 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9656 ins_pipe(ialu_reg);
9657 %}
9658
9659 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9660 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9661 ins_cost(140);
9662 format %{ "MOV$cmp $xcc,$src,$dst" %}
9663 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9664 ins_pipe(ialu_imm);
9665 %}
9666
9667 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9668 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9669 ins_cost(150);
9670 opcode(0x101);
9671 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9672 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9673 ins_pipe(int_conditional_float_move);
9674 %}
9675
9676 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9677 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9678 ins_cost(150);
9679 opcode(0x102);
9680 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9681 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9682 ins_pipe(int_conditional_float_move);
9683 %}
9684
9685 // ============================================================================
9686 // Safepoint Instruction
9687 instruct safePoint_poll(iRegP poll) %{
9688 match(SafePoint poll);
9689 effect(USE poll);
9690
9691 size(4);
9692 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9693 ins_encode %{
9694 __ relocate(relocInfo::poll_type);
9695 __ ld_ptr($poll$$Register, 0, G0);
9696 %}
9697 ins_pipe(loadPollP);
9698 %}
9699
9700 // ============================================================================
9701 // Call Instructions
9702 // Call Java Static Instruction
9703 instruct CallStaticJavaDirect( method meth ) %{
9704 match(CallStaticJava);
9705 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9706 effect(USE meth);
9707
9708 size(8);
9709 ins_cost(CALL_COST);
9710 format %{ "CALL,static ; NOP ==> " %}
9711 ins_encode( Java_Static_Call( meth ), call_epilog );
9712 ins_avoid_back_to_back(AVOID_BEFORE);
9713 ins_pipe(simple_call);
9714 %}
9715
9716 // Call Java Static Instruction (method handle version)
9717 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9718 match(CallStaticJava);
9719 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9720 effect(USE meth, KILL l7_mh_SP_save);
9721
9722 size(16);
9723 ins_cost(CALL_COST);
9724 format %{ "CALL,static/MethodHandle" %}
9725 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9726 ins_pipe(simple_call);
9727 %}
9728
9729 // Call Java Dynamic Instruction
9730 instruct CallDynamicJavaDirect( method meth ) %{
9731 match(CallDynamicJava);
9732 effect(USE meth);
9733
9734 ins_cost(CALL_COST);
9735 format %{ "SET (empty),R_G5\n\t"
9736 "CALL,dynamic ; NOP ==> " %}
9737 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9738 ins_pipe(call);
9739 %}
9740
9741 // Call Runtime Instruction
9742 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9743 match(CallRuntime);
9744 effect(USE meth, KILL l7);
9745 ins_cost(CALL_COST);
9746 format %{ "CALL,runtime" %}
9747 ins_encode( Java_To_Runtime( meth ),
9748 call_epilog, adjust_long_from_native_call );
9749 ins_avoid_back_to_back(AVOID_BEFORE);
9750 ins_pipe(simple_call);
9751 %}
9752
9753 // Call runtime without safepoint - same as CallRuntime
9754 instruct CallLeafDirect(method meth, l7RegP l7) %{
9755 match(CallLeaf);
9756 effect(USE meth, KILL l7);
9757 ins_cost(CALL_COST);
9758 format %{ "CALL,runtime leaf" %}
9759 ins_encode( Java_To_Runtime( meth ),
9760 call_epilog,
9761 adjust_long_from_native_call );
9762 ins_avoid_back_to_back(AVOID_BEFORE);
9763 ins_pipe(simple_call);
9764 %}
9765
9766 // Call runtime without safepoint - same as CallLeaf
9767 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9768 match(CallLeafNoFP);
9769 effect(USE meth, KILL l7);
9770 ins_cost(CALL_COST);
9771 format %{ "CALL,runtime leaf nofp" %}
9772 ins_encode( Java_To_Runtime( meth ),
9773 call_epilog,
9774 adjust_long_from_native_call );
9775 ins_avoid_back_to_back(AVOID_BEFORE);
9776 ins_pipe(simple_call);
9777 %}
9778
9779 // Tail Call; Jump from runtime stub to Java code.
9780 // Also known as an 'interprocedural jump'.
9781 // Target of jump will eventually return to caller.
9782 // TailJump below removes the return address.
9783 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9784 match(TailCall jump_target method_oop );
9785
9786 ins_cost(CALL_COST);
9787 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9788 ins_encode(form_jmpl(jump_target));
9789 ins_avoid_back_to_back(AVOID_BEFORE);
9790 ins_pipe(tail_call);
9791 %}
9792
9793
9794 // Return Instruction
9795 instruct Ret() %{
9796 match(Return);
9797
9798 // The epilogue node did the ret already.
9799 size(0);
9800 format %{ "! return" %}
9801 ins_encode();
9802 ins_pipe(empty);
9803 %}
9804
9805
9806 // Tail Jump; remove the return address; jump to target.
9807 // TailCall above leaves the return address around.
9808 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9809 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9810 // "restore" before this instruction (in Epilogue), we need to materialize it
9811 // in %i0.
9812 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9813 match( TailJump jump_target ex_oop );
9814 ins_cost(CALL_COST);
9815 format %{ "! discard R_O7\n\t"
9816 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9817 ins_encode(form_jmpl_set_exception_pc(jump_target));
9818 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9819 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9820 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9821 ins_avoid_back_to_back(AVOID_BEFORE);
9822 ins_pipe(tail_call);
9823 %}
9824
9825 // Create exception oop: created by stack-crawling runtime code.
9826 // Created exception is now available to this handler, and is setup
9827 // just prior to jumping to this handler. No code emitted.
9828 instruct CreateException( o0RegP ex_oop )
9829 %{
9830 match(Set ex_oop (CreateEx));
9831 ins_cost(0);
9832
9833 size(0);
9834 // use the following format syntax
9835 format %{ "! exception oop is in R_O0; no code emitted" %}
9836 ins_encode();
9837 ins_pipe(empty);
9838 %}
9839
9840
9841 // Rethrow exception:
9842 // The exception oop will come in the first argument position.
9843 // Then JUMP (not call) to the rethrow stub code.
9844 instruct RethrowException()
9845 %{
9846 match(Rethrow);
9847 ins_cost(CALL_COST);
9848
9849 // use the following format syntax
9850 format %{ "Jmp rethrow_stub" %}
9851 ins_encode(enc_rethrow);
9852 ins_avoid_back_to_back(AVOID_BEFORE);
9853 ins_pipe(tail_call);
9854 %}
9855
9856
9857 // Die now
9858 instruct ShouldNotReachHere( )
9859 %{
9860 match(Halt);
9861 ins_cost(CALL_COST);
9862
9863 size(4);
9864 // Use the following format syntax
9865 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9866 ins_encode( form2_illtrap() );
9867 ins_pipe(tail_call);
9868 %}
9869
9870 // ============================================================================
9871 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9872 // array for an instance of the superklass. Set a hidden internal cache on a
9873 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9874 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9875 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9876 match(Set index (PartialSubtypeCheck sub super));
9877 effect( KILL pcc, KILL o7 );
9878 ins_cost(DEFAULT_COST*10);
9879 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9880 ins_encode( enc_PartialSubtypeCheck() );
9881 ins_avoid_back_to_back(AVOID_BEFORE);
9882 ins_pipe(partial_subtype_check_pipe);
9883 %}
9884
9885 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9886 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9887 effect( KILL idx, KILL o7 );
9888 ins_cost(DEFAULT_COST*10);
9889 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9890 ins_encode( enc_PartialSubtypeCheck() );
9891 ins_avoid_back_to_back(AVOID_BEFORE);
9892 ins_pipe(partial_subtype_check_pipe);
9893 %}
9894
9895
9896 // ============================================================================
9897 // inlined locking and unlocking
9898
9899 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9900 match(Set pcc (FastLock object box));
9901
9902 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9903 ins_cost(100);
9904
9905 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9906 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9907 ins_pipe(long_memory_op);
9908 %}
9909
9910
9911 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9912 match(Set pcc (FastUnlock object box));
9913 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9914 ins_cost(100);
9915
9916 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9917 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9918 ins_pipe(long_memory_op);
9919 %}
9920
9921 // The encodings are generic.
9922 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9923 predicate(!use_block_zeroing(n->in(2)) );
9924 match(Set dummy (ClearArray cnt base));
9925 effect(TEMP temp, KILL ccr);
9926 ins_cost(300);
9927 format %{ "MOV $cnt,$temp\n"
9928 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9929 " BRge loop\t\t! Clearing loop\n"
9930 " STX G0,[$base+$temp]\t! delay slot" %}
9931
9932 ins_encode %{
9933 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9934 Register nof_bytes_arg = $cnt$$Register;
9935 Register nof_bytes_tmp = $temp$$Register;
9936 Register base_pointer_arg = $base$$Register;
9937
9938 Label loop;
9939 __ mov(nof_bytes_arg, nof_bytes_tmp);
9940
9941 // Loop and clear, walking backwards through the array.
9942 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9943 __ bind(loop);
9944 __ deccc(nof_bytes_tmp, 8);
9945 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9946 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9947 // %%%% this mini-loop must not cross a cache boundary!
9948 %}
9949 ins_pipe(long_memory_op);
9950 %}
9951
9952 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
9953 predicate(use_block_zeroing(n->in(2)));
9954 match(Set dummy (ClearArray cnt base));
9955 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
9956 ins_cost(300);
9957 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9958
9959 ins_encode %{
9960
9961 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9962 Register to = $base$$Register;
9963 Register count = $cnt$$Register;
9964
9965 Label Ldone;
9966 __ nop(); // Separate short branches
9967 // Use BIS for zeroing (temp is not used).
9968 __ bis_zeroing(to, count, G0, Ldone);
9969 __ bind(Ldone);
9970
9971 %}
9972 ins_pipe(long_memory_op);
9973 %}
9974
9975 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
9976 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
9977 match(Set dummy (ClearArray cnt base));
9978 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
9979 ins_cost(300);
9980 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9981
9982 ins_encode %{
9983
9984 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9985 Register to = $base$$Register;
9986 Register count = $cnt$$Register;
9987 Register temp = $tmp$$Register;
9988
9989 Label Ldone;
9990 __ nop(); // Separate short branches
9991 // Use BIS for zeroing
9992 __ bis_zeroing(to, count, temp, Ldone);
9993 __ bind(Ldone);
9994
9995 %}
9996 ins_pipe(long_memory_op);
9997 %}
9998
9999 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10000 o7RegI tmp, flagsReg ccr) %{
10001 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10002 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10003 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10004 ins_cost(300);
10005 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10006 ins_encode %{
10007 __ string_compare($str1$$Register, $str2$$Register,
10008 $cnt1$$Register, $cnt2$$Register,
10009 $tmp$$Register, $tmp$$Register,
10010 $result$$Register, StrIntrinsicNode::LL);
10011 %}
10012 ins_pipe(long_memory_op);
10013 %}
10014
10015 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10016 o7RegI tmp, flagsReg ccr) %{
10017 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10018 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10019 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10020 ins_cost(300);
10021 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10022 ins_encode %{
10023 __ string_compare($str1$$Register, $str2$$Register,
10024 $cnt1$$Register, $cnt2$$Register,
10025 $tmp$$Register, $tmp$$Register,
10026 $result$$Register, StrIntrinsicNode::UU);
10027 %}
10028 ins_pipe(long_memory_op);
10029 %}
10030
10031 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10032 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10033 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10034 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10035 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10036 ins_cost(300);
10037 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10038 ins_encode %{
10039 __ string_compare($str1$$Register, $str2$$Register,
10040 $cnt1$$Register, $cnt2$$Register,
10041 $tmp1$$Register, $tmp2$$Register,
10042 $result$$Register, StrIntrinsicNode::LU);
10043 %}
10044 ins_pipe(long_memory_op);
10045 %}
10046
10047 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10048 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10049 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10050 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10051 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10052 ins_cost(300);
10053 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10054 ins_encode %{
10055 __ string_compare($str2$$Register, $str1$$Register,
10056 $cnt2$$Register, $cnt1$$Register,
10057 $tmp1$$Register, $tmp2$$Register,
10058 $result$$Register, StrIntrinsicNode::UL);
10059 %}
10060 ins_pipe(long_memory_op);
10061 %}
10062
10063 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10064 o7RegI tmp, flagsReg ccr) %{
10065 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10066 match(Set result (StrEquals (Binary str1 str2) cnt));
10067 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10068 ins_cost(300);
10069 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10070 ins_encode %{
10071 __ array_equals(false, $str1$$Register, $str2$$Register,
10072 $cnt$$Register, $tmp$$Register,
10073 $result$$Register, true /* byte */);
10074 %}
10075 ins_pipe(long_memory_op);
10076 %}
10077
10078 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10079 o7RegI tmp, flagsReg ccr) %{
10080 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10081 match(Set result (StrEquals (Binary str1 str2) cnt));
10082 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10083 ins_cost(300);
10084 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10085 ins_encode %{
10086 __ array_equals(false, $str1$$Register, $str2$$Register,
10087 $cnt$$Register, $tmp$$Register,
10088 $result$$Register, false /* byte */);
10089 %}
10090 ins_pipe(long_memory_op);
10091 %}
10092
10093 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10094 o7RegI tmp2, flagsReg ccr) %{
10095 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10096 match(Set result (AryEq ary1 ary2));
10097 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10098 ins_cost(300);
10099 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10100 ins_encode %{
10101 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10102 $tmp1$$Register, $tmp2$$Register,
10103 $result$$Register, true /* byte */);
10104 %}
10105 ins_pipe(long_memory_op);
10106 %}
10107
10108 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10109 o7RegI tmp2, flagsReg ccr) %{
10110 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10111 match(Set result (AryEq ary1 ary2));
10112 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10113 ins_cost(300);
10114 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10115 ins_encode %{
10116 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10117 $tmp1$$Register, $tmp2$$Register,
10118 $result$$Register, false /* byte */);
10119 %}
10120 ins_pipe(long_memory_op);
10121 %}
10122
10123 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10124 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10125 flagsReg ccr)
10126 %{
10127 match(Set resultR (HasNegatives pAryR iSizeR));
10128 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10129 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10130 ins_encode %{
10131 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
10132 $resultR$$Register,
10133 $tmp1L$$Register, $tmp2L$$Register,
10134 $tmp3L$$Register, $tmp4L$$Register);
10135 %}
10136 ins_pipe(long_memory_op);
10137 %}
10138
10139 // char[] to byte[] compression
10140 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10141 predicate(UseVIS < 3);
10142 match(Set result (StrCompressedCopy src (Binary dst len)));
10143 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10144 ins_cost(300);
10145 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10146 ins_encode %{
10147 Label Ldone;
10148 __ signx($len$$Register);
10149 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10150 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10151 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10152 __ bind(Ldone);
10153 %}
10154 ins_pipe(long_memory_op);
10155 %}
10156
10157 // fast char[] to byte[] compression using VIS instructions
10158 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10159 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10160 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10161 predicate(UseVIS >= 3);
10162 match(Set result (StrCompressedCopy src (Binary dst len)));
10163 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10164 ins_cost(300);
10165 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10166 ins_encode %{
10167 Label Ldone;
10168 __ signx($len$$Register);
10169 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10170 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10171 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10172 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10173 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10174 __ bind(Ldone);
10175 %}
10176 ins_pipe(long_memory_op);
10177 %}
10178
10179 // byte[] to char[] inflation
10180 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10181 iRegL tmp, flagsReg ccr) %{
10182 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10183 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10184 ins_cost(300);
10185 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10186 ins_encode %{
10187 Label Ldone;
10188 __ signx($len$$Register);
10189 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10190 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10191 __ bind(Ldone);
10192 %}
10193 ins_pipe(long_memory_op);
10194 %}
10195
10196 // fast byte[] to char[] inflation using VIS instructions
10197 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10198 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10199 predicate(UseVIS >= 3);
10200 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10201 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10202 ins_cost(300);
10203 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10204 ins_encode %{
10205 Label Ldone;
10206 __ signx($len$$Register);
10207 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10208 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10209 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10210 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10211 __ bind(Ldone);
10212 %}
10213 ins_pipe(long_memory_op);
10214 %}
10215
10216
10217 //---------- Zeros Count Instructions ------------------------------------------
10218
10219 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10220 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10221 match(Set dst (CountLeadingZerosI src));
10222 effect(TEMP dst, TEMP tmp, KILL cr);
10223
10224 // x |= (x >> 1);
10225 // x |= (x >> 2);
10226 // x |= (x >> 4);
10227 // x |= (x >> 8);
10228 // x |= (x >> 16);
10229 // return (WORDBITS - popc(x));
10230 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10231 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10232 "OR $dst,$tmp,$dst\n\t"
10233 "SRL $dst,2,$tmp\n\t"
10234 "OR $dst,$tmp,$dst\n\t"
10235 "SRL $dst,4,$tmp\n\t"
10236 "OR $dst,$tmp,$dst\n\t"
10237 "SRL $dst,8,$tmp\n\t"
10238 "OR $dst,$tmp,$dst\n\t"
10239 "SRL $dst,16,$tmp\n\t"
10240 "OR $dst,$tmp,$dst\n\t"
10241 "POPC $dst,$dst\n\t"
10242 "MOV 32,$tmp\n\t"
10243 "SUB $tmp,$dst,$dst" %}
10244 ins_encode %{
10245 Register Rdst = $dst$$Register;
10246 Register Rsrc = $src$$Register;
10247 Register Rtmp = $tmp$$Register;
10248 __ srl(Rsrc, 1, Rtmp);
10249 __ srl(Rsrc, 0, Rdst);
10250 __ or3(Rdst, Rtmp, Rdst);
10251 __ srl(Rdst, 2, Rtmp);
10252 __ or3(Rdst, Rtmp, Rdst);
10253 __ srl(Rdst, 4, Rtmp);
10254 __ or3(Rdst, Rtmp, Rdst);
10255 __ srl(Rdst, 8, Rtmp);
10256 __ or3(Rdst, Rtmp, Rdst);
10257 __ srl(Rdst, 16, Rtmp);
10258 __ or3(Rdst, Rtmp, Rdst);
10259 __ popc(Rdst, Rdst);
10260 __ mov(BitsPerInt, Rtmp);
10261 __ sub(Rtmp, Rdst, Rdst);
10262 %}
10263 ins_pipe(ialu_reg);
10264 %}
10265
10266 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10267 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10268 match(Set dst (CountLeadingZerosL src));
10269 effect(TEMP dst, TEMP tmp, KILL cr);
10270
10271 // x |= (x >> 1);
10272 // x |= (x >> 2);
10273 // x |= (x >> 4);
10274 // x |= (x >> 8);
10275 // x |= (x >> 16);
10276 // x |= (x >> 32);
10277 // return (WORDBITS - popc(x));
10278 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10279 "OR $src,$tmp,$dst\n\t"
10280 "SRLX $dst,2,$tmp\n\t"
10281 "OR $dst,$tmp,$dst\n\t"
10282 "SRLX $dst,4,$tmp\n\t"
10283 "OR $dst,$tmp,$dst\n\t"
10284 "SRLX $dst,8,$tmp\n\t"
10285 "OR $dst,$tmp,$dst\n\t"
10286 "SRLX $dst,16,$tmp\n\t"
10287 "OR $dst,$tmp,$dst\n\t"
10288 "SRLX $dst,32,$tmp\n\t"
10289 "OR $dst,$tmp,$dst\n\t"
10290 "POPC $dst,$dst\n\t"
10291 "MOV 64,$tmp\n\t"
10292 "SUB $tmp,$dst,$dst" %}
10293 ins_encode %{
10294 Register Rdst = $dst$$Register;
10295 Register Rsrc = $src$$Register;
10296 Register Rtmp = $tmp$$Register;
10297 __ srlx(Rsrc, 1, Rtmp);
10298 __ or3( Rsrc, Rtmp, Rdst);
10299 __ srlx(Rdst, 2, Rtmp);
10300 __ or3( Rdst, Rtmp, Rdst);
10301 __ srlx(Rdst, 4, Rtmp);
10302 __ or3( Rdst, Rtmp, Rdst);
10303 __ srlx(Rdst, 8, Rtmp);
10304 __ or3( Rdst, Rtmp, Rdst);
10305 __ srlx(Rdst, 16, Rtmp);
10306 __ or3( Rdst, Rtmp, Rdst);
10307 __ srlx(Rdst, 32, Rtmp);
10308 __ or3( Rdst, Rtmp, Rdst);
10309 __ popc(Rdst, Rdst);
10310 __ mov(BitsPerLong, Rtmp);
10311 __ sub(Rtmp, Rdst, Rdst);
10312 %}
10313 ins_pipe(ialu_reg);
10314 %}
10315
10316 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10317 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10318 match(Set dst (CountTrailingZerosI src));
10319 effect(TEMP dst, KILL cr);
10320
10321 // return popc(~x & (x - 1));
10322 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10323 "ANDN $dst,$src,$dst\n\t"
10324 "SRL $dst,R_G0,$dst\n\t"
10325 "POPC $dst,$dst" %}
10326 ins_encode %{
10327 Register Rdst = $dst$$Register;
10328 Register Rsrc = $src$$Register;
10329 __ sub(Rsrc, 1, Rdst);
10330 __ andn(Rdst, Rsrc, Rdst);
10331 __ srl(Rdst, G0, Rdst);
10332 __ popc(Rdst, Rdst);
10333 %}
10334 ins_pipe(ialu_reg);
10335 %}
10336
10337 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10338 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10339 match(Set dst (CountTrailingZerosL src));
10340 effect(TEMP dst, KILL cr);
10341
10342 // return popc(~x & (x - 1));
10343 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10344 "ANDN $dst,$src,$dst\n\t"
10345 "POPC $dst,$dst" %}
10346 ins_encode %{
10347 Register Rdst = $dst$$Register;
10348 Register Rsrc = $src$$Register;
10349 __ sub(Rsrc, 1, Rdst);
10350 __ andn(Rdst, Rsrc, Rdst);
10351 __ popc(Rdst, Rdst);
10352 %}
10353 ins_pipe(ialu_reg);
10354 %}
10355
10356
10357 //---------- Population Count Instructions -------------------------------------
10358
10359 instruct popCountI(iRegIsafe dst, iRegI src) %{
10360 predicate(UsePopCountInstruction);
10361 match(Set dst (PopCountI src));
10362
10363 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10364 "POPC $dst, $dst" %}
10365 ins_encode %{
10366 __ srl($src$$Register, G0, $dst$$Register);
10367 __ popc($dst$$Register, $dst$$Register);
10368 %}
10369 ins_pipe(ialu_reg);
10370 %}
10371
10372 // Note: Long.bitCount(long) returns an int.
10373 instruct popCountL(iRegIsafe dst, iRegL src) %{
10374 predicate(UsePopCountInstruction);
10375 match(Set dst (PopCountL src));
10376
10377 format %{ "POPC $src, $dst" %}
10378 ins_encode %{
10379 __ popc($src$$Register, $dst$$Register);
10380 %}
10381 ins_pipe(ialu_reg);
10382 %}
10383
10384
10385 // ============================================================================
10386 //------------Bytes reverse--------------------------------------------------
10387
10388 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10389 match(Set dst (ReverseBytesI src));
10390
10391 // Op cost is artificially doubled to make sure that load or store
10392 // instructions are preferred over this one which requires a spill
10393 // onto a stack slot.
10394 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10395 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10396
10397 ins_encode %{
10398 __ set($src$$disp + STACK_BIAS, O7);
10399 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10400 %}
10401 ins_pipe( iload_mem );
10402 %}
10403
10404 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10405 match(Set dst (ReverseBytesL src));
10406
10407 // Op cost is artificially doubled to make sure that load or store
10408 // instructions are preferred over this one which requires a spill
10409 // onto a stack slot.
10410 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10411 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10412
10413 ins_encode %{
10414 __ set($src$$disp + STACK_BIAS, O7);
10415 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10416 %}
10417 ins_pipe( iload_mem );
10418 %}
10419
10420 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10421 match(Set dst (ReverseBytesUS src));
10422
10423 // Op cost is artificially doubled to make sure that load or store
10424 // instructions are preferred over this one which requires a spill
10425 // onto a stack slot.
10426 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10427 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10428
10429 ins_encode %{
10430 // the value was spilled as an int so bias the load
10431 __ set($src$$disp + STACK_BIAS + 2, O7);
10432 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10433 %}
10434 ins_pipe( iload_mem );
10435 %}
10436
10437 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10438 match(Set dst (ReverseBytesS src));
10439
10440 // Op cost is artificially doubled to make sure that load or store
10441 // instructions are preferred over this one which requires a spill
10442 // onto a stack slot.
10443 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10444 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10445
10446 ins_encode %{
10447 // the value was spilled as an int so bias the load
10448 __ set($src$$disp + STACK_BIAS + 2, O7);
10449 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10450 %}
10451 ins_pipe( iload_mem );
10452 %}
10453
10454 // Load Integer reversed byte order
10455 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10456 match(Set dst (ReverseBytesI (LoadI src)));
10457
10458 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10459 size(4);
10460 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10461
10462 ins_encode %{
10463 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10464 %}
10465 ins_pipe(iload_mem);
10466 %}
10467
10468 // Load Long - aligned and reversed
10469 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10470 match(Set dst (ReverseBytesL (LoadL src)));
10471
10472 ins_cost(MEMORY_REF_COST);
10473 size(4);
10474 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10475
10476 ins_encode %{
10477 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10478 %}
10479 ins_pipe(iload_mem);
10480 %}
10481
10482 // Load unsigned short / char reversed byte order
10483 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10484 match(Set dst (ReverseBytesUS (LoadUS src)));
10485
10486 ins_cost(MEMORY_REF_COST);
10487 size(4);
10488 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10489
10490 ins_encode %{
10491 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10492 %}
10493 ins_pipe(iload_mem);
10494 %}
10495
10496 // Load short reversed byte order
10497 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10498 match(Set dst (ReverseBytesS (LoadS src)));
10499
10500 ins_cost(MEMORY_REF_COST);
10501 size(4);
10502 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10503
10504 ins_encode %{
10505 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10506 %}
10507 ins_pipe(iload_mem);
10508 %}
10509
10510 // Store Integer reversed byte order
10511 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10512 match(Set dst (StoreI dst (ReverseBytesI src)));
10513
10514 ins_cost(MEMORY_REF_COST);
10515 size(4);
10516 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10517
10518 ins_encode %{
10519 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10520 %}
10521 ins_pipe(istore_mem_reg);
10522 %}
10523
10524 // Store Long reversed byte order
10525 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10526 match(Set dst (StoreL dst (ReverseBytesL src)));
10527
10528 ins_cost(MEMORY_REF_COST);
10529 size(4);
10530 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10531
10532 ins_encode %{
10533 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10534 %}
10535 ins_pipe(istore_mem_reg);
10536 %}
10537
10538 // Store unsighed short/char reversed byte order
10539 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10540 match(Set dst (StoreC dst (ReverseBytesUS src)));
10541
10542 ins_cost(MEMORY_REF_COST);
10543 size(4);
10544 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10545
10546 ins_encode %{
10547 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10548 %}
10549 ins_pipe(istore_mem_reg);
10550 %}
10551
10552 // Store short reversed byte order
10553 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10554 match(Set dst (StoreC dst (ReverseBytesS src)));
10555
10556 ins_cost(MEMORY_REF_COST);
10557 size(4);
10558 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10559
10560 ins_encode %{
10561 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10562 %}
10563 ins_pipe(istore_mem_reg);
10564 %}
10565
10566 // ====================VECTOR INSTRUCTIONS=====================================
10567
10568 // Load Aligned Packed values into a Double Register
10569 instruct loadV8(regD dst, memory mem) %{
10570 predicate(n->as_LoadVector()->memory_size() == 8);
10571 match(Set dst (LoadVector mem));
10572 ins_cost(MEMORY_REF_COST);
10573 size(4);
10574 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10575 ins_encode %{
10576 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10577 %}
10578 ins_pipe(floadD_mem);
10579 %}
10580
10581 // Store Vector in Double register to memory
10582 instruct storeV8(memory mem, regD src) %{
10583 predicate(n->as_StoreVector()->memory_size() == 8);
10584 match(Set mem (StoreVector mem src));
10585 ins_cost(MEMORY_REF_COST);
10586 size(4);
10587 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10588 ins_encode %{
10589 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10590 %}
10591 ins_pipe(fstoreD_mem_reg);
10592 %}
10593
10594 // Store Zero into vector in memory
10595 instruct storeV8B_zero(memory mem, immI0 zero) %{
10596 predicate(n->as_StoreVector()->memory_size() == 8);
10597 match(Set mem (StoreVector mem (ReplicateB zero)));
10598 ins_cost(MEMORY_REF_COST);
10599 size(4);
10600 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10601 ins_encode %{
10602 __ stx(G0, $mem$$Address);
10603 %}
10604 ins_pipe(fstoreD_mem_zero);
10605 %}
10606
10607 instruct storeV4S_zero(memory mem, immI0 zero) %{
10608 predicate(n->as_StoreVector()->memory_size() == 8);
10609 match(Set mem (StoreVector mem (ReplicateS zero)));
10610 ins_cost(MEMORY_REF_COST);
10611 size(4);
10612 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10613 ins_encode %{
10614 __ stx(G0, $mem$$Address);
10615 %}
10616 ins_pipe(fstoreD_mem_zero);
10617 %}
10618
10619 instruct storeV2I_zero(memory mem, immI0 zero) %{
10620 predicate(n->as_StoreVector()->memory_size() == 8);
10621 match(Set mem (StoreVector mem (ReplicateI zero)));
10622 ins_cost(MEMORY_REF_COST);
10623 size(4);
10624 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10625 ins_encode %{
10626 __ stx(G0, $mem$$Address);
10627 %}
10628 ins_pipe(fstoreD_mem_zero);
10629 %}
10630
10631 instruct storeV2F_zero(memory mem, immF0 zero) %{
10632 predicate(n->as_StoreVector()->memory_size() == 8);
10633 match(Set mem (StoreVector mem (ReplicateF zero)));
10634 ins_cost(MEMORY_REF_COST);
10635 size(4);
10636 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10637 ins_encode %{
10638 __ stx(G0, $mem$$Address);
10639 %}
10640 ins_pipe(fstoreD_mem_zero);
10641 %}
10642
10643 // Replicate scalar to packed byte values into Double register
10644 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10645 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10646 match(Set dst (ReplicateB src));
10647 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10648 format %{ "SLLX $src,56,$tmp\n\t"
10649 "SRLX $tmp, 8,$tmp2\n\t"
10650 "OR $tmp,$tmp2,$tmp\n\t"
10651 "SRLX $tmp,16,$tmp2\n\t"
10652 "OR $tmp,$tmp2,$tmp\n\t"
10653 "SRLX $tmp,32,$tmp2\n\t"
10654 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10655 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10656 ins_encode %{
10657 Register Rsrc = $src$$Register;
10658 Register Rtmp = $tmp$$Register;
10659 Register Rtmp2 = $tmp2$$Register;
10660 __ sllx(Rsrc, 56, Rtmp);
10661 __ srlx(Rtmp, 8, Rtmp2);
10662 __ or3 (Rtmp, Rtmp2, Rtmp);
10663 __ srlx(Rtmp, 16, Rtmp2);
10664 __ or3 (Rtmp, Rtmp2, Rtmp);
10665 __ srlx(Rtmp, 32, Rtmp2);
10666 __ or3 (Rtmp, Rtmp2, Rtmp);
10667 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10668 %}
10669 ins_pipe(ialu_reg);
10670 %}
10671
10672 // Replicate scalar to packed byte values into Double stack
10673 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10674 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10675 match(Set dst (ReplicateB src));
10676 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10677 format %{ "SLLX $src,56,$tmp\n\t"
10678 "SRLX $tmp, 8,$tmp2\n\t"
10679 "OR $tmp,$tmp2,$tmp\n\t"
10680 "SRLX $tmp,16,$tmp2\n\t"
10681 "OR $tmp,$tmp2,$tmp\n\t"
10682 "SRLX $tmp,32,$tmp2\n\t"
10683 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10684 "STX $tmp,$dst\t! regL to stkD" %}
10685 ins_encode %{
10686 Register Rsrc = $src$$Register;
10687 Register Rtmp = $tmp$$Register;
10688 Register Rtmp2 = $tmp2$$Register;
10689 __ sllx(Rsrc, 56, Rtmp);
10690 __ srlx(Rtmp, 8, Rtmp2);
10691 __ or3 (Rtmp, Rtmp2, Rtmp);
10692 __ srlx(Rtmp, 16, Rtmp2);
10693 __ or3 (Rtmp, Rtmp2, Rtmp);
10694 __ srlx(Rtmp, 32, Rtmp2);
10695 __ or3 (Rtmp, Rtmp2, Rtmp);
10696 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10697 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10698 %}
10699 ins_pipe(ialu_reg);
10700 %}
10701
10702 // Replicate scalar constant to packed byte values in Double register
10703 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10704 predicate(n->as_Vector()->length() == 8);
10705 match(Set dst (ReplicateB con));
10706 effect(KILL tmp);
10707 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10708 ins_encode %{
10709 // XXX This is a quick fix for 6833573.
10710 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10711 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10712 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10713 %}
10714 ins_pipe(loadConFD);
10715 %}
10716
10717 // Replicate scalar to packed char/short values into Double register
10718 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10719 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10720 match(Set dst (ReplicateS src));
10721 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10722 format %{ "SLLX $src,48,$tmp\n\t"
10723 "SRLX $tmp,16,$tmp2\n\t"
10724 "OR $tmp,$tmp2,$tmp\n\t"
10725 "SRLX $tmp,32,$tmp2\n\t"
10726 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10727 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10728 ins_encode %{
10729 Register Rsrc = $src$$Register;
10730 Register Rtmp = $tmp$$Register;
10731 Register Rtmp2 = $tmp2$$Register;
10732 __ sllx(Rsrc, 48, Rtmp);
10733 __ srlx(Rtmp, 16, Rtmp2);
10734 __ or3 (Rtmp, Rtmp2, Rtmp);
10735 __ srlx(Rtmp, 32, Rtmp2);
10736 __ or3 (Rtmp, Rtmp2, Rtmp);
10737 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10738 %}
10739 ins_pipe(ialu_reg);
10740 %}
10741
10742 // Replicate scalar to packed char/short values into Double stack
10743 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10744 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10745 match(Set dst (ReplicateS src));
10746 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10747 format %{ "SLLX $src,48,$tmp\n\t"
10748 "SRLX $tmp,16,$tmp2\n\t"
10749 "OR $tmp,$tmp2,$tmp\n\t"
10750 "SRLX $tmp,32,$tmp2\n\t"
10751 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10752 "STX $tmp,$dst\t! regL to stkD" %}
10753 ins_encode %{
10754 Register Rsrc = $src$$Register;
10755 Register Rtmp = $tmp$$Register;
10756 Register Rtmp2 = $tmp2$$Register;
10757 __ sllx(Rsrc, 48, Rtmp);
10758 __ srlx(Rtmp, 16, Rtmp2);
10759 __ or3 (Rtmp, Rtmp2, Rtmp);
10760 __ srlx(Rtmp, 32, Rtmp2);
10761 __ or3 (Rtmp, Rtmp2, Rtmp);
10762 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10763 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10764 %}
10765 ins_pipe(ialu_reg);
10766 %}
10767
10768 // Replicate scalar constant to packed char/short values in Double register
10769 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10770 predicate(n->as_Vector()->length() == 4);
10771 match(Set dst (ReplicateS con));
10772 effect(KILL tmp);
10773 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10774 ins_encode %{
10775 // XXX This is a quick fix for 6833573.
10776 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10777 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10778 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10779 %}
10780 ins_pipe(loadConFD);
10781 %}
10782
10783 // Replicate scalar to packed int values into Double register
10784 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10785 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10786 match(Set dst (ReplicateI src));
10787 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10788 format %{ "SLLX $src,32,$tmp\n\t"
10789 "SRLX $tmp,32,$tmp2\n\t"
10790 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10791 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10792 ins_encode %{
10793 Register Rsrc = $src$$Register;
10794 Register Rtmp = $tmp$$Register;
10795 Register Rtmp2 = $tmp2$$Register;
10796 __ sllx(Rsrc, 32, Rtmp);
10797 __ srlx(Rtmp, 32, Rtmp2);
10798 __ or3 (Rtmp, Rtmp2, Rtmp);
10799 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10800 %}
10801 ins_pipe(ialu_reg);
10802 %}
10803
10804 // Replicate scalar to packed int values into Double stack
10805 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10806 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10807 match(Set dst (ReplicateI src));
10808 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10809 format %{ "SLLX $src,32,$tmp\n\t"
10810 "SRLX $tmp,32,$tmp2\n\t"
10811 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10812 "STX $tmp,$dst\t! regL to stkD" %}
10813 ins_encode %{
10814 Register Rsrc = $src$$Register;
10815 Register Rtmp = $tmp$$Register;
10816 Register Rtmp2 = $tmp2$$Register;
10817 __ sllx(Rsrc, 32, Rtmp);
10818 __ srlx(Rtmp, 32, Rtmp2);
10819 __ or3 (Rtmp, Rtmp2, Rtmp);
10820 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10821 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10822 %}
10823 ins_pipe(ialu_reg);
10824 %}
10825
10826 // Replicate scalar zero constant to packed int values in Double register
10827 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10828 predicate(n->as_Vector()->length() == 2);
10829 match(Set dst (ReplicateI con));
10830 effect(KILL tmp);
10831 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10832 ins_encode %{
10833 // XXX This is a quick fix for 6833573.
10834 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10835 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10836 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10837 %}
10838 ins_pipe(loadConFD);
10839 %}
10840
10841 // Replicate scalar to packed float values into Double stack
10842 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10843 predicate(n->as_Vector()->length() == 2);
10844 match(Set dst (ReplicateF src));
10845 ins_cost(MEMORY_REF_COST*2);
10846 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10847 "STF $src,$dst.lo" %}
10848 opcode(Assembler::stf_op3);
10849 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10850 ins_pipe(fstoreF_stk_reg);
10851 %}
10852
10853 // Replicate scalar zero constant to packed float values in Double register
10854 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10855 predicate(n->as_Vector()->length() == 2);
10856 match(Set dst (ReplicateF con));
10857 effect(KILL tmp);
10858 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10859 ins_encode %{
10860 // XXX This is a quick fix for 6833573.
10861 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10862 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10863 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10864 %}
10865 ins_pipe(loadConFD);
10866 %}
10867
10868 //----------PEEPHOLE RULES-----------------------------------------------------
10869 // These must follow all instruction definitions as they use the names
10870 // defined in the instructions definitions.
10871 //
10872 // peepmatch ( root_instr_name [preceding_instruction]* );
10873 //
10874 // peepconstraint %{
10875 // (instruction_number.operand_name relational_op instruction_number.operand_name
10876 // [, ...] );
10877 // // instruction numbers are zero-based using left to right order in peepmatch
10878 //
10879 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10880 // // provide an instruction_number.operand_name for each operand that appears
10881 // // in the replacement instruction's match rule
10882 //
10883 // ---------VM FLAGS---------------------------------------------------------
10884 //
10885 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10886 //
10887 // Each peephole rule is given an identifying number starting with zero and
10888 // increasing by one in the order seen by the parser. An individual peephole
10889 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10890 // on the command-line.
10891 //
10892 // ---------CURRENT LIMITATIONS----------------------------------------------
10893 //
10894 // Only match adjacent instructions in same basic block
10895 // Only equality constraints
10896 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10897 // Only one replacement instruction
10898 //
10899 // ---------EXAMPLE----------------------------------------------------------
10900 //
10901 // // pertinent parts of existing instructions in architecture description
10902 // instruct movI(eRegI dst, eRegI src) %{
10903 // match(Set dst (CopyI src));
10904 // %}
10905 //
10906 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10907 // match(Set dst (AddI dst src));
10908 // effect(KILL cr);
10909 // %}
10910 //
10911 // // Change (inc mov) to lea
10912 // peephole %{
10913 // // increment preceeded by register-register move
10914 // peepmatch ( incI_eReg movI );
10915 // // require that the destination register of the increment
10916 // // match the destination register of the move
10917 // peepconstraint ( 0.dst == 1.dst );
10918 // // construct a replacement instruction that sets
10919 // // the destination to ( move's source register + one )
10920 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10921 // %}
10922 //
10923
10924 // // Change load of spilled value to only a spill
10925 // instruct storeI(memory mem, eRegI src) %{
10926 // match(Set mem (StoreI mem src));
10927 // %}
10928 //
10929 // instruct loadI(eRegI dst, memory mem) %{
10930 // match(Set dst (LoadI mem));
10931 // %}
10932 //
10933 // peephole %{
10934 // peepmatch ( loadI storeI );
10935 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10936 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10937 // %}
10938
10939 //----------SMARTSPILL RULES---------------------------------------------------
10940 // These must follow all instruction definitions as they use the names
10941 // defined in the instructions definitions.
10942 //
10943 // SPARC will probably not have any of these rules due to RISC instruction set.
10944
10945 //----------PIPELINE-----------------------------------------------------------
10946 // Rules which define the behavior of the target architectures pipeline.