1 /* 2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "vmreg_x86.inline.hpp" 42 43 44 // These masks are used to provide 128-bit aligned bitmasks to the XMM 45 // instructions, to allow sign-masking or sign-bit flipping. They allow 46 // fast versions of NegF/NegD and AbsF/AbsD. 47 48 // Note: 'double' and 'long long' have 32-bits alignment on x86. 49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 51 // of 128-bits operands for SSE instructions. 52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 53 // Store the value to a 128-bits operand. 54 operand[0] = lo; 55 operand[1] = hi; 56 return operand; 57 } 58 59 // Buffer for 128-bits masks used by SSE instructions. 60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 61 62 // Static initialization during VM startup. 63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 67 68 69 70 NEEDS_CLEANUP // remove this definitions ? 71 const Register IC_Klass = rax; // where the IC klass is cached 72 const Register SYNC_header = rax; // synchronization header 73 const Register SHIFT_count = rcx; // where count for shift operations must be 74 75 #define __ _masm-> 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2) { 82 if (tmp1 == preserve) { 83 assert_different_registers(tmp1, tmp2, extra); 84 tmp1 = extra; 85 } else if (tmp2 == preserve) { 86 assert_different_registers(tmp1, tmp2, extra); 87 tmp2 = extra; 88 } 89 assert_different_registers(preserve, tmp1, tmp2); 90 } 91 92 93 94 static void select_different_registers(Register preserve, 95 Register extra, 96 Register &tmp1, 97 Register &tmp2, 98 Register &tmp3) { 99 if (tmp1 == preserve) { 100 assert_different_registers(tmp1, tmp2, tmp3, extra); 101 tmp1 = extra; 102 } else if (tmp2 == preserve) { 103 assert_different_registers(tmp1, tmp2, tmp3, extra); 104 tmp2 = extra; 105 } else if (tmp3 == preserve) { 106 assert_different_registers(tmp1, tmp2, tmp3, extra); 107 tmp3 = extra; 108 } 109 assert_different_registers(preserve, tmp1, tmp2, tmp3); 110 } 111 112 113 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 115 if (opr->is_constant()) { 116 LIR_Const* constant = opr->as_constant_ptr(); 117 switch (constant->type()) { 118 case T_INT: { 119 return true; 120 } 121 122 default: 123 return false; 124 } 125 } 126 return false; 127 } 128 129 130 LIR_Opr LIR_Assembler::receiverOpr() { 131 return FrameMap::receiver_opr; 132 } 133 134 LIR_Opr LIR_Assembler::osrBufferPointer() { 135 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 136 } 137 138 //--------------fpu register translations----------------------- 139 140 141 address LIR_Assembler::float_constant(float f) { 142 address const_addr = __ float_constant(f); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 address LIR_Assembler::double_constant(double d) { 153 address const_addr = __ double_constant(d); 154 if (const_addr == NULL) { 155 bailout("const section overflow"); 156 return __ code()->consts()->start(); 157 } else { 158 return const_addr; 159 } 160 } 161 162 163 void LIR_Assembler::set_24bit_FPU() { 164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 165 } 166 167 void LIR_Assembler::reset_FPU() { 168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 169 } 170 171 void LIR_Assembler::fpop() { 172 __ fpop(); 173 } 174 175 void LIR_Assembler::fxch(int i) { 176 __ fxch(i); 177 } 178 179 void LIR_Assembler::fld(int i) { 180 __ fld_s(i); 181 } 182 183 void LIR_Assembler::ffree(int i) { 184 __ ffree(i); 185 } 186 187 void LIR_Assembler::breakpoint() { 188 __ int3(); 189 } 190 191 void LIR_Assembler::push(LIR_Opr opr) { 192 if (opr->is_single_cpu()) { 193 __ push_reg(opr->as_register()); 194 } else if (opr->is_double_cpu()) { 195 NOT_LP64(__ push_reg(opr->as_register_hi())); 196 __ push_reg(opr->as_register_lo()); 197 } else if (opr->is_stack()) { 198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 199 } else if (opr->is_constant()) { 200 LIR_Const* const_opr = opr->as_constant_ptr(); 201 if (const_opr->type() == T_OBJECT) { 202 __ push_oop(const_opr->as_jobject()); 203 } else if (const_opr->type() == T_INT) { 204 __ push_jint(const_opr->as_jint()); 205 } else { 206 ShouldNotReachHere(); 207 } 208 209 } else { 210 ShouldNotReachHere(); 211 } 212 } 213 214 void LIR_Assembler::pop(LIR_Opr opr) { 215 if (opr->is_single_cpu()) { 216 __ pop_reg(opr->as_register()); 217 } else { 218 ShouldNotReachHere(); 219 } 220 } 221 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 223 return addr->base()->is_illegal() && addr->index()->is_illegal(); 224 } 225 226 //------------------------------------------- 227 228 Address LIR_Assembler::as_Address(LIR_Address* addr) { 229 return as_Address(addr, rscratch1); 230 } 231 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 233 if (addr->base()->is_illegal()) { 234 assert(addr->index()->is_illegal(), "must be illegal too"); 235 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 236 if (! __ reachable(laddr)) { 237 __ movptr(tmp, laddr.addr()); 238 Address res(tmp, 0); 239 return res; 240 } else { 241 return __ as_Address(laddr); 242 } 243 } 244 245 Register base = addr->base()->as_pointer_register(); 246 247 if (addr->index()->is_illegal()) { 248 return Address( base, addr->disp()); 249 } else if (addr->index()->is_cpu_register()) { 250 Register index = addr->index()->as_pointer_register(); 251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 252 } else if (addr->index()->is_constant()) { 253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 254 assert(Assembler::is_simm32(addr_offset), "must be"); 255 256 return Address(base, addr_offset); 257 } else { 258 Unimplemented(); 259 return Address(); 260 } 261 } 262 263 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 265 Address base = as_Address(addr); 266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 267 } 268 269 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 271 return as_Address(addr); 272 } 273 274 275 void LIR_Assembler::osr_entry() { 276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 277 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 278 ValueStack* entry_state = osr_entry->state(); 279 int number_of_locks = entry_state->locks_size(); 280 281 // we jump here if osr happens with the interpreter 282 // state set up to continue at the beginning of the 283 // loop that triggered osr - in particular, we have 284 // the following registers setup: 285 // 286 // rcx: osr buffer 287 // 288 289 // build frame 290 ciMethod* m = compilation()->method(); 291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 292 293 // OSR buffer is 294 // 295 // locals[nlocals-1..0] 296 // monitors[0..number_of_locks] 297 // 298 // locals is a direct copy of the interpreter frame so in the osr buffer 299 // so first slot in the local array is the last local from the interpreter 300 // and last slot is local[0] (receiver) from the interpreter 301 // 302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 304 // in the interpreter frame (the method lock if a sync method) 305 306 // Initialize monitors in the compiled activation. 307 // rcx: pointer to osr buffer 308 // 309 // All other registers are dead at this point and the locals will be 310 // copied into place by code emitted in the IR. 311 312 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 314 int monitor_offset = BytesPerWord * method()->max_locals() + 315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 317 // the OSR buffer using 2 word entries: first the lock and then 318 // the oop. 319 for (int i = 0; i < number_of_locks; i++) { 320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 321 #ifdef ASSERT 322 // verify the interpreter's monitor has a non-null object 323 { 324 Label L; 325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 326 __ jcc(Assembler::notZero, L); 327 __ stop("locked object is NULL"); 328 __ bind(L); 329 } 330 #endif 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 334 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 335 } 336 } 337 } 338 339 340 // inline cache check; done before the frame is built. 341 int LIR_Assembler::check_icache() { 342 Register receiver = FrameMap::receiver_opr->as_register(); 343 Register ic_klass = IC_Klass; 344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 346 if (!do_post_padding) { 347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 349 } 350 int offset = __ offset(); 351 __ inline_cache_check(receiver, IC_Klass); 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353 if (do_post_padding) { 354 // force alignment after the cache check. 355 // It's been verified to be aligned if !VerifyOops 356 __ align(CodeEntryAlignment); 357 } 358 return offset; 359 } 360 361 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363 jobject o = NULL; 364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 365 __ movoop(reg, o); 366 patching_epilog(patch, lir_patch_normal, reg, info); 367 } 368 369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 370 Metadata* o = NULL; 371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 372 __ mov_metadata(reg, o); 373 patching_epilog(patch, lir_patch_normal, reg, info); 374 } 375 376 // This specifies the rsp decrement needed to build the frame 377 int LIR_Assembler::initial_frame_size_in_bytes() const { 378 // if rounding, must let FrameMap know! 379 380 // The frame_map records size in slots (32bit word) 381 382 // subtract two words to account for return address and link 383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 384 } 385 386 387 int LIR_Assembler::emit_exception_handler() { 388 // if the last instruction is a call (typically to do a throw which 389 // is coming at the end after block reordering) the return address 390 // must still point into the code area in order to avoid assertion 391 // failures when searching for the corresponding bci => add a nop 392 // (was bug 5/14/1999 - gri) 393 __ nop(); 394 395 // generate code for exception handler 396 address handler_base = __ start_a_stub(exception_handler_size()); 397 if (handler_base == NULL) { 398 // not enough space left for the handler 399 bailout("exception handler overflow"); 400 return -1; 401 } 402 403 int offset = code_offset(); 404 405 // the exception oop and pc are in rax, and rdx 406 // no other registers need to be preserved, so invalidate them 407 __ invalidate_registers(false, true, true, false, true, true); 408 409 // check that there is really an exception 410 __ verify_not_null_oop(rax); 411 412 // search an exception handler (rax: exception oop, rdx: throwing pc) 413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 414 __ should_not_reach_here(); 415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 416 __ end_a_stub(); 417 418 return offset; 419 } 420 421 422 // Emit the code to remove the frame from the stack in the exception 423 // unwind path. 424 int LIR_Assembler::emit_unwind_handler() { 425 #ifndef PRODUCT 426 if (CommentedAssembly) { 427 _masm->block_comment("Unwind handler"); 428 } 429 #endif 430 431 int offset = code_offset(); 432 433 // Fetch the exception from TLS and clear out exception related thread state 434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 435 NOT_LP64(__ get_thread(rsi)); 436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 439 440 __ bind(_unwind_handler_entry); 441 __ verify_not_null_oop(rax); 442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 444 } 445 446 // Preform needed unlocking 447 MonitorExitStub* stub = NULL; 448 if (method()->is_synchronized()) { 449 monitor_address(0, FrameMap::rax_opr); 450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 451 __ unlock_object(rdi, rsi, rax, *stub->entry()); 452 __ bind(*stub->continuation()); 453 } 454 455 if (compilation()->env()->dtrace_method_probes()) { 456 #ifdef _LP64 457 __ mov(rdi, r15_thread); 458 __ mov_metadata(rsi, method()->constant_encoding()); 459 #else 460 __ get_thread(rax); 461 __ movptr(Address(rsp, 0), rax); 462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 463 #endif 464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 465 } 466 467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 468 __ mov(rax, rbx); // Restore the exception 469 } 470 471 // remove the activation and dispatch to the unwind handler 472 __ remove_frame(initial_frame_size_in_bytes()); 473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 474 475 // Emit the slow path assembly 476 if (stub != NULL) { 477 stub->emit_code(this); 478 } 479 480 return offset; 481 } 482 483 484 int LIR_Assembler::emit_deopt_handler() { 485 // if the last instruction is a call (typically to do a throw which 486 // is coming at the end after block reordering) the return address 487 // must still point into the code area in order to avoid assertion 488 // failures when searching for the corresponding bci => add a nop 489 // (was bug 5/14/1999 - gri) 490 __ nop(); 491 492 // generate code for exception handler 493 address handler_base = __ start_a_stub(deopt_handler_size()); 494 if (handler_base == NULL) { 495 // not enough space left for the handler 496 bailout("deopt handler overflow"); 497 return -1; 498 } 499 500 int offset = code_offset(); 501 InternalAddress here(__ pc()); 502 503 __ pushptr(here.addr()); 504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 506 __ end_a_stub(); 507 508 return offset; 509 } 510 511 512 void LIR_Assembler::return_op(LIR_Opr result) { 513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 515 assert(result->fpu() == 0, "result must already be on TOS"); 516 } 517 518 // Pop the stack before the safepoint code 519 __ remove_frame(initial_frame_size_in_bytes()); 520 521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 522 __ reserved_stack_check(); 523 } 524 525 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 530 if (SafepointMechanism::uses_thread_local_poll()) { 531 #ifdef _LP64 532 __ movptr(rscratch1, Address(r15_thread, Thread::polling_page_offset())); 533 __ relocate(relocInfo::poll_return_type); 534 __ testl(rax, Address(rscratch1, 0)); 535 #else 536 ShouldNotReachHere(); 537 #endif 538 } else { 539 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 540 541 if (Assembler::is_polling_page_far()) { 542 __ lea(rscratch1, polling_page); 543 __ relocate(relocInfo::poll_return_type); 544 __ testl(rax, Address(rscratch1, 0)); 545 } else { 546 __ testl(rax, polling_page); 547 } 548 } 549 __ ret(0); 550 } 551 552 553 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 554 guarantee(info != NULL, "Shouldn't be NULL"); 555 int offset = __ offset(); 556 if (SafepointMechanism::uses_thread_local_poll()) { 557 #ifdef _LP64 558 __ movptr(rscratch1, Address(r15_thread, Thread::polling_page_offset())); 559 add_debug_info_for_branch(info); 560 __ relocate(relocInfo::poll_type); 561 address pre_pc = __ pc(); 562 __ testl(rax, Address(rscratch1, 0)); 563 address post_pc = __ pc(); 564 guarantee(pointer_delta(post_pc, pre_pc, 1) == 3, "must be exact length"); 565 #else 566 ShouldNotReachHere(); 567 #endif 568 } else { 569 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 570 if (Assembler::is_polling_page_far()) { 571 __ lea(rscratch1, polling_page); 572 offset = __ offset(); 573 add_debug_info_for_branch(info); 574 __ relocate(relocInfo::poll_type); 575 __ testl(rax, Address(rscratch1, 0)); 576 } else { 577 add_debug_info_for_branch(info); 578 __ testl(rax, polling_page); 579 } 580 } 581 return offset; 582 } 583 584 585 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 586 if (from_reg != to_reg) __ mov(to_reg, from_reg); 587 } 588 589 void LIR_Assembler::swap_reg(Register a, Register b) { 590 __ xchgptr(a, b); 591 } 592 593 594 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 595 assert(src->is_constant(), "should not call otherwise"); 596 assert(dest->is_register(), "should not call otherwise"); 597 LIR_Const* c = src->as_constant_ptr(); 598 599 switch (c->type()) { 600 case T_INT: { 601 assert(patch_code == lir_patch_none, "no patching handled here"); 602 __ movl(dest->as_register(), c->as_jint()); 603 break; 604 } 605 606 case T_ADDRESS: { 607 assert(patch_code == lir_patch_none, "no patching handled here"); 608 __ movptr(dest->as_register(), c->as_jint()); 609 break; 610 } 611 612 case T_LONG: { 613 assert(patch_code == lir_patch_none, "no patching handled here"); 614 #ifdef _LP64 615 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 616 #else 617 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 618 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 619 #endif // _LP64 620 break; 621 } 622 623 case T_OBJECT: { 624 if (patch_code != lir_patch_none) { 625 jobject2reg_with_patching(dest->as_register(), info); 626 } else { 627 __ movoop(dest->as_register(), c->as_jobject()); 628 } 629 break; 630 } 631 632 case T_METADATA: { 633 if (patch_code != lir_patch_none) { 634 klass2reg_with_patching(dest->as_register(), info); 635 } else { 636 __ mov_metadata(dest->as_register(), c->as_metadata()); 637 } 638 break; 639 } 640 641 case T_FLOAT: { 642 if (dest->is_single_xmm()) { 643 if (c->is_zero_float()) { 644 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 645 } else { 646 __ movflt(dest->as_xmm_float_reg(), 647 InternalAddress(float_constant(c->as_jfloat()))); 648 } 649 } else { 650 assert(dest->is_single_fpu(), "must be"); 651 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 652 if (c->is_zero_float()) { 653 __ fldz(); 654 } else if (c->is_one_float()) { 655 __ fld1(); 656 } else { 657 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 658 } 659 } 660 break; 661 } 662 663 case T_DOUBLE: { 664 if (dest->is_double_xmm()) { 665 if (c->is_zero_double()) { 666 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 667 } else { 668 __ movdbl(dest->as_xmm_double_reg(), 669 InternalAddress(double_constant(c->as_jdouble()))); 670 } 671 } else { 672 assert(dest->is_double_fpu(), "must be"); 673 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 674 if (c->is_zero_double()) { 675 __ fldz(); 676 } else if (c->is_one_double()) { 677 __ fld1(); 678 } else { 679 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 680 } 681 } 682 break; 683 } 684 685 default: 686 ShouldNotReachHere(); 687 } 688 } 689 690 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 691 assert(src->is_constant(), "should not call otherwise"); 692 assert(dest->is_stack(), "should not call otherwise"); 693 LIR_Const* c = src->as_constant_ptr(); 694 695 switch (c->type()) { 696 case T_INT: // fall through 697 case T_FLOAT: 698 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 699 break; 700 701 case T_ADDRESS: 702 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 703 break; 704 705 case T_OBJECT: 706 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 707 break; 708 709 case T_LONG: // fall through 710 case T_DOUBLE: 711 #ifdef _LP64 712 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 713 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 714 #else 715 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 716 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 717 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 718 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 719 #endif // _LP64 720 break; 721 722 default: 723 ShouldNotReachHere(); 724 } 725 } 726 727 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 728 assert(src->is_constant(), "should not call otherwise"); 729 assert(dest->is_address(), "should not call otherwise"); 730 LIR_Const* c = src->as_constant_ptr(); 731 LIR_Address* addr = dest->as_address_ptr(); 732 733 int null_check_here = code_offset(); 734 switch (type) { 735 case T_INT: // fall through 736 case T_FLOAT: 737 __ movl(as_Address(addr), c->as_jint_bits()); 738 break; 739 740 case T_ADDRESS: 741 __ movptr(as_Address(addr), c->as_jint_bits()); 742 break; 743 744 case T_OBJECT: // fall through 745 case T_ARRAY: 746 if (c->as_jobject() == NULL) { 747 if (UseCompressedOops && !wide) { 748 __ movl(as_Address(addr), (int32_t)NULL_WORD); 749 } else { 750 #ifdef _LP64 751 __ xorptr(rscratch1, rscratch1); 752 null_check_here = code_offset(); 753 __ movptr(as_Address(addr), rscratch1); 754 #else 755 __ movptr(as_Address(addr), NULL_WORD); 756 #endif 757 } 758 } else { 759 if (is_literal_address(addr)) { 760 ShouldNotReachHere(); 761 __ movoop(as_Address(addr, noreg), c->as_jobject()); 762 } else { 763 #ifdef _LP64 764 __ movoop(rscratch1, c->as_jobject()); 765 if (UseCompressedOops && !wide) { 766 __ encode_heap_oop(rscratch1); 767 null_check_here = code_offset(); 768 __ movl(as_Address_lo(addr), rscratch1); 769 } else { 770 null_check_here = code_offset(); 771 __ movptr(as_Address_lo(addr), rscratch1); 772 } 773 #else 774 __ movoop(as_Address(addr), c->as_jobject()); 775 #endif 776 } 777 } 778 break; 779 780 case T_LONG: // fall through 781 case T_DOUBLE: 782 #ifdef _LP64 783 if (is_literal_address(addr)) { 784 ShouldNotReachHere(); 785 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 786 } else { 787 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 788 null_check_here = code_offset(); 789 __ movptr(as_Address_lo(addr), r10); 790 } 791 #else 792 // Always reachable in 32bit so this doesn't produce useless move literal 793 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 794 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 795 #endif // _LP64 796 break; 797 798 case T_BOOLEAN: // fall through 799 case T_BYTE: 800 __ movb(as_Address(addr), c->as_jint() & 0xFF); 801 break; 802 803 case T_CHAR: // fall through 804 case T_SHORT: 805 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 806 break; 807 808 default: 809 ShouldNotReachHere(); 810 }; 811 812 if (info != NULL) { 813 add_debug_info_for_null_check(null_check_here, info); 814 } 815 } 816 817 818 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 819 assert(src->is_register(), "should not call otherwise"); 820 assert(dest->is_register(), "should not call otherwise"); 821 822 // move between cpu-registers 823 if (dest->is_single_cpu()) { 824 #ifdef _LP64 825 if (src->type() == T_LONG) { 826 // Can do LONG -> OBJECT 827 move_regs(src->as_register_lo(), dest->as_register()); 828 return; 829 } 830 #endif 831 assert(src->is_single_cpu(), "must match"); 832 if (src->type() == T_OBJECT) { 833 __ verify_oop(src->as_register()); 834 } 835 move_regs(src->as_register(), dest->as_register()); 836 837 } else if (dest->is_double_cpu()) { 838 #ifdef _LP64 839 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 840 // Surprising to me but we can see move of a long to t_object 841 __ verify_oop(src->as_register()); 842 move_regs(src->as_register(), dest->as_register_lo()); 843 return; 844 } 845 #endif 846 assert(src->is_double_cpu(), "must match"); 847 Register f_lo = src->as_register_lo(); 848 Register f_hi = src->as_register_hi(); 849 Register t_lo = dest->as_register_lo(); 850 Register t_hi = dest->as_register_hi(); 851 #ifdef _LP64 852 assert(f_hi == f_lo, "must be same"); 853 assert(t_hi == t_lo, "must be same"); 854 move_regs(f_lo, t_lo); 855 #else 856 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 857 858 859 if (f_lo == t_hi && f_hi == t_lo) { 860 swap_reg(f_lo, f_hi); 861 } else if (f_hi == t_lo) { 862 assert(f_lo != t_hi, "overwriting register"); 863 move_regs(f_hi, t_hi); 864 move_regs(f_lo, t_lo); 865 } else { 866 assert(f_hi != t_lo, "overwriting register"); 867 move_regs(f_lo, t_lo); 868 move_regs(f_hi, t_hi); 869 } 870 #endif // LP64 871 872 // special moves from fpu-register to xmm-register 873 // necessary for method results 874 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 875 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 876 __ fld_s(Address(rsp, 0)); 877 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 878 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 879 __ fld_d(Address(rsp, 0)); 880 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 881 __ fstp_s(Address(rsp, 0)); 882 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 883 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 884 __ fstp_d(Address(rsp, 0)); 885 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 886 887 // move between xmm-registers 888 } else if (dest->is_single_xmm()) { 889 assert(src->is_single_xmm(), "must match"); 890 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 891 } else if (dest->is_double_xmm()) { 892 assert(src->is_double_xmm(), "must match"); 893 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 894 895 // move between fpu-registers (no instruction necessary because of fpu-stack) 896 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 897 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 898 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 899 } else { 900 ShouldNotReachHere(); 901 } 902 } 903 904 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 905 assert(src->is_register(), "should not call otherwise"); 906 assert(dest->is_stack(), "should not call otherwise"); 907 908 if (src->is_single_cpu()) { 909 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 910 if (type == T_OBJECT || type == T_ARRAY) { 911 __ verify_oop(src->as_register()); 912 __ movptr (dst, src->as_register()); 913 } else if (type == T_METADATA) { 914 __ movptr (dst, src->as_register()); 915 } else { 916 __ movl (dst, src->as_register()); 917 } 918 919 } else if (src->is_double_cpu()) { 920 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 921 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 922 __ movptr (dstLO, src->as_register_lo()); 923 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 924 925 } else if (src->is_single_xmm()) { 926 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 927 __ movflt(dst_addr, src->as_xmm_float_reg()); 928 929 } else if (src->is_double_xmm()) { 930 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 931 __ movdbl(dst_addr, src->as_xmm_double_reg()); 932 933 } else if (src->is_single_fpu()) { 934 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 935 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 936 if (pop_fpu_stack) __ fstp_s (dst_addr); 937 else __ fst_s (dst_addr); 938 939 } else if (src->is_double_fpu()) { 940 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 941 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 942 if (pop_fpu_stack) __ fstp_d (dst_addr); 943 else __ fst_d (dst_addr); 944 945 } else { 946 ShouldNotReachHere(); 947 } 948 } 949 950 951 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 952 LIR_Address* to_addr = dest->as_address_ptr(); 953 PatchingStub* patch = NULL; 954 Register compressed_src = rscratch1; 955 956 if (type == T_ARRAY || type == T_OBJECT) { 957 __ verify_oop(src->as_register()); 958 #ifdef _LP64 959 if (UseCompressedOops && !wide) { 960 __ movptr(compressed_src, src->as_register()); 961 __ encode_heap_oop(compressed_src); 962 if (patch_code != lir_patch_none) { 963 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 964 } 965 } 966 #endif 967 } 968 969 if (patch_code != lir_patch_none) { 970 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 971 Address toa = as_Address(to_addr); 972 assert(toa.disp() != 0, "must have"); 973 } 974 975 int null_check_here = code_offset(); 976 switch (type) { 977 case T_FLOAT: { 978 if (src->is_single_xmm()) { 979 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 980 } else { 981 assert(src->is_single_fpu(), "must be"); 982 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 983 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 984 else __ fst_s (as_Address(to_addr)); 985 } 986 break; 987 } 988 989 case T_DOUBLE: { 990 if (src->is_double_xmm()) { 991 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 992 } else { 993 assert(src->is_double_fpu(), "must be"); 994 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 995 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 996 else __ fst_d (as_Address(to_addr)); 997 } 998 break; 999 } 1000 1001 case T_ARRAY: // fall through 1002 case T_OBJECT: // fall through 1003 if (UseCompressedOops && !wide) { 1004 __ movl(as_Address(to_addr), compressed_src); 1005 } else { 1006 __ movptr(as_Address(to_addr), src->as_register()); 1007 } 1008 break; 1009 case T_METADATA: 1010 // We get here to store a method pointer to the stack to pass to 1011 // a dtrace runtime call. This can't work on 64 bit with 1012 // compressed klass ptrs: T_METADATA can be a compressed klass 1013 // ptr or a 64 bit method pointer. 1014 LP64_ONLY(ShouldNotReachHere()); 1015 __ movptr(as_Address(to_addr), src->as_register()); 1016 break; 1017 case T_ADDRESS: 1018 __ movptr(as_Address(to_addr), src->as_register()); 1019 break; 1020 case T_INT: 1021 __ movl(as_Address(to_addr), src->as_register()); 1022 break; 1023 1024 case T_LONG: { 1025 Register from_lo = src->as_register_lo(); 1026 Register from_hi = src->as_register_hi(); 1027 #ifdef _LP64 1028 __ movptr(as_Address_lo(to_addr), from_lo); 1029 #else 1030 Register base = to_addr->base()->as_register(); 1031 Register index = noreg; 1032 if (to_addr->index()->is_register()) { 1033 index = to_addr->index()->as_register(); 1034 } 1035 if (base == from_lo || index == from_lo) { 1036 assert(base != from_hi, "can't be"); 1037 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1038 __ movl(as_Address_hi(to_addr), from_hi); 1039 if (patch != NULL) { 1040 patching_epilog(patch, lir_patch_high, base, info); 1041 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1042 patch_code = lir_patch_low; 1043 } 1044 __ movl(as_Address_lo(to_addr), from_lo); 1045 } else { 1046 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1047 __ movl(as_Address_lo(to_addr), from_lo); 1048 if (patch != NULL) { 1049 patching_epilog(patch, lir_patch_low, base, info); 1050 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1051 patch_code = lir_patch_high; 1052 } 1053 __ movl(as_Address_hi(to_addr), from_hi); 1054 } 1055 #endif // _LP64 1056 break; 1057 } 1058 1059 case T_BYTE: // fall through 1060 case T_BOOLEAN: { 1061 Register src_reg = src->as_register(); 1062 Address dst_addr = as_Address(to_addr); 1063 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1064 __ movb(dst_addr, src_reg); 1065 break; 1066 } 1067 1068 case T_CHAR: // fall through 1069 case T_SHORT: 1070 __ movw(as_Address(to_addr), src->as_register()); 1071 break; 1072 1073 default: 1074 ShouldNotReachHere(); 1075 } 1076 if (info != NULL) { 1077 add_debug_info_for_null_check(null_check_here, info); 1078 } 1079 1080 if (patch_code != lir_patch_none) { 1081 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1082 } 1083 } 1084 1085 1086 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1087 assert(src->is_stack(), "should not call otherwise"); 1088 assert(dest->is_register(), "should not call otherwise"); 1089 1090 if (dest->is_single_cpu()) { 1091 if (type == T_ARRAY || type == T_OBJECT) { 1092 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1093 __ verify_oop(dest->as_register()); 1094 } else if (type == T_METADATA) { 1095 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1096 } else { 1097 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1098 } 1099 1100 } else if (dest->is_double_cpu()) { 1101 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1102 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1103 __ movptr(dest->as_register_lo(), src_addr_LO); 1104 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1105 1106 } else if (dest->is_single_xmm()) { 1107 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1108 __ movflt(dest->as_xmm_float_reg(), src_addr); 1109 1110 } else if (dest->is_double_xmm()) { 1111 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1112 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1113 1114 } else if (dest->is_single_fpu()) { 1115 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1116 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1117 __ fld_s(src_addr); 1118 1119 } else if (dest->is_double_fpu()) { 1120 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1122 __ fld_d(src_addr); 1123 1124 } else { 1125 ShouldNotReachHere(); 1126 } 1127 } 1128 1129 1130 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1131 if (src->is_single_stack()) { 1132 if (type == T_OBJECT || type == T_ARRAY) { 1133 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1134 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1135 } else { 1136 #ifndef _LP64 1137 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1138 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1139 #else 1140 //no pushl on 64bits 1141 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1142 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1143 #endif 1144 } 1145 1146 } else if (src->is_double_stack()) { 1147 #ifdef _LP64 1148 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1149 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1150 #else 1151 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1152 // push and pop the part at src + wordSize, adding wordSize for the previous push 1153 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1154 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1155 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1156 #endif // _LP64 1157 1158 } else { 1159 ShouldNotReachHere(); 1160 } 1161 } 1162 1163 1164 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1165 assert(src->is_address(), "should not call otherwise"); 1166 assert(dest->is_register(), "should not call otherwise"); 1167 1168 LIR_Address* addr = src->as_address_ptr(); 1169 Address from_addr = as_Address(addr); 1170 1171 if (addr->base()->type() == T_OBJECT) { 1172 __ verify_oop(addr->base()->as_pointer_register()); 1173 } 1174 1175 switch (type) { 1176 case T_BOOLEAN: // fall through 1177 case T_BYTE: // fall through 1178 case T_CHAR: // fall through 1179 case T_SHORT: 1180 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1181 // on pre P6 processors we may get partial register stalls 1182 // so blow away the value of to_rinfo before loading a 1183 // partial word into it. Do it here so that it precedes 1184 // the potential patch point below. 1185 __ xorptr(dest->as_register(), dest->as_register()); 1186 } 1187 break; 1188 default: 1189 break; 1190 } 1191 1192 PatchingStub* patch = NULL; 1193 if (patch_code != lir_patch_none) { 1194 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1195 assert(from_addr.disp() != 0, "must have"); 1196 } 1197 if (info != NULL) { 1198 add_debug_info_for_null_check_here(info); 1199 } 1200 1201 switch (type) { 1202 case T_FLOAT: { 1203 if (dest->is_single_xmm()) { 1204 __ movflt(dest->as_xmm_float_reg(), from_addr); 1205 } else { 1206 assert(dest->is_single_fpu(), "must be"); 1207 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1208 __ fld_s(from_addr); 1209 } 1210 break; 1211 } 1212 1213 case T_DOUBLE: { 1214 if (dest->is_double_xmm()) { 1215 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1216 } else { 1217 assert(dest->is_double_fpu(), "must be"); 1218 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1219 __ fld_d(from_addr); 1220 } 1221 break; 1222 } 1223 1224 case T_OBJECT: // fall through 1225 case T_ARRAY: // fall through 1226 if (UseCompressedOops && !wide) { 1227 __ movl(dest->as_register(), from_addr); 1228 } else { 1229 __ movptr(dest->as_register(), from_addr); 1230 } 1231 break; 1232 1233 case T_ADDRESS: 1234 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1235 __ movl(dest->as_register(), from_addr); 1236 } else { 1237 __ movptr(dest->as_register(), from_addr); 1238 } 1239 break; 1240 case T_INT: 1241 __ movl(dest->as_register(), from_addr); 1242 break; 1243 1244 case T_LONG: { 1245 Register to_lo = dest->as_register_lo(); 1246 Register to_hi = dest->as_register_hi(); 1247 #ifdef _LP64 1248 __ movptr(to_lo, as_Address_lo(addr)); 1249 #else 1250 Register base = addr->base()->as_register(); 1251 Register index = noreg; 1252 if (addr->index()->is_register()) { 1253 index = addr->index()->as_register(); 1254 } 1255 if ((base == to_lo && index == to_hi) || 1256 (base == to_hi && index == to_lo)) { 1257 // addresses with 2 registers are only formed as a result of 1258 // array access so this code will never have to deal with 1259 // patches or null checks. 1260 assert(info == NULL && patch == NULL, "must be"); 1261 __ lea(to_hi, as_Address(addr)); 1262 __ movl(to_lo, Address(to_hi, 0)); 1263 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1264 } else if (base == to_lo || index == to_lo) { 1265 assert(base != to_hi, "can't be"); 1266 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1267 __ movl(to_hi, as_Address_hi(addr)); 1268 if (patch != NULL) { 1269 patching_epilog(patch, lir_patch_high, base, info); 1270 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1271 patch_code = lir_patch_low; 1272 } 1273 __ movl(to_lo, as_Address_lo(addr)); 1274 } else { 1275 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1276 __ movl(to_lo, as_Address_lo(addr)); 1277 if (patch != NULL) { 1278 patching_epilog(patch, lir_patch_low, base, info); 1279 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1280 patch_code = lir_patch_high; 1281 } 1282 __ movl(to_hi, as_Address_hi(addr)); 1283 } 1284 #endif // _LP64 1285 break; 1286 } 1287 1288 case T_BOOLEAN: // fall through 1289 case T_BYTE: { 1290 Register dest_reg = dest->as_register(); 1291 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1292 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1293 __ movsbl(dest_reg, from_addr); 1294 } else { 1295 __ movb(dest_reg, from_addr); 1296 __ shll(dest_reg, 24); 1297 __ sarl(dest_reg, 24); 1298 } 1299 break; 1300 } 1301 1302 case T_CHAR: { 1303 Register dest_reg = dest->as_register(); 1304 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1305 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1306 __ movzwl(dest_reg, from_addr); 1307 } else { 1308 __ movw(dest_reg, from_addr); 1309 } 1310 break; 1311 } 1312 1313 case T_SHORT: { 1314 Register dest_reg = dest->as_register(); 1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1316 __ movswl(dest_reg, from_addr); 1317 } else { 1318 __ movw(dest_reg, from_addr); 1319 __ shll(dest_reg, 16); 1320 __ sarl(dest_reg, 16); 1321 } 1322 break; 1323 } 1324 1325 default: 1326 ShouldNotReachHere(); 1327 } 1328 1329 if (patch != NULL) { 1330 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1331 } 1332 1333 if (type == T_ARRAY || type == T_OBJECT) { 1334 #ifdef _LP64 1335 if (UseCompressedOops && !wide) { 1336 __ decode_heap_oop(dest->as_register()); 1337 } 1338 #endif 1339 __ verify_oop(dest->as_register()); 1340 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1341 #ifdef _LP64 1342 if (UseCompressedClassPointers) { 1343 __ decode_klass_not_null(dest->as_register()); 1344 } 1345 #endif 1346 } 1347 } 1348 1349 1350 NEEDS_CLEANUP; // This could be static? 1351 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1352 int elem_size = type2aelembytes(type); 1353 switch (elem_size) { 1354 case 1: return Address::times_1; 1355 case 2: return Address::times_2; 1356 case 4: return Address::times_4; 1357 case 8: return Address::times_8; 1358 } 1359 ShouldNotReachHere(); 1360 return Address::no_scale; 1361 } 1362 1363 1364 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1365 switch (op->code()) { 1366 case lir_idiv: 1367 case lir_irem: 1368 arithmetic_idiv(op->code(), 1369 op->in_opr1(), 1370 op->in_opr2(), 1371 op->in_opr3(), 1372 op->result_opr(), 1373 op->info()); 1374 break; 1375 case lir_fmad: 1376 __ fmad(op->result_opr()->as_xmm_double_reg(), 1377 op->in_opr1()->as_xmm_double_reg(), 1378 op->in_opr2()->as_xmm_double_reg(), 1379 op->in_opr3()->as_xmm_double_reg()); 1380 break; 1381 case lir_fmaf: 1382 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1383 op->in_opr1()->as_xmm_float_reg(), 1384 op->in_opr2()->as_xmm_float_reg(), 1385 op->in_opr3()->as_xmm_float_reg()); 1386 break; 1387 default: ShouldNotReachHere(); break; 1388 } 1389 } 1390 1391 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1392 #ifdef ASSERT 1393 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1394 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1395 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1396 #endif 1397 1398 if (op->cond() == lir_cond_always) { 1399 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1400 __ jmp (*(op->label())); 1401 } else { 1402 Assembler::Condition acond = Assembler::zero; 1403 if (op->code() == lir_cond_float_branch) { 1404 assert(op->ublock() != NULL, "must have unordered successor"); 1405 __ jcc(Assembler::parity, *(op->ublock()->label())); 1406 switch(op->cond()) { 1407 case lir_cond_equal: acond = Assembler::equal; break; 1408 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1409 case lir_cond_less: acond = Assembler::below; break; 1410 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1411 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1412 case lir_cond_greater: acond = Assembler::above; break; 1413 default: ShouldNotReachHere(); 1414 } 1415 } else { 1416 switch (op->cond()) { 1417 case lir_cond_equal: acond = Assembler::equal; break; 1418 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1419 case lir_cond_less: acond = Assembler::less; break; 1420 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1421 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1422 case lir_cond_greater: acond = Assembler::greater; break; 1423 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1424 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1425 default: ShouldNotReachHere(); 1426 } 1427 } 1428 __ jcc(acond,*(op->label())); 1429 } 1430 } 1431 1432 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1433 LIR_Opr src = op->in_opr(); 1434 LIR_Opr dest = op->result_opr(); 1435 1436 switch (op->bytecode()) { 1437 case Bytecodes::_i2l: 1438 #ifdef _LP64 1439 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1440 #else 1441 move_regs(src->as_register(), dest->as_register_lo()); 1442 move_regs(src->as_register(), dest->as_register_hi()); 1443 __ sarl(dest->as_register_hi(), 31); 1444 #endif // LP64 1445 break; 1446 1447 case Bytecodes::_l2i: 1448 #ifdef _LP64 1449 __ movl(dest->as_register(), src->as_register_lo()); 1450 #else 1451 move_regs(src->as_register_lo(), dest->as_register()); 1452 #endif 1453 break; 1454 1455 case Bytecodes::_i2b: 1456 move_regs(src->as_register(), dest->as_register()); 1457 __ sign_extend_byte(dest->as_register()); 1458 break; 1459 1460 case Bytecodes::_i2c: 1461 move_regs(src->as_register(), dest->as_register()); 1462 __ andl(dest->as_register(), 0xFFFF); 1463 break; 1464 1465 case Bytecodes::_i2s: 1466 move_regs(src->as_register(), dest->as_register()); 1467 __ sign_extend_short(dest->as_register()); 1468 break; 1469 1470 1471 case Bytecodes::_f2d: 1472 case Bytecodes::_d2f: 1473 if (dest->is_single_xmm()) { 1474 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1475 } else if (dest->is_double_xmm()) { 1476 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1477 } else { 1478 assert(src->fpu() == dest->fpu(), "register must be equal"); 1479 // do nothing (float result is rounded later through spilling) 1480 } 1481 break; 1482 1483 case Bytecodes::_i2f: 1484 case Bytecodes::_i2d: 1485 if (dest->is_single_xmm()) { 1486 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1487 } else if (dest->is_double_xmm()) { 1488 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1489 } else { 1490 assert(dest->fpu() == 0, "result must be on TOS"); 1491 __ movl(Address(rsp, 0), src->as_register()); 1492 __ fild_s(Address(rsp, 0)); 1493 } 1494 break; 1495 1496 case Bytecodes::_f2i: 1497 case Bytecodes::_d2i: 1498 if (src->is_single_xmm()) { 1499 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1500 } else if (src->is_double_xmm()) { 1501 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1502 } else { 1503 assert(src->fpu() == 0, "input must be on TOS"); 1504 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1505 __ fist_s(Address(rsp, 0)); 1506 __ movl(dest->as_register(), Address(rsp, 0)); 1507 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1508 } 1509 1510 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1511 assert(op->stub() != NULL, "stub required"); 1512 __ cmpl(dest->as_register(), 0x80000000); 1513 __ jcc(Assembler::equal, *op->stub()->entry()); 1514 __ bind(*op->stub()->continuation()); 1515 break; 1516 1517 case Bytecodes::_l2f: 1518 case Bytecodes::_l2d: 1519 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1520 assert(dest->fpu() == 0, "result must be on TOS"); 1521 1522 __ movptr(Address(rsp, 0), src->as_register_lo()); 1523 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1524 __ fild_d(Address(rsp, 0)); 1525 // float result is rounded later through spilling 1526 break; 1527 1528 case Bytecodes::_f2l: 1529 case Bytecodes::_d2l: 1530 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1531 assert(src->fpu() == 0, "input must be on TOS"); 1532 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1533 1534 // instruction sequence too long to inline it here 1535 { 1536 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1537 } 1538 break; 1539 1540 default: ShouldNotReachHere(); 1541 } 1542 } 1543 1544 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1545 if (op->init_check()) { 1546 __ cmpb(Address(op->klass()->as_register(), 1547 InstanceKlass::init_state_offset()), 1548 InstanceKlass::fully_initialized); 1549 add_debug_info_for_null_check_here(op->stub()->info()); 1550 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1551 } 1552 __ allocate_object(op->obj()->as_register(), 1553 op->tmp1()->as_register(), 1554 op->tmp2()->as_register(), 1555 op->header_size(), 1556 op->object_size(), 1557 op->klass()->as_register(), 1558 *op->stub()->entry()); 1559 __ bind(*op->stub()->continuation()); 1560 } 1561 1562 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1563 Register len = op->len()->as_register(); 1564 LP64_ONLY( __ movslq(len, len); ) 1565 1566 if (UseSlowPath || 1567 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1568 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1569 __ jmp(*op->stub()->entry()); 1570 } else { 1571 Register tmp1 = op->tmp1()->as_register(); 1572 Register tmp2 = op->tmp2()->as_register(); 1573 Register tmp3 = op->tmp3()->as_register(); 1574 if (len == tmp1) { 1575 tmp1 = tmp3; 1576 } else if (len == tmp2) { 1577 tmp2 = tmp3; 1578 } else if (len == tmp3) { 1579 // everything is ok 1580 } else { 1581 __ mov(tmp3, len); 1582 } 1583 __ allocate_array(op->obj()->as_register(), 1584 len, 1585 tmp1, 1586 tmp2, 1587 arrayOopDesc::header_size(op->type()), 1588 array_element_size(op->type()), 1589 op->klass()->as_register(), 1590 *op->stub()->entry()); 1591 } 1592 __ bind(*op->stub()->continuation()); 1593 } 1594 1595 void LIR_Assembler::type_profile_helper(Register mdo, 1596 ciMethodData *md, ciProfileData *data, 1597 Register recv, Label* update_done) { 1598 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1599 Label next_test; 1600 // See if the receiver is receiver[n]. 1601 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1602 __ jccb(Assembler::notEqual, next_test); 1603 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1604 __ addptr(data_addr, DataLayout::counter_increment); 1605 __ jmp(*update_done); 1606 __ bind(next_test); 1607 } 1608 1609 // Didn't find receiver; find next empty slot and fill it in 1610 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1611 Label next_test; 1612 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1613 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1614 __ jccb(Assembler::notEqual, next_test); 1615 __ movptr(recv_addr, recv); 1616 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1617 __ jmp(*update_done); 1618 __ bind(next_test); 1619 } 1620 } 1621 1622 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1623 // we always need a stub for the failure case. 1624 CodeStub* stub = op->stub(); 1625 Register obj = op->object()->as_register(); 1626 Register k_RInfo = op->tmp1()->as_register(); 1627 Register klass_RInfo = op->tmp2()->as_register(); 1628 Register dst = op->result_opr()->as_register(); 1629 ciKlass* k = op->klass(); 1630 Register Rtmp1 = noreg; 1631 1632 // check if it needs to be profiled 1633 ciMethodData* md = NULL; 1634 ciProfileData* data = NULL; 1635 1636 if (op->should_profile()) { 1637 ciMethod* method = op->profiled_method(); 1638 assert(method != NULL, "Should have method"); 1639 int bci = op->profiled_bci(); 1640 md = method->method_data_or_null(); 1641 assert(md != NULL, "Sanity"); 1642 data = md->bci_to_data(bci); 1643 assert(data != NULL, "need data for type check"); 1644 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1645 } 1646 Label profile_cast_success, profile_cast_failure; 1647 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1648 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1649 1650 if (obj == k_RInfo) { 1651 k_RInfo = dst; 1652 } else if (obj == klass_RInfo) { 1653 klass_RInfo = dst; 1654 } 1655 if (k->is_loaded() && !UseCompressedClassPointers) { 1656 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1657 } else { 1658 Rtmp1 = op->tmp3()->as_register(); 1659 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1660 } 1661 1662 assert_different_registers(obj, k_RInfo, klass_RInfo); 1663 1664 __ cmpptr(obj, (int32_t)NULL_WORD); 1665 if (op->should_profile()) { 1666 Label not_null; 1667 __ jccb(Assembler::notEqual, not_null); 1668 // Object is null; update MDO and exit 1669 Register mdo = klass_RInfo; 1670 __ mov_metadata(mdo, md->constant_encoding()); 1671 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1672 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1673 __ orl(data_addr, header_bits); 1674 __ jmp(*obj_is_null); 1675 __ bind(not_null); 1676 } else { 1677 __ jcc(Assembler::equal, *obj_is_null); 1678 } 1679 1680 if (!k->is_loaded()) { 1681 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1682 } else { 1683 #ifdef _LP64 1684 __ mov_metadata(k_RInfo, k->constant_encoding()); 1685 #endif // _LP64 1686 } 1687 __ verify_oop(obj); 1688 1689 if (op->fast_check()) { 1690 // get object class 1691 // not a safepoint as obj null check happens earlier 1692 #ifdef _LP64 1693 if (UseCompressedClassPointers) { 1694 __ load_klass(Rtmp1, obj); 1695 __ cmpptr(k_RInfo, Rtmp1); 1696 } else { 1697 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1698 } 1699 #else 1700 if (k->is_loaded()) { 1701 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1702 } else { 1703 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1704 } 1705 #endif 1706 __ jcc(Assembler::notEqual, *failure_target); 1707 // successful cast, fall through to profile or jump 1708 } else { 1709 // get object class 1710 // not a safepoint as obj null check happens earlier 1711 __ load_klass(klass_RInfo, obj); 1712 if (k->is_loaded()) { 1713 // See if we get an immediate positive hit 1714 #ifdef _LP64 1715 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1716 #else 1717 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1718 #endif // _LP64 1719 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1720 __ jcc(Assembler::notEqual, *failure_target); 1721 // successful cast, fall through to profile or jump 1722 } else { 1723 // See if we get an immediate positive hit 1724 __ jcc(Assembler::equal, *success_target); 1725 // check for self 1726 #ifdef _LP64 1727 __ cmpptr(klass_RInfo, k_RInfo); 1728 #else 1729 __ cmpklass(klass_RInfo, k->constant_encoding()); 1730 #endif // _LP64 1731 __ jcc(Assembler::equal, *success_target); 1732 1733 __ push(klass_RInfo); 1734 #ifdef _LP64 1735 __ push(k_RInfo); 1736 #else 1737 __ pushklass(k->constant_encoding()); 1738 #endif // _LP64 1739 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1740 __ pop(klass_RInfo); 1741 __ pop(klass_RInfo); 1742 // result is a boolean 1743 __ cmpl(klass_RInfo, 0); 1744 __ jcc(Assembler::equal, *failure_target); 1745 // successful cast, fall through to profile or jump 1746 } 1747 } else { 1748 // perform the fast part of the checking logic 1749 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1750 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1751 __ push(klass_RInfo); 1752 __ push(k_RInfo); 1753 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1754 __ pop(klass_RInfo); 1755 __ pop(k_RInfo); 1756 // result is a boolean 1757 __ cmpl(k_RInfo, 0); 1758 __ jcc(Assembler::equal, *failure_target); 1759 // successful cast, fall through to profile or jump 1760 } 1761 } 1762 if (op->should_profile()) { 1763 Register mdo = klass_RInfo, recv = k_RInfo; 1764 __ bind(profile_cast_success); 1765 __ mov_metadata(mdo, md->constant_encoding()); 1766 __ load_klass(recv, obj); 1767 Label update_done; 1768 type_profile_helper(mdo, md, data, recv, success); 1769 __ jmp(*success); 1770 1771 __ bind(profile_cast_failure); 1772 __ mov_metadata(mdo, md->constant_encoding()); 1773 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1774 __ subptr(counter_addr, DataLayout::counter_increment); 1775 __ jmp(*failure); 1776 } 1777 __ jmp(*success); 1778 } 1779 1780 1781 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1782 LIR_Code code = op->code(); 1783 if (code == lir_store_check) { 1784 Register value = op->object()->as_register(); 1785 Register array = op->array()->as_register(); 1786 Register k_RInfo = op->tmp1()->as_register(); 1787 Register klass_RInfo = op->tmp2()->as_register(); 1788 Register Rtmp1 = op->tmp3()->as_register(); 1789 1790 CodeStub* stub = op->stub(); 1791 1792 // check if it needs to be profiled 1793 ciMethodData* md = NULL; 1794 ciProfileData* data = NULL; 1795 1796 if (op->should_profile()) { 1797 ciMethod* method = op->profiled_method(); 1798 assert(method != NULL, "Should have method"); 1799 int bci = op->profiled_bci(); 1800 md = method->method_data_or_null(); 1801 assert(md != NULL, "Sanity"); 1802 data = md->bci_to_data(bci); 1803 assert(data != NULL, "need data for type check"); 1804 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1805 } 1806 Label profile_cast_success, profile_cast_failure, done; 1807 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1808 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1809 1810 __ cmpptr(value, (int32_t)NULL_WORD); 1811 if (op->should_profile()) { 1812 Label not_null; 1813 __ jccb(Assembler::notEqual, not_null); 1814 // Object is null; update MDO and exit 1815 Register mdo = klass_RInfo; 1816 __ mov_metadata(mdo, md->constant_encoding()); 1817 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1818 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1819 __ orl(data_addr, header_bits); 1820 __ jmp(done); 1821 __ bind(not_null); 1822 } else { 1823 __ jcc(Assembler::equal, done); 1824 } 1825 1826 add_debug_info_for_null_check_here(op->info_for_exception()); 1827 __ load_klass(k_RInfo, array); 1828 __ load_klass(klass_RInfo, value); 1829 1830 // get instance klass (it's already uncompressed) 1831 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1832 // perform the fast part of the checking logic 1833 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1834 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1835 __ push(klass_RInfo); 1836 __ push(k_RInfo); 1837 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1838 __ pop(klass_RInfo); 1839 __ pop(k_RInfo); 1840 // result is a boolean 1841 __ cmpl(k_RInfo, 0); 1842 __ jcc(Assembler::equal, *failure_target); 1843 // fall through to the success case 1844 1845 if (op->should_profile()) { 1846 Register mdo = klass_RInfo, recv = k_RInfo; 1847 __ bind(profile_cast_success); 1848 __ mov_metadata(mdo, md->constant_encoding()); 1849 __ load_klass(recv, value); 1850 Label update_done; 1851 type_profile_helper(mdo, md, data, recv, &done); 1852 __ jmpb(done); 1853 1854 __ bind(profile_cast_failure); 1855 __ mov_metadata(mdo, md->constant_encoding()); 1856 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1857 __ subptr(counter_addr, DataLayout::counter_increment); 1858 __ jmp(*stub->entry()); 1859 } 1860 1861 __ bind(done); 1862 } else 1863 if (code == lir_checkcast) { 1864 Register obj = op->object()->as_register(); 1865 Register dst = op->result_opr()->as_register(); 1866 Label success; 1867 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1868 __ bind(success); 1869 if (dst != obj) { 1870 __ mov(dst, obj); 1871 } 1872 } else 1873 if (code == lir_instanceof) { 1874 Register obj = op->object()->as_register(); 1875 Register dst = op->result_opr()->as_register(); 1876 Label success, failure, done; 1877 emit_typecheck_helper(op, &success, &failure, &failure); 1878 __ bind(failure); 1879 __ xorptr(dst, dst); 1880 __ jmpb(done); 1881 __ bind(success); 1882 __ movptr(dst, 1); 1883 __ bind(done); 1884 } else { 1885 ShouldNotReachHere(); 1886 } 1887 1888 } 1889 1890 1891 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1892 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1893 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1894 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1895 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1896 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1897 Register addr = op->addr()->as_register(); 1898 if (os::is_MP()) { 1899 __ lock(); 1900 } 1901 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1902 1903 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1904 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1905 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1906 Register newval = op->new_value()->as_register(); 1907 Register cmpval = op->cmp_value()->as_register(); 1908 assert(cmpval == rax, "wrong register"); 1909 assert(newval != NULL, "new val must be register"); 1910 assert(cmpval != newval, "cmp and new values must be in different registers"); 1911 assert(cmpval != addr, "cmp and addr must be in different registers"); 1912 assert(newval != addr, "new value and addr must be in different registers"); 1913 1914 if ( op->code() == lir_cas_obj) { 1915 #ifdef _LP64 1916 if (UseCompressedOops) { 1917 __ encode_heap_oop(cmpval); 1918 __ mov(rscratch1, newval); 1919 __ encode_heap_oop(rscratch1); 1920 if (os::is_MP()) { 1921 __ lock(); 1922 } 1923 // cmpval (rax) is implicitly used by this instruction 1924 __ cmpxchgl(rscratch1, Address(addr, 0)); 1925 } else 1926 #endif 1927 { 1928 if (os::is_MP()) { 1929 __ lock(); 1930 } 1931 __ cmpxchgptr(newval, Address(addr, 0)); 1932 } 1933 } else { 1934 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1935 if (os::is_MP()) { 1936 __ lock(); 1937 } 1938 __ cmpxchgl(newval, Address(addr, 0)); 1939 } 1940 #ifdef _LP64 1941 } else if (op->code() == lir_cas_long) { 1942 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1943 Register newval = op->new_value()->as_register_lo(); 1944 Register cmpval = op->cmp_value()->as_register_lo(); 1945 assert(cmpval == rax, "wrong register"); 1946 assert(newval != NULL, "new val must be register"); 1947 assert(cmpval != newval, "cmp and new values must be in different registers"); 1948 assert(cmpval != addr, "cmp and addr must be in different registers"); 1949 assert(newval != addr, "new value and addr must be in different registers"); 1950 if (os::is_MP()) { 1951 __ lock(); 1952 } 1953 __ cmpxchgq(newval, Address(addr, 0)); 1954 #endif // _LP64 1955 } else { 1956 Unimplemented(); 1957 } 1958 } 1959 1960 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1961 Assembler::Condition acond, ncond; 1962 switch (condition) { 1963 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1964 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1965 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1966 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1967 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1968 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1969 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1970 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1971 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1972 ShouldNotReachHere(); 1973 } 1974 1975 if (opr1->is_cpu_register()) { 1976 reg2reg(opr1, result); 1977 } else if (opr1->is_stack()) { 1978 stack2reg(opr1, result, result->type()); 1979 } else if (opr1->is_constant()) { 1980 const2reg(opr1, result, lir_patch_none, NULL); 1981 } else { 1982 ShouldNotReachHere(); 1983 } 1984 1985 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1986 // optimized version that does not require a branch 1987 if (opr2->is_single_cpu()) { 1988 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1989 __ cmov(ncond, result->as_register(), opr2->as_register()); 1990 } else if (opr2->is_double_cpu()) { 1991 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1992 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1993 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1994 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1995 } else if (opr2->is_single_stack()) { 1996 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 1997 } else if (opr2->is_double_stack()) { 1998 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 1999 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2000 } else { 2001 ShouldNotReachHere(); 2002 } 2003 2004 } else { 2005 Label skip; 2006 __ jcc (acond, skip); 2007 if (opr2->is_cpu_register()) { 2008 reg2reg(opr2, result); 2009 } else if (opr2->is_stack()) { 2010 stack2reg(opr2, result, result->type()); 2011 } else if (opr2->is_constant()) { 2012 const2reg(opr2, result, lir_patch_none, NULL); 2013 } else { 2014 ShouldNotReachHere(); 2015 } 2016 __ bind(skip); 2017 } 2018 } 2019 2020 2021 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2022 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2023 2024 if (left->is_single_cpu()) { 2025 assert(left == dest, "left and dest must be equal"); 2026 Register lreg = left->as_register(); 2027 2028 if (right->is_single_cpu()) { 2029 // cpu register - cpu register 2030 Register rreg = right->as_register(); 2031 switch (code) { 2032 case lir_add: __ addl (lreg, rreg); break; 2033 case lir_sub: __ subl (lreg, rreg); break; 2034 case lir_mul: __ imull(lreg, rreg); break; 2035 default: ShouldNotReachHere(); 2036 } 2037 2038 } else if (right->is_stack()) { 2039 // cpu register - stack 2040 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2041 switch (code) { 2042 case lir_add: __ addl(lreg, raddr); break; 2043 case lir_sub: __ subl(lreg, raddr); break; 2044 default: ShouldNotReachHere(); 2045 } 2046 2047 } else if (right->is_constant()) { 2048 // cpu register - constant 2049 jint c = right->as_constant_ptr()->as_jint(); 2050 switch (code) { 2051 case lir_add: { 2052 __ incrementl(lreg, c); 2053 break; 2054 } 2055 case lir_sub: { 2056 __ decrementl(lreg, c); 2057 break; 2058 } 2059 default: ShouldNotReachHere(); 2060 } 2061 2062 } else { 2063 ShouldNotReachHere(); 2064 } 2065 2066 } else if (left->is_double_cpu()) { 2067 assert(left == dest, "left and dest must be equal"); 2068 Register lreg_lo = left->as_register_lo(); 2069 Register lreg_hi = left->as_register_hi(); 2070 2071 if (right->is_double_cpu()) { 2072 // cpu register - cpu register 2073 Register rreg_lo = right->as_register_lo(); 2074 Register rreg_hi = right->as_register_hi(); 2075 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2076 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2077 switch (code) { 2078 case lir_add: 2079 __ addptr(lreg_lo, rreg_lo); 2080 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2081 break; 2082 case lir_sub: 2083 __ subptr(lreg_lo, rreg_lo); 2084 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2085 break; 2086 case lir_mul: 2087 #ifdef _LP64 2088 __ imulq(lreg_lo, rreg_lo); 2089 #else 2090 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2091 __ imull(lreg_hi, rreg_lo); 2092 __ imull(rreg_hi, lreg_lo); 2093 __ addl (rreg_hi, lreg_hi); 2094 __ mull (rreg_lo); 2095 __ addl (lreg_hi, rreg_hi); 2096 #endif // _LP64 2097 break; 2098 default: 2099 ShouldNotReachHere(); 2100 } 2101 2102 } else if (right->is_constant()) { 2103 // cpu register - constant 2104 #ifdef _LP64 2105 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2106 __ movptr(r10, (intptr_t) c); 2107 switch (code) { 2108 case lir_add: 2109 __ addptr(lreg_lo, r10); 2110 break; 2111 case lir_sub: 2112 __ subptr(lreg_lo, r10); 2113 break; 2114 default: 2115 ShouldNotReachHere(); 2116 } 2117 #else 2118 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2119 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2120 switch (code) { 2121 case lir_add: 2122 __ addptr(lreg_lo, c_lo); 2123 __ adcl(lreg_hi, c_hi); 2124 break; 2125 case lir_sub: 2126 __ subptr(lreg_lo, c_lo); 2127 __ sbbl(lreg_hi, c_hi); 2128 break; 2129 default: 2130 ShouldNotReachHere(); 2131 } 2132 #endif // _LP64 2133 2134 } else { 2135 ShouldNotReachHere(); 2136 } 2137 2138 } else if (left->is_single_xmm()) { 2139 assert(left == dest, "left and dest must be equal"); 2140 XMMRegister lreg = left->as_xmm_float_reg(); 2141 2142 if (right->is_single_xmm()) { 2143 XMMRegister rreg = right->as_xmm_float_reg(); 2144 switch (code) { 2145 case lir_add: __ addss(lreg, rreg); break; 2146 case lir_sub: __ subss(lreg, rreg); break; 2147 case lir_mul_strictfp: // fall through 2148 case lir_mul: __ mulss(lreg, rreg); break; 2149 case lir_div_strictfp: // fall through 2150 case lir_div: __ divss(lreg, rreg); break; 2151 default: ShouldNotReachHere(); 2152 } 2153 } else { 2154 Address raddr; 2155 if (right->is_single_stack()) { 2156 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2157 } else if (right->is_constant()) { 2158 // hack for now 2159 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2160 } else { 2161 ShouldNotReachHere(); 2162 } 2163 switch (code) { 2164 case lir_add: __ addss(lreg, raddr); break; 2165 case lir_sub: __ subss(lreg, raddr); break; 2166 case lir_mul_strictfp: // fall through 2167 case lir_mul: __ mulss(lreg, raddr); break; 2168 case lir_div_strictfp: // fall through 2169 case lir_div: __ divss(lreg, raddr); break; 2170 default: ShouldNotReachHere(); 2171 } 2172 } 2173 2174 } else if (left->is_double_xmm()) { 2175 assert(left == dest, "left and dest must be equal"); 2176 2177 XMMRegister lreg = left->as_xmm_double_reg(); 2178 if (right->is_double_xmm()) { 2179 XMMRegister rreg = right->as_xmm_double_reg(); 2180 switch (code) { 2181 case lir_add: __ addsd(lreg, rreg); break; 2182 case lir_sub: __ subsd(lreg, rreg); break; 2183 case lir_mul_strictfp: // fall through 2184 case lir_mul: __ mulsd(lreg, rreg); break; 2185 case lir_div_strictfp: // fall through 2186 case lir_div: __ divsd(lreg, rreg); break; 2187 default: ShouldNotReachHere(); 2188 } 2189 } else { 2190 Address raddr; 2191 if (right->is_double_stack()) { 2192 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2193 } else if (right->is_constant()) { 2194 // hack for now 2195 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2196 } else { 2197 ShouldNotReachHere(); 2198 } 2199 switch (code) { 2200 case lir_add: __ addsd(lreg, raddr); break; 2201 case lir_sub: __ subsd(lreg, raddr); break; 2202 case lir_mul_strictfp: // fall through 2203 case lir_mul: __ mulsd(lreg, raddr); break; 2204 case lir_div_strictfp: // fall through 2205 case lir_div: __ divsd(lreg, raddr); break; 2206 default: ShouldNotReachHere(); 2207 } 2208 } 2209 2210 } else if (left->is_single_fpu()) { 2211 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2212 2213 if (right->is_single_fpu()) { 2214 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2215 2216 } else { 2217 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2218 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2219 2220 Address raddr; 2221 if (right->is_single_stack()) { 2222 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2223 } else if (right->is_constant()) { 2224 address const_addr = float_constant(right->as_jfloat()); 2225 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2226 // hack for now 2227 raddr = __ as_Address(InternalAddress(const_addr)); 2228 } else { 2229 ShouldNotReachHere(); 2230 } 2231 2232 switch (code) { 2233 case lir_add: __ fadd_s(raddr); break; 2234 case lir_sub: __ fsub_s(raddr); break; 2235 case lir_mul_strictfp: // fall through 2236 case lir_mul: __ fmul_s(raddr); break; 2237 case lir_div_strictfp: // fall through 2238 case lir_div: __ fdiv_s(raddr); break; 2239 default: ShouldNotReachHere(); 2240 } 2241 } 2242 2243 } else if (left->is_double_fpu()) { 2244 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2245 2246 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2247 // Double values require special handling for strictfp mul/div on x86 2248 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2249 __ fmulp(left->fpu_regnrLo() + 1); 2250 } 2251 2252 if (right->is_double_fpu()) { 2253 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2254 2255 } else { 2256 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2257 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2258 2259 Address raddr; 2260 if (right->is_double_stack()) { 2261 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2262 } else if (right->is_constant()) { 2263 // hack for now 2264 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2265 } else { 2266 ShouldNotReachHere(); 2267 } 2268 2269 switch (code) { 2270 case lir_add: __ fadd_d(raddr); break; 2271 case lir_sub: __ fsub_d(raddr); break; 2272 case lir_mul_strictfp: // fall through 2273 case lir_mul: __ fmul_d(raddr); break; 2274 case lir_div_strictfp: // fall through 2275 case lir_div: __ fdiv_d(raddr); break; 2276 default: ShouldNotReachHere(); 2277 } 2278 } 2279 2280 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2281 // Double values require special handling for strictfp mul/div on x86 2282 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2283 __ fmulp(dest->fpu_regnrLo() + 1); 2284 } 2285 2286 } else if (left->is_single_stack() || left->is_address()) { 2287 assert(left == dest, "left and dest must be equal"); 2288 2289 Address laddr; 2290 if (left->is_single_stack()) { 2291 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2292 } else if (left->is_address()) { 2293 laddr = as_Address(left->as_address_ptr()); 2294 } else { 2295 ShouldNotReachHere(); 2296 } 2297 2298 if (right->is_single_cpu()) { 2299 Register rreg = right->as_register(); 2300 switch (code) { 2301 case lir_add: __ addl(laddr, rreg); break; 2302 case lir_sub: __ subl(laddr, rreg); break; 2303 default: ShouldNotReachHere(); 2304 } 2305 } else if (right->is_constant()) { 2306 jint c = right->as_constant_ptr()->as_jint(); 2307 switch (code) { 2308 case lir_add: { 2309 __ incrementl(laddr, c); 2310 break; 2311 } 2312 case lir_sub: { 2313 __ decrementl(laddr, c); 2314 break; 2315 } 2316 default: ShouldNotReachHere(); 2317 } 2318 } else { 2319 ShouldNotReachHere(); 2320 } 2321 2322 } else { 2323 ShouldNotReachHere(); 2324 } 2325 } 2326 2327 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2328 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2329 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2330 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2331 2332 bool left_is_tos = (left_index == 0); 2333 bool dest_is_tos = (dest_index == 0); 2334 int non_tos_index = (left_is_tos ? right_index : left_index); 2335 2336 switch (code) { 2337 case lir_add: 2338 if (pop_fpu_stack) __ faddp(non_tos_index); 2339 else if (dest_is_tos) __ fadd (non_tos_index); 2340 else __ fadda(non_tos_index); 2341 break; 2342 2343 case lir_sub: 2344 if (left_is_tos) { 2345 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2346 else if (dest_is_tos) __ fsub (non_tos_index); 2347 else __ fsubra(non_tos_index); 2348 } else { 2349 if (pop_fpu_stack) __ fsubp (non_tos_index); 2350 else if (dest_is_tos) __ fsubr (non_tos_index); 2351 else __ fsuba (non_tos_index); 2352 } 2353 break; 2354 2355 case lir_mul_strictfp: // fall through 2356 case lir_mul: 2357 if (pop_fpu_stack) __ fmulp(non_tos_index); 2358 else if (dest_is_tos) __ fmul (non_tos_index); 2359 else __ fmula(non_tos_index); 2360 break; 2361 2362 case lir_div_strictfp: // fall through 2363 case lir_div: 2364 if (left_is_tos) { 2365 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2366 else if (dest_is_tos) __ fdiv (non_tos_index); 2367 else __ fdivra(non_tos_index); 2368 } else { 2369 if (pop_fpu_stack) __ fdivp (non_tos_index); 2370 else if (dest_is_tos) __ fdivr (non_tos_index); 2371 else __ fdiva (non_tos_index); 2372 } 2373 break; 2374 2375 case lir_rem: 2376 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2377 __ fremr(noreg); 2378 break; 2379 2380 default: 2381 ShouldNotReachHere(); 2382 } 2383 } 2384 2385 2386 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2387 if (value->is_double_xmm()) { 2388 switch(code) { 2389 case lir_abs : 2390 { 2391 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2392 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2393 } 2394 __ andpd(dest->as_xmm_double_reg(), 2395 ExternalAddress((address)double_signmask_pool)); 2396 } 2397 break; 2398 2399 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2400 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2401 default : ShouldNotReachHere(); 2402 } 2403 2404 } else if (value->is_double_fpu()) { 2405 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2406 switch(code) { 2407 case lir_abs : __ fabs() ; break; 2408 case lir_sqrt : __ fsqrt(); break; 2409 default : ShouldNotReachHere(); 2410 } 2411 } else { 2412 Unimplemented(); 2413 } 2414 } 2415 2416 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2417 // assert(left->destroys_register(), "check"); 2418 if (left->is_single_cpu()) { 2419 Register reg = left->as_register(); 2420 if (right->is_constant()) { 2421 int val = right->as_constant_ptr()->as_jint(); 2422 switch (code) { 2423 case lir_logic_and: __ andl (reg, val); break; 2424 case lir_logic_or: __ orl (reg, val); break; 2425 case lir_logic_xor: __ xorl (reg, val); break; 2426 default: ShouldNotReachHere(); 2427 } 2428 } else if (right->is_stack()) { 2429 // added support for stack operands 2430 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2431 switch (code) { 2432 case lir_logic_and: __ andl (reg, raddr); break; 2433 case lir_logic_or: __ orl (reg, raddr); break; 2434 case lir_logic_xor: __ xorl (reg, raddr); break; 2435 default: ShouldNotReachHere(); 2436 } 2437 } else { 2438 Register rright = right->as_register(); 2439 switch (code) { 2440 case lir_logic_and: __ andptr (reg, rright); break; 2441 case lir_logic_or : __ orptr (reg, rright); break; 2442 case lir_logic_xor: __ xorptr (reg, rright); break; 2443 default: ShouldNotReachHere(); 2444 } 2445 } 2446 move_regs(reg, dst->as_register()); 2447 } else { 2448 Register l_lo = left->as_register_lo(); 2449 Register l_hi = left->as_register_hi(); 2450 if (right->is_constant()) { 2451 #ifdef _LP64 2452 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2453 switch (code) { 2454 case lir_logic_and: 2455 __ andq(l_lo, rscratch1); 2456 break; 2457 case lir_logic_or: 2458 __ orq(l_lo, rscratch1); 2459 break; 2460 case lir_logic_xor: 2461 __ xorq(l_lo, rscratch1); 2462 break; 2463 default: ShouldNotReachHere(); 2464 } 2465 #else 2466 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2467 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2468 switch (code) { 2469 case lir_logic_and: 2470 __ andl(l_lo, r_lo); 2471 __ andl(l_hi, r_hi); 2472 break; 2473 case lir_logic_or: 2474 __ orl(l_lo, r_lo); 2475 __ orl(l_hi, r_hi); 2476 break; 2477 case lir_logic_xor: 2478 __ xorl(l_lo, r_lo); 2479 __ xorl(l_hi, r_hi); 2480 break; 2481 default: ShouldNotReachHere(); 2482 } 2483 #endif // _LP64 2484 } else { 2485 #ifdef _LP64 2486 Register r_lo; 2487 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2488 r_lo = right->as_register(); 2489 } else { 2490 r_lo = right->as_register_lo(); 2491 } 2492 #else 2493 Register r_lo = right->as_register_lo(); 2494 Register r_hi = right->as_register_hi(); 2495 assert(l_lo != r_hi, "overwriting registers"); 2496 #endif 2497 switch (code) { 2498 case lir_logic_and: 2499 __ andptr(l_lo, r_lo); 2500 NOT_LP64(__ andptr(l_hi, r_hi);) 2501 break; 2502 case lir_logic_or: 2503 __ orptr(l_lo, r_lo); 2504 NOT_LP64(__ orptr(l_hi, r_hi);) 2505 break; 2506 case lir_logic_xor: 2507 __ xorptr(l_lo, r_lo); 2508 NOT_LP64(__ xorptr(l_hi, r_hi);) 2509 break; 2510 default: ShouldNotReachHere(); 2511 } 2512 } 2513 2514 Register dst_lo = dst->as_register_lo(); 2515 Register dst_hi = dst->as_register_hi(); 2516 2517 #ifdef _LP64 2518 move_regs(l_lo, dst_lo); 2519 #else 2520 if (dst_lo == l_hi) { 2521 assert(dst_hi != l_lo, "overwriting registers"); 2522 move_regs(l_hi, dst_hi); 2523 move_regs(l_lo, dst_lo); 2524 } else { 2525 assert(dst_lo != l_hi, "overwriting registers"); 2526 move_regs(l_lo, dst_lo); 2527 move_regs(l_hi, dst_hi); 2528 } 2529 #endif // _LP64 2530 } 2531 } 2532 2533 2534 // we assume that rax, and rdx can be overwritten 2535 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2536 2537 assert(left->is_single_cpu(), "left must be register"); 2538 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2539 assert(result->is_single_cpu(), "result must be register"); 2540 2541 // assert(left->destroys_register(), "check"); 2542 // assert(right->destroys_register(), "check"); 2543 2544 Register lreg = left->as_register(); 2545 Register dreg = result->as_register(); 2546 2547 if (right->is_constant()) { 2548 int divisor = right->as_constant_ptr()->as_jint(); 2549 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2550 if (code == lir_idiv) { 2551 assert(lreg == rax, "must be rax,"); 2552 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2553 __ cdql(); // sign extend into rdx:rax 2554 if (divisor == 2) { 2555 __ subl(lreg, rdx); 2556 } else { 2557 __ andl(rdx, divisor - 1); 2558 __ addl(lreg, rdx); 2559 } 2560 __ sarl(lreg, log2_intptr(divisor)); 2561 move_regs(lreg, dreg); 2562 } else if (code == lir_irem) { 2563 Label done; 2564 __ mov(dreg, lreg); 2565 __ andl(dreg, 0x80000000 | (divisor - 1)); 2566 __ jcc(Assembler::positive, done); 2567 __ decrement(dreg); 2568 __ orl(dreg, ~(divisor - 1)); 2569 __ increment(dreg); 2570 __ bind(done); 2571 } else { 2572 ShouldNotReachHere(); 2573 } 2574 } else { 2575 Register rreg = right->as_register(); 2576 assert(lreg == rax, "left register must be rax,"); 2577 assert(rreg != rdx, "right register must not be rdx"); 2578 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2579 2580 move_regs(lreg, rax); 2581 2582 int idivl_offset = __ corrected_idivl(rreg); 2583 add_debug_info_for_div0(idivl_offset, info); 2584 if (code == lir_irem) { 2585 move_regs(rdx, dreg); // result is in rdx 2586 } else { 2587 move_regs(rax, dreg); 2588 } 2589 } 2590 } 2591 2592 2593 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2594 if (opr1->is_single_cpu()) { 2595 Register reg1 = opr1->as_register(); 2596 if (opr2->is_single_cpu()) { 2597 // cpu register - cpu register 2598 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2599 __ cmpptr(reg1, opr2->as_register()); 2600 } else { 2601 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2602 __ cmpl(reg1, opr2->as_register()); 2603 } 2604 } else if (opr2->is_stack()) { 2605 // cpu register - stack 2606 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2607 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2608 } else { 2609 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2610 } 2611 } else if (opr2->is_constant()) { 2612 // cpu register - constant 2613 LIR_Const* c = opr2->as_constant_ptr(); 2614 if (c->type() == T_INT) { 2615 __ cmpl(reg1, c->as_jint()); 2616 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2617 // In 64bit oops are single register 2618 jobject o = c->as_jobject(); 2619 if (o == NULL) { 2620 __ cmpptr(reg1, (int32_t)NULL_WORD); 2621 } else { 2622 #ifdef _LP64 2623 __ movoop(rscratch1, o); 2624 __ cmpptr(reg1, rscratch1); 2625 #else 2626 __ cmpoop(reg1, c->as_jobject()); 2627 #endif // _LP64 2628 } 2629 } else { 2630 fatal("unexpected type: %s", basictype_to_str(c->type())); 2631 } 2632 // cpu register - address 2633 } else if (opr2->is_address()) { 2634 if (op->info() != NULL) { 2635 add_debug_info_for_null_check_here(op->info()); 2636 } 2637 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2638 } else { 2639 ShouldNotReachHere(); 2640 } 2641 2642 } else if(opr1->is_double_cpu()) { 2643 Register xlo = opr1->as_register_lo(); 2644 Register xhi = opr1->as_register_hi(); 2645 if (opr2->is_double_cpu()) { 2646 #ifdef _LP64 2647 __ cmpptr(xlo, opr2->as_register_lo()); 2648 #else 2649 // cpu register - cpu register 2650 Register ylo = opr2->as_register_lo(); 2651 Register yhi = opr2->as_register_hi(); 2652 __ subl(xlo, ylo); 2653 __ sbbl(xhi, yhi); 2654 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2655 __ orl(xhi, xlo); 2656 } 2657 #endif // _LP64 2658 } else if (opr2->is_constant()) { 2659 // cpu register - constant 0 2660 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2661 #ifdef _LP64 2662 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2663 #else 2664 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2665 __ orl(xhi, xlo); 2666 #endif // _LP64 2667 } else { 2668 ShouldNotReachHere(); 2669 } 2670 2671 } else if (opr1->is_single_xmm()) { 2672 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2673 if (opr2->is_single_xmm()) { 2674 // xmm register - xmm register 2675 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2676 } else if (opr2->is_stack()) { 2677 // xmm register - stack 2678 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2679 } else if (opr2->is_constant()) { 2680 // xmm register - constant 2681 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2682 } else if (opr2->is_address()) { 2683 // xmm register - address 2684 if (op->info() != NULL) { 2685 add_debug_info_for_null_check_here(op->info()); 2686 } 2687 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2688 } else { 2689 ShouldNotReachHere(); 2690 } 2691 2692 } else if (opr1->is_double_xmm()) { 2693 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2694 if (opr2->is_double_xmm()) { 2695 // xmm register - xmm register 2696 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2697 } else if (opr2->is_stack()) { 2698 // xmm register - stack 2699 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2700 } else if (opr2->is_constant()) { 2701 // xmm register - constant 2702 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2703 } else if (opr2->is_address()) { 2704 // xmm register - address 2705 if (op->info() != NULL) { 2706 add_debug_info_for_null_check_here(op->info()); 2707 } 2708 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2709 } else { 2710 ShouldNotReachHere(); 2711 } 2712 2713 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2714 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2715 assert(opr2->is_fpu_register(), "both must be registers"); 2716 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2717 2718 } else if (opr1->is_address() && opr2->is_constant()) { 2719 LIR_Const* c = opr2->as_constant_ptr(); 2720 #ifdef _LP64 2721 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2722 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2723 __ movoop(rscratch1, c->as_jobject()); 2724 } 2725 #endif // LP64 2726 if (op->info() != NULL) { 2727 add_debug_info_for_null_check_here(op->info()); 2728 } 2729 // special case: address - constant 2730 LIR_Address* addr = opr1->as_address_ptr(); 2731 if (c->type() == T_INT) { 2732 __ cmpl(as_Address(addr), c->as_jint()); 2733 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2734 #ifdef _LP64 2735 // %%% Make this explode if addr isn't reachable until we figure out a 2736 // better strategy by giving noreg as the temp for as_Address 2737 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2738 #else 2739 __ cmpoop(as_Address(addr), c->as_jobject()); 2740 #endif // _LP64 2741 } else { 2742 ShouldNotReachHere(); 2743 } 2744 2745 } else { 2746 ShouldNotReachHere(); 2747 } 2748 } 2749 2750 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2751 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2752 if (left->is_single_xmm()) { 2753 assert(right->is_single_xmm(), "must match"); 2754 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2755 } else if (left->is_double_xmm()) { 2756 assert(right->is_double_xmm(), "must match"); 2757 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2758 2759 } else { 2760 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2761 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2762 2763 assert(left->fpu() == 0, "left must be on TOS"); 2764 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2765 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2766 } 2767 } else { 2768 assert(code == lir_cmp_l2i, "check"); 2769 #ifdef _LP64 2770 Label done; 2771 Register dest = dst->as_register(); 2772 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2773 __ movl(dest, -1); 2774 __ jccb(Assembler::less, done); 2775 __ set_byte_if_not_zero(dest); 2776 __ movzbl(dest, dest); 2777 __ bind(done); 2778 #else 2779 __ lcmp2int(left->as_register_hi(), 2780 left->as_register_lo(), 2781 right->as_register_hi(), 2782 right->as_register_lo()); 2783 move_regs(left->as_register_hi(), dst->as_register()); 2784 #endif // _LP64 2785 } 2786 } 2787 2788 2789 void LIR_Assembler::align_call(LIR_Code code) { 2790 if (os::is_MP()) { 2791 // make sure that the displacement word of the call ends up word aligned 2792 int offset = __ offset(); 2793 switch (code) { 2794 case lir_static_call: 2795 case lir_optvirtual_call: 2796 case lir_dynamic_call: 2797 offset += NativeCall::displacement_offset; 2798 break; 2799 case lir_icvirtual_call: 2800 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2801 break; 2802 case lir_virtual_call: // currently, sparc-specific for niagara 2803 default: ShouldNotReachHere(); 2804 } 2805 __ align(BytesPerWord, offset); 2806 } 2807 } 2808 2809 2810 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2811 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2812 "must be aligned"); 2813 __ call(AddressLiteral(op->addr(), rtype)); 2814 add_call_info(code_offset(), op->info()); 2815 } 2816 2817 2818 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2819 __ ic_call(op->addr()); 2820 add_call_info(code_offset(), op->info()); 2821 assert(!os::is_MP() || 2822 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2823 "must be aligned"); 2824 } 2825 2826 2827 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2828 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2829 ShouldNotReachHere(); 2830 } 2831 2832 2833 void LIR_Assembler::emit_static_call_stub() { 2834 address call_pc = __ pc(); 2835 address stub = __ start_a_stub(call_stub_size()); 2836 if (stub == NULL) { 2837 bailout("static call stub overflow"); 2838 return; 2839 } 2840 2841 int start = __ offset(); 2842 if (os::is_MP()) { 2843 // make sure that the displacement word of the call ends up word aligned 2844 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2845 } 2846 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2847 __ mov_metadata(rbx, (Metadata*)NULL); 2848 // must be set to -1 at code generation time 2849 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2850 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2851 __ jump(RuntimeAddress(__ pc())); 2852 2853 if (UseAOT) { 2854 // Trampoline to aot code 2855 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2856 #ifdef _LP64 2857 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2858 #else 2859 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2860 #endif 2861 __ jmp(rax); 2862 } 2863 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2864 __ end_a_stub(); 2865 } 2866 2867 2868 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2869 assert(exceptionOop->as_register() == rax, "must match"); 2870 assert(exceptionPC->as_register() == rdx, "must match"); 2871 2872 // exception object is not added to oop map by LinearScan 2873 // (LinearScan assumes that no oops are in fixed registers) 2874 info->add_register_oop(exceptionOop); 2875 Runtime1::StubID unwind_id; 2876 2877 // get current pc information 2878 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2879 int pc_for_athrow_offset = __ offset(); 2880 InternalAddress pc_for_athrow(__ pc()); 2881 __ lea(exceptionPC->as_register(), pc_for_athrow); 2882 add_call_info(pc_for_athrow_offset, info); // for exception handler 2883 2884 __ verify_not_null_oop(rax); 2885 // search an exception handler (rax: exception oop, rdx: throwing pc) 2886 if (compilation()->has_fpu_code()) { 2887 unwind_id = Runtime1::handle_exception_id; 2888 } else { 2889 unwind_id = Runtime1::handle_exception_nofpu_id; 2890 } 2891 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2892 2893 // enough room for two byte trap 2894 __ nop(); 2895 } 2896 2897 2898 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2899 assert(exceptionOop->as_register() == rax, "must match"); 2900 2901 __ jmp(_unwind_handler_entry); 2902 } 2903 2904 2905 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2906 2907 // optimized version for linear scan: 2908 // * count must be already in ECX (guaranteed by LinearScan) 2909 // * left and dest must be equal 2910 // * tmp must be unused 2911 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2912 assert(left == dest, "left and dest must be equal"); 2913 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2914 2915 if (left->is_single_cpu()) { 2916 Register value = left->as_register(); 2917 assert(value != SHIFT_count, "left cannot be ECX"); 2918 2919 switch (code) { 2920 case lir_shl: __ shll(value); break; 2921 case lir_shr: __ sarl(value); break; 2922 case lir_ushr: __ shrl(value); break; 2923 default: ShouldNotReachHere(); 2924 } 2925 } else if (left->is_double_cpu()) { 2926 Register lo = left->as_register_lo(); 2927 Register hi = left->as_register_hi(); 2928 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2929 #ifdef _LP64 2930 switch (code) { 2931 case lir_shl: __ shlptr(lo); break; 2932 case lir_shr: __ sarptr(lo); break; 2933 case lir_ushr: __ shrptr(lo); break; 2934 default: ShouldNotReachHere(); 2935 } 2936 #else 2937 2938 switch (code) { 2939 case lir_shl: __ lshl(hi, lo); break; 2940 case lir_shr: __ lshr(hi, lo, true); break; 2941 case lir_ushr: __ lshr(hi, lo, false); break; 2942 default: ShouldNotReachHere(); 2943 } 2944 #endif // LP64 2945 } else { 2946 ShouldNotReachHere(); 2947 } 2948 } 2949 2950 2951 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2952 if (dest->is_single_cpu()) { 2953 // first move left into dest so that left is not destroyed by the shift 2954 Register value = dest->as_register(); 2955 count = count & 0x1F; // Java spec 2956 2957 move_regs(left->as_register(), value); 2958 switch (code) { 2959 case lir_shl: __ shll(value, count); break; 2960 case lir_shr: __ sarl(value, count); break; 2961 case lir_ushr: __ shrl(value, count); break; 2962 default: ShouldNotReachHere(); 2963 } 2964 } else if (dest->is_double_cpu()) { 2965 #ifndef _LP64 2966 Unimplemented(); 2967 #else 2968 // first move left into dest so that left is not destroyed by the shift 2969 Register value = dest->as_register_lo(); 2970 count = count & 0x1F; // Java spec 2971 2972 move_regs(left->as_register_lo(), value); 2973 switch (code) { 2974 case lir_shl: __ shlptr(value, count); break; 2975 case lir_shr: __ sarptr(value, count); break; 2976 case lir_ushr: __ shrptr(value, count); break; 2977 default: ShouldNotReachHere(); 2978 } 2979 #endif // _LP64 2980 } else { 2981 ShouldNotReachHere(); 2982 } 2983 } 2984 2985 2986 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2987 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2988 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2989 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2990 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2991 } 2992 2993 2994 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2995 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2996 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2997 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2998 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 2999 } 3000 3001 3002 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3003 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3004 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3005 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3006 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3007 } 3008 3009 3010 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3014 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3015 } 3016 3017 3018 // This code replaces a call to arraycopy; no exception may 3019 // be thrown in this code, they must be thrown in the System.arraycopy 3020 // activation frame; we could save some checks if this would not be the case 3021 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3022 ciArrayKlass* default_type = op->expected_type(); 3023 Register src = op->src()->as_register(); 3024 Register dst = op->dst()->as_register(); 3025 Register src_pos = op->src_pos()->as_register(); 3026 Register dst_pos = op->dst_pos()->as_register(); 3027 Register length = op->length()->as_register(); 3028 Register tmp = op->tmp()->as_register(); 3029 3030 CodeStub* stub = op->stub(); 3031 int flags = op->flags(); 3032 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3033 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3034 3035 // if we don't know anything, just go through the generic arraycopy 3036 if (default_type == NULL) { 3037 Label done; 3038 // save outgoing arguments on stack in case call to System.arraycopy is needed 3039 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3040 // for interpreter calling conventions. Now we have to do it in new style conventions. 3041 // For the moment until C1 gets the new register allocator I just force all the 3042 // args to the right place (except the register args) and then on the back side 3043 // reload the register args properly if we go slow path. Yuck 3044 3045 // These are proper for the calling convention 3046 store_parameter(length, 2); 3047 store_parameter(dst_pos, 1); 3048 store_parameter(dst, 0); 3049 3050 // these are just temporary placements until we need to reload 3051 store_parameter(src_pos, 3); 3052 store_parameter(src, 4); 3053 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3054 3055 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3056 3057 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3058 3059 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3060 #ifdef _LP64 3061 // The arguments are in java calling convention so we can trivially shift them to C 3062 // convention 3063 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3064 __ mov(c_rarg0, j_rarg0); 3065 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3066 __ mov(c_rarg1, j_rarg1); 3067 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3068 __ mov(c_rarg2, j_rarg2); 3069 assert_different_registers(c_rarg3, j_rarg4); 3070 __ mov(c_rarg3, j_rarg3); 3071 #ifdef _WIN64 3072 // Allocate abi space for args but be sure to keep stack aligned 3073 __ subptr(rsp, 6*wordSize); 3074 store_parameter(j_rarg4, 4); 3075 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3076 __ call(RuntimeAddress(C_entry)); 3077 } else { 3078 #ifndef PRODUCT 3079 if (PrintC1Statistics) { 3080 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3081 } 3082 #endif 3083 __ call(RuntimeAddress(copyfunc_addr)); 3084 } 3085 __ addptr(rsp, 6*wordSize); 3086 #else 3087 __ mov(c_rarg4, j_rarg4); 3088 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3089 __ call(RuntimeAddress(C_entry)); 3090 } else { 3091 #ifndef PRODUCT 3092 if (PrintC1Statistics) { 3093 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3094 } 3095 #endif 3096 __ call(RuntimeAddress(copyfunc_addr)); 3097 } 3098 #endif // _WIN64 3099 #else 3100 __ push(length); 3101 __ push(dst_pos); 3102 __ push(dst); 3103 __ push(src_pos); 3104 __ push(src); 3105 3106 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3107 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3108 } else { 3109 #ifndef PRODUCT 3110 if (PrintC1Statistics) { 3111 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3112 } 3113 #endif 3114 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3115 } 3116 3117 #endif // _LP64 3118 3119 __ cmpl(rax, 0); 3120 __ jcc(Assembler::equal, *stub->continuation()); 3121 3122 if (copyfunc_addr != NULL) { 3123 __ mov(tmp, rax); 3124 __ xorl(tmp, -1); 3125 } 3126 3127 // Reload values from the stack so they are where the stub 3128 // expects them. 3129 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3130 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3131 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3132 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3133 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3134 3135 if (copyfunc_addr != NULL) { 3136 __ subl(length, tmp); 3137 __ addl(src_pos, tmp); 3138 __ addl(dst_pos, tmp); 3139 } 3140 __ jmp(*stub->entry()); 3141 3142 __ bind(*stub->continuation()); 3143 return; 3144 } 3145 3146 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3147 3148 int elem_size = type2aelembytes(basic_type); 3149 Address::ScaleFactor scale; 3150 3151 switch (elem_size) { 3152 case 1 : 3153 scale = Address::times_1; 3154 break; 3155 case 2 : 3156 scale = Address::times_2; 3157 break; 3158 case 4 : 3159 scale = Address::times_4; 3160 break; 3161 case 8 : 3162 scale = Address::times_8; 3163 break; 3164 default: 3165 scale = Address::no_scale; 3166 ShouldNotReachHere(); 3167 } 3168 3169 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3170 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3171 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3172 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3173 3174 // length and pos's are all sign extended at this point on 64bit 3175 3176 // test for NULL 3177 if (flags & LIR_OpArrayCopy::src_null_check) { 3178 __ testptr(src, src); 3179 __ jcc(Assembler::zero, *stub->entry()); 3180 } 3181 if (flags & LIR_OpArrayCopy::dst_null_check) { 3182 __ testptr(dst, dst); 3183 __ jcc(Assembler::zero, *stub->entry()); 3184 } 3185 3186 // If the compiler was not able to prove that exact type of the source or the destination 3187 // of the arraycopy is an array type, check at runtime if the source or the destination is 3188 // an instance type. 3189 if (flags & LIR_OpArrayCopy::type_check) { 3190 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3191 __ load_klass(tmp, dst); 3192 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3193 __ jcc(Assembler::greaterEqual, *stub->entry()); 3194 } 3195 3196 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3197 __ load_klass(tmp, src); 3198 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3199 __ jcc(Assembler::greaterEqual, *stub->entry()); 3200 } 3201 } 3202 3203 // check if negative 3204 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3205 __ testl(src_pos, src_pos); 3206 __ jcc(Assembler::less, *stub->entry()); 3207 } 3208 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3209 __ testl(dst_pos, dst_pos); 3210 __ jcc(Assembler::less, *stub->entry()); 3211 } 3212 3213 if (flags & LIR_OpArrayCopy::src_range_check) { 3214 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3215 __ cmpl(tmp, src_length_addr); 3216 __ jcc(Assembler::above, *stub->entry()); 3217 } 3218 if (flags & LIR_OpArrayCopy::dst_range_check) { 3219 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3220 __ cmpl(tmp, dst_length_addr); 3221 __ jcc(Assembler::above, *stub->entry()); 3222 } 3223 3224 if (flags & LIR_OpArrayCopy::length_positive_check) { 3225 __ testl(length, length); 3226 __ jcc(Assembler::less, *stub->entry()); 3227 } 3228 3229 #ifdef _LP64 3230 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3231 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3232 #endif 3233 3234 if (flags & LIR_OpArrayCopy::type_check) { 3235 // We don't know the array types are compatible 3236 if (basic_type != T_OBJECT) { 3237 // Simple test for basic type arrays 3238 if (UseCompressedClassPointers) { 3239 __ movl(tmp, src_klass_addr); 3240 __ cmpl(tmp, dst_klass_addr); 3241 } else { 3242 __ movptr(tmp, src_klass_addr); 3243 __ cmpptr(tmp, dst_klass_addr); 3244 } 3245 __ jcc(Assembler::notEqual, *stub->entry()); 3246 } else { 3247 // For object arrays, if src is a sub class of dst then we can 3248 // safely do the copy. 3249 Label cont, slow; 3250 3251 __ push(src); 3252 __ push(dst); 3253 3254 __ load_klass(src, src); 3255 __ load_klass(dst, dst); 3256 3257 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3258 3259 __ push(src); 3260 __ push(dst); 3261 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3262 __ pop(dst); 3263 __ pop(src); 3264 3265 __ cmpl(src, 0); 3266 __ jcc(Assembler::notEqual, cont); 3267 3268 __ bind(slow); 3269 __ pop(dst); 3270 __ pop(src); 3271 3272 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3273 if (copyfunc_addr != NULL) { // use stub if available 3274 // src is not a sub class of dst so we have to do a 3275 // per-element check. 3276 3277 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3278 if ((flags & mask) != mask) { 3279 // Check that at least both of them object arrays. 3280 assert(flags & mask, "one of the two should be known to be an object array"); 3281 3282 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3283 __ load_klass(tmp, src); 3284 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3285 __ load_klass(tmp, dst); 3286 } 3287 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3288 Address klass_lh_addr(tmp, lh_offset); 3289 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3290 __ cmpl(klass_lh_addr, objArray_lh); 3291 __ jcc(Assembler::notEqual, *stub->entry()); 3292 } 3293 3294 // Spill because stubs can use any register they like and it's 3295 // easier to restore just those that we care about. 3296 store_parameter(dst, 0); 3297 store_parameter(dst_pos, 1); 3298 store_parameter(length, 2); 3299 store_parameter(src_pos, 3); 3300 store_parameter(src, 4); 3301 3302 #ifndef _LP64 3303 __ movptr(tmp, dst_klass_addr); 3304 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3305 __ push(tmp); 3306 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3307 __ push(tmp); 3308 __ push(length); 3309 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3310 __ push(tmp); 3311 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3312 __ push(tmp); 3313 3314 __ call_VM_leaf(copyfunc_addr, 5); 3315 #else 3316 __ movl2ptr(length, length); //higher 32bits must be null 3317 3318 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3319 assert_different_registers(c_rarg0, dst, dst_pos, length); 3320 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3321 assert_different_registers(c_rarg1, dst, length); 3322 3323 __ mov(c_rarg2, length); 3324 assert_different_registers(c_rarg2, dst); 3325 3326 #ifdef _WIN64 3327 // Allocate abi space for args but be sure to keep stack aligned 3328 __ subptr(rsp, 6*wordSize); 3329 __ load_klass(c_rarg3, dst); 3330 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3331 store_parameter(c_rarg3, 4); 3332 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3333 __ call(RuntimeAddress(copyfunc_addr)); 3334 __ addptr(rsp, 6*wordSize); 3335 #else 3336 __ load_klass(c_rarg4, dst); 3337 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3338 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3339 __ call(RuntimeAddress(copyfunc_addr)); 3340 #endif 3341 3342 #endif 3343 3344 #ifndef PRODUCT 3345 if (PrintC1Statistics) { 3346 Label failed; 3347 __ testl(rax, rax); 3348 __ jcc(Assembler::notZero, failed); 3349 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3350 __ bind(failed); 3351 } 3352 #endif 3353 3354 __ testl(rax, rax); 3355 __ jcc(Assembler::zero, *stub->continuation()); 3356 3357 #ifndef PRODUCT 3358 if (PrintC1Statistics) { 3359 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3360 } 3361 #endif 3362 3363 __ mov(tmp, rax); 3364 3365 __ xorl(tmp, -1); 3366 3367 // Restore previously spilled arguments 3368 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3369 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3370 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3371 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3372 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3373 3374 3375 __ subl(length, tmp); 3376 __ addl(src_pos, tmp); 3377 __ addl(dst_pos, tmp); 3378 } 3379 3380 __ jmp(*stub->entry()); 3381 3382 __ bind(cont); 3383 __ pop(dst); 3384 __ pop(src); 3385 } 3386 } 3387 3388 #ifdef ASSERT 3389 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3390 // Sanity check the known type with the incoming class. For the 3391 // primitive case the types must match exactly with src.klass and 3392 // dst.klass each exactly matching the default type. For the 3393 // object array case, if no type check is needed then either the 3394 // dst type is exactly the expected type and the src type is a 3395 // subtype which we can't check or src is the same array as dst 3396 // but not necessarily exactly of type default_type. 3397 Label known_ok, halt; 3398 __ mov_metadata(tmp, default_type->constant_encoding()); 3399 #ifdef _LP64 3400 if (UseCompressedClassPointers) { 3401 __ encode_klass_not_null(tmp); 3402 } 3403 #endif 3404 3405 if (basic_type != T_OBJECT) { 3406 3407 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3408 else __ cmpptr(tmp, dst_klass_addr); 3409 __ jcc(Assembler::notEqual, halt); 3410 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3411 else __ cmpptr(tmp, src_klass_addr); 3412 __ jcc(Assembler::equal, known_ok); 3413 } else { 3414 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3415 else __ cmpptr(tmp, dst_klass_addr); 3416 __ jcc(Assembler::equal, known_ok); 3417 __ cmpptr(src, dst); 3418 __ jcc(Assembler::equal, known_ok); 3419 } 3420 __ bind(halt); 3421 __ stop("incorrect type information in arraycopy"); 3422 __ bind(known_ok); 3423 } 3424 #endif 3425 3426 #ifndef PRODUCT 3427 if (PrintC1Statistics) { 3428 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3429 } 3430 #endif 3431 3432 #ifdef _LP64 3433 assert_different_registers(c_rarg0, dst, dst_pos, length); 3434 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3435 assert_different_registers(c_rarg1, length); 3436 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3437 __ mov(c_rarg2, length); 3438 3439 #else 3440 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3441 store_parameter(tmp, 0); 3442 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3443 store_parameter(tmp, 1); 3444 store_parameter(length, 2); 3445 #endif // _LP64 3446 3447 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3448 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3449 const char *name; 3450 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3451 __ call_VM_leaf(entry, 0); 3452 3453 __ bind(*stub->continuation()); 3454 } 3455 3456 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3457 assert(op->crc()->is_single_cpu(), "crc must be register"); 3458 assert(op->val()->is_single_cpu(), "byte value must be register"); 3459 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3460 Register crc = op->crc()->as_register(); 3461 Register val = op->val()->as_register(); 3462 Register res = op->result_opr()->as_register(); 3463 3464 assert_different_registers(val, crc, res); 3465 3466 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3467 __ notl(crc); // ~crc 3468 __ update_byte_crc32(crc, val, res); 3469 __ notl(crc); // ~crc 3470 __ mov(res, crc); 3471 } 3472 3473 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3474 Register obj = op->obj_opr()->as_register(); // may not be an oop 3475 Register hdr = op->hdr_opr()->as_register(); 3476 Register lock = op->lock_opr()->as_register(); 3477 if (!UseFastLocking) { 3478 __ jmp(*op->stub()->entry()); 3479 } else if (op->code() == lir_lock) { 3480 Register scratch = noreg; 3481 if (UseBiasedLocking) { 3482 scratch = op->scratch_opr()->as_register(); 3483 } 3484 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3485 // add debug info for NullPointerException only if one is possible 3486 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3487 if (op->info() != NULL) { 3488 add_debug_info_for_null_check(null_check_offset, op->info()); 3489 } 3490 // done 3491 } else if (op->code() == lir_unlock) { 3492 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3493 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3494 } else { 3495 Unimplemented(); 3496 } 3497 __ bind(*op->stub()->continuation()); 3498 } 3499 3500 3501 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3502 ciMethod* method = op->profiled_method(); 3503 int bci = op->profiled_bci(); 3504 ciMethod* callee = op->profiled_callee(); 3505 3506 // Update counter for all call types 3507 ciMethodData* md = method->method_data_or_null(); 3508 assert(md != NULL, "Sanity"); 3509 ciProfileData* data = md->bci_to_data(bci); 3510 assert(data->is_CounterData(), "need CounterData for calls"); 3511 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3512 Register mdo = op->mdo()->as_register(); 3513 __ mov_metadata(mdo, md->constant_encoding()); 3514 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3515 Bytecodes::Code bc = method->java_code_at_bci(bci); 3516 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 3517 // Perform additional virtual call profiling for invokevirtual and 3518 // invokeinterface bytecodes 3519 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3520 !callee_is_static && // required for optimized MH invokes 3521 C1ProfileVirtualCalls) { 3522 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3523 Register recv = op->recv()->as_register(); 3524 assert_different_registers(mdo, recv); 3525 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3526 ciKlass* known_klass = op->known_holder(); 3527 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3528 // We know the type that will be seen at this call site; we can 3529 // statically update the MethodData* rather than needing to do 3530 // dynamic tests on the receiver type 3531 3532 // NOTE: we should probably put a lock around this search to 3533 // avoid collisions by concurrent compilations 3534 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3535 uint i; 3536 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3537 ciKlass* receiver = vc_data->receiver(i); 3538 if (known_klass->equals(receiver)) { 3539 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3540 __ addptr(data_addr, DataLayout::counter_increment); 3541 return; 3542 } 3543 } 3544 3545 // Receiver type not found in profile data; select an empty slot 3546 3547 // Note that this is less efficient than it should be because it 3548 // always does a write to the receiver part of the 3549 // VirtualCallData rather than just the first time 3550 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3551 ciKlass* receiver = vc_data->receiver(i); 3552 if (receiver == NULL) { 3553 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3554 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3555 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3556 __ addptr(data_addr, DataLayout::counter_increment); 3557 return; 3558 } 3559 } 3560 } else { 3561 __ load_klass(recv, recv); 3562 Label update_done; 3563 type_profile_helper(mdo, md, data, recv, &update_done); 3564 // Receiver did not match any saved receiver and there is no empty row for it. 3565 // Increment total counter to indicate polymorphic case. 3566 __ addptr(counter_addr, DataLayout::counter_increment); 3567 3568 __ bind(update_done); 3569 } 3570 } else { 3571 // Static call 3572 __ addptr(counter_addr, DataLayout::counter_increment); 3573 } 3574 } 3575 3576 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3577 Register obj = op->obj()->as_register(); 3578 Register tmp = op->tmp()->as_pointer_register(); 3579 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3580 ciKlass* exact_klass = op->exact_klass(); 3581 intptr_t current_klass = op->current_klass(); 3582 bool not_null = op->not_null(); 3583 bool no_conflict = op->no_conflict(); 3584 3585 Label update, next, none; 3586 3587 bool do_null = !not_null; 3588 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3589 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3590 3591 assert(do_null || do_update, "why are we here?"); 3592 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3593 3594 __ verify_oop(obj); 3595 3596 if (tmp != obj) { 3597 __ mov(tmp, obj); 3598 } 3599 if (do_null) { 3600 __ testptr(tmp, tmp); 3601 __ jccb(Assembler::notZero, update); 3602 if (!TypeEntries::was_null_seen(current_klass)) { 3603 __ orptr(mdo_addr, TypeEntries::null_seen); 3604 } 3605 if (do_update) { 3606 #ifndef ASSERT 3607 __ jmpb(next); 3608 } 3609 #else 3610 __ jmp(next); 3611 } 3612 } else { 3613 __ testptr(tmp, tmp); 3614 __ jccb(Assembler::notZero, update); 3615 __ stop("unexpect null obj"); 3616 #endif 3617 } 3618 3619 __ bind(update); 3620 3621 if (do_update) { 3622 #ifdef ASSERT 3623 if (exact_klass != NULL) { 3624 Label ok; 3625 __ load_klass(tmp, tmp); 3626 __ push(tmp); 3627 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3628 __ cmpptr(tmp, Address(rsp, 0)); 3629 __ jccb(Assembler::equal, ok); 3630 __ stop("exact klass and actual klass differ"); 3631 __ bind(ok); 3632 __ pop(tmp); 3633 } 3634 #endif 3635 if (!no_conflict) { 3636 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3637 if (exact_klass != NULL) { 3638 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3639 } else { 3640 __ load_klass(tmp, tmp); 3641 } 3642 3643 __ xorptr(tmp, mdo_addr); 3644 __ testptr(tmp, TypeEntries::type_klass_mask); 3645 // klass seen before, nothing to do. The unknown bit may have been 3646 // set already but no need to check. 3647 __ jccb(Assembler::zero, next); 3648 3649 __ testptr(tmp, TypeEntries::type_unknown); 3650 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3651 3652 if (TypeEntries::is_type_none(current_klass)) { 3653 __ cmpptr(mdo_addr, 0); 3654 __ jccb(Assembler::equal, none); 3655 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3656 __ jccb(Assembler::equal, none); 3657 // There is a chance that the checks above (re-reading profiling 3658 // data from memory) fail if another thread has just set the 3659 // profiling to this obj's klass 3660 __ xorptr(tmp, mdo_addr); 3661 __ testptr(tmp, TypeEntries::type_klass_mask); 3662 __ jccb(Assembler::zero, next); 3663 } 3664 } else { 3665 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3666 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3667 3668 __ movptr(tmp, mdo_addr); 3669 __ testptr(tmp, TypeEntries::type_unknown); 3670 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3671 } 3672 3673 // different than before. Cannot keep accurate profile. 3674 __ orptr(mdo_addr, TypeEntries::type_unknown); 3675 3676 if (TypeEntries::is_type_none(current_klass)) { 3677 __ jmpb(next); 3678 3679 __ bind(none); 3680 // first time here. Set profile type. 3681 __ movptr(mdo_addr, tmp); 3682 } 3683 } else { 3684 // There's a single possible klass at this profile point 3685 assert(exact_klass != NULL, "should be"); 3686 if (TypeEntries::is_type_none(current_klass)) { 3687 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3688 __ xorptr(tmp, mdo_addr); 3689 __ testptr(tmp, TypeEntries::type_klass_mask); 3690 #ifdef ASSERT 3691 __ jcc(Assembler::zero, next); 3692 3693 { 3694 Label ok; 3695 __ push(tmp); 3696 __ cmpptr(mdo_addr, 0); 3697 __ jcc(Assembler::equal, ok); 3698 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3699 __ jcc(Assembler::equal, ok); 3700 // may have been set by another thread 3701 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3702 __ xorptr(tmp, mdo_addr); 3703 __ testptr(tmp, TypeEntries::type_mask); 3704 __ jcc(Assembler::zero, ok); 3705 3706 __ stop("unexpected profiling mismatch"); 3707 __ bind(ok); 3708 __ pop(tmp); 3709 } 3710 #else 3711 __ jccb(Assembler::zero, next); 3712 #endif 3713 // first time here. Set profile type. 3714 __ movptr(mdo_addr, tmp); 3715 } else { 3716 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3717 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3718 3719 __ movptr(tmp, mdo_addr); 3720 __ testptr(tmp, TypeEntries::type_unknown); 3721 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3722 3723 __ orptr(mdo_addr, TypeEntries::type_unknown); 3724 } 3725 } 3726 3727 __ bind(next); 3728 } 3729 } 3730 3731 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3732 Unimplemented(); 3733 } 3734 3735 3736 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3737 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3738 } 3739 3740 3741 void LIR_Assembler::align_backward_branch_target() { 3742 __ align(BytesPerWord); 3743 } 3744 3745 3746 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3747 if (left->is_single_cpu()) { 3748 __ negl(left->as_register()); 3749 move_regs(left->as_register(), dest->as_register()); 3750 3751 } else if (left->is_double_cpu()) { 3752 Register lo = left->as_register_lo(); 3753 #ifdef _LP64 3754 Register dst = dest->as_register_lo(); 3755 __ movptr(dst, lo); 3756 __ negptr(dst); 3757 #else 3758 Register hi = left->as_register_hi(); 3759 __ lneg(hi, lo); 3760 if (dest->as_register_lo() == hi) { 3761 assert(dest->as_register_hi() != lo, "destroying register"); 3762 move_regs(hi, dest->as_register_hi()); 3763 move_regs(lo, dest->as_register_lo()); 3764 } else { 3765 move_regs(lo, dest->as_register_lo()); 3766 move_regs(hi, dest->as_register_hi()); 3767 } 3768 #endif // _LP64 3769 3770 } else if (dest->is_single_xmm()) { 3771 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3772 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3773 } 3774 if (UseAVX > 0) { 3775 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3776 ExternalAddress((address)float_signflip_pool)); 3777 } else { 3778 __ xorps(dest->as_xmm_float_reg(), 3779 ExternalAddress((address)float_signflip_pool)); 3780 } 3781 } else if (dest->is_double_xmm()) { 3782 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3783 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3784 } 3785 if (UseAVX > 0) { 3786 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3787 ExternalAddress((address)double_signflip_pool)); 3788 } else { 3789 __ xorpd(dest->as_xmm_double_reg(), 3790 ExternalAddress((address)double_signflip_pool)); 3791 } 3792 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3793 assert(left->fpu() == 0, "arg must be on TOS"); 3794 assert(dest->fpu() == 0, "dest must be TOS"); 3795 __ fchs(); 3796 3797 } else { 3798 ShouldNotReachHere(); 3799 } 3800 } 3801 3802 3803 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3804 assert(addr->is_address() && dest->is_register(), "check"); 3805 Register reg; 3806 reg = dest->as_pointer_register(); 3807 __ lea(reg, as_Address(addr->as_address_ptr())); 3808 } 3809 3810 3811 3812 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3813 assert(!tmp->is_valid(), "don't need temporary"); 3814 __ call(RuntimeAddress(dest)); 3815 if (info != NULL) { 3816 add_call_info_here(info); 3817 } 3818 } 3819 3820 3821 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3822 assert(type == T_LONG, "only for volatile long fields"); 3823 3824 if (info != NULL) { 3825 add_debug_info_for_null_check_here(info); 3826 } 3827 3828 if (src->is_double_xmm()) { 3829 if (dest->is_double_cpu()) { 3830 #ifdef _LP64 3831 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3832 #else 3833 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3834 __ psrlq(src->as_xmm_double_reg(), 32); 3835 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3836 #endif // _LP64 3837 } else if (dest->is_double_stack()) { 3838 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3839 } else if (dest->is_address()) { 3840 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3841 } else { 3842 ShouldNotReachHere(); 3843 } 3844 3845 } else if (dest->is_double_xmm()) { 3846 if (src->is_double_stack()) { 3847 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3848 } else if (src->is_address()) { 3849 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3850 } else { 3851 ShouldNotReachHere(); 3852 } 3853 3854 } else if (src->is_double_fpu()) { 3855 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3856 if (dest->is_double_stack()) { 3857 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3858 } else if (dest->is_address()) { 3859 __ fistp_d(as_Address(dest->as_address_ptr())); 3860 } else { 3861 ShouldNotReachHere(); 3862 } 3863 3864 } else if (dest->is_double_fpu()) { 3865 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3866 if (src->is_double_stack()) { 3867 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3868 } else if (src->is_address()) { 3869 __ fild_d(as_Address(src->as_address_ptr())); 3870 } else { 3871 ShouldNotReachHere(); 3872 } 3873 } else { 3874 ShouldNotReachHere(); 3875 } 3876 } 3877 3878 #ifdef ASSERT 3879 // emit run-time assertion 3880 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3881 assert(op->code() == lir_assert, "must be"); 3882 3883 if (op->in_opr1()->is_valid()) { 3884 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3885 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3886 } else { 3887 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3888 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3889 } 3890 3891 Label ok; 3892 if (op->condition() != lir_cond_always) { 3893 Assembler::Condition acond = Assembler::zero; 3894 switch (op->condition()) { 3895 case lir_cond_equal: acond = Assembler::equal; break; 3896 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3897 case lir_cond_less: acond = Assembler::less; break; 3898 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3899 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3900 case lir_cond_greater: acond = Assembler::greater; break; 3901 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3902 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3903 default: ShouldNotReachHere(); 3904 } 3905 __ jcc(acond, ok); 3906 } 3907 if (op->halt()) { 3908 const char* str = __ code_string(op->msg()); 3909 __ stop(str); 3910 } else { 3911 breakpoint(); 3912 } 3913 __ bind(ok); 3914 } 3915 #endif 3916 3917 void LIR_Assembler::membar() { 3918 // QQQ sparc TSO uses this, 3919 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3920 } 3921 3922 void LIR_Assembler::membar_acquire() { 3923 // No x86 machines currently require load fences 3924 } 3925 3926 void LIR_Assembler::membar_release() { 3927 // No x86 machines currently require store fences 3928 } 3929 3930 void LIR_Assembler::membar_loadload() { 3931 // no-op 3932 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3933 } 3934 3935 void LIR_Assembler::membar_storestore() { 3936 // no-op 3937 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3938 } 3939 3940 void LIR_Assembler::membar_loadstore() { 3941 // no-op 3942 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3943 } 3944 3945 void LIR_Assembler::membar_storeload() { 3946 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3947 } 3948 3949 void LIR_Assembler::on_spin_wait() { 3950 __ pause (); 3951 } 3952 3953 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3954 assert(result_reg->is_register(), "check"); 3955 #ifdef _LP64 3956 // __ get_thread(result_reg->as_register_lo()); 3957 __ mov(result_reg->as_register(), r15_thread); 3958 #else 3959 __ get_thread(result_reg->as_register()); 3960 #endif // _LP64 3961 } 3962 3963 3964 void LIR_Assembler::peephole(LIR_List*) { 3965 // do nothing for now 3966 } 3967 3968 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3969 assert(data == dest, "xchg/xadd uses only 2 operands"); 3970 3971 if (data->type() == T_INT) { 3972 if (code == lir_xadd) { 3973 if (os::is_MP()) { 3974 __ lock(); 3975 } 3976 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3977 } else { 3978 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3979 } 3980 } else if (data->is_oop()) { 3981 assert (code == lir_xchg, "xadd for oops"); 3982 Register obj = data->as_register(); 3983 #ifdef _LP64 3984 if (UseCompressedOops) { 3985 __ encode_heap_oop(obj); 3986 __ xchgl(obj, as_Address(src->as_address_ptr())); 3987 __ decode_heap_oop(obj); 3988 } else { 3989 __ xchgptr(obj, as_Address(src->as_address_ptr())); 3990 } 3991 #else 3992 __ xchgl(obj, as_Address(src->as_address_ptr())); 3993 #endif 3994 } else if (data->type() == T_LONG) { 3995 #ifdef _LP64 3996 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 3997 if (code == lir_xadd) { 3998 if (os::is_MP()) { 3999 __ lock(); 4000 } 4001 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4002 } else { 4003 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4004 } 4005 #else 4006 ShouldNotReachHere(); 4007 #endif 4008 } else { 4009 ShouldNotReachHere(); 4010 } 4011 } 4012 4013 #undef __