1 //
2 // Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // The registers which can be used for
321 // a thread local safepoint poll
322 // * R12 is reserved for heap base
323 // * R13 cannot be encoded for addressing without an offset byte
324 // * R15 is reserved for the JavaThread
325 reg_class ptr_rex_reg(R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R14, R14_H);
330
331
332 // Class for all long registers (excluding RSP)
333 reg_class long_reg_with_rbp(RAX, RAX_H,
334 RDX, RDX_H,
335 RBP, RBP_H,
336 RDI, RDI_H,
337 RSI, RSI_H,
338 RCX, RCX_H,
339 RBX, RBX_H,
340 R8, R8_H,
341 R9, R9_H,
342 R10, R10_H,
343 R11, R11_H,
344 R13, R13_H,
345 R14, R14_H);
346
347 // Class for all long registers (excluding RSP and RBP)
348 reg_class long_reg_no_rbp(RAX, RAX_H,
349 RDX, RDX_H,
350 RDI, RDI_H,
351 RSI, RSI_H,
352 RCX, RCX_H,
353 RBX, RBX_H,
354 R8, R8_H,
355 R9, R9_H,
356 R10, R10_H,
357 R11, R11_H,
358 R13, R13_H,
359 R14, R14_H);
360
361 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
362 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
363
364 // Class for all long registers (excluding RAX, RDX and RSP)
365 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
366 RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
378 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
379 RSI, RSI_H,
380 RCX, RCX_H,
381 RBX, RBX_H,
382 R8, R8_H,
383 R9, R9_H,
384 R10, R10_H,
385 R11, R11_H,
386 R13, R13_H,
387 R14, R14_H);
388
389 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
390 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
391
392 // Class for all long registers (excluding RCX and RSP)
393 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
394 RDI, RDI_H,
395 RSI, RSI_H,
396 RAX, RAX_H,
397 RDX, RDX_H,
398 RBX, RBX_H,
399 R8, R8_H,
400 R9, R9_H,
401 R10, R10_H,
402 R11, R11_H,
403 R13, R13_H,
404 R14, R14_H);
405
406 // Class for all long registers (excluding RCX, RSP, and RBP)
407 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
408 RSI, RSI_H,
409 RAX, RAX_H,
410 RDX, RDX_H,
411 RBX, RBX_H,
412 R8, R8_H,
413 R9, R9_H,
414 R10, R10_H,
415 R11, R11_H,
416 R13, R13_H,
417 R14, R14_H);
418
419 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
420 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
421
422 // Singleton class for RAX long register
423 reg_class long_rax_reg(RAX, RAX_H);
424
425 // Singleton class for RCX long register
426 reg_class long_rcx_reg(RCX, RCX_H);
427
428 // Singleton class for RDX long register
429 reg_class long_rdx_reg(RDX, RDX_H);
430
431 // Class for all int registers (excluding RSP)
432 reg_class int_reg_with_rbp(RAX,
433 RDX,
434 RBP,
435 RDI,
436 RSI,
437 RCX,
438 RBX,
439 R8,
440 R9,
441 R10,
442 R11,
443 R13,
444 R14);
445
446 // Class for all int registers (excluding RSP and RBP)
447 reg_class int_reg_no_rbp(RAX,
448 RDX,
449 RDI,
450 RSI,
451 RCX,
452 RBX,
453 R8,
454 R9,
455 R10,
456 R11,
457 R13,
458 R14);
459
460 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
461 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
462
463 // Class for all int registers (excluding RCX and RSP)
464 reg_class int_no_rcx_reg_with_rbp(RAX,
465 RDX,
466 RBP,
467 RDI,
468 RSI,
469 RBX,
470 R8,
471 R9,
472 R10,
473 R11,
474 R13,
475 R14);
476
477 // Class for all int registers (excluding RCX, RSP, and RBP)
478 reg_class int_no_rcx_reg_no_rbp(RAX,
479 RDX,
480 RDI,
481 RSI,
482 RBX,
483 R8,
484 R9,
485 R10,
486 R11,
487 R13,
488 R14);
489
490 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
491 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
492
493 // Class for all int registers (excluding RAX, RDX, and RSP)
494 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
495 RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
507 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
508 RSI,
509 RCX,
510 RBX,
511 R8,
512 R9,
513 R10,
514 R11,
515 R13,
516 R14);
517
518 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
519 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
520
521 // Singleton class for RAX int register
522 reg_class int_rax_reg(RAX);
523
524 // Singleton class for RBX int register
525 reg_class int_rbx_reg(RBX);
526
527 // Singleton class for RCX int register
528 reg_class int_rcx_reg(RCX);
529
530 // Singleton class for RCX int register
531 reg_class int_rdx_reg(RDX);
532
533 // Singleton class for RCX int register
534 reg_class int_rdi_reg(RDI);
535
536 // Singleton class for instruction pointer
537 // reg_class ip_reg(RIP);
538
539 %}
540
541 //----------SOURCE BLOCK-------------------------------------------------------
542 // This is a block of C++ code which provides values, functions, and
543 // definitions necessary in the rest of the architecture description
544 source %{
545 #define RELOC_IMM64 Assembler::imm_operand
546 #define RELOC_DISP32 Assembler::disp32_operand
547
548 #define __ _masm.
549
550 static int clear_avx_size() {
551 return (VM_Version::supports_vzeroupper()) ? 3: 0; // vzeroupper
552 }
553
554 // !!!!! Special hack to get all types of calls to specify the byte offset
555 // from the start of the call to the point where the return address
556 // will point.
557 int MachCallStaticJavaNode::ret_addr_offset()
558 {
559 int offset = 5; // 5 bytes from start of call to where return address points
560 offset += clear_avx_size();
561 return offset;
562 }
563
564 int MachCallDynamicJavaNode::ret_addr_offset()
565 {
566 int offset = 15; // 15 bytes from start of call to where return address points
567 offset += clear_avx_size();
568 return offset;
569 }
570
571 int MachCallRuntimeNode::ret_addr_offset() {
572 int offset = 13; // movq r10,#addr; callq (r10)
573 offset += clear_avx_size();
574 return offset;
575 }
576
577 // Indicate if the safepoint node needs the polling page as an input,
578 // it does if the polling page is more than disp32 away.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
582 }
583
584 //
585 // Compute padding required for nodes which need alignment
586 //
587
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += clear_avx_size(); // skip vzeroupper
593 current_offset += 1; // skip call opcode byte
594 return align_up(current_offset, alignment_required()) - current_offset;
595 }
596
597 // The address of the call instruction needs to be 4-byte aligned to
598 // ensure that it does not span a cache line so that it can be patched.
599 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
600 {
601 current_offset += clear_avx_size(); // skip vzeroupper
602 current_offset += 11; // skip movq instruction + call opcode byte
603 return align_up(current_offset, alignment_required()) - current_offset;
604 }
605
606 // EMIT_RM()
607 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
608 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
609 cbuf.insts()->emit_int8(c);
610 }
611
612 // EMIT_CC()
613 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
614 unsigned char c = (unsigned char) (f1 | f2);
615 cbuf.insts()->emit_int8(c);
616 }
617
618 // EMIT_OPCODE()
619 void emit_opcode(CodeBuffer &cbuf, int code) {
620 cbuf.insts()->emit_int8((unsigned char) code);
621 }
622
623 // EMIT_OPCODE() w/ relocation information
624 void emit_opcode(CodeBuffer &cbuf,
625 int code, relocInfo::relocType reloc, int offset, int format)
626 {
627 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
628 emit_opcode(cbuf, code);
629 }
630
631 // EMIT_D8()
632 void emit_d8(CodeBuffer &cbuf, int d8) {
633 cbuf.insts()->emit_int8((unsigned char) d8);
634 }
635
636 // EMIT_D16()
637 void emit_d16(CodeBuffer &cbuf, int d16) {
638 cbuf.insts()->emit_int16(d16);
639 }
640
641 // EMIT_D32()
642 void emit_d32(CodeBuffer &cbuf, int d32) {
643 cbuf.insts()->emit_int32(d32);
644 }
645
646 // EMIT_D64()
647 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
648 cbuf.insts()->emit_int64(d64);
649 }
650
651 // emit 32 bit value and construct relocation entry from relocInfo::relocType
652 void emit_d32_reloc(CodeBuffer& cbuf,
653 int d32,
654 relocInfo::relocType reloc,
655 int format)
656 {
657 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
658 cbuf.relocate(cbuf.insts_mark(), reloc, format);
659 cbuf.insts()->emit_int32(d32);
660 }
661
662 // emit 32 bit value and construct relocation entry from RelocationHolder
663 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
664 #ifdef ASSERT
665 if (rspec.reloc()->type() == relocInfo::oop_type &&
666 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
667 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
668 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
669 }
670 #endif
671 cbuf.relocate(cbuf.insts_mark(), rspec, format);
672 cbuf.insts()->emit_int32(d32);
673 }
674
675 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
676 address next_ip = cbuf.insts_end() + 4;
677 emit_d32_reloc(cbuf, (int) (addr - next_ip),
678 external_word_Relocation::spec(addr),
679 RELOC_DISP32);
680 }
681
682
683 // emit 64 bit value and construct relocation entry from relocInfo::relocType
684 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
685 cbuf.relocate(cbuf.insts_mark(), reloc, format);
686 cbuf.insts()->emit_int64(d64);
687 }
688
689 // emit 64 bit value and construct relocation entry from RelocationHolder
690 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
691 #ifdef ASSERT
692 if (rspec.reloc()->type() == relocInfo::oop_type &&
693 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
694 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
695 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
696 "cannot embed scavengable oops in code");
697 }
698 #endif
699 cbuf.relocate(cbuf.insts_mark(), rspec, format);
700 cbuf.insts()->emit_int64(d64);
701 }
702
703 // Access stack slot for load or store
704 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
705 {
706 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
707 if (-0x80 <= disp && disp < 0x80) {
708 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
709 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
710 emit_d8(cbuf, disp); // Displacement // R/M byte
711 } else {
712 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
713 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
714 emit_d32(cbuf, disp); // Displacement // R/M byte
715 }
716 }
717
718 // rRegI ereg, memory mem) %{ // emit_reg_mem
719 void encode_RegMem(CodeBuffer &cbuf,
720 int reg,
721 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
722 {
723 assert(disp_reloc == relocInfo::none, "cannot have disp");
724 int regenc = reg & 7;
725 int baseenc = base & 7;
726 int indexenc = index & 7;
727
728 // There is no index & no scale, use form without SIB byte
729 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
730 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
731 if (disp == 0 && base != RBP_enc && base != R13_enc) {
732 emit_rm(cbuf, 0x0, regenc, baseenc); // *
733 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
734 // If 8-bit displacement, mode 0x1
735 emit_rm(cbuf, 0x1, regenc, baseenc); // *
736 emit_d8(cbuf, disp);
737 } else {
738 // If 32-bit displacement
739 if (base == -1) { // Special flag for absolute address
740 emit_rm(cbuf, 0x0, regenc, 0x5); // *
741 if (disp_reloc != relocInfo::none) {
742 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
743 } else {
744 emit_d32(cbuf, disp);
745 }
746 } else {
747 // Normal base + offset
748 emit_rm(cbuf, 0x2, regenc, baseenc); // *
749 if (disp_reloc != relocInfo::none) {
750 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
751 } else {
752 emit_d32(cbuf, disp);
753 }
754 }
755 }
756 } else {
757 // Else, encode with the SIB byte
758 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
759 if (disp == 0 && base != RBP_enc && base != R13_enc) {
760 // If no displacement
761 emit_rm(cbuf, 0x0, regenc, 0x4); // *
762 emit_rm(cbuf, scale, indexenc, baseenc);
763 } else {
764 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
765 // If 8-bit displacement, mode 0x1
766 emit_rm(cbuf, 0x1, regenc, 0x4); // *
767 emit_rm(cbuf, scale, indexenc, baseenc);
768 emit_d8(cbuf, disp);
769 } else {
770 // If 32-bit displacement
771 if (base == 0x04 ) {
772 emit_rm(cbuf, 0x2, regenc, 0x4);
773 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
774 } else {
775 emit_rm(cbuf, 0x2, regenc, 0x4);
776 emit_rm(cbuf, scale, indexenc, baseenc); // *
777 }
778 if (disp_reloc != relocInfo::none) {
779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
780 } else {
781 emit_d32(cbuf, disp);
782 }
783 }
784 }
785 }
786 }
787
788 // This could be in MacroAssembler but it's fairly C2 specific
789 void emit_cmpfp_fixup(MacroAssembler& _masm) {
790 Label exit;
791 __ jccb(Assembler::noParity, exit);
792 __ pushf();
793 //
794 // comiss/ucomiss instructions set ZF,PF,CF flags and
795 // zero OF,AF,SF for NaN values.
796 // Fixup flags by zeroing ZF,PF so that compare of NaN
797 // values returns 'less than' result (CF is set).
798 // Leave the rest of flags unchanged.
799 //
800 // 7 6 5 4 3 2 1 0
801 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
802 // 0 0 1 0 1 0 1 1 (0x2B)
803 //
804 __ andq(Address(rsp, 0), 0xffffff2b);
805 __ popf();
806 __ bind(exit);
807 }
808
809 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
810 Label done;
811 __ movl(dst, -1);
812 __ jcc(Assembler::parity, done);
813 __ jcc(Assembler::below, done);
814 __ setb(Assembler::notEqual, dst);
815 __ movzbl(dst, dst);
816 __ bind(done);
817 }
818
819
820 //=============================================================================
821 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
822
823 int Compile::ConstantTable::calculate_table_base_offset() const {
824 return 0; // absolute addressing, no offset
825 }
826
827 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
828 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
829 ShouldNotReachHere();
830 }
831
832 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
833 // Empty encoding
834 }
835
836 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
837 return 0;
838 }
839
840 #ifndef PRODUCT
841 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
842 st->print("# MachConstantBaseNode (empty encoding)");
843 }
844 #endif
845
846
847 //=============================================================================
848 #ifndef PRODUCT
849 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
850 Compile* C = ra_->C;
851
852 int framesize = C->frame_size_in_bytes();
853 int bangsize = C->bang_size_in_bytes();
854 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
855 // Remove wordSize for return addr which is already pushed.
856 framesize -= wordSize;
857
858 if (C->need_stack_bang(bangsize)) {
859 framesize -= wordSize;
860 st->print("# stack bang (%d bytes)", bangsize);
861 st->print("\n\t");
862 st->print("pushq rbp\t# Save rbp");
863 if (PreserveFramePointer) {
864 st->print("\n\t");
865 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
866 }
867 if (framesize) {
868 st->print("\n\t");
869 st->print("subq rsp, #%d\t# Create frame",framesize);
870 }
871 } else {
872 st->print("subq rsp, #%d\t# Create frame",framesize);
873 st->print("\n\t");
874 framesize -= wordSize;
875 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
876 if (PreserveFramePointer) {
877 st->print("\n\t");
878 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
879 if (framesize > 0) {
880 st->print("\n\t");
881 st->print("addq rbp, #%d", framesize);
882 }
883 }
884 }
885
886 if (VerifyStackAtCalls) {
887 st->print("\n\t");
888 framesize -= wordSize;
889 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
890 #ifdef ASSERT
891 st->print("\n\t");
892 st->print("# stack alignment check");
893 #endif
894 }
895 st->cr();
896 }
897 #endif
898
899 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
900 Compile* C = ra_->C;
901 MacroAssembler _masm(&cbuf);
902
903 int framesize = C->frame_size_in_bytes();
904 int bangsize = C->bang_size_in_bytes();
905
906 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
907
908 C->set_frame_complete(cbuf.insts_size());
909
910 if (C->has_mach_constant_base_node()) {
911 // NOTE: We set the table base offset here because users might be
912 // emitted before MachConstantBaseNode.
913 Compile::ConstantTable& constant_table = C->constant_table();
914 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
915 }
916 }
917
918 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
919 {
920 return MachNode::size(ra_); // too many variables; just compute it
921 // the hard way
922 }
923
924 int MachPrologNode::reloc() const
925 {
926 return 0; // a large enough number
927 }
928
929 //=============================================================================
930 #ifndef PRODUCT
931 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
932 {
933 Compile* C = ra_->C;
934 if (VM_Version::supports_vzeroupper()) {
935 st->print("vzeroupper");
936 st->cr(); st->print("\t");
937 }
938
939 int framesize = C->frame_size_in_bytes();
940 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
941 // Remove word for return adr already pushed
942 // and RBP
943 framesize -= 2*wordSize;
944
945 if (framesize) {
946 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
947 st->print("\t");
948 }
949
950 st->print_cr("popq rbp");
951 if (do_polling() && C->is_method_compilation()) {
952 st->print("\t");
953 if (SafepointMechanism::uses_thread_local_poll()) {
954 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
955 "testl rax, [rscratch1]\t"
956 "# Safepoint: poll for GC");
957 } else if (Assembler::is_polling_page_far()) {
958 st->print_cr("movq rscratch1, #polling_page_address\n\t"
959 "testl rax, [rscratch1]\t"
960 "# Safepoint: poll for GC");
961 } else {
962 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
963 "# Safepoint: poll for GC");
964 }
965 }
966 }
967 #endif
968
969 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
970 {
971 Compile* C = ra_->C;
972 MacroAssembler _masm(&cbuf);
973
974 // Clear upper bits of YMM registers when current compiled code uses
975 // wide vectors to avoid AVX <-> SSE transition penalty during call.
976 __ vzeroupper();
977
978 int framesize = C->frame_size_in_bytes();
979 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
980 // Remove word for return adr already pushed
981 // and RBP
982 framesize -= 2*wordSize;
983
984 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
985
986 if (framesize) {
987 emit_opcode(cbuf, Assembler::REX_W);
988 if (framesize < 0x80) {
989 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
990 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
991 emit_d8(cbuf, framesize);
992 } else {
993 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
994 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
995 emit_d32(cbuf, framesize);
996 }
997 }
998
999 // popq rbp
1000 emit_opcode(cbuf, 0x58 | RBP_enc);
1001
1002 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1003 __ reserved_stack_check();
1004 }
1005
1006 if (do_polling() && C->is_method_compilation()) {
1007 MacroAssembler _masm(&cbuf);
1008 if (SafepointMechanism::uses_thread_local_poll()) {
1009 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1010 __ relocate(relocInfo::poll_return_type);
1011 __ testl(rax, Address(rscratch1, 0));
1012 } else {
1013 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1014 if (Assembler::is_polling_page_far()) {
1015 __ lea(rscratch1, polling_page);
1016 __ relocate(relocInfo::poll_return_type);
1017 __ testl(rax, Address(rscratch1, 0));
1018 } else {
1019 __ testl(rax, polling_page);
1020 }
1021 }
1022 }
1023 }
1024
1025 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1026 {
1027 return MachNode::size(ra_); // too many variables; just compute it
1028 // the hard way
1029 }
1030
1031 int MachEpilogNode::reloc() const
1032 {
1033 return 2; // a large enough number
1034 }
1035
1036 const Pipeline* MachEpilogNode::pipeline() const
1037 {
1038 return MachNode::pipeline_class();
1039 }
1040
1041 int MachEpilogNode::safepoint_offset() const
1042 {
1043 return 0;
1044 }
1045
1046 //=============================================================================
1047
1048 enum RC {
1049 rc_bad,
1050 rc_int,
1051 rc_float,
1052 rc_stack
1053 };
1054
1055 static enum RC rc_class(OptoReg::Name reg)
1056 {
1057 if( !OptoReg::is_valid(reg) ) return rc_bad;
1058
1059 if (OptoReg::is_stack(reg)) return rc_stack;
1060
1061 VMReg r = OptoReg::as_VMReg(reg);
1062
1063 if (r->is_Register()) return rc_int;
1064
1065 assert(r->is_XMMRegister(), "must be");
1066 return rc_float;
1067 }
1068
1069 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1070 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1071 int src_hi, int dst_hi, uint ireg, outputStream* st);
1072
1073 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1074 int stack_offset, int reg, uint ireg, outputStream* st);
1075
1076 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1077 int dst_offset, uint ireg, outputStream* st) {
1078 if (cbuf) {
1079 MacroAssembler _masm(cbuf);
1080 switch (ireg) {
1081 case Op_VecS:
1082 __ movq(Address(rsp, -8), rax);
1083 __ movl(rax, Address(rsp, src_offset));
1084 __ movl(Address(rsp, dst_offset), rax);
1085 __ movq(rax, Address(rsp, -8));
1086 break;
1087 case Op_VecD:
1088 __ pushq(Address(rsp, src_offset));
1089 __ popq (Address(rsp, dst_offset));
1090 break;
1091 case Op_VecX:
1092 __ pushq(Address(rsp, src_offset));
1093 __ popq (Address(rsp, dst_offset));
1094 __ pushq(Address(rsp, src_offset+8));
1095 __ popq (Address(rsp, dst_offset+8));
1096 break;
1097 case Op_VecY:
1098 __ vmovdqu(Address(rsp, -32), xmm0);
1099 __ vmovdqu(xmm0, Address(rsp, src_offset));
1100 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1101 __ vmovdqu(xmm0, Address(rsp, -32));
1102 break;
1103 case Op_VecZ:
1104 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1105 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1106 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1107 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1108 break;
1109 default:
1110 ShouldNotReachHere();
1111 }
1112 #ifndef PRODUCT
1113 } else {
1114 switch (ireg) {
1115 case Op_VecS:
1116 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1117 "movl rax, [rsp + #%d]\n\t"
1118 "movl [rsp + #%d], rax\n\t"
1119 "movq rax, [rsp - #8]",
1120 src_offset, dst_offset);
1121 break;
1122 case Op_VecD:
1123 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1124 "popq [rsp + #%d]",
1125 src_offset, dst_offset);
1126 break;
1127 case Op_VecX:
1128 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1129 "popq [rsp + #%d]\n\t"
1130 "pushq [rsp + #%d]\n\t"
1131 "popq [rsp + #%d]",
1132 src_offset, dst_offset, src_offset+8, dst_offset+8);
1133 break;
1134 case Op_VecY:
1135 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1136 "vmovdqu xmm0, [rsp + #%d]\n\t"
1137 "vmovdqu [rsp + #%d], xmm0\n\t"
1138 "vmovdqu xmm0, [rsp - #32]",
1139 src_offset, dst_offset);
1140 break;
1141 case Op_VecZ:
1142 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1143 "vmovdqu xmm0, [rsp + #%d]\n\t"
1144 "vmovdqu [rsp + #%d], xmm0\n\t"
1145 "vmovdqu xmm0, [rsp - #64]",
1146 src_offset, dst_offset);
1147 break;
1148 default:
1149 ShouldNotReachHere();
1150 }
1151 #endif
1152 }
1153 }
1154
1155 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1156 PhaseRegAlloc* ra_,
1157 bool do_size,
1158 outputStream* st) const {
1159 assert(cbuf != NULL || st != NULL, "sanity");
1160 // Get registers to move
1161 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1162 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1163 OptoReg::Name dst_second = ra_->get_reg_second(this);
1164 OptoReg::Name dst_first = ra_->get_reg_first(this);
1165
1166 enum RC src_second_rc = rc_class(src_second);
1167 enum RC src_first_rc = rc_class(src_first);
1168 enum RC dst_second_rc = rc_class(dst_second);
1169 enum RC dst_first_rc = rc_class(dst_first);
1170
1171 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1172 "must move at least 1 register" );
1173
1174 if (src_first == dst_first && src_second == dst_second) {
1175 // Self copy, no move
1176 return 0;
1177 }
1178 if (bottom_type()->isa_vect() != NULL) {
1179 uint ireg = ideal_reg();
1180 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1181 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1182 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1183 // mem -> mem
1184 int src_offset = ra_->reg2offset(src_first);
1185 int dst_offset = ra_->reg2offset(dst_first);
1186 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1187 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1188 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1189 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1190 int stack_offset = ra_->reg2offset(dst_first);
1191 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1192 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1193 int stack_offset = ra_->reg2offset(src_first);
1194 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1195 } else {
1196 ShouldNotReachHere();
1197 }
1198 return 0;
1199 }
1200 if (src_first_rc == rc_stack) {
1201 // mem ->
1202 if (dst_first_rc == rc_stack) {
1203 // mem -> mem
1204 assert(src_second != dst_first, "overlap");
1205 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1206 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1207 // 64-bit
1208 int src_offset = ra_->reg2offset(src_first);
1209 int dst_offset = ra_->reg2offset(dst_first);
1210 if (cbuf) {
1211 MacroAssembler _masm(cbuf);
1212 __ pushq(Address(rsp, src_offset));
1213 __ popq (Address(rsp, dst_offset));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1217 "popq [rsp + #%d]",
1218 src_offset, dst_offset);
1219 #endif
1220 }
1221 } else {
1222 // 32-bit
1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1225 // No pushl/popl, so:
1226 int src_offset = ra_->reg2offset(src_first);
1227 int dst_offset = ra_->reg2offset(dst_first);
1228 if (cbuf) {
1229 MacroAssembler _masm(cbuf);
1230 __ movq(Address(rsp, -8), rax);
1231 __ movl(rax, Address(rsp, src_offset));
1232 __ movl(Address(rsp, dst_offset), rax);
1233 __ movq(rax, Address(rsp, -8));
1234 #ifndef PRODUCT
1235 } else {
1236 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1237 "movl rax, [rsp + #%d]\n\t"
1238 "movl [rsp + #%d], rax\n\t"
1239 "movq rax, [rsp - #8]",
1240 src_offset, dst_offset);
1241 #endif
1242 }
1243 }
1244 return 0;
1245 } else if (dst_first_rc == rc_int) {
1246 // mem -> gpr
1247 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1248 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1249 // 64-bit
1250 int offset = ra_->reg2offset(src_first);
1251 if (cbuf) {
1252 MacroAssembler _masm(cbuf);
1253 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1254 #ifndef PRODUCT
1255 } else {
1256 st->print("movq %s, [rsp + #%d]\t# spill",
1257 Matcher::regName[dst_first],
1258 offset);
1259 #endif
1260 }
1261 } else {
1262 // 32-bit
1263 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1264 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1265 int offset = ra_->reg2offset(src_first);
1266 if (cbuf) {
1267 MacroAssembler _masm(cbuf);
1268 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1269 #ifndef PRODUCT
1270 } else {
1271 st->print("movl %s, [rsp + #%d]\t# spill",
1272 Matcher::regName[dst_first],
1273 offset);
1274 #endif
1275 }
1276 }
1277 return 0;
1278 } else if (dst_first_rc == rc_float) {
1279 // mem-> xmm
1280 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1281 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1282 // 64-bit
1283 int offset = ra_->reg2offset(src_first);
1284 if (cbuf) {
1285 MacroAssembler _masm(cbuf);
1286 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1287 #ifndef PRODUCT
1288 } else {
1289 st->print("%s %s, [rsp + #%d]\t# spill",
1290 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1291 Matcher::regName[dst_first],
1292 offset);
1293 #endif
1294 }
1295 } else {
1296 // 32-bit
1297 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1298 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1299 int offset = ra_->reg2offset(src_first);
1300 if (cbuf) {
1301 MacroAssembler _masm(cbuf);
1302 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1303 #ifndef PRODUCT
1304 } else {
1305 st->print("movss %s, [rsp + #%d]\t# spill",
1306 Matcher::regName[dst_first],
1307 offset);
1308 #endif
1309 }
1310 }
1311 return 0;
1312 }
1313 } else if (src_first_rc == rc_int) {
1314 // gpr ->
1315 if (dst_first_rc == rc_stack) {
1316 // gpr -> mem
1317 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1318 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1319 // 64-bit
1320 int offset = ra_->reg2offset(dst_first);
1321 if (cbuf) {
1322 MacroAssembler _masm(cbuf);
1323 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1324 #ifndef PRODUCT
1325 } else {
1326 st->print("movq [rsp + #%d], %s\t# spill",
1327 offset,
1328 Matcher::regName[src_first]);
1329 #endif
1330 }
1331 } else {
1332 // 32-bit
1333 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1334 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1335 int offset = ra_->reg2offset(dst_first);
1336 if (cbuf) {
1337 MacroAssembler _masm(cbuf);
1338 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1339 #ifndef PRODUCT
1340 } else {
1341 st->print("movl [rsp + #%d], %s\t# spill",
1342 offset,
1343 Matcher::regName[src_first]);
1344 #endif
1345 }
1346 }
1347 return 0;
1348 } else if (dst_first_rc == rc_int) {
1349 // gpr -> gpr
1350 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1351 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1352 // 64-bit
1353 if (cbuf) {
1354 MacroAssembler _masm(cbuf);
1355 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1356 as_Register(Matcher::_regEncode[src_first]));
1357 #ifndef PRODUCT
1358 } else {
1359 st->print("movq %s, %s\t# spill",
1360 Matcher::regName[dst_first],
1361 Matcher::regName[src_first]);
1362 #endif
1363 }
1364 return 0;
1365 } else {
1366 // 32-bit
1367 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1368 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1369 if (cbuf) {
1370 MacroAssembler _masm(cbuf);
1371 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1372 as_Register(Matcher::_regEncode[src_first]));
1373 #ifndef PRODUCT
1374 } else {
1375 st->print("movl %s, %s\t# spill",
1376 Matcher::regName[dst_first],
1377 Matcher::regName[src_first]);
1378 #endif
1379 }
1380 return 0;
1381 }
1382 } else if (dst_first_rc == rc_float) {
1383 // gpr -> xmm
1384 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1385 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1386 // 64-bit
1387 if (cbuf) {
1388 MacroAssembler _masm(cbuf);
1389 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1390 #ifndef PRODUCT
1391 } else {
1392 st->print("movdq %s, %s\t# spill",
1393 Matcher::regName[dst_first],
1394 Matcher::regName[src_first]);
1395 #endif
1396 }
1397 } else {
1398 // 32-bit
1399 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1400 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1401 if (cbuf) {
1402 MacroAssembler _masm(cbuf);
1403 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1404 #ifndef PRODUCT
1405 } else {
1406 st->print("movdl %s, %s\t# spill",
1407 Matcher::regName[dst_first],
1408 Matcher::regName[src_first]);
1409 #endif
1410 }
1411 }
1412 return 0;
1413 }
1414 } else if (src_first_rc == rc_float) {
1415 // xmm ->
1416 if (dst_first_rc == rc_stack) {
1417 // xmm -> mem
1418 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1419 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1420 // 64-bit
1421 int offset = ra_->reg2offset(dst_first);
1422 if (cbuf) {
1423 MacroAssembler _masm(cbuf);
1424 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1425 #ifndef PRODUCT
1426 } else {
1427 st->print("movsd [rsp + #%d], %s\t# spill",
1428 offset,
1429 Matcher::regName[src_first]);
1430 #endif
1431 }
1432 } else {
1433 // 32-bit
1434 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1435 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1436 int offset = ra_->reg2offset(dst_first);
1437 if (cbuf) {
1438 MacroAssembler _masm(cbuf);
1439 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1440 #ifndef PRODUCT
1441 } else {
1442 st->print("movss [rsp + #%d], %s\t# spill",
1443 offset,
1444 Matcher::regName[src_first]);
1445 #endif
1446 }
1447 }
1448 return 0;
1449 } else if (dst_first_rc == rc_int) {
1450 // xmm -> gpr
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1453 // 64-bit
1454 if (cbuf) {
1455 MacroAssembler _masm(cbuf);
1456 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1457 #ifndef PRODUCT
1458 } else {
1459 st->print("movdq %s, %s\t# spill",
1460 Matcher::regName[dst_first],
1461 Matcher::regName[src_first]);
1462 #endif
1463 }
1464 } else {
1465 // 32-bit
1466 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1467 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1468 if (cbuf) {
1469 MacroAssembler _masm(cbuf);
1470 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1471 #ifndef PRODUCT
1472 } else {
1473 st->print("movdl %s, %s\t# spill",
1474 Matcher::regName[dst_first],
1475 Matcher::regName[src_first]);
1476 #endif
1477 }
1478 }
1479 return 0;
1480 } else if (dst_first_rc == rc_float) {
1481 // xmm -> xmm
1482 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1483 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1484 // 64-bit
1485 if (cbuf) {
1486 MacroAssembler _masm(cbuf);
1487 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1488 #ifndef PRODUCT
1489 } else {
1490 st->print("%s %s, %s\t# spill",
1491 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1492 Matcher::regName[dst_first],
1493 Matcher::regName[src_first]);
1494 #endif
1495 }
1496 } else {
1497 // 32-bit
1498 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1499 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1500 if (cbuf) {
1501 MacroAssembler _masm(cbuf);
1502 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1503 #ifndef PRODUCT
1504 } else {
1505 st->print("%s %s, %s\t# spill",
1506 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1507 Matcher::regName[dst_first],
1508 Matcher::regName[src_first]);
1509 #endif
1510 }
1511 }
1512 return 0;
1513 }
1514 }
1515
1516 assert(0," foo ");
1517 Unimplemented();
1518 return 0;
1519 }
1520
1521 #ifndef PRODUCT
1522 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1523 implementation(NULL, ra_, false, st);
1524 }
1525 #endif
1526
1527 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1528 implementation(&cbuf, ra_, false, NULL);
1529 }
1530
1531 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1532 return MachNode::size(ra_);
1533 }
1534
1535 //=============================================================================
1536 #ifndef PRODUCT
1537 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1538 {
1539 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1540 int reg = ra_->get_reg_first(this);
1541 st->print("leaq %s, [rsp + #%d]\t# box lock",
1542 Matcher::regName[reg], offset);
1543 }
1544 #endif
1545
1546 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1547 {
1548 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1549 int reg = ra_->get_encode(this);
1550 if (offset >= 0x80) {
1551 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1552 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1553 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1554 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1555 emit_d32(cbuf, offset);
1556 } else {
1557 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1558 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1559 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1560 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1561 emit_d8(cbuf, offset);
1562 }
1563 }
1564
1565 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1566 {
1567 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1568 return (offset < 0x80) ? 5 : 8; // REX
1569 }
1570
1571 //=============================================================================
1572 #ifndef PRODUCT
1573 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1574 {
1575 if (UseCompressedClassPointers) {
1576 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1577 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1578 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1579 } else {
1580 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1581 "# Inline cache check");
1582 }
1583 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1584 st->print_cr("\tnop\t# nops to align entry point");
1585 }
1586 #endif
1587
1588 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1589 {
1590 MacroAssembler masm(&cbuf);
1591 uint insts_size = cbuf.insts_size();
1592 if (UseCompressedClassPointers) {
1593 masm.load_klass(rscratch1, j_rarg0);
1594 masm.cmpptr(rax, rscratch1);
1595 } else {
1596 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1597 }
1598
1599 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1600
1601 /* WARNING these NOPs are critical so that verified entry point is properly
1602 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1603 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1604 if (OptoBreakpoint) {
1605 // Leave space for int3
1606 nops_cnt -= 1;
1607 }
1608 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1609 if (nops_cnt > 0)
1610 masm.nop(nops_cnt);
1611 }
1612
1613 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1614 {
1615 return MachNode::size(ra_); // too many variables; just compute it
1616 // the hard way
1617 }
1618
1619
1620 //=============================================================================
1621
1622 int Matcher::regnum_to_fpu_offset(int regnum)
1623 {
1624 return regnum - 32; // The FP registers are in the second chunk
1625 }
1626
1627 // This is UltraSparc specific, true just means we have fast l2f conversion
1628 const bool Matcher::convL2FSupported(void) {
1629 return true;
1630 }
1631
1632 // Is this branch offset short enough that a short branch can be used?
1633 //
1634 // NOTE: If the platform does not provide any short branch variants, then
1635 // this method should return false for offset 0.
1636 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1637 // The passed offset is relative to address of the branch.
1638 // On 86 a branch displacement is calculated relative to address
1639 // of a next instruction.
1640 offset -= br_size;
1641
1642 // the short version of jmpConUCF2 contains multiple branches,
1643 // making the reach slightly less
1644 if (rule == jmpConUCF2_rule)
1645 return (-126 <= offset && offset <= 125);
1646 return (-128 <= offset && offset <= 127);
1647 }
1648
1649 const bool Matcher::isSimpleConstant64(jlong value) {
1650 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1651 //return value == (int) value; // Cf. storeImmL and immL32.
1652
1653 // Probably always true, even if a temp register is required.
1654 return true;
1655 }
1656
1657 // The ecx parameter to rep stosq for the ClearArray node is in words.
1658 const bool Matcher::init_array_count_is_in_bytes = false;
1659
1660 // No additional cost for CMOVL.
1661 const int Matcher::long_cmove_cost() { return 0; }
1662
1663 // No CMOVF/CMOVD with SSE2
1664 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1665
1666 // Does the CPU require late expand (see block.cpp for description of late expand)?
1667 const bool Matcher::require_postalloc_expand = false;
1668
1669 // Do we need to mask the count passed to shift instructions or does
1670 // the cpu only look at the lower 5/6 bits anyway?
1671 const bool Matcher::need_masked_shift_count = false;
1672
1673 bool Matcher::narrow_oop_use_complex_address() {
1674 assert(UseCompressedOops, "only for compressed oops code");
1675 return (LogMinObjAlignmentInBytes <= 3);
1676 }
1677
1678 bool Matcher::narrow_klass_use_complex_address() {
1679 assert(UseCompressedClassPointers, "only for compressed klass code");
1680 return (LogKlassAlignmentInBytes <= 3);
1681 }
1682
1683 bool Matcher::const_oop_prefer_decode() {
1684 // Prefer ConN+DecodeN over ConP.
1685 return true;
1686 }
1687
1688 bool Matcher::const_klass_prefer_decode() {
1689 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1690 // or condisider the following:
1691 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1692 //return Universe::narrow_klass_base() == NULL;
1693 return true;
1694 }
1695
1696 // Is it better to copy float constants, or load them directly from
1697 // memory? Intel can load a float constant from a direct address,
1698 // requiring no extra registers. Most RISCs will have to materialize
1699 // an address into a register first, so they would do better to copy
1700 // the constant from stack.
1701 const bool Matcher::rematerialize_float_constants = true; // XXX
1702
1703 // If CPU can load and store mis-aligned doubles directly then no
1704 // fixup is needed. Else we split the double into 2 integer pieces
1705 // and move it piece-by-piece. Only happens when passing doubles into
1706 // C code as the Java calling convention forces doubles to be aligned.
1707 const bool Matcher::misaligned_doubles_ok = true;
1708
1709 // No-op on amd64
1710 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1711
1712 // Advertise here if the CPU requires explicit rounding operations to
1713 // implement the UseStrictFP mode.
1714 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1715
1716 // Are floats conerted to double when stored to stack during deoptimization?
1717 // On x64 it is stored without convertion so we can use normal access.
1718 bool Matcher::float_in_double() { return false; }
1719
1720 // Do ints take an entire long register or just half?
1721 const bool Matcher::int_in_long = true;
1722
1723 // Return whether or not this register is ever used as an argument.
1724 // This function is used on startup to build the trampoline stubs in
1725 // generateOptoStub. Registers not mentioned will be killed by the VM
1726 // call in the trampoline, and arguments in those registers not be
1727 // available to the callee.
1728 bool Matcher::can_be_java_arg(int reg)
1729 {
1730 return
1731 reg == RDI_num || reg == RDI_H_num ||
1732 reg == RSI_num || reg == RSI_H_num ||
1733 reg == RDX_num || reg == RDX_H_num ||
1734 reg == RCX_num || reg == RCX_H_num ||
1735 reg == R8_num || reg == R8_H_num ||
1736 reg == R9_num || reg == R9_H_num ||
1737 reg == R12_num || reg == R12_H_num ||
1738 reg == XMM0_num || reg == XMM0b_num ||
1739 reg == XMM1_num || reg == XMM1b_num ||
1740 reg == XMM2_num || reg == XMM2b_num ||
1741 reg == XMM3_num || reg == XMM3b_num ||
1742 reg == XMM4_num || reg == XMM4b_num ||
1743 reg == XMM5_num || reg == XMM5b_num ||
1744 reg == XMM6_num || reg == XMM6b_num ||
1745 reg == XMM7_num || reg == XMM7b_num;
1746 }
1747
1748 bool Matcher::is_spillable_arg(int reg)
1749 {
1750 return can_be_java_arg(reg);
1751 }
1752
1753 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1754 // In 64 bit mode a code which use multiply when
1755 // devisor is constant is faster than hardware
1756 // DIV instruction (it uses MulHiL).
1757 return false;
1758 }
1759
1760 // Register for DIVI projection of divmodI
1761 RegMask Matcher::divI_proj_mask() {
1762 return INT_RAX_REG_mask();
1763 }
1764
1765 // Register for MODI projection of divmodI
1766 RegMask Matcher::modI_proj_mask() {
1767 return INT_RDX_REG_mask();
1768 }
1769
1770 // Register for DIVL projection of divmodL
1771 RegMask Matcher::divL_proj_mask() {
1772 return LONG_RAX_REG_mask();
1773 }
1774
1775 // Register for MODL projection of divmodL
1776 RegMask Matcher::modL_proj_mask() {
1777 return LONG_RDX_REG_mask();
1778 }
1779
1780 // Register for saving SP into on method handle invokes. Not used on x86_64.
1781 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1782 return NO_REG_mask();
1783 }
1784
1785 %}
1786
1787 //----------ENCODING BLOCK-----------------------------------------------------
1788 // This block specifies the encoding classes used by the compiler to
1789 // output byte streams. Encoding classes are parameterized macros
1790 // used by Machine Instruction Nodes in order to generate the bit
1791 // encoding of the instruction. Operands specify their base encoding
1792 // interface with the interface keyword. There are currently
1793 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1794 // COND_INTER. REG_INTER causes an operand to generate a function
1795 // which returns its register number when queried. CONST_INTER causes
1796 // an operand to generate a function which returns the value of the
1797 // constant when queried. MEMORY_INTER causes an operand to generate
1798 // four functions which return the Base Register, the Index Register,
1799 // the Scale Value, and the Offset Value of the operand when queried.
1800 // COND_INTER causes an operand to generate six functions which return
1801 // the encoding code (ie - encoding bits for the instruction)
1802 // associated with each basic boolean condition for a conditional
1803 // instruction.
1804 //
1805 // Instructions specify two basic values for encoding. Again, a
1806 // function is available to check if the constant displacement is an
1807 // oop. They use the ins_encode keyword to specify their encoding
1808 // classes (which must be a sequence of enc_class names, and their
1809 // parameters, specified in the encoding block), and they use the
1810 // opcode keyword to specify, in order, their primary, secondary, and
1811 // tertiary opcode. Only the opcode sections which a particular
1812 // instruction needs for encoding need to be specified.
1813 encode %{
1814 // Build emit functions for each basic byte or larger field in the
1815 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1816 // from C++ code in the enc_class source block. Emit functions will
1817 // live in the main source block for now. In future, we can
1818 // generalize this by adding a syntax that specifies the sizes of
1819 // fields in an order, so that the adlc can build the emit functions
1820 // automagically
1821
1822 // Emit primary opcode
1823 enc_class OpcP
1824 %{
1825 emit_opcode(cbuf, $primary);
1826 %}
1827
1828 // Emit secondary opcode
1829 enc_class OpcS
1830 %{
1831 emit_opcode(cbuf, $secondary);
1832 %}
1833
1834 // Emit tertiary opcode
1835 enc_class OpcT
1836 %{
1837 emit_opcode(cbuf, $tertiary);
1838 %}
1839
1840 // Emit opcode directly
1841 enc_class Opcode(immI d8)
1842 %{
1843 emit_opcode(cbuf, $d8$$constant);
1844 %}
1845
1846 // Emit size prefix
1847 enc_class SizePrefix
1848 %{
1849 emit_opcode(cbuf, 0x66);
1850 %}
1851
1852 enc_class reg(rRegI reg)
1853 %{
1854 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1855 %}
1856
1857 enc_class reg_reg(rRegI dst, rRegI src)
1858 %{
1859 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1860 %}
1861
1862 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1863 %{
1864 emit_opcode(cbuf, $opcode$$constant);
1865 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1866 %}
1867
1868 enc_class cdql_enc(no_rax_rdx_RegI div)
1869 %{
1870 // Full implementation of Java idiv and irem; checks for
1871 // special case as described in JVM spec., p.243 & p.271.
1872 //
1873 // normal case special case
1874 //
1875 // input : rax: dividend min_int
1876 // reg: divisor -1
1877 //
1878 // output: rax: quotient (= rax idiv reg) min_int
1879 // rdx: remainder (= rax irem reg) 0
1880 //
1881 // Code sequnce:
1882 //
1883 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1884 // 5: 75 07/08 jne e <normal>
1885 // 7: 33 d2 xor %edx,%edx
1886 // [div >= 8 -> offset + 1]
1887 // [REX_B]
1888 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1889 // c: 74 03/04 je 11 <done>
1890 // 000000000000000e <normal>:
1891 // e: 99 cltd
1892 // [div >= 8 -> offset + 1]
1893 // [REX_B]
1894 // f: f7 f9 idiv $div
1895 // 0000000000000011 <done>:
1896
1897 // cmp $0x80000000,%eax
1898 emit_opcode(cbuf, 0x3d);
1899 emit_d8(cbuf, 0x00);
1900 emit_d8(cbuf, 0x00);
1901 emit_d8(cbuf, 0x00);
1902 emit_d8(cbuf, 0x80);
1903
1904 // jne e <normal>
1905 emit_opcode(cbuf, 0x75);
1906 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1907
1908 // xor %edx,%edx
1909 emit_opcode(cbuf, 0x33);
1910 emit_d8(cbuf, 0xD2);
1911
1912 // cmp $0xffffffffffffffff,%ecx
1913 if ($div$$reg >= 8) {
1914 emit_opcode(cbuf, Assembler::REX_B);
1915 }
1916 emit_opcode(cbuf, 0x83);
1917 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1918 emit_d8(cbuf, 0xFF);
1919
1920 // je 11 <done>
1921 emit_opcode(cbuf, 0x74);
1922 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1923
1924 // <normal>
1925 // cltd
1926 emit_opcode(cbuf, 0x99);
1927
1928 // idivl (note: must be emitted by the user of this rule)
1929 // <done>
1930 %}
1931
1932 enc_class cdqq_enc(no_rax_rdx_RegL div)
1933 %{
1934 // Full implementation of Java ldiv and lrem; checks for
1935 // special case as described in JVM spec., p.243 & p.271.
1936 //
1937 // normal case special case
1938 //
1939 // input : rax: dividend min_long
1940 // reg: divisor -1
1941 //
1942 // output: rax: quotient (= rax idiv reg) min_long
1943 // rdx: remainder (= rax irem reg) 0
1944 //
1945 // Code sequnce:
1946 //
1947 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1948 // 7: 00 00 80
1949 // a: 48 39 d0 cmp %rdx,%rax
1950 // d: 75 08 jne 17 <normal>
1951 // f: 33 d2 xor %edx,%edx
1952 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1953 // 15: 74 05 je 1c <done>
1954 // 0000000000000017 <normal>:
1955 // 17: 48 99 cqto
1956 // 19: 48 f7 f9 idiv $div
1957 // 000000000000001c <done>:
1958
1959 // mov $0x8000000000000000,%rdx
1960 emit_opcode(cbuf, Assembler::REX_W);
1961 emit_opcode(cbuf, 0xBA);
1962 emit_d8(cbuf, 0x00);
1963 emit_d8(cbuf, 0x00);
1964 emit_d8(cbuf, 0x00);
1965 emit_d8(cbuf, 0x00);
1966 emit_d8(cbuf, 0x00);
1967 emit_d8(cbuf, 0x00);
1968 emit_d8(cbuf, 0x00);
1969 emit_d8(cbuf, 0x80);
1970
1971 // cmp %rdx,%rax
1972 emit_opcode(cbuf, Assembler::REX_W);
1973 emit_opcode(cbuf, 0x39);
1974 emit_d8(cbuf, 0xD0);
1975
1976 // jne 17 <normal>
1977 emit_opcode(cbuf, 0x75);
1978 emit_d8(cbuf, 0x08);
1979
1980 // xor %edx,%edx
1981 emit_opcode(cbuf, 0x33);
1982 emit_d8(cbuf, 0xD2);
1983
1984 // cmp $0xffffffffffffffff,$div
1985 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1986 emit_opcode(cbuf, 0x83);
1987 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1988 emit_d8(cbuf, 0xFF);
1989
1990 // je 1e <done>
1991 emit_opcode(cbuf, 0x74);
1992 emit_d8(cbuf, 0x05);
1993
1994 // <normal>
1995 // cqto
1996 emit_opcode(cbuf, Assembler::REX_W);
1997 emit_opcode(cbuf, 0x99);
1998
1999 // idivq (note: must be emitted by the user of this rule)
2000 // <done>
2001 %}
2002
2003 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2004 enc_class OpcSE(immI imm)
2005 %{
2006 // Emit primary opcode and set sign-extend bit
2007 // Check for 8-bit immediate, and set sign extend bit in opcode
2008 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2009 emit_opcode(cbuf, $primary | 0x02);
2010 } else {
2011 // 32-bit immediate
2012 emit_opcode(cbuf, $primary);
2013 }
2014 %}
2015
2016 enc_class OpcSErm(rRegI dst, immI imm)
2017 %{
2018 // OpcSEr/m
2019 int dstenc = $dst$$reg;
2020 if (dstenc >= 8) {
2021 emit_opcode(cbuf, Assembler::REX_B);
2022 dstenc -= 8;
2023 }
2024 // Emit primary opcode and set sign-extend bit
2025 // Check for 8-bit immediate, and set sign extend bit in opcode
2026 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2027 emit_opcode(cbuf, $primary | 0x02);
2028 } else {
2029 // 32-bit immediate
2030 emit_opcode(cbuf, $primary);
2031 }
2032 // Emit r/m byte with secondary opcode, after primary opcode.
2033 emit_rm(cbuf, 0x3, $secondary, dstenc);
2034 %}
2035
2036 enc_class OpcSErm_wide(rRegL dst, immI imm)
2037 %{
2038 // OpcSEr/m
2039 int dstenc = $dst$$reg;
2040 if (dstenc < 8) {
2041 emit_opcode(cbuf, Assembler::REX_W);
2042 } else {
2043 emit_opcode(cbuf, Assembler::REX_WB);
2044 dstenc -= 8;
2045 }
2046 // Emit primary opcode and set sign-extend bit
2047 // Check for 8-bit immediate, and set sign extend bit in opcode
2048 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2049 emit_opcode(cbuf, $primary | 0x02);
2050 } else {
2051 // 32-bit immediate
2052 emit_opcode(cbuf, $primary);
2053 }
2054 // Emit r/m byte with secondary opcode, after primary opcode.
2055 emit_rm(cbuf, 0x3, $secondary, dstenc);
2056 %}
2057
2058 enc_class Con8or32(immI imm)
2059 %{
2060 // Check for 8-bit immediate, and set sign extend bit in opcode
2061 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2062 $$$emit8$imm$$constant;
2063 } else {
2064 // 32-bit immediate
2065 $$$emit32$imm$$constant;
2066 }
2067 %}
2068
2069 enc_class opc2_reg(rRegI dst)
2070 %{
2071 // BSWAP
2072 emit_cc(cbuf, $secondary, $dst$$reg);
2073 %}
2074
2075 enc_class opc3_reg(rRegI dst)
2076 %{
2077 // BSWAP
2078 emit_cc(cbuf, $tertiary, $dst$$reg);
2079 %}
2080
2081 enc_class reg_opc(rRegI div)
2082 %{
2083 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2084 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2085 %}
2086
2087 enc_class enc_cmov(cmpOp cop)
2088 %{
2089 // CMOV
2090 $$$emit8$primary;
2091 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2092 %}
2093
2094 enc_class enc_PartialSubtypeCheck()
2095 %{
2096 Register Rrdi = as_Register(RDI_enc); // result register
2097 Register Rrax = as_Register(RAX_enc); // super class
2098 Register Rrcx = as_Register(RCX_enc); // killed
2099 Register Rrsi = as_Register(RSI_enc); // sub class
2100 Label miss;
2101 const bool set_cond_codes = true;
2102
2103 MacroAssembler _masm(&cbuf);
2104 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2105 NULL, &miss,
2106 /*set_cond_codes:*/ true);
2107 if ($primary) {
2108 __ xorptr(Rrdi, Rrdi);
2109 }
2110 __ bind(miss);
2111 %}
2112
2113 enc_class clear_avx %{
2114 debug_only(int off0 = cbuf.insts_size());
2115 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2116 // Clear upper bits of YMM registers when current compiled code uses
2117 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2118 MacroAssembler _masm(&cbuf);
2119 __ vzeroupper();
2120 debug_only(int off1 = cbuf.insts_size());
2121 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2122 %}
2123
2124 enc_class Java_To_Runtime(method meth) %{
2125 // No relocation needed
2126 MacroAssembler _masm(&cbuf);
2127 __ mov64(r10, (int64_t) $meth$$method);
2128 __ call(r10);
2129 %}
2130
2131 enc_class Java_To_Interpreter(method meth)
2132 %{
2133 // CALL Java_To_Interpreter
2134 // This is the instruction starting address for relocation info.
2135 cbuf.set_insts_mark();
2136 $$$emit8$primary;
2137 // CALL directly to the runtime
2138 emit_d32_reloc(cbuf,
2139 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2140 runtime_call_Relocation::spec(),
2141 RELOC_DISP32);
2142 %}
2143
2144 enc_class Java_Static_Call(method meth)
2145 %{
2146 // JAVA STATIC CALL
2147 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2148 // determine who we intended to call.
2149 cbuf.set_insts_mark();
2150 $$$emit8$primary;
2151
2152 if (!_method) {
2153 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2154 runtime_call_Relocation::spec(),
2155 RELOC_DISP32);
2156 } else {
2157 int method_index = resolved_method_index(cbuf);
2158 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2159 : static_call_Relocation::spec(method_index);
2160 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2161 rspec, RELOC_DISP32);
2162 // Emit stubs for static call.
2163 address mark = cbuf.insts_mark();
2164 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2165 if (stub == NULL) {
2166 ciEnv::current()->record_failure("CodeCache is full");
2167 return;
2168 }
2169 #if INCLUDE_AOT
2170 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2171 #endif
2172 }
2173 %}
2174
2175 enc_class Java_Dynamic_Call(method meth) %{
2176 MacroAssembler _masm(&cbuf);
2177 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2178 %}
2179
2180 enc_class Java_Compiled_Call(method meth)
2181 %{
2182 // JAVA COMPILED CALL
2183 int disp = in_bytes(Method:: from_compiled_offset());
2184
2185 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2186 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2187
2188 // callq *disp(%rax)
2189 cbuf.set_insts_mark();
2190 $$$emit8$primary;
2191 if (disp < 0x80) {
2192 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2193 emit_d8(cbuf, disp); // Displacement
2194 } else {
2195 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2196 emit_d32(cbuf, disp); // Displacement
2197 }
2198 %}
2199
2200 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2201 %{
2202 // SAL, SAR, SHR
2203 int dstenc = $dst$$reg;
2204 if (dstenc >= 8) {
2205 emit_opcode(cbuf, Assembler::REX_B);
2206 dstenc -= 8;
2207 }
2208 $$$emit8$primary;
2209 emit_rm(cbuf, 0x3, $secondary, dstenc);
2210 $$$emit8$shift$$constant;
2211 %}
2212
2213 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2214 %{
2215 // SAL, SAR, SHR
2216 int dstenc = $dst$$reg;
2217 if (dstenc < 8) {
2218 emit_opcode(cbuf, Assembler::REX_W);
2219 } else {
2220 emit_opcode(cbuf, Assembler::REX_WB);
2221 dstenc -= 8;
2222 }
2223 $$$emit8$primary;
2224 emit_rm(cbuf, 0x3, $secondary, dstenc);
2225 $$$emit8$shift$$constant;
2226 %}
2227
2228 enc_class load_immI(rRegI dst, immI src)
2229 %{
2230 int dstenc = $dst$$reg;
2231 if (dstenc >= 8) {
2232 emit_opcode(cbuf, Assembler::REX_B);
2233 dstenc -= 8;
2234 }
2235 emit_opcode(cbuf, 0xB8 | dstenc);
2236 $$$emit32$src$$constant;
2237 %}
2238
2239 enc_class load_immL(rRegL dst, immL src)
2240 %{
2241 int dstenc = $dst$$reg;
2242 if (dstenc < 8) {
2243 emit_opcode(cbuf, Assembler::REX_W);
2244 } else {
2245 emit_opcode(cbuf, Assembler::REX_WB);
2246 dstenc -= 8;
2247 }
2248 emit_opcode(cbuf, 0xB8 | dstenc);
2249 emit_d64(cbuf, $src$$constant);
2250 %}
2251
2252 enc_class load_immUL32(rRegL dst, immUL32 src)
2253 %{
2254 // same as load_immI, but this time we care about zeroes in the high word
2255 int dstenc = $dst$$reg;
2256 if (dstenc >= 8) {
2257 emit_opcode(cbuf, Assembler::REX_B);
2258 dstenc -= 8;
2259 }
2260 emit_opcode(cbuf, 0xB8 | dstenc);
2261 $$$emit32$src$$constant;
2262 %}
2263
2264 enc_class load_immL32(rRegL dst, immL32 src)
2265 %{
2266 int dstenc = $dst$$reg;
2267 if (dstenc < 8) {
2268 emit_opcode(cbuf, Assembler::REX_W);
2269 } else {
2270 emit_opcode(cbuf, Assembler::REX_WB);
2271 dstenc -= 8;
2272 }
2273 emit_opcode(cbuf, 0xC7);
2274 emit_rm(cbuf, 0x03, 0x00, dstenc);
2275 $$$emit32$src$$constant;
2276 %}
2277
2278 enc_class load_immP31(rRegP dst, immP32 src)
2279 %{
2280 // same as load_immI, but this time we care about zeroes in the high word
2281 int dstenc = $dst$$reg;
2282 if (dstenc >= 8) {
2283 emit_opcode(cbuf, Assembler::REX_B);
2284 dstenc -= 8;
2285 }
2286 emit_opcode(cbuf, 0xB8 | dstenc);
2287 $$$emit32$src$$constant;
2288 %}
2289
2290 enc_class load_immP(rRegP dst, immP src)
2291 %{
2292 int dstenc = $dst$$reg;
2293 if (dstenc < 8) {
2294 emit_opcode(cbuf, Assembler::REX_W);
2295 } else {
2296 emit_opcode(cbuf, Assembler::REX_WB);
2297 dstenc -= 8;
2298 }
2299 emit_opcode(cbuf, 0xB8 | dstenc);
2300 // This next line should be generated from ADLC
2301 if ($src->constant_reloc() != relocInfo::none) {
2302 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2303 } else {
2304 emit_d64(cbuf, $src$$constant);
2305 }
2306 %}
2307
2308 enc_class Con32(immI src)
2309 %{
2310 // Output immediate
2311 $$$emit32$src$$constant;
2312 %}
2313
2314 enc_class Con32F_as_bits(immF src)
2315 %{
2316 // Output Float immediate bits
2317 jfloat jf = $src$$constant;
2318 jint jf_as_bits = jint_cast(jf);
2319 emit_d32(cbuf, jf_as_bits);
2320 %}
2321
2322 enc_class Con16(immI src)
2323 %{
2324 // Output immediate
2325 $$$emit16$src$$constant;
2326 %}
2327
2328 // How is this different from Con32??? XXX
2329 enc_class Con_d32(immI src)
2330 %{
2331 emit_d32(cbuf,$src$$constant);
2332 %}
2333
2334 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2335 // Output immediate memory reference
2336 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2337 emit_d32(cbuf, 0x00);
2338 %}
2339
2340 enc_class lock_prefix()
2341 %{
2342 if (os::is_MP()) {
2343 emit_opcode(cbuf, 0xF0); // lock
2344 }
2345 %}
2346
2347 enc_class REX_mem(memory mem)
2348 %{
2349 if ($mem$$base >= 8) {
2350 if ($mem$$index < 8) {
2351 emit_opcode(cbuf, Assembler::REX_B);
2352 } else {
2353 emit_opcode(cbuf, Assembler::REX_XB);
2354 }
2355 } else {
2356 if ($mem$$index >= 8) {
2357 emit_opcode(cbuf, Assembler::REX_X);
2358 }
2359 }
2360 %}
2361
2362 enc_class REX_mem_wide(memory mem)
2363 %{
2364 if ($mem$$base >= 8) {
2365 if ($mem$$index < 8) {
2366 emit_opcode(cbuf, Assembler::REX_WB);
2367 } else {
2368 emit_opcode(cbuf, Assembler::REX_WXB);
2369 }
2370 } else {
2371 if ($mem$$index < 8) {
2372 emit_opcode(cbuf, Assembler::REX_W);
2373 } else {
2374 emit_opcode(cbuf, Assembler::REX_WX);
2375 }
2376 }
2377 %}
2378
2379 // for byte regs
2380 enc_class REX_breg(rRegI reg)
2381 %{
2382 if ($reg$$reg >= 4) {
2383 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2384 }
2385 %}
2386
2387 // for byte regs
2388 enc_class REX_reg_breg(rRegI dst, rRegI src)
2389 %{
2390 if ($dst$$reg < 8) {
2391 if ($src$$reg >= 4) {
2392 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2393 }
2394 } else {
2395 if ($src$$reg < 8) {
2396 emit_opcode(cbuf, Assembler::REX_R);
2397 } else {
2398 emit_opcode(cbuf, Assembler::REX_RB);
2399 }
2400 }
2401 %}
2402
2403 // for byte regs
2404 enc_class REX_breg_mem(rRegI reg, memory mem)
2405 %{
2406 if ($reg$$reg < 8) {
2407 if ($mem$$base < 8) {
2408 if ($mem$$index >= 8) {
2409 emit_opcode(cbuf, Assembler::REX_X);
2410 } else if ($reg$$reg >= 4) {
2411 emit_opcode(cbuf, Assembler::REX);
2412 }
2413 } else {
2414 if ($mem$$index < 8) {
2415 emit_opcode(cbuf, Assembler::REX_B);
2416 } else {
2417 emit_opcode(cbuf, Assembler::REX_XB);
2418 }
2419 }
2420 } else {
2421 if ($mem$$base < 8) {
2422 if ($mem$$index < 8) {
2423 emit_opcode(cbuf, Assembler::REX_R);
2424 } else {
2425 emit_opcode(cbuf, Assembler::REX_RX);
2426 }
2427 } else {
2428 if ($mem$$index < 8) {
2429 emit_opcode(cbuf, Assembler::REX_RB);
2430 } else {
2431 emit_opcode(cbuf, Assembler::REX_RXB);
2432 }
2433 }
2434 }
2435 %}
2436
2437 enc_class REX_reg(rRegI reg)
2438 %{
2439 if ($reg$$reg >= 8) {
2440 emit_opcode(cbuf, Assembler::REX_B);
2441 }
2442 %}
2443
2444 enc_class REX_reg_wide(rRegI reg)
2445 %{
2446 if ($reg$$reg < 8) {
2447 emit_opcode(cbuf, Assembler::REX_W);
2448 } else {
2449 emit_opcode(cbuf, Assembler::REX_WB);
2450 }
2451 %}
2452
2453 enc_class REX_reg_reg(rRegI dst, rRegI src)
2454 %{
2455 if ($dst$$reg < 8) {
2456 if ($src$$reg >= 8) {
2457 emit_opcode(cbuf, Assembler::REX_B);
2458 }
2459 } else {
2460 if ($src$$reg < 8) {
2461 emit_opcode(cbuf, Assembler::REX_R);
2462 } else {
2463 emit_opcode(cbuf, Assembler::REX_RB);
2464 }
2465 }
2466 %}
2467
2468 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2469 %{
2470 if ($dst$$reg < 8) {
2471 if ($src$$reg < 8) {
2472 emit_opcode(cbuf, Assembler::REX_W);
2473 } else {
2474 emit_opcode(cbuf, Assembler::REX_WB);
2475 }
2476 } else {
2477 if ($src$$reg < 8) {
2478 emit_opcode(cbuf, Assembler::REX_WR);
2479 } else {
2480 emit_opcode(cbuf, Assembler::REX_WRB);
2481 }
2482 }
2483 %}
2484
2485 enc_class REX_reg_mem(rRegI reg, memory mem)
2486 %{
2487 if ($reg$$reg < 8) {
2488 if ($mem$$base < 8) {
2489 if ($mem$$index >= 8) {
2490 emit_opcode(cbuf, Assembler::REX_X);
2491 }
2492 } else {
2493 if ($mem$$index < 8) {
2494 emit_opcode(cbuf, Assembler::REX_B);
2495 } else {
2496 emit_opcode(cbuf, Assembler::REX_XB);
2497 }
2498 }
2499 } else {
2500 if ($mem$$base < 8) {
2501 if ($mem$$index < 8) {
2502 emit_opcode(cbuf, Assembler::REX_R);
2503 } else {
2504 emit_opcode(cbuf, Assembler::REX_RX);
2505 }
2506 } else {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_RB);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_RXB);
2511 }
2512 }
2513 }
2514 %}
2515
2516 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2517 %{
2518 if ($reg$$reg < 8) {
2519 if ($mem$$base < 8) {
2520 if ($mem$$index < 8) {
2521 emit_opcode(cbuf, Assembler::REX_W);
2522 } else {
2523 emit_opcode(cbuf, Assembler::REX_WX);
2524 }
2525 } else {
2526 if ($mem$$index < 8) {
2527 emit_opcode(cbuf, Assembler::REX_WB);
2528 } else {
2529 emit_opcode(cbuf, Assembler::REX_WXB);
2530 }
2531 }
2532 } else {
2533 if ($mem$$base < 8) {
2534 if ($mem$$index < 8) {
2535 emit_opcode(cbuf, Assembler::REX_WR);
2536 } else {
2537 emit_opcode(cbuf, Assembler::REX_WRX);
2538 }
2539 } else {
2540 if ($mem$$index < 8) {
2541 emit_opcode(cbuf, Assembler::REX_WRB);
2542 } else {
2543 emit_opcode(cbuf, Assembler::REX_WRXB);
2544 }
2545 }
2546 }
2547 %}
2548
2549 enc_class reg_mem(rRegI ereg, memory mem)
2550 %{
2551 // High registers handle in encode_RegMem
2552 int reg = $ereg$$reg;
2553 int base = $mem$$base;
2554 int index = $mem$$index;
2555 int scale = $mem$$scale;
2556 int disp = $mem$$disp;
2557 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2558
2559 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2560 %}
2561
2562 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2563 %{
2564 int rm_byte_opcode = $rm_opcode$$constant;
2565
2566 // High registers handle in encode_RegMem
2567 int base = $mem$$base;
2568 int index = $mem$$index;
2569 int scale = $mem$$scale;
2570 int displace = $mem$$disp;
2571
2572 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2573 // working with static
2574 // globals
2575 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2576 disp_reloc);
2577 %}
2578
2579 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2580 %{
2581 int reg_encoding = $dst$$reg;
2582 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2583 int index = 0x04; // 0x04 indicates no index
2584 int scale = 0x00; // 0x00 indicates no scale
2585 int displace = $src1$$constant; // 0x00 indicates no displacement
2586 relocInfo::relocType disp_reloc = relocInfo::none;
2587 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2588 disp_reloc);
2589 %}
2590
2591 enc_class neg_reg(rRegI dst)
2592 %{
2593 int dstenc = $dst$$reg;
2594 if (dstenc >= 8) {
2595 emit_opcode(cbuf, Assembler::REX_B);
2596 dstenc -= 8;
2597 }
2598 // NEG $dst
2599 emit_opcode(cbuf, 0xF7);
2600 emit_rm(cbuf, 0x3, 0x03, dstenc);
2601 %}
2602
2603 enc_class neg_reg_wide(rRegI dst)
2604 %{
2605 int dstenc = $dst$$reg;
2606 if (dstenc < 8) {
2607 emit_opcode(cbuf, Assembler::REX_W);
2608 } else {
2609 emit_opcode(cbuf, Assembler::REX_WB);
2610 dstenc -= 8;
2611 }
2612 // NEG $dst
2613 emit_opcode(cbuf, 0xF7);
2614 emit_rm(cbuf, 0x3, 0x03, dstenc);
2615 %}
2616
2617 enc_class setLT_reg(rRegI dst)
2618 %{
2619 int dstenc = $dst$$reg;
2620 if (dstenc >= 8) {
2621 emit_opcode(cbuf, Assembler::REX_B);
2622 dstenc -= 8;
2623 } else if (dstenc >= 4) {
2624 emit_opcode(cbuf, Assembler::REX);
2625 }
2626 // SETLT $dst
2627 emit_opcode(cbuf, 0x0F);
2628 emit_opcode(cbuf, 0x9C);
2629 emit_rm(cbuf, 0x3, 0x0, dstenc);
2630 %}
2631
2632 enc_class setNZ_reg(rRegI dst)
2633 %{
2634 int dstenc = $dst$$reg;
2635 if (dstenc >= 8) {
2636 emit_opcode(cbuf, Assembler::REX_B);
2637 dstenc -= 8;
2638 } else if (dstenc >= 4) {
2639 emit_opcode(cbuf, Assembler::REX);
2640 }
2641 // SETNZ $dst
2642 emit_opcode(cbuf, 0x0F);
2643 emit_opcode(cbuf, 0x95);
2644 emit_rm(cbuf, 0x3, 0x0, dstenc);
2645 %}
2646
2647
2648 // Compare the lonogs and set -1, 0, or 1 into dst
2649 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2650 %{
2651 int src1enc = $src1$$reg;
2652 int src2enc = $src2$$reg;
2653 int dstenc = $dst$$reg;
2654
2655 // cmpq $src1, $src2
2656 if (src1enc < 8) {
2657 if (src2enc < 8) {
2658 emit_opcode(cbuf, Assembler::REX_W);
2659 } else {
2660 emit_opcode(cbuf, Assembler::REX_WB);
2661 }
2662 } else {
2663 if (src2enc < 8) {
2664 emit_opcode(cbuf, Assembler::REX_WR);
2665 } else {
2666 emit_opcode(cbuf, Assembler::REX_WRB);
2667 }
2668 }
2669 emit_opcode(cbuf, 0x3B);
2670 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2671
2672 // movl $dst, -1
2673 if (dstenc >= 8) {
2674 emit_opcode(cbuf, Assembler::REX_B);
2675 }
2676 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2677 emit_d32(cbuf, -1);
2678
2679 // jl,s done
2680 emit_opcode(cbuf, 0x7C);
2681 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2682
2683 // setne $dst
2684 if (dstenc >= 4) {
2685 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2686 }
2687 emit_opcode(cbuf, 0x0F);
2688 emit_opcode(cbuf, 0x95);
2689 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2690
2691 // movzbl $dst, $dst
2692 if (dstenc >= 4) {
2693 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2694 }
2695 emit_opcode(cbuf, 0x0F);
2696 emit_opcode(cbuf, 0xB6);
2697 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2698 %}
2699
2700 enc_class Push_ResultXD(regD dst) %{
2701 MacroAssembler _masm(&cbuf);
2702 __ fstp_d(Address(rsp, 0));
2703 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2704 __ addptr(rsp, 8);
2705 %}
2706
2707 enc_class Push_SrcXD(regD src) %{
2708 MacroAssembler _masm(&cbuf);
2709 __ subptr(rsp, 8);
2710 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2711 __ fld_d(Address(rsp, 0));
2712 %}
2713
2714
2715 enc_class enc_rethrow()
2716 %{
2717 cbuf.set_insts_mark();
2718 emit_opcode(cbuf, 0xE9); // jmp entry
2719 emit_d32_reloc(cbuf,
2720 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2721 runtime_call_Relocation::spec(),
2722 RELOC_DISP32);
2723 %}
2724
2725 %}
2726
2727
2728
2729 //----------FRAME--------------------------------------------------------------
2730 // Definition of frame structure and management information.
2731 //
2732 // S T A C K L A Y O U T Allocators stack-slot number
2733 // | (to get allocators register number
2734 // G Owned by | | v add OptoReg::stack0())
2735 // r CALLER | |
2736 // o | +--------+ pad to even-align allocators stack-slot
2737 // w V | pad0 | numbers; owned by CALLER
2738 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2739 // h ^ | in | 5
2740 // | | args | 4 Holes in incoming args owned by SELF
2741 // | | | | 3
2742 // | | +--------+
2743 // V | | old out| Empty on Intel, window on Sparc
2744 // | old |preserve| Must be even aligned.
2745 // | SP-+--------+----> Matcher::_old_SP, even aligned
2746 // | | in | 3 area for Intel ret address
2747 // Owned by |preserve| Empty on Sparc.
2748 // SELF +--------+
2749 // | | pad2 | 2 pad to align old SP
2750 // | +--------+ 1
2751 // | | locks | 0
2752 // | +--------+----> OptoReg::stack0(), even aligned
2753 // | | pad1 | 11 pad to align new SP
2754 // | +--------+
2755 // | | | 10
2756 // | | spills | 9 spills
2757 // V | | 8 (pad0 slot for callee)
2758 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2759 // ^ | out | 7
2760 // | | args | 6 Holes in outgoing args owned by CALLEE
2761 // Owned by +--------+
2762 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2763 // | new |preserve| Must be even-aligned.
2764 // | SP-+--------+----> Matcher::_new_SP, even aligned
2765 // | | |
2766 //
2767 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2768 // known from SELF's arguments and the Java calling convention.
2769 // Region 6-7 is determined per call site.
2770 // Note 2: If the calling convention leaves holes in the incoming argument
2771 // area, those holes are owned by SELF. Holes in the outgoing area
2772 // are owned by the CALLEE. Holes should not be nessecary in the
2773 // incoming area, as the Java calling convention is completely under
2774 // the control of the AD file. Doubles can be sorted and packed to
2775 // avoid holes. Holes in the outgoing arguments may be nessecary for
2776 // varargs C calling conventions.
2777 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2778 // even aligned with pad0 as needed.
2779 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2780 // region 6-11 is even aligned; it may be padded out more so that
2781 // the region from SP to FP meets the minimum stack alignment.
2782 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2783 // alignment. Region 11, pad1, may be dynamically extended so that
2784 // SP meets the minimum alignment.
2785
2786 frame
2787 %{
2788 // What direction does stack grow in (assumed to be same for C & Java)
2789 stack_direction(TOWARDS_LOW);
2790
2791 // These three registers define part of the calling convention
2792 // between compiled code and the interpreter.
2793 inline_cache_reg(RAX); // Inline Cache Register
2794 interpreter_method_oop_reg(RBX); // Method Oop Register when
2795 // calling interpreter
2796
2797 // Optional: name the operand used by cisc-spilling to access
2798 // [stack_pointer + offset]
2799 cisc_spilling_operand_name(indOffset32);
2800
2801 // Number of stack slots consumed by locking an object
2802 sync_stack_slots(2);
2803
2804 // Compiled code's Frame Pointer
2805 frame_pointer(RSP);
2806
2807 // Interpreter stores its frame pointer in a register which is
2808 // stored to the stack by I2CAdaptors.
2809 // I2CAdaptors convert from interpreted java to compiled java.
2810 interpreter_frame_pointer(RBP);
2811
2812 // Stack alignment requirement
2813 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2814
2815 // Number of stack slots between incoming argument block and the start of
2816 // a new frame. The PROLOG must add this many slots to the stack. The
2817 // EPILOG must remove this many slots. amd64 needs two slots for
2818 // return address.
2819 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2820
2821 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2822 // for calls to C. Supports the var-args backing area for register parms.
2823 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2824
2825 // The after-PROLOG location of the return address. Location of
2826 // return address specifies a type (REG or STACK) and a number
2827 // representing the register number (i.e. - use a register name) or
2828 // stack slot.
2829 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2830 // Otherwise, it is above the locks and verification slot and alignment word
2831 return_addr(STACK - 2 +
2832 align_up((Compile::current()->in_preserve_stack_slots() +
2833 Compile::current()->fixed_slots()),
2834 stack_alignment_in_slots()));
2835
2836 // Body of function which returns an integer array locating
2837 // arguments either in registers or in stack slots. Passed an array
2838 // of ideal registers called "sig" and a "length" count. Stack-slot
2839 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2840 // arguments for a CALLEE. Incoming stack arguments are
2841 // automatically biased by the preserve_stack_slots field above.
2842
2843 calling_convention
2844 %{
2845 // No difference between ingoing/outgoing just pass false
2846 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2847 %}
2848
2849 c_calling_convention
2850 %{
2851 // This is obviously always outgoing
2852 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2853 %}
2854
2855 // Location of compiled Java return values. Same as C for now.
2856 return_value
2857 %{
2858 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2859 "only return normal values");
2860
2861 static const int lo[Op_RegL + 1] = {
2862 0,
2863 0,
2864 RAX_num, // Op_RegN
2865 RAX_num, // Op_RegI
2866 RAX_num, // Op_RegP
2867 XMM0_num, // Op_RegF
2868 XMM0_num, // Op_RegD
2869 RAX_num // Op_RegL
2870 };
2871 static const int hi[Op_RegL + 1] = {
2872 0,
2873 0,
2874 OptoReg::Bad, // Op_RegN
2875 OptoReg::Bad, // Op_RegI
2876 RAX_H_num, // Op_RegP
2877 OptoReg::Bad, // Op_RegF
2878 XMM0b_num, // Op_RegD
2879 RAX_H_num // Op_RegL
2880 };
2881 // Excluded flags and vector registers.
2882 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2883 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2884 %}
2885 %}
2886
2887 //----------ATTRIBUTES---------------------------------------------------------
2888 //----------Operand Attributes-------------------------------------------------
2889 op_attrib op_cost(0); // Required cost attribute
2890
2891 //----------Instruction Attributes---------------------------------------------
2892 ins_attrib ins_cost(100); // Required cost attribute
2893 ins_attrib ins_size(8); // Required size attribute (in bits)
2894 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2895 // a non-matching short branch variant
2896 // of some long branch?
2897 ins_attrib ins_alignment(1); // Required alignment attribute (must
2898 // be a power of 2) specifies the
2899 // alignment that some part of the
2900 // instruction (not necessarily the
2901 // start) requires. If > 1, a
2902 // compute_padding() function must be
2903 // provided for the instruction
2904
2905 //----------OPERANDS-----------------------------------------------------------
2906 // Operand definitions must precede instruction definitions for correct parsing
2907 // in the ADLC because operands constitute user defined types which are used in
2908 // instruction definitions.
2909
2910 //----------Simple Operands----------------------------------------------------
2911 // Immediate Operands
2912 // Integer Immediate
2913 operand immI()
2914 %{
2915 match(ConI);
2916
2917 op_cost(10);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // Constant for test vs zero
2923 operand immI0()
2924 %{
2925 predicate(n->get_int() == 0);
2926 match(ConI);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 // Constant for increment
2934 operand immI1()
2935 %{
2936 predicate(n->get_int() == 1);
2937 match(ConI);
2938
2939 op_cost(0);
2940 format %{ %}
2941 interface(CONST_INTER);
2942 %}
2943
2944 // Constant for decrement
2945 operand immI_M1()
2946 %{
2947 predicate(n->get_int() == -1);
2948 match(ConI);
2949
2950 op_cost(0);
2951 format %{ %}
2952 interface(CONST_INTER);
2953 %}
2954
2955 // Valid scale values for addressing modes
2956 operand immI2()
2957 %{
2958 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2959 match(ConI);
2960
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 operand immI8()
2966 %{
2967 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2968 match(ConI);
2969
2970 op_cost(5);
2971 format %{ %}
2972 interface(CONST_INTER);
2973 %}
2974
2975 operand immI16()
2976 %{
2977 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2978 match(ConI);
2979
2980 op_cost(10);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985 // Int Immediate non-negative
2986 operand immU31()
2987 %{
2988 predicate(n->get_int() >= 0);
2989 match(ConI);
2990
2991 op_cost(0);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 // Constant for long shifts
2997 operand immI_32()
2998 %{
2999 predicate( n->get_int() == 32 );
3000 match(ConI);
3001
3002 op_cost(0);
3003 format %{ %}
3004 interface(CONST_INTER);
3005 %}
3006
3007 // Constant for long shifts
3008 operand immI_64()
3009 %{
3010 predicate( n->get_int() == 64 );
3011 match(ConI);
3012
3013 op_cost(0);
3014 format %{ %}
3015 interface(CONST_INTER);
3016 %}
3017
3018 // Pointer Immediate
3019 operand immP()
3020 %{
3021 match(ConP);
3022
3023 op_cost(10);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 // NULL Pointer Immediate
3029 operand immP0()
3030 %{
3031 predicate(n->get_ptr() == 0);
3032 match(ConP);
3033
3034 op_cost(5);
3035 format %{ %}
3036 interface(CONST_INTER);
3037 %}
3038
3039 // Pointer Immediate
3040 operand immN() %{
3041 match(ConN);
3042
3043 op_cost(10);
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 operand immNKlass() %{
3049 match(ConNKlass);
3050
3051 op_cost(10);
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3055
3056 // NULL Pointer Immediate
3057 operand immN0() %{
3058 predicate(n->get_narrowcon() == 0);
3059 match(ConN);
3060
3061 op_cost(5);
3062 format %{ %}
3063 interface(CONST_INTER);
3064 %}
3065
3066 operand immP31()
3067 %{
3068 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3069 && (n->get_ptr() >> 31) == 0);
3070 match(ConP);
3071
3072 op_cost(5);
3073 format %{ %}
3074 interface(CONST_INTER);
3075 %}
3076
3077
3078 // Long Immediate
3079 operand immL()
3080 %{
3081 match(ConL);
3082
3083 op_cost(20);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 // Long Immediate 8-bit
3089 operand immL8()
3090 %{
3091 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3092 match(ConL);
3093
3094 op_cost(5);
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3098
3099 // Long Immediate 32-bit unsigned
3100 operand immUL32()
3101 %{
3102 predicate(n->get_long() == (unsigned int) (n->get_long()));
3103 match(ConL);
3104
3105 op_cost(10);
3106 format %{ %}
3107 interface(CONST_INTER);
3108 %}
3109
3110 // Long Immediate 32-bit signed
3111 operand immL32()
3112 %{
3113 predicate(n->get_long() == (int) (n->get_long()));
3114 match(ConL);
3115
3116 op_cost(15);
3117 format %{ %}
3118 interface(CONST_INTER);
3119 %}
3120
3121 // Long Immediate zero
3122 operand immL0()
3123 %{
3124 predicate(n->get_long() == 0L);
3125 match(ConL);
3126
3127 op_cost(10);
3128 format %{ %}
3129 interface(CONST_INTER);
3130 %}
3131
3132 // Constant for increment
3133 operand immL1()
3134 %{
3135 predicate(n->get_long() == 1);
3136 match(ConL);
3137
3138 format %{ %}
3139 interface(CONST_INTER);
3140 %}
3141
3142 // Constant for decrement
3143 operand immL_M1()
3144 %{
3145 predicate(n->get_long() == -1);
3146 match(ConL);
3147
3148 format %{ %}
3149 interface(CONST_INTER);
3150 %}
3151
3152 // Long Immediate: the value 10
3153 operand immL10()
3154 %{
3155 predicate(n->get_long() == 10);
3156 match(ConL);
3157
3158 format %{ %}
3159 interface(CONST_INTER);
3160 %}
3161
3162 // Long immediate from 0 to 127.
3163 // Used for a shorter form of long mul by 10.
3164 operand immL_127()
3165 %{
3166 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3167 match(ConL);
3168
3169 op_cost(10);
3170 format %{ %}
3171 interface(CONST_INTER);
3172 %}
3173
3174 // Long Immediate: low 32-bit mask
3175 operand immL_32bits()
3176 %{
3177 predicate(n->get_long() == 0xFFFFFFFFL);
3178 match(ConL);
3179 op_cost(20);
3180
3181 format %{ %}
3182 interface(CONST_INTER);
3183 %}
3184
3185 // Float Immediate zero
3186 operand immF0()
3187 %{
3188 predicate(jint_cast(n->getf()) == 0);
3189 match(ConF);
3190
3191 op_cost(5);
3192 format %{ %}
3193 interface(CONST_INTER);
3194 %}
3195
3196 // Float Immediate
3197 operand immF()
3198 %{
3199 match(ConF);
3200
3201 op_cost(15);
3202 format %{ %}
3203 interface(CONST_INTER);
3204 %}
3205
3206 // Double Immediate zero
3207 operand immD0()
3208 %{
3209 predicate(jlong_cast(n->getd()) == 0);
3210 match(ConD);
3211
3212 op_cost(5);
3213 format %{ %}
3214 interface(CONST_INTER);
3215 %}
3216
3217 // Double Immediate
3218 operand immD()
3219 %{
3220 match(ConD);
3221
3222 op_cost(15);
3223 format %{ %}
3224 interface(CONST_INTER);
3225 %}
3226
3227 // Immediates for special shifts (sign extend)
3228
3229 // Constants for increment
3230 operand immI_16()
3231 %{
3232 predicate(n->get_int() == 16);
3233 match(ConI);
3234
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 operand immI_24()
3240 %{
3241 predicate(n->get_int() == 24);
3242 match(ConI);
3243
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 // Constant for byte-wide masking
3249 operand immI_255()
3250 %{
3251 predicate(n->get_int() == 255);
3252 match(ConI);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 // Constant for short-wide masking
3259 operand immI_65535()
3260 %{
3261 predicate(n->get_int() == 65535);
3262 match(ConI);
3263
3264 format %{ %}
3265 interface(CONST_INTER);
3266 %}
3267
3268 // Constant for byte-wide masking
3269 operand immL_255()
3270 %{
3271 predicate(n->get_long() == 255);
3272 match(ConL);
3273
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3277
3278 // Constant for short-wide masking
3279 operand immL_65535()
3280 %{
3281 predicate(n->get_long() == 65535);
3282 match(ConL);
3283
3284 format %{ %}
3285 interface(CONST_INTER);
3286 %}
3287
3288 // Register Operands
3289 // Integer Register
3290 operand rRegI()
3291 %{
3292 constraint(ALLOC_IN_RC(int_reg));
3293 match(RegI);
3294
3295 match(rax_RegI);
3296 match(rbx_RegI);
3297 match(rcx_RegI);
3298 match(rdx_RegI);
3299 match(rdi_RegI);
3300
3301 format %{ %}
3302 interface(REG_INTER);
3303 %}
3304
3305 // Special Registers
3306 operand rax_RegI()
3307 %{
3308 constraint(ALLOC_IN_RC(int_rax_reg));
3309 match(RegI);
3310 match(rRegI);
3311
3312 format %{ "RAX" %}
3313 interface(REG_INTER);
3314 %}
3315
3316 // Special Registers
3317 operand rbx_RegI()
3318 %{
3319 constraint(ALLOC_IN_RC(int_rbx_reg));
3320 match(RegI);
3321 match(rRegI);
3322
3323 format %{ "RBX" %}
3324 interface(REG_INTER);
3325 %}
3326
3327 operand rcx_RegI()
3328 %{
3329 constraint(ALLOC_IN_RC(int_rcx_reg));
3330 match(RegI);
3331 match(rRegI);
3332
3333 format %{ "RCX" %}
3334 interface(REG_INTER);
3335 %}
3336
3337 operand rdx_RegI()
3338 %{
3339 constraint(ALLOC_IN_RC(int_rdx_reg));
3340 match(RegI);
3341 match(rRegI);
3342
3343 format %{ "RDX" %}
3344 interface(REG_INTER);
3345 %}
3346
3347 operand rdi_RegI()
3348 %{
3349 constraint(ALLOC_IN_RC(int_rdi_reg));
3350 match(RegI);
3351 match(rRegI);
3352
3353 format %{ "RDI" %}
3354 interface(REG_INTER);
3355 %}
3356
3357 operand no_rcx_RegI()
3358 %{
3359 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3360 match(RegI);
3361 match(rax_RegI);
3362 match(rbx_RegI);
3363 match(rdx_RegI);
3364 match(rdi_RegI);
3365
3366 format %{ %}
3367 interface(REG_INTER);
3368 %}
3369
3370 operand no_rax_rdx_RegI()
3371 %{
3372 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3373 match(RegI);
3374 match(rbx_RegI);
3375 match(rcx_RegI);
3376 match(rdi_RegI);
3377
3378 format %{ %}
3379 interface(REG_INTER);
3380 %}
3381
3382 // Pointer Register
3383 operand any_RegP()
3384 %{
3385 constraint(ALLOC_IN_RC(any_reg));
3386 match(RegP);
3387 match(rax_RegP);
3388 match(rbx_RegP);
3389 match(rdi_RegP);
3390 match(rsi_RegP);
3391 match(rbp_RegP);
3392 match(r15_RegP);
3393 match(rRegP);
3394
3395 format %{ %}
3396 interface(REG_INTER);
3397 %}
3398
3399 operand rRegP()
3400 %{
3401 constraint(ALLOC_IN_RC(ptr_reg));
3402 match(RegP);
3403 match(rax_RegP);
3404 match(rbx_RegP);
3405 match(rdi_RegP);
3406 match(rsi_RegP);
3407 match(rbp_RegP); // See Q&A below about
3408 match(r15_RegP); // r15_RegP and rbp_RegP.
3409
3410 format %{ %}
3411 interface(REG_INTER);
3412 %}
3413
3414 operand rRegN() %{
3415 constraint(ALLOC_IN_RC(int_reg));
3416 match(RegN);
3417
3418 format %{ %}
3419 interface(REG_INTER);
3420 %}
3421
3422 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3423 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3424 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3425 // The output of an instruction is controlled by the allocator, which respects
3426 // register class masks, not match rules. Unless an instruction mentions
3427 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3428 // by the allocator as an input.
3429 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3430 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3431 // result, RBP is not included in the output of the instruction either.
3432
3433 operand no_rax_RegP()
3434 %{
3435 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3436 match(RegP);
3437 match(rbx_RegP);
3438 match(rsi_RegP);
3439 match(rdi_RegP);
3440
3441 format %{ %}
3442 interface(REG_INTER);
3443 %}
3444
3445 // This operand is not allowed to use RBP even if
3446 // RBP is not used to hold the frame pointer.
3447 operand no_rbp_RegP()
3448 %{
3449 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3450 match(RegP);
3451 match(rbx_RegP);
3452 match(rsi_RegP);
3453 match(rdi_RegP);
3454
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 operand no_rax_rbx_RegP()
3460 %{
3461 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3462 match(RegP);
3463 match(rsi_RegP);
3464 match(rdi_RegP);
3465
3466 format %{ %}
3467 interface(REG_INTER);
3468 %}
3469
3470 // Special Registers
3471 // Return a pointer value
3472 operand rax_RegP()
3473 %{
3474 constraint(ALLOC_IN_RC(ptr_rax_reg));
3475 match(RegP);
3476 match(rRegP);
3477
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 // Special Registers
3483 // Return a compressed pointer value
3484 operand rax_RegN()
3485 %{
3486 constraint(ALLOC_IN_RC(int_rax_reg));
3487 match(RegN);
3488 match(rRegN);
3489
3490 format %{ %}
3491 interface(REG_INTER);
3492 %}
3493
3494 // Used in AtomicAdd
3495 operand rbx_RegP()
3496 %{
3497 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3498 match(RegP);
3499 match(rRegP);
3500
3501 format %{ %}
3502 interface(REG_INTER);
3503 %}
3504
3505 operand rsi_RegP()
3506 %{
3507 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3508 match(RegP);
3509 match(rRegP);
3510
3511 format %{ %}
3512 interface(REG_INTER);
3513 %}
3514
3515 // Used in rep stosq
3516 operand rdi_RegP()
3517 %{
3518 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3519 match(RegP);
3520 match(rRegP);
3521
3522 format %{ %}
3523 interface(REG_INTER);
3524 %}
3525
3526 operand r15_RegP()
3527 %{
3528 constraint(ALLOC_IN_RC(ptr_r15_reg));
3529 match(RegP);
3530 match(rRegP);
3531
3532 format %{ %}
3533 interface(REG_INTER);
3534 %}
3535
3536 operand rex_RegP()
3537 %{
3538 constraint(ALLOC_IN_RC(ptr_rex_reg));
3539 match(RegP);
3540 match(rRegP);
3541
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3545
3546 operand rRegL()
3547 %{
3548 constraint(ALLOC_IN_RC(long_reg));
3549 match(RegL);
3550 match(rax_RegL);
3551 match(rdx_RegL);
3552
3553 format %{ %}
3554 interface(REG_INTER);
3555 %}
3556
3557 // Special Registers
3558 operand no_rax_rdx_RegL()
3559 %{
3560 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3561 match(RegL);
3562 match(rRegL);
3563
3564 format %{ %}
3565 interface(REG_INTER);
3566 %}
3567
3568 operand no_rax_RegL()
3569 %{
3570 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3571 match(RegL);
3572 match(rRegL);
3573 match(rdx_RegL);
3574
3575 format %{ %}
3576 interface(REG_INTER);
3577 %}
3578
3579 operand no_rcx_RegL()
3580 %{
3581 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3582 match(RegL);
3583 match(rRegL);
3584
3585 format %{ %}
3586 interface(REG_INTER);
3587 %}
3588
3589 operand rax_RegL()
3590 %{
3591 constraint(ALLOC_IN_RC(long_rax_reg));
3592 match(RegL);
3593 match(rRegL);
3594
3595 format %{ "RAX" %}
3596 interface(REG_INTER);
3597 %}
3598
3599 operand rcx_RegL()
3600 %{
3601 constraint(ALLOC_IN_RC(long_rcx_reg));
3602 match(RegL);
3603 match(rRegL);
3604
3605 format %{ %}
3606 interface(REG_INTER);
3607 %}
3608
3609 operand rdx_RegL()
3610 %{
3611 constraint(ALLOC_IN_RC(long_rdx_reg));
3612 match(RegL);
3613 match(rRegL);
3614
3615 format %{ %}
3616 interface(REG_INTER);
3617 %}
3618
3619 // Flags register, used as output of compare instructions
3620 operand rFlagsReg()
3621 %{
3622 constraint(ALLOC_IN_RC(int_flags));
3623 match(RegFlags);
3624
3625 format %{ "RFLAGS" %}
3626 interface(REG_INTER);
3627 %}
3628
3629 // Flags register, used as output of FLOATING POINT compare instructions
3630 operand rFlagsRegU()
3631 %{
3632 constraint(ALLOC_IN_RC(int_flags));
3633 match(RegFlags);
3634
3635 format %{ "RFLAGS_U" %}
3636 interface(REG_INTER);
3637 %}
3638
3639 operand rFlagsRegUCF() %{
3640 constraint(ALLOC_IN_RC(int_flags));
3641 match(RegFlags);
3642 predicate(false);
3643
3644 format %{ "RFLAGS_U_CF" %}
3645 interface(REG_INTER);
3646 %}
3647
3648 // Float register operands
3649 operand regF() %{
3650 constraint(ALLOC_IN_RC(float_reg));
3651 match(RegF);
3652
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3656
3657 // Double register operands
3658 operand regD() %{
3659 constraint(ALLOC_IN_RC(double_reg));
3660 match(RegD);
3661
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Vectors
3667 operand vecS() %{
3668 constraint(ALLOC_IN_RC(vectors_reg));
3669 match(VecS);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 operand vecD() %{
3676 constraint(ALLOC_IN_RC(vectord_reg));
3677 match(VecD);
3678
3679 format %{ %}
3680 interface(REG_INTER);
3681 %}
3682
3683 operand vecX() %{
3684 constraint(ALLOC_IN_RC(vectorx_reg));
3685 match(VecX);
3686
3687 format %{ %}
3688 interface(REG_INTER);
3689 %}
3690
3691 operand vecY() %{
3692 constraint(ALLOC_IN_RC(vectory_reg));
3693 match(VecY);
3694
3695 format %{ %}
3696 interface(REG_INTER);
3697 %}
3698
3699 //----------Memory Operands----------------------------------------------------
3700 // Direct Memory Operand
3701 // operand direct(immP addr)
3702 // %{
3703 // match(addr);
3704
3705 // format %{ "[$addr]" %}
3706 // interface(MEMORY_INTER) %{
3707 // base(0xFFFFFFFF);
3708 // index(0x4);
3709 // scale(0x0);
3710 // disp($addr);
3711 // %}
3712 // %}
3713
3714 // Indirect Memory Operand
3715 operand indirect(any_RegP reg)
3716 %{
3717 constraint(ALLOC_IN_RC(ptr_reg));
3718 match(reg);
3719
3720 format %{ "[$reg]" %}
3721 interface(MEMORY_INTER) %{
3722 base($reg);
3723 index(0x4);
3724 scale(0x0);
3725 disp(0x0);
3726 %}
3727 %}
3728
3729 // Indirect Memory Plus Short Offset Operand
3730 operand indOffset8(any_RegP reg, immL8 off)
3731 %{
3732 constraint(ALLOC_IN_RC(ptr_reg));
3733 match(AddP reg off);
3734
3735 format %{ "[$reg + $off (8-bit)]" %}
3736 interface(MEMORY_INTER) %{
3737 base($reg);
3738 index(0x4);
3739 scale(0x0);
3740 disp($off);
3741 %}
3742 %}
3743
3744 // Indirect Memory Plus Long Offset Operand
3745 operand indOffset32(any_RegP reg, immL32 off)
3746 %{
3747 constraint(ALLOC_IN_RC(ptr_reg));
3748 match(AddP reg off);
3749
3750 format %{ "[$reg + $off (32-bit)]" %}
3751 interface(MEMORY_INTER) %{
3752 base($reg);
3753 index(0x4);
3754 scale(0x0);
3755 disp($off);
3756 %}
3757 %}
3758
3759 // Indirect Memory Plus Index Register Plus Offset Operand
3760 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3761 %{
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(AddP (AddP reg lreg) off);
3764
3765 op_cost(10);
3766 format %{"[$reg + $off + $lreg]" %}
3767 interface(MEMORY_INTER) %{
3768 base($reg);
3769 index($lreg);
3770 scale(0x0);
3771 disp($off);
3772 %}
3773 %}
3774
3775 // Indirect Memory Plus Index Register Plus Offset Operand
3776 operand indIndex(any_RegP reg, rRegL lreg)
3777 %{
3778 constraint(ALLOC_IN_RC(ptr_reg));
3779 match(AddP reg lreg);
3780
3781 op_cost(10);
3782 format %{"[$reg + $lreg]" %}
3783 interface(MEMORY_INTER) %{
3784 base($reg);
3785 index($lreg);
3786 scale(0x0);
3787 disp(0x0);
3788 %}
3789 %}
3790
3791 // Indirect Memory Times Scale Plus Index Register
3792 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3793 %{
3794 constraint(ALLOC_IN_RC(ptr_reg));
3795 match(AddP reg (LShiftL lreg scale));
3796
3797 op_cost(10);
3798 format %{"[$reg + $lreg << $scale]" %}
3799 interface(MEMORY_INTER) %{
3800 base($reg);
3801 index($lreg);
3802 scale($scale);
3803 disp(0x0);
3804 %}
3805 %}
3806
3807 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3808 %{
3809 constraint(ALLOC_IN_RC(ptr_reg));
3810 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3811 match(AddP reg (LShiftL (ConvI2L idx) scale));
3812
3813 op_cost(10);
3814 format %{"[$reg + pos $idx << $scale]" %}
3815 interface(MEMORY_INTER) %{
3816 base($reg);
3817 index($idx);
3818 scale($scale);
3819 disp(0x0);
3820 %}
3821 %}
3822
3823 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3824 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3825 %{
3826 constraint(ALLOC_IN_RC(ptr_reg));
3827 match(AddP (AddP reg (LShiftL lreg scale)) off);
3828
3829 op_cost(10);
3830 format %{"[$reg + $off + $lreg << $scale]" %}
3831 interface(MEMORY_INTER) %{
3832 base($reg);
3833 index($lreg);
3834 scale($scale);
3835 disp($off);
3836 %}
3837 %}
3838
3839 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3840 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3841 %{
3842 constraint(ALLOC_IN_RC(ptr_reg));
3843 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3844 match(AddP (AddP reg (ConvI2L idx)) off);
3845
3846 op_cost(10);
3847 format %{"[$reg + $off + $idx]" %}
3848 interface(MEMORY_INTER) %{
3849 base($reg);
3850 index($idx);
3851 scale(0x0);
3852 disp($off);
3853 %}
3854 %}
3855
3856 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3857 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3858 %{
3859 constraint(ALLOC_IN_RC(ptr_reg));
3860 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3861 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3862
3863 op_cost(10);
3864 format %{"[$reg + $off + $idx << $scale]" %}
3865 interface(MEMORY_INTER) %{
3866 base($reg);
3867 index($idx);
3868 scale($scale);
3869 disp($off);
3870 %}
3871 %}
3872
3873 // Indirect Narrow Oop Plus Offset Operand
3874 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3875 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3876 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3877 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3878 constraint(ALLOC_IN_RC(ptr_reg));
3879 match(AddP (DecodeN reg) off);
3880
3881 op_cost(10);
3882 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3883 interface(MEMORY_INTER) %{
3884 base(0xc); // R12
3885 index($reg);
3886 scale(0x3);
3887 disp($off);
3888 %}
3889 %}
3890
3891 // Indirect Memory Operand
3892 operand indirectNarrow(rRegN reg)
3893 %{
3894 predicate(Universe::narrow_oop_shift() == 0);
3895 constraint(ALLOC_IN_RC(ptr_reg));
3896 match(DecodeN reg);
3897
3898 format %{ "[$reg]" %}
3899 interface(MEMORY_INTER) %{
3900 base($reg);
3901 index(0x4);
3902 scale(0x0);
3903 disp(0x0);
3904 %}
3905 %}
3906
3907 // Indirect Memory Plus Short Offset Operand
3908 operand indOffset8Narrow(rRegN reg, immL8 off)
3909 %{
3910 predicate(Universe::narrow_oop_shift() == 0);
3911 constraint(ALLOC_IN_RC(ptr_reg));
3912 match(AddP (DecodeN reg) off);
3913
3914 format %{ "[$reg + $off (8-bit)]" %}
3915 interface(MEMORY_INTER) %{
3916 base($reg);
3917 index(0x4);
3918 scale(0x0);
3919 disp($off);
3920 %}
3921 %}
3922
3923 // Indirect Memory Plus Long Offset Operand
3924 operand indOffset32Narrow(rRegN reg, immL32 off)
3925 %{
3926 predicate(Universe::narrow_oop_shift() == 0);
3927 constraint(ALLOC_IN_RC(ptr_reg));
3928 match(AddP (DecodeN reg) off);
3929
3930 format %{ "[$reg + $off (32-bit)]" %}
3931 interface(MEMORY_INTER) %{
3932 base($reg);
3933 index(0x4);
3934 scale(0x0);
3935 disp($off);
3936 %}
3937 %}
3938
3939 // Indirect Memory Plus Index Register Plus Offset Operand
3940 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3941 %{
3942 predicate(Universe::narrow_oop_shift() == 0);
3943 constraint(ALLOC_IN_RC(ptr_reg));
3944 match(AddP (AddP (DecodeN reg) lreg) off);
3945
3946 op_cost(10);
3947 format %{"[$reg + $off + $lreg]" %}
3948 interface(MEMORY_INTER) %{
3949 base($reg);
3950 index($lreg);
3951 scale(0x0);
3952 disp($off);
3953 %}
3954 %}
3955
3956 // Indirect Memory Plus Index Register Plus Offset Operand
3957 operand indIndexNarrow(rRegN reg, rRegL lreg)
3958 %{
3959 predicate(Universe::narrow_oop_shift() == 0);
3960 constraint(ALLOC_IN_RC(ptr_reg));
3961 match(AddP (DecodeN reg) lreg);
3962
3963 op_cost(10);
3964 format %{"[$reg + $lreg]" %}
3965 interface(MEMORY_INTER) %{
3966 base($reg);
3967 index($lreg);
3968 scale(0x0);
3969 disp(0x0);
3970 %}
3971 %}
3972
3973 // Indirect Memory Times Scale Plus Index Register
3974 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3975 %{
3976 predicate(Universe::narrow_oop_shift() == 0);
3977 constraint(ALLOC_IN_RC(ptr_reg));
3978 match(AddP (DecodeN reg) (LShiftL lreg scale));
3979
3980 op_cost(10);
3981 format %{"[$reg + $lreg << $scale]" %}
3982 interface(MEMORY_INTER) %{
3983 base($reg);
3984 index($lreg);
3985 scale($scale);
3986 disp(0x0);
3987 %}
3988 %}
3989
3990 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3991 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3992 %{
3993 predicate(Universe::narrow_oop_shift() == 0);
3994 constraint(ALLOC_IN_RC(ptr_reg));
3995 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3996
3997 op_cost(10);
3998 format %{"[$reg + $off + $lreg << $scale]" %}
3999 interface(MEMORY_INTER) %{
4000 base($reg);
4001 index($lreg);
4002 scale($scale);
4003 disp($off);
4004 %}
4005 %}
4006
4007 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4008 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4009 %{
4010 constraint(ALLOC_IN_RC(ptr_reg));
4011 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4012 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4013
4014 op_cost(10);
4015 format %{"[$reg + $off + $idx]" %}
4016 interface(MEMORY_INTER) %{
4017 base($reg);
4018 index($idx);
4019 scale(0x0);
4020 disp($off);
4021 %}
4022 %}
4023
4024 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4025 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4026 %{
4027 constraint(ALLOC_IN_RC(ptr_reg));
4028 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4029 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4030
4031 op_cost(10);
4032 format %{"[$reg + $off + $idx << $scale]" %}
4033 interface(MEMORY_INTER) %{
4034 base($reg);
4035 index($idx);
4036 scale($scale);
4037 disp($off);
4038 %}
4039 %}
4040
4041 //----------Special Memory Operands--------------------------------------------
4042 // Stack Slot Operand - This operand is used for loading and storing temporary
4043 // values on the stack where a match requires a value to
4044 // flow through memory.
4045 operand stackSlotP(sRegP reg)
4046 %{
4047 constraint(ALLOC_IN_RC(stack_slots));
4048 // No match rule because this operand is only generated in matching
4049
4050 format %{ "[$reg]" %}
4051 interface(MEMORY_INTER) %{
4052 base(0x4); // RSP
4053 index(0x4); // No Index
4054 scale(0x0); // No Scale
4055 disp($reg); // Stack Offset
4056 %}
4057 %}
4058
4059 operand stackSlotI(sRegI reg)
4060 %{
4061 constraint(ALLOC_IN_RC(stack_slots));
4062 // No match rule because this operand is only generated in matching
4063
4064 format %{ "[$reg]" %}
4065 interface(MEMORY_INTER) %{
4066 base(0x4); // RSP
4067 index(0x4); // No Index
4068 scale(0x0); // No Scale
4069 disp($reg); // Stack Offset
4070 %}
4071 %}
4072
4073 operand stackSlotF(sRegF reg)
4074 %{
4075 constraint(ALLOC_IN_RC(stack_slots));
4076 // No match rule because this operand is only generated in matching
4077
4078 format %{ "[$reg]" %}
4079 interface(MEMORY_INTER) %{
4080 base(0x4); // RSP
4081 index(0x4); // No Index
4082 scale(0x0); // No Scale
4083 disp($reg); // Stack Offset
4084 %}
4085 %}
4086
4087 operand stackSlotD(sRegD reg)
4088 %{
4089 constraint(ALLOC_IN_RC(stack_slots));
4090 // No match rule because this operand is only generated in matching
4091
4092 format %{ "[$reg]" %}
4093 interface(MEMORY_INTER) %{
4094 base(0x4); // RSP
4095 index(0x4); // No Index
4096 scale(0x0); // No Scale
4097 disp($reg); // Stack Offset
4098 %}
4099 %}
4100 operand stackSlotL(sRegL reg)
4101 %{
4102 constraint(ALLOC_IN_RC(stack_slots));
4103 // No match rule because this operand is only generated in matching
4104
4105 format %{ "[$reg]" %}
4106 interface(MEMORY_INTER) %{
4107 base(0x4); // RSP
4108 index(0x4); // No Index
4109 scale(0x0); // No Scale
4110 disp($reg); // Stack Offset
4111 %}
4112 %}
4113
4114 //----------Conditional Branch Operands----------------------------------------
4115 // Comparison Op - This is the operation of the comparison, and is limited to
4116 // the following set of codes:
4117 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4118 //
4119 // Other attributes of the comparison, such as unsignedness, are specified
4120 // by the comparison instruction that sets a condition code flags register.
4121 // That result is represented by a flags operand whose subtype is appropriate
4122 // to the unsignedness (etc.) of the comparison.
4123 //
4124 // Later, the instruction which matches both the Comparison Op (a Bool) and
4125 // the flags (produced by the Cmp) specifies the coding of the comparison op
4126 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4127
4128 // Comparision Code
4129 operand cmpOp()
4130 %{
4131 match(Bool);
4132
4133 format %{ "" %}
4134 interface(COND_INTER) %{
4135 equal(0x4, "e");
4136 not_equal(0x5, "ne");
4137 less(0xC, "l");
4138 greater_equal(0xD, "ge");
4139 less_equal(0xE, "le");
4140 greater(0xF, "g");
4141 overflow(0x0, "o");
4142 no_overflow(0x1, "no");
4143 %}
4144 %}
4145
4146 // Comparison Code, unsigned compare. Used by FP also, with
4147 // C2 (unordered) turned into GT or LT already. The other bits
4148 // C0 and C3 are turned into Carry & Zero flags.
4149 operand cmpOpU()
4150 %{
4151 match(Bool);
4152
4153 format %{ "" %}
4154 interface(COND_INTER) %{
4155 equal(0x4, "e");
4156 not_equal(0x5, "ne");
4157 less(0x2, "b");
4158 greater_equal(0x3, "nb");
4159 less_equal(0x6, "be");
4160 greater(0x7, "nbe");
4161 overflow(0x0, "o");
4162 no_overflow(0x1, "no");
4163 %}
4164 %}
4165
4166
4167 // Floating comparisons that don't require any fixup for the unordered case
4168 operand cmpOpUCF() %{
4169 match(Bool);
4170 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4171 n->as_Bool()->_test._test == BoolTest::ge ||
4172 n->as_Bool()->_test._test == BoolTest::le ||
4173 n->as_Bool()->_test._test == BoolTest::gt);
4174 format %{ "" %}
4175 interface(COND_INTER) %{
4176 equal(0x4, "e");
4177 not_equal(0x5, "ne");
4178 less(0x2, "b");
4179 greater_equal(0x3, "nb");
4180 less_equal(0x6, "be");
4181 greater(0x7, "nbe");
4182 overflow(0x0, "o");
4183 no_overflow(0x1, "no");
4184 %}
4185 %}
4186
4187
4188 // Floating comparisons that can be fixed up with extra conditional jumps
4189 operand cmpOpUCF2() %{
4190 match(Bool);
4191 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4192 n->as_Bool()->_test._test == BoolTest::eq);
4193 format %{ "" %}
4194 interface(COND_INTER) %{
4195 equal(0x4, "e");
4196 not_equal(0x5, "ne");
4197 less(0x2, "b");
4198 greater_equal(0x3, "nb");
4199 less_equal(0x6, "be");
4200 greater(0x7, "nbe");
4201 overflow(0x0, "o");
4202 no_overflow(0x1, "no");
4203 %}
4204 %}
4205
4206
4207 //----------OPERAND CLASSES----------------------------------------------------
4208 // Operand Classes are groups of operands that are used as to simplify
4209 // instruction definitions by not requiring the AD writer to specify separate
4210 // instructions for every form of operand when the instruction accepts
4211 // multiple operand types with the same basic encoding and format. The classic
4212 // case of this is memory operands.
4213
4214 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4215 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4216 indCompressedOopOffset,
4217 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4218 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4219 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4220
4221 //----------PIPELINE-----------------------------------------------------------
4222 // Rules which define the behavior of the target architectures pipeline.
4223 pipeline %{
4224
4225 //----------ATTRIBUTES---------------------------------------------------------
4226 attributes %{
4227 variable_size_instructions; // Fixed size instructions
4228 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4229 instruction_unit_size = 1; // An instruction is 1 bytes long
4230 instruction_fetch_unit_size = 16; // The processor fetches one line
4231 instruction_fetch_units = 1; // of 16 bytes
4232
4233 // List of nop instructions
4234 nops( MachNop );
4235 %}
4236
4237 //----------RESOURCES----------------------------------------------------------
4238 // Resources are the functional units available to the machine
4239
4240 // Generic P2/P3 pipeline
4241 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4242 // 3 instructions decoded per cycle.
4243 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4244 // 3 ALU op, only ALU0 handles mul instructions.
4245 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4246 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4247 BR, FPU,
4248 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4249
4250 //----------PIPELINE DESCRIPTION-----------------------------------------------
4251 // Pipeline Description specifies the stages in the machine's pipeline
4252
4253 // Generic P2/P3 pipeline
4254 pipe_desc(S0, S1, S2, S3, S4, S5);
4255
4256 //----------PIPELINE CLASSES---------------------------------------------------
4257 // Pipeline Classes describe the stages in which input and output are
4258 // referenced by the hardware pipeline.
4259
4260 // Naming convention: ialu or fpu
4261 // Then: _reg
4262 // Then: _reg if there is a 2nd register
4263 // Then: _long if it's a pair of instructions implementing a long
4264 // Then: _fat if it requires the big decoder
4265 // Or: _mem if it requires the big decoder and a memory unit.
4266
4267 // Integer ALU reg operation
4268 pipe_class ialu_reg(rRegI dst)
4269 %{
4270 single_instruction;
4271 dst : S4(write);
4272 dst : S3(read);
4273 DECODE : S0; // any decoder
4274 ALU : S3; // any alu
4275 %}
4276
4277 // Long ALU reg operation
4278 pipe_class ialu_reg_long(rRegL dst)
4279 %{
4280 instruction_count(2);
4281 dst : S4(write);
4282 dst : S3(read);
4283 DECODE : S0(2); // any 2 decoders
4284 ALU : S3(2); // both alus
4285 %}
4286
4287 // Integer ALU reg operation using big decoder
4288 pipe_class ialu_reg_fat(rRegI dst)
4289 %{
4290 single_instruction;
4291 dst : S4(write);
4292 dst : S3(read);
4293 D0 : S0; // big decoder only
4294 ALU : S3; // any alu
4295 %}
4296
4297 // Long ALU reg operation using big decoder
4298 pipe_class ialu_reg_long_fat(rRegL dst)
4299 %{
4300 instruction_count(2);
4301 dst : S4(write);
4302 dst : S3(read);
4303 D0 : S0(2); // big decoder only; twice
4304 ALU : S3(2); // any 2 alus
4305 %}
4306
4307 // Integer ALU reg-reg operation
4308 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4309 %{
4310 single_instruction;
4311 dst : S4(write);
4312 src : S3(read);
4313 DECODE : S0; // any decoder
4314 ALU : S3; // any alu
4315 %}
4316
4317 // Long ALU reg-reg operation
4318 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4319 %{
4320 instruction_count(2);
4321 dst : S4(write);
4322 src : S3(read);
4323 DECODE : S0(2); // any 2 decoders
4324 ALU : S3(2); // both alus
4325 %}
4326
4327 // Integer ALU reg-reg operation
4328 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4329 %{
4330 single_instruction;
4331 dst : S4(write);
4332 src : S3(read);
4333 D0 : S0; // big decoder only
4334 ALU : S3; // any alu
4335 %}
4336
4337 // Long ALU reg-reg operation
4338 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4339 %{
4340 instruction_count(2);
4341 dst : S4(write);
4342 src : S3(read);
4343 D0 : S0(2); // big decoder only; twice
4344 ALU : S3(2); // both alus
4345 %}
4346
4347 // Integer ALU reg-mem operation
4348 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4349 %{
4350 single_instruction;
4351 dst : S5(write);
4352 mem : S3(read);
4353 D0 : S0; // big decoder only
4354 ALU : S4; // any alu
4355 MEM : S3; // any mem
4356 %}
4357
4358 // Integer mem operation (prefetch)
4359 pipe_class ialu_mem(memory mem)
4360 %{
4361 single_instruction;
4362 mem : S3(read);
4363 D0 : S0; // big decoder only
4364 MEM : S3; // any mem
4365 %}
4366
4367 // Integer Store to Memory
4368 pipe_class ialu_mem_reg(memory mem, rRegI src)
4369 %{
4370 single_instruction;
4371 mem : S3(read);
4372 src : S5(read);
4373 D0 : S0; // big decoder only
4374 ALU : S4; // any alu
4375 MEM : S3;
4376 %}
4377
4378 // // Long Store to Memory
4379 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4380 // %{
4381 // instruction_count(2);
4382 // mem : S3(read);
4383 // src : S5(read);
4384 // D0 : S0(2); // big decoder only; twice
4385 // ALU : S4(2); // any 2 alus
4386 // MEM : S3(2); // Both mems
4387 // %}
4388
4389 // Integer Store to Memory
4390 pipe_class ialu_mem_imm(memory mem)
4391 %{
4392 single_instruction;
4393 mem : S3(read);
4394 D0 : S0; // big decoder only
4395 ALU : S4; // any alu
4396 MEM : S3;
4397 %}
4398
4399 // Integer ALU0 reg-reg operation
4400 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4401 %{
4402 single_instruction;
4403 dst : S4(write);
4404 src : S3(read);
4405 D0 : S0; // Big decoder only
4406 ALU0 : S3; // only alu0
4407 %}
4408
4409 // Integer ALU0 reg-mem operation
4410 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4411 %{
4412 single_instruction;
4413 dst : S5(write);
4414 mem : S3(read);
4415 D0 : S0; // big decoder only
4416 ALU0 : S4; // ALU0 only
4417 MEM : S3; // any mem
4418 %}
4419
4420 // Integer ALU reg-reg operation
4421 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4422 %{
4423 single_instruction;
4424 cr : S4(write);
4425 src1 : S3(read);
4426 src2 : S3(read);
4427 DECODE : S0; // any decoder
4428 ALU : S3; // any alu
4429 %}
4430
4431 // Integer ALU reg-imm operation
4432 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4433 %{
4434 single_instruction;
4435 cr : S4(write);
4436 src1 : S3(read);
4437 DECODE : S0; // any decoder
4438 ALU : S3; // any alu
4439 %}
4440
4441 // Integer ALU reg-mem operation
4442 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4443 %{
4444 single_instruction;
4445 cr : S4(write);
4446 src1 : S3(read);
4447 src2 : S3(read);
4448 D0 : S0; // big decoder only
4449 ALU : S4; // any alu
4450 MEM : S3;
4451 %}
4452
4453 // Conditional move reg-reg
4454 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4455 %{
4456 instruction_count(4);
4457 y : S4(read);
4458 q : S3(read);
4459 p : S3(read);
4460 DECODE : S0(4); // any decoder
4461 %}
4462
4463 // Conditional move reg-reg
4464 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4465 %{
4466 single_instruction;
4467 dst : S4(write);
4468 src : S3(read);
4469 cr : S3(read);
4470 DECODE : S0; // any decoder
4471 %}
4472
4473 // Conditional move reg-mem
4474 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4475 %{
4476 single_instruction;
4477 dst : S4(write);
4478 src : S3(read);
4479 cr : S3(read);
4480 DECODE : S0; // any decoder
4481 MEM : S3;
4482 %}
4483
4484 // Conditional move reg-reg long
4485 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4486 %{
4487 single_instruction;
4488 dst : S4(write);
4489 src : S3(read);
4490 cr : S3(read);
4491 DECODE : S0(2); // any 2 decoders
4492 %}
4493
4494 // XXX
4495 // // Conditional move double reg-reg
4496 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4497 // %{
4498 // single_instruction;
4499 // dst : S4(write);
4500 // src : S3(read);
4501 // cr : S3(read);
4502 // DECODE : S0; // any decoder
4503 // %}
4504
4505 // Float reg-reg operation
4506 pipe_class fpu_reg(regD dst)
4507 %{
4508 instruction_count(2);
4509 dst : S3(read);
4510 DECODE : S0(2); // any 2 decoders
4511 FPU : S3;
4512 %}
4513
4514 // Float reg-reg operation
4515 pipe_class fpu_reg_reg(regD dst, regD src)
4516 %{
4517 instruction_count(2);
4518 dst : S4(write);
4519 src : S3(read);
4520 DECODE : S0(2); // any 2 decoders
4521 FPU : S3;
4522 %}
4523
4524 // Float reg-reg operation
4525 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4526 %{
4527 instruction_count(3);
4528 dst : S4(write);
4529 src1 : S3(read);
4530 src2 : S3(read);
4531 DECODE : S0(3); // any 3 decoders
4532 FPU : S3(2);
4533 %}
4534
4535 // Float reg-reg operation
4536 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4537 %{
4538 instruction_count(4);
4539 dst : S4(write);
4540 src1 : S3(read);
4541 src2 : S3(read);
4542 src3 : S3(read);
4543 DECODE : S0(4); // any 3 decoders
4544 FPU : S3(2);
4545 %}
4546
4547 // Float reg-reg operation
4548 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4549 %{
4550 instruction_count(4);
4551 dst : S4(write);
4552 src1 : S3(read);
4553 src2 : S3(read);
4554 src3 : S3(read);
4555 DECODE : S1(3); // any 3 decoders
4556 D0 : S0; // Big decoder only
4557 FPU : S3(2);
4558 MEM : S3;
4559 %}
4560
4561 // Float reg-mem operation
4562 pipe_class fpu_reg_mem(regD dst, memory mem)
4563 %{
4564 instruction_count(2);
4565 dst : S5(write);
4566 mem : S3(read);
4567 D0 : S0; // big decoder only
4568 DECODE : S1; // any decoder for FPU POP
4569 FPU : S4;
4570 MEM : S3; // any mem
4571 %}
4572
4573 // Float reg-mem operation
4574 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4575 %{
4576 instruction_count(3);
4577 dst : S5(write);
4578 src1 : S3(read);
4579 mem : S3(read);
4580 D0 : S0; // big decoder only
4581 DECODE : S1(2); // any decoder for FPU POP
4582 FPU : S4;
4583 MEM : S3; // any mem
4584 %}
4585
4586 // Float mem-reg operation
4587 pipe_class fpu_mem_reg(memory mem, regD src)
4588 %{
4589 instruction_count(2);
4590 src : S5(read);
4591 mem : S3(read);
4592 DECODE : S0; // any decoder for FPU PUSH
4593 D0 : S1; // big decoder only
4594 FPU : S4;
4595 MEM : S3; // any mem
4596 %}
4597
4598 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4599 %{
4600 instruction_count(3);
4601 src1 : S3(read);
4602 src2 : S3(read);
4603 mem : S3(read);
4604 DECODE : S0(2); // any decoder for FPU PUSH
4605 D0 : S1; // big decoder only
4606 FPU : S4;
4607 MEM : S3; // any mem
4608 %}
4609
4610 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4611 %{
4612 instruction_count(3);
4613 src1 : S3(read);
4614 src2 : S3(read);
4615 mem : S4(read);
4616 DECODE : S0; // any decoder for FPU PUSH
4617 D0 : S0(2); // big decoder only
4618 FPU : S4;
4619 MEM : S3(2); // any mem
4620 %}
4621
4622 pipe_class fpu_mem_mem(memory dst, memory src1)
4623 %{
4624 instruction_count(2);
4625 src1 : S3(read);
4626 dst : S4(read);
4627 D0 : S0(2); // big decoder only
4628 MEM : S3(2); // any mem
4629 %}
4630
4631 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4632 %{
4633 instruction_count(3);
4634 src1 : S3(read);
4635 src2 : S3(read);
4636 dst : S4(read);
4637 D0 : S0(3); // big decoder only
4638 FPU : S4;
4639 MEM : S3(3); // any mem
4640 %}
4641
4642 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4643 %{
4644 instruction_count(3);
4645 src1 : S4(read);
4646 mem : S4(read);
4647 DECODE : S0; // any decoder for FPU PUSH
4648 D0 : S0(2); // big decoder only
4649 FPU : S4;
4650 MEM : S3(2); // any mem
4651 %}
4652
4653 // Float load constant
4654 pipe_class fpu_reg_con(regD dst)
4655 %{
4656 instruction_count(2);
4657 dst : S5(write);
4658 D0 : S0; // big decoder only for the load
4659 DECODE : S1; // any decoder for FPU POP
4660 FPU : S4;
4661 MEM : S3; // any mem
4662 %}
4663
4664 // Float load constant
4665 pipe_class fpu_reg_reg_con(regD dst, regD src)
4666 %{
4667 instruction_count(3);
4668 dst : S5(write);
4669 src : S3(read);
4670 D0 : S0; // big decoder only for the load
4671 DECODE : S1(2); // any decoder for FPU POP
4672 FPU : S4;
4673 MEM : S3; // any mem
4674 %}
4675
4676 // UnConditional branch
4677 pipe_class pipe_jmp(label labl)
4678 %{
4679 single_instruction;
4680 BR : S3;
4681 %}
4682
4683 // Conditional branch
4684 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4685 %{
4686 single_instruction;
4687 cr : S1(read);
4688 BR : S3;
4689 %}
4690
4691 // Allocation idiom
4692 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4693 %{
4694 instruction_count(1); force_serialization;
4695 fixed_latency(6);
4696 heap_ptr : S3(read);
4697 DECODE : S0(3);
4698 D0 : S2;
4699 MEM : S3;
4700 ALU : S3(2);
4701 dst : S5(write);
4702 BR : S5;
4703 %}
4704
4705 // Generic big/slow expanded idiom
4706 pipe_class pipe_slow()
4707 %{
4708 instruction_count(10); multiple_bundles; force_serialization;
4709 fixed_latency(100);
4710 D0 : S0(2);
4711 MEM : S3(2);
4712 %}
4713
4714 // The real do-nothing guy
4715 pipe_class empty()
4716 %{
4717 instruction_count(0);
4718 %}
4719
4720 // Define the class for the Nop node
4721 define
4722 %{
4723 MachNop = empty;
4724 %}
4725
4726 %}
4727
4728 //----------INSTRUCTIONS-------------------------------------------------------
4729 //
4730 // match -- States which machine-independent subtree may be replaced
4731 // by this instruction.
4732 // ins_cost -- The estimated cost of this instruction is used by instruction
4733 // selection to identify a minimum cost tree of machine
4734 // instructions that matches a tree of machine-independent
4735 // instructions.
4736 // format -- A string providing the disassembly for this instruction.
4737 // The value of an instruction's operand may be inserted
4738 // by referring to it with a '$' prefix.
4739 // opcode -- Three instruction opcodes may be provided. These are referred
4740 // to within an encode class as $primary, $secondary, and $tertiary
4741 // rrspectively. The primary opcode is commonly used to
4742 // indicate the type of machine instruction, while secondary
4743 // and tertiary are often used for prefix options or addressing
4744 // modes.
4745 // ins_encode -- A list of encode classes with parameters. The encode class
4746 // name must have been defined in an 'enc_class' specification
4747 // in the encode section of the architecture description.
4748
4749
4750 //----------Load/Store/Move Instructions---------------------------------------
4751 //----------Load Instructions--------------------------------------------------
4752
4753 // Load Byte (8 bit signed)
4754 instruct loadB(rRegI dst, memory mem)
4755 %{
4756 match(Set dst (LoadB mem));
4757
4758 ins_cost(125);
4759 format %{ "movsbl $dst, $mem\t# byte" %}
4760
4761 ins_encode %{
4762 __ movsbl($dst$$Register, $mem$$Address);
4763 %}
4764
4765 ins_pipe(ialu_reg_mem);
4766 %}
4767
4768 // Load Byte (8 bit signed) into Long Register
4769 instruct loadB2L(rRegL dst, memory mem)
4770 %{
4771 match(Set dst (ConvI2L (LoadB mem)));
4772
4773 ins_cost(125);
4774 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4775
4776 ins_encode %{
4777 __ movsbq($dst$$Register, $mem$$Address);
4778 %}
4779
4780 ins_pipe(ialu_reg_mem);
4781 %}
4782
4783 // Load Unsigned Byte (8 bit UNsigned)
4784 instruct loadUB(rRegI dst, memory mem)
4785 %{
4786 match(Set dst (LoadUB mem));
4787
4788 ins_cost(125);
4789 format %{ "movzbl $dst, $mem\t# ubyte" %}
4790
4791 ins_encode %{
4792 __ movzbl($dst$$Register, $mem$$Address);
4793 %}
4794
4795 ins_pipe(ialu_reg_mem);
4796 %}
4797
4798 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4799 instruct loadUB2L(rRegL dst, memory mem)
4800 %{
4801 match(Set dst (ConvI2L (LoadUB mem)));
4802
4803 ins_cost(125);
4804 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4805
4806 ins_encode %{
4807 __ movzbq($dst$$Register, $mem$$Address);
4808 %}
4809
4810 ins_pipe(ialu_reg_mem);
4811 %}
4812
4813 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4814 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4815 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4816 effect(KILL cr);
4817
4818 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4819 "andl $dst, right_n_bits($mask, 8)" %}
4820 ins_encode %{
4821 Register Rdst = $dst$$Register;
4822 __ movzbq(Rdst, $mem$$Address);
4823 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4824 %}
4825 ins_pipe(ialu_reg_mem);
4826 %}
4827
4828 // Load Short (16 bit signed)
4829 instruct loadS(rRegI dst, memory mem)
4830 %{
4831 match(Set dst (LoadS mem));
4832
4833 ins_cost(125);
4834 format %{ "movswl $dst, $mem\t# short" %}
4835
4836 ins_encode %{
4837 __ movswl($dst$$Register, $mem$$Address);
4838 %}
4839
4840 ins_pipe(ialu_reg_mem);
4841 %}
4842
4843 // Load Short (16 bit signed) to Byte (8 bit signed)
4844 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4845 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4846
4847 ins_cost(125);
4848 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4849 ins_encode %{
4850 __ movsbl($dst$$Register, $mem$$Address);
4851 %}
4852 ins_pipe(ialu_reg_mem);
4853 %}
4854
4855 // Load Short (16 bit signed) into Long Register
4856 instruct loadS2L(rRegL dst, memory mem)
4857 %{
4858 match(Set dst (ConvI2L (LoadS mem)));
4859
4860 ins_cost(125);
4861 format %{ "movswq $dst, $mem\t# short -> long" %}
4862
4863 ins_encode %{
4864 __ movswq($dst$$Register, $mem$$Address);
4865 %}
4866
4867 ins_pipe(ialu_reg_mem);
4868 %}
4869
4870 // Load Unsigned Short/Char (16 bit UNsigned)
4871 instruct loadUS(rRegI dst, memory mem)
4872 %{
4873 match(Set dst (LoadUS mem));
4874
4875 ins_cost(125);
4876 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4877
4878 ins_encode %{
4879 __ movzwl($dst$$Register, $mem$$Address);
4880 %}
4881
4882 ins_pipe(ialu_reg_mem);
4883 %}
4884
4885 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4886 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4887 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4888
4889 ins_cost(125);
4890 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4891 ins_encode %{
4892 __ movsbl($dst$$Register, $mem$$Address);
4893 %}
4894 ins_pipe(ialu_reg_mem);
4895 %}
4896
4897 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4898 instruct loadUS2L(rRegL dst, memory mem)
4899 %{
4900 match(Set dst (ConvI2L (LoadUS mem)));
4901
4902 ins_cost(125);
4903 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4904
4905 ins_encode %{
4906 __ movzwq($dst$$Register, $mem$$Address);
4907 %}
4908
4909 ins_pipe(ialu_reg_mem);
4910 %}
4911
4912 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4913 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4914 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4915
4916 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4917 ins_encode %{
4918 __ movzbq($dst$$Register, $mem$$Address);
4919 %}
4920 ins_pipe(ialu_reg_mem);
4921 %}
4922
4923 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4924 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4925 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4926 effect(KILL cr);
4927
4928 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4929 "andl $dst, right_n_bits($mask, 16)" %}
4930 ins_encode %{
4931 Register Rdst = $dst$$Register;
4932 __ movzwq(Rdst, $mem$$Address);
4933 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4934 %}
4935 ins_pipe(ialu_reg_mem);
4936 %}
4937
4938 // Load Integer
4939 instruct loadI(rRegI dst, memory mem)
4940 %{
4941 match(Set dst (LoadI mem));
4942
4943 ins_cost(125);
4944 format %{ "movl $dst, $mem\t# int" %}
4945
4946 ins_encode %{
4947 __ movl($dst$$Register, $mem$$Address);
4948 %}
4949
4950 ins_pipe(ialu_reg_mem);
4951 %}
4952
4953 // Load Integer (32 bit signed) to Byte (8 bit signed)
4954 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4955 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4956
4957 ins_cost(125);
4958 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4959 ins_encode %{
4960 __ movsbl($dst$$Register, $mem$$Address);
4961 %}
4962 ins_pipe(ialu_reg_mem);
4963 %}
4964
4965 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4966 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4967 match(Set dst (AndI (LoadI mem) mask));
4968
4969 ins_cost(125);
4970 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4971 ins_encode %{
4972 __ movzbl($dst$$Register, $mem$$Address);
4973 %}
4974 ins_pipe(ialu_reg_mem);
4975 %}
4976
4977 // Load Integer (32 bit signed) to Short (16 bit signed)
4978 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4979 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4980
4981 ins_cost(125);
4982 format %{ "movswl $dst, $mem\t# int -> short" %}
4983 ins_encode %{
4984 __ movswl($dst$$Register, $mem$$Address);
4985 %}
4986 ins_pipe(ialu_reg_mem);
4987 %}
4988
4989 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4990 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4991 match(Set dst (AndI (LoadI mem) mask));
4992
4993 ins_cost(125);
4994 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4995 ins_encode %{
4996 __ movzwl($dst$$Register, $mem$$Address);
4997 %}
4998 ins_pipe(ialu_reg_mem);
4999 %}
5000
5001 // Load Integer into Long Register
5002 instruct loadI2L(rRegL dst, memory mem)
5003 %{
5004 match(Set dst (ConvI2L (LoadI mem)));
5005
5006 ins_cost(125);
5007 format %{ "movslq $dst, $mem\t# int -> long" %}
5008
5009 ins_encode %{
5010 __ movslq($dst$$Register, $mem$$Address);
5011 %}
5012
5013 ins_pipe(ialu_reg_mem);
5014 %}
5015
5016 // Load Integer with mask 0xFF into Long Register
5017 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5018 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5019
5020 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5021 ins_encode %{
5022 __ movzbq($dst$$Register, $mem$$Address);
5023 %}
5024 ins_pipe(ialu_reg_mem);
5025 %}
5026
5027 // Load Integer with mask 0xFFFF into Long Register
5028 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5029 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5030
5031 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5032 ins_encode %{
5033 __ movzwq($dst$$Register, $mem$$Address);
5034 %}
5035 ins_pipe(ialu_reg_mem);
5036 %}
5037
5038 // Load Integer with a 31-bit mask into Long Register
5039 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5040 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5041 effect(KILL cr);
5042
5043 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5044 "andl $dst, $mask" %}
5045 ins_encode %{
5046 Register Rdst = $dst$$Register;
5047 __ movl(Rdst, $mem$$Address);
5048 __ andl(Rdst, $mask$$constant);
5049 %}
5050 ins_pipe(ialu_reg_mem);
5051 %}
5052
5053 // Load Unsigned Integer into Long Register
5054 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5055 %{
5056 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5057
5058 ins_cost(125);
5059 format %{ "movl $dst, $mem\t# uint -> long" %}
5060
5061 ins_encode %{
5062 __ movl($dst$$Register, $mem$$Address);
5063 %}
5064
5065 ins_pipe(ialu_reg_mem);
5066 %}
5067
5068 // Load Long
5069 instruct loadL(rRegL dst, memory mem)
5070 %{
5071 match(Set dst (LoadL mem));
5072
5073 ins_cost(125);
5074 format %{ "movq $dst, $mem\t# long" %}
5075
5076 ins_encode %{
5077 __ movq($dst$$Register, $mem$$Address);
5078 %}
5079
5080 ins_pipe(ialu_reg_mem); // XXX
5081 %}
5082
5083 // Load Range
5084 instruct loadRange(rRegI dst, memory mem)
5085 %{
5086 match(Set dst (LoadRange mem));
5087
5088 ins_cost(125); // XXX
5089 format %{ "movl $dst, $mem\t# range" %}
5090 opcode(0x8B);
5091 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5092 ins_pipe(ialu_reg_mem);
5093 %}
5094
5095 // Load Pointer
5096 instruct loadP(rRegP dst, memory mem)
5097 %{
5098 match(Set dst (LoadP mem));
5099
5100 ins_cost(125); // XXX
5101 format %{ "movq $dst, $mem\t# ptr" %}
5102 opcode(0x8B);
5103 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5104 ins_pipe(ialu_reg_mem); // XXX
5105 %}
5106
5107 // Load Compressed Pointer
5108 instruct loadN(rRegN dst, memory mem)
5109 %{
5110 match(Set dst (LoadN mem));
5111
5112 ins_cost(125); // XXX
5113 format %{ "movl $dst, $mem\t# compressed ptr" %}
5114 ins_encode %{
5115 __ movl($dst$$Register, $mem$$Address);
5116 %}
5117 ins_pipe(ialu_reg_mem); // XXX
5118 %}
5119
5120
5121 // Load Klass Pointer
5122 instruct loadKlass(rRegP dst, memory mem)
5123 %{
5124 match(Set dst (LoadKlass mem));
5125
5126 ins_cost(125); // XXX
5127 format %{ "movq $dst, $mem\t# class" %}
5128 opcode(0x8B);
5129 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5130 ins_pipe(ialu_reg_mem); // XXX
5131 %}
5132
5133 // Load narrow Klass Pointer
5134 instruct loadNKlass(rRegN dst, memory mem)
5135 %{
5136 match(Set dst (LoadNKlass mem));
5137
5138 ins_cost(125); // XXX
5139 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5140 ins_encode %{
5141 __ movl($dst$$Register, $mem$$Address);
5142 %}
5143 ins_pipe(ialu_reg_mem); // XXX
5144 %}
5145
5146 // Load Float
5147 instruct loadF(regF dst, memory mem)
5148 %{
5149 match(Set dst (LoadF mem));
5150
5151 ins_cost(145); // XXX
5152 format %{ "movss $dst, $mem\t# float" %}
5153 ins_encode %{
5154 __ movflt($dst$$XMMRegister, $mem$$Address);
5155 %}
5156 ins_pipe(pipe_slow); // XXX
5157 %}
5158
5159 // Load Double
5160 instruct loadD_partial(regD dst, memory mem)
5161 %{
5162 predicate(!UseXmmLoadAndClearUpper);
5163 match(Set dst (LoadD mem));
5164
5165 ins_cost(145); // XXX
5166 format %{ "movlpd $dst, $mem\t# double" %}
5167 ins_encode %{
5168 __ movdbl($dst$$XMMRegister, $mem$$Address);
5169 %}
5170 ins_pipe(pipe_slow); // XXX
5171 %}
5172
5173 instruct loadD(regD dst, memory mem)
5174 %{
5175 predicate(UseXmmLoadAndClearUpper);
5176 match(Set dst (LoadD mem));
5177
5178 ins_cost(145); // XXX
5179 format %{ "movsd $dst, $mem\t# double" %}
5180 ins_encode %{
5181 __ movdbl($dst$$XMMRegister, $mem$$Address);
5182 %}
5183 ins_pipe(pipe_slow); // XXX
5184 %}
5185
5186 // Load Effective Address
5187 instruct leaP8(rRegP dst, indOffset8 mem)
5188 %{
5189 match(Set dst mem);
5190
5191 ins_cost(110); // XXX
5192 format %{ "leaq $dst, $mem\t# ptr 8" %}
5193 opcode(0x8D);
5194 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5195 ins_pipe(ialu_reg_reg_fat);
5196 %}
5197
5198 instruct leaP32(rRegP dst, indOffset32 mem)
5199 %{
5200 match(Set dst mem);
5201
5202 ins_cost(110);
5203 format %{ "leaq $dst, $mem\t# ptr 32" %}
5204 opcode(0x8D);
5205 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5206 ins_pipe(ialu_reg_reg_fat);
5207 %}
5208
5209 // instruct leaPIdx(rRegP dst, indIndex mem)
5210 // %{
5211 // match(Set dst mem);
5212
5213 // ins_cost(110);
5214 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5215 // opcode(0x8D);
5216 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5217 // ins_pipe(ialu_reg_reg_fat);
5218 // %}
5219
5220 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5221 %{
5222 match(Set dst mem);
5223
5224 ins_cost(110);
5225 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5226 opcode(0x8D);
5227 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5228 ins_pipe(ialu_reg_reg_fat);
5229 %}
5230
5231 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5232 %{
5233 match(Set dst mem);
5234
5235 ins_cost(110);
5236 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5237 opcode(0x8D);
5238 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5239 ins_pipe(ialu_reg_reg_fat);
5240 %}
5241
5242 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5243 %{
5244 match(Set dst mem);
5245
5246 ins_cost(110);
5247 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5248 opcode(0x8D);
5249 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5250 ins_pipe(ialu_reg_reg_fat);
5251 %}
5252
5253 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5254 %{
5255 match(Set dst mem);
5256
5257 ins_cost(110);
5258 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5259 opcode(0x8D);
5260 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5261 ins_pipe(ialu_reg_reg_fat);
5262 %}
5263
5264 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5265 %{
5266 match(Set dst mem);
5267
5268 ins_cost(110);
5269 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5270 opcode(0x8D);
5271 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5272 ins_pipe(ialu_reg_reg_fat);
5273 %}
5274
5275 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5276 %{
5277 match(Set dst mem);
5278
5279 ins_cost(110);
5280 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5281 opcode(0x8D);
5282 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5283 ins_pipe(ialu_reg_reg_fat);
5284 %}
5285
5286 // Load Effective Address which uses Narrow (32-bits) oop
5287 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5288 %{
5289 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5290 match(Set dst mem);
5291
5292 ins_cost(110);
5293 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5294 opcode(0x8D);
5295 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5296 ins_pipe(ialu_reg_reg_fat);
5297 %}
5298
5299 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5300 %{
5301 predicate(Universe::narrow_oop_shift() == 0);
5302 match(Set dst mem);
5303
5304 ins_cost(110); // XXX
5305 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5306 opcode(0x8D);
5307 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5308 ins_pipe(ialu_reg_reg_fat);
5309 %}
5310
5311 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5312 %{
5313 predicate(Universe::narrow_oop_shift() == 0);
5314 match(Set dst mem);
5315
5316 ins_cost(110);
5317 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5318 opcode(0x8D);
5319 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5320 ins_pipe(ialu_reg_reg_fat);
5321 %}
5322
5323 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5324 %{
5325 predicate(Universe::narrow_oop_shift() == 0);
5326 match(Set dst mem);
5327
5328 ins_cost(110);
5329 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5330 opcode(0x8D);
5331 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5332 ins_pipe(ialu_reg_reg_fat);
5333 %}
5334
5335 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5336 %{
5337 predicate(Universe::narrow_oop_shift() == 0);
5338 match(Set dst mem);
5339
5340 ins_cost(110);
5341 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5342 opcode(0x8D);
5343 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5344 ins_pipe(ialu_reg_reg_fat);
5345 %}
5346
5347 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5348 %{
5349 predicate(Universe::narrow_oop_shift() == 0);
5350 match(Set dst mem);
5351
5352 ins_cost(110);
5353 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5354 opcode(0x8D);
5355 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5356 ins_pipe(ialu_reg_reg_fat);
5357 %}
5358
5359 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5360 %{
5361 predicate(Universe::narrow_oop_shift() == 0);
5362 match(Set dst mem);
5363
5364 ins_cost(110);
5365 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5366 opcode(0x8D);
5367 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5368 ins_pipe(ialu_reg_reg_fat);
5369 %}
5370
5371 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5372 %{
5373 predicate(Universe::narrow_oop_shift() == 0);
5374 match(Set dst mem);
5375
5376 ins_cost(110);
5377 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5378 opcode(0x8D);
5379 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5380 ins_pipe(ialu_reg_reg_fat);
5381 %}
5382
5383 instruct loadConI(rRegI dst, immI src)
5384 %{
5385 match(Set dst src);
5386
5387 format %{ "movl $dst, $src\t# int" %}
5388 ins_encode(load_immI(dst, src));
5389 ins_pipe(ialu_reg_fat); // XXX
5390 %}
5391
5392 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5393 %{
5394 match(Set dst src);
5395 effect(KILL cr);
5396
5397 ins_cost(50);
5398 format %{ "xorl $dst, $dst\t# int" %}
5399 opcode(0x33); /* + rd */
5400 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5401 ins_pipe(ialu_reg);
5402 %}
5403
5404 instruct loadConL(rRegL dst, immL src)
5405 %{
5406 match(Set dst src);
5407
5408 ins_cost(150);
5409 format %{ "movq $dst, $src\t# long" %}
5410 ins_encode(load_immL(dst, src));
5411 ins_pipe(ialu_reg);
5412 %}
5413
5414 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5415 %{
5416 match(Set dst src);
5417 effect(KILL cr);
5418
5419 ins_cost(50);
5420 format %{ "xorl $dst, $dst\t# long" %}
5421 opcode(0x33); /* + rd */
5422 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5423 ins_pipe(ialu_reg); // XXX
5424 %}
5425
5426 instruct loadConUL32(rRegL dst, immUL32 src)
5427 %{
5428 match(Set dst src);
5429
5430 ins_cost(60);
5431 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5432 ins_encode(load_immUL32(dst, src));
5433 ins_pipe(ialu_reg);
5434 %}
5435
5436 instruct loadConL32(rRegL dst, immL32 src)
5437 %{
5438 match(Set dst src);
5439
5440 ins_cost(70);
5441 format %{ "movq $dst, $src\t# long (32-bit)" %}
5442 ins_encode(load_immL32(dst, src));
5443 ins_pipe(ialu_reg);
5444 %}
5445
5446 instruct loadConP(rRegP dst, immP con) %{
5447 match(Set dst con);
5448
5449 format %{ "movq $dst, $con\t# ptr" %}
5450 ins_encode(load_immP(dst, con));
5451 ins_pipe(ialu_reg_fat); // XXX
5452 %}
5453
5454 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5455 %{
5456 match(Set dst src);
5457 effect(KILL cr);
5458
5459 ins_cost(50);
5460 format %{ "xorl $dst, $dst\t# ptr" %}
5461 opcode(0x33); /* + rd */
5462 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5463 ins_pipe(ialu_reg);
5464 %}
5465
5466 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5467 %{
5468 match(Set dst src);
5469 effect(KILL cr);
5470
5471 ins_cost(60);
5472 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5473 ins_encode(load_immP31(dst, src));
5474 ins_pipe(ialu_reg);
5475 %}
5476
5477 instruct loadConF(regF dst, immF con) %{
5478 match(Set dst con);
5479 ins_cost(125);
5480 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5481 ins_encode %{
5482 __ movflt($dst$$XMMRegister, $constantaddress($con));
5483 %}
5484 ins_pipe(pipe_slow);
5485 %}
5486
5487 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5488 match(Set dst src);
5489 effect(KILL cr);
5490 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5491 ins_encode %{
5492 __ xorq($dst$$Register, $dst$$Register);
5493 %}
5494 ins_pipe(ialu_reg);
5495 %}
5496
5497 instruct loadConN(rRegN dst, immN src) %{
5498 match(Set dst src);
5499
5500 ins_cost(125);
5501 format %{ "movl $dst, $src\t# compressed ptr" %}
5502 ins_encode %{
5503 address con = (address)$src$$constant;
5504 if (con == NULL) {
5505 ShouldNotReachHere();
5506 } else {
5507 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5508 }
5509 %}
5510 ins_pipe(ialu_reg_fat); // XXX
5511 %}
5512
5513 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5514 match(Set dst src);
5515
5516 ins_cost(125);
5517 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5518 ins_encode %{
5519 address con = (address)$src$$constant;
5520 if (con == NULL) {
5521 ShouldNotReachHere();
5522 } else {
5523 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5524 }
5525 %}
5526 ins_pipe(ialu_reg_fat); // XXX
5527 %}
5528
5529 instruct loadConF0(regF dst, immF0 src)
5530 %{
5531 match(Set dst src);
5532 ins_cost(100);
5533
5534 format %{ "xorps $dst, $dst\t# float 0.0" %}
5535 ins_encode %{
5536 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5537 %}
5538 ins_pipe(pipe_slow);
5539 %}
5540
5541 // Use the same format since predicate() can not be used here.
5542 instruct loadConD(regD dst, immD con) %{
5543 match(Set dst con);
5544 ins_cost(125);
5545 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5546 ins_encode %{
5547 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5548 %}
5549 ins_pipe(pipe_slow);
5550 %}
5551
5552 instruct loadConD0(regD dst, immD0 src)
5553 %{
5554 match(Set dst src);
5555 ins_cost(100);
5556
5557 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5558 ins_encode %{
5559 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5560 %}
5561 ins_pipe(pipe_slow);
5562 %}
5563
5564 instruct loadSSI(rRegI dst, stackSlotI src)
5565 %{
5566 match(Set dst src);
5567
5568 ins_cost(125);
5569 format %{ "movl $dst, $src\t# int stk" %}
5570 opcode(0x8B);
5571 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5572 ins_pipe(ialu_reg_mem);
5573 %}
5574
5575 instruct loadSSL(rRegL dst, stackSlotL src)
5576 %{
5577 match(Set dst src);
5578
5579 ins_cost(125);
5580 format %{ "movq $dst, $src\t# long stk" %}
5581 opcode(0x8B);
5582 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5583 ins_pipe(ialu_reg_mem);
5584 %}
5585
5586 instruct loadSSP(rRegP dst, stackSlotP src)
5587 %{
5588 match(Set dst src);
5589
5590 ins_cost(125);
5591 format %{ "movq $dst, $src\t# ptr stk" %}
5592 opcode(0x8B);
5593 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5594 ins_pipe(ialu_reg_mem);
5595 %}
5596
5597 instruct loadSSF(regF dst, stackSlotF src)
5598 %{
5599 match(Set dst src);
5600
5601 ins_cost(125);
5602 format %{ "movss $dst, $src\t# float stk" %}
5603 ins_encode %{
5604 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5605 %}
5606 ins_pipe(pipe_slow); // XXX
5607 %}
5608
5609 // Use the same format since predicate() can not be used here.
5610 instruct loadSSD(regD dst, stackSlotD src)
5611 %{
5612 match(Set dst src);
5613
5614 ins_cost(125);
5615 format %{ "movsd $dst, $src\t# double stk" %}
5616 ins_encode %{
5617 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5618 %}
5619 ins_pipe(pipe_slow); // XXX
5620 %}
5621
5622 // Prefetch instructions for allocation.
5623 // Must be safe to execute with invalid address (cannot fault).
5624
5625 instruct prefetchAlloc( memory mem ) %{
5626 predicate(AllocatePrefetchInstr==3);
5627 match(PrefetchAllocation mem);
5628 ins_cost(125);
5629
5630 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5631 ins_encode %{
5632 __ prefetchw($mem$$Address);
5633 %}
5634 ins_pipe(ialu_mem);
5635 %}
5636
5637 instruct prefetchAllocNTA( memory mem ) %{
5638 predicate(AllocatePrefetchInstr==0);
5639 match(PrefetchAllocation mem);
5640 ins_cost(125);
5641
5642 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5643 ins_encode %{
5644 __ prefetchnta($mem$$Address);
5645 %}
5646 ins_pipe(ialu_mem);
5647 %}
5648
5649 instruct prefetchAllocT0( memory mem ) %{
5650 predicate(AllocatePrefetchInstr==1);
5651 match(PrefetchAllocation mem);
5652 ins_cost(125);
5653
5654 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5655 ins_encode %{
5656 __ prefetcht0($mem$$Address);
5657 %}
5658 ins_pipe(ialu_mem);
5659 %}
5660
5661 instruct prefetchAllocT2( memory mem ) %{
5662 predicate(AllocatePrefetchInstr==2);
5663 match(PrefetchAllocation mem);
5664 ins_cost(125);
5665
5666 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5667 ins_encode %{
5668 __ prefetcht2($mem$$Address);
5669 %}
5670 ins_pipe(ialu_mem);
5671 %}
5672
5673 //----------Store Instructions-------------------------------------------------
5674
5675 // Store Byte
5676 instruct storeB(memory mem, rRegI src)
5677 %{
5678 match(Set mem (StoreB mem src));
5679
5680 ins_cost(125); // XXX
5681 format %{ "movb $mem, $src\t# byte" %}
5682 opcode(0x88);
5683 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5684 ins_pipe(ialu_mem_reg);
5685 %}
5686
5687 // Store Char/Short
5688 instruct storeC(memory mem, rRegI src)
5689 %{
5690 match(Set mem (StoreC mem src));
5691
5692 ins_cost(125); // XXX
5693 format %{ "movw $mem, $src\t# char/short" %}
5694 opcode(0x89);
5695 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5696 ins_pipe(ialu_mem_reg);
5697 %}
5698
5699 // Store Integer
5700 instruct storeI(memory mem, rRegI src)
5701 %{
5702 match(Set mem (StoreI mem src));
5703
5704 ins_cost(125); // XXX
5705 format %{ "movl $mem, $src\t# int" %}
5706 opcode(0x89);
5707 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5708 ins_pipe(ialu_mem_reg);
5709 %}
5710
5711 // Store Long
5712 instruct storeL(memory mem, rRegL src)
5713 %{
5714 match(Set mem (StoreL mem src));
5715
5716 ins_cost(125); // XXX
5717 format %{ "movq $mem, $src\t# long" %}
5718 opcode(0x89);
5719 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5720 ins_pipe(ialu_mem_reg); // XXX
5721 %}
5722
5723 // Store Pointer
5724 instruct storeP(memory mem, any_RegP src)
5725 %{
5726 match(Set mem (StoreP mem src));
5727
5728 ins_cost(125); // XXX
5729 format %{ "movq $mem, $src\t# ptr" %}
5730 opcode(0x89);
5731 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5732 ins_pipe(ialu_mem_reg);
5733 %}
5734
5735 instruct storeImmP0(memory mem, immP0 zero)
5736 %{
5737 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5738 match(Set mem (StoreP mem zero));
5739
5740 ins_cost(125); // XXX
5741 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5742 ins_encode %{
5743 __ movq($mem$$Address, r12);
5744 %}
5745 ins_pipe(ialu_mem_reg);
5746 %}
5747
5748 // Store NULL Pointer, mark word, or other simple pointer constant.
5749 instruct storeImmP(memory mem, immP31 src)
5750 %{
5751 match(Set mem (StoreP mem src));
5752
5753 ins_cost(150); // XXX
5754 format %{ "movq $mem, $src\t# ptr" %}
5755 opcode(0xC7); /* C7 /0 */
5756 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5757 ins_pipe(ialu_mem_imm);
5758 %}
5759
5760 // Store Compressed Pointer
5761 instruct storeN(memory mem, rRegN src)
5762 %{
5763 match(Set mem (StoreN mem src));
5764
5765 ins_cost(125); // XXX
5766 format %{ "movl $mem, $src\t# compressed ptr" %}
5767 ins_encode %{
5768 __ movl($mem$$Address, $src$$Register);
5769 %}
5770 ins_pipe(ialu_mem_reg);
5771 %}
5772
5773 instruct storeNKlass(memory mem, rRegN src)
5774 %{
5775 match(Set mem (StoreNKlass mem src));
5776
5777 ins_cost(125); // XXX
5778 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5779 ins_encode %{
5780 __ movl($mem$$Address, $src$$Register);
5781 %}
5782 ins_pipe(ialu_mem_reg);
5783 %}
5784
5785 instruct storeImmN0(memory mem, immN0 zero)
5786 %{
5787 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5788 match(Set mem (StoreN mem zero));
5789
5790 ins_cost(125); // XXX
5791 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5792 ins_encode %{
5793 __ movl($mem$$Address, r12);
5794 %}
5795 ins_pipe(ialu_mem_reg);
5796 %}
5797
5798 instruct storeImmN(memory mem, immN src)
5799 %{
5800 match(Set mem (StoreN mem src));
5801
5802 ins_cost(150); // XXX
5803 format %{ "movl $mem, $src\t# compressed ptr" %}
5804 ins_encode %{
5805 address con = (address)$src$$constant;
5806 if (con == NULL) {
5807 __ movl($mem$$Address, (int32_t)0);
5808 } else {
5809 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5810 }
5811 %}
5812 ins_pipe(ialu_mem_imm);
5813 %}
5814
5815 instruct storeImmNKlass(memory mem, immNKlass src)
5816 %{
5817 match(Set mem (StoreNKlass mem src));
5818
5819 ins_cost(150); // XXX
5820 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5821 ins_encode %{
5822 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5823 %}
5824 ins_pipe(ialu_mem_imm);
5825 %}
5826
5827 // Store Integer Immediate
5828 instruct storeImmI0(memory mem, immI0 zero)
5829 %{
5830 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5831 match(Set mem (StoreI mem zero));
5832
5833 ins_cost(125); // XXX
5834 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5835 ins_encode %{
5836 __ movl($mem$$Address, r12);
5837 %}
5838 ins_pipe(ialu_mem_reg);
5839 %}
5840
5841 instruct storeImmI(memory mem, immI src)
5842 %{
5843 match(Set mem (StoreI mem src));
5844
5845 ins_cost(150);
5846 format %{ "movl $mem, $src\t# int" %}
5847 opcode(0xC7); /* C7 /0 */
5848 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5849 ins_pipe(ialu_mem_imm);
5850 %}
5851
5852 // Store Long Immediate
5853 instruct storeImmL0(memory mem, immL0 zero)
5854 %{
5855 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5856 match(Set mem (StoreL mem zero));
5857
5858 ins_cost(125); // XXX
5859 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5860 ins_encode %{
5861 __ movq($mem$$Address, r12);
5862 %}
5863 ins_pipe(ialu_mem_reg);
5864 %}
5865
5866 instruct storeImmL(memory mem, immL32 src)
5867 %{
5868 match(Set mem (StoreL mem src));
5869
5870 ins_cost(150);
5871 format %{ "movq $mem, $src\t# long" %}
5872 opcode(0xC7); /* C7 /0 */
5873 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5874 ins_pipe(ialu_mem_imm);
5875 %}
5876
5877 // Store Short/Char Immediate
5878 instruct storeImmC0(memory mem, immI0 zero)
5879 %{
5880 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5881 match(Set mem (StoreC mem zero));
5882
5883 ins_cost(125); // XXX
5884 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5885 ins_encode %{
5886 __ movw($mem$$Address, r12);
5887 %}
5888 ins_pipe(ialu_mem_reg);
5889 %}
5890
5891 instruct storeImmI16(memory mem, immI16 src)
5892 %{
5893 predicate(UseStoreImmI16);
5894 match(Set mem (StoreC mem src));
5895
5896 ins_cost(150);
5897 format %{ "movw $mem, $src\t# short/char" %}
5898 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5899 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5900 ins_pipe(ialu_mem_imm);
5901 %}
5902
5903 // Store Byte Immediate
5904 instruct storeImmB0(memory mem, immI0 zero)
5905 %{
5906 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5907 match(Set mem (StoreB mem zero));
5908
5909 ins_cost(125); // XXX
5910 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5911 ins_encode %{
5912 __ movb($mem$$Address, r12);
5913 %}
5914 ins_pipe(ialu_mem_reg);
5915 %}
5916
5917 instruct storeImmB(memory mem, immI8 src)
5918 %{
5919 match(Set mem (StoreB mem src));
5920
5921 ins_cost(150); // XXX
5922 format %{ "movb $mem, $src\t# byte" %}
5923 opcode(0xC6); /* C6 /0 */
5924 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5925 ins_pipe(ialu_mem_imm);
5926 %}
5927
5928 // Store CMS card-mark Immediate
5929 instruct storeImmCM0_reg(memory mem, immI0 zero)
5930 %{
5931 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5932 match(Set mem (StoreCM mem zero));
5933
5934 ins_cost(125); // XXX
5935 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5936 ins_encode %{
5937 __ movb($mem$$Address, r12);
5938 %}
5939 ins_pipe(ialu_mem_reg);
5940 %}
5941
5942 instruct storeImmCM0(memory mem, immI0 src)
5943 %{
5944 match(Set mem (StoreCM mem src));
5945
5946 ins_cost(150); // XXX
5947 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5948 opcode(0xC6); /* C6 /0 */
5949 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5950 ins_pipe(ialu_mem_imm);
5951 %}
5952
5953 // Store Float
5954 instruct storeF(memory mem, regF src)
5955 %{
5956 match(Set mem (StoreF mem src));
5957
5958 ins_cost(95); // XXX
5959 format %{ "movss $mem, $src\t# float" %}
5960 ins_encode %{
5961 __ movflt($mem$$Address, $src$$XMMRegister);
5962 %}
5963 ins_pipe(pipe_slow); // XXX
5964 %}
5965
5966 // Store immediate Float value (it is faster than store from XMM register)
5967 instruct storeF0(memory mem, immF0 zero)
5968 %{
5969 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5970 match(Set mem (StoreF mem zero));
5971
5972 ins_cost(25); // XXX
5973 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5974 ins_encode %{
5975 __ movl($mem$$Address, r12);
5976 %}
5977 ins_pipe(ialu_mem_reg);
5978 %}
5979
5980 instruct storeF_imm(memory mem, immF src)
5981 %{
5982 match(Set mem (StoreF mem src));
5983
5984 ins_cost(50);
5985 format %{ "movl $mem, $src\t# float" %}
5986 opcode(0xC7); /* C7 /0 */
5987 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5988 ins_pipe(ialu_mem_imm);
5989 %}
5990
5991 // Store Double
5992 instruct storeD(memory mem, regD src)
5993 %{
5994 match(Set mem (StoreD mem src));
5995
5996 ins_cost(95); // XXX
5997 format %{ "movsd $mem, $src\t# double" %}
5998 ins_encode %{
5999 __ movdbl($mem$$Address, $src$$XMMRegister);
6000 %}
6001 ins_pipe(pipe_slow); // XXX
6002 %}
6003
6004 // Store immediate double 0.0 (it is faster than store from XMM register)
6005 instruct storeD0_imm(memory mem, immD0 src)
6006 %{
6007 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6008 match(Set mem (StoreD mem src));
6009
6010 ins_cost(50);
6011 format %{ "movq $mem, $src\t# double 0." %}
6012 opcode(0xC7); /* C7 /0 */
6013 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6014 ins_pipe(ialu_mem_imm);
6015 %}
6016
6017 instruct storeD0(memory mem, immD0 zero)
6018 %{
6019 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6020 match(Set mem (StoreD mem zero));
6021
6022 ins_cost(25); // XXX
6023 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6024 ins_encode %{
6025 __ movq($mem$$Address, r12);
6026 %}
6027 ins_pipe(ialu_mem_reg);
6028 %}
6029
6030 instruct storeSSI(stackSlotI dst, rRegI src)
6031 %{
6032 match(Set dst src);
6033
6034 ins_cost(100);
6035 format %{ "movl $dst, $src\t# int stk" %}
6036 opcode(0x89);
6037 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6038 ins_pipe( ialu_mem_reg );
6039 %}
6040
6041 instruct storeSSL(stackSlotL dst, rRegL src)
6042 %{
6043 match(Set dst src);
6044
6045 ins_cost(100);
6046 format %{ "movq $dst, $src\t# long stk" %}
6047 opcode(0x89);
6048 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6049 ins_pipe(ialu_mem_reg);
6050 %}
6051
6052 instruct storeSSP(stackSlotP dst, rRegP src)
6053 %{
6054 match(Set dst src);
6055
6056 ins_cost(100);
6057 format %{ "movq $dst, $src\t# ptr stk" %}
6058 opcode(0x89);
6059 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6060 ins_pipe(ialu_mem_reg);
6061 %}
6062
6063 instruct storeSSF(stackSlotF dst, regF src)
6064 %{
6065 match(Set dst src);
6066
6067 ins_cost(95); // XXX
6068 format %{ "movss $dst, $src\t# float stk" %}
6069 ins_encode %{
6070 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6071 %}
6072 ins_pipe(pipe_slow); // XXX
6073 %}
6074
6075 instruct storeSSD(stackSlotD dst, regD src)
6076 %{
6077 match(Set dst src);
6078
6079 ins_cost(95); // XXX
6080 format %{ "movsd $dst, $src\t# double stk" %}
6081 ins_encode %{
6082 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6083 %}
6084 ins_pipe(pipe_slow); // XXX
6085 %}
6086
6087 //----------BSWAP Instructions-------------------------------------------------
6088 instruct bytes_reverse_int(rRegI dst) %{
6089 match(Set dst (ReverseBytesI dst));
6090
6091 format %{ "bswapl $dst" %}
6092 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6093 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6094 ins_pipe( ialu_reg );
6095 %}
6096
6097 instruct bytes_reverse_long(rRegL dst) %{
6098 match(Set dst (ReverseBytesL dst));
6099
6100 format %{ "bswapq $dst" %}
6101 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6102 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6103 ins_pipe( ialu_reg);
6104 %}
6105
6106 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6107 match(Set dst (ReverseBytesUS dst));
6108 effect(KILL cr);
6109
6110 format %{ "bswapl $dst\n\t"
6111 "shrl $dst,16\n\t" %}
6112 ins_encode %{
6113 __ bswapl($dst$$Register);
6114 __ shrl($dst$$Register, 16);
6115 %}
6116 ins_pipe( ialu_reg );
6117 %}
6118
6119 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6120 match(Set dst (ReverseBytesS dst));
6121 effect(KILL cr);
6122
6123 format %{ "bswapl $dst\n\t"
6124 "sar $dst,16\n\t" %}
6125 ins_encode %{
6126 __ bswapl($dst$$Register);
6127 __ sarl($dst$$Register, 16);
6128 %}
6129 ins_pipe( ialu_reg );
6130 %}
6131
6132 //---------- Zeros Count Instructions ------------------------------------------
6133
6134 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6135 predicate(UseCountLeadingZerosInstruction);
6136 match(Set dst (CountLeadingZerosI src));
6137 effect(KILL cr);
6138
6139 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6140 ins_encode %{
6141 __ lzcntl($dst$$Register, $src$$Register);
6142 %}
6143 ins_pipe(ialu_reg);
6144 %}
6145
6146 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6147 predicate(!UseCountLeadingZerosInstruction);
6148 match(Set dst (CountLeadingZerosI src));
6149 effect(KILL cr);
6150
6151 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6152 "jnz skip\n\t"
6153 "movl $dst, -1\n"
6154 "skip:\n\t"
6155 "negl $dst\n\t"
6156 "addl $dst, 31" %}
6157 ins_encode %{
6158 Register Rdst = $dst$$Register;
6159 Register Rsrc = $src$$Register;
6160 Label skip;
6161 __ bsrl(Rdst, Rsrc);
6162 __ jccb(Assembler::notZero, skip);
6163 __ movl(Rdst, -1);
6164 __ bind(skip);
6165 __ negl(Rdst);
6166 __ addl(Rdst, BitsPerInt - 1);
6167 %}
6168 ins_pipe(ialu_reg);
6169 %}
6170
6171 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6172 predicate(UseCountLeadingZerosInstruction);
6173 match(Set dst (CountLeadingZerosL src));
6174 effect(KILL cr);
6175
6176 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6177 ins_encode %{
6178 __ lzcntq($dst$$Register, $src$$Register);
6179 %}
6180 ins_pipe(ialu_reg);
6181 %}
6182
6183 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6184 predicate(!UseCountLeadingZerosInstruction);
6185 match(Set dst (CountLeadingZerosL src));
6186 effect(KILL cr);
6187
6188 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6189 "jnz skip\n\t"
6190 "movl $dst, -1\n"
6191 "skip:\n\t"
6192 "negl $dst\n\t"
6193 "addl $dst, 63" %}
6194 ins_encode %{
6195 Register Rdst = $dst$$Register;
6196 Register Rsrc = $src$$Register;
6197 Label skip;
6198 __ bsrq(Rdst, Rsrc);
6199 __ jccb(Assembler::notZero, skip);
6200 __ movl(Rdst, -1);
6201 __ bind(skip);
6202 __ negl(Rdst);
6203 __ addl(Rdst, BitsPerLong - 1);
6204 %}
6205 ins_pipe(ialu_reg);
6206 %}
6207
6208 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6209 predicate(UseCountTrailingZerosInstruction);
6210 match(Set dst (CountTrailingZerosI src));
6211 effect(KILL cr);
6212
6213 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6214 ins_encode %{
6215 __ tzcntl($dst$$Register, $src$$Register);
6216 %}
6217 ins_pipe(ialu_reg);
6218 %}
6219
6220 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6221 predicate(!UseCountTrailingZerosInstruction);
6222 match(Set dst (CountTrailingZerosI src));
6223 effect(KILL cr);
6224
6225 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6226 "jnz done\n\t"
6227 "movl $dst, 32\n"
6228 "done:" %}
6229 ins_encode %{
6230 Register Rdst = $dst$$Register;
6231 Label done;
6232 __ bsfl(Rdst, $src$$Register);
6233 __ jccb(Assembler::notZero, done);
6234 __ movl(Rdst, BitsPerInt);
6235 __ bind(done);
6236 %}
6237 ins_pipe(ialu_reg);
6238 %}
6239
6240 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6241 predicate(UseCountTrailingZerosInstruction);
6242 match(Set dst (CountTrailingZerosL src));
6243 effect(KILL cr);
6244
6245 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6246 ins_encode %{
6247 __ tzcntq($dst$$Register, $src$$Register);
6248 %}
6249 ins_pipe(ialu_reg);
6250 %}
6251
6252 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6253 predicate(!UseCountTrailingZerosInstruction);
6254 match(Set dst (CountTrailingZerosL src));
6255 effect(KILL cr);
6256
6257 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6258 "jnz done\n\t"
6259 "movl $dst, 64\n"
6260 "done:" %}
6261 ins_encode %{
6262 Register Rdst = $dst$$Register;
6263 Label done;
6264 __ bsfq(Rdst, $src$$Register);
6265 __ jccb(Assembler::notZero, done);
6266 __ movl(Rdst, BitsPerLong);
6267 __ bind(done);
6268 %}
6269 ins_pipe(ialu_reg);
6270 %}
6271
6272
6273 //---------- Population Count Instructions -------------------------------------
6274
6275 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6276 predicate(UsePopCountInstruction);
6277 match(Set dst (PopCountI src));
6278 effect(KILL cr);
6279
6280 format %{ "popcnt $dst, $src" %}
6281 ins_encode %{
6282 __ popcntl($dst$$Register, $src$$Register);
6283 %}
6284 ins_pipe(ialu_reg);
6285 %}
6286
6287 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6288 predicate(UsePopCountInstruction);
6289 match(Set dst (PopCountI (LoadI mem)));
6290 effect(KILL cr);
6291
6292 format %{ "popcnt $dst, $mem" %}
6293 ins_encode %{
6294 __ popcntl($dst$$Register, $mem$$Address);
6295 %}
6296 ins_pipe(ialu_reg);
6297 %}
6298
6299 // Note: Long.bitCount(long) returns an int.
6300 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6301 predicate(UsePopCountInstruction);
6302 match(Set dst (PopCountL src));
6303 effect(KILL cr);
6304
6305 format %{ "popcnt $dst, $src" %}
6306 ins_encode %{
6307 __ popcntq($dst$$Register, $src$$Register);
6308 %}
6309 ins_pipe(ialu_reg);
6310 %}
6311
6312 // Note: Long.bitCount(long) returns an int.
6313 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6314 predicate(UsePopCountInstruction);
6315 match(Set dst (PopCountL (LoadL mem)));
6316 effect(KILL cr);
6317
6318 format %{ "popcnt $dst, $mem" %}
6319 ins_encode %{
6320 __ popcntq($dst$$Register, $mem$$Address);
6321 %}
6322 ins_pipe(ialu_reg);
6323 %}
6324
6325
6326 //----------MemBar Instructions-----------------------------------------------
6327 // Memory barrier flavors
6328
6329 instruct membar_acquire()
6330 %{
6331 match(MemBarAcquire);
6332 match(LoadFence);
6333 ins_cost(0);
6334
6335 size(0);
6336 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6337 ins_encode();
6338 ins_pipe(empty);
6339 %}
6340
6341 instruct membar_acquire_lock()
6342 %{
6343 match(MemBarAcquireLock);
6344 ins_cost(0);
6345
6346 size(0);
6347 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6348 ins_encode();
6349 ins_pipe(empty);
6350 %}
6351
6352 instruct membar_release()
6353 %{
6354 match(MemBarRelease);
6355 match(StoreFence);
6356 ins_cost(0);
6357
6358 size(0);
6359 format %{ "MEMBAR-release ! (empty encoding)" %}
6360 ins_encode();
6361 ins_pipe(empty);
6362 %}
6363
6364 instruct membar_release_lock()
6365 %{
6366 match(MemBarReleaseLock);
6367 ins_cost(0);
6368
6369 size(0);
6370 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6371 ins_encode();
6372 ins_pipe(empty);
6373 %}
6374
6375 instruct membar_volatile(rFlagsReg cr) %{
6376 match(MemBarVolatile);
6377 effect(KILL cr);
6378 ins_cost(400);
6379
6380 format %{
6381 $$template
6382 if (os::is_MP()) {
6383 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6384 } else {
6385 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6386 }
6387 %}
6388 ins_encode %{
6389 __ membar(Assembler::StoreLoad);
6390 %}
6391 ins_pipe(pipe_slow);
6392 %}
6393
6394 instruct unnecessary_membar_volatile()
6395 %{
6396 match(MemBarVolatile);
6397 predicate(Matcher::post_store_load_barrier(n));
6398 ins_cost(0);
6399
6400 size(0);
6401 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6402 ins_encode();
6403 ins_pipe(empty);
6404 %}
6405
6406 instruct membar_storestore() %{
6407 match(MemBarStoreStore);
6408 ins_cost(0);
6409
6410 size(0);
6411 format %{ "MEMBAR-storestore (empty encoding)" %}
6412 ins_encode( );
6413 ins_pipe(empty);
6414 %}
6415
6416 //----------Move Instructions--------------------------------------------------
6417
6418 instruct castX2P(rRegP dst, rRegL src)
6419 %{
6420 match(Set dst (CastX2P src));
6421
6422 format %{ "movq $dst, $src\t# long->ptr" %}
6423 ins_encode %{
6424 if ($dst$$reg != $src$$reg) {
6425 __ movptr($dst$$Register, $src$$Register);
6426 }
6427 %}
6428 ins_pipe(ialu_reg_reg); // XXX
6429 %}
6430
6431 instruct castP2X(rRegL dst, rRegP src)
6432 %{
6433 match(Set dst (CastP2X src));
6434
6435 format %{ "movq $dst, $src\t# ptr -> long" %}
6436 ins_encode %{
6437 if ($dst$$reg != $src$$reg) {
6438 __ movptr($dst$$Register, $src$$Register);
6439 }
6440 %}
6441 ins_pipe(ialu_reg_reg); // XXX
6442 %}
6443
6444 // Convert oop into int for vectors alignment masking
6445 instruct convP2I(rRegI dst, rRegP src)
6446 %{
6447 match(Set dst (ConvL2I (CastP2X src)));
6448
6449 format %{ "movl $dst, $src\t# ptr -> int" %}
6450 ins_encode %{
6451 __ movl($dst$$Register, $src$$Register);
6452 %}
6453 ins_pipe(ialu_reg_reg); // XXX
6454 %}
6455
6456 // Convert compressed oop into int for vectors alignment masking
6457 // in case of 32bit oops (heap < 4Gb).
6458 instruct convN2I(rRegI dst, rRegN src)
6459 %{
6460 predicate(Universe::narrow_oop_shift() == 0);
6461 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6462
6463 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6464 ins_encode %{
6465 __ movl($dst$$Register, $src$$Register);
6466 %}
6467 ins_pipe(ialu_reg_reg); // XXX
6468 %}
6469
6470 // Convert oop pointer into compressed form
6471 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6472 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6473 match(Set dst (EncodeP src));
6474 effect(KILL cr);
6475 format %{ "encode_heap_oop $dst,$src" %}
6476 ins_encode %{
6477 Register s = $src$$Register;
6478 Register d = $dst$$Register;
6479 if (s != d) {
6480 __ movq(d, s);
6481 }
6482 __ encode_heap_oop(d);
6483 %}
6484 ins_pipe(ialu_reg_long);
6485 %}
6486
6487 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6488 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6489 match(Set dst (EncodeP src));
6490 effect(KILL cr);
6491 format %{ "encode_heap_oop_not_null $dst,$src" %}
6492 ins_encode %{
6493 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6494 %}
6495 ins_pipe(ialu_reg_long);
6496 %}
6497
6498 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6499 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6500 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6501 match(Set dst (DecodeN src));
6502 effect(KILL cr);
6503 format %{ "decode_heap_oop $dst,$src" %}
6504 ins_encode %{
6505 Register s = $src$$Register;
6506 Register d = $dst$$Register;
6507 if (s != d) {
6508 __ movq(d, s);
6509 }
6510 __ decode_heap_oop(d);
6511 %}
6512 ins_pipe(ialu_reg_long);
6513 %}
6514
6515 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6516 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6517 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6518 match(Set dst (DecodeN src));
6519 effect(KILL cr);
6520 format %{ "decode_heap_oop_not_null $dst,$src" %}
6521 ins_encode %{
6522 Register s = $src$$Register;
6523 Register d = $dst$$Register;
6524 if (s != d) {
6525 __ decode_heap_oop_not_null(d, s);
6526 } else {
6527 __ decode_heap_oop_not_null(d);
6528 }
6529 %}
6530 ins_pipe(ialu_reg_long);
6531 %}
6532
6533 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6534 match(Set dst (EncodePKlass src));
6535 effect(KILL cr);
6536 format %{ "encode_klass_not_null $dst,$src" %}
6537 ins_encode %{
6538 __ encode_klass_not_null($dst$$Register, $src$$Register);
6539 %}
6540 ins_pipe(ialu_reg_long);
6541 %}
6542
6543 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6544 match(Set dst (DecodeNKlass src));
6545 effect(KILL cr);
6546 format %{ "decode_klass_not_null $dst,$src" %}
6547 ins_encode %{
6548 Register s = $src$$Register;
6549 Register d = $dst$$Register;
6550 if (s != d) {
6551 __ decode_klass_not_null(d, s);
6552 } else {
6553 __ decode_klass_not_null(d);
6554 }
6555 %}
6556 ins_pipe(ialu_reg_long);
6557 %}
6558
6559
6560 //----------Conditional Move---------------------------------------------------
6561 // Jump
6562 // dummy instruction for generating temp registers
6563 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6564 match(Jump (LShiftL switch_val shift));
6565 ins_cost(350);
6566 predicate(false);
6567 effect(TEMP dest);
6568
6569 format %{ "leaq $dest, [$constantaddress]\n\t"
6570 "jmp [$dest + $switch_val << $shift]\n\t" %}
6571 ins_encode %{
6572 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6573 // to do that and the compiler is using that register as one it can allocate.
6574 // So we build it all by hand.
6575 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6576 // ArrayAddress dispatch(table, index);
6577 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6578 __ lea($dest$$Register, $constantaddress);
6579 __ jmp(dispatch);
6580 %}
6581 ins_pipe(pipe_jmp);
6582 %}
6583
6584 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6585 match(Jump (AddL (LShiftL switch_val shift) offset));
6586 ins_cost(350);
6587 effect(TEMP dest);
6588
6589 format %{ "leaq $dest, [$constantaddress]\n\t"
6590 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6591 ins_encode %{
6592 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6593 // to do that and the compiler is using that register as one it can allocate.
6594 // So we build it all by hand.
6595 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6596 // ArrayAddress dispatch(table, index);
6597 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6598 __ lea($dest$$Register, $constantaddress);
6599 __ jmp(dispatch);
6600 %}
6601 ins_pipe(pipe_jmp);
6602 %}
6603
6604 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6605 match(Jump switch_val);
6606 ins_cost(350);
6607 effect(TEMP dest);
6608
6609 format %{ "leaq $dest, [$constantaddress]\n\t"
6610 "jmp [$dest + $switch_val]\n\t" %}
6611 ins_encode %{
6612 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6613 // to do that and the compiler is using that register as one it can allocate.
6614 // So we build it all by hand.
6615 // Address index(noreg, switch_reg, Address::times_1);
6616 // ArrayAddress dispatch(table, index);
6617 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6618 __ lea($dest$$Register, $constantaddress);
6619 __ jmp(dispatch);
6620 %}
6621 ins_pipe(pipe_jmp);
6622 %}
6623
6624 // Conditional move
6625 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6626 %{
6627 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6628
6629 ins_cost(200); // XXX
6630 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6631 opcode(0x0F, 0x40);
6632 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6633 ins_pipe(pipe_cmov_reg);
6634 %}
6635
6636 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6637 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6638
6639 ins_cost(200); // XXX
6640 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6641 opcode(0x0F, 0x40);
6642 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6643 ins_pipe(pipe_cmov_reg);
6644 %}
6645
6646 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6647 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6648 ins_cost(200);
6649 expand %{
6650 cmovI_regU(cop, cr, dst, src);
6651 %}
6652 %}
6653
6654 // Conditional move
6655 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6656 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6657
6658 ins_cost(250); // XXX
6659 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6660 opcode(0x0F, 0x40);
6661 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6662 ins_pipe(pipe_cmov_mem);
6663 %}
6664
6665 // Conditional move
6666 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6667 %{
6668 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6669
6670 ins_cost(250); // XXX
6671 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6672 opcode(0x0F, 0x40);
6673 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6674 ins_pipe(pipe_cmov_mem);
6675 %}
6676
6677 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6678 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6679 ins_cost(250);
6680 expand %{
6681 cmovI_memU(cop, cr, dst, src);
6682 %}
6683 %}
6684
6685 // Conditional move
6686 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6687 %{
6688 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6689
6690 ins_cost(200); // XXX
6691 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6692 opcode(0x0F, 0x40);
6693 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6694 ins_pipe(pipe_cmov_reg);
6695 %}
6696
6697 // Conditional move
6698 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6699 %{
6700 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6701
6702 ins_cost(200); // XXX
6703 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6704 opcode(0x0F, 0x40);
6705 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6706 ins_pipe(pipe_cmov_reg);
6707 %}
6708
6709 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6710 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6711 ins_cost(200);
6712 expand %{
6713 cmovN_regU(cop, cr, dst, src);
6714 %}
6715 %}
6716
6717 // Conditional move
6718 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6719 %{
6720 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6721
6722 ins_cost(200); // XXX
6723 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6724 opcode(0x0F, 0x40);
6725 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6726 ins_pipe(pipe_cmov_reg); // XXX
6727 %}
6728
6729 // Conditional move
6730 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6731 %{
6732 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6733
6734 ins_cost(200); // XXX
6735 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6736 opcode(0x0F, 0x40);
6737 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6738 ins_pipe(pipe_cmov_reg); // XXX
6739 %}
6740
6741 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6742 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6743 ins_cost(200);
6744 expand %{
6745 cmovP_regU(cop, cr, dst, src);
6746 %}
6747 %}
6748
6749 // DISABLED: Requires the ADLC to emit a bottom_type call that
6750 // correctly meets the two pointer arguments; one is an incoming
6751 // register but the other is a memory operand. ALSO appears to
6752 // be buggy with implicit null checks.
6753 //
6754 //// Conditional move
6755 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6756 //%{
6757 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6758 // ins_cost(250);
6759 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6760 // opcode(0x0F,0x40);
6761 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6762 // ins_pipe( pipe_cmov_mem );
6763 //%}
6764 //
6765 //// Conditional move
6766 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6767 //%{
6768 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6769 // ins_cost(250);
6770 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6771 // opcode(0x0F,0x40);
6772 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6773 // ins_pipe( pipe_cmov_mem );
6774 //%}
6775
6776 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6777 %{
6778 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6779
6780 ins_cost(200); // XXX
6781 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6782 opcode(0x0F, 0x40);
6783 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6784 ins_pipe(pipe_cmov_reg); // XXX
6785 %}
6786
6787 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6788 %{
6789 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6790
6791 ins_cost(200); // XXX
6792 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6793 opcode(0x0F, 0x40);
6794 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6795 ins_pipe(pipe_cmov_mem); // XXX
6796 %}
6797
6798 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6799 %{
6800 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6801
6802 ins_cost(200); // XXX
6803 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6804 opcode(0x0F, 0x40);
6805 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6806 ins_pipe(pipe_cmov_reg); // XXX
6807 %}
6808
6809 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6810 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6811 ins_cost(200);
6812 expand %{
6813 cmovL_regU(cop, cr, dst, src);
6814 %}
6815 %}
6816
6817 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6818 %{
6819 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6820
6821 ins_cost(200); // XXX
6822 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6823 opcode(0x0F, 0x40);
6824 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6825 ins_pipe(pipe_cmov_mem); // XXX
6826 %}
6827
6828 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6829 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6830 ins_cost(200);
6831 expand %{
6832 cmovL_memU(cop, cr, dst, src);
6833 %}
6834 %}
6835
6836 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6837 %{
6838 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6839
6840 ins_cost(200); // XXX
6841 format %{ "jn$cop skip\t# signed cmove float\n\t"
6842 "movss $dst, $src\n"
6843 "skip:" %}
6844 ins_encode %{
6845 Label Lskip;
6846 // Invert sense of branch from sense of CMOV
6847 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6848 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6849 __ bind(Lskip);
6850 %}
6851 ins_pipe(pipe_slow);
6852 %}
6853
6854 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6855 // %{
6856 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6857
6858 // ins_cost(200); // XXX
6859 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6860 // "movss $dst, $src\n"
6861 // "skip:" %}
6862 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6863 // ins_pipe(pipe_slow);
6864 // %}
6865
6866 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6867 %{
6868 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6869
6870 ins_cost(200); // XXX
6871 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6872 "movss $dst, $src\n"
6873 "skip:" %}
6874 ins_encode %{
6875 Label Lskip;
6876 // Invert sense of branch from sense of CMOV
6877 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6878 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6879 __ bind(Lskip);
6880 %}
6881 ins_pipe(pipe_slow);
6882 %}
6883
6884 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6885 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6886 ins_cost(200);
6887 expand %{
6888 cmovF_regU(cop, cr, dst, src);
6889 %}
6890 %}
6891
6892 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6893 %{
6894 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6895
6896 ins_cost(200); // XXX
6897 format %{ "jn$cop skip\t# signed cmove double\n\t"
6898 "movsd $dst, $src\n"
6899 "skip:" %}
6900 ins_encode %{
6901 Label Lskip;
6902 // Invert sense of branch from sense of CMOV
6903 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6904 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6905 __ bind(Lskip);
6906 %}
6907 ins_pipe(pipe_slow);
6908 %}
6909
6910 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6911 %{
6912 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6913
6914 ins_cost(200); // XXX
6915 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6916 "movsd $dst, $src\n"
6917 "skip:" %}
6918 ins_encode %{
6919 Label Lskip;
6920 // Invert sense of branch from sense of CMOV
6921 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6922 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6923 __ bind(Lskip);
6924 %}
6925 ins_pipe(pipe_slow);
6926 %}
6927
6928 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6929 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6930 ins_cost(200);
6931 expand %{
6932 cmovD_regU(cop, cr, dst, src);
6933 %}
6934 %}
6935
6936 //----------Arithmetic Instructions--------------------------------------------
6937 //----------Addition Instructions----------------------------------------------
6938
6939 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6940 %{
6941 match(Set dst (AddI dst src));
6942 effect(KILL cr);
6943
6944 format %{ "addl $dst, $src\t# int" %}
6945 opcode(0x03);
6946 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6947 ins_pipe(ialu_reg_reg);
6948 %}
6949
6950 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6951 %{
6952 match(Set dst (AddI dst src));
6953 effect(KILL cr);
6954
6955 format %{ "addl $dst, $src\t# int" %}
6956 opcode(0x81, 0x00); /* /0 id */
6957 ins_encode(OpcSErm(dst, src), Con8or32(src));
6958 ins_pipe( ialu_reg );
6959 %}
6960
6961 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6962 %{
6963 match(Set dst (AddI dst (LoadI src)));
6964 effect(KILL cr);
6965
6966 ins_cost(125); // XXX
6967 format %{ "addl $dst, $src\t# int" %}
6968 opcode(0x03);
6969 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6970 ins_pipe(ialu_reg_mem);
6971 %}
6972
6973 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6974 %{
6975 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6976 effect(KILL cr);
6977
6978 ins_cost(150); // XXX
6979 format %{ "addl $dst, $src\t# int" %}
6980 opcode(0x01); /* Opcode 01 /r */
6981 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6982 ins_pipe(ialu_mem_reg);
6983 %}
6984
6985 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6986 %{
6987 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6988 effect(KILL cr);
6989
6990 ins_cost(125); // XXX
6991 format %{ "addl $dst, $src\t# int" %}
6992 opcode(0x81); /* Opcode 81 /0 id */
6993 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6994 ins_pipe(ialu_mem_imm);
6995 %}
6996
6997 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6998 %{
6999 predicate(UseIncDec);
7000 match(Set dst (AddI dst src));
7001 effect(KILL cr);
7002
7003 format %{ "incl $dst\t# int" %}
7004 opcode(0xFF, 0x00); // FF /0
7005 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7006 ins_pipe(ialu_reg);
7007 %}
7008
7009 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7010 %{
7011 predicate(UseIncDec);
7012 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7013 effect(KILL cr);
7014
7015 ins_cost(125); // XXX
7016 format %{ "incl $dst\t# int" %}
7017 opcode(0xFF); /* Opcode FF /0 */
7018 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7019 ins_pipe(ialu_mem_imm);
7020 %}
7021
7022 // XXX why does that use AddI
7023 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7024 %{
7025 predicate(UseIncDec);
7026 match(Set dst (AddI dst src));
7027 effect(KILL cr);
7028
7029 format %{ "decl $dst\t# int" %}
7030 opcode(0xFF, 0x01); // FF /1
7031 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7032 ins_pipe(ialu_reg);
7033 %}
7034
7035 // XXX why does that use AddI
7036 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7037 %{
7038 predicate(UseIncDec);
7039 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7040 effect(KILL cr);
7041
7042 ins_cost(125); // XXX
7043 format %{ "decl $dst\t# int" %}
7044 opcode(0xFF); /* Opcode FF /1 */
7045 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7046 ins_pipe(ialu_mem_imm);
7047 %}
7048
7049 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7050 %{
7051 match(Set dst (AddI src0 src1));
7052
7053 ins_cost(110);
7054 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7055 opcode(0x8D); /* 0x8D /r */
7056 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7057 ins_pipe(ialu_reg_reg);
7058 %}
7059
7060 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7061 %{
7062 match(Set dst (AddL dst src));
7063 effect(KILL cr);
7064
7065 format %{ "addq $dst, $src\t# long" %}
7066 opcode(0x03);
7067 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7068 ins_pipe(ialu_reg_reg);
7069 %}
7070
7071 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7072 %{
7073 match(Set dst (AddL dst src));
7074 effect(KILL cr);
7075
7076 format %{ "addq $dst, $src\t# long" %}
7077 opcode(0x81, 0x00); /* /0 id */
7078 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7079 ins_pipe( ialu_reg );
7080 %}
7081
7082 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7083 %{
7084 match(Set dst (AddL dst (LoadL src)));
7085 effect(KILL cr);
7086
7087 ins_cost(125); // XXX
7088 format %{ "addq $dst, $src\t# long" %}
7089 opcode(0x03);
7090 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7091 ins_pipe(ialu_reg_mem);
7092 %}
7093
7094 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7095 %{
7096 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7097 effect(KILL cr);
7098
7099 ins_cost(150); // XXX
7100 format %{ "addq $dst, $src\t# long" %}
7101 opcode(0x01); /* Opcode 01 /r */
7102 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7103 ins_pipe(ialu_mem_reg);
7104 %}
7105
7106 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7107 %{
7108 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7109 effect(KILL cr);
7110
7111 ins_cost(125); // XXX
7112 format %{ "addq $dst, $src\t# long" %}
7113 opcode(0x81); /* Opcode 81 /0 id */
7114 ins_encode(REX_mem_wide(dst),
7115 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7116 ins_pipe(ialu_mem_imm);
7117 %}
7118
7119 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7120 %{
7121 predicate(UseIncDec);
7122 match(Set dst (AddL dst src));
7123 effect(KILL cr);
7124
7125 format %{ "incq $dst\t# long" %}
7126 opcode(0xFF, 0x00); // FF /0
7127 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7128 ins_pipe(ialu_reg);
7129 %}
7130
7131 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7132 %{
7133 predicate(UseIncDec);
7134 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7135 effect(KILL cr);
7136
7137 ins_cost(125); // XXX
7138 format %{ "incq $dst\t# long" %}
7139 opcode(0xFF); /* Opcode FF /0 */
7140 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7141 ins_pipe(ialu_mem_imm);
7142 %}
7143
7144 // XXX why does that use AddL
7145 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7146 %{
7147 predicate(UseIncDec);
7148 match(Set dst (AddL dst src));
7149 effect(KILL cr);
7150
7151 format %{ "decq $dst\t# long" %}
7152 opcode(0xFF, 0x01); // FF /1
7153 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7154 ins_pipe(ialu_reg);
7155 %}
7156
7157 // XXX why does that use AddL
7158 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7159 %{
7160 predicate(UseIncDec);
7161 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7162 effect(KILL cr);
7163
7164 ins_cost(125); // XXX
7165 format %{ "decq $dst\t# long" %}
7166 opcode(0xFF); /* Opcode FF /1 */
7167 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7168 ins_pipe(ialu_mem_imm);
7169 %}
7170
7171 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7172 %{
7173 match(Set dst (AddL src0 src1));
7174
7175 ins_cost(110);
7176 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7177 opcode(0x8D); /* 0x8D /r */
7178 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7179 ins_pipe(ialu_reg_reg);
7180 %}
7181
7182 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7183 %{
7184 match(Set dst (AddP dst src));
7185 effect(KILL cr);
7186
7187 format %{ "addq $dst, $src\t# ptr" %}
7188 opcode(0x03);
7189 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7190 ins_pipe(ialu_reg_reg);
7191 %}
7192
7193 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7194 %{
7195 match(Set dst (AddP dst src));
7196 effect(KILL cr);
7197
7198 format %{ "addq $dst, $src\t# ptr" %}
7199 opcode(0x81, 0x00); /* /0 id */
7200 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7201 ins_pipe( ialu_reg );
7202 %}
7203
7204 // XXX addP mem ops ????
7205
7206 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7207 %{
7208 match(Set dst (AddP src0 src1));
7209
7210 ins_cost(110);
7211 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7212 opcode(0x8D); /* 0x8D /r */
7213 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7214 ins_pipe(ialu_reg_reg);
7215 %}
7216
7217 instruct checkCastPP(rRegP dst)
7218 %{
7219 match(Set dst (CheckCastPP dst));
7220
7221 size(0);
7222 format %{ "# checkcastPP of $dst" %}
7223 ins_encode(/* empty encoding */);
7224 ins_pipe(empty);
7225 %}
7226
7227 instruct castPP(rRegP dst)
7228 %{
7229 match(Set dst (CastPP dst));
7230
7231 size(0);
7232 format %{ "# castPP of $dst" %}
7233 ins_encode(/* empty encoding */);
7234 ins_pipe(empty);
7235 %}
7236
7237 instruct castII(rRegI dst)
7238 %{
7239 match(Set dst (CastII dst));
7240
7241 size(0);
7242 format %{ "# castII of $dst" %}
7243 ins_encode(/* empty encoding */);
7244 ins_cost(0);
7245 ins_pipe(empty);
7246 %}
7247
7248 // LoadP-locked same as a regular LoadP when used with compare-swap
7249 instruct loadPLocked(rRegP dst, memory mem)
7250 %{
7251 match(Set dst (LoadPLocked mem));
7252
7253 ins_cost(125); // XXX
7254 format %{ "movq $dst, $mem\t# ptr locked" %}
7255 opcode(0x8B);
7256 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7257 ins_pipe(ialu_reg_mem); // XXX
7258 %}
7259
7260 // Conditional-store of the updated heap-top.
7261 // Used during allocation of the shared heap.
7262 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7263
7264 instruct storePConditional(memory heap_top_ptr,
7265 rax_RegP oldval, rRegP newval,
7266 rFlagsReg cr)
7267 %{
7268 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7269
7270 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7271 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7272 opcode(0x0F, 0xB1);
7273 ins_encode(lock_prefix,
7274 REX_reg_mem_wide(newval, heap_top_ptr),
7275 OpcP, OpcS,
7276 reg_mem(newval, heap_top_ptr));
7277 ins_pipe(pipe_cmpxchg);
7278 %}
7279
7280 // Conditional-store of an int value.
7281 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7282 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7283 %{
7284 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7285 effect(KILL oldval);
7286
7287 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7288 opcode(0x0F, 0xB1);
7289 ins_encode(lock_prefix,
7290 REX_reg_mem(newval, mem),
7291 OpcP, OpcS,
7292 reg_mem(newval, mem));
7293 ins_pipe(pipe_cmpxchg);
7294 %}
7295
7296 // Conditional-store of a long value.
7297 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7298 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7299 %{
7300 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7301 effect(KILL oldval);
7302
7303 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7304 opcode(0x0F, 0xB1);
7305 ins_encode(lock_prefix,
7306 REX_reg_mem_wide(newval, mem),
7307 OpcP, OpcS,
7308 reg_mem(newval, mem));
7309 ins_pipe(pipe_cmpxchg);
7310 %}
7311
7312
7313 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7314 instruct compareAndSwapP(rRegI res,
7315 memory mem_ptr,
7316 rax_RegP oldval, rRegP newval,
7317 rFlagsReg cr)
7318 %{
7319 predicate(VM_Version::supports_cx8());
7320 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7321 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7322 effect(KILL cr, KILL oldval);
7323
7324 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7325 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7326 "sete $res\n\t"
7327 "movzbl $res, $res" %}
7328 opcode(0x0F, 0xB1);
7329 ins_encode(lock_prefix,
7330 REX_reg_mem_wide(newval, mem_ptr),
7331 OpcP, OpcS,
7332 reg_mem(newval, mem_ptr),
7333 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7334 REX_reg_breg(res, res), // movzbl
7335 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7336 ins_pipe( pipe_cmpxchg );
7337 %}
7338
7339 instruct compareAndSwapL(rRegI res,
7340 memory mem_ptr,
7341 rax_RegL oldval, rRegL newval,
7342 rFlagsReg cr)
7343 %{
7344 predicate(VM_Version::supports_cx8());
7345 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7346 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7347 effect(KILL cr, KILL oldval);
7348
7349 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7350 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7351 "sete $res\n\t"
7352 "movzbl $res, $res" %}
7353 opcode(0x0F, 0xB1);
7354 ins_encode(lock_prefix,
7355 REX_reg_mem_wide(newval, mem_ptr),
7356 OpcP, OpcS,
7357 reg_mem(newval, mem_ptr),
7358 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7359 REX_reg_breg(res, res), // movzbl
7360 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7361 ins_pipe( pipe_cmpxchg );
7362 %}
7363
7364 instruct compareAndSwapI(rRegI res,
7365 memory mem_ptr,
7366 rax_RegI oldval, rRegI newval,
7367 rFlagsReg cr)
7368 %{
7369 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7370 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7371 effect(KILL cr, KILL oldval);
7372
7373 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7374 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7375 "sete $res\n\t"
7376 "movzbl $res, $res" %}
7377 opcode(0x0F, 0xB1);
7378 ins_encode(lock_prefix,
7379 REX_reg_mem(newval, mem_ptr),
7380 OpcP, OpcS,
7381 reg_mem(newval, mem_ptr),
7382 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7383 REX_reg_breg(res, res), // movzbl
7384 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7385 ins_pipe( pipe_cmpxchg );
7386 %}
7387
7388 instruct compareAndSwapB(rRegI res,
7389 memory mem_ptr,
7390 rax_RegI oldval, rRegI newval,
7391 rFlagsReg cr)
7392 %{
7393 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7394 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7395 effect(KILL cr, KILL oldval);
7396
7397 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7398 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7399 "sete $res\n\t"
7400 "movzbl $res, $res" %}
7401 opcode(0x0F, 0xB0);
7402 ins_encode(lock_prefix,
7403 REX_breg_mem(newval, mem_ptr),
7404 OpcP, OpcS,
7405 reg_mem(newval, mem_ptr),
7406 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7407 REX_reg_breg(res, res), // movzbl
7408 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7409 ins_pipe( pipe_cmpxchg );
7410 %}
7411
7412 instruct compareAndSwapS(rRegI res,
7413 memory mem_ptr,
7414 rax_RegI oldval, rRegI newval,
7415 rFlagsReg cr)
7416 %{
7417 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7418 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7419 effect(KILL cr, KILL oldval);
7420
7421 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7422 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7423 "sete $res\n\t"
7424 "movzbl $res, $res" %}
7425 opcode(0x0F, 0xB1);
7426 ins_encode(lock_prefix,
7427 SizePrefix,
7428 REX_reg_mem(newval, mem_ptr),
7429 OpcP, OpcS,
7430 reg_mem(newval, mem_ptr),
7431 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7432 REX_reg_breg(res, res), // movzbl
7433 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7434 ins_pipe( pipe_cmpxchg );
7435 %}
7436
7437 instruct compareAndSwapN(rRegI res,
7438 memory mem_ptr,
7439 rax_RegN oldval, rRegN newval,
7440 rFlagsReg cr) %{
7441 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7442 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7443 effect(KILL cr, KILL oldval);
7444
7445 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7446 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7447 "sete $res\n\t"
7448 "movzbl $res, $res" %}
7449 opcode(0x0F, 0xB1);
7450 ins_encode(lock_prefix,
7451 REX_reg_mem(newval, mem_ptr),
7452 OpcP, OpcS,
7453 reg_mem(newval, mem_ptr),
7454 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7455 REX_reg_breg(res, res), // movzbl
7456 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7457 ins_pipe( pipe_cmpxchg );
7458 %}
7459
7460 instruct compareAndExchangeB(
7461 memory mem_ptr,
7462 rax_RegI oldval, rRegI newval,
7463 rFlagsReg cr)
7464 %{
7465 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7466 effect(KILL cr);
7467
7468 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7469 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7470 opcode(0x0F, 0xB0);
7471 ins_encode(lock_prefix,
7472 REX_breg_mem(newval, mem_ptr),
7473 OpcP, OpcS,
7474 reg_mem(newval, mem_ptr) // lock cmpxchg
7475 );
7476 ins_pipe( pipe_cmpxchg );
7477 %}
7478
7479 instruct compareAndExchangeS(
7480 memory mem_ptr,
7481 rax_RegI oldval, rRegI newval,
7482 rFlagsReg cr)
7483 %{
7484 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7485 effect(KILL cr);
7486
7487 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7488 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7489 opcode(0x0F, 0xB1);
7490 ins_encode(lock_prefix,
7491 SizePrefix,
7492 REX_reg_mem(newval, mem_ptr),
7493 OpcP, OpcS,
7494 reg_mem(newval, mem_ptr) // lock cmpxchg
7495 );
7496 ins_pipe( pipe_cmpxchg );
7497 %}
7498
7499 instruct compareAndExchangeI(
7500 memory mem_ptr,
7501 rax_RegI oldval, rRegI newval,
7502 rFlagsReg cr)
7503 %{
7504 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7505 effect(KILL cr);
7506
7507 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7508 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7509 opcode(0x0F, 0xB1);
7510 ins_encode(lock_prefix,
7511 REX_reg_mem(newval, mem_ptr),
7512 OpcP, OpcS,
7513 reg_mem(newval, mem_ptr) // lock cmpxchg
7514 );
7515 ins_pipe( pipe_cmpxchg );
7516 %}
7517
7518 instruct compareAndExchangeL(
7519 memory mem_ptr,
7520 rax_RegL oldval, rRegL newval,
7521 rFlagsReg cr)
7522 %{
7523 predicate(VM_Version::supports_cx8());
7524 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7525 effect(KILL cr);
7526
7527 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7528 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7529 opcode(0x0F, 0xB1);
7530 ins_encode(lock_prefix,
7531 REX_reg_mem_wide(newval, mem_ptr),
7532 OpcP, OpcS,
7533 reg_mem(newval, mem_ptr) // lock cmpxchg
7534 );
7535 ins_pipe( pipe_cmpxchg );
7536 %}
7537
7538 instruct compareAndExchangeN(
7539 memory mem_ptr,
7540 rax_RegN oldval, rRegN newval,
7541 rFlagsReg cr) %{
7542 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7543 effect(KILL cr);
7544
7545 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7546 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7547 opcode(0x0F, 0xB1);
7548 ins_encode(lock_prefix,
7549 REX_reg_mem(newval, mem_ptr),
7550 OpcP, OpcS,
7551 reg_mem(newval, mem_ptr) // lock cmpxchg
7552 );
7553 ins_pipe( pipe_cmpxchg );
7554 %}
7555
7556 instruct compareAndExchangeP(
7557 memory mem_ptr,
7558 rax_RegP oldval, rRegP newval,
7559 rFlagsReg cr)
7560 %{
7561 predicate(VM_Version::supports_cx8());
7562 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7563 effect(KILL cr);
7564
7565 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7566 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7567 opcode(0x0F, 0xB1);
7568 ins_encode(lock_prefix,
7569 REX_reg_mem_wide(newval, mem_ptr),
7570 OpcP, OpcS,
7571 reg_mem(newval, mem_ptr) // lock cmpxchg
7572 );
7573 ins_pipe( pipe_cmpxchg );
7574 %}
7575
7576 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7577 predicate(n->as_LoadStore()->result_not_used());
7578 match(Set dummy (GetAndAddB mem add));
7579 effect(KILL cr);
7580 format %{ "ADDB [$mem],$add" %}
7581 ins_encode %{
7582 if (os::is_MP()) { __ lock(); }
7583 __ addb($mem$$Address, $add$$constant);
7584 %}
7585 ins_pipe( pipe_cmpxchg );
7586 %}
7587
7588 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7589 match(Set newval (GetAndAddB mem newval));
7590 effect(KILL cr);
7591 format %{ "XADDB [$mem],$newval" %}
7592 ins_encode %{
7593 if (os::is_MP()) { __ lock(); }
7594 __ xaddb($mem$$Address, $newval$$Register);
7595 %}
7596 ins_pipe( pipe_cmpxchg );
7597 %}
7598
7599 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7600 predicate(n->as_LoadStore()->result_not_used());
7601 match(Set dummy (GetAndAddS mem add));
7602 effect(KILL cr);
7603 format %{ "ADDW [$mem],$add" %}
7604 ins_encode %{
7605 if (os::is_MP()) { __ lock(); }
7606 __ addw($mem$$Address, $add$$constant);
7607 %}
7608 ins_pipe( pipe_cmpxchg );
7609 %}
7610
7611 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7612 match(Set newval (GetAndAddS mem newval));
7613 effect(KILL cr);
7614 format %{ "XADDW [$mem],$newval" %}
7615 ins_encode %{
7616 if (os::is_MP()) { __ lock(); }
7617 __ xaddw($mem$$Address, $newval$$Register);
7618 %}
7619 ins_pipe( pipe_cmpxchg );
7620 %}
7621
7622 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7623 predicate(n->as_LoadStore()->result_not_used());
7624 match(Set dummy (GetAndAddI mem add));
7625 effect(KILL cr);
7626 format %{ "ADDL [$mem],$add" %}
7627 ins_encode %{
7628 if (os::is_MP()) { __ lock(); }
7629 __ addl($mem$$Address, $add$$constant);
7630 %}
7631 ins_pipe( pipe_cmpxchg );
7632 %}
7633
7634 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7635 match(Set newval (GetAndAddI mem newval));
7636 effect(KILL cr);
7637 format %{ "XADDL [$mem],$newval" %}
7638 ins_encode %{
7639 if (os::is_MP()) { __ lock(); }
7640 __ xaddl($mem$$Address, $newval$$Register);
7641 %}
7642 ins_pipe( pipe_cmpxchg );
7643 %}
7644
7645 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7646 predicate(n->as_LoadStore()->result_not_used());
7647 match(Set dummy (GetAndAddL mem add));
7648 effect(KILL cr);
7649 format %{ "ADDQ [$mem],$add" %}
7650 ins_encode %{
7651 if (os::is_MP()) { __ lock(); }
7652 __ addq($mem$$Address, $add$$constant);
7653 %}
7654 ins_pipe( pipe_cmpxchg );
7655 %}
7656
7657 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7658 match(Set newval (GetAndAddL mem newval));
7659 effect(KILL cr);
7660 format %{ "XADDQ [$mem],$newval" %}
7661 ins_encode %{
7662 if (os::is_MP()) { __ lock(); }
7663 __ xaddq($mem$$Address, $newval$$Register);
7664 %}
7665 ins_pipe( pipe_cmpxchg );
7666 %}
7667
7668 instruct xchgB( memory mem, rRegI newval) %{
7669 match(Set newval (GetAndSetB mem newval));
7670 format %{ "XCHGB $newval,[$mem]" %}
7671 ins_encode %{
7672 __ xchgb($newval$$Register, $mem$$Address);
7673 %}
7674 ins_pipe( pipe_cmpxchg );
7675 %}
7676
7677 instruct xchgS( memory mem, rRegI newval) %{
7678 match(Set newval (GetAndSetS mem newval));
7679 format %{ "XCHGW $newval,[$mem]" %}
7680 ins_encode %{
7681 __ xchgw($newval$$Register, $mem$$Address);
7682 %}
7683 ins_pipe( pipe_cmpxchg );
7684 %}
7685
7686 instruct xchgI( memory mem, rRegI newval) %{
7687 match(Set newval (GetAndSetI mem newval));
7688 format %{ "XCHGL $newval,[$mem]" %}
7689 ins_encode %{
7690 __ xchgl($newval$$Register, $mem$$Address);
7691 %}
7692 ins_pipe( pipe_cmpxchg );
7693 %}
7694
7695 instruct xchgL( memory mem, rRegL newval) %{
7696 match(Set newval (GetAndSetL mem newval));
7697 format %{ "XCHGL $newval,[$mem]" %}
7698 ins_encode %{
7699 __ xchgq($newval$$Register, $mem$$Address);
7700 %}
7701 ins_pipe( pipe_cmpxchg );
7702 %}
7703
7704 instruct xchgP( memory mem, rRegP newval) %{
7705 match(Set newval (GetAndSetP mem newval));
7706 format %{ "XCHGQ $newval,[$mem]" %}
7707 ins_encode %{
7708 __ xchgq($newval$$Register, $mem$$Address);
7709 %}
7710 ins_pipe( pipe_cmpxchg );
7711 %}
7712
7713 instruct xchgN( memory mem, rRegN newval) %{
7714 match(Set newval (GetAndSetN mem newval));
7715 format %{ "XCHGL $newval,$mem]" %}
7716 ins_encode %{
7717 __ xchgl($newval$$Register, $mem$$Address);
7718 %}
7719 ins_pipe( pipe_cmpxchg );
7720 %}
7721
7722 //----------Subtraction Instructions-------------------------------------------
7723
7724 // Integer Subtraction Instructions
7725 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7726 %{
7727 match(Set dst (SubI dst src));
7728 effect(KILL cr);
7729
7730 format %{ "subl $dst, $src\t# int" %}
7731 opcode(0x2B);
7732 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7733 ins_pipe(ialu_reg_reg);
7734 %}
7735
7736 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7737 %{
7738 match(Set dst (SubI dst src));
7739 effect(KILL cr);
7740
7741 format %{ "subl $dst, $src\t# int" %}
7742 opcode(0x81, 0x05); /* Opcode 81 /5 */
7743 ins_encode(OpcSErm(dst, src), Con8or32(src));
7744 ins_pipe(ialu_reg);
7745 %}
7746
7747 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7748 %{
7749 match(Set dst (SubI dst (LoadI src)));
7750 effect(KILL cr);
7751
7752 ins_cost(125);
7753 format %{ "subl $dst, $src\t# int" %}
7754 opcode(0x2B);
7755 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7756 ins_pipe(ialu_reg_mem);
7757 %}
7758
7759 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7760 %{
7761 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7762 effect(KILL cr);
7763
7764 ins_cost(150);
7765 format %{ "subl $dst, $src\t# int" %}
7766 opcode(0x29); /* Opcode 29 /r */
7767 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7768 ins_pipe(ialu_mem_reg);
7769 %}
7770
7771 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7772 %{
7773 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7774 effect(KILL cr);
7775
7776 ins_cost(125); // XXX
7777 format %{ "subl $dst, $src\t# int" %}
7778 opcode(0x81); /* Opcode 81 /5 id */
7779 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7780 ins_pipe(ialu_mem_imm);
7781 %}
7782
7783 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7784 %{
7785 match(Set dst (SubL dst src));
7786 effect(KILL cr);
7787
7788 format %{ "subq $dst, $src\t# long" %}
7789 opcode(0x2B);
7790 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7791 ins_pipe(ialu_reg_reg);
7792 %}
7793
7794 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7795 %{
7796 match(Set dst (SubL dst src));
7797 effect(KILL cr);
7798
7799 format %{ "subq $dst, $src\t# long" %}
7800 opcode(0x81, 0x05); /* Opcode 81 /5 */
7801 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7802 ins_pipe(ialu_reg);
7803 %}
7804
7805 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7806 %{
7807 match(Set dst (SubL dst (LoadL src)));
7808 effect(KILL cr);
7809
7810 ins_cost(125);
7811 format %{ "subq $dst, $src\t# long" %}
7812 opcode(0x2B);
7813 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7814 ins_pipe(ialu_reg_mem);
7815 %}
7816
7817 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7818 %{
7819 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7820 effect(KILL cr);
7821
7822 ins_cost(150);
7823 format %{ "subq $dst, $src\t# long" %}
7824 opcode(0x29); /* Opcode 29 /r */
7825 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7826 ins_pipe(ialu_mem_reg);
7827 %}
7828
7829 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7830 %{
7831 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7832 effect(KILL cr);
7833
7834 ins_cost(125); // XXX
7835 format %{ "subq $dst, $src\t# long" %}
7836 opcode(0x81); /* Opcode 81 /5 id */
7837 ins_encode(REX_mem_wide(dst),
7838 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7839 ins_pipe(ialu_mem_imm);
7840 %}
7841
7842 // Subtract from a pointer
7843 // XXX hmpf???
7844 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7845 %{
7846 match(Set dst (AddP dst (SubI zero src)));
7847 effect(KILL cr);
7848
7849 format %{ "subq $dst, $src\t# ptr - int" %}
7850 opcode(0x2B);
7851 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7852 ins_pipe(ialu_reg_reg);
7853 %}
7854
7855 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7856 %{
7857 match(Set dst (SubI zero dst));
7858 effect(KILL cr);
7859
7860 format %{ "negl $dst\t# int" %}
7861 opcode(0xF7, 0x03); // Opcode F7 /3
7862 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7863 ins_pipe(ialu_reg);
7864 %}
7865
7866 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7867 %{
7868 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7869 effect(KILL cr);
7870
7871 format %{ "negl $dst\t# int" %}
7872 opcode(0xF7, 0x03); // Opcode F7 /3
7873 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7874 ins_pipe(ialu_reg);
7875 %}
7876
7877 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7878 %{
7879 match(Set dst (SubL zero dst));
7880 effect(KILL cr);
7881
7882 format %{ "negq $dst\t# long" %}
7883 opcode(0xF7, 0x03); // Opcode F7 /3
7884 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7885 ins_pipe(ialu_reg);
7886 %}
7887
7888 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7889 %{
7890 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7891 effect(KILL cr);
7892
7893 format %{ "negq $dst\t# long" %}
7894 opcode(0xF7, 0x03); // Opcode F7 /3
7895 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7896 ins_pipe(ialu_reg);
7897 %}
7898
7899 //----------Multiplication/Division Instructions-------------------------------
7900 // Integer Multiplication Instructions
7901 // Multiply Register
7902
7903 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7904 %{
7905 match(Set dst (MulI dst src));
7906 effect(KILL cr);
7907
7908 ins_cost(300);
7909 format %{ "imull $dst, $src\t# int" %}
7910 opcode(0x0F, 0xAF);
7911 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7912 ins_pipe(ialu_reg_reg_alu0);
7913 %}
7914
7915 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7916 %{
7917 match(Set dst (MulI src imm));
7918 effect(KILL cr);
7919
7920 ins_cost(300);
7921 format %{ "imull $dst, $src, $imm\t# int" %}
7922 opcode(0x69); /* 69 /r id */
7923 ins_encode(REX_reg_reg(dst, src),
7924 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7925 ins_pipe(ialu_reg_reg_alu0);
7926 %}
7927
7928 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7929 %{
7930 match(Set dst (MulI dst (LoadI src)));
7931 effect(KILL cr);
7932
7933 ins_cost(350);
7934 format %{ "imull $dst, $src\t# int" %}
7935 opcode(0x0F, 0xAF);
7936 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7937 ins_pipe(ialu_reg_mem_alu0);
7938 %}
7939
7940 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7941 %{
7942 match(Set dst (MulI (LoadI src) imm));
7943 effect(KILL cr);
7944
7945 ins_cost(300);
7946 format %{ "imull $dst, $src, $imm\t# int" %}
7947 opcode(0x69); /* 69 /r id */
7948 ins_encode(REX_reg_mem(dst, src),
7949 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7950 ins_pipe(ialu_reg_mem_alu0);
7951 %}
7952
7953 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7954 %{
7955 match(Set dst (MulL dst src));
7956 effect(KILL cr);
7957
7958 ins_cost(300);
7959 format %{ "imulq $dst, $src\t# long" %}
7960 opcode(0x0F, 0xAF);
7961 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7962 ins_pipe(ialu_reg_reg_alu0);
7963 %}
7964
7965 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7966 %{
7967 match(Set dst (MulL src imm));
7968 effect(KILL cr);
7969
7970 ins_cost(300);
7971 format %{ "imulq $dst, $src, $imm\t# long" %}
7972 opcode(0x69); /* 69 /r id */
7973 ins_encode(REX_reg_reg_wide(dst, src),
7974 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7975 ins_pipe(ialu_reg_reg_alu0);
7976 %}
7977
7978 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7979 %{
7980 match(Set dst (MulL dst (LoadL src)));
7981 effect(KILL cr);
7982
7983 ins_cost(350);
7984 format %{ "imulq $dst, $src\t# long" %}
7985 opcode(0x0F, 0xAF);
7986 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7987 ins_pipe(ialu_reg_mem_alu0);
7988 %}
7989
7990 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7991 %{
7992 match(Set dst (MulL (LoadL src) imm));
7993 effect(KILL cr);
7994
7995 ins_cost(300);
7996 format %{ "imulq $dst, $src, $imm\t# long" %}
7997 opcode(0x69); /* 69 /r id */
7998 ins_encode(REX_reg_mem_wide(dst, src),
7999 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8000 ins_pipe(ialu_reg_mem_alu0);
8001 %}
8002
8003 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8004 %{
8005 match(Set dst (MulHiL src rax));
8006 effect(USE_KILL rax, KILL cr);
8007
8008 ins_cost(300);
8009 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8010 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8011 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8012 ins_pipe(ialu_reg_reg_alu0);
8013 %}
8014
8015 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8016 rFlagsReg cr)
8017 %{
8018 match(Set rax (DivI rax div));
8019 effect(KILL rdx, KILL cr);
8020
8021 ins_cost(30*100+10*100); // XXX
8022 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8023 "jne,s normal\n\t"
8024 "xorl rdx, rdx\n\t"
8025 "cmpl $div, -1\n\t"
8026 "je,s done\n"
8027 "normal: cdql\n\t"
8028 "idivl $div\n"
8029 "done:" %}
8030 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8031 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8032 ins_pipe(ialu_reg_reg_alu0);
8033 %}
8034
8035 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8036 rFlagsReg cr)
8037 %{
8038 match(Set rax (DivL rax div));
8039 effect(KILL rdx, KILL cr);
8040
8041 ins_cost(30*100+10*100); // XXX
8042 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8043 "cmpq rax, rdx\n\t"
8044 "jne,s normal\n\t"
8045 "xorl rdx, rdx\n\t"
8046 "cmpq $div, -1\n\t"
8047 "je,s done\n"
8048 "normal: cdqq\n\t"
8049 "idivq $div\n"
8050 "done:" %}
8051 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8052 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8053 ins_pipe(ialu_reg_reg_alu0);
8054 %}
8055
8056 // Integer DIVMOD with Register, both quotient and mod results
8057 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8058 rFlagsReg cr)
8059 %{
8060 match(DivModI rax div);
8061 effect(KILL cr);
8062
8063 ins_cost(30*100+10*100); // XXX
8064 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8065 "jne,s normal\n\t"
8066 "xorl rdx, rdx\n\t"
8067 "cmpl $div, -1\n\t"
8068 "je,s done\n"
8069 "normal: cdql\n\t"
8070 "idivl $div\n"
8071 "done:" %}
8072 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8073 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8074 ins_pipe(pipe_slow);
8075 %}
8076
8077 // Long DIVMOD with Register, both quotient and mod results
8078 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8079 rFlagsReg cr)
8080 %{
8081 match(DivModL rax div);
8082 effect(KILL cr);
8083
8084 ins_cost(30*100+10*100); // XXX
8085 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8086 "cmpq rax, rdx\n\t"
8087 "jne,s normal\n\t"
8088 "xorl rdx, rdx\n\t"
8089 "cmpq $div, -1\n\t"
8090 "je,s done\n"
8091 "normal: cdqq\n\t"
8092 "idivq $div\n"
8093 "done:" %}
8094 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8095 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8096 ins_pipe(pipe_slow);
8097 %}
8098
8099 //----------- DivL-By-Constant-Expansions--------------------------------------
8100 // DivI cases are handled by the compiler
8101
8102 // Magic constant, reciprocal of 10
8103 instruct loadConL_0x6666666666666667(rRegL dst)
8104 %{
8105 effect(DEF dst);
8106
8107 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8108 ins_encode(load_immL(dst, 0x6666666666666667));
8109 ins_pipe(ialu_reg);
8110 %}
8111
8112 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8113 %{
8114 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8115
8116 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8117 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8118 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8119 ins_pipe(ialu_reg_reg_alu0);
8120 %}
8121
8122 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8123 %{
8124 effect(USE_DEF dst, KILL cr);
8125
8126 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8127 opcode(0xC1, 0x7); /* C1 /7 ib */
8128 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8129 ins_pipe(ialu_reg);
8130 %}
8131
8132 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8133 %{
8134 effect(USE_DEF dst, KILL cr);
8135
8136 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8137 opcode(0xC1, 0x7); /* C1 /7 ib */
8138 ins_encode(reg_opc_imm_wide(dst, 0x2));
8139 ins_pipe(ialu_reg);
8140 %}
8141
8142 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8143 %{
8144 match(Set dst (DivL src div));
8145
8146 ins_cost((5+8)*100);
8147 expand %{
8148 rax_RegL rax; // Killed temp
8149 rFlagsReg cr; // Killed
8150 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8151 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8152 sarL_rReg_63(src, cr); // sarq src, 63
8153 sarL_rReg_2(dst, cr); // sarq rdx, 2
8154 subL_rReg(dst, src, cr); // subl rdx, src
8155 %}
8156 %}
8157
8158 //-----------------------------------------------------------------------------
8159
8160 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8161 rFlagsReg cr)
8162 %{
8163 match(Set rdx (ModI rax div));
8164 effect(KILL rax, KILL cr);
8165
8166 ins_cost(300); // XXX
8167 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8168 "jne,s normal\n\t"
8169 "xorl rdx, rdx\n\t"
8170 "cmpl $div, -1\n\t"
8171 "je,s done\n"
8172 "normal: cdql\n\t"
8173 "idivl $div\n"
8174 "done:" %}
8175 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8176 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8177 ins_pipe(ialu_reg_reg_alu0);
8178 %}
8179
8180 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8181 rFlagsReg cr)
8182 %{
8183 match(Set rdx (ModL rax div));
8184 effect(KILL rax, KILL cr);
8185
8186 ins_cost(300); // XXX
8187 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8188 "cmpq rax, rdx\n\t"
8189 "jne,s normal\n\t"
8190 "xorl rdx, rdx\n\t"
8191 "cmpq $div, -1\n\t"
8192 "je,s done\n"
8193 "normal: cdqq\n\t"
8194 "idivq $div\n"
8195 "done:" %}
8196 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8197 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8198 ins_pipe(ialu_reg_reg_alu0);
8199 %}
8200
8201 // Integer Shift Instructions
8202 // Shift Left by one
8203 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8204 %{
8205 match(Set dst (LShiftI dst shift));
8206 effect(KILL cr);
8207
8208 format %{ "sall $dst, $shift" %}
8209 opcode(0xD1, 0x4); /* D1 /4 */
8210 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8211 ins_pipe(ialu_reg);
8212 %}
8213
8214 // Shift Left by one
8215 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8216 %{
8217 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8218 effect(KILL cr);
8219
8220 format %{ "sall $dst, $shift\t" %}
8221 opcode(0xD1, 0x4); /* D1 /4 */
8222 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8223 ins_pipe(ialu_mem_imm);
8224 %}
8225
8226 // Shift Left by 8-bit immediate
8227 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8228 %{
8229 match(Set dst (LShiftI dst shift));
8230 effect(KILL cr);
8231
8232 format %{ "sall $dst, $shift" %}
8233 opcode(0xC1, 0x4); /* C1 /4 ib */
8234 ins_encode(reg_opc_imm(dst, shift));
8235 ins_pipe(ialu_reg);
8236 %}
8237
8238 // Shift Left by 8-bit immediate
8239 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8240 %{
8241 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8242 effect(KILL cr);
8243
8244 format %{ "sall $dst, $shift" %}
8245 opcode(0xC1, 0x4); /* C1 /4 ib */
8246 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8247 ins_pipe(ialu_mem_imm);
8248 %}
8249
8250 // Shift Left by variable
8251 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8252 %{
8253 match(Set dst (LShiftI dst shift));
8254 effect(KILL cr);
8255
8256 format %{ "sall $dst, $shift" %}
8257 opcode(0xD3, 0x4); /* D3 /4 */
8258 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8259 ins_pipe(ialu_reg_reg);
8260 %}
8261
8262 // Shift Left by variable
8263 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8264 %{
8265 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8266 effect(KILL cr);
8267
8268 format %{ "sall $dst, $shift" %}
8269 opcode(0xD3, 0x4); /* D3 /4 */
8270 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8271 ins_pipe(ialu_mem_reg);
8272 %}
8273
8274 // Arithmetic shift right by one
8275 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8276 %{
8277 match(Set dst (RShiftI dst shift));
8278 effect(KILL cr);
8279
8280 format %{ "sarl $dst, $shift" %}
8281 opcode(0xD1, 0x7); /* D1 /7 */
8282 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8283 ins_pipe(ialu_reg);
8284 %}
8285
8286 // Arithmetic shift right by one
8287 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8288 %{
8289 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8290 effect(KILL cr);
8291
8292 format %{ "sarl $dst, $shift" %}
8293 opcode(0xD1, 0x7); /* D1 /7 */
8294 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8295 ins_pipe(ialu_mem_imm);
8296 %}
8297
8298 // Arithmetic Shift Right by 8-bit immediate
8299 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8300 %{
8301 match(Set dst (RShiftI dst shift));
8302 effect(KILL cr);
8303
8304 format %{ "sarl $dst, $shift" %}
8305 opcode(0xC1, 0x7); /* C1 /7 ib */
8306 ins_encode(reg_opc_imm(dst, shift));
8307 ins_pipe(ialu_mem_imm);
8308 %}
8309
8310 // Arithmetic Shift Right by 8-bit immediate
8311 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8312 %{
8313 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8314 effect(KILL cr);
8315
8316 format %{ "sarl $dst, $shift" %}
8317 opcode(0xC1, 0x7); /* C1 /7 ib */
8318 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8319 ins_pipe(ialu_mem_imm);
8320 %}
8321
8322 // Arithmetic Shift Right by variable
8323 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8324 %{
8325 match(Set dst (RShiftI dst shift));
8326 effect(KILL cr);
8327
8328 format %{ "sarl $dst, $shift" %}
8329 opcode(0xD3, 0x7); /* D3 /7 */
8330 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8331 ins_pipe(ialu_reg_reg);
8332 %}
8333
8334 // Arithmetic Shift Right by variable
8335 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8336 %{
8337 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8338 effect(KILL cr);
8339
8340 format %{ "sarl $dst, $shift" %}
8341 opcode(0xD3, 0x7); /* D3 /7 */
8342 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8343 ins_pipe(ialu_mem_reg);
8344 %}
8345
8346 // Logical shift right by one
8347 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8348 %{
8349 match(Set dst (URShiftI dst shift));
8350 effect(KILL cr);
8351
8352 format %{ "shrl $dst, $shift" %}
8353 opcode(0xD1, 0x5); /* D1 /5 */
8354 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8355 ins_pipe(ialu_reg);
8356 %}
8357
8358 // Logical shift right by one
8359 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8360 %{
8361 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8362 effect(KILL cr);
8363
8364 format %{ "shrl $dst, $shift" %}
8365 opcode(0xD1, 0x5); /* D1 /5 */
8366 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8367 ins_pipe(ialu_mem_imm);
8368 %}
8369
8370 // Logical Shift Right by 8-bit immediate
8371 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8372 %{
8373 match(Set dst (URShiftI dst shift));
8374 effect(KILL cr);
8375
8376 format %{ "shrl $dst, $shift" %}
8377 opcode(0xC1, 0x5); /* C1 /5 ib */
8378 ins_encode(reg_opc_imm(dst, shift));
8379 ins_pipe(ialu_reg);
8380 %}
8381
8382 // Logical Shift Right by 8-bit immediate
8383 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8384 %{
8385 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8386 effect(KILL cr);
8387
8388 format %{ "shrl $dst, $shift" %}
8389 opcode(0xC1, 0x5); /* C1 /5 ib */
8390 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8391 ins_pipe(ialu_mem_imm);
8392 %}
8393
8394 // Logical Shift Right by variable
8395 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8396 %{
8397 match(Set dst (URShiftI dst shift));
8398 effect(KILL cr);
8399
8400 format %{ "shrl $dst, $shift" %}
8401 opcode(0xD3, 0x5); /* D3 /5 */
8402 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8403 ins_pipe(ialu_reg_reg);
8404 %}
8405
8406 // Logical Shift Right by variable
8407 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8408 %{
8409 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8410 effect(KILL cr);
8411
8412 format %{ "shrl $dst, $shift" %}
8413 opcode(0xD3, 0x5); /* D3 /5 */
8414 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8415 ins_pipe(ialu_mem_reg);
8416 %}
8417
8418 // Long Shift Instructions
8419 // Shift Left by one
8420 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8421 %{
8422 match(Set dst (LShiftL dst shift));
8423 effect(KILL cr);
8424
8425 format %{ "salq $dst, $shift" %}
8426 opcode(0xD1, 0x4); /* D1 /4 */
8427 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8428 ins_pipe(ialu_reg);
8429 %}
8430
8431 // Shift Left by one
8432 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8433 %{
8434 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8435 effect(KILL cr);
8436
8437 format %{ "salq $dst, $shift" %}
8438 opcode(0xD1, 0x4); /* D1 /4 */
8439 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8440 ins_pipe(ialu_mem_imm);
8441 %}
8442
8443 // Shift Left by 8-bit immediate
8444 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8445 %{
8446 match(Set dst (LShiftL dst shift));
8447 effect(KILL cr);
8448
8449 format %{ "salq $dst, $shift" %}
8450 opcode(0xC1, 0x4); /* C1 /4 ib */
8451 ins_encode(reg_opc_imm_wide(dst, shift));
8452 ins_pipe(ialu_reg);
8453 %}
8454
8455 // Shift Left by 8-bit immediate
8456 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8457 %{
8458 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8459 effect(KILL cr);
8460
8461 format %{ "salq $dst, $shift" %}
8462 opcode(0xC1, 0x4); /* C1 /4 ib */
8463 ins_encode(REX_mem_wide(dst), OpcP,
8464 RM_opc_mem(secondary, dst), Con8or32(shift));
8465 ins_pipe(ialu_mem_imm);
8466 %}
8467
8468 // Shift Left by variable
8469 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8470 %{
8471 match(Set dst (LShiftL dst shift));
8472 effect(KILL cr);
8473
8474 format %{ "salq $dst, $shift" %}
8475 opcode(0xD3, 0x4); /* D3 /4 */
8476 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8477 ins_pipe(ialu_reg_reg);
8478 %}
8479
8480 // Shift Left by variable
8481 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8482 %{
8483 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8484 effect(KILL cr);
8485
8486 format %{ "salq $dst, $shift" %}
8487 opcode(0xD3, 0x4); /* D3 /4 */
8488 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8489 ins_pipe(ialu_mem_reg);
8490 %}
8491
8492 // Arithmetic shift right by one
8493 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8494 %{
8495 match(Set dst (RShiftL dst shift));
8496 effect(KILL cr);
8497
8498 format %{ "sarq $dst, $shift" %}
8499 opcode(0xD1, 0x7); /* D1 /7 */
8500 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8501 ins_pipe(ialu_reg);
8502 %}
8503
8504 // Arithmetic shift right by one
8505 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8506 %{
8507 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8508 effect(KILL cr);
8509
8510 format %{ "sarq $dst, $shift" %}
8511 opcode(0xD1, 0x7); /* D1 /7 */
8512 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8513 ins_pipe(ialu_mem_imm);
8514 %}
8515
8516 // Arithmetic Shift Right by 8-bit immediate
8517 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8518 %{
8519 match(Set dst (RShiftL dst shift));
8520 effect(KILL cr);
8521
8522 format %{ "sarq $dst, $shift" %}
8523 opcode(0xC1, 0x7); /* C1 /7 ib */
8524 ins_encode(reg_opc_imm_wide(dst, shift));
8525 ins_pipe(ialu_mem_imm);
8526 %}
8527
8528 // Arithmetic Shift Right by 8-bit immediate
8529 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8530 %{
8531 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8532 effect(KILL cr);
8533
8534 format %{ "sarq $dst, $shift" %}
8535 opcode(0xC1, 0x7); /* C1 /7 ib */
8536 ins_encode(REX_mem_wide(dst), OpcP,
8537 RM_opc_mem(secondary, dst), Con8or32(shift));
8538 ins_pipe(ialu_mem_imm);
8539 %}
8540
8541 // Arithmetic Shift Right by variable
8542 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8543 %{
8544 match(Set dst (RShiftL dst shift));
8545 effect(KILL cr);
8546
8547 format %{ "sarq $dst, $shift" %}
8548 opcode(0xD3, 0x7); /* D3 /7 */
8549 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8550 ins_pipe(ialu_reg_reg);
8551 %}
8552
8553 // Arithmetic Shift Right by variable
8554 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8555 %{
8556 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8557 effect(KILL cr);
8558
8559 format %{ "sarq $dst, $shift" %}
8560 opcode(0xD3, 0x7); /* D3 /7 */
8561 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8562 ins_pipe(ialu_mem_reg);
8563 %}
8564
8565 // Logical shift right by one
8566 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8567 %{
8568 match(Set dst (URShiftL dst shift));
8569 effect(KILL cr);
8570
8571 format %{ "shrq $dst, $shift" %}
8572 opcode(0xD1, 0x5); /* D1 /5 */
8573 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8574 ins_pipe(ialu_reg);
8575 %}
8576
8577 // Logical shift right by one
8578 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8579 %{
8580 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8581 effect(KILL cr);
8582
8583 format %{ "shrq $dst, $shift" %}
8584 opcode(0xD1, 0x5); /* D1 /5 */
8585 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8586 ins_pipe(ialu_mem_imm);
8587 %}
8588
8589 // Logical Shift Right by 8-bit immediate
8590 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8591 %{
8592 match(Set dst (URShiftL dst shift));
8593 effect(KILL cr);
8594
8595 format %{ "shrq $dst, $shift" %}
8596 opcode(0xC1, 0x5); /* C1 /5 ib */
8597 ins_encode(reg_opc_imm_wide(dst, shift));
8598 ins_pipe(ialu_reg);
8599 %}
8600
8601
8602 // Logical Shift Right by 8-bit immediate
8603 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8604 %{
8605 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8606 effect(KILL cr);
8607
8608 format %{ "shrq $dst, $shift" %}
8609 opcode(0xC1, 0x5); /* C1 /5 ib */
8610 ins_encode(REX_mem_wide(dst), OpcP,
8611 RM_opc_mem(secondary, dst), Con8or32(shift));
8612 ins_pipe(ialu_mem_imm);
8613 %}
8614
8615 // Logical Shift Right by variable
8616 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8617 %{
8618 match(Set dst (URShiftL dst shift));
8619 effect(KILL cr);
8620
8621 format %{ "shrq $dst, $shift" %}
8622 opcode(0xD3, 0x5); /* D3 /5 */
8623 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8624 ins_pipe(ialu_reg_reg);
8625 %}
8626
8627 // Logical Shift Right by variable
8628 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8629 %{
8630 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8631 effect(KILL cr);
8632
8633 format %{ "shrq $dst, $shift" %}
8634 opcode(0xD3, 0x5); /* D3 /5 */
8635 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8636 ins_pipe(ialu_mem_reg);
8637 %}
8638
8639 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8640 // This idiom is used by the compiler for the i2b bytecode.
8641 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8642 %{
8643 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8644
8645 format %{ "movsbl $dst, $src\t# i2b" %}
8646 opcode(0x0F, 0xBE);
8647 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8648 ins_pipe(ialu_reg_reg);
8649 %}
8650
8651 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8652 // This idiom is used by the compiler the i2s bytecode.
8653 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8654 %{
8655 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8656
8657 format %{ "movswl $dst, $src\t# i2s" %}
8658 opcode(0x0F, 0xBF);
8659 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8660 ins_pipe(ialu_reg_reg);
8661 %}
8662
8663 // ROL/ROR instructions
8664
8665 // ROL expand
8666 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8667 effect(KILL cr, USE_DEF dst);
8668
8669 format %{ "roll $dst" %}
8670 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8671 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8672 ins_pipe(ialu_reg);
8673 %}
8674
8675 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8676 effect(USE_DEF dst, USE shift, KILL cr);
8677
8678 format %{ "roll $dst, $shift" %}
8679 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8680 ins_encode( reg_opc_imm(dst, shift) );
8681 ins_pipe(ialu_reg);
8682 %}
8683
8684 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8685 %{
8686 effect(USE_DEF dst, USE shift, KILL cr);
8687
8688 format %{ "roll $dst, $shift" %}
8689 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8690 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8691 ins_pipe(ialu_reg_reg);
8692 %}
8693 // end of ROL expand
8694
8695 // Rotate Left by one
8696 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8697 %{
8698 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8699
8700 expand %{
8701 rolI_rReg_imm1(dst, cr);
8702 %}
8703 %}
8704
8705 // Rotate Left by 8-bit immediate
8706 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8707 %{
8708 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8709 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8710
8711 expand %{
8712 rolI_rReg_imm8(dst, lshift, cr);
8713 %}
8714 %}
8715
8716 // Rotate Left by variable
8717 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8718 %{
8719 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8720
8721 expand %{
8722 rolI_rReg_CL(dst, shift, cr);
8723 %}
8724 %}
8725
8726 // Rotate Left by variable
8727 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8728 %{
8729 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8730
8731 expand %{
8732 rolI_rReg_CL(dst, shift, cr);
8733 %}
8734 %}
8735
8736 // ROR expand
8737 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8738 %{
8739 effect(USE_DEF dst, KILL cr);
8740
8741 format %{ "rorl $dst" %}
8742 opcode(0xD1, 0x1); /* D1 /1 */
8743 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8744 ins_pipe(ialu_reg);
8745 %}
8746
8747 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8748 %{
8749 effect(USE_DEF dst, USE shift, KILL cr);
8750
8751 format %{ "rorl $dst, $shift" %}
8752 opcode(0xC1, 0x1); /* C1 /1 ib */
8753 ins_encode(reg_opc_imm(dst, shift));
8754 ins_pipe(ialu_reg);
8755 %}
8756
8757 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8758 %{
8759 effect(USE_DEF dst, USE shift, KILL cr);
8760
8761 format %{ "rorl $dst, $shift" %}
8762 opcode(0xD3, 0x1); /* D3 /1 */
8763 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8764 ins_pipe(ialu_reg_reg);
8765 %}
8766 // end of ROR expand
8767
8768 // Rotate Right by one
8769 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8770 %{
8771 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8772
8773 expand %{
8774 rorI_rReg_imm1(dst, cr);
8775 %}
8776 %}
8777
8778 // Rotate Right by 8-bit immediate
8779 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8780 %{
8781 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8782 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8783
8784 expand %{
8785 rorI_rReg_imm8(dst, rshift, cr);
8786 %}
8787 %}
8788
8789 // Rotate Right by variable
8790 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8791 %{
8792 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8793
8794 expand %{
8795 rorI_rReg_CL(dst, shift, cr);
8796 %}
8797 %}
8798
8799 // Rotate Right by variable
8800 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8801 %{
8802 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8803
8804 expand %{
8805 rorI_rReg_CL(dst, shift, cr);
8806 %}
8807 %}
8808
8809 // for long rotate
8810 // ROL expand
8811 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8812 effect(USE_DEF dst, KILL cr);
8813
8814 format %{ "rolq $dst" %}
8815 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8816 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8817 ins_pipe(ialu_reg);
8818 %}
8819
8820 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8821 effect(USE_DEF dst, USE shift, KILL cr);
8822
8823 format %{ "rolq $dst, $shift" %}
8824 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8825 ins_encode( reg_opc_imm_wide(dst, shift) );
8826 ins_pipe(ialu_reg);
8827 %}
8828
8829 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8830 %{
8831 effect(USE_DEF dst, USE shift, KILL cr);
8832
8833 format %{ "rolq $dst, $shift" %}
8834 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8835 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8836 ins_pipe(ialu_reg_reg);
8837 %}
8838 // end of ROL expand
8839
8840 // Rotate Left by one
8841 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8842 %{
8843 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8844
8845 expand %{
8846 rolL_rReg_imm1(dst, cr);
8847 %}
8848 %}
8849
8850 // Rotate Left by 8-bit immediate
8851 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8852 %{
8853 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8854 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8855
8856 expand %{
8857 rolL_rReg_imm8(dst, lshift, cr);
8858 %}
8859 %}
8860
8861 // Rotate Left by variable
8862 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8863 %{
8864 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8865
8866 expand %{
8867 rolL_rReg_CL(dst, shift, cr);
8868 %}
8869 %}
8870
8871 // Rotate Left by variable
8872 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8873 %{
8874 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8875
8876 expand %{
8877 rolL_rReg_CL(dst, shift, cr);
8878 %}
8879 %}
8880
8881 // ROR expand
8882 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8883 %{
8884 effect(USE_DEF dst, KILL cr);
8885
8886 format %{ "rorq $dst" %}
8887 opcode(0xD1, 0x1); /* D1 /1 */
8888 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8889 ins_pipe(ialu_reg);
8890 %}
8891
8892 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8893 %{
8894 effect(USE_DEF dst, USE shift, KILL cr);
8895
8896 format %{ "rorq $dst, $shift" %}
8897 opcode(0xC1, 0x1); /* C1 /1 ib */
8898 ins_encode(reg_opc_imm_wide(dst, shift));
8899 ins_pipe(ialu_reg);
8900 %}
8901
8902 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8903 %{
8904 effect(USE_DEF dst, USE shift, KILL cr);
8905
8906 format %{ "rorq $dst, $shift" %}
8907 opcode(0xD3, 0x1); /* D3 /1 */
8908 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8909 ins_pipe(ialu_reg_reg);
8910 %}
8911 // end of ROR expand
8912
8913 // Rotate Right by one
8914 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8915 %{
8916 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8917
8918 expand %{
8919 rorL_rReg_imm1(dst, cr);
8920 %}
8921 %}
8922
8923 // Rotate Right by 8-bit immediate
8924 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8925 %{
8926 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8927 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8928
8929 expand %{
8930 rorL_rReg_imm8(dst, rshift, cr);
8931 %}
8932 %}
8933
8934 // Rotate Right by variable
8935 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8936 %{
8937 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8938
8939 expand %{
8940 rorL_rReg_CL(dst, shift, cr);
8941 %}
8942 %}
8943
8944 // Rotate Right by variable
8945 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8946 %{
8947 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8948
8949 expand %{
8950 rorL_rReg_CL(dst, shift, cr);
8951 %}
8952 %}
8953
8954 // Logical Instructions
8955
8956 // Integer Logical Instructions
8957
8958 // And Instructions
8959 // And Register with Register
8960 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8961 %{
8962 match(Set dst (AndI dst src));
8963 effect(KILL cr);
8964
8965 format %{ "andl $dst, $src\t# int" %}
8966 opcode(0x23);
8967 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8968 ins_pipe(ialu_reg_reg);
8969 %}
8970
8971 // And Register with Immediate 255
8972 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8973 %{
8974 match(Set dst (AndI dst src));
8975
8976 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8977 opcode(0x0F, 0xB6);
8978 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8979 ins_pipe(ialu_reg);
8980 %}
8981
8982 // And Register with Immediate 255 and promote to long
8983 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8984 %{
8985 match(Set dst (ConvI2L (AndI src mask)));
8986
8987 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8988 opcode(0x0F, 0xB6);
8989 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8990 ins_pipe(ialu_reg);
8991 %}
8992
8993 // And Register with Immediate 65535
8994 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8995 %{
8996 match(Set dst (AndI dst src));
8997
8998 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8999 opcode(0x0F, 0xB7);
9000 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9001 ins_pipe(ialu_reg);
9002 %}
9003
9004 // And Register with Immediate 65535 and promote to long
9005 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9006 %{
9007 match(Set dst (ConvI2L (AndI src mask)));
9008
9009 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9010 opcode(0x0F, 0xB7);
9011 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9012 ins_pipe(ialu_reg);
9013 %}
9014
9015 // And Register with Immediate
9016 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9017 %{
9018 match(Set dst (AndI dst src));
9019 effect(KILL cr);
9020
9021 format %{ "andl $dst, $src\t# int" %}
9022 opcode(0x81, 0x04); /* Opcode 81 /4 */
9023 ins_encode(OpcSErm(dst, src), Con8or32(src));
9024 ins_pipe(ialu_reg);
9025 %}
9026
9027 // And Register with Memory
9028 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9029 %{
9030 match(Set dst (AndI dst (LoadI src)));
9031 effect(KILL cr);
9032
9033 ins_cost(125);
9034 format %{ "andl $dst, $src\t# int" %}
9035 opcode(0x23);
9036 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9037 ins_pipe(ialu_reg_mem);
9038 %}
9039
9040 // And Memory with Register
9041 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9042 %{
9043 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9044 effect(KILL cr);
9045
9046 ins_cost(150);
9047 format %{ "andl $dst, $src\t# int" %}
9048 opcode(0x21); /* Opcode 21 /r */
9049 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9050 ins_pipe(ialu_mem_reg);
9051 %}
9052
9053 // And Memory with Immediate
9054 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9055 %{
9056 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9057 effect(KILL cr);
9058
9059 ins_cost(125);
9060 format %{ "andl $dst, $src\t# int" %}
9061 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9062 ins_encode(REX_mem(dst), OpcSE(src),
9063 RM_opc_mem(secondary, dst), Con8or32(src));
9064 ins_pipe(ialu_mem_imm);
9065 %}
9066
9067 // BMI1 instructions
9068 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9069 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9070 predicate(UseBMI1Instructions);
9071 effect(KILL cr);
9072
9073 ins_cost(125);
9074 format %{ "andnl $dst, $src1, $src2" %}
9075
9076 ins_encode %{
9077 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9078 %}
9079 ins_pipe(ialu_reg_mem);
9080 %}
9081
9082 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9083 match(Set dst (AndI (XorI src1 minus_1) src2));
9084 predicate(UseBMI1Instructions);
9085 effect(KILL cr);
9086
9087 format %{ "andnl $dst, $src1, $src2" %}
9088
9089 ins_encode %{
9090 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9091 %}
9092 ins_pipe(ialu_reg);
9093 %}
9094
9095 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9096 match(Set dst (AndI (SubI imm_zero src) src));
9097 predicate(UseBMI1Instructions);
9098 effect(KILL cr);
9099
9100 format %{ "blsil $dst, $src" %}
9101
9102 ins_encode %{
9103 __ blsil($dst$$Register, $src$$Register);
9104 %}
9105 ins_pipe(ialu_reg);
9106 %}
9107
9108 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9109 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9110 predicate(UseBMI1Instructions);
9111 effect(KILL cr);
9112
9113 ins_cost(125);
9114 format %{ "blsil $dst, $src" %}
9115
9116 ins_encode %{
9117 __ blsil($dst$$Register, $src$$Address);
9118 %}
9119 ins_pipe(ialu_reg_mem);
9120 %}
9121
9122 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9123 %{
9124 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9125 predicate(UseBMI1Instructions);
9126 effect(KILL cr);
9127
9128 ins_cost(125);
9129 format %{ "blsmskl $dst, $src" %}
9130
9131 ins_encode %{
9132 __ blsmskl($dst$$Register, $src$$Address);
9133 %}
9134 ins_pipe(ialu_reg_mem);
9135 %}
9136
9137 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9138 %{
9139 match(Set dst (XorI (AddI src minus_1) src));
9140 predicate(UseBMI1Instructions);
9141 effect(KILL cr);
9142
9143 format %{ "blsmskl $dst, $src" %}
9144
9145 ins_encode %{
9146 __ blsmskl($dst$$Register, $src$$Register);
9147 %}
9148
9149 ins_pipe(ialu_reg);
9150 %}
9151
9152 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9153 %{
9154 match(Set dst (AndI (AddI src minus_1) src) );
9155 predicate(UseBMI1Instructions);
9156 effect(KILL cr);
9157
9158 format %{ "blsrl $dst, $src" %}
9159
9160 ins_encode %{
9161 __ blsrl($dst$$Register, $src$$Register);
9162 %}
9163
9164 ins_pipe(ialu_reg_mem);
9165 %}
9166
9167 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9168 %{
9169 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9170 predicate(UseBMI1Instructions);
9171 effect(KILL cr);
9172
9173 ins_cost(125);
9174 format %{ "blsrl $dst, $src" %}
9175
9176 ins_encode %{
9177 __ blsrl($dst$$Register, $src$$Address);
9178 %}
9179
9180 ins_pipe(ialu_reg);
9181 %}
9182
9183 // Or Instructions
9184 // Or Register with Register
9185 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9186 %{
9187 match(Set dst (OrI dst src));
9188 effect(KILL cr);
9189
9190 format %{ "orl $dst, $src\t# int" %}
9191 opcode(0x0B);
9192 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9193 ins_pipe(ialu_reg_reg);
9194 %}
9195
9196 // Or Register with Immediate
9197 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9198 %{
9199 match(Set dst (OrI dst src));
9200 effect(KILL cr);
9201
9202 format %{ "orl $dst, $src\t# int" %}
9203 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9204 ins_encode(OpcSErm(dst, src), Con8or32(src));
9205 ins_pipe(ialu_reg);
9206 %}
9207
9208 // Or Register with Memory
9209 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9210 %{
9211 match(Set dst (OrI dst (LoadI src)));
9212 effect(KILL cr);
9213
9214 ins_cost(125);
9215 format %{ "orl $dst, $src\t# int" %}
9216 opcode(0x0B);
9217 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9218 ins_pipe(ialu_reg_mem);
9219 %}
9220
9221 // Or Memory with Register
9222 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9223 %{
9224 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9225 effect(KILL cr);
9226
9227 ins_cost(150);
9228 format %{ "orl $dst, $src\t# int" %}
9229 opcode(0x09); /* Opcode 09 /r */
9230 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9231 ins_pipe(ialu_mem_reg);
9232 %}
9233
9234 // Or Memory with Immediate
9235 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9236 %{
9237 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9238 effect(KILL cr);
9239
9240 ins_cost(125);
9241 format %{ "orl $dst, $src\t# int" %}
9242 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9243 ins_encode(REX_mem(dst), OpcSE(src),
9244 RM_opc_mem(secondary, dst), Con8or32(src));
9245 ins_pipe(ialu_mem_imm);
9246 %}
9247
9248 // Xor Instructions
9249 // Xor Register with Register
9250 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9251 %{
9252 match(Set dst (XorI dst src));
9253 effect(KILL cr);
9254
9255 format %{ "xorl $dst, $src\t# int" %}
9256 opcode(0x33);
9257 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9258 ins_pipe(ialu_reg_reg);
9259 %}
9260
9261 // Xor Register with Immediate -1
9262 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9263 match(Set dst (XorI dst imm));
9264
9265 format %{ "not $dst" %}
9266 ins_encode %{
9267 __ notl($dst$$Register);
9268 %}
9269 ins_pipe(ialu_reg);
9270 %}
9271
9272 // Xor Register with Immediate
9273 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9274 %{
9275 match(Set dst (XorI dst src));
9276 effect(KILL cr);
9277
9278 format %{ "xorl $dst, $src\t# int" %}
9279 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9280 ins_encode(OpcSErm(dst, src), Con8or32(src));
9281 ins_pipe(ialu_reg);
9282 %}
9283
9284 // Xor Register with Memory
9285 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9286 %{
9287 match(Set dst (XorI dst (LoadI src)));
9288 effect(KILL cr);
9289
9290 ins_cost(125);
9291 format %{ "xorl $dst, $src\t# int" %}
9292 opcode(0x33);
9293 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9294 ins_pipe(ialu_reg_mem);
9295 %}
9296
9297 // Xor Memory with Register
9298 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9299 %{
9300 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9301 effect(KILL cr);
9302
9303 ins_cost(150);
9304 format %{ "xorl $dst, $src\t# int" %}
9305 opcode(0x31); /* Opcode 31 /r */
9306 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9307 ins_pipe(ialu_mem_reg);
9308 %}
9309
9310 // Xor Memory with Immediate
9311 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9312 %{
9313 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9314 effect(KILL cr);
9315
9316 ins_cost(125);
9317 format %{ "xorl $dst, $src\t# int" %}
9318 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9319 ins_encode(REX_mem(dst), OpcSE(src),
9320 RM_opc_mem(secondary, dst), Con8or32(src));
9321 ins_pipe(ialu_mem_imm);
9322 %}
9323
9324
9325 // Long Logical Instructions
9326
9327 // And Instructions
9328 // And Register with Register
9329 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9330 %{
9331 match(Set dst (AndL dst src));
9332 effect(KILL cr);
9333
9334 format %{ "andq $dst, $src\t# long" %}
9335 opcode(0x23);
9336 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9337 ins_pipe(ialu_reg_reg);
9338 %}
9339
9340 // And Register with Immediate 255
9341 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9342 %{
9343 match(Set dst (AndL dst src));
9344
9345 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9346 opcode(0x0F, 0xB6);
9347 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9348 ins_pipe(ialu_reg);
9349 %}
9350
9351 // And Register with Immediate 65535
9352 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9353 %{
9354 match(Set dst (AndL dst src));
9355
9356 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9357 opcode(0x0F, 0xB7);
9358 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9359 ins_pipe(ialu_reg);
9360 %}
9361
9362 // And Register with Immediate
9363 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9364 %{
9365 match(Set dst (AndL dst src));
9366 effect(KILL cr);
9367
9368 format %{ "andq $dst, $src\t# long" %}
9369 opcode(0x81, 0x04); /* Opcode 81 /4 */
9370 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9371 ins_pipe(ialu_reg);
9372 %}
9373
9374 // And Register with Memory
9375 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9376 %{
9377 match(Set dst (AndL dst (LoadL src)));
9378 effect(KILL cr);
9379
9380 ins_cost(125);
9381 format %{ "andq $dst, $src\t# long" %}
9382 opcode(0x23);
9383 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9384 ins_pipe(ialu_reg_mem);
9385 %}
9386
9387 // And Memory with Register
9388 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9389 %{
9390 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9391 effect(KILL cr);
9392
9393 ins_cost(150);
9394 format %{ "andq $dst, $src\t# long" %}
9395 opcode(0x21); /* Opcode 21 /r */
9396 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9397 ins_pipe(ialu_mem_reg);
9398 %}
9399
9400 // And Memory with Immediate
9401 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9402 %{
9403 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9404 effect(KILL cr);
9405
9406 ins_cost(125);
9407 format %{ "andq $dst, $src\t# long" %}
9408 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9409 ins_encode(REX_mem_wide(dst), OpcSE(src),
9410 RM_opc_mem(secondary, dst), Con8or32(src));
9411 ins_pipe(ialu_mem_imm);
9412 %}
9413
9414 // BMI1 instructions
9415 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9416 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9417 predicate(UseBMI1Instructions);
9418 effect(KILL cr);
9419
9420 ins_cost(125);
9421 format %{ "andnq $dst, $src1, $src2" %}
9422
9423 ins_encode %{
9424 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9425 %}
9426 ins_pipe(ialu_reg_mem);
9427 %}
9428
9429 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9430 match(Set dst (AndL (XorL src1 minus_1) src2));
9431 predicate(UseBMI1Instructions);
9432 effect(KILL cr);
9433
9434 format %{ "andnq $dst, $src1, $src2" %}
9435
9436 ins_encode %{
9437 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9438 %}
9439 ins_pipe(ialu_reg_mem);
9440 %}
9441
9442 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9443 match(Set dst (AndL (SubL imm_zero src) src));
9444 predicate(UseBMI1Instructions);
9445 effect(KILL cr);
9446
9447 format %{ "blsiq $dst, $src" %}
9448
9449 ins_encode %{
9450 __ blsiq($dst$$Register, $src$$Register);
9451 %}
9452 ins_pipe(ialu_reg);
9453 %}
9454
9455 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9456 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9457 predicate(UseBMI1Instructions);
9458 effect(KILL cr);
9459
9460 ins_cost(125);
9461 format %{ "blsiq $dst, $src" %}
9462
9463 ins_encode %{
9464 __ blsiq($dst$$Register, $src$$Address);
9465 %}
9466 ins_pipe(ialu_reg_mem);
9467 %}
9468
9469 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9470 %{
9471 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9472 predicate(UseBMI1Instructions);
9473 effect(KILL cr);
9474
9475 ins_cost(125);
9476 format %{ "blsmskq $dst, $src" %}
9477
9478 ins_encode %{
9479 __ blsmskq($dst$$Register, $src$$Address);
9480 %}
9481 ins_pipe(ialu_reg_mem);
9482 %}
9483
9484 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9485 %{
9486 match(Set dst (XorL (AddL src minus_1) src));
9487 predicate(UseBMI1Instructions);
9488 effect(KILL cr);
9489
9490 format %{ "blsmskq $dst, $src" %}
9491
9492 ins_encode %{
9493 __ blsmskq($dst$$Register, $src$$Register);
9494 %}
9495
9496 ins_pipe(ialu_reg);
9497 %}
9498
9499 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9500 %{
9501 match(Set dst (AndL (AddL src minus_1) src) );
9502 predicate(UseBMI1Instructions);
9503 effect(KILL cr);
9504
9505 format %{ "blsrq $dst, $src" %}
9506
9507 ins_encode %{
9508 __ blsrq($dst$$Register, $src$$Register);
9509 %}
9510
9511 ins_pipe(ialu_reg);
9512 %}
9513
9514 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9515 %{
9516 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9517 predicate(UseBMI1Instructions);
9518 effect(KILL cr);
9519
9520 ins_cost(125);
9521 format %{ "blsrq $dst, $src" %}
9522
9523 ins_encode %{
9524 __ blsrq($dst$$Register, $src$$Address);
9525 %}
9526
9527 ins_pipe(ialu_reg);
9528 %}
9529
9530 // Or Instructions
9531 // Or Register with Register
9532 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9533 %{
9534 match(Set dst (OrL dst src));
9535 effect(KILL cr);
9536
9537 format %{ "orq $dst, $src\t# long" %}
9538 opcode(0x0B);
9539 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9540 ins_pipe(ialu_reg_reg);
9541 %}
9542
9543 // Use any_RegP to match R15 (TLS register) without spilling.
9544 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9545 match(Set dst (OrL dst (CastP2X src)));
9546 effect(KILL cr);
9547
9548 format %{ "orq $dst, $src\t# long" %}
9549 opcode(0x0B);
9550 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9551 ins_pipe(ialu_reg_reg);
9552 %}
9553
9554
9555 // Or Register with Immediate
9556 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9557 %{
9558 match(Set dst (OrL dst src));
9559 effect(KILL cr);
9560
9561 format %{ "orq $dst, $src\t# long" %}
9562 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9563 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9564 ins_pipe(ialu_reg);
9565 %}
9566
9567 // Or Register with Memory
9568 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9569 %{
9570 match(Set dst (OrL dst (LoadL src)));
9571 effect(KILL cr);
9572
9573 ins_cost(125);
9574 format %{ "orq $dst, $src\t# long" %}
9575 opcode(0x0B);
9576 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9577 ins_pipe(ialu_reg_mem);
9578 %}
9579
9580 // Or Memory with Register
9581 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9582 %{
9583 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9584 effect(KILL cr);
9585
9586 ins_cost(150);
9587 format %{ "orq $dst, $src\t# long" %}
9588 opcode(0x09); /* Opcode 09 /r */
9589 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9590 ins_pipe(ialu_mem_reg);
9591 %}
9592
9593 // Or Memory with Immediate
9594 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9595 %{
9596 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9597 effect(KILL cr);
9598
9599 ins_cost(125);
9600 format %{ "orq $dst, $src\t# long" %}
9601 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9602 ins_encode(REX_mem_wide(dst), OpcSE(src),
9603 RM_opc_mem(secondary, dst), Con8or32(src));
9604 ins_pipe(ialu_mem_imm);
9605 %}
9606
9607 // Xor Instructions
9608 // Xor Register with Register
9609 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9610 %{
9611 match(Set dst (XorL dst src));
9612 effect(KILL cr);
9613
9614 format %{ "xorq $dst, $src\t# long" %}
9615 opcode(0x33);
9616 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9617 ins_pipe(ialu_reg_reg);
9618 %}
9619
9620 // Xor Register with Immediate -1
9621 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9622 match(Set dst (XorL dst imm));
9623
9624 format %{ "notq $dst" %}
9625 ins_encode %{
9626 __ notq($dst$$Register);
9627 %}
9628 ins_pipe(ialu_reg);
9629 %}
9630
9631 // Xor Register with Immediate
9632 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9633 %{
9634 match(Set dst (XorL dst src));
9635 effect(KILL cr);
9636
9637 format %{ "xorq $dst, $src\t# long" %}
9638 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9639 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9640 ins_pipe(ialu_reg);
9641 %}
9642
9643 // Xor Register with Memory
9644 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9645 %{
9646 match(Set dst (XorL dst (LoadL src)));
9647 effect(KILL cr);
9648
9649 ins_cost(125);
9650 format %{ "xorq $dst, $src\t# long" %}
9651 opcode(0x33);
9652 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9653 ins_pipe(ialu_reg_mem);
9654 %}
9655
9656 // Xor Memory with Register
9657 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9658 %{
9659 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9660 effect(KILL cr);
9661
9662 ins_cost(150);
9663 format %{ "xorq $dst, $src\t# long" %}
9664 opcode(0x31); /* Opcode 31 /r */
9665 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9666 ins_pipe(ialu_mem_reg);
9667 %}
9668
9669 // Xor Memory with Immediate
9670 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9671 %{
9672 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9673 effect(KILL cr);
9674
9675 ins_cost(125);
9676 format %{ "xorq $dst, $src\t# long" %}
9677 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9678 ins_encode(REX_mem_wide(dst), OpcSE(src),
9679 RM_opc_mem(secondary, dst), Con8or32(src));
9680 ins_pipe(ialu_mem_imm);
9681 %}
9682
9683 // Convert Int to Boolean
9684 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9685 %{
9686 match(Set dst (Conv2B src));
9687 effect(KILL cr);
9688
9689 format %{ "testl $src, $src\t# ci2b\n\t"
9690 "setnz $dst\n\t"
9691 "movzbl $dst, $dst" %}
9692 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9693 setNZ_reg(dst),
9694 REX_reg_breg(dst, dst), // movzbl
9695 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9696 ins_pipe(pipe_slow); // XXX
9697 %}
9698
9699 // Convert Pointer to Boolean
9700 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9701 %{
9702 match(Set dst (Conv2B src));
9703 effect(KILL cr);
9704
9705 format %{ "testq $src, $src\t# cp2b\n\t"
9706 "setnz $dst\n\t"
9707 "movzbl $dst, $dst" %}
9708 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9709 setNZ_reg(dst),
9710 REX_reg_breg(dst, dst), // movzbl
9711 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9712 ins_pipe(pipe_slow); // XXX
9713 %}
9714
9715 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9716 %{
9717 match(Set dst (CmpLTMask p q));
9718 effect(KILL cr);
9719
9720 ins_cost(400);
9721 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9722 "setlt $dst\n\t"
9723 "movzbl $dst, $dst\n\t"
9724 "negl $dst" %}
9725 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9726 setLT_reg(dst),
9727 REX_reg_breg(dst, dst), // movzbl
9728 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9729 neg_reg(dst));
9730 ins_pipe(pipe_slow);
9731 %}
9732
9733 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9734 %{
9735 match(Set dst (CmpLTMask dst zero));
9736 effect(KILL cr);
9737
9738 ins_cost(100);
9739 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9740 ins_encode %{
9741 __ sarl($dst$$Register, 31);
9742 %}
9743 ins_pipe(ialu_reg);
9744 %}
9745
9746 /* Better to save a register than avoid a branch */
9747 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9748 %{
9749 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9750 effect(KILL cr);
9751 ins_cost(300);
9752 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9753 "jge done\n\t"
9754 "addl $p,$y\n"
9755 "done: " %}
9756 ins_encode %{
9757 Register Rp = $p$$Register;
9758 Register Rq = $q$$Register;
9759 Register Ry = $y$$Register;
9760 Label done;
9761 __ subl(Rp, Rq);
9762 __ jccb(Assembler::greaterEqual, done);
9763 __ addl(Rp, Ry);
9764 __ bind(done);
9765 %}
9766 ins_pipe(pipe_cmplt);
9767 %}
9768
9769 /* Better to save a register than avoid a branch */
9770 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9771 %{
9772 match(Set y (AndI (CmpLTMask p q) y));
9773 effect(KILL cr);
9774
9775 ins_cost(300);
9776
9777 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9778 "jlt done\n\t"
9779 "xorl $y, $y\n"
9780 "done: " %}
9781 ins_encode %{
9782 Register Rp = $p$$Register;
9783 Register Rq = $q$$Register;
9784 Register Ry = $y$$Register;
9785 Label done;
9786 __ cmpl(Rp, Rq);
9787 __ jccb(Assembler::less, done);
9788 __ xorl(Ry, Ry);
9789 __ bind(done);
9790 %}
9791 ins_pipe(pipe_cmplt);
9792 %}
9793
9794
9795 //---------- FP Instructions------------------------------------------------
9796
9797 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9798 %{
9799 match(Set cr (CmpF src1 src2));
9800
9801 ins_cost(145);
9802 format %{ "ucomiss $src1, $src2\n\t"
9803 "jnp,s exit\n\t"
9804 "pushfq\t# saw NaN, set CF\n\t"
9805 "andq [rsp], #0xffffff2b\n\t"
9806 "popfq\n"
9807 "exit:" %}
9808 ins_encode %{
9809 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9810 emit_cmpfp_fixup(_masm);
9811 %}
9812 ins_pipe(pipe_slow);
9813 %}
9814
9815 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9816 match(Set cr (CmpF src1 src2));
9817
9818 ins_cost(100);
9819 format %{ "ucomiss $src1, $src2" %}
9820 ins_encode %{
9821 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9822 %}
9823 ins_pipe(pipe_slow);
9824 %}
9825
9826 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9827 %{
9828 match(Set cr (CmpF src1 (LoadF src2)));
9829
9830 ins_cost(145);
9831 format %{ "ucomiss $src1, $src2\n\t"
9832 "jnp,s exit\n\t"
9833 "pushfq\t# saw NaN, set CF\n\t"
9834 "andq [rsp], #0xffffff2b\n\t"
9835 "popfq\n"
9836 "exit:" %}
9837 ins_encode %{
9838 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9839 emit_cmpfp_fixup(_masm);
9840 %}
9841 ins_pipe(pipe_slow);
9842 %}
9843
9844 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9845 match(Set cr (CmpF src1 (LoadF src2)));
9846
9847 ins_cost(100);
9848 format %{ "ucomiss $src1, $src2" %}
9849 ins_encode %{
9850 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9851 %}
9852 ins_pipe(pipe_slow);
9853 %}
9854
9855 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9856 match(Set cr (CmpF src con));
9857
9858 ins_cost(145);
9859 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9860 "jnp,s exit\n\t"
9861 "pushfq\t# saw NaN, set CF\n\t"
9862 "andq [rsp], #0xffffff2b\n\t"
9863 "popfq\n"
9864 "exit:" %}
9865 ins_encode %{
9866 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9867 emit_cmpfp_fixup(_masm);
9868 %}
9869 ins_pipe(pipe_slow);
9870 %}
9871
9872 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9873 match(Set cr (CmpF src con));
9874 ins_cost(100);
9875 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9876 ins_encode %{
9877 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9878 %}
9879 ins_pipe(pipe_slow);
9880 %}
9881
9882 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9883 %{
9884 match(Set cr (CmpD src1 src2));
9885
9886 ins_cost(145);
9887 format %{ "ucomisd $src1, $src2\n\t"
9888 "jnp,s exit\n\t"
9889 "pushfq\t# saw NaN, set CF\n\t"
9890 "andq [rsp], #0xffffff2b\n\t"
9891 "popfq\n"
9892 "exit:" %}
9893 ins_encode %{
9894 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9895 emit_cmpfp_fixup(_masm);
9896 %}
9897 ins_pipe(pipe_slow);
9898 %}
9899
9900 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9901 match(Set cr (CmpD src1 src2));
9902
9903 ins_cost(100);
9904 format %{ "ucomisd $src1, $src2 test" %}
9905 ins_encode %{
9906 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9907 %}
9908 ins_pipe(pipe_slow);
9909 %}
9910
9911 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9912 %{
9913 match(Set cr (CmpD src1 (LoadD src2)));
9914
9915 ins_cost(145);
9916 format %{ "ucomisd $src1, $src2\n\t"
9917 "jnp,s exit\n\t"
9918 "pushfq\t# saw NaN, set CF\n\t"
9919 "andq [rsp], #0xffffff2b\n\t"
9920 "popfq\n"
9921 "exit:" %}
9922 ins_encode %{
9923 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9924 emit_cmpfp_fixup(_masm);
9925 %}
9926 ins_pipe(pipe_slow);
9927 %}
9928
9929 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9930 match(Set cr (CmpD src1 (LoadD src2)));
9931
9932 ins_cost(100);
9933 format %{ "ucomisd $src1, $src2" %}
9934 ins_encode %{
9935 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9936 %}
9937 ins_pipe(pipe_slow);
9938 %}
9939
9940 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9941 match(Set cr (CmpD src con));
9942
9943 ins_cost(145);
9944 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9945 "jnp,s exit\n\t"
9946 "pushfq\t# saw NaN, set CF\n\t"
9947 "andq [rsp], #0xffffff2b\n\t"
9948 "popfq\n"
9949 "exit:" %}
9950 ins_encode %{
9951 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9952 emit_cmpfp_fixup(_masm);
9953 %}
9954 ins_pipe(pipe_slow);
9955 %}
9956
9957 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9958 match(Set cr (CmpD src con));
9959 ins_cost(100);
9960 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9961 ins_encode %{
9962 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9963 %}
9964 ins_pipe(pipe_slow);
9965 %}
9966
9967 // Compare into -1,0,1
9968 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9969 %{
9970 match(Set dst (CmpF3 src1 src2));
9971 effect(KILL cr);
9972
9973 ins_cost(275);
9974 format %{ "ucomiss $src1, $src2\n\t"
9975 "movl $dst, #-1\n\t"
9976 "jp,s done\n\t"
9977 "jb,s done\n\t"
9978 "setne $dst\n\t"
9979 "movzbl $dst, $dst\n"
9980 "done:" %}
9981 ins_encode %{
9982 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9983 emit_cmpfp3(_masm, $dst$$Register);
9984 %}
9985 ins_pipe(pipe_slow);
9986 %}
9987
9988 // Compare into -1,0,1
9989 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9990 %{
9991 match(Set dst (CmpF3 src1 (LoadF src2)));
9992 effect(KILL cr);
9993
9994 ins_cost(275);
9995 format %{ "ucomiss $src1, $src2\n\t"
9996 "movl $dst, #-1\n\t"
9997 "jp,s done\n\t"
9998 "jb,s done\n\t"
9999 "setne $dst\n\t"
10000 "movzbl $dst, $dst\n"
10001 "done:" %}
10002 ins_encode %{
10003 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10004 emit_cmpfp3(_masm, $dst$$Register);
10005 %}
10006 ins_pipe(pipe_slow);
10007 %}
10008
10009 // Compare into -1,0,1
10010 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10011 match(Set dst (CmpF3 src con));
10012 effect(KILL cr);
10013
10014 ins_cost(275);
10015 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10016 "movl $dst, #-1\n\t"
10017 "jp,s done\n\t"
10018 "jb,s done\n\t"
10019 "setne $dst\n\t"
10020 "movzbl $dst, $dst\n"
10021 "done:" %}
10022 ins_encode %{
10023 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10024 emit_cmpfp3(_masm, $dst$$Register);
10025 %}
10026 ins_pipe(pipe_slow);
10027 %}
10028
10029 // Compare into -1,0,1
10030 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10031 %{
10032 match(Set dst (CmpD3 src1 src2));
10033 effect(KILL cr);
10034
10035 ins_cost(275);
10036 format %{ "ucomisd $src1, $src2\n\t"
10037 "movl $dst, #-1\n\t"
10038 "jp,s done\n\t"
10039 "jb,s done\n\t"
10040 "setne $dst\n\t"
10041 "movzbl $dst, $dst\n"
10042 "done:" %}
10043 ins_encode %{
10044 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10045 emit_cmpfp3(_masm, $dst$$Register);
10046 %}
10047 ins_pipe(pipe_slow);
10048 %}
10049
10050 // Compare into -1,0,1
10051 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10052 %{
10053 match(Set dst (CmpD3 src1 (LoadD src2)));
10054 effect(KILL cr);
10055
10056 ins_cost(275);
10057 format %{ "ucomisd $src1, $src2\n\t"
10058 "movl $dst, #-1\n\t"
10059 "jp,s done\n\t"
10060 "jb,s done\n\t"
10061 "setne $dst\n\t"
10062 "movzbl $dst, $dst\n"
10063 "done:" %}
10064 ins_encode %{
10065 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10066 emit_cmpfp3(_masm, $dst$$Register);
10067 %}
10068 ins_pipe(pipe_slow);
10069 %}
10070
10071 // Compare into -1,0,1
10072 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10073 match(Set dst (CmpD3 src con));
10074 effect(KILL cr);
10075
10076 ins_cost(275);
10077 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10078 "movl $dst, #-1\n\t"
10079 "jp,s done\n\t"
10080 "jb,s done\n\t"
10081 "setne $dst\n\t"
10082 "movzbl $dst, $dst\n"
10083 "done:" %}
10084 ins_encode %{
10085 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10086 emit_cmpfp3(_masm, $dst$$Register);
10087 %}
10088 ins_pipe(pipe_slow);
10089 %}
10090
10091 //----------Arithmetic Conversion Instructions---------------------------------
10092
10093 instruct roundFloat_nop(regF dst)
10094 %{
10095 match(Set dst (RoundFloat dst));
10096
10097 ins_cost(0);
10098 ins_encode();
10099 ins_pipe(empty);
10100 %}
10101
10102 instruct roundDouble_nop(regD dst)
10103 %{
10104 match(Set dst (RoundDouble dst));
10105
10106 ins_cost(0);
10107 ins_encode();
10108 ins_pipe(empty);
10109 %}
10110
10111 instruct convF2D_reg_reg(regD dst, regF src)
10112 %{
10113 match(Set dst (ConvF2D src));
10114
10115 format %{ "cvtss2sd $dst, $src" %}
10116 ins_encode %{
10117 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10118 %}
10119 ins_pipe(pipe_slow); // XXX
10120 %}
10121
10122 instruct convF2D_reg_mem(regD dst, memory src)
10123 %{
10124 match(Set dst (ConvF2D (LoadF src)));
10125
10126 format %{ "cvtss2sd $dst, $src" %}
10127 ins_encode %{
10128 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10129 %}
10130 ins_pipe(pipe_slow); // XXX
10131 %}
10132
10133 instruct convD2F_reg_reg(regF dst, regD src)
10134 %{
10135 match(Set dst (ConvD2F src));
10136
10137 format %{ "cvtsd2ss $dst, $src" %}
10138 ins_encode %{
10139 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10140 %}
10141 ins_pipe(pipe_slow); // XXX
10142 %}
10143
10144 instruct convD2F_reg_mem(regF dst, memory src)
10145 %{
10146 match(Set dst (ConvD2F (LoadD src)));
10147
10148 format %{ "cvtsd2ss $dst, $src" %}
10149 ins_encode %{
10150 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10151 %}
10152 ins_pipe(pipe_slow); // XXX
10153 %}
10154
10155 // XXX do mem variants
10156 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10157 %{
10158 match(Set dst (ConvF2I src));
10159 effect(KILL cr);
10160
10161 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10162 "cmpl $dst, #0x80000000\n\t"
10163 "jne,s done\n\t"
10164 "subq rsp, #8\n\t"
10165 "movss [rsp], $src\n\t"
10166 "call f2i_fixup\n\t"
10167 "popq $dst\n"
10168 "done: "%}
10169 ins_encode %{
10170 Label done;
10171 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10172 __ cmpl($dst$$Register, 0x80000000);
10173 __ jccb(Assembler::notEqual, done);
10174 __ subptr(rsp, 8);
10175 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10176 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10177 __ pop($dst$$Register);
10178 __ bind(done);
10179 %}
10180 ins_pipe(pipe_slow);
10181 %}
10182
10183 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10184 %{
10185 match(Set dst (ConvF2L src));
10186 effect(KILL cr);
10187
10188 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10189 "cmpq $dst, [0x8000000000000000]\n\t"
10190 "jne,s done\n\t"
10191 "subq rsp, #8\n\t"
10192 "movss [rsp], $src\n\t"
10193 "call f2l_fixup\n\t"
10194 "popq $dst\n"
10195 "done: "%}
10196 ins_encode %{
10197 Label done;
10198 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10199 __ cmp64($dst$$Register,
10200 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10201 __ jccb(Assembler::notEqual, done);
10202 __ subptr(rsp, 8);
10203 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10204 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10205 __ pop($dst$$Register);
10206 __ bind(done);
10207 %}
10208 ins_pipe(pipe_slow);
10209 %}
10210
10211 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10212 %{
10213 match(Set dst (ConvD2I src));
10214 effect(KILL cr);
10215
10216 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10217 "cmpl $dst, #0x80000000\n\t"
10218 "jne,s done\n\t"
10219 "subq rsp, #8\n\t"
10220 "movsd [rsp], $src\n\t"
10221 "call d2i_fixup\n\t"
10222 "popq $dst\n"
10223 "done: "%}
10224 ins_encode %{
10225 Label done;
10226 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10227 __ cmpl($dst$$Register, 0x80000000);
10228 __ jccb(Assembler::notEqual, done);
10229 __ subptr(rsp, 8);
10230 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10231 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10232 __ pop($dst$$Register);
10233 __ bind(done);
10234 %}
10235 ins_pipe(pipe_slow);
10236 %}
10237
10238 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10239 %{
10240 match(Set dst (ConvD2L src));
10241 effect(KILL cr);
10242
10243 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10244 "cmpq $dst, [0x8000000000000000]\n\t"
10245 "jne,s done\n\t"
10246 "subq rsp, #8\n\t"
10247 "movsd [rsp], $src\n\t"
10248 "call d2l_fixup\n\t"
10249 "popq $dst\n"
10250 "done: "%}
10251 ins_encode %{
10252 Label done;
10253 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10254 __ cmp64($dst$$Register,
10255 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10256 __ jccb(Assembler::notEqual, done);
10257 __ subptr(rsp, 8);
10258 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10259 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10260 __ pop($dst$$Register);
10261 __ bind(done);
10262 %}
10263 ins_pipe(pipe_slow);
10264 %}
10265
10266 instruct convI2F_reg_reg(regF dst, rRegI src)
10267 %{
10268 predicate(!UseXmmI2F);
10269 match(Set dst (ConvI2F src));
10270
10271 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10272 ins_encode %{
10273 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10274 %}
10275 ins_pipe(pipe_slow); // XXX
10276 %}
10277
10278 instruct convI2F_reg_mem(regF dst, memory src)
10279 %{
10280 match(Set dst (ConvI2F (LoadI src)));
10281
10282 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10283 ins_encode %{
10284 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10285 %}
10286 ins_pipe(pipe_slow); // XXX
10287 %}
10288
10289 instruct convI2D_reg_reg(regD dst, rRegI src)
10290 %{
10291 predicate(!UseXmmI2D);
10292 match(Set dst (ConvI2D src));
10293
10294 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10295 ins_encode %{
10296 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10297 %}
10298 ins_pipe(pipe_slow); // XXX
10299 %}
10300
10301 instruct convI2D_reg_mem(regD dst, memory src)
10302 %{
10303 match(Set dst (ConvI2D (LoadI src)));
10304
10305 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10306 ins_encode %{
10307 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10308 %}
10309 ins_pipe(pipe_slow); // XXX
10310 %}
10311
10312 instruct convXI2F_reg(regF dst, rRegI src)
10313 %{
10314 predicate(UseXmmI2F);
10315 match(Set dst (ConvI2F src));
10316
10317 format %{ "movdl $dst, $src\n\t"
10318 "cvtdq2psl $dst, $dst\t# i2f" %}
10319 ins_encode %{
10320 __ movdl($dst$$XMMRegister, $src$$Register);
10321 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10322 %}
10323 ins_pipe(pipe_slow); // XXX
10324 %}
10325
10326 instruct convXI2D_reg(regD dst, rRegI src)
10327 %{
10328 predicate(UseXmmI2D);
10329 match(Set dst (ConvI2D src));
10330
10331 format %{ "movdl $dst, $src\n\t"
10332 "cvtdq2pdl $dst, $dst\t# i2d" %}
10333 ins_encode %{
10334 __ movdl($dst$$XMMRegister, $src$$Register);
10335 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10336 %}
10337 ins_pipe(pipe_slow); // XXX
10338 %}
10339
10340 instruct convL2F_reg_reg(regF dst, rRegL src)
10341 %{
10342 match(Set dst (ConvL2F src));
10343
10344 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10345 ins_encode %{
10346 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10347 %}
10348 ins_pipe(pipe_slow); // XXX
10349 %}
10350
10351 instruct convL2F_reg_mem(regF dst, memory src)
10352 %{
10353 match(Set dst (ConvL2F (LoadL src)));
10354
10355 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10356 ins_encode %{
10357 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10358 %}
10359 ins_pipe(pipe_slow); // XXX
10360 %}
10361
10362 instruct convL2D_reg_reg(regD dst, rRegL src)
10363 %{
10364 match(Set dst (ConvL2D src));
10365
10366 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10367 ins_encode %{
10368 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10369 %}
10370 ins_pipe(pipe_slow); // XXX
10371 %}
10372
10373 instruct convL2D_reg_mem(regD dst, memory src)
10374 %{
10375 match(Set dst (ConvL2D (LoadL src)));
10376
10377 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10378 ins_encode %{
10379 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10380 %}
10381 ins_pipe(pipe_slow); // XXX
10382 %}
10383
10384 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10385 %{
10386 match(Set dst (ConvI2L src));
10387
10388 ins_cost(125);
10389 format %{ "movslq $dst, $src\t# i2l" %}
10390 ins_encode %{
10391 __ movslq($dst$$Register, $src$$Register);
10392 %}
10393 ins_pipe(ialu_reg_reg);
10394 %}
10395
10396 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10397 // %{
10398 // match(Set dst (ConvI2L src));
10399 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10400 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10401 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10402 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10403 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10404 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10405
10406 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10407 // ins_encode(enc_copy(dst, src));
10408 // // opcode(0x63); // needs REX.W
10409 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10410 // ins_pipe(ialu_reg_reg);
10411 // %}
10412
10413 // Zero-extend convert int to long
10414 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10415 %{
10416 match(Set dst (AndL (ConvI2L src) mask));
10417
10418 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10419 ins_encode %{
10420 if ($dst$$reg != $src$$reg) {
10421 __ movl($dst$$Register, $src$$Register);
10422 }
10423 %}
10424 ins_pipe(ialu_reg_reg);
10425 %}
10426
10427 // Zero-extend convert int to long
10428 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10429 %{
10430 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10431
10432 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10433 ins_encode %{
10434 __ movl($dst$$Register, $src$$Address);
10435 %}
10436 ins_pipe(ialu_reg_mem);
10437 %}
10438
10439 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10440 %{
10441 match(Set dst (AndL src mask));
10442
10443 format %{ "movl $dst, $src\t# zero-extend long" %}
10444 ins_encode %{
10445 __ movl($dst$$Register, $src$$Register);
10446 %}
10447 ins_pipe(ialu_reg_reg);
10448 %}
10449
10450 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10451 %{
10452 match(Set dst (ConvL2I src));
10453
10454 format %{ "movl $dst, $src\t# l2i" %}
10455 ins_encode %{
10456 __ movl($dst$$Register, $src$$Register);
10457 %}
10458 ins_pipe(ialu_reg_reg);
10459 %}
10460
10461
10462 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10463 match(Set dst (MoveF2I src));
10464 effect(DEF dst, USE src);
10465
10466 ins_cost(125);
10467 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10468 ins_encode %{
10469 __ movl($dst$$Register, Address(rsp, $src$$disp));
10470 %}
10471 ins_pipe(ialu_reg_mem);
10472 %}
10473
10474 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10475 match(Set dst (MoveI2F src));
10476 effect(DEF dst, USE src);
10477
10478 ins_cost(125);
10479 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10480 ins_encode %{
10481 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10482 %}
10483 ins_pipe(pipe_slow);
10484 %}
10485
10486 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10487 match(Set dst (MoveD2L src));
10488 effect(DEF dst, USE src);
10489
10490 ins_cost(125);
10491 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10492 ins_encode %{
10493 __ movq($dst$$Register, Address(rsp, $src$$disp));
10494 %}
10495 ins_pipe(ialu_reg_mem);
10496 %}
10497
10498 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10499 predicate(!UseXmmLoadAndClearUpper);
10500 match(Set dst (MoveL2D src));
10501 effect(DEF dst, USE src);
10502
10503 ins_cost(125);
10504 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10505 ins_encode %{
10506 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10507 %}
10508 ins_pipe(pipe_slow);
10509 %}
10510
10511 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10512 predicate(UseXmmLoadAndClearUpper);
10513 match(Set dst (MoveL2D src));
10514 effect(DEF dst, USE src);
10515
10516 ins_cost(125);
10517 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10518 ins_encode %{
10519 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10520 %}
10521 ins_pipe(pipe_slow);
10522 %}
10523
10524
10525 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10526 match(Set dst (MoveF2I src));
10527 effect(DEF dst, USE src);
10528
10529 ins_cost(95); // XXX
10530 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10531 ins_encode %{
10532 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10533 %}
10534 ins_pipe(pipe_slow);
10535 %}
10536
10537 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10538 match(Set dst (MoveI2F src));
10539 effect(DEF dst, USE src);
10540
10541 ins_cost(100);
10542 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10543 ins_encode %{
10544 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10545 %}
10546 ins_pipe( ialu_mem_reg );
10547 %}
10548
10549 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10550 match(Set dst (MoveD2L src));
10551 effect(DEF dst, USE src);
10552
10553 ins_cost(95); // XXX
10554 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10555 ins_encode %{
10556 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10557 %}
10558 ins_pipe(pipe_slow);
10559 %}
10560
10561 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10562 match(Set dst (MoveL2D src));
10563 effect(DEF dst, USE src);
10564
10565 ins_cost(100);
10566 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10567 ins_encode %{
10568 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10569 %}
10570 ins_pipe(ialu_mem_reg);
10571 %}
10572
10573 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10574 match(Set dst (MoveF2I src));
10575 effect(DEF dst, USE src);
10576 ins_cost(85);
10577 format %{ "movd $dst,$src\t# MoveF2I" %}
10578 ins_encode %{
10579 __ movdl($dst$$Register, $src$$XMMRegister);
10580 %}
10581 ins_pipe( pipe_slow );
10582 %}
10583
10584 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10585 match(Set dst (MoveD2L src));
10586 effect(DEF dst, USE src);
10587 ins_cost(85);
10588 format %{ "movd $dst,$src\t# MoveD2L" %}
10589 ins_encode %{
10590 __ movdq($dst$$Register, $src$$XMMRegister);
10591 %}
10592 ins_pipe( pipe_slow );
10593 %}
10594
10595 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10596 match(Set dst (MoveI2F src));
10597 effect(DEF dst, USE src);
10598 ins_cost(100);
10599 format %{ "movd $dst,$src\t# MoveI2F" %}
10600 ins_encode %{
10601 __ movdl($dst$$XMMRegister, $src$$Register);
10602 %}
10603 ins_pipe( pipe_slow );
10604 %}
10605
10606 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10607 match(Set dst (MoveL2D src));
10608 effect(DEF dst, USE src);
10609 ins_cost(100);
10610 format %{ "movd $dst,$src\t# MoveL2D" %}
10611 ins_encode %{
10612 __ movdq($dst$$XMMRegister, $src$$Register);
10613 %}
10614 ins_pipe( pipe_slow );
10615 %}
10616
10617
10618 // =======================================================================
10619 // fast clearing of an array
10620 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10621 rFlagsReg cr)
10622 %{
10623 predicate(!((ClearArrayNode*)n)->is_large());
10624 match(Set dummy (ClearArray cnt base));
10625 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10626
10627 format %{ $$template
10628 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10629 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10630 $$emit$$"jg LARGE\n\t"
10631 $$emit$$"dec rcx\n\t"
10632 $$emit$$"js DONE\t# Zero length\n\t"
10633 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10634 $$emit$$"dec rcx\n\t"
10635 $$emit$$"jge LOOP\n\t"
10636 $$emit$$"jmp DONE\n\t"
10637 $$emit$$"# LARGE:\n\t"
10638 if (UseFastStosb) {
10639 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10640 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10641 } else {
10642 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10643 }
10644 $$emit$$"# DONE"
10645 %}
10646 ins_encode %{
10647 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, false);
10648 %}
10649 ins_pipe(pipe_slow);
10650 %}
10651
10652 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10653 rFlagsReg cr)
10654 %{
10655 predicate(((ClearArrayNode*)n)->is_large());
10656 match(Set dummy (ClearArray cnt base));
10657 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10658
10659 format %{ $$template
10660 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10661 if (UseFastStosb) {
10662 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10663 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10664 } else {
10665 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10666 }
10667 %}
10668 ins_encode %{
10669 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, true);
10670 %}
10671 ins_pipe(pipe_slow);
10672 %}
10673
10674 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10675 rax_RegI result, regD tmp1, rFlagsReg cr)
10676 %{
10677 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10678 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10679 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10680
10681 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10682 ins_encode %{
10683 __ string_compare($str1$$Register, $str2$$Register,
10684 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10685 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10686 %}
10687 ins_pipe( pipe_slow );
10688 %}
10689
10690 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10691 rax_RegI result, regD tmp1, rFlagsReg cr)
10692 %{
10693 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10694 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10695 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10696
10697 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10698 ins_encode %{
10699 __ string_compare($str1$$Register, $str2$$Register,
10700 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10701 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10702 %}
10703 ins_pipe( pipe_slow );
10704 %}
10705
10706 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10707 rax_RegI result, regD tmp1, rFlagsReg cr)
10708 %{
10709 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10710 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10711 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10712
10713 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10714 ins_encode %{
10715 __ string_compare($str1$$Register, $str2$$Register,
10716 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10717 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10718 %}
10719 ins_pipe( pipe_slow );
10720 %}
10721
10722 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10723 rax_RegI result, regD tmp1, rFlagsReg cr)
10724 %{
10725 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10726 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10727 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10728
10729 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10730 ins_encode %{
10731 __ string_compare($str2$$Register, $str1$$Register,
10732 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10733 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10734 %}
10735 ins_pipe( pipe_slow );
10736 %}
10737
10738 // fast search of substring with known size.
10739 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10740 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10741 %{
10742 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10743 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10744 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10745
10746 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10747 ins_encode %{
10748 int icnt2 = (int)$int_cnt2$$constant;
10749 if (icnt2 >= 16) {
10750 // IndexOf for constant substrings with size >= 16 elements
10751 // which don't need to be loaded through stack.
10752 __ string_indexofC8($str1$$Register, $str2$$Register,
10753 $cnt1$$Register, $cnt2$$Register,
10754 icnt2, $result$$Register,
10755 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10756 } else {
10757 // Small strings are loaded through stack if they cross page boundary.
10758 __ string_indexof($str1$$Register, $str2$$Register,
10759 $cnt1$$Register, $cnt2$$Register,
10760 icnt2, $result$$Register,
10761 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10762 }
10763 %}
10764 ins_pipe( pipe_slow );
10765 %}
10766
10767 // fast search of substring with known size.
10768 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10769 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10770 %{
10771 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10772 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10773 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10774
10775 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10776 ins_encode %{
10777 int icnt2 = (int)$int_cnt2$$constant;
10778 if (icnt2 >= 8) {
10779 // IndexOf for constant substrings with size >= 8 elements
10780 // which don't need to be loaded through stack.
10781 __ string_indexofC8($str1$$Register, $str2$$Register,
10782 $cnt1$$Register, $cnt2$$Register,
10783 icnt2, $result$$Register,
10784 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10785 } else {
10786 // Small strings are loaded through stack if they cross page boundary.
10787 __ string_indexof($str1$$Register, $str2$$Register,
10788 $cnt1$$Register, $cnt2$$Register,
10789 icnt2, $result$$Register,
10790 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10791 }
10792 %}
10793 ins_pipe( pipe_slow );
10794 %}
10795
10796 // fast search of substring with known size.
10797 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10798 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10799 %{
10800 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10801 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10802 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10803
10804 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10805 ins_encode %{
10806 int icnt2 = (int)$int_cnt2$$constant;
10807 if (icnt2 >= 8) {
10808 // IndexOf for constant substrings with size >= 8 elements
10809 // which don't need to be loaded through stack.
10810 __ string_indexofC8($str1$$Register, $str2$$Register,
10811 $cnt1$$Register, $cnt2$$Register,
10812 icnt2, $result$$Register,
10813 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10814 } else {
10815 // Small strings are loaded through stack if they cross page boundary.
10816 __ string_indexof($str1$$Register, $str2$$Register,
10817 $cnt1$$Register, $cnt2$$Register,
10818 icnt2, $result$$Register,
10819 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10820 }
10821 %}
10822 ins_pipe( pipe_slow );
10823 %}
10824
10825 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10826 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10827 %{
10828 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10829 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10830 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10831
10832 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10833 ins_encode %{
10834 __ string_indexof($str1$$Register, $str2$$Register,
10835 $cnt1$$Register, $cnt2$$Register,
10836 (-1), $result$$Register,
10837 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10838 %}
10839 ins_pipe( pipe_slow );
10840 %}
10841
10842 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10843 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10844 %{
10845 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10846 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10847 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10848
10849 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10850 ins_encode %{
10851 __ string_indexof($str1$$Register, $str2$$Register,
10852 $cnt1$$Register, $cnt2$$Register,
10853 (-1), $result$$Register,
10854 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10855 %}
10856 ins_pipe( pipe_slow );
10857 %}
10858
10859 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10860 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10861 %{
10862 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10863 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10864 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10865
10866 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10867 ins_encode %{
10868 __ string_indexof($str1$$Register, $str2$$Register,
10869 $cnt1$$Register, $cnt2$$Register,
10870 (-1), $result$$Register,
10871 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10872 %}
10873 ins_pipe( pipe_slow );
10874 %}
10875
10876 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10877 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10878 %{
10879 predicate(UseSSE42Intrinsics);
10880 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10881 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10882 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10883 ins_encode %{
10884 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10885 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10886 %}
10887 ins_pipe( pipe_slow );
10888 %}
10889
10890 // fast string equals
10891 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10892 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10893 %{
10894 match(Set result (StrEquals (Binary str1 str2) cnt));
10895 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10896
10897 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10898 ins_encode %{
10899 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10900 $cnt$$Register, $result$$Register, $tmp3$$Register,
10901 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10902 %}
10903 ins_pipe( pipe_slow );
10904 %}
10905
10906 // fast array equals
10907 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10908 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10909 %{
10910 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10911 match(Set result (AryEq ary1 ary2));
10912 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10913
10914 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10915 ins_encode %{
10916 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10917 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10918 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10919 %}
10920 ins_pipe( pipe_slow );
10921 %}
10922
10923 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10924 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10925 %{
10926 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10927 match(Set result (AryEq ary1 ary2));
10928 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10929
10930 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10931 ins_encode %{
10932 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10933 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10934 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10935 %}
10936 ins_pipe( pipe_slow );
10937 %}
10938
10939 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10940 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10941 %{
10942 match(Set result (HasNegatives ary1 len));
10943 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10944
10945 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10946 ins_encode %{
10947 __ has_negatives($ary1$$Register, $len$$Register,
10948 $result$$Register, $tmp3$$Register,
10949 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 // fast char[] to byte[] compression
10955 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10956 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10957 match(Set result (StrCompressedCopy src (Binary dst len)));
10958 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10959
10960 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10961 ins_encode %{
10962 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10963 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10964 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10965 %}
10966 ins_pipe( pipe_slow );
10967 %}
10968
10969 // fast byte[] to char[] inflation
10970 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10971 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10972 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10973 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10974
10975 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10976 ins_encode %{
10977 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10978 $tmp1$$XMMRegister, $tmp2$$Register);
10979 %}
10980 ins_pipe( pipe_slow );
10981 %}
10982
10983 // encode char[] to byte[] in ISO_8859_1
10984 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10985 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10986 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10987 match(Set result (EncodeISOArray src (Binary dst len)));
10988 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10989
10990 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10991 ins_encode %{
10992 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10993 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10994 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10995 %}
10996 ins_pipe( pipe_slow );
10997 %}
10998
10999 //----------Overflow Math Instructions-----------------------------------------
11000
11001 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11002 %{
11003 match(Set cr (OverflowAddI op1 op2));
11004 effect(DEF cr, USE_KILL op1, USE op2);
11005
11006 format %{ "addl $op1, $op2\t# overflow check int" %}
11007
11008 ins_encode %{
11009 __ addl($op1$$Register, $op2$$Register);
11010 %}
11011 ins_pipe(ialu_reg_reg);
11012 %}
11013
11014 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11015 %{
11016 match(Set cr (OverflowAddI op1 op2));
11017 effect(DEF cr, USE_KILL op1, USE op2);
11018
11019 format %{ "addl $op1, $op2\t# overflow check int" %}
11020
11021 ins_encode %{
11022 __ addl($op1$$Register, $op2$$constant);
11023 %}
11024 ins_pipe(ialu_reg_reg);
11025 %}
11026
11027 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11028 %{
11029 match(Set cr (OverflowAddL op1 op2));
11030 effect(DEF cr, USE_KILL op1, USE op2);
11031
11032 format %{ "addq $op1, $op2\t# overflow check long" %}
11033 ins_encode %{
11034 __ addq($op1$$Register, $op2$$Register);
11035 %}
11036 ins_pipe(ialu_reg_reg);
11037 %}
11038
11039 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11040 %{
11041 match(Set cr (OverflowAddL op1 op2));
11042 effect(DEF cr, USE_KILL op1, USE op2);
11043
11044 format %{ "addq $op1, $op2\t# overflow check long" %}
11045 ins_encode %{
11046 __ addq($op1$$Register, $op2$$constant);
11047 %}
11048 ins_pipe(ialu_reg_reg);
11049 %}
11050
11051 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11052 %{
11053 match(Set cr (OverflowSubI op1 op2));
11054
11055 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11056 ins_encode %{
11057 __ cmpl($op1$$Register, $op2$$Register);
11058 %}
11059 ins_pipe(ialu_reg_reg);
11060 %}
11061
11062 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11063 %{
11064 match(Set cr (OverflowSubI op1 op2));
11065
11066 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11067 ins_encode %{
11068 __ cmpl($op1$$Register, $op2$$constant);
11069 %}
11070 ins_pipe(ialu_reg_reg);
11071 %}
11072
11073 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11074 %{
11075 match(Set cr (OverflowSubL op1 op2));
11076
11077 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11078 ins_encode %{
11079 __ cmpq($op1$$Register, $op2$$Register);
11080 %}
11081 ins_pipe(ialu_reg_reg);
11082 %}
11083
11084 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11085 %{
11086 match(Set cr (OverflowSubL op1 op2));
11087
11088 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11089 ins_encode %{
11090 __ cmpq($op1$$Register, $op2$$constant);
11091 %}
11092 ins_pipe(ialu_reg_reg);
11093 %}
11094
11095 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11096 %{
11097 match(Set cr (OverflowSubI zero op2));
11098 effect(DEF cr, USE_KILL op2);
11099
11100 format %{ "negl $op2\t# overflow check int" %}
11101 ins_encode %{
11102 __ negl($op2$$Register);
11103 %}
11104 ins_pipe(ialu_reg_reg);
11105 %}
11106
11107 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11108 %{
11109 match(Set cr (OverflowSubL zero op2));
11110 effect(DEF cr, USE_KILL op2);
11111
11112 format %{ "negq $op2\t# overflow check long" %}
11113 ins_encode %{
11114 __ negq($op2$$Register);
11115 %}
11116 ins_pipe(ialu_reg_reg);
11117 %}
11118
11119 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11120 %{
11121 match(Set cr (OverflowMulI op1 op2));
11122 effect(DEF cr, USE_KILL op1, USE op2);
11123
11124 format %{ "imull $op1, $op2\t# overflow check int" %}
11125 ins_encode %{
11126 __ imull($op1$$Register, $op2$$Register);
11127 %}
11128 ins_pipe(ialu_reg_reg_alu0);
11129 %}
11130
11131 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11132 %{
11133 match(Set cr (OverflowMulI op1 op2));
11134 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11135
11136 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11137 ins_encode %{
11138 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11139 %}
11140 ins_pipe(ialu_reg_reg_alu0);
11141 %}
11142
11143 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11144 %{
11145 match(Set cr (OverflowMulL op1 op2));
11146 effect(DEF cr, USE_KILL op1, USE op2);
11147
11148 format %{ "imulq $op1, $op2\t# overflow check long" %}
11149 ins_encode %{
11150 __ imulq($op1$$Register, $op2$$Register);
11151 %}
11152 ins_pipe(ialu_reg_reg_alu0);
11153 %}
11154
11155 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11156 %{
11157 match(Set cr (OverflowMulL op1 op2));
11158 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11159
11160 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11161 ins_encode %{
11162 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11163 %}
11164 ins_pipe(ialu_reg_reg_alu0);
11165 %}
11166
11167
11168 //----------Control Flow Instructions------------------------------------------
11169 // Signed compare Instructions
11170
11171 // XXX more variants!!
11172 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11173 %{
11174 match(Set cr (CmpI op1 op2));
11175 effect(DEF cr, USE op1, USE op2);
11176
11177 format %{ "cmpl $op1, $op2" %}
11178 opcode(0x3B); /* Opcode 3B /r */
11179 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11180 ins_pipe(ialu_cr_reg_reg);
11181 %}
11182
11183 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11184 %{
11185 match(Set cr (CmpI op1 op2));
11186
11187 format %{ "cmpl $op1, $op2" %}
11188 opcode(0x81, 0x07); /* Opcode 81 /7 */
11189 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11190 ins_pipe(ialu_cr_reg_imm);
11191 %}
11192
11193 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11194 %{
11195 match(Set cr (CmpI op1 (LoadI op2)));
11196
11197 ins_cost(500); // XXX
11198 format %{ "cmpl $op1, $op2" %}
11199 opcode(0x3B); /* Opcode 3B /r */
11200 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11201 ins_pipe(ialu_cr_reg_mem);
11202 %}
11203
11204 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11205 %{
11206 match(Set cr (CmpI src zero));
11207
11208 format %{ "testl $src, $src" %}
11209 opcode(0x85);
11210 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11211 ins_pipe(ialu_cr_reg_imm);
11212 %}
11213
11214 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11215 %{
11216 match(Set cr (CmpI (AndI src con) zero));
11217
11218 format %{ "testl $src, $con" %}
11219 opcode(0xF7, 0x00);
11220 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11221 ins_pipe(ialu_cr_reg_imm);
11222 %}
11223
11224 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11225 %{
11226 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11227
11228 format %{ "testl $src, $mem" %}
11229 opcode(0x85);
11230 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11231 ins_pipe(ialu_cr_reg_mem);
11232 %}
11233
11234 // Unsigned compare Instructions; really, same as signed except they
11235 // produce an rFlagsRegU instead of rFlagsReg.
11236 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11237 %{
11238 match(Set cr (CmpU op1 op2));
11239
11240 format %{ "cmpl $op1, $op2\t# unsigned" %}
11241 opcode(0x3B); /* Opcode 3B /r */
11242 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11243 ins_pipe(ialu_cr_reg_reg);
11244 %}
11245
11246 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11247 %{
11248 match(Set cr (CmpU op1 op2));
11249
11250 format %{ "cmpl $op1, $op2\t# unsigned" %}
11251 opcode(0x81,0x07); /* Opcode 81 /7 */
11252 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11253 ins_pipe(ialu_cr_reg_imm);
11254 %}
11255
11256 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11257 %{
11258 match(Set cr (CmpU op1 (LoadI op2)));
11259
11260 ins_cost(500); // XXX
11261 format %{ "cmpl $op1, $op2\t# unsigned" %}
11262 opcode(0x3B); /* Opcode 3B /r */
11263 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11264 ins_pipe(ialu_cr_reg_mem);
11265 %}
11266
11267 // // // Cisc-spilled version of cmpU_rReg
11268 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11269 // //%{
11270 // // match(Set cr (CmpU (LoadI op1) op2));
11271 // //
11272 // // format %{ "CMPu $op1,$op2" %}
11273 // // ins_cost(500);
11274 // // opcode(0x39); /* Opcode 39 /r */
11275 // // ins_encode( OpcP, reg_mem( op1, op2) );
11276 // //%}
11277
11278 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11279 %{
11280 match(Set cr (CmpU src zero));
11281
11282 format %{ "testl $src, $src\t# unsigned" %}
11283 opcode(0x85);
11284 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11285 ins_pipe(ialu_cr_reg_imm);
11286 %}
11287
11288 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11289 %{
11290 match(Set cr (CmpP op1 op2));
11291
11292 format %{ "cmpq $op1, $op2\t# ptr" %}
11293 opcode(0x3B); /* Opcode 3B /r */
11294 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11295 ins_pipe(ialu_cr_reg_reg);
11296 %}
11297
11298 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11299 %{
11300 match(Set cr (CmpP op1 (LoadP op2)));
11301
11302 ins_cost(500); // XXX
11303 format %{ "cmpq $op1, $op2\t# ptr" %}
11304 opcode(0x3B); /* Opcode 3B /r */
11305 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11306 ins_pipe(ialu_cr_reg_mem);
11307 %}
11308
11309 // // // Cisc-spilled version of cmpP_rReg
11310 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11311 // //%{
11312 // // match(Set cr (CmpP (LoadP op1) op2));
11313 // //
11314 // // format %{ "CMPu $op1,$op2" %}
11315 // // ins_cost(500);
11316 // // opcode(0x39); /* Opcode 39 /r */
11317 // // ins_encode( OpcP, reg_mem( op1, op2) );
11318 // //%}
11319
11320 // XXX this is generalized by compP_rReg_mem???
11321 // Compare raw pointer (used in out-of-heap check).
11322 // Only works because non-oop pointers must be raw pointers
11323 // and raw pointers have no anti-dependencies.
11324 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11325 %{
11326 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11327 match(Set cr (CmpP op1 (LoadP op2)));
11328
11329 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11330 opcode(0x3B); /* Opcode 3B /r */
11331 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11332 ins_pipe(ialu_cr_reg_mem);
11333 %}
11334
11335 // This will generate a signed flags result. This should be OK since
11336 // any compare to a zero should be eq/neq.
11337 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11338 %{
11339 match(Set cr (CmpP src zero));
11340
11341 format %{ "testq $src, $src\t# ptr" %}
11342 opcode(0x85);
11343 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11344 ins_pipe(ialu_cr_reg_imm);
11345 %}
11346
11347 // This will generate a signed flags result. This should be OK since
11348 // any compare to a zero should be eq/neq.
11349 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11350 %{
11351 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11352 match(Set cr (CmpP (LoadP op) zero));
11353
11354 ins_cost(500); // XXX
11355 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11356 opcode(0xF7); /* Opcode F7 /0 */
11357 ins_encode(REX_mem_wide(op),
11358 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11359 ins_pipe(ialu_cr_reg_imm);
11360 %}
11361
11362 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11363 %{
11364 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11365 match(Set cr (CmpP (LoadP mem) zero));
11366
11367 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11368 ins_encode %{
11369 __ cmpq(r12, $mem$$Address);
11370 %}
11371 ins_pipe(ialu_cr_reg_mem);
11372 %}
11373
11374 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11375 %{
11376 match(Set cr (CmpN op1 op2));
11377
11378 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11379 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11380 ins_pipe(ialu_cr_reg_reg);
11381 %}
11382
11383 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11384 %{
11385 match(Set cr (CmpN src (LoadN mem)));
11386
11387 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11388 ins_encode %{
11389 __ cmpl($src$$Register, $mem$$Address);
11390 %}
11391 ins_pipe(ialu_cr_reg_mem);
11392 %}
11393
11394 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11395 match(Set cr (CmpN op1 op2));
11396
11397 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11398 ins_encode %{
11399 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11400 %}
11401 ins_pipe(ialu_cr_reg_imm);
11402 %}
11403
11404 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11405 %{
11406 match(Set cr (CmpN src (LoadN mem)));
11407
11408 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11409 ins_encode %{
11410 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11411 %}
11412 ins_pipe(ialu_cr_reg_mem);
11413 %}
11414
11415 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11416 match(Set cr (CmpN op1 op2));
11417
11418 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11419 ins_encode %{
11420 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11421 %}
11422 ins_pipe(ialu_cr_reg_imm);
11423 %}
11424
11425 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11426 %{
11427 match(Set cr (CmpN src (LoadNKlass mem)));
11428
11429 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11430 ins_encode %{
11431 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11432 %}
11433 ins_pipe(ialu_cr_reg_mem);
11434 %}
11435
11436 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11437 match(Set cr (CmpN src zero));
11438
11439 format %{ "testl $src, $src\t# compressed ptr" %}
11440 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11441 ins_pipe(ialu_cr_reg_imm);
11442 %}
11443
11444 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11445 %{
11446 predicate(Universe::narrow_oop_base() != NULL);
11447 match(Set cr (CmpN (LoadN mem) zero));
11448
11449 ins_cost(500); // XXX
11450 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11451 ins_encode %{
11452 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11453 %}
11454 ins_pipe(ialu_cr_reg_mem);
11455 %}
11456
11457 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11458 %{
11459 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11460 match(Set cr (CmpN (LoadN mem) zero));
11461
11462 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11463 ins_encode %{
11464 __ cmpl(r12, $mem$$Address);
11465 %}
11466 ins_pipe(ialu_cr_reg_mem);
11467 %}
11468
11469 // Yanked all unsigned pointer compare operations.
11470 // Pointer compares are done with CmpP which is already unsigned.
11471
11472 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11473 %{
11474 match(Set cr (CmpL op1 op2));
11475
11476 format %{ "cmpq $op1, $op2" %}
11477 opcode(0x3B); /* Opcode 3B /r */
11478 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11479 ins_pipe(ialu_cr_reg_reg);
11480 %}
11481
11482 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11483 %{
11484 match(Set cr (CmpL op1 op2));
11485
11486 format %{ "cmpq $op1, $op2" %}
11487 opcode(0x81, 0x07); /* Opcode 81 /7 */
11488 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11489 ins_pipe(ialu_cr_reg_imm);
11490 %}
11491
11492 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11493 %{
11494 match(Set cr (CmpL op1 (LoadL op2)));
11495
11496 format %{ "cmpq $op1, $op2" %}
11497 opcode(0x3B); /* Opcode 3B /r */
11498 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11499 ins_pipe(ialu_cr_reg_mem);
11500 %}
11501
11502 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11503 %{
11504 match(Set cr (CmpL src zero));
11505
11506 format %{ "testq $src, $src" %}
11507 opcode(0x85);
11508 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11509 ins_pipe(ialu_cr_reg_imm);
11510 %}
11511
11512 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11513 %{
11514 match(Set cr (CmpL (AndL src con) zero));
11515
11516 format %{ "testq $src, $con\t# long" %}
11517 opcode(0xF7, 0x00);
11518 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11519 ins_pipe(ialu_cr_reg_imm);
11520 %}
11521
11522 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11523 %{
11524 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11525
11526 format %{ "testq $src, $mem" %}
11527 opcode(0x85);
11528 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11529 ins_pipe(ialu_cr_reg_mem);
11530 %}
11531
11532 // Manifest a CmpL result in an integer register. Very painful.
11533 // This is the test to avoid.
11534 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11535 %{
11536 match(Set dst (CmpL3 src1 src2));
11537 effect(KILL flags);
11538
11539 ins_cost(275); // XXX
11540 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11541 "movl $dst, -1\n\t"
11542 "jl,s done\n\t"
11543 "setne $dst\n\t"
11544 "movzbl $dst, $dst\n\t"
11545 "done:" %}
11546 ins_encode(cmpl3_flag(src1, src2, dst));
11547 ins_pipe(pipe_slow);
11548 %}
11549
11550 // Unsigned long compare Instructions; really, same as signed long except they
11551 // produce an rFlagsRegU instead of rFlagsReg.
11552 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11553 %{
11554 match(Set cr (CmpUL op1 op2));
11555
11556 format %{ "cmpq $op1, $op2\t# unsigned" %}
11557 opcode(0x3B); /* Opcode 3B /r */
11558 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11559 ins_pipe(ialu_cr_reg_reg);
11560 %}
11561
11562 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11563 %{
11564 match(Set cr (CmpUL op1 op2));
11565
11566 format %{ "cmpq $op1, $op2\t# unsigned" %}
11567 opcode(0x81, 0x07); /* Opcode 81 /7 */
11568 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11569 ins_pipe(ialu_cr_reg_imm);
11570 %}
11571
11572 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11573 %{
11574 match(Set cr (CmpUL op1 (LoadL op2)));
11575
11576 format %{ "cmpq $op1, $op2\t# unsigned" %}
11577 opcode(0x3B); /* Opcode 3B /r */
11578 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11579 ins_pipe(ialu_cr_reg_mem);
11580 %}
11581
11582 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11583 %{
11584 match(Set cr (CmpUL src zero));
11585
11586 format %{ "testq $src, $src\t# unsigned" %}
11587 opcode(0x85);
11588 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11589 ins_pipe(ialu_cr_reg_imm);
11590 %}
11591
11592 //----------Max and Min--------------------------------------------------------
11593 // Min Instructions
11594
11595 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11596 %{
11597 effect(USE_DEF dst, USE src, USE cr);
11598
11599 format %{ "cmovlgt $dst, $src\t# min" %}
11600 opcode(0x0F, 0x4F);
11601 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11602 ins_pipe(pipe_cmov_reg);
11603 %}
11604
11605
11606 instruct minI_rReg(rRegI dst, rRegI src)
11607 %{
11608 match(Set dst (MinI dst src));
11609
11610 ins_cost(200);
11611 expand %{
11612 rFlagsReg cr;
11613 compI_rReg(cr, dst, src);
11614 cmovI_reg_g(dst, src, cr);
11615 %}
11616 %}
11617
11618 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11619 %{
11620 effect(USE_DEF dst, USE src, USE cr);
11621
11622 format %{ "cmovllt $dst, $src\t# max" %}
11623 opcode(0x0F, 0x4C);
11624 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11625 ins_pipe(pipe_cmov_reg);
11626 %}
11627
11628
11629 instruct maxI_rReg(rRegI dst, rRegI src)
11630 %{
11631 match(Set dst (MaxI dst src));
11632
11633 ins_cost(200);
11634 expand %{
11635 rFlagsReg cr;
11636 compI_rReg(cr, dst, src);
11637 cmovI_reg_l(dst, src, cr);
11638 %}
11639 %}
11640
11641 // ============================================================================
11642 // Branch Instructions
11643
11644 // Jump Direct - Label defines a relative address from JMP+1
11645 instruct jmpDir(label labl)
11646 %{
11647 match(Goto);
11648 effect(USE labl);
11649
11650 ins_cost(300);
11651 format %{ "jmp $labl" %}
11652 size(5);
11653 ins_encode %{
11654 Label* L = $labl$$label;
11655 __ jmp(*L, false); // Always long jump
11656 %}
11657 ins_pipe(pipe_jmp);
11658 %}
11659
11660 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11661 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11662 %{
11663 match(If cop cr);
11664 effect(USE labl);
11665
11666 ins_cost(300);
11667 format %{ "j$cop $labl" %}
11668 size(6);
11669 ins_encode %{
11670 Label* L = $labl$$label;
11671 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11672 %}
11673 ins_pipe(pipe_jcc);
11674 %}
11675
11676 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11677 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11678 %{
11679 predicate(!n->has_vector_mask_set());
11680 match(CountedLoopEnd cop cr);
11681 effect(USE labl);
11682
11683 ins_cost(300);
11684 format %{ "j$cop $labl\t# loop end" %}
11685 size(6);
11686 ins_encode %{
11687 Label* L = $labl$$label;
11688 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11689 %}
11690 ins_pipe(pipe_jcc);
11691 %}
11692
11693 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11694 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11695 predicate(!n->has_vector_mask_set());
11696 match(CountedLoopEnd cop cmp);
11697 effect(USE labl);
11698
11699 ins_cost(300);
11700 format %{ "j$cop,u $labl\t# loop end" %}
11701 size(6);
11702 ins_encode %{
11703 Label* L = $labl$$label;
11704 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11705 %}
11706 ins_pipe(pipe_jcc);
11707 %}
11708
11709 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11710 predicate(!n->has_vector_mask_set());
11711 match(CountedLoopEnd cop cmp);
11712 effect(USE labl);
11713
11714 ins_cost(200);
11715 format %{ "j$cop,u $labl\t# loop end" %}
11716 size(6);
11717 ins_encode %{
11718 Label* L = $labl$$label;
11719 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11720 %}
11721 ins_pipe(pipe_jcc);
11722 %}
11723
11724 // mask version
11725 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11726 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
11727 %{
11728 predicate(n->has_vector_mask_set());
11729 match(CountedLoopEnd cop cr);
11730 effect(USE labl);
11731
11732 ins_cost(400);
11733 format %{ "j$cop $labl\t# loop end\n\t"
11734 "restorevectmask \t# vector mask restore for loops" %}
11735 size(10);
11736 ins_encode %{
11737 Label* L = $labl$$label;
11738 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11739 __ restorevectmask();
11740 %}
11741 ins_pipe(pipe_jcc);
11742 %}
11743
11744 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11745 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11746 predicate(n->has_vector_mask_set());
11747 match(CountedLoopEnd cop cmp);
11748 effect(USE labl);
11749
11750 ins_cost(400);
11751 format %{ "j$cop,u $labl\t# loop end\n\t"
11752 "restorevectmask \t# vector mask restore for loops" %}
11753 size(10);
11754 ins_encode %{
11755 Label* L = $labl$$label;
11756 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11757 __ restorevectmask();
11758 %}
11759 ins_pipe(pipe_jcc);
11760 %}
11761
11762 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11763 predicate(n->has_vector_mask_set());
11764 match(CountedLoopEnd cop cmp);
11765 effect(USE labl);
11766
11767 ins_cost(300);
11768 format %{ "j$cop,u $labl\t# loop end\n\t"
11769 "restorevectmask \t# vector mask restore for loops" %}
11770 size(10);
11771 ins_encode %{
11772 Label* L = $labl$$label;
11773 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11774 __ restorevectmask();
11775 %}
11776 ins_pipe(pipe_jcc);
11777 %}
11778
11779 // Jump Direct Conditional - using unsigned comparison
11780 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11781 match(If cop cmp);
11782 effect(USE labl);
11783
11784 ins_cost(300);
11785 format %{ "j$cop,u $labl" %}
11786 size(6);
11787 ins_encode %{
11788 Label* L = $labl$$label;
11789 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11790 %}
11791 ins_pipe(pipe_jcc);
11792 %}
11793
11794 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11795 match(If cop cmp);
11796 effect(USE labl);
11797
11798 ins_cost(200);
11799 format %{ "j$cop,u $labl" %}
11800 size(6);
11801 ins_encode %{
11802 Label* L = $labl$$label;
11803 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11804 %}
11805 ins_pipe(pipe_jcc);
11806 %}
11807
11808 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11809 match(If cop cmp);
11810 effect(USE labl);
11811
11812 ins_cost(200);
11813 format %{ $$template
11814 if ($cop$$cmpcode == Assembler::notEqual) {
11815 $$emit$$"jp,u $labl\n\t"
11816 $$emit$$"j$cop,u $labl"
11817 } else {
11818 $$emit$$"jp,u done\n\t"
11819 $$emit$$"j$cop,u $labl\n\t"
11820 $$emit$$"done:"
11821 }
11822 %}
11823 ins_encode %{
11824 Label* l = $labl$$label;
11825 if ($cop$$cmpcode == Assembler::notEqual) {
11826 __ jcc(Assembler::parity, *l, false);
11827 __ jcc(Assembler::notEqual, *l, false);
11828 } else if ($cop$$cmpcode == Assembler::equal) {
11829 Label done;
11830 __ jccb(Assembler::parity, done);
11831 __ jcc(Assembler::equal, *l, false);
11832 __ bind(done);
11833 } else {
11834 ShouldNotReachHere();
11835 }
11836 %}
11837 ins_pipe(pipe_jcc);
11838 %}
11839
11840 // ============================================================================
11841 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11842 // superklass array for an instance of the superklass. Set a hidden
11843 // internal cache on a hit (cache is checked with exposed code in
11844 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11845 // encoding ALSO sets flags.
11846
11847 instruct partialSubtypeCheck(rdi_RegP result,
11848 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11849 rFlagsReg cr)
11850 %{
11851 match(Set result (PartialSubtypeCheck sub super));
11852 effect(KILL rcx, KILL cr);
11853
11854 ins_cost(1100); // slightly larger than the next version
11855 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11856 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11857 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11858 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11859 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11860 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11861 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11862 "miss:\t" %}
11863
11864 opcode(0x1); // Force a XOR of RDI
11865 ins_encode(enc_PartialSubtypeCheck());
11866 ins_pipe(pipe_slow);
11867 %}
11868
11869 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11870 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11871 immP0 zero,
11872 rdi_RegP result)
11873 %{
11874 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11875 effect(KILL rcx, KILL result);
11876
11877 ins_cost(1000);
11878 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11879 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11880 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11881 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11882 "jne,s miss\t\t# Missed: flags nz\n\t"
11883 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11884 "miss:\t" %}
11885
11886 opcode(0x0); // No need to XOR RDI
11887 ins_encode(enc_PartialSubtypeCheck());
11888 ins_pipe(pipe_slow);
11889 %}
11890
11891 // ============================================================================
11892 // Branch Instructions -- short offset versions
11893 //
11894 // These instructions are used to replace jumps of a long offset (the default
11895 // match) with jumps of a shorter offset. These instructions are all tagged
11896 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11897 // match rules in general matching. Instead, the ADLC generates a conversion
11898 // method in the MachNode which can be used to do in-place replacement of the
11899 // long variant with the shorter variant. The compiler will determine if a
11900 // branch can be taken by the is_short_branch_offset() predicate in the machine
11901 // specific code section of the file.
11902
11903 // Jump Direct - Label defines a relative address from JMP+1
11904 instruct jmpDir_short(label labl) %{
11905 match(Goto);
11906 effect(USE labl);
11907
11908 ins_cost(300);
11909 format %{ "jmp,s $labl" %}
11910 size(2);
11911 ins_encode %{
11912 Label* L = $labl$$label;
11913 __ jmpb(*L);
11914 %}
11915 ins_pipe(pipe_jmp);
11916 ins_short_branch(1);
11917 %}
11918
11919 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11920 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11921 match(If cop cr);
11922 effect(USE labl);
11923
11924 ins_cost(300);
11925 format %{ "j$cop,s $labl" %}
11926 size(2);
11927 ins_encode %{
11928 Label* L = $labl$$label;
11929 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11930 %}
11931 ins_pipe(pipe_jcc);
11932 ins_short_branch(1);
11933 %}
11934
11935 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11936 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11937 match(CountedLoopEnd cop cr);
11938 effect(USE labl);
11939
11940 ins_cost(300);
11941 format %{ "j$cop,s $labl\t# loop end" %}
11942 size(2);
11943 ins_encode %{
11944 Label* L = $labl$$label;
11945 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11946 %}
11947 ins_pipe(pipe_jcc);
11948 ins_short_branch(1);
11949 %}
11950
11951 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11952 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11953 match(CountedLoopEnd cop cmp);
11954 effect(USE labl);
11955
11956 ins_cost(300);
11957 format %{ "j$cop,us $labl\t# loop end" %}
11958 size(2);
11959 ins_encode %{
11960 Label* L = $labl$$label;
11961 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11962 %}
11963 ins_pipe(pipe_jcc);
11964 ins_short_branch(1);
11965 %}
11966
11967 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11968 match(CountedLoopEnd cop cmp);
11969 effect(USE labl);
11970
11971 ins_cost(300);
11972 format %{ "j$cop,us $labl\t# loop end" %}
11973 size(2);
11974 ins_encode %{
11975 Label* L = $labl$$label;
11976 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11977 %}
11978 ins_pipe(pipe_jcc);
11979 ins_short_branch(1);
11980 %}
11981
11982 // Jump Direct Conditional - using unsigned comparison
11983 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11984 match(If cop cmp);
11985 effect(USE labl);
11986
11987 ins_cost(300);
11988 format %{ "j$cop,us $labl" %}
11989 size(2);
11990 ins_encode %{
11991 Label* L = $labl$$label;
11992 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11993 %}
11994 ins_pipe(pipe_jcc);
11995 ins_short_branch(1);
11996 %}
11997
11998 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11999 match(If cop cmp);
12000 effect(USE labl);
12001
12002 ins_cost(300);
12003 format %{ "j$cop,us $labl" %}
12004 size(2);
12005 ins_encode %{
12006 Label* L = $labl$$label;
12007 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12008 %}
12009 ins_pipe(pipe_jcc);
12010 ins_short_branch(1);
12011 %}
12012
12013 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12014 match(If cop cmp);
12015 effect(USE labl);
12016
12017 ins_cost(300);
12018 format %{ $$template
12019 if ($cop$$cmpcode == Assembler::notEqual) {
12020 $$emit$$"jp,u,s $labl\n\t"
12021 $$emit$$"j$cop,u,s $labl"
12022 } else {
12023 $$emit$$"jp,u,s done\n\t"
12024 $$emit$$"j$cop,u,s $labl\n\t"
12025 $$emit$$"done:"
12026 }
12027 %}
12028 size(4);
12029 ins_encode %{
12030 Label* l = $labl$$label;
12031 if ($cop$$cmpcode == Assembler::notEqual) {
12032 __ jccb(Assembler::parity, *l);
12033 __ jccb(Assembler::notEqual, *l);
12034 } else if ($cop$$cmpcode == Assembler::equal) {
12035 Label done;
12036 __ jccb(Assembler::parity, done);
12037 __ jccb(Assembler::equal, *l);
12038 __ bind(done);
12039 } else {
12040 ShouldNotReachHere();
12041 }
12042 %}
12043 ins_pipe(pipe_jcc);
12044 ins_short_branch(1);
12045 %}
12046
12047 // ============================================================================
12048 // inlined locking and unlocking
12049
12050 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12051 predicate(Compile::current()->use_rtm());
12052 match(Set cr (FastLock object box));
12053 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12054 ins_cost(300);
12055 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12056 ins_encode %{
12057 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12058 $scr$$Register, $cx1$$Register, $cx2$$Register,
12059 _counters, _rtm_counters, _stack_rtm_counters,
12060 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12061 true, ra_->C->profile_rtm());
12062 %}
12063 ins_pipe(pipe_slow);
12064 %}
12065
12066 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12067 predicate(!Compile::current()->use_rtm());
12068 match(Set cr (FastLock object box));
12069 effect(TEMP tmp, TEMP scr, USE_KILL box);
12070 ins_cost(300);
12071 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12072 ins_encode %{
12073 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12074 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12075 %}
12076 ins_pipe(pipe_slow);
12077 %}
12078
12079 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12080 match(Set cr (FastUnlock object box));
12081 effect(TEMP tmp, USE_KILL box);
12082 ins_cost(300);
12083 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12084 ins_encode %{
12085 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12086 %}
12087 ins_pipe(pipe_slow);
12088 %}
12089
12090
12091 // ============================================================================
12092 // Safepoint Instructions
12093 instruct safePoint_poll(rFlagsReg cr)
12094 %{
12095 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12096 match(SafePoint);
12097 effect(KILL cr);
12098
12099 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12100 "# Safepoint: poll for GC" %}
12101 ins_cost(125);
12102 ins_encode %{
12103 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12104 __ testl(rax, addr);
12105 %}
12106 ins_pipe(ialu_reg_mem);
12107 %}
12108
12109 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12110 %{
12111 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12112 match(SafePoint poll);
12113 effect(KILL cr, USE poll);
12114
12115 format %{ "testl rax, [$poll]\t"
12116 "# Safepoint: poll for GC" %}
12117 ins_cost(125);
12118 ins_encode %{
12119 __ relocate(relocInfo::poll_type);
12120 __ testl(rax, Address($poll$$Register, 0));
12121 %}
12122 ins_pipe(ialu_reg_mem);
12123 %}
12124
12125 instruct safePoint_poll_tls(rFlagsReg cr, rex_RegP poll)
12126 %{
12127 predicate(SafepointMechanism::uses_thread_local_poll());
12128 match(SafePoint poll);
12129 effect(KILL cr, USE poll);
12130
12131 format %{ "testl rax, [$poll]\t"
12132 "# Safepoint: poll for GC" %}
12133 ins_cost(125);
12134 size(3); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12135 ins_encode %{
12136 __ relocate(relocInfo::poll_type);
12137 address pre_pc = __ pc();
12138 __ testl(rax, Address($poll$$Register, 0));
12139 address post_pc = __ pc();
12140 guarantee(pre_pc[0] == 0x41 && pre_pc[1] == 0x85, "must emit #rex test-ax [reg]");
12141 %}
12142 ins_pipe(ialu_reg_mem);
12143 %}
12144
12145 // ============================================================================
12146 // Procedure Call/Return Instructions
12147 // Call Java Static Instruction
12148 // Note: If this code changes, the corresponding ret_addr_offset() and
12149 // compute_padding() functions will have to be adjusted.
12150 instruct CallStaticJavaDirect(method meth) %{
12151 match(CallStaticJava);
12152 effect(USE meth);
12153
12154 ins_cost(300);
12155 format %{ "call,static " %}
12156 opcode(0xE8); /* E8 cd */
12157 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12158 ins_pipe(pipe_slow);
12159 ins_alignment(4);
12160 %}
12161
12162 // Call Java Dynamic Instruction
12163 // Note: If this code changes, the corresponding ret_addr_offset() and
12164 // compute_padding() functions will have to be adjusted.
12165 instruct CallDynamicJavaDirect(method meth)
12166 %{
12167 match(CallDynamicJava);
12168 effect(USE meth);
12169
12170 ins_cost(300);
12171 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12172 "call,dynamic " %}
12173 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12174 ins_pipe(pipe_slow);
12175 ins_alignment(4);
12176 %}
12177
12178 // Call Runtime Instruction
12179 instruct CallRuntimeDirect(method meth)
12180 %{
12181 match(CallRuntime);
12182 effect(USE meth);
12183
12184 ins_cost(300);
12185 format %{ "call,runtime " %}
12186 ins_encode(clear_avx, Java_To_Runtime(meth));
12187 ins_pipe(pipe_slow);
12188 %}
12189
12190 // Call runtime without safepoint
12191 instruct CallLeafDirect(method meth)
12192 %{
12193 match(CallLeaf);
12194 effect(USE meth);
12195
12196 ins_cost(300);
12197 format %{ "call_leaf,runtime " %}
12198 ins_encode(clear_avx, Java_To_Runtime(meth));
12199 ins_pipe(pipe_slow);
12200 %}
12201
12202 // Call runtime without safepoint
12203 instruct CallLeafNoFPDirect(method meth)
12204 %{
12205 match(CallLeafNoFP);
12206 effect(USE meth);
12207
12208 ins_cost(300);
12209 format %{ "call_leaf_nofp,runtime " %}
12210 ins_encode(clear_avx, Java_To_Runtime(meth));
12211 ins_pipe(pipe_slow);
12212 %}
12213
12214 // Return Instruction
12215 // Remove the return address & jump to it.
12216 // Notice: We always emit a nop after a ret to make sure there is room
12217 // for safepoint patching
12218 instruct Ret()
12219 %{
12220 match(Return);
12221
12222 format %{ "ret" %}
12223 opcode(0xC3);
12224 ins_encode(OpcP);
12225 ins_pipe(pipe_jmp);
12226 %}
12227
12228 // Tail Call; Jump from runtime stub to Java code.
12229 // Also known as an 'interprocedural jump'.
12230 // Target of jump will eventually return to caller.
12231 // TailJump below removes the return address.
12232 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12233 %{
12234 match(TailCall jump_target method_oop);
12235
12236 ins_cost(300);
12237 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12238 opcode(0xFF, 0x4); /* Opcode FF /4 */
12239 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12240 ins_pipe(pipe_jmp);
12241 %}
12242
12243 // Tail Jump; remove the return address; jump to target.
12244 // TailCall above leaves the return address around.
12245 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12246 %{
12247 match(TailJump jump_target ex_oop);
12248
12249 ins_cost(300);
12250 format %{ "popq rdx\t# pop return address\n\t"
12251 "jmp $jump_target" %}
12252 opcode(0xFF, 0x4); /* Opcode FF /4 */
12253 ins_encode(Opcode(0x5a), // popq rdx
12254 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12255 ins_pipe(pipe_jmp);
12256 %}
12257
12258 // Create exception oop: created by stack-crawling runtime code.
12259 // Created exception is now available to this handler, and is setup
12260 // just prior to jumping to this handler. No code emitted.
12261 instruct CreateException(rax_RegP ex_oop)
12262 %{
12263 match(Set ex_oop (CreateEx));
12264
12265 size(0);
12266 // use the following format syntax
12267 format %{ "# exception oop is in rax; no code emitted" %}
12268 ins_encode();
12269 ins_pipe(empty);
12270 %}
12271
12272 // Rethrow exception:
12273 // The exception oop will come in the first argument position.
12274 // Then JUMP (not call) to the rethrow stub code.
12275 instruct RethrowException()
12276 %{
12277 match(Rethrow);
12278
12279 // use the following format syntax
12280 format %{ "jmp rethrow_stub" %}
12281 ins_encode(enc_rethrow);
12282 ins_pipe(pipe_jmp);
12283 %}
12284
12285
12286 // ============================================================================
12287 // This name is KNOWN by the ADLC and cannot be changed.
12288 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12289 // for this guy.
12290 instruct tlsLoadP(r15_RegP dst) %{
12291 match(Set dst (ThreadLocal));
12292 effect(DEF dst);
12293
12294 size(0);
12295 format %{ "# TLS is in R15" %}
12296 ins_encode( /*empty encoding*/ );
12297 ins_pipe(ialu_reg_reg);
12298 %}
12299
12300
12301 //----------PEEPHOLE RULES-----------------------------------------------------
12302 // These must follow all instruction definitions as they use the names
12303 // defined in the instructions definitions.
12304 //
12305 // peepmatch ( root_instr_name [preceding_instruction]* );
12306 //
12307 // peepconstraint %{
12308 // (instruction_number.operand_name relational_op instruction_number.operand_name
12309 // [, ...] );
12310 // // instruction numbers are zero-based using left to right order in peepmatch
12311 //
12312 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12313 // // provide an instruction_number.operand_name for each operand that appears
12314 // // in the replacement instruction's match rule
12315 //
12316 // ---------VM FLAGS---------------------------------------------------------
12317 //
12318 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12319 //
12320 // Each peephole rule is given an identifying number starting with zero and
12321 // increasing by one in the order seen by the parser. An individual peephole
12322 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12323 // on the command-line.
12324 //
12325 // ---------CURRENT LIMITATIONS----------------------------------------------
12326 //
12327 // Only match adjacent instructions in same basic block
12328 // Only equality constraints
12329 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12330 // Only one replacement instruction
12331 //
12332 // ---------EXAMPLE----------------------------------------------------------
12333 //
12334 // // pertinent parts of existing instructions in architecture description
12335 // instruct movI(rRegI dst, rRegI src)
12336 // %{
12337 // match(Set dst (CopyI src));
12338 // %}
12339 //
12340 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12341 // %{
12342 // match(Set dst (AddI dst src));
12343 // effect(KILL cr);
12344 // %}
12345 //
12346 // // Change (inc mov) to lea
12347 // peephole %{
12348 // // increment preceeded by register-register move
12349 // peepmatch ( incI_rReg movI );
12350 // // require that the destination register of the increment
12351 // // match the destination register of the move
12352 // peepconstraint ( 0.dst == 1.dst );
12353 // // construct a replacement instruction that sets
12354 // // the destination to ( move's source register + one )
12355 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12356 // %}
12357 //
12358
12359 // Implementation no longer uses movX instructions since
12360 // machine-independent system no longer uses CopyX nodes.
12361 //
12362 // peephole
12363 // %{
12364 // peepmatch (incI_rReg movI);
12365 // peepconstraint (0.dst == 1.dst);
12366 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12367 // %}
12368
12369 // peephole
12370 // %{
12371 // peepmatch (decI_rReg movI);
12372 // peepconstraint (0.dst == 1.dst);
12373 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12374 // %}
12375
12376 // peephole
12377 // %{
12378 // peepmatch (addI_rReg_imm movI);
12379 // peepconstraint (0.dst == 1.dst);
12380 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12381 // %}
12382
12383 // peephole
12384 // %{
12385 // peepmatch (incL_rReg movL);
12386 // peepconstraint (0.dst == 1.dst);
12387 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12388 // %}
12389
12390 // peephole
12391 // %{
12392 // peepmatch (decL_rReg movL);
12393 // peepconstraint (0.dst == 1.dst);
12394 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12395 // %}
12396
12397 // peephole
12398 // %{
12399 // peepmatch (addL_rReg_imm movL);
12400 // peepconstraint (0.dst == 1.dst);
12401 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12402 // %}
12403
12404 // peephole
12405 // %{
12406 // peepmatch (addP_rReg_imm movP);
12407 // peepconstraint (0.dst == 1.dst);
12408 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12409 // %}
12410
12411 // // Change load of spilled value to only a spill
12412 // instruct storeI(memory mem, rRegI src)
12413 // %{
12414 // match(Set mem (StoreI mem src));
12415 // %}
12416 //
12417 // instruct loadI(rRegI dst, memory mem)
12418 // %{
12419 // match(Set dst (LoadI mem));
12420 // %}
12421 //
12422
12423 peephole
12424 %{
12425 peepmatch (loadI storeI);
12426 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12427 peepreplace (storeI(1.mem 1.mem 1.src));
12428 %}
12429
12430 peephole
12431 %{
12432 peepmatch (loadL storeL);
12433 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12434 peepreplace (storeL(1.mem 1.mem 1.src));
12435 %}
12436
12437 //----------SMARTSPILL RULES---------------------------------------------------
12438 // These must follow all instruction definitions as they use the names
12439 // defined in the instructions definitions.