12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP
  27 #define CPU_ZERO_VM_ICACHE_ZERO_HPP
  28 
  29 // Interface for updating the instruction cache.  Whenever the VM
  30 // modifies code, part of the processor instruction cache potentially
  31 // has to be flushed.  This implementation is empty: Zero never deals
  32 // with code, and LLVM handles cache flushing for Shark.
  33 
  34 class ICache : public AbstractICache {
  35  public:
  36   static void initialize() {}
  37   static void invalidate_word(address addr) {}
  38   static void invalidate_range(address start, int nbytes) {}
  39 };
  40 
  41 #endif // CPU_ZERO_VM_ICACHE_ZERO_HPP

  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP
  27 #define CPU_ZERO_VM_ICACHE_ZERO_HPP
  28 
  29 // Interface for updating the instruction cache.  Whenever the VM
  30 // modifies code, part of the processor instruction cache potentially
  31 // has to be flushed.  This implementation is empty: Zero never deals
  32 // with code.
  33 
  34 class ICache : public AbstractICache {
  35  public:
  36   static void initialize() {}
  37   static void invalidate_word(address addr) {}
  38   static void invalidate_range(address start, int nbytes) {}
  39 };
  40 
  41 #endif // CPU_ZERO_VM_ICACHE_ZERO_HPP