1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "jvm.h"
30 #include "asm/assembler.hpp"
31 #include "asm/assembler.inline.hpp"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/cardTable.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "nativeInst_aarch64.hpp"
40 #include "oops/accessDecorators.hpp"
41 #include "oops/compressedOops.inline.hpp"
42 #include "oops/klass.inline.hpp"
43 #include "oops/oop.hpp"
44 #include "opto/compile.hpp"
45 #include "opto/intrinsicnode.hpp"
46 #include "opto/node.hpp"
47 #include "runtime/biasedLocking.hpp"
48 #include "runtime/icache.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/jniHandles.inline.hpp"
51 #include "runtime/sharedRuntime.hpp"
52 #include "runtime/thread.hpp"
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 // Patch any kind of instruction; there may be several instructions.
65 // Return the total length (in bytes) of the instructions.
66 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
67 int instructions = 1;
68 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
69 long offset = (target - branch) >> 2;
70 unsigned insn = *(unsigned*)branch;
71 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
72 // Load register (literal)
73 Instruction_aarch64::spatch(branch, 23, 5, offset);
74 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
75 // Unconditional branch (immediate)
76 Instruction_aarch64::spatch(branch, 25, 0, offset);
77 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
78 // Conditional branch (immediate)
79 Instruction_aarch64::spatch(branch, 23, 5, offset);
80 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
81 // Compare & branch (immediate)
82 Instruction_aarch64::spatch(branch, 23, 5, offset);
83 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
84 // Test & branch (immediate)
85 Instruction_aarch64::spatch(branch, 18, 5, offset);
86 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
87 // PC-rel. addressing
88 offset = target-branch;
89 int shift = Instruction_aarch64::extract(insn, 31, 31);
90 if (shift) {
91 u_int64_t dest = (u_int64_t)target;
92 uint64_t pc_page = (uint64_t)branch >> 12;
93 uint64_t adr_page = (uint64_t)target >> 12;
94 unsigned offset_lo = dest & 0xfff;
95 offset = adr_page - pc_page;
96
97 // We handle 4 types of PC relative addressing
98 // 1 - adrp Rx, target_page
99 // ldr/str Ry, [Rx, #offset_in_page]
100 // 2 - adrp Rx, target_page
101 // add Ry, Rx, #offset_in_page
102 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
103 // movk Rx, #imm16<<32
104 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
105 // In the first 3 cases we must check that Rx is the same in the adrp and the
106 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end
107 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened
108 // to be followed by a random unrelated ldr/str, add or movk instruction.
109 //
110 unsigned insn2 = ((unsigned*)branch)[1];
111 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
112 Instruction_aarch64::extract(insn, 4, 0) ==
113 Instruction_aarch64::extract(insn2, 9, 5)) {
114 // Load/store register (unsigned immediate)
115 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
116 Instruction_aarch64::patch(branch + sizeof (unsigned),
117 21, 10, offset_lo >> size);
118 guarantee(((dest >> size) << size) == dest, "misaligned target");
119 instructions = 2;
120 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
121 Instruction_aarch64::extract(insn, 4, 0) ==
122 Instruction_aarch64::extract(insn2, 4, 0)) {
123 // add (immediate)
124 Instruction_aarch64::patch(branch + sizeof (unsigned),
125 21, 10, offset_lo);
126 instructions = 2;
127 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
128 Instruction_aarch64::extract(insn, 4, 0) ==
129 Instruction_aarch64::extract(insn2, 4, 0)) {
130 // movk #imm16<<32
131 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
132 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
133 long pc_page = (long)branch >> 12;
134 long adr_page = (long)dest >> 12;
135 offset = adr_page - pc_page;
136 instructions = 2;
137 }
138 }
139 int offset_lo = offset & 3;
140 offset >>= 2;
141 Instruction_aarch64::spatch(branch, 23, 5, offset);
142 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
143 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
144 u_int64_t dest = (u_int64_t)target;
145 // Move wide constant
146 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
147 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
148 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
149 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
150 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
151 assert(target_addr_for_insn(branch) == target, "should be");
152 instructions = 3;
153 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
154 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
155 // nothing to do
156 assert(target == 0, "did not expect to relocate target for polling page load");
157 } else {
158 ShouldNotReachHere();
159 }
160 return instructions * NativeInstruction::instruction_size;
161 }
162
163 int MacroAssembler::patch_oop(address insn_addr, address o) {
164 int instructions;
165 unsigned insn = *(unsigned*)insn_addr;
166 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
167
168 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
169 // narrow OOPs by setting the upper 16 bits in the first
170 // instruction.
171 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
172 // Move narrow OOP
173 narrowOop n = CompressedOops::encode((oop)o);
174 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
175 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
176 instructions = 2;
177 } else {
178 // Move wide OOP
179 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
180 uintptr_t dest = (uintptr_t)o;
181 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
182 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
183 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
184 instructions = 3;
185 }
186 return instructions * NativeInstruction::instruction_size;
187 }
188
189 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
190 // Metatdata pointers are either narrow (32 bits) or wide (48 bits).
191 // We encode narrow ones by setting the upper 16 bits in the first
192 // instruction.
193 NativeInstruction *insn = nativeInstruction_at(insn_addr);
194 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
195 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
196
197 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
198 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
199 return 2 * NativeInstruction::instruction_size;
200 }
201
202 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
203 long offset = 0;
204 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
205 // Load register (literal)
206 offset = Instruction_aarch64::sextract(insn, 23, 5);
207 return address(((uint64_t)insn_addr + (offset << 2)));
208 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
209 // Unconditional branch (immediate)
210 offset = Instruction_aarch64::sextract(insn, 25, 0);
211 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
212 // Conditional branch (immediate)
213 offset = Instruction_aarch64::sextract(insn, 23, 5);
214 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
215 // Compare & branch (immediate)
216 offset = Instruction_aarch64::sextract(insn, 23, 5);
217 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
218 // Test & branch (immediate)
219 offset = Instruction_aarch64::sextract(insn, 18, 5);
220 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
221 // PC-rel. addressing
222 offset = Instruction_aarch64::extract(insn, 30, 29);
223 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
224 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
225 if (shift) {
226 offset <<= shift;
227 uint64_t target_page = ((uint64_t)insn_addr) + offset;
228 target_page &= ((uint64_t)-1) << shift;
229 // Return the target address for the following sequences
230 // 1 - adrp Rx, target_page
231 // ldr/str Ry, [Rx, #offset_in_page]
232 // 2 - adrp Rx, target_page
233 // add Ry, Rx, #offset_in_page
234 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
235 // movk Rx, #imm12<<32
236 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
237 //
238 // In the first two cases we check that the register is the same and
239 // return the target_page + the offset within the page.
240 // Otherwise we assume it is a page aligned relocation and return
241 // the target page only.
242 //
243 unsigned insn2 = ((unsigned*)insn_addr)[1];
244 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
245 Instruction_aarch64::extract(insn, 4, 0) ==
246 Instruction_aarch64::extract(insn2, 9, 5)) {
247 // Load/store register (unsigned immediate)
248 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
249 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
250 return address(target_page + (byte_offset << size));
251 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
252 Instruction_aarch64::extract(insn, 4, 0) ==
253 Instruction_aarch64::extract(insn2, 4, 0)) {
254 // add (immediate)
255 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
256 return address(target_page + byte_offset);
257 } else {
258 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
259 Instruction_aarch64::extract(insn, 4, 0) ==
260 Instruction_aarch64::extract(insn2, 4, 0)) {
261 target_page = (target_page & 0xffffffff) |
262 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
263 }
264 return (address)target_page;
265 }
266 } else {
267 ShouldNotReachHere();
268 }
269 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
270 u_int32_t *insns = (u_int32_t *)insn_addr;
271 // Move wide constant: movz, movk, movk. See movptr().
272 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
273 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
274 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
275 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
276 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
277 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
278 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
279 return 0;
280 } else {
281 ShouldNotReachHere();
282 }
283 return address(((uint64_t)insn_addr + (offset << 2)));
284 }
285
286 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
287 dsb(Assembler::SY);
288 }
289
290 void MacroAssembler::safepoint_poll(Label& slow_path) {
291 if (SafepointMechanism::uses_thread_local_poll()) {
292 ldr(rscratch1, Address(rthread, Thread::polling_page_offset()));
293 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
294 } else {
295 unsigned long offset;
296 adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset);
297 ldrw(rscratch1, Address(rscratch1, offset));
298 assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code");
299 cbnz(rscratch1, slow_path);
300 }
301 }
302
303 // Just like safepoint_poll, but use an acquiring load for thread-
304 // local polling.
305 //
306 // We need an acquire here to ensure that any subsequent load of the
307 // global SafepointSynchronize::_state flag is ordered after this load
308 // of the local Thread::_polling page. We don't want this poll to
309 // return false (i.e. not safepointing) and a later poll of the global
310 // SafepointSynchronize::_state spuriously to return true.
311 //
312 // This is to avoid a race when we're in a native->Java transition
313 // racing the code which wakes up from a safepoint.
314 //
315 void MacroAssembler::safepoint_poll_acquire(Label& slow_path) {
316 if (SafepointMechanism::uses_thread_local_poll()) {
317 lea(rscratch1, Address(rthread, Thread::polling_page_offset()));
318 ldar(rscratch1, rscratch1);
319 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
320 } else {
321 safepoint_poll(slow_path);
322 }
323 }
324
325 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
326 // we must set sp to zero to clear frame
327 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
328
329 // must clear fp, so that compiled frames are not confused; it is
330 // possible that we need it only for debugging
331 if (clear_fp) {
332 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
333 }
334
335 // Always clear the pc because it could have been set by make_walkable()
336 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
337 }
338
339 // Calls to C land
340 //
341 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
342 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
343 // has to be reset to 0. This is required to allow proper stack traversal.
344 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
345 Register last_java_fp,
346 Register last_java_pc,
347 Register scratch) {
348
349 if (last_java_pc->is_valid()) {
350 str(last_java_pc, Address(rthread,
351 JavaThread::frame_anchor_offset()
352 + JavaFrameAnchor::last_Java_pc_offset()));
353 }
354
355 // determine last_java_sp register
356 if (last_java_sp == sp) {
357 mov(scratch, sp);
358 last_java_sp = scratch;
359 } else if (!last_java_sp->is_valid()) {
360 last_java_sp = esp;
361 }
362
363 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
364
365 // last_java_fp is optional
366 if (last_java_fp->is_valid()) {
367 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
368 }
369 }
370
371 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
372 Register last_java_fp,
373 address last_java_pc,
374 Register scratch) {
375 if (last_java_pc != NULL) {
376 adr(scratch, last_java_pc);
377 } else {
378 // FIXME: This is almost never correct. We should delete all
379 // cases of set_last_Java_frame with last_java_pc=NULL and use the
380 // correct return address instead.
381 adr(scratch, pc());
382 }
383
384 str(scratch, Address(rthread,
385 JavaThread::frame_anchor_offset()
386 + JavaFrameAnchor::last_Java_pc_offset()));
387
388 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
389 }
390
391 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
392 Register last_java_fp,
393 Label &L,
394 Register scratch) {
395 if (L.is_bound()) {
396 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
397 } else {
398 InstructionMark im(this);
399 L.add_patch_at(code(), locator());
400 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
401 }
402 }
403
404 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
405 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
406 assert(CodeCache::find_blob(entry.target()) != NULL,
407 "destination of far call not found in code cache");
408 if (far_branches()) {
409 unsigned long offset;
410 // We can use ADRP here because we know that the total size of
411 // the code cache cannot exceed 2Gb.
412 adrp(tmp, entry, offset);
413 add(tmp, tmp, offset);
414 if (cbuf) cbuf->set_insts_mark();
415 blr(tmp);
416 } else {
417 if (cbuf) cbuf->set_insts_mark();
418 bl(entry);
419 }
420 }
421
422 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
423 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
424 assert(CodeCache::find_blob(entry.target()) != NULL,
425 "destination of far call not found in code cache");
426 if (far_branches()) {
427 unsigned long offset;
428 // We can use ADRP here because we know that the total size of
429 // the code cache cannot exceed 2Gb.
430 adrp(tmp, entry, offset);
431 add(tmp, tmp, offset);
432 if (cbuf) cbuf->set_insts_mark();
433 br(tmp);
434 } else {
435 if (cbuf) cbuf->set_insts_mark();
436 b(entry);
437 }
438 }
439
440 void MacroAssembler::reserved_stack_check() {
441 // testing if reserved zone needs to be enabled
442 Label no_reserved_zone_enabling;
443
444 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
445 cmp(sp, rscratch1);
446 br(Assembler::LO, no_reserved_zone_enabling);
447
448 enter(); // LR and FP are live.
449 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone));
450 mov(c_rarg0, rthread);
451 blr(rscratch1);
452 leave();
453
454 // We have already removed our own frame.
455 // throw_delayed_StackOverflowError will think that it's been
456 // called by our caller.
457 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
458 br(rscratch1);
459 should_not_reach_here();
460
461 bind(no_reserved_zone_enabling);
462 }
463
464 int MacroAssembler::biased_locking_enter(Register lock_reg,
465 Register obj_reg,
466 Register swap_reg,
467 Register tmp_reg,
468 bool swap_reg_contains_mark,
469 Label& done,
470 Label* slow_case,
471 BiasedLockingCounters* counters) {
472 assert(UseBiasedLocking, "why call this otherwise?");
473 assert_different_registers(lock_reg, obj_reg, swap_reg);
474
475 if (PrintBiasedLockingStatistics && counters == NULL)
476 counters = BiasedLocking::counters();
477
478 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
479 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
480 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
481 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
482 Address saved_mark_addr(lock_reg, 0);
483
484 // Biased locking
485 // See whether the lock is currently biased toward our thread and
486 // whether the epoch is still valid
487 // Note that the runtime guarantees sufficient alignment of JavaThread
488 // pointers to allow age to be placed into low bits
489 // First check to see whether biasing is even enabled for this object
490 Label cas_label;
491 int null_check_offset = -1;
492 if (!swap_reg_contains_mark) {
493 null_check_offset = offset();
494 ldr(swap_reg, mark_addr);
495 }
496 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
497 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
498 br(Assembler::NE, cas_label);
499 // The bias pattern is present in the object's header. Need to check
500 // whether the bias owner and the epoch are both still current.
501 load_prototype_header(tmp_reg, obj_reg);
502 orr(tmp_reg, tmp_reg, rthread);
503 eor(tmp_reg, swap_reg, tmp_reg);
504 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
505 if (counters != NULL) {
506 Label around;
507 cbnz(tmp_reg, around);
508 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
509 b(done);
510 bind(around);
511 } else {
512 cbz(tmp_reg, done);
513 }
514
515 Label try_revoke_bias;
516 Label try_rebias;
517
518 // At this point we know that the header has the bias pattern and
519 // that we are not the bias owner in the current epoch. We need to
520 // figure out more details about the state of the header in order to
521 // know what operations can be legally performed on the object's
522 // header.
523
524 // If the low three bits in the xor result aren't clear, that means
525 // the prototype header is no longer biased and we have to revoke
526 // the bias on this object.
527 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
528 cbnz(rscratch1, try_revoke_bias);
529
530 // Biasing is still enabled for this data type. See whether the
531 // epoch of the current bias is still valid, meaning that the epoch
532 // bits of the mark word are equal to the epoch bits of the
533 // prototype header. (Note that the prototype header's epoch bits
534 // only change at a safepoint.) If not, attempt to rebias the object
535 // toward the current thread. Note that we must be absolutely sure
536 // that the current epoch is invalid in order to do this because
537 // otherwise the manipulations it performs on the mark word are
538 // illegal.
539 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
540 cbnz(rscratch1, try_rebias);
541
542 // The epoch of the current bias is still valid but we know nothing
543 // about the owner; it might be set or it might be clear. Try to
544 // acquire the bias of the object using an atomic operation. If this
545 // fails we will go in to the runtime to revoke the object's bias.
546 // Note that we first construct the presumed unbiased header so we
547 // don't accidentally blow away another thread's valid bias.
548 {
549 Label here;
550 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
551 andr(swap_reg, swap_reg, rscratch1);
552 orr(tmp_reg, swap_reg, rthread);
553 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
554 // If the biasing toward our thread failed, this means that
555 // another thread succeeded in biasing it toward itself and we
556 // need to revoke that bias. The revocation will occur in the
557 // interpreter runtime in the slow case.
558 bind(here);
559 if (counters != NULL) {
560 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
561 tmp_reg, rscratch1, rscratch2);
562 }
563 }
564 b(done);
565
566 bind(try_rebias);
567 // At this point we know the epoch has expired, meaning that the
568 // current "bias owner", if any, is actually invalid. Under these
569 // circumstances _only_, we are allowed to use the current header's
570 // value as the comparison value when doing the cas to acquire the
571 // bias in the current epoch. In other words, we allow transfer of
572 // the bias from one thread to another directly in this situation.
573 //
574 // FIXME: due to a lack of registers we currently blow away the age
575 // bits in this situation. Should attempt to preserve them.
576 {
577 Label here;
578 load_prototype_header(tmp_reg, obj_reg);
579 orr(tmp_reg, rthread, tmp_reg);
580 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
581 // If the biasing toward our thread failed, then another thread
582 // succeeded in biasing it toward itself and we need to revoke that
583 // bias. The revocation will occur in the runtime in the slow case.
584 bind(here);
585 if (counters != NULL) {
586 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
587 tmp_reg, rscratch1, rscratch2);
588 }
589 }
590 b(done);
591
592 bind(try_revoke_bias);
593 // The prototype mark in the klass doesn't have the bias bit set any
594 // more, indicating that objects of this data type are not supposed
595 // to be biased any more. We are going to try to reset the mark of
596 // this object to the prototype value and fall through to the
597 // CAS-based locking scheme. Note that if our CAS fails, it means
598 // that another thread raced us for the privilege of revoking the
599 // bias of this particular object, so it's okay to continue in the
600 // normal locking code.
601 //
602 // FIXME: due to a lack of registers we currently blow away the age
603 // bits in this situation. Should attempt to preserve them.
604 {
605 Label here, nope;
606 load_prototype_header(tmp_reg, obj_reg);
607 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
608 bind(here);
609
610 // Fall through to the normal CAS-based lock, because no matter what
611 // the result of the above CAS, some thread must have succeeded in
612 // removing the bias bit from the object's header.
613 if (counters != NULL) {
614 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
615 rscratch1, rscratch2);
616 }
617 bind(nope);
618 }
619
620 bind(cas_label);
621
622 return null_check_offset;
623 }
624
625 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
626 assert(UseBiasedLocking, "why call this otherwise?");
627
628 // Check for biased locking unlock case, which is a no-op
629 // Note: we do not have to check the thread ID for two reasons.
630 // First, the interpreter checks for IllegalMonitorStateException at
631 // a higher level. Second, if the bias was revoked while we held the
632 // lock, the object could not be rebiased toward another thread, so
633 // the bias bit would be clear.
634 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
635 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
636 cmp(temp_reg, markOopDesc::biased_lock_pattern);
637 br(Assembler::EQ, done);
638 }
639
640 static void pass_arg0(MacroAssembler* masm, Register arg) {
641 if (c_rarg0 != arg ) {
642 masm->mov(c_rarg0, arg);
643 }
644 }
645
646 static void pass_arg1(MacroAssembler* masm, Register arg) {
647 if (c_rarg1 != arg ) {
648 masm->mov(c_rarg1, arg);
649 }
650 }
651
652 static void pass_arg2(MacroAssembler* masm, Register arg) {
653 if (c_rarg2 != arg ) {
654 masm->mov(c_rarg2, arg);
655 }
656 }
657
658 static void pass_arg3(MacroAssembler* masm, Register arg) {
659 if (c_rarg3 != arg ) {
660 masm->mov(c_rarg3, arg);
661 }
662 }
663
664 void MacroAssembler::call_VM_base(Register oop_result,
665 Register java_thread,
666 Register last_java_sp,
667 address entry_point,
668 int number_of_arguments,
669 bool check_exceptions) {
670 // determine java_thread register
671 if (!java_thread->is_valid()) {
672 java_thread = rthread;
673 }
674
675 // determine last_java_sp register
676 if (!last_java_sp->is_valid()) {
677 last_java_sp = esp;
678 }
679
680 // debugging support
681 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
682 assert(java_thread == rthread, "unexpected register");
683 #ifdef ASSERT
684 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
685 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
686 #endif // ASSERT
687
688 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
689 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
690
691 // push java thread (becomes first argument of C function)
692
693 mov(c_rarg0, java_thread);
694
695 // set last Java frame before call
696 assert(last_java_sp != rfp, "can't use rfp");
697
698 Label l;
699 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
700
701 // do the call, remove parameters
702 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
703
704 // reset last Java frame
705 // Only interpreter should have to clear fp
706 reset_last_Java_frame(true);
707
708 // C++ interp handles this in the interpreter
709 check_and_handle_popframe(java_thread);
710 check_and_handle_earlyret(java_thread);
711
712 if (check_exceptions) {
713 // check for pending exceptions (java_thread is set upon return)
714 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
715 Label ok;
716 cbz(rscratch1, ok);
717 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
718 br(rscratch1);
719 bind(ok);
720 }
721
722 // get oop result if there is one and reset the value in the thread
723 if (oop_result->is_valid()) {
724 get_vm_result(oop_result, java_thread);
725 }
726 }
727
728 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
729 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
730 }
731
732 // Maybe emit a call via a trampoline. If the code cache is small
733 // trampolines won't be emitted.
734
735 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
736 assert(JavaThread::current()->is_Compiler_thread(), "just checking");
737 assert(entry.rspec().type() == relocInfo::runtime_call_type
738 || entry.rspec().type() == relocInfo::opt_virtual_call_type
739 || entry.rspec().type() == relocInfo::static_call_type
740 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
741
742 unsigned int start_offset = offset();
743 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
744 address stub = emit_trampoline_stub(start_offset, entry.target());
745 if (stub == NULL) {
746 return NULL; // CodeCache is full
747 }
748 }
749
750 if (cbuf) cbuf->set_insts_mark();
751 relocate(entry.rspec());
752 if (!far_branches()) {
753 bl(entry.target());
754 } else {
755 bl(pc());
756 }
757 // just need to return a non-null address
758 return pc();
759 }
760
761
762 // Emit a trampoline stub for a call to a target which is too far away.
763 //
764 // code sequences:
765 //
766 // call-site:
767 // branch-and-link to <destination> or <trampoline stub>
768 //
769 // Related trampoline stub for this call site in the stub section:
770 // load the call target from the constant pool
771 // branch (LR still points to the call site above)
772
773 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
774 address dest) {
775 address stub = start_a_stub(Compile::MAX_stubs_size/2);
776 if (stub == NULL) {
777 return NULL; // CodeBuffer::expand failed
778 }
779
780 // Create a trampoline stub relocation which relates this trampoline stub
781 // with the call instruction at insts_call_instruction_offset in the
782 // instructions code-section.
783 align(wordSize);
784 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
785 + insts_call_instruction_offset));
786 const int stub_start_offset = offset();
787
788 // Now, create the trampoline stub's code:
789 // - load the call
790 // - call
791 Label target;
792 ldr(rscratch1, target);
793 br(rscratch1);
794 bind(target);
795 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
796 "should be");
797 emit_int64((int64_t)dest);
798
799 const address stub_start_addr = addr_at(stub_start_offset);
800
801 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
802
803 end_a_stub();
804 return stub_start_addr;
805 }
806
807 address MacroAssembler::ic_call(address entry, jint method_index) {
808 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
809 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
810 // unsigned long offset;
811 // ldr_constant(rscratch2, const_ptr);
812 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
813 return trampoline_call(Address(entry, rh));
814 }
815
816 // Implementation of call_VM versions
817
818 void MacroAssembler::call_VM(Register oop_result,
819 address entry_point,
820 bool check_exceptions) {
821 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
822 }
823
824 void MacroAssembler::call_VM(Register oop_result,
825 address entry_point,
826 Register arg_1,
827 bool check_exceptions) {
828 pass_arg1(this, arg_1);
829 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
830 }
831
832 void MacroAssembler::call_VM(Register oop_result,
833 address entry_point,
834 Register arg_1,
835 Register arg_2,
836 bool check_exceptions) {
837 assert(arg_1 != c_rarg2, "smashed arg");
838 pass_arg2(this, arg_2);
839 pass_arg1(this, arg_1);
840 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
841 }
842
843 void MacroAssembler::call_VM(Register oop_result,
844 address entry_point,
845 Register arg_1,
846 Register arg_2,
847 Register arg_3,
848 bool check_exceptions) {
849 assert(arg_1 != c_rarg3, "smashed arg");
850 assert(arg_2 != c_rarg3, "smashed arg");
851 pass_arg3(this, arg_3);
852
853 assert(arg_1 != c_rarg2, "smashed arg");
854 pass_arg2(this, arg_2);
855
856 pass_arg1(this, arg_1);
857 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
858 }
859
860 void MacroAssembler::call_VM(Register oop_result,
861 Register last_java_sp,
862 address entry_point,
863 int number_of_arguments,
864 bool check_exceptions) {
865 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
866 }
867
868 void MacroAssembler::call_VM(Register oop_result,
869 Register last_java_sp,
870 address entry_point,
871 Register arg_1,
872 bool check_exceptions) {
873 pass_arg1(this, arg_1);
874 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
875 }
876
877 void MacroAssembler::call_VM(Register oop_result,
878 Register last_java_sp,
879 address entry_point,
880 Register arg_1,
881 Register arg_2,
882 bool check_exceptions) {
883
884 assert(arg_1 != c_rarg2, "smashed arg");
885 pass_arg2(this, arg_2);
886 pass_arg1(this, arg_1);
887 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
888 }
889
890 void MacroAssembler::call_VM(Register oop_result,
891 Register last_java_sp,
892 address entry_point,
893 Register arg_1,
894 Register arg_2,
895 Register arg_3,
896 bool check_exceptions) {
897 assert(arg_1 != c_rarg3, "smashed arg");
898 assert(arg_2 != c_rarg3, "smashed arg");
899 pass_arg3(this, arg_3);
900 assert(arg_1 != c_rarg2, "smashed arg");
901 pass_arg2(this, arg_2);
902 pass_arg1(this, arg_1);
903 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
904 }
905
906
907 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
908 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
909 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
910 verify_oop(oop_result, "broken oop in call_VM_base");
911 }
912
913 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
914 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
915 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
916 }
917
918 void MacroAssembler::align(int modulus) {
919 while (offset() % modulus != 0) nop();
920 }
921
922 // these are no-ops overridden by InterpreterMacroAssembler
923
924 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
925
926 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
927
928
929 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
930 Register tmp,
931 int offset) {
932 intptr_t value = *delayed_value_addr;
933 if (value != 0)
934 return RegisterOrConstant(value + offset);
935
936 // load indirectly to solve generation ordering problem
937 ldr(tmp, ExternalAddress((address) delayed_value_addr));
938
939 if (offset != 0)
940 add(tmp, tmp, offset);
941
942 return RegisterOrConstant(tmp);
943 }
944
945
946 void MacroAssembler:: notify(int type) {
947 if (type == bytecode_start) {
948 // set_last_Java_frame(esp, rfp, (address)NULL);
949 Assembler:: notify(type);
950 // reset_last_Java_frame(true);
951 }
952 else
953 Assembler:: notify(type);
954 }
955
956 // Look up the method for a megamorphic invokeinterface call.
957 // The target method is determined by <intf_klass, itable_index>.
958 // The receiver klass is in recv_klass.
959 // On success, the result will be in method_result, and execution falls through.
960 // On failure, execution transfers to the given label.
961 void MacroAssembler::lookup_interface_method(Register recv_klass,
962 Register intf_klass,
963 RegisterOrConstant itable_index,
964 Register method_result,
965 Register scan_temp,
966 Label& L_no_such_interface,
967 bool return_method) {
968 assert_different_registers(recv_klass, intf_klass, scan_temp);
969 assert_different_registers(method_result, intf_klass, scan_temp);
970 assert(recv_klass != method_result || !return_method,
971 "recv_klass can be destroyed when method isn't needed");
972 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
973 "caller must use same register for non-constant itable index as for method");
974
975 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
976 int vtable_base = in_bytes(Klass::vtable_start_offset());
977 int itentry_off = itableMethodEntry::method_offset_in_bytes();
978 int scan_step = itableOffsetEntry::size() * wordSize;
979 int vte_size = vtableEntry::size_in_bytes();
980 assert(vte_size == wordSize, "else adjust times_vte_scale");
981
982 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
983
984 // %%% Could store the aligned, prescaled offset in the klassoop.
985 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
986 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
987 add(scan_temp, scan_temp, vtable_base);
988
989 if (return_method) {
990 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
991 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
992 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
993 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
994 if (itentry_off)
995 add(recv_klass, recv_klass, itentry_off);
996 }
997
998 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
999 // if (scan->interface() == intf) {
1000 // result = (klass + scan->offset() + itable_index);
1001 // }
1002 // }
1003 Label search, found_method;
1004
1005 for (int peel = 1; peel >= 0; peel--) {
1006 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
1007 cmp(intf_klass, method_result);
1008
1009 if (peel) {
1010 br(Assembler::EQ, found_method);
1011 } else {
1012 br(Assembler::NE, search);
1013 // (invert the test to fall through to found_method...)
1014 }
1015
1016 if (!peel) break;
1017
1018 bind(search);
1019
1020 // Check that the previous entry is non-null. A null entry means that
1021 // the receiver class doesn't implement the interface, and wasn't the
1022 // same as when the caller was compiled.
1023 cbz(method_result, L_no_such_interface);
1024 add(scan_temp, scan_temp, scan_step);
1025 }
1026
1027 bind(found_method);
1028
1029 // Got a hit.
1030 if (return_method) {
1031 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
1032 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1033 }
1034 }
1035
1036 // virtual method calling
1037 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1038 RegisterOrConstant vtable_index,
1039 Register method_result) {
1040 const int base = in_bytes(Klass::vtable_start_offset());
1041 assert(vtableEntry::size() * wordSize == 8,
1042 "adjust the scaling in the code below");
1043 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
1044
1045 if (vtable_index.is_register()) {
1046 lea(method_result, Address(recv_klass,
1047 vtable_index.as_register(),
1048 Address::lsl(LogBytesPerWord)));
1049 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1050 } else {
1051 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1052 ldr(method_result,
1053 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1054 }
1055 }
1056
1057 void MacroAssembler::check_klass_subtype(Register sub_klass,
1058 Register super_klass,
1059 Register temp_reg,
1060 Label& L_success) {
1061 Label L_failure;
1062 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
1063 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
1064 bind(L_failure);
1065 }
1066
1067
1068 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1069 Register super_klass,
1070 Register temp_reg,
1071 Label* L_success,
1072 Label* L_failure,
1073 Label* L_slow_path,
1074 RegisterOrConstant super_check_offset) {
1075 assert_different_registers(sub_klass, super_klass, temp_reg);
1076 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1077 if (super_check_offset.is_register()) {
1078 assert_different_registers(sub_klass, super_klass,
1079 super_check_offset.as_register());
1080 } else if (must_load_sco) {
1081 assert(temp_reg != noreg, "supply either a temp or a register offset");
1082 }
1083
1084 Label L_fallthrough;
1085 int label_nulls = 0;
1086 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1087 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1088 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1089 assert(label_nulls <= 1, "at most one NULL in the batch");
1090
1091 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1092 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1093 Address super_check_offset_addr(super_klass, sco_offset);
1094
1095 // Hacked jmp, which may only be used just before L_fallthrough.
1096 #define final_jmp(label) \
1097 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1098 else b(label) /*omit semi*/
1099
1100 // If the pointers are equal, we are done (e.g., String[] elements).
1101 // This self-check enables sharing of secondary supertype arrays among
1102 // non-primary types such as array-of-interface. Otherwise, each such
1103 // type would need its own customized SSA.
1104 // We move this check to the front of the fast path because many
1105 // type checks are in fact trivially successful in this manner,
1106 // so we get a nicely predicted branch right at the start of the check.
1107 cmp(sub_klass, super_klass);
1108 br(Assembler::EQ, *L_success);
1109
1110 // Check the supertype display:
1111 if (must_load_sco) {
1112 ldrw(temp_reg, super_check_offset_addr);
1113 super_check_offset = RegisterOrConstant(temp_reg);
1114 }
1115 Address super_check_addr(sub_klass, super_check_offset);
1116 ldr(rscratch1, super_check_addr);
1117 cmp(super_klass, rscratch1); // load displayed supertype
1118
1119 // This check has worked decisively for primary supers.
1120 // Secondary supers are sought in the super_cache ('super_cache_addr').
1121 // (Secondary supers are interfaces and very deeply nested subtypes.)
1122 // This works in the same check above because of a tricky aliasing
1123 // between the super_cache and the primary super display elements.
1124 // (The 'super_check_addr' can address either, as the case requires.)
1125 // Note that the cache is updated below if it does not help us find
1126 // what we need immediately.
1127 // So if it was a primary super, we can just fail immediately.
1128 // Otherwise, it's the slow path for us (no success at this point).
1129
1130 if (super_check_offset.is_register()) {
1131 br(Assembler::EQ, *L_success);
1132 cmp(super_check_offset.as_register(), sc_offset);
1133 if (L_failure == &L_fallthrough) {
1134 br(Assembler::EQ, *L_slow_path);
1135 } else {
1136 br(Assembler::NE, *L_failure);
1137 final_jmp(*L_slow_path);
1138 }
1139 } else if (super_check_offset.as_constant() == sc_offset) {
1140 // Need a slow path; fast failure is impossible.
1141 if (L_slow_path == &L_fallthrough) {
1142 br(Assembler::EQ, *L_success);
1143 } else {
1144 br(Assembler::NE, *L_slow_path);
1145 final_jmp(*L_success);
1146 }
1147 } else {
1148 // No slow path; it's a fast decision.
1149 if (L_failure == &L_fallthrough) {
1150 br(Assembler::EQ, *L_success);
1151 } else {
1152 br(Assembler::NE, *L_failure);
1153 final_jmp(*L_success);
1154 }
1155 }
1156
1157 bind(L_fallthrough);
1158
1159 #undef final_jmp
1160 }
1161
1162 // These two are taken from x86, but they look generally useful
1163
1164 // scans count pointer sized words at [addr] for occurence of value,
1165 // generic
1166 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1167 Register scratch) {
1168 Label Lloop, Lexit;
1169 cbz(count, Lexit);
1170 bind(Lloop);
1171 ldr(scratch, post(addr, wordSize));
1172 cmp(value, scratch);
1173 br(EQ, Lexit);
1174 sub(count, count, 1);
1175 cbnz(count, Lloop);
1176 bind(Lexit);
1177 }
1178
1179 // scans count 4 byte words at [addr] for occurence of value,
1180 // generic
1181 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1182 Register scratch) {
1183 Label Lloop, Lexit;
1184 cbz(count, Lexit);
1185 bind(Lloop);
1186 ldrw(scratch, post(addr, wordSize));
1187 cmpw(value, scratch);
1188 br(EQ, Lexit);
1189 sub(count, count, 1);
1190 cbnz(count, Lloop);
1191 bind(Lexit);
1192 }
1193
1194 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1195 Register super_klass,
1196 Register temp_reg,
1197 Register temp2_reg,
1198 Label* L_success,
1199 Label* L_failure,
1200 bool set_cond_codes) {
1201 assert_different_registers(sub_klass, super_klass, temp_reg);
1202 if (temp2_reg != noreg)
1203 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1204 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1205
1206 Label L_fallthrough;
1207 int label_nulls = 0;
1208 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1209 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1210 assert(label_nulls <= 1, "at most one NULL in the batch");
1211
1212 // a couple of useful fields in sub_klass:
1213 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1214 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1215 Address secondary_supers_addr(sub_klass, ss_offset);
1216 Address super_cache_addr( sub_klass, sc_offset);
1217
1218 BLOCK_COMMENT("check_klass_subtype_slow_path");
1219
1220 // Do a linear scan of the secondary super-klass chain.
1221 // This code is rarely used, so simplicity is a virtue here.
1222 // The repne_scan instruction uses fixed registers, which we must spill.
1223 // Don't worry too much about pre-existing connections with the input regs.
1224
1225 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1226 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1227
1228 RegSet pushed_registers;
1229 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1230 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1231
1232 if (super_klass != r0 || UseCompressedOops) {
1233 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1234 }
1235
1236 push(pushed_registers, sp);
1237
1238 // Get super_klass value into r0 (even if it was in r5 or r2).
1239 if (super_klass != r0) {
1240 mov(r0, super_klass);
1241 }
1242
1243 #ifndef PRODUCT
1244 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1245 Address pst_counter_addr(rscratch2);
1246 ldr(rscratch1, pst_counter_addr);
1247 add(rscratch1, rscratch1, 1);
1248 str(rscratch1, pst_counter_addr);
1249 #endif //PRODUCT
1250
1251 // We will consult the secondary-super array.
1252 ldr(r5, secondary_supers_addr);
1253 // Load the array length.
1254 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1255 // Skip to start of data.
1256 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1257
1258 cmp(sp, zr); // Clear Z flag; SP is never zero
1259 // Scan R2 words at [R5] for an occurrence of R0.
1260 // Set NZ/Z based on last compare.
1261 repne_scan(r5, r0, r2, rscratch1);
1262
1263 // Unspill the temp. registers:
1264 pop(pushed_registers, sp);
1265
1266 br(Assembler::NE, *L_failure);
1267
1268 // Success. Cache the super we found and proceed in triumph.
1269 str(super_klass, super_cache_addr);
1270
1271 if (L_success != &L_fallthrough) {
1272 b(*L_success);
1273 }
1274
1275 #undef IS_A_TEMP
1276
1277 bind(L_fallthrough);
1278 }
1279
1280
1281 void MacroAssembler::verify_oop(Register reg, const char* s) {
1282 if (!VerifyOops) return;
1283
1284 // Pass register number to verify_oop_subroutine
1285 const char* b = NULL;
1286 {
1287 ResourceMark rm;
1288 stringStream ss;
1289 ss.print("verify_oop: %s: %s", reg->name(), s);
1290 b = code_string(ss.as_string());
1291 }
1292 BLOCK_COMMENT("verify_oop {");
1293
1294 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1295 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1296
1297 mov(r0, reg);
1298 mov(rscratch1, (address)b);
1299
1300 // call indirectly to solve generation ordering problem
1301 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1302 ldr(rscratch2, Address(rscratch2));
1303 blr(rscratch2);
1304
1305 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1306 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1307
1308 BLOCK_COMMENT("} verify_oop");
1309 }
1310
1311 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1312 if (!VerifyOops) return;
1313
1314 const char* b = NULL;
1315 {
1316 ResourceMark rm;
1317 stringStream ss;
1318 ss.print("verify_oop_addr: %s", s);
1319 b = code_string(ss.as_string());
1320 }
1321 BLOCK_COMMENT("verify_oop_addr {");
1322
1323 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1324 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1325
1326 // addr may contain sp so we will have to adjust it based on the
1327 // pushes that we just did.
1328 if (addr.uses(sp)) {
1329 lea(r0, addr);
1330 ldr(r0, Address(r0, 4 * wordSize));
1331 } else {
1332 ldr(r0, addr);
1333 }
1334 mov(rscratch1, (address)b);
1335
1336 // call indirectly to solve generation ordering problem
1337 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1338 ldr(rscratch2, Address(rscratch2));
1339 blr(rscratch2);
1340
1341 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1342 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1343
1344 BLOCK_COMMENT("} verify_oop_addr");
1345 }
1346
1347 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1348 int extra_slot_offset) {
1349 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1350 int stackElementSize = Interpreter::stackElementSize;
1351 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1352 #ifdef ASSERT
1353 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1354 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1355 #endif
1356 if (arg_slot.is_constant()) {
1357 return Address(esp, arg_slot.as_constant() * stackElementSize
1358 + offset);
1359 } else {
1360 add(rscratch1, esp, arg_slot.as_register(),
1361 ext::uxtx, exact_log2(stackElementSize));
1362 return Address(rscratch1, offset);
1363 }
1364 }
1365
1366 void MacroAssembler::call_VM_leaf_base(address entry_point,
1367 int number_of_arguments,
1368 Label *retaddr) {
1369 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1370 }
1371
1372 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1373 int number_of_gp_arguments,
1374 int number_of_fp_arguments,
1375 ret_type type,
1376 Label *retaddr) {
1377 Label E, L;
1378
1379 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1380
1381 // We add 1 to number_of_arguments because the thread in arg0 is
1382 // not counted
1383 mov(rscratch1, entry_point);
1384 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1385 if (retaddr)
1386 bind(*retaddr);
1387
1388 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1389 maybe_isb();
1390 }
1391
1392 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1393 call_VM_leaf_base(entry_point, number_of_arguments);
1394 }
1395
1396 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1397 pass_arg0(this, arg_0);
1398 call_VM_leaf_base(entry_point, 1);
1399 }
1400
1401 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1402 pass_arg0(this, arg_0);
1403 pass_arg1(this, arg_1);
1404 call_VM_leaf_base(entry_point, 2);
1405 }
1406
1407 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1408 Register arg_1, Register arg_2) {
1409 pass_arg0(this, arg_0);
1410 pass_arg1(this, arg_1);
1411 pass_arg2(this, arg_2);
1412 call_VM_leaf_base(entry_point, 3);
1413 }
1414
1415 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1416 pass_arg0(this, arg_0);
1417 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1418 }
1419
1420 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1421
1422 assert(arg_0 != c_rarg1, "smashed arg");
1423 pass_arg1(this, arg_1);
1424 pass_arg0(this, arg_0);
1425 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1426 }
1427
1428 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1429 assert(arg_0 != c_rarg2, "smashed arg");
1430 assert(arg_1 != c_rarg2, "smashed arg");
1431 pass_arg2(this, arg_2);
1432 assert(arg_0 != c_rarg1, "smashed arg");
1433 pass_arg1(this, arg_1);
1434 pass_arg0(this, arg_0);
1435 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1436 }
1437
1438 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1439 assert(arg_0 != c_rarg3, "smashed arg");
1440 assert(arg_1 != c_rarg3, "smashed arg");
1441 assert(arg_2 != c_rarg3, "smashed arg");
1442 pass_arg3(this, arg_3);
1443 assert(arg_0 != c_rarg2, "smashed arg");
1444 assert(arg_1 != c_rarg2, "smashed arg");
1445 pass_arg2(this, arg_2);
1446 assert(arg_0 != c_rarg1, "smashed arg");
1447 pass_arg1(this, arg_1);
1448 pass_arg0(this, arg_0);
1449 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1450 }
1451
1452 void MacroAssembler::null_check(Register reg, int offset) {
1453 if (needs_explicit_null_check(offset)) {
1454 // provoke OS NULL exception if reg = NULL by
1455 // accessing M[reg] w/o changing any registers
1456 // NOTE: this is plenty to provoke a segv
1457 ldr(zr, Address(reg));
1458 } else {
1459 // nothing to do, (later) access of M[reg + offset]
1460 // will provoke OS NULL exception if reg = NULL
1461 }
1462 }
1463
1464 // MacroAssembler protected routines needed to implement
1465 // public methods
1466
1467 void MacroAssembler::mov(Register r, Address dest) {
1468 code_section()->relocate(pc(), dest.rspec());
1469 u_int64_t imm64 = (u_int64_t)dest.target();
1470 movptr(r, imm64);
1471 }
1472
1473 // Move a constant pointer into r. In AArch64 mode the virtual
1474 // address space is 48 bits in size, so we only need three
1475 // instructions to create a patchable instruction sequence that can
1476 // reach anywhere.
1477 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1478 #ifndef PRODUCT
1479 {
1480 char buffer[64];
1481 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1482 block_comment(buffer);
1483 }
1484 #endif
1485 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1486 movz(r, imm64 & 0xffff);
1487 imm64 >>= 16;
1488 movk(r, imm64 & 0xffff, 16);
1489 imm64 >>= 16;
1490 movk(r, imm64 & 0xffff, 32);
1491 }
1492
1493 // Macro to mov replicated immediate to vector register.
1494 // Vd will get the following values for different arrangements in T
1495 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1496 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1497 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1498 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1499 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1500 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1501 // T1D/T2D: invalid
1502 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1503 assert(T != T1D && T != T2D, "invalid arrangement");
1504 if (T == T8B || T == T16B) {
1505 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1506 movi(Vd, T, imm32 & 0xff, 0);
1507 return;
1508 }
1509 u_int32_t nimm32 = ~imm32;
1510 if (T == T4H || T == T8H) {
1511 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1512 imm32 &= 0xffff;
1513 nimm32 &= 0xffff;
1514 }
1515 u_int32_t x = imm32;
1516 int movi_cnt = 0;
1517 int movn_cnt = 0;
1518 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1519 x = nimm32;
1520 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1521 if (movn_cnt < movi_cnt) imm32 = nimm32;
1522 unsigned lsl = 0;
1523 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1524 if (movn_cnt < movi_cnt)
1525 mvni(Vd, T, imm32 & 0xff, lsl);
1526 else
1527 movi(Vd, T, imm32 & 0xff, lsl);
1528 imm32 >>= 8; lsl += 8;
1529 while (imm32) {
1530 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1531 if (movn_cnt < movi_cnt)
1532 bici(Vd, T, imm32 & 0xff, lsl);
1533 else
1534 orri(Vd, T, imm32 & 0xff, lsl);
1535 lsl += 8; imm32 >>= 8;
1536 }
1537 }
1538
1539 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1540 {
1541 #ifndef PRODUCT
1542 {
1543 char buffer[64];
1544 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1545 block_comment(buffer);
1546 }
1547 #endif
1548 if (operand_valid_for_logical_immediate(false, imm64)) {
1549 orr(dst, zr, imm64);
1550 } else {
1551 // we can use a combination of MOVZ or MOVN with
1552 // MOVK to build up the constant
1553 u_int64_t imm_h[4];
1554 int zero_count = 0;
1555 int neg_count = 0;
1556 int i;
1557 for (i = 0; i < 4; i++) {
1558 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1559 if (imm_h[i] == 0) {
1560 zero_count++;
1561 } else if (imm_h[i] == 0xffffL) {
1562 neg_count++;
1563 }
1564 }
1565 if (zero_count == 4) {
1566 // one MOVZ will do
1567 movz(dst, 0);
1568 } else if (neg_count == 4) {
1569 // one MOVN will do
1570 movn(dst, 0);
1571 } else if (zero_count == 3) {
1572 for (i = 0; i < 4; i++) {
1573 if (imm_h[i] != 0L) {
1574 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1575 break;
1576 }
1577 }
1578 } else if (neg_count == 3) {
1579 // one MOVN will do
1580 for (int i = 0; i < 4; i++) {
1581 if (imm_h[i] != 0xffffL) {
1582 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1583 break;
1584 }
1585 }
1586 } else if (zero_count == 2) {
1587 // one MOVZ and one MOVK will do
1588 for (i = 0; i < 3; i++) {
1589 if (imm_h[i] != 0L) {
1590 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1591 i++;
1592 break;
1593 }
1594 }
1595 for (;i < 4; i++) {
1596 if (imm_h[i] != 0L) {
1597 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1598 }
1599 }
1600 } else if (neg_count == 2) {
1601 // one MOVN and one MOVK will do
1602 for (i = 0; i < 4; i++) {
1603 if (imm_h[i] != 0xffffL) {
1604 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1605 i++;
1606 break;
1607 }
1608 }
1609 for (;i < 4; i++) {
1610 if (imm_h[i] != 0xffffL) {
1611 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1612 }
1613 }
1614 } else if (zero_count == 1) {
1615 // one MOVZ and two MOVKs will do
1616 for (i = 0; i < 4; i++) {
1617 if (imm_h[i] != 0L) {
1618 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1619 i++;
1620 break;
1621 }
1622 }
1623 for (;i < 4; i++) {
1624 if (imm_h[i] != 0x0L) {
1625 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1626 }
1627 }
1628 } else if (neg_count == 1) {
1629 // one MOVN and two MOVKs will do
1630 for (i = 0; i < 4; i++) {
1631 if (imm_h[i] != 0xffffL) {
1632 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1633 i++;
1634 break;
1635 }
1636 }
1637 for (;i < 4; i++) {
1638 if (imm_h[i] != 0xffffL) {
1639 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1640 }
1641 }
1642 } else {
1643 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1644 movz(dst, (u_int32_t)imm_h[0], 0);
1645 for (i = 1; i < 4; i++) {
1646 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1647 }
1648 }
1649 }
1650 }
1651
1652 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1653 {
1654 #ifndef PRODUCT
1655 {
1656 char buffer[64];
1657 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1658 block_comment(buffer);
1659 }
1660 #endif
1661 if (operand_valid_for_logical_immediate(true, imm32)) {
1662 orrw(dst, zr, imm32);
1663 } else {
1664 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1665 // constant
1666 u_int32_t imm_h[2];
1667 imm_h[0] = imm32 & 0xffff;
1668 imm_h[1] = ((imm32 >> 16) & 0xffff);
1669 if (imm_h[0] == 0) {
1670 movzw(dst, imm_h[1], 16);
1671 } else if (imm_h[0] == 0xffff) {
1672 movnw(dst, imm_h[1] ^ 0xffff, 16);
1673 } else if (imm_h[1] == 0) {
1674 movzw(dst, imm_h[0], 0);
1675 } else if (imm_h[1] == 0xffff) {
1676 movnw(dst, imm_h[0] ^ 0xffff, 0);
1677 } else {
1678 // use a MOVZ and MOVK (makes it easier to debug)
1679 movzw(dst, imm_h[0], 0);
1680 movkw(dst, imm_h[1], 16);
1681 }
1682 }
1683 }
1684
1685 // Form an address from base + offset in Rd. Rd may or may
1686 // not actually be used: you must use the Address that is returned.
1687 // It is up to you to ensure that the shift provided matches the size
1688 // of your data.
1689 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1690 if (Address::offset_ok_for_immed(byte_offset, shift))
1691 // It fits; no need for any heroics
1692 return Address(base, byte_offset);
1693
1694 // Don't do anything clever with negative or misaligned offsets
1695 unsigned mask = (1 << shift) - 1;
1696 if (byte_offset < 0 || byte_offset & mask) {
1697 mov(Rd, byte_offset);
1698 add(Rd, base, Rd);
1699 return Address(Rd);
1700 }
1701
1702 // See if we can do this with two 12-bit offsets
1703 {
1704 unsigned long word_offset = byte_offset >> shift;
1705 unsigned long masked_offset = word_offset & 0xfff000;
1706 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1707 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1708 add(Rd, base, masked_offset << shift);
1709 word_offset -= masked_offset;
1710 return Address(Rd, word_offset << shift);
1711 }
1712 }
1713
1714 // Do it the hard way
1715 mov(Rd, byte_offset);
1716 add(Rd, base, Rd);
1717 return Address(Rd);
1718 }
1719
1720 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1721 if (UseLSE) {
1722 mov(tmp, 1);
1723 ldadd(Assembler::word, tmp, zr, counter_addr);
1724 return;
1725 }
1726 Label retry_load;
1727 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
1728 prfm(Address(counter_addr), PSTL1STRM);
1729 bind(retry_load);
1730 // flush and load exclusive from the memory location
1731 ldxrw(tmp, counter_addr);
1732 addw(tmp, tmp, 1);
1733 // if we store+flush with no intervening write tmp wil be zero
1734 stxrw(tmp2, tmp, counter_addr);
1735 cbnzw(tmp2, retry_load);
1736 }
1737
1738
1739 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1740 bool want_remainder, Register scratch)
1741 {
1742 // Full implementation of Java idiv and irem. The function
1743 // returns the (pc) offset of the div instruction - may be needed
1744 // for implicit exceptions.
1745 //
1746 // constraint : ra/rb =/= scratch
1747 // normal case
1748 //
1749 // input : ra: dividend
1750 // rb: divisor
1751 //
1752 // result: either
1753 // quotient (= ra idiv rb)
1754 // remainder (= ra irem rb)
1755
1756 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1757
1758 int idivl_offset = offset();
1759 if (! want_remainder) {
1760 sdivw(result, ra, rb);
1761 } else {
1762 sdivw(scratch, ra, rb);
1763 Assembler::msubw(result, scratch, rb, ra);
1764 }
1765
1766 return idivl_offset;
1767 }
1768
1769 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1770 bool want_remainder, Register scratch)
1771 {
1772 // Full implementation of Java ldiv and lrem. The function
1773 // returns the (pc) offset of the div instruction - may be needed
1774 // for implicit exceptions.
1775 //
1776 // constraint : ra/rb =/= scratch
1777 // normal case
1778 //
1779 // input : ra: dividend
1780 // rb: divisor
1781 //
1782 // result: either
1783 // quotient (= ra idiv rb)
1784 // remainder (= ra irem rb)
1785
1786 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1787
1788 int idivq_offset = offset();
1789 if (! want_remainder) {
1790 sdiv(result, ra, rb);
1791 } else {
1792 sdiv(scratch, ra, rb);
1793 Assembler::msub(result, scratch, rb, ra);
1794 }
1795
1796 return idivq_offset;
1797 }
1798
1799 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1800 address prev = pc() - NativeMembar::instruction_size;
1801 address last = code()->last_insn();
1802 if (last != NULL && nativeInstruction_at(last)->is_Membar() && prev == last) {
1803 NativeMembar *bar = NativeMembar_at(prev);
1804 // We are merging two memory barrier instructions. On AArch64 we
1805 // can do this simply by ORing them together.
1806 bar->set_kind(bar->get_kind() | order_constraint);
1807 BLOCK_COMMENT("merged membar");
1808 } else {
1809 code()->set_last_insn(pc());
1810 dmb(Assembler::barrier(order_constraint));
1811 }
1812 }
1813
1814 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
1815 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
1816 merge_ldst(rt, adr, size_in_bytes, is_store);
1817 code()->clear_last_insn();
1818 return true;
1819 } else {
1820 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
1821 const unsigned mask = size_in_bytes - 1;
1822 if (adr.getMode() == Address::base_plus_offset &&
1823 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
1824 code()->set_last_insn(pc());
1825 }
1826 return false;
1827 }
1828 }
1829
1830 void MacroAssembler::ldr(Register Rx, const Address &adr) {
1831 // We always try to merge two adjacent loads into one ldp.
1832 if (!try_merge_ldst(Rx, adr, 8, false)) {
1833 Assembler::ldr(Rx, adr);
1834 }
1835 }
1836
1837 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
1838 // We always try to merge two adjacent loads into one ldp.
1839 if (!try_merge_ldst(Rw, adr, 4, false)) {
1840 Assembler::ldrw(Rw, adr);
1841 }
1842 }
1843
1844 void MacroAssembler::str(Register Rx, const Address &adr) {
1845 // We always try to merge two adjacent stores into one stp.
1846 if (!try_merge_ldst(Rx, adr, 8, true)) {
1847 Assembler::str(Rx, adr);
1848 }
1849 }
1850
1851 void MacroAssembler::strw(Register Rw, const Address &adr) {
1852 // We always try to merge two adjacent stores into one stp.
1853 if (!try_merge_ldst(Rw, adr, 4, true)) {
1854 Assembler::strw(Rw, adr);
1855 }
1856 }
1857
1858 // MacroAssembler routines found actually to be needed
1859
1860 void MacroAssembler::push(Register src)
1861 {
1862 str(src, Address(pre(esp, -1 * wordSize)));
1863 }
1864
1865 void MacroAssembler::pop(Register dst)
1866 {
1867 ldr(dst, Address(post(esp, 1 * wordSize)));
1868 }
1869
1870 // Note: load_unsigned_short used to be called load_unsigned_word.
1871 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1872 int off = offset();
1873 ldrh(dst, src);
1874 return off;
1875 }
1876
1877 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1878 int off = offset();
1879 ldrb(dst, src);
1880 return off;
1881 }
1882
1883 int MacroAssembler::load_signed_short(Register dst, Address src) {
1884 int off = offset();
1885 ldrsh(dst, src);
1886 return off;
1887 }
1888
1889 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1890 int off = offset();
1891 ldrsb(dst, src);
1892 return off;
1893 }
1894
1895 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1896 int off = offset();
1897 ldrshw(dst, src);
1898 return off;
1899 }
1900
1901 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1902 int off = offset();
1903 ldrsbw(dst, src);
1904 return off;
1905 }
1906
1907 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1908 switch (size_in_bytes) {
1909 case 8: ldr(dst, src); break;
1910 case 4: ldrw(dst, src); break;
1911 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1912 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1913 default: ShouldNotReachHere();
1914 }
1915 }
1916
1917 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1918 switch (size_in_bytes) {
1919 case 8: str(src, dst); break;
1920 case 4: strw(src, dst); break;
1921 case 2: strh(src, dst); break;
1922 case 1: strb(src, dst); break;
1923 default: ShouldNotReachHere();
1924 }
1925 }
1926
1927 void MacroAssembler::decrementw(Register reg, int value)
1928 {
1929 if (value < 0) { incrementw(reg, -value); return; }
1930 if (value == 0) { return; }
1931 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1932 /* else */ {
1933 guarantee(reg != rscratch2, "invalid dst for register decrement");
1934 movw(rscratch2, (unsigned)value);
1935 subw(reg, reg, rscratch2);
1936 }
1937 }
1938
1939 void MacroAssembler::decrement(Register reg, int value)
1940 {
1941 if (value < 0) { increment(reg, -value); return; }
1942 if (value == 0) { return; }
1943 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1944 /* else */ {
1945 assert(reg != rscratch2, "invalid dst for register decrement");
1946 mov(rscratch2, (unsigned long)value);
1947 sub(reg, reg, rscratch2);
1948 }
1949 }
1950
1951 void MacroAssembler::decrementw(Address dst, int value)
1952 {
1953 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1954 if (dst.getMode() == Address::literal) {
1955 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
1956 lea(rscratch2, dst);
1957 dst = Address(rscratch2);
1958 }
1959 ldrw(rscratch1, dst);
1960 decrementw(rscratch1, value);
1961 strw(rscratch1, dst);
1962 }
1963
1964 void MacroAssembler::decrement(Address dst, int value)
1965 {
1966 assert(!dst.uses(rscratch1), "invalid address for decrement");
1967 if (dst.getMode() == Address::literal) {
1968 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
1969 lea(rscratch2, dst);
1970 dst = Address(rscratch2);
1971 }
1972 ldr(rscratch1, dst);
1973 decrement(rscratch1, value);
1974 str(rscratch1, dst);
1975 }
1976
1977 void MacroAssembler::incrementw(Register reg, int value)
1978 {
1979 if (value < 0) { decrementw(reg, -value); return; }
1980 if (value == 0) { return; }
1981 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1982 /* else */ {
1983 assert(reg != rscratch2, "invalid dst for register increment");
1984 movw(rscratch2, (unsigned)value);
1985 addw(reg, reg, rscratch2);
1986 }
1987 }
1988
1989 void MacroAssembler::increment(Register reg, int value)
1990 {
1991 if (value < 0) { decrement(reg, -value); return; }
1992 if (value == 0) { return; }
1993 if (value < (1 << 12)) { add(reg, reg, value); return; }
1994 /* else */ {
1995 assert(reg != rscratch2, "invalid dst for register increment");
1996 movw(rscratch2, (unsigned)value);
1997 add(reg, reg, rscratch2);
1998 }
1999 }
2000
2001 void MacroAssembler::incrementw(Address dst, int value)
2002 {
2003 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2004 if (dst.getMode() == Address::literal) {
2005 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2006 lea(rscratch2, dst);
2007 dst = Address(rscratch2);
2008 }
2009 ldrw(rscratch1, dst);
2010 incrementw(rscratch1, value);
2011 strw(rscratch1, dst);
2012 }
2013
2014 void MacroAssembler::increment(Address dst, int value)
2015 {
2016 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2017 if (dst.getMode() == Address::literal) {
2018 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2019 lea(rscratch2, dst);
2020 dst = Address(rscratch2);
2021 }
2022 ldr(rscratch1, dst);
2023 increment(rscratch1, value);
2024 str(rscratch1, dst);
2025 }
2026
2027
2028 void MacroAssembler::pusha() {
2029 push(0x7fffffff, sp);
2030 }
2031
2032 void MacroAssembler::popa() {
2033 pop(0x7fffffff, sp);
2034 }
2035
2036 // Push lots of registers in the bit set supplied. Don't push sp.
2037 // Return the number of words pushed
2038 int MacroAssembler::push(unsigned int bitset, Register stack) {
2039 int words_pushed = 0;
2040
2041 // Scan bitset to accumulate register pairs
2042 unsigned char regs[32];
2043 int count = 0;
2044 for (int reg = 0; reg <= 30; reg++) {
2045 if (1 & bitset)
2046 regs[count++] = reg;
2047 bitset >>= 1;
2048 }
2049 regs[count++] = zr->encoding_nocheck();
2050 count &= ~1; // Only push an even nuber of regs
2051
2052 if (count) {
2053 stp(as_Register(regs[0]), as_Register(regs[1]),
2054 Address(pre(stack, -count * wordSize)));
2055 words_pushed += 2;
2056 }
2057 for (int i = 2; i < count; i += 2) {
2058 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2059 Address(stack, i * wordSize));
2060 words_pushed += 2;
2061 }
2062
2063 assert(words_pushed == count, "oops, pushed != count");
2064
2065 return count;
2066 }
2067
2068 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2069 int words_pushed = 0;
2070
2071 // Scan bitset to accumulate register pairs
2072 unsigned char regs[32];
2073 int count = 0;
2074 for (int reg = 0; reg <= 30; reg++) {
2075 if (1 & bitset)
2076 regs[count++] = reg;
2077 bitset >>= 1;
2078 }
2079 regs[count++] = zr->encoding_nocheck();
2080 count &= ~1;
2081
2082 for (int i = 2; i < count; i += 2) {
2083 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2084 Address(stack, i * wordSize));
2085 words_pushed += 2;
2086 }
2087 if (count) {
2088 ldp(as_Register(regs[0]), as_Register(regs[1]),
2089 Address(post(stack, count * wordSize)));
2090 words_pushed += 2;
2091 }
2092
2093 assert(words_pushed == count, "oops, pushed != count");
2094
2095 return count;
2096 }
2097 #ifdef ASSERT
2098 void MacroAssembler::verify_heapbase(const char* msg) {
2099 #if 0
2100 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
2101 assert (Universe::heap() != NULL, "java heap should be initialized");
2102 if (CheckCompressedOops) {
2103 Label ok;
2104 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
2105 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2106 br(Assembler::EQ, ok);
2107 stop(msg);
2108 bind(ok);
2109 pop(1 << rscratch1->encoding(), sp);
2110 }
2111 #endif
2112 }
2113 #endif
2114
2115 void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) {
2116 Label done, not_weak;
2117 cbz(value, done); // Use NULL as-is.
2118
2119 STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
2120 tbz(r0, 0, not_weak); // Test for jweak tag.
2121
2122 // Resolve jweak.
2123 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, value,
2124 Address(value, -JNIHandles::weak_tag_value), tmp, thread);
2125 verify_oop(value);
2126 b(done);
2127
2128 bind(not_weak);
2129 // Resolve (untagged) jobject.
2130 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, value, Address(value, 0), tmp,
2131 thread);
2132 verify_oop(value);
2133 bind(done);
2134 }
2135
2136 void MacroAssembler::stop(const char* msg) {
2137 address ip = pc();
2138 pusha();
2139 mov(c_rarg0, (address)msg);
2140 mov(c_rarg1, (address)ip);
2141 mov(c_rarg2, sp);
2142 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
2143 // call(c_rarg3);
2144 blrt(c_rarg3, 3, 0, 1);
2145 hlt(0);
2146 }
2147
2148 void MacroAssembler::unimplemented(const char* what) {
2149 const char* buf = NULL;
2150 {
2151 ResourceMark rm;
2152 stringStream ss;
2153 ss.print("unimplemented: %s", what);
2154 buf = code_string(ss.as_string());
2155 }
2156 stop(buf);
2157 }
2158
2159 // If a constant does not fit in an immediate field, generate some
2160 // number of MOV instructions and then perform the operation.
2161 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
2162 add_sub_imm_insn insn1,
2163 add_sub_reg_insn insn2) {
2164 assert(Rd != zr, "Rd = zr and not setting flags?");
2165 if (operand_valid_for_add_sub_immediate((int)imm)) {
2166 (this->*insn1)(Rd, Rn, imm);
2167 } else {
2168 if (uabs(imm) < (1 << 24)) {
2169 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
2170 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
2171 } else {
2172 assert_different_registers(Rd, Rn);
2173 mov(Rd, (uint64_t)imm);
2174 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2175 }
2176 }
2177 }
2178
2179 // Seperate vsn which sets the flags. Optimisations are more restricted
2180 // because we must set the flags correctly.
2181 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
2182 add_sub_imm_insn insn1,
2183 add_sub_reg_insn insn2) {
2184 if (operand_valid_for_add_sub_immediate((int)imm)) {
2185 (this->*insn1)(Rd, Rn, imm);
2186 } else {
2187 assert_different_registers(Rd, Rn);
2188 assert(Rd != zr, "overflow in immediate operand");
2189 mov(Rd, (uint64_t)imm);
2190 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2191 }
2192 }
2193
2194
2195 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2196 if (increment.is_register()) {
2197 add(Rd, Rn, increment.as_register());
2198 } else {
2199 add(Rd, Rn, increment.as_constant());
2200 }
2201 }
2202
2203 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2204 if (increment.is_register()) {
2205 addw(Rd, Rn, increment.as_register());
2206 } else {
2207 addw(Rd, Rn, increment.as_constant());
2208 }
2209 }
2210
2211 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2212 if (decrement.is_register()) {
2213 sub(Rd, Rn, decrement.as_register());
2214 } else {
2215 sub(Rd, Rn, decrement.as_constant());
2216 }
2217 }
2218
2219 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2220 if (decrement.is_register()) {
2221 subw(Rd, Rn, decrement.as_register());
2222 } else {
2223 subw(Rd, Rn, decrement.as_constant());
2224 }
2225 }
2226
2227 void MacroAssembler::reinit_heapbase()
2228 {
2229 if (UseCompressedOops) {
2230 if (Universe::is_fully_initialized()) {
2231 mov(rheapbase, Universe::narrow_ptrs_base());
2232 } else {
2233 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2234 ldr(rheapbase, Address(rheapbase));
2235 }
2236 }
2237 }
2238
2239 // this simulates the behaviour of the x86 cmpxchg instruction using a
2240 // load linked/store conditional pair. we use the acquire/release
2241 // versions of these instructions so that we flush pending writes as
2242 // per Java semantics.
2243
2244 // n.b the x86 version assumes the old value to be compared against is
2245 // in rax and updates rax with the value located in memory if the
2246 // cmpxchg fails. we supply a register for the old value explicitly
2247
2248 // the aarch64 load linked/store conditional instructions do not
2249 // accept an offset. so, unlike x86, we must provide a plain register
2250 // to identify the memory word to be compared/exchanged rather than a
2251 // register+offset Address.
2252
2253 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2254 Label &succeed, Label *fail) {
2255 // oldv holds comparison value
2256 // newv holds value to write in exchange
2257 // addr identifies memory word to compare against/update
2258 if (UseLSE) {
2259 mov(tmp, oldv);
2260 casal(Assembler::xword, oldv, newv, addr);
2261 cmp(tmp, oldv);
2262 br(Assembler::EQ, succeed);
2263 membar(AnyAny);
2264 } else {
2265 Label retry_load, nope;
2266 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2267 prfm(Address(addr), PSTL1STRM);
2268 bind(retry_load);
2269 // flush and load exclusive from the memory location
2270 // and fail if it is not what we expect
2271 ldaxr(tmp, addr);
2272 cmp(tmp, oldv);
2273 br(Assembler::NE, nope);
2274 // if we store+flush with no intervening write tmp wil be zero
2275 stlxr(tmp, newv, addr);
2276 cbzw(tmp, succeed);
2277 // retry so we only ever return after a load fails to compare
2278 // ensures we don't return a stale value after a failed write.
2279 b(retry_load);
2280 // if the memory word differs we return it in oldv and signal a fail
2281 bind(nope);
2282 membar(AnyAny);
2283 mov(oldv, tmp);
2284 }
2285 if (fail)
2286 b(*fail);
2287 }
2288
2289 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
2290 Label &succeed, Label *fail) {
2291 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
2292 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
2293 }
2294
2295 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2296 Label &succeed, Label *fail) {
2297 // oldv holds comparison value
2298 // newv holds value to write in exchange
2299 // addr identifies memory word to compare against/update
2300 // tmp returns 0/1 for success/failure
2301 if (UseLSE) {
2302 mov(tmp, oldv);
2303 casal(Assembler::word, oldv, newv, addr);
2304 cmp(tmp, oldv);
2305 br(Assembler::EQ, succeed);
2306 membar(AnyAny);
2307 } else {
2308 Label retry_load, nope;
2309 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2310 prfm(Address(addr), PSTL1STRM);
2311 bind(retry_load);
2312 // flush and load exclusive from the memory location
2313 // and fail if it is not what we expect
2314 ldaxrw(tmp, addr);
2315 cmp(tmp, oldv);
2316 br(Assembler::NE, nope);
2317 // if we store+flush with no intervening write tmp wil be zero
2318 stlxrw(tmp, newv, addr);
2319 cbzw(tmp, succeed);
2320 // retry so we only ever return after a load fails to compare
2321 // ensures we don't return a stale value after a failed write.
2322 b(retry_load);
2323 // if the memory word differs we return it in oldv and signal a fail
2324 bind(nope);
2325 membar(AnyAny);
2326 mov(oldv, tmp);
2327 }
2328 if (fail)
2329 b(*fail);
2330 }
2331
2332 // A generic CAS; success or failure is in the EQ flag. A weak CAS
2333 // doesn't retry and may fail spuriously. If the oldval is wanted,
2334 // Pass a register for the result, otherwise pass noreg.
2335
2336 // Clobbers rscratch1
2337 void MacroAssembler::cmpxchg(Register addr, Register expected,
2338 Register new_val,
2339 enum operand_size size,
2340 bool acquire, bool release,
2341 bool weak,
2342 Register result) {
2343 if (result == noreg) result = rscratch1;
2344 if (UseLSE) {
2345 mov(result, expected);
2346 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
2347 cmp(result, expected);
2348 } else {
2349 BLOCK_COMMENT("cmpxchg {");
2350 Label retry_load, done;
2351 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2352 prfm(Address(addr), PSTL1STRM);
2353 bind(retry_load);
2354 load_exclusive(result, addr, size, acquire);
2355 if (size == xword)
2356 cmp(result, expected);
2357 else
2358 cmpw(result, expected);
2359 br(Assembler::NE, done);
2360 store_exclusive(rscratch1, new_val, addr, size, release);
2361 if (weak) {
2362 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
2363 } else {
2364 cbnzw(rscratch1, retry_load);
2365 }
2366 bind(done);
2367 BLOCK_COMMENT("} cmpxchg");
2368 }
2369 }
2370
2371 static bool different(Register a, RegisterOrConstant b, Register c) {
2372 if (b.is_constant())
2373 return a != c;
2374 else
2375 return a != b.as_register() && a != c && b.as_register() != c;
2376 }
2377
2378 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
2379 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
2380 if (UseLSE) { \
2381 prev = prev->is_valid() ? prev : zr; \
2382 if (incr.is_register()) { \
2383 AOP(sz, incr.as_register(), prev, addr); \
2384 } else { \
2385 mov(rscratch2, incr.as_constant()); \
2386 AOP(sz, rscratch2, prev, addr); \
2387 } \
2388 return; \
2389 } \
2390 Register result = rscratch2; \
2391 if (prev->is_valid()) \
2392 result = different(prev, incr, addr) ? prev : rscratch2; \
2393 \
2394 Label retry_load; \
2395 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2396 prfm(Address(addr), PSTL1STRM); \
2397 bind(retry_load); \
2398 LDXR(result, addr); \
2399 OP(rscratch1, result, incr); \
2400 STXR(rscratch2, rscratch1, addr); \
2401 cbnzw(rscratch2, retry_load); \
2402 if (prev->is_valid() && prev != result) { \
2403 IOP(prev, rscratch1, incr); \
2404 } \
2405 }
2406
2407 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
2408 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
2409 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
2410 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
2411
2412 #undef ATOMIC_OP
2413
2414 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
2415 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2416 if (UseLSE) { \
2417 prev = prev->is_valid() ? prev : zr; \
2418 AOP(sz, newv, prev, addr); \
2419 return; \
2420 } \
2421 Register result = rscratch2; \
2422 if (prev->is_valid()) \
2423 result = different(prev, newv, addr) ? prev : rscratch2; \
2424 \
2425 Label retry_load; \
2426 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2427 prfm(Address(addr), PSTL1STRM); \
2428 bind(retry_load); \
2429 LDXR(result, addr); \
2430 STXR(rscratch1, newv, addr); \
2431 cbnzw(rscratch1, retry_load); \
2432 if (prev->is_valid() && prev != result) \
2433 mov(prev, result); \
2434 }
2435
2436 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
2437 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
2438 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
2439 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
2440
2441 #undef ATOMIC_XCHG
2442
2443 #ifndef PRODUCT
2444 extern "C" void findpc(intptr_t x);
2445 #endif
2446
2447 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2448 {
2449 // In order to get locks to work, we need to fake a in_VM state
2450 if (ShowMessageBoxOnError ) {
2451 JavaThread* thread = JavaThread::current();
2452 JavaThreadState saved_state = thread->thread_state();
2453 thread->set_thread_state(_thread_in_vm);
2454 #ifndef PRODUCT
2455 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2456 ttyLocker ttyl;
2457 BytecodeCounter::print();
2458 }
2459 #endif
2460 if (os::message_box(msg, "Execution stopped, print registers?")) {
2461 ttyLocker ttyl;
2462 tty->print_cr(" pc = 0x%016lx", pc);
2463 #ifndef PRODUCT
2464 tty->cr();
2465 findpc(pc);
2466 tty->cr();
2467 #endif
2468 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2469 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2470 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2471 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2472 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2473 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2474 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2475 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2476 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2477 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2478 tty->print_cr("r10 = 0x%016lx", regs[10]);
2479 tty->print_cr("r11 = 0x%016lx", regs[11]);
2480 tty->print_cr("r12 = 0x%016lx", regs[12]);
2481 tty->print_cr("r13 = 0x%016lx", regs[13]);
2482 tty->print_cr("r14 = 0x%016lx", regs[14]);
2483 tty->print_cr("r15 = 0x%016lx", regs[15]);
2484 tty->print_cr("r16 = 0x%016lx", regs[16]);
2485 tty->print_cr("r17 = 0x%016lx", regs[17]);
2486 tty->print_cr("r18 = 0x%016lx", regs[18]);
2487 tty->print_cr("r19 = 0x%016lx", regs[19]);
2488 tty->print_cr("r20 = 0x%016lx", regs[20]);
2489 tty->print_cr("r21 = 0x%016lx", regs[21]);
2490 tty->print_cr("r22 = 0x%016lx", regs[22]);
2491 tty->print_cr("r23 = 0x%016lx", regs[23]);
2492 tty->print_cr("r24 = 0x%016lx", regs[24]);
2493 tty->print_cr("r25 = 0x%016lx", regs[25]);
2494 tty->print_cr("r26 = 0x%016lx", regs[26]);
2495 tty->print_cr("r27 = 0x%016lx", regs[27]);
2496 tty->print_cr("r28 = 0x%016lx", regs[28]);
2497 tty->print_cr("r30 = 0x%016lx", regs[30]);
2498 tty->print_cr("r31 = 0x%016lx", regs[31]);
2499 BREAKPOINT;
2500 }
2501 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2502 } else {
2503 ttyLocker ttyl;
2504 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2505 msg);
2506 assert(false, "DEBUG MESSAGE: %s", msg);
2507 }
2508 }
2509
2510 #ifdef BUILTIN_SIM
2511 // routine to generate an x86 prolog for a stub function which
2512 // bootstraps into the generated ARM code which directly follows the
2513 // stub
2514 //
2515 // the argument encodes the number of general and fp registers
2516 // passed by the caller and the callng convention (currently just
2517 // the number of general registers and assumes C argument passing)
2518
2519 extern "C" {
2520 int aarch64_stub_prolog_size();
2521 void aarch64_stub_prolog();
2522 void aarch64_prolog();
2523 }
2524
2525 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2526 address *prolog_ptr)
2527 {
2528 int calltype = (((ret_type & 0x3) << 8) |
2529 ((fp_arg_count & 0xf) << 4) |
2530 (gp_arg_count & 0xf));
2531
2532 // the addresses for the x86 to ARM entry code we need to use
2533 address start = pc();
2534 // printf("start = %lx\n", start);
2535 int byteCount = aarch64_stub_prolog_size();
2536 // printf("byteCount = %x\n", byteCount);
2537 int instructionCount = (byteCount + 3)/ 4;
2538 // printf("instructionCount = %x\n", instructionCount);
2539 for (int i = 0; i < instructionCount; i++) {
2540 nop();
2541 }
2542
2543 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2544
2545 // write the address of the setup routine and the call format at the
2546 // end of into the copied code
2547 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2548 if (prolog_ptr)
2549 patch_end[-2] = (u_int64_t)prolog_ptr;
2550 patch_end[-1] = calltype;
2551 }
2552 #endif
2553
2554 void MacroAssembler::push_call_clobbered_registers() {
2555 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2556
2557 // Push v0-v7, v16-v31.
2558 for (int i = 30; i >= 0; i -= 2) {
2559 if (i <= v7->encoding() || i >= v16->encoding()) {
2560 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2561 Address(pre(sp, -2 * wordSize)));
2562 }
2563 }
2564 }
2565
2566 void MacroAssembler::pop_call_clobbered_registers() {
2567
2568 for (int i = 0; i < 32; i += 2) {
2569 if (i <= v7->encoding() || i >= v16->encoding()) {
2570 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2571 Address(post(sp, 2 * wordSize)));
2572 }
2573 }
2574
2575 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2576 }
2577
2578 void MacroAssembler::push_CPU_state(bool save_vectors) {
2579 push(0x3fffffff, sp); // integer registers except lr & sp
2580
2581 if (!save_vectors) {
2582 for (int i = 30; i >= 0; i -= 2)
2583 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2584 Address(pre(sp, -2 * wordSize)));
2585 } else {
2586 for (int i = 30; i >= 0; i -= 2)
2587 stpq(as_FloatRegister(i), as_FloatRegister(i+1),
2588 Address(pre(sp, -4 * wordSize)));
2589 }
2590 }
2591
2592 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2593 if (!restore_vectors) {
2594 for (int i = 0; i < 32; i += 2)
2595 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2596 Address(post(sp, 2 * wordSize)));
2597 } else {
2598 for (int i = 0; i < 32; i += 2)
2599 ldpq(as_FloatRegister(i), as_FloatRegister(i+1),
2600 Address(post(sp, 4 * wordSize)));
2601 }
2602
2603 pop(0x3fffffff, sp); // integer registers except lr & sp
2604 }
2605
2606 /**
2607 * Helpers for multiply_to_len().
2608 */
2609 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2610 Register src1, Register src2) {
2611 adds(dest_lo, dest_lo, src1);
2612 adc(dest_hi, dest_hi, zr);
2613 adds(dest_lo, dest_lo, src2);
2614 adc(final_dest_hi, dest_hi, zr);
2615 }
2616
2617 // Generate an address from (r + r1 extend offset). "size" is the
2618 // size of the operand. The result may be in rscratch2.
2619 Address MacroAssembler::offsetted_address(Register r, Register r1,
2620 Address::extend ext, int offset, int size) {
2621 if (offset || (ext.shift() % size != 0)) {
2622 lea(rscratch2, Address(r, r1, ext));
2623 return Address(rscratch2, offset);
2624 } else {
2625 return Address(r, r1, ext);
2626 }
2627 }
2628
2629 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2630 {
2631 assert(offset >= 0, "spill to negative address?");
2632 // Offset reachable ?
2633 // Not aligned - 9 bits signed offset
2634 // Aligned - 12 bits unsigned offset shifted
2635 Register base = sp;
2636 if ((offset & (size-1)) && offset >= (1<<8)) {
2637 add(tmp, base, offset & ((1<<12)-1));
2638 base = tmp;
2639 offset &= -1<<12;
2640 }
2641
2642 if (offset >= (1<<12) * size) {
2643 add(tmp, base, offset & (((1<<12)-1)<<12));
2644 base = tmp;
2645 offset &= ~(((1<<12)-1)<<12);
2646 }
2647
2648 return Address(base, offset);
2649 }
2650
2651 // Checks whether offset is aligned.
2652 // Returns true if it is, else false.
2653 bool MacroAssembler::merge_alignment_check(Register base,
2654 size_t size,
2655 long cur_offset,
2656 long prev_offset) const {
2657 if (AvoidUnalignedAccesses) {
2658 if (base == sp) {
2659 // Checks whether low offset if aligned to pair of registers.
2660 long pair_mask = size * 2 - 1;
2661 long offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2662 return (offset & pair_mask) == 0;
2663 } else { // If base is not sp, we can't guarantee the access is aligned.
2664 return false;
2665 }
2666 } else {
2667 long mask = size - 1;
2668 // Load/store pair instruction only supports element size aligned offset.
2669 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
2670 }
2671 }
2672
2673 // Checks whether current and previous loads/stores can be merged.
2674 // Returns true if it can be merged, else false.
2675 bool MacroAssembler::ldst_can_merge(Register rt,
2676 const Address &adr,
2677 size_t cur_size_in_bytes,
2678 bool is_store) const {
2679 address prev = pc() - NativeInstruction::instruction_size;
2680 address last = code()->last_insn();
2681
2682 if (last == NULL || !nativeInstruction_at(last)->is_Imm_LdSt()) {
2683 return false;
2684 }
2685
2686 if (adr.getMode() != Address::base_plus_offset || prev != last) {
2687 return false;
2688 }
2689
2690 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2691 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
2692
2693 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
2694 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
2695
2696 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
2697 return false;
2698 }
2699
2700 long max_offset = 63 * prev_size_in_bytes;
2701 long min_offset = -64 * prev_size_in_bytes;
2702
2703 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
2704
2705 // Only same base can be merged.
2706 if (adr.base() != prev_ldst->base()) {
2707 return false;
2708 }
2709
2710 long cur_offset = adr.offset();
2711 long prev_offset = prev_ldst->offset();
2712 size_t diff = abs(cur_offset - prev_offset);
2713 if (diff != prev_size_in_bytes) {
2714 return false;
2715 }
2716
2717 // Following cases can not be merged:
2718 // ldr x2, [x2, #8]
2719 // ldr x3, [x2, #16]
2720 // or:
2721 // ldr x2, [x3, #8]
2722 // ldr x2, [x3, #16]
2723 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
2724 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
2725 return false;
2726 }
2727
2728 long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2729 // Offset range must be in ldp/stp instruction's range.
2730 if (low_offset > max_offset || low_offset < min_offset) {
2731 return false;
2732 }
2733
2734 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
2735 return true;
2736 }
2737
2738 return false;
2739 }
2740
2741 // Merge current load/store with previous load/store into ldp/stp.
2742 void MacroAssembler::merge_ldst(Register rt,
2743 const Address &adr,
2744 size_t cur_size_in_bytes,
2745 bool is_store) {
2746
2747 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
2748
2749 Register rt_low, rt_high;
2750 address prev = pc() - NativeInstruction::instruction_size;
2751 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2752
2753 long offset;
2754
2755 if (adr.offset() < prev_ldst->offset()) {
2756 offset = adr.offset();
2757 rt_low = rt;
2758 rt_high = prev_ldst->target();
2759 } else {
2760 offset = prev_ldst->offset();
2761 rt_low = prev_ldst->target();
2762 rt_high = rt;
2763 }
2764
2765 Address adr_p = Address(prev_ldst->base(), offset);
2766 // Overwrite previous generated binary.
2767 code_section()->set_end(prev);
2768
2769 const int sz = prev_ldst->size_in_bytes();
2770 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
2771 if (!is_store) {
2772 BLOCK_COMMENT("merged ldr pair");
2773 if (sz == 8) {
2774 ldp(rt_low, rt_high, adr_p);
2775 } else {
2776 ldpw(rt_low, rt_high, adr_p);
2777 }
2778 } else {
2779 BLOCK_COMMENT("merged str pair");
2780 if (sz == 8) {
2781 stp(rt_low, rt_high, adr_p);
2782 } else {
2783 stpw(rt_low, rt_high, adr_p);
2784 }
2785 }
2786 }
2787
2788 /**
2789 * Multiply 64 bit by 64 bit first loop.
2790 */
2791 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2792 Register y, Register y_idx, Register z,
2793 Register carry, Register product,
2794 Register idx, Register kdx) {
2795 //
2796 // jlong carry, x[], y[], z[];
2797 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2798 // huge_128 product = y[idx] * x[xstart] + carry;
2799 // z[kdx] = (jlong)product;
2800 // carry = (jlong)(product >>> 64);
2801 // }
2802 // z[xstart] = carry;
2803 //
2804
2805 Label L_first_loop, L_first_loop_exit;
2806 Label L_one_x, L_one_y, L_multiply;
2807
2808 subsw(xstart, xstart, 1);
2809 br(Assembler::MI, L_one_x);
2810
2811 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2812 ldr(x_xstart, Address(rscratch1));
2813 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2814
2815 bind(L_first_loop);
2816 subsw(idx, idx, 1);
2817 br(Assembler::MI, L_first_loop_exit);
2818 subsw(idx, idx, 1);
2819 br(Assembler::MI, L_one_y);
2820 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2821 ldr(y_idx, Address(rscratch1));
2822 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2823 bind(L_multiply);
2824
2825 // AArch64 has a multiply-accumulate instruction that we can't use
2826 // here because it has no way to process carries, so we have to use
2827 // separate add and adc instructions. Bah.
2828 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2829 mul(product, x_xstart, y_idx);
2830 adds(product, product, carry);
2831 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2832
2833 subw(kdx, kdx, 2);
2834 ror(product, product, 32); // back to big-endian
2835 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2836
2837 b(L_first_loop);
2838
2839 bind(L_one_y);
2840 ldrw(y_idx, Address(y, 0));
2841 b(L_multiply);
2842
2843 bind(L_one_x);
2844 ldrw(x_xstart, Address(x, 0));
2845 b(L_first_loop);
2846
2847 bind(L_first_loop_exit);
2848 }
2849
2850 /**
2851 * Multiply 128 bit by 128. Unrolled inner loop.
2852 *
2853 */
2854 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2855 Register carry, Register carry2,
2856 Register idx, Register jdx,
2857 Register yz_idx1, Register yz_idx2,
2858 Register tmp, Register tmp3, Register tmp4,
2859 Register tmp6, Register product_hi) {
2860
2861 // jlong carry, x[], y[], z[];
2862 // int kdx = ystart+1;
2863 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2864 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2865 // jlong carry2 = (jlong)(tmp3 >>> 64);
2866 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2867 // carry = (jlong)(tmp4 >>> 64);
2868 // z[kdx+idx+1] = (jlong)tmp3;
2869 // z[kdx+idx] = (jlong)tmp4;
2870 // }
2871 // idx += 2;
2872 // if (idx > 0) {
2873 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2874 // z[kdx+idx] = (jlong)yz_idx1;
2875 // carry = (jlong)(yz_idx1 >>> 64);
2876 // }
2877 //
2878
2879 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2880
2881 lsrw(jdx, idx, 2);
2882
2883 bind(L_third_loop);
2884
2885 subsw(jdx, jdx, 1);
2886 br(Assembler::MI, L_third_loop_exit);
2887 subw(idx, idx, 4);
2888
2889 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2890
2891 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2892
2893 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2894
2895 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2896 ror(yz_idx2, yz_idx2, 32);
2897
2898 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2899
2900 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2901 umulh(tmp4, product_hi, yz_idx1);
2902
2903 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2904 ror(rscratch2, rscratch2, 32);
2905
2906 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2907 umulh(carry2, product_hi, yz_idx2);
2908
2909 // propagate sum of both multiplications into carry:tmp4:tmp3
2910 adds(tmp3, tmp3, carry);
2911 adc(tmp4, tmp4, zr);
2912 adds(tmp3, tmp3, rscratch1);
2913 adcs(tmp4, tmp4, tmp);
2914 adc(carry, carry2, zr);
2915 adds(tmp4, tmp4, rscratch2);
2916 adc(carry, carry, zr);
2917
2918 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2919 ror(tmp4, tmp4, 32);
2920 stp(tmp4, tmp3, Address(tmp6, 0));
2921
2922 b(L_third_loop);
2923 bind (L_third_loop_exit);
2924
2925 andw (idx, idx, 0x3);
2926 cbz(idx, L_post_third_loop_done);
2927
2928 Label L_check_1;
2929 subsw(idx, idx, 2);
2930 br(Assembler::MI, L_check_1);
2931
2932 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2933 ldr(yz_idx1, Address(rscratch1, 0));
2934 ror(yz_idx1, yz_idx1, 32);
2935 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2936 umulh(tmp4, product_hi, yz_idx1);
2937 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2938 ldr(yz_idx2, Address(rscratch1, 0));
2939 ror(yz_idx2, yz_idx2, 32);
2940
2941 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2942
2943 ror(tmp3, tmp3, 32);
2944 str(tmp3, Address(rscratch1, 0));
2945
2946 bind (L_check_1);
2947
2948 andw (idx, idx, 0x1);
2949 subsw(idx, idx, 1);
2950 br(Assembler::MI, L_post_third_loop_done);
2951 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2952 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2953 umulh(carry2, tmp4, product_hi);
2954 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2955
2956 add2_with_carry(carry2, tmp3, tmp4, carry);
2957
2958 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2959 extr(carry, carry2, tmp3, 32);
2960
2961 bind(L_post_third_loop_done);
2962 }
2963
2964 /**
2965 * Code for BigInteger::multiplyToLen() instrinsic.
2966 *
2967 * r0: x
2968 * r1: xlen
2969 * r2: y
2970 * r3: ylen
2971 * r4: z
2972 * r5: zlen
2973 * r10: tmp1
2974 * r11: tmp2
2975 * r12: tmp3
2976 * r13: tmp4
2977 * r14: tmp5
2978 * r15: tmp6
2979 * r16: tmp7
2980 *
2981 */
2982 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2983 Register z, Register zlen,
2984 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2985 Register tmp5, Register tmp6, Register product_hi) {
2986
2987 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2988
2989 const Register idx = tmp1;
2990 const Register kdx = tmp2;
2991 const Register xstart = tmp3;
2992
2993 const Register y_idx = tmp4;
2994 const Register carry = tmp5;
2995 const Register product = xlen;
2996 const Register x_xstart = zlen; // reuse register
2997
2998 // First Loop.
2999 //
3000 // final static long LONG_MASK = 0xffffffffL;
3001 // int xstart = xlen - 1;
3002 // int ystart = ylen - 1;
3003 // long carry = 0;
3004 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3005 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
3006 // z[kdx] = (int)product;
3007 // carry = product >>> 32;
3008 // }
3009 // z[xstart] = (int)carry;
3010 //
3011
3012 movw(idx, ylen); // idx = ylen;
3013 movw(kdx, zlen); // kdx = xlen+ylen;
3014 mov(carry, zr); // carry = 0;
3015
3016 Label L_done;
3017
3018 movw(xstart, xlen);
3019 subsw(xstart, xstart, 1);
3020 br(Assembler::MI, L_done);
3021
3022 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
3023
3024 Label L_second_loop;
3025 cbzw(kdx, L_second_loop);
3026
3027 Label L_carry;
3028 subw(kdx, kdx, 1);
3029 cbzw(kdx, L_carry);
3030
3031 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3032 lsr(carry, carry, 32);
3033 subw(kdx, kdx, 1);
3034
3035 bind(L_carry);
3036 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3037
3038 // Second and third (nested) loops.
3039 //
3040 // for (int i = xstart-1; i >= 0; i--) { // Second loop
3041 // carry = 0;
3042 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
3043 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
3044 // (z[k] & LONG_MASK) + carry;
3045 // z[k] = (int)product;
3046 // carry = product >>> 32;
3047 // }
3048 // z[i] = (int)carry;
3049 // }
3050 //
3051 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
3052
3053 const Register jdx = tmp1;
3054
3055 bind(L_second_loop);
3056 mov(carry, zr); // carry = 0;
3057 movw(jdx, ylen); // j = ystart+1
3058
3059 subsw(xstart, xstart, 1); // i = xstart-1;
3060 br(Assembler::MI, L_done);
3061
3062 str(z, Address(pre(sp, -4 * wordSize)));
3063
3064 Label L_last_x;
3065 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
3066 subsw(xstart, xstart, 1); // i = xstart-1;
3067 br(Assembler::MI, L_last_x);
3068
3069 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
3070 ldr(product_hi, Address(rscratch1));
3071 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3072
3073 Label L_third_loop_prologue;
3074 bind(L_third_loop_prologue);
3075
3076 str(ylen, Address(sp, wordSize));
3077 stp(x, xstart, Address(sp, 2 * wordSize));
3078 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
3079 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
3080 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
3081 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
3082
3083 addw(tmp3, xlen, 1);
3084 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3085 subsw(tmp3, tmp3, 1);
3086 br(Assembler::MI, L_done);
3087
3088 lsr(carry, carry, 32);
3089 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3090 b(L_second_loop);
3091
3092 // Next infrequent code is moved outside loops.
3093 bind(L_last_x);
3094 ldrw(product_hi, Address(x, 0));
3095 b(L_third_loop_prologue);
3096
3097 bind(L_done);
3098 }
3099
3100 // Code for BigInteger::mulAdd instrinsic
3101 // out = r0
3102 // in = r1
3103 // offset = r2 (already out.length-offset)
3104 // len = r3
3105 // k = r4
3106 //
3107 // pseudo code from java implementation:
3108 // carry = 0;
3109 // offset = out.length-offset - 1;
3110 // for (int j=len-1; j >= 0; j--) {
3111 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
3112 // out[offset--] = (int)product;
3113 // carry = product >>> 32;
3114 // }
3115 // return (int)carry;
3116 void MacroAssembler::mul_add(Register out, Register in, Register offset,
3117 Register len, Register k) {
3118 Label LOOP, END;
3119 // pre-loop
3120 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
3121 csel(out, zr, out, Assembler::EQ);
3122 br(Assembler::EQ, END);
3123 add(in, in, len, LSL, 2); // in[j+1] address
3124 add(offset, out, offset, LSL, 2); // out[offset + 1] address
3125 mov(out, zr); // used to keep carry now
3126 BIND(LOOP);
3127 ldrw(rscratch1, Address(pre(in, -4)));
3128 madd(rscratch1, rscratch1, k, out);
3129 ldrw(rscratch2, Address(pre(offset, -4)));
3130 add(rscratch1, rscratch1, rscratch2);
3131 strw(rscratch1, Address(offset));
3132 lsr(out, rscratch1, 32);
3133 subs(len, len, 1);
3134 br(Assembler::NE, LOOP);
3135 BIND(END);
3136 }
3137
3138 /**
3139 * Emits code to update CRC-32 with a byte value according to constants in table
3140 *
3141 * @param [in,out]crc Register containing the crc.
3142 * @param [in]val Register containing the byte to fold into the CRC.
3143 * @param [in]table Register containing the table of crc constants.
3144 *
3145 * uint32_t crc;
3146 * val = crc_table[(val ^ crc) & 0xFF];
3147 * crc = val ^ (crc >> 8);
3148 *
3149 */
3150 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3151 eor(val, val, crc);
3152 andr(val, val, 0xff);
3153 ldrw(val, Address(table, val, Address::lsl(2)));
3154 eor(crc, val, crc, Assembler::LSR, 8);
3155 }
3156
3157 /**
3158 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
3159 *
3160 * @param [in,out]crc Register containing the crc.
3161 * @param [in]v Register containing the 32-bit to fold into the CRC.
3162 * @param [in]table0 Register containing table 0 of crc constants.
3163 * @param [in]table1 Register containing table 1 of crc constants.
3164 * @param [in]table2 Register containing table 2 of crc constants.
3165 * @param [in]table3 Register containing table 3 of crc constants.
3166 *
3167 * uint32_t crc;
3168 * v = crc ^ v
3169 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
3170 *
3171 */
3172 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
3173 Register table0, Register table1, Register table2, Register table3,
3174 bool upper) {
3175 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
3176 uxtb(tmp, v);
3177 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
3178 ubfx(tmp, v, 8, 8);
3179 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
3180 eor(crc, crc, tmp);
3181 ubfx(tmp, v, 16, 8);
3182 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
3183 eor(crc, crc, tmp);
3184 ubfx(tmp, v, 24, 8);
3185 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
3186 eor(crc, crc, tmp);
3187 }
3188
3189 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
3190 Register len, Register tmp0, Register tmp1, Register tmp2,
3191 Register tmp3) {
3192 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3193 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3194
3195 mvnw(crc, crc);
3196
3197 subs(len, len, 128);
3198 br(Assembler::GE, CRC_by64_pre);
3199 BIND(CRC_less64);
3200 adds(len, len, 128-32);
3201 br(Assembler::GE, CRC_by32_loop);
3202 BIND(CRC_less32);
3203 adds(len, len, 32-4);
3204 br(Assembler::GE, CRC_by4_loop);
3205 adds(len, len, 4);
3206 br(Assembler::GT, CRC_by1_loop);
3207 b(L_exit);
3208
3209 BIND(CRC_by32_loop);
3210 ldp(tmp0, tmp1, Address(post(buf, 16)));
3211 subs(len, len, 32);
3212 crc32x(crc, crc, tmp0);
3213 ldr(tmp2, Address(post(buf, 8)));
3214 crc32x(crc, crc, tmp1);
3215 ldr(tmp3, Address(post(buf, 8)));
3216 crc32x(crc, crc, tmp2);
3217 crc32x(crc, crc, tmp3);
3218 br(Assembler::GE, CRC_by32_loop);
3219 cmn(len, 32);
3220 br(Assembler::NE, CRC_less32);
3221 b(L_exit);
3222
3223 BIND(CRC_by4_loop);
3224 ldrw(tmp0, Address(post(buf, 4)));
3225 subs(len, len, 4);
3226 crc32w(crc, crc, tmp0);
3227 br(Assembler::GE, CRC_by4_loop);
3228 adds(len, len, 4);
3229 br(Assembler::LE, L_exit);
3230 BIND(CRC_by1_loop);
3231 ldrb(tmp0, Address(post(buf, 1)));
3232 subs(len, len, 1);
3233 crc32b(crc, crc, tmp0);
3234 br(Assembler::GT, CRC_by1_loop);
3235 b(L_exit);
3236
3237 BIND(CRC_by64_pre);
3238 sub(buf, buf, 8);
3239 ldp(tmp0, tmp1, Address(buf, 8));
3240 crc32x(crc, crc, tmp0);
3241 ldr(tmp2, Address(buf, 24));
3242 crc32x(crc, crc, tmp1);
3243 ldr(tmp3, Address(buf, 32));
3244 crc32x(crc, crc, tmp2);
3245 ldr(tmp0, Address(buf, 40));
3246 crc32x(crc, crc, tmp3);
3247 ldr(tmp1, Address(buf, 48));
3248 crc32x(crc, crc, tmp0);
3249 ldr(tmp2, Address(buf, 56));
3250 crc32x(crc, crc, tmp1);
3251 ldr(tmp3, Address(pre(buf, 64)));
3252
3253 b(CRC_by64_loop);
3254
3255 align(CodeEntryAlignment);
3256 BIND(CRC_by64_loop);
3257 subs(len, len, 64);
3258 crc32x(crc, crc, tmp2);
3259 ldr(tmp0, Address(buf, 8));
3260 crc32x(crc, crc, tmp3);
3261 ldr(tmp1, Address(buf, 16));
3262 crc32x(crc, crc, tmp0);
3263 ldr(tmp2, Address(buf, 24));
3264 crc32x(crc, crc, tmp1);
3265 ldr(tmp3, Address(buf, 32));
3266 crc32x(crc, crc, tmp2);
3267 ldr(tmp0, Address(buf, 40));
3268 crc32x(crc, crc, tmp3);
3269 ldr(tmp1, Address(buf, 48));
3270 crc32x(crc, crc, tmp0);
3271 ldr(tmp2, Address(buf, 56));
3272 crc32x(crc, crc, tmp1);
3273 ldr(tmp3, Address(pre(buf, 64)));
3274 br(Assembler::GE, CRC_by64_loop);
3275
3276 // post-loop
3277 crc32x(crc, crc, tmp2);
3278 crc32x(crc, crc, tmp3);
3279
3280 sub(len, len, 64);
3281 add(buf, buf, 8);
3282 cmn(len, 128);
3283 br(Assembler::NE, CRC_less64);
3284 BIND(L_exit);
3285 mvnw(crc, crc);
3286 }
3287
3288 /**
3289 * @param crc register containing existing CRC (32-bit)
3290 * @param buf register pointing to input byte buffer (byte*)
3291 * @param len register containing number of bytes
3292 * @param table register that will contain address of CRC table
3293 * @param tmp scratch register
3294 */
3295 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
3296 Register table0, Register table1, Register table2, Register table3,
3297 Register tmp, Register tmp2, Register tmp3) {
3298 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
3299 unsigned long offset;
3300
3301 if (UseCRC32) {
3302 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
3303 return;
3304 }
3305
3306 mvnw(crc, crc);
3307
3308 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
3309 if (offset) add(table0, table0, offset);
3310 add(table1, table0, 1*256*sizeof(juint));
3311 add(table2, table0, 2*256*sizeof(juint));
3312 add(table3, table0, 3*256*sizeof(juint));
3313
3314 if (UseNeon) {
3315 cmp(len, 64);
3316 br(Assembler::LT, L_by16);
3317 eor(v16, T16B, v16, v16);
3318
3319 Label L_fold;
3320
3321 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
3322
3323 ld1(v0, v1, T2D, post(buf, 32));
3324 ld1r(v4, T2D, post(tmp, 8));
3325 ld1r(v5, T2D, post(tmp, 8));
3326 ld1r(v6, T2D, post(tmp, 8));
3327 ld1r(v7, T2D, post(tmp, 8));
3328 mov(v16, T4S, 0, crc);
3329
3330 eor(v0, T16B, v0, v16);
3331 sub(len, len, 64);
3332
3333 BIND(L_fold);
3334 pmull(v22, T8H, v0, v5, T8B);
3335 pmull(v20, T8H, v0, v7, T8B);
3336 pmull(v23, T8H, v0, v4, T8B);
3337 pmull(v21, T8H, v0, v6, T8B);
3338
3339 pmull2(v18, T8H, v0, v5, T16B);
3340 pmull2(v16, T8H, v0, v7, T16B);
3341 pmull2(v19, T8H, v0, v4, T16B);
3342 pmull2(v17, T8H, v0, v6, T16B);
3343
3344 uzp1(v24, v20, v22, T8H);
3345 uzp2(v25, v20, v22, T8H);
3346 eor(v20, T16B, v24, v25);
3347
3348 uzp1(v26, v16, v18, T8H);
3349 uzp2(v27, v16, v18, T8H);
3350 eor(v16, T16B, v26, v27);
3351
3352 ushll2(v22, T4S, v20, T8H, 8);
3353 ushll(v20, T4S, v20, T4H, 8);
3354
3355 ushll2(v18, T4S, v16, T8H, 8);
3356 ushll(v16, T4S, v16, T4H, 8);
3357
3358 eor(v22, T16B, v23, v22);
3359 eor(v18, T16B, v19, v18);
3360 eor(v20, T16B, v21, v20);
3361 eor(v16, T16B, v17, v16);
3362
3363 uzp1(v17, v16, v20, T2D);
3364 uzp2(v21, v16, v20, T2D);
3365 eor(v17, T16B, v17, v21);
3366
3367 ushll2(v20, T2D, v17, T4S, 16);
3368 ushll(v16, T2D, v17, T2S, 16);
3369
3370 eor(v20, T16B, v20, v22);
3371 eor(v16, T16B, v16, v18);
3372
3373 uzp1(v17, v20, v16, T2D);
3374 uzp2(v21, v20, v16, T2D);
3375 eor(v28, T16B, v17, v21);
3376
3377 pmull(v22, T8H, v1, v5, T8B);
3378 pmull(v20, T8H, v1, v7, T8B);
3379 pmull(v23, T8H, v1, v4, T8B);
3380 pmull(v21, T8H, v1, v6, T8B);
3381
3382 pmull2(v18, T8H, v1, v5, T16B);
3383 pmull2(v16, T8H, v1, v7, T16B);
3384 pmull2(v19, T8H, v1, v4, T16B);
3385 pmull2(v17, T8H, v1, v6, T16B);
3386
3387 ld1(v0, v1, T2D, post(buf, 32));
3388
3389 uzp1(v24, v20, v22, T8H);
3390 uzp2(v25, v20, v22, T8H);
3391 eor(v20, T16B, v24, v25);
3392
3393 uzp1(v26, v16, v18, T8H);
3394 uzp2(v27, v16, v18, T8H);
3395 eor(v16, T16B, v26, v27);
3396
3397 ushll2(v22, T4S, v20, T8H, 8);
3398 ushll(v20, T4S, v20, T4H, 8);
3399
3400 ushll2(v18, T4S, v16, T8H, 8);
3401 ushll(v16, T4S, v16, T4H, 8);
3402
3403 eor(v22, T16B, v23, v22);
3404 eor(v18, T16B, v19, v18);
3405 eor(v20, T16B, v21, v20);
3406 eor(v16, T16B, v17, v16);
3407
3408 uzp1(v17, v16, v20, T2D);
3409 uzp2(v21, v16, v20, T2D);
3410 eor(v16, T16B, v17, v21);
3411
3412 ushll2(v20, T2D, v16, T4S, 16);
3413 ushll(v16, T2D, v16, T2S, 16);
3414
3415 eor(v20, T16B, v22, v20);
3416 eor(v16, T16B, v16, v18);
3417
3418 uzp1(v17, v20, v16, T2D);
3419 uzp2(v21, v20, v16, T2D);
3420 eor(v20, T16B, v17, v21);
3421
3422 shl(v16, T2D, v28, 1);
3423 shl(v17, T2D, v20, 1);
3424
3425 eor(v0, T16B, v0, v16);
3426 eor(v1, T16B, v1, v17);
3427
3428 subs(len, len, 32);
3429 br(Assembler::GE, L_fold);
3430
3431 mov(crc, 0);
3432 mov(tmp, v0, T1D, 0);
3433 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3434 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3435 mov(tmp, v0, T1D, 1);
3436 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3437 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3438 mov(tmp, v1, T1D, 0);
3439 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3440 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3441 mov(tmp, v1, T1D, 1);
3442 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3443 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3444
3445 add(len, len, 32);
3446 }
3447
3448 BIND(L_by16);
3449 subs(len, len, 16);
3450 br(Assembler::GE, L_by16_loop);
3451 adds(len, len, 16-4);
3452 br(Assembler::GE, L_by4_loop);
3453 adds(len, len, 4);
3454 br(Assembler::GT, L_by1_loop);
3455 b(L_exit);
3456
3457 BIND(L_by4_loop);
3458 ldrw(tmp, Address(post(buf, 4)));
3459 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
3460 subs(len, len, 4);
3461 br(Assembler::GE, L_by4_loop);
3462 adds(len, len, 4);
3463 br(Assembler::LE, L_exit);
3464 BIND(L_by1_loop);
3465 subs(len, len, 1);
3466 ldrb(tmp, Address(post(buf, 1)));
3467 update_byte_crc32(crc, tmp, table0);
3468 br(Assembler::GT, L_by1_loop);
3469 b(L_exit);
3470
3471 align(CodeEntryAlignment);
3472 BIND(L_by16_loop);
3473 subs(len, len, 16);
3474 ldp(tmp, tmp3, Address(post(buf, 16)));
3475 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3476 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3477 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
3478 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
3479 br(Assembler::GE, L_by16_loop);
3480 adds(len, len, 16-4);
3481 br(Assembler::GE, L_by4_loop);
3482 adds(len, len, 4);
3483 br(Assembler::GT, L_by1_loop);
3484 BIND(L_exit);
3485 mvnw(crc, crc);
3486 }
3487
3488 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
3489 Register len, Register tmp0, Register tmp1, Register tmp2,
3490 Register tmp3) {
3491 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3492 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3493
3494 subs(len, len, 128);
3495 br(Assembler::GE, CRC_by64_pre);
3496 BIND(CRC_less64);
3497 adds(len, len, 128-32);
3498 br(Assembler::GE, CRC_by32_loop);
3499 BIND(CRC_less32);
3500 adds(len, len, 32-4);
3501 br(Assembler::GE, CRC_by4_loop);
3502 adds(len, len, 4);
3503 br(Assembler::GT, CRC_by1_loop);
3504 b(L_exit);
3505
3506 BIND(CRC_by32_loop);
3507 ldp(tmp0, tmp1, Address(post(buf, 16)));
3508 subs(len, len, 32);
3509 crc32cx(crc, crc, tmp0);
3510 ldr(tmp2, Address(post(buf, 8)));
3511 crc32cx(crc, crc, tmp1);
3512 ldr(tmp3, Address(post(buf, 8)));
3513 crc32cx(crc, crc, tmp2);
3514 crc32cx(crc, crc, tmp3);
3515 br(Assembler::GE, CRC_by32_loop);
3516 cmn(len, 32);
3517 br(Assembler::NE, CRC_less32);
3518 b(L_exit);
3519
3520 BIND(CRC_by4_loop);
3521 ldrw(tmp0, Address(post(buf, 4)));
3522 subs(len, len, 4);
3523 crc32cw(crc, crc, tmp0);
3524 br(Assembler::GE, CRC_by4_loop);
3525 adds(len, len, 4);
3526 br(Assembler::LE, L_exit);
3527 BIND(CRC_by1_loop);
3528 ldrb(tmp0, Address(post(buf, 1)));
3529 subs(len, len, 1);
3530 crc32cb(crc, crc, tmp0);
3531 br(Assembler::GT, CRC_by1_loop);
3532 b(L_exit);
3533
3534 BIND(CRC_by64_pre);
3535 sub(buf, buf, 8);
3536 ldp(tmp0, tmp1, Address(buf, 8));
3537 crc32cx(crc, crc, tmp0);
3538 ldr(tmp2, Address(buf, 24));
3539 crc32cx(crc, crc, tmp1);
3540 ldr(tmp3, Address(buf, 32));
3541 crc32cx(crc, crc, tmp2);
3542 ldr(tmp0, Address(buf, 40));
3543 crc32cx(crc, crc, tmp3);
3544 ldr(tmp1, Address(buf, 48));
3545 crc32cx(crc, crc, tmp0);
3546 ldr(tmp2, Address(buf, 56));
3547 crc32cx(crc, crc, tmp1);
3548 ldr(tmp3, Address(pre(buf, 64)));
3549
3550 b(CRC_by64_loop);
3551
3552 align(CodeEntryAlignment);
3553 BIND(CRC_by64_loop);
3554 subs(len, len, 64);
3555 crc32cx(crc, crc, tmp2);
3556 ldr(tmp0, Address(buf, 8));
3557 crc32cx(crc, crc, tmp3);
3558 ldr(tmp1, Address(buf, 16));
3559 crc32cx(crc, crc, tmp0);
3560 ldr(tmp2, Address(buf, 24));
3561 crc32cx(crc, crc, tmp1);
3562 ldr(tmp3, Address(buf, 32));
3563 crc32cx(crc, crc, tmp2);
3564 ldr(tmp0, Address(buf, 40));
3565 crc32cx(crc, crc, tmp3);
3566 ldr(tmp1, Address(buf, 48));
3567 crc32cx(crc, crc, tmp0);
3568 ldr(tmp2, Address(buf, 56));
3569 crc32cx(crc, crc, tmp1);
3570 ldr(tmp3, Address(pre(buf, 64)));
3571 br(Assembler::GE, CRC_by64_loop);
3572
3573 // post-loop
3574 crc32cx(crc, crc, tmp2);
3575 crc32cx(crc, crc, tmp3);
3576
3577 sub(len, len, 64);
3578 add(buf, buf, 8);
3579 cmn(len, 128);
3580 br(Assembler::NE, CRC_less64);
3581 BIND(L_exit);
3582 }
3583
3584 /**
3585 * @param crc register containing existing CRC (32-bit)
3586 * @param buf register pointing to input byte buffer (byte*)
3587 * @param len register containing number of bytes
3588 * @param table register that will contain address of CRC table
3589 * @param tmp scratch register
3590 */
3591 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
3592 Register table0, Register table1, Register table2, Register table3,
3593 Register tmp, Register tmp2, Register tmp3) {
3594 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
3595 }
3596
3597
3598 SkipIfEqual::SkipIfEqual(
3599 MacroAssembler* masm, const bool* flag_addr, bool value) {
3600 _masm = masm;
3601 unsigned long offset;
3602 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3603 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3604 _masm->cbzw(rscratch1, _label);
3605 }
3606
3607 SkipIfEqual::~SkipIfEqual() {
3608 _masm->bind(_label);
3609 }
3610
3611 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3612 Address adr;
3613 switch(dst.getMode()) {
3614 case Address::base_plus_offset:
3615 // This is the expected mode, although we allow all the other
3616 // forms below.
3617 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3618 break;
3619 default:
3620 lea(rscratch2, dst);
3621 adr = Address(rscratch2);
3622 break;
3623 }
3624 ldr(rscratch1, adr);
3625 add(rscratch1, rscratch1, src);
3626 str(rscratch1, adr);
3627 }
3628
3629 void MacroAssembler::cmpptr(Register src1, Address src2) {
3630 unsigned long offset;
3631 adrp(rscratch1, src2, offset);
3632 ldr(rscratch1, Address(rscratch1, offset));
3633 cmp(src1, rscratch1);
3634 }
3635
3636 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
3637 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3638 bs->obj_equals(this, obj1, obj2);
3639 }
3640
3641 void MacroAssembler::load_klass(Register dst, Register src) {
3642 if (UseCompressedClassPointers) {
3643 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3644 decode_klass_not_null(dst);
3645 } else {
3646 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3647 }
3648 }
3649
3650 // ((OopHandle)result).resolve();
3651 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
3652 // OopHandle::resolve is an indirection.
3653 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT,
3654 result, Address(result, 0), tmp, noreg);
3655 }
3656
3657 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp) {
3658 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
3659 ldr(dst, Address(rmethod, Method::const_offset()));
3660 ldr(dst, Address(dst, ConstMethod::constants_offset()));
3661 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes()));
3662 ldr(dst, Address(dst, mirror_offset));
3663 resolve_oop_handle(dst, tmp);
3664 }
3665
3666 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3667 if (UseCompressedClassPointers) {
3668 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3669 if (Universe::narrow_klass_base() == NULL) {
3670 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3671 return;
3672 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3673 && Universe::narrow_klass_shift() == 0) {
3674 // Only the bottom 32 bits matter
3675 cmpw(trial_klass, tmp);
3676 return;
3677 }
3678 decode_klass_not_null(tmp);
3679 } else {
3680 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3681 }
3682 cmp(trial_klass, tmp);
3683 }
3684
3685 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3686 load_klass(dst, src);
3687 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3688 }
3689
3690 void MacroAssembler::store_klass(Register dst, Register src) {
3691 // FIXME: Should this be a store release? concurrent gcs assumes
3692 // klass length is valid if klass field is not null.
3693 if (UseCompressedClassPointers) {
3694 encode_klass_not_null(src);
3695 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3696 } else {
3697 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3698 }
3699 }
3700
3701 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3702 if (UseCompressedClassPointers) {
3703 // Store to klass gap in destination
3704 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3705 }
3706 }
3707
3708 // Algorithm must match CompressedOops::encode.
3709 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3710 #ifdef ASSERT
3711 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3712 #endif
3713 verify_oop(s, "broken oop in encode_heap_oop");
3714 if (Universe::narrow_oop_base() == NULL) {
3715 if (Universe::narrow_oop_shift() != 0) {
3716 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3717 lsr(d, s, LogMinObjAlignmentInBytes);
3718 } else {
3719 mov(d, s);
3720 }
3721 } else {
3722 subs(d, s, rheapbase);
3723 csel(d, d, zr, Assembler::HS);
3724 lsr(d, d, LogMinObjAlignmentInBytes);
3725
3726 /* Old algorithm: is this any worse?
3727 Label nonnull;
3728 cbnz(r, nonnull);
3729 sub(r, r, rheapbase);
3730 bind(nonnull);
3731 lsr(r, r, LogMinObjAlignmentInBytes);
3732 */
3733 }
3734 }
3735
3736 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3737 #ifdef ASSERT
3738 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3739 if (CheckCompressedOops) {
3740 Label ok;
3741 cbnz(r, ok);
3742 stop("null oop passed to encode_heap_oop_not_null");
3743 bind(ok);
3744 }
3745 #endif
3746 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3747 if (Universe::narrow_oop_base() != NULL) {
3748 sub(r, r, rheapbase);
3749 }
3750 if (Universe::narrow_oop_shift() != 0) {
3751 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3752 lsr(r, r, LogMinObjAlignmentInBytes);
3753 }
3754 }
3755
3756 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3757 #ifdef ASSERT
3758 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3759 if (CheckCompressedOops) {
3760 Label ok;
3761 cbnz(src, ok);
3762 stop("null oop passed to encode_heap_oop_not_null2");
3763 bind(ok);
3764 }
3765 #endif
3766 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3767
3768 Register data = src;
3769 if (Universe::narrow_oop_base() != NULL) {
3770 sub(dst, src, rheapbase);
3771 data = dst;
3772 }
3773 if (Universe::narrow_oop_shift() != 0) {
3774 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3775 lsr(dst, data, LogMinObjAlignmentInBytes);
3776 data = dst;
3777 }
3778 if (data == src)
3779 mov(dst, src);
3780 }
3781
3782 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3783 #ifdef ASSERT
3784 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3785 #endif
3786 if (Universe::narrow_oop_base() == NULL) {
3787 if (Universe::narrow_oop_shift() != 0 || d != s) {
3788 lsl(d, s, Universe::narrow_oop_shift());
3789 }
3790 } else {
3791 Label done;
3792 if (d != s)
3793 mov(d, s);
3794 cbz(s, done);
3795 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3796 bind(done);
3797 }
3798 verify_oop(d, "broken oop in decode_heap_oop");
3799 }
3800
3801 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3802 assert (UseCompressedOops, "should only be used for compressed headers");
3803 assert (Universe::heap() != NULL, "java heap should be initialized");
3804 // Cannot assert, unverified entry point counts instructions (see .ad file)
3805 // vtableStubs also counts instructions in pd_code_size_limit.
3806 // Also do not verify_oop as this is called by verify_oop.
3807 if (Universe::narrow_oop_shift() != 0) {
3808 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3809 if (Universe::narrow_oop_base() != NULL) {
3810 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3811 } else {
3812 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3813 }
3814 } else {
3815 assert (Universe::narrow_oop_base() == NULL, "sanity");
3816 }
3817 }
3818
3819 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3820 assert (UseCompressedOops, "should only be used for compressed headers");
3821 assert (Universe::heap() != NULL, "java heap should be initialized");
3822 // Cannot assert, unverified entry point counts instructions (see .ad file)
3823 // vtableStubs also counts instructions in pd_code_size_limit.
3824 // Also do not verify_oop as this is called by verify_oop.
3825 if (Universe::narrow_oop_shift() != 0) {
3826 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3827 if (Universe::narrow_oop_base() != NULL) {
3828 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3829 } else {
3830 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3831 }
3832 } else {
3833 assert (Universe::narrow_oop_base() == NULL, "sanity");
3834 if (dst != src) {
3835 mov(dst, src);
3836 }
3837 }
3838 }
3839
3840 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3841 if (Universe::narrow_klass_base() == NULL) {
3842 if (Universe::narrow_klass_shift() != 0) {
3843 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3844 lsr(dst, src, LogKlassAlignmentInBytes);
3845 } else {
3846 if (dst != src) mov(dst, src);
3847 }
3848 return;
3849 }
3850
3851 if (use_XOR_for_compressed_class_base) {
3852 if (Universe::narrow_klass_shift() != 0) {
3853 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3854 lsr(dst, dst, LogKlassAlignmentInBytes);
3855 } else {
3856 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3857 }
3858 return;
3859 }
3860
3861 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3862 && Universe::narrow_klass_shift() == 0) {
3863 movw(dst, src);
3864 return;
3865 }
3866
3867 #ifdef ASSERT
3868 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3869 #endif
3870
3871 Register rbase = dst;
3872 if (dst == src) rbase = rheapbase;
3873 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3874 sub(dst, src, rbase);
3875 if (Universe::narrow_klass_shift() != 0) {
3876 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3877 lsr(dst, dst, LogKlassAlignmentInBytes);
3878 }
3879 if (dst == src) reinit_heapbase();
3880 }
3881
3882 void MacroAssembler::encode_klass_not_null(Register r) {
3883 encode_klass_not_null(r, r);
3884 }
3885
3886 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3887 Register rbase = dst;
3888 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3889
3890 if (Universe::narrow_klass_base() == NULL) {
3891 if (Universe::narrow_klass_shift() != 0) {
3892 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3893 lsl(dst, src, LogKlassAlignmentInBytes);
3894 } else {
3895 if (dst != src) mov(dst, src);
3896 }
3897 return;
3898 }
3899
3900 if (use_XOR_for_compressed_class_base) {
3901 if (Universe::narrow_klass_shift() != 0) {
3902 lsl(dst, src, LogKlassAlignmentInBytes);
3903 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3904 } else {
3905 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3906 }
3907 return;
3908 }
3909
3910 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3911 && Universe::narrow_klass_shift() == 0) {
3912 if (dst != src)
3913 movw(dst, src);
3914 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3915 return;
3916 }
3917
3918 // Cannot assert, unverified entry point counts instructions (see .ad file)
3919 // vtableStubs also counts instructions in pd_code_size_limit.
3920 // Also do not verify_oop as this is called by verify_oop.
3921 if (dst == src) rbase = rheapbase;
3922 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3923 if (Universe::narrow_klass_shift() != 0) {
3924 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3925 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3926 } else {
3927 add(dst, rbase, src);
3928 }
3929 if (dst == src) reinit_heapbase();
3930 }
3931
3932 void MacroAssembler::decode_klass_not_null(Register r) {
3933 decode_klass_not_null(r, r);
3934 }
3935
3936 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3937 #ifdef ASSERT
3938 {
3939 ThreadInVMfromUnknown tiv;
3940 assert (UseCompressedOops, "should only be used for compressed oops");
3941 assert (Universe::heap() != NULL, "java heap should be initialized");
3942 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3943 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3944 }
3945 #endif
3946 int oop_index = oop_recorder()->find_index(obj);
3947 InstructionMark im(this);
3948 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3949 code_section()->relocate(inst_mark(), rspec);
3950 movz(dst, 0xDEAD, 16);
3951 movk(dst, 0xBEEF);
3952 }
3953
3954 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3955 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3956 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3957 int index = oop_recorder()->find_index(k);
3958 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3959
3960 InstructionMark im(this);
3961 RelocationHolder rspec = metadata_Relocation::spec(index);
3962 code_section()->relocate(inst_mark(), rspec);
3963 narrowKlass nk = Klass::encode_klass(k);
3964 movz(dst, (nk >> 16), 16);
3965 movk(dst, nk & 0xffff);
3966 }
3967
3968 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
3969 Register dst, Address src,
3970 Register tmp1, Register thread_tmp) {
3971 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
3972 decorators = AccessInternal::decorator_fixup(decorators);
3973 bool as_raw = (decorators & AS_RAW) != 0;
3974 if (as_raw) {
3975 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3976 } else {
3977 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3978 }
3979 }
3980
3981 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
3982 Address dst, Register src,
3983 Register tmp1, Register thread_tmp) {
3984 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
3985 decorators = AccessInternal::decorator_fixup(decorators);
3986 bool as_raw = (decorators & AS_RAW) != 0;
3987 if (as_raw) {
3988 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3989 } else {
3990 bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3991 }
3992 }
3993
3994 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
3995 Register thread_tmp, DecoratorSet decorators) {
3996 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
3997 }
3998
3999 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4000 Register thread_tmp, DecoratorSet decorators) {
4001 access_load_at(T_OBJECT, IN_HEAP | OOP_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4002 }
4003
4004 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4005 Register thread_tmp, DecoratorSet decorators) {
4006 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4007 }
4008
4009 // Used for storing NULLs.
4010 void MacroAssembler::store_heap_oop_null(Address dst) {
4011 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4012 }
4013
4014 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
4015 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
4016 int index = oop_recorder()->allocate_metadata_index(obj);
4017 RelocationHolder rspec = metadata_Relocation::spec(index);
4018 return Address((address)obj, rspec);
4019 }
4020
4021 // Move an oop into a register. immediate is true if we want
4022 // immediate instrcutions, i.e. we are not going to patch this
4023 // instruction while the code is being executed by another thread. In
4024 // that case we can use move immediates rather than the constant pool.
4025 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
4026 int oop_index;
4027 if (obj == NULL) {
4028 oop_index = oop_recorder()->allocate_oop_index(obj);
4029 } else {
4030 #ifdef ASSERT
4031 {
4032 ThreadInVMfromUnknown tiv;
4033 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
4034 }
4035 #endif
4036 oop_index = oop_recorder()->find_index(obj);
4037 }
4038 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4039 if (! immediate) {
4040 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
4041 ldr_constant(dst, Address(dummy, rspec));
4042 } else
4043 mov(dst, Address((address)obj, rspec));
4044 }
4045
4046 // Move a metadata address into a register.
4047 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
4048 int oop_index;
4049 if (obj == NULL) {
4050 oop_index = oop_recorder()->allocate_metadata_index(obj);
4051 } else {
4052 oop_index = oop_recorder()->find_index(obj);
4053 }
4054 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4055 mov(dst, Address((address)obj, rspec));
4056 }
4057
4058 Address MacroAssembler::constant_oop_address(jobject obj) {
4059 #ifdef ASSERT
4060 {
4061 ThreadInVMfromUnknown tiv;
4062 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4063 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
4064 }
4065 #endif
4066 int oop_index = oop_recorder()->find_index(obj);
4067 return Address((address)obj, oop_Relocation::spec(oop_index));
4068 }
4069
4070 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4071 void MacroAssembler::tlab_allocate(Register obj,
4072 Register var_size_in_bytes,
4073 int con_size_in_bytes,
4074 Register t1,
4075 Register t2,
4076 Label& slow_case) {
4077 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4078 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4079 }
4080
4081 // Defines obj, preserves var_size_in_bytes
4082 void MacroAssembler::eden_allocate(Register thread, Register obj,
4083 Register var_size_in_bytes,
4084 int con_size_in_bytes,
4085 Register t1,
4086 Label& slow_case) {
4087 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4088 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4089 }
4090
4091 // Zero words; len is in bytes
4092 // Destroys all registers except addr
4093 // len must be a nonzero multiple of wordSize
4094 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) {
4095 assert_different_registers(addr, len, t1, rscratch1, rscratch2);
4096
4097 #ifdef ASSERT
4098 { Label L;
4099 tst(len, BytesPerWord - 1);
4100 br(Assembler::EQ, L);
4101 stop("len is not a multiple of BytesPerWord");
4102 bind(L);
4103 }
4104 #endif
4105
4106 #ifndef PRODUCT
4107 block_comment("zero memory");
4108 #endif
4109
4110 Label loop;
4111 Label entry;
4112
4113 // Algorithm:
4114 //
4115 // scratch1 = cnt & 7;
4116 // cnt -= scratch1;
4117 // p += scratch1;
4118 // switch (scratch1) {
4119 // do {
4120 // cnt -= 8;
4121 // p[-8] = 0;
4122 // case 7:
4123 // p[-7] = 0;
4124 // case 6:
4125 // p[-6] = 0;
4126 // // ...
4127 // case 1:
4128 // p[-1] = 0;
4129 // case 0:
4130 // p += 8;
4131 // } while (cnt);
4132 // }
4133
4134 const int unroll = 8; // Number of str(zr) instructions we'll unroll
4135
4136 lsr(len, len, LogBytesPerWord);
4137 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll
4138 sub(len, len, rscratch1); // cnt -= unroll
4139 // t1 always points to the end of the region we're about to zero
4140 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord);
4141 adr(rscratch2, entry);
4142 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2);
4143 br(rscratch2);
4144 bind(loop);
4145 sub(len, len, unroll);
4146 for (int i = -unroll; i < 0; i++)
4147 Assembler::str(zr, Address(t1, i * wordSize));
4148 bind(entry);
4149 add(t1, t1, unroll * wordSize);
4150 cbnz(len, loop);
4151 }
4152
4153 void MacroAssembler::verify_tlab() {
4154 #ifdef ASSERT
4155 if (UseTLAB && VerifyOops) {
4156 Label next, ok;
4157
4158 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4159
4160 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4161 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4162 cmp(rscratch2, rscratch1);
4163 br(Assembler::HS, next);
4164 STOP("assert(top >= start)");
4165 should_not_reach_here();
4166
4167 bind(next);
4168 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4169 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4170 cmp(rscratch2, rscratch1);
4171 br(Assembler::HS, ok);
4172 STOP("assert(top <= end)");
4173 should_not_reach_here();
4174
4175 bind(ok);
4176 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4177 }
4178 #endif
4179 }
4180
4181 // Writes to stack successive pages until offset reached to check for
4182 // stack overflow + shadow pages. This clobbers tmp.
4183 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4184 assert_different_registers(tmp, size, rscratch1);
4185 mov(tmp, sp);
4186 // Bang stack for total size given plus shadow page size.
4187 // Bang one page at a time because large size can bang beyond yellow and
4188 // red zones.
4189 Label loop;
4190 mov(rscratch1, os::vm_page_size());
4191 bind(loop);
4192 lea(tmp, Address(tmp, -os::vm_page_size()));
4193 subsw(size, size, rscratch1);
4194 str(size, Address(tmp));
4195 br(Assembler::GT, loop);
4196
4197 // Bang down shadow pages too.
4198 // At this point, (tmp-0) is the last address touched, so don't
4199 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4200 // was post-decremented.) Skip this address by starting at i=1, and
4201 // touch a few more pages below. N.B. It is important to touch all
4202 // the way down to and including i=StackShadowPages.
4203 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
4204 // this could be any sized move but this is can be a debugging crumb
4205 // so the bigger the better.
4206 lea(tmp, Address(tmp, -os::vm_page_size()));
4207 str(size, Address(tmp));
4208 }
4209 }
4210
4211
4212 // Move the address of the polling page into dest.
4213 void MacroAssembler::get_polling_page(Register dest, address page, relocInfo::relocType rtype) {
4214 if (SafepointMechanism::uses_thread_local_poll()) {
4215 ldr(dest, Address(rthread, Thread::polling_page_offset()));
4216 } else {
4217 unsigned long off;
4218 adrp(dest, Address(page, rtype), off);
4219 assert(off == 0, "polling page must be page aligned");
4220 }
4221 }
4222
4223 // Move the address of the polling page into r, then read the polling
4224 // page.
4225 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
4226 get_polling_page(r, page, rtype);
4227 return read_polling_page(r, rtype);
4228 }
4229
4230 // Read the polling page. The address of the polling page must
4231 // already be in r.
4232 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
4233 InstructionMark im(this);
4234 code_section()->relocate(inst_mark(), rtype);
4235 ldrw(zr, Address(r, 0));
4236 return inst_mark();
4237 }
4238
4239 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
4240 relocInfo::relocType rtype = dest.rspec().reloc()->type();
4241 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
4242 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
4243 unsigned long dest_page = (unsigned long)dest.target() >> 12;
4244 long offset_low = dest_page - low_page;
4245 long offset_high = dest_page - high_page;
4246
4247 assert(is_valid_AArch64_address(dest.target()), "bad address");
4248 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
4249
4250 InstructionMark im(this);
4251 code_section()->relocate(inst_mark(), dest.rspec());
4252 // 8143067: Ensure that the adrp can reach the dest from anywhere within
4253 // the code cache so that if it is relocated we know it will still reach
4254 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
4255 _adrp(reg1, dest.target());
4256 } else {
4257 unsigned long target = (unsigned long)dest.target();
4258 unsigned long adrp_target
4259 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
4260
4261 _adrp(reg1, (address)adrp_target);
4262 movk(reg1, target >> 32, 32);
4263 }
4264 byte_offset = (unsigned long)dest.target() & 0xfff;
4265 }
4266
4267 void MacroAssembler::load_byte_map_base(Register reg) {
4268 jbyte *byte_map_base =
4269 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
4270
4271 if (is_valid_AArch64_address((address)byte_map_base)) {
4272 // Strictly speaking the byte_map_base isn't an address at all,
4273 // and it might even be negative.
4274 unsigned long offset;
4275 adrp(reg, ExternalAddress((address)byte_map_base), offset);
4276 // We expect offset to be zero with most collectors.
4277 if (offset != 0) {
4278 add(reg, reg, offset);
4279 }
4280 } else {
4281 mov(reg, (uint64_t)byte_map_base);
4282 }
4283 }
4284
4285 void MacroAssembler::build_frame(int framesize) {
4286 assert(framesize > 0, "framesize must be > 0");
4287 if (framesize < ((1 << 9) + 2 * wordSize)) {
4288 sub(sp, sp, framesize);
4289 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4290 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4291 } else {
4292 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4293 if (PreserveFramePointer) mov(rfp, sp);
4294 if (framesize < ((1 << 12) + 2 * wordSize))
4295 sub(sp, sp, framesize - 2 * wordSize);
4296 else {
4297 mov(rscratch1, framesize - 2 * wordSize);
4298 sub(sp, sp, rscratch1);
4299 }
4300 }
4301 }
4302
4303 void MacroAssembler::remove_frame(int framesize) {
4304 assert(framesize > 0, "framesize must be > 0");
4305 if (framesize < ((1 << 9) + 2 * wordSize)) {
4306 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4307 add(sp, sp, framesize);
4308 } else {
4309 if (framesize < ((1 << 12) + 2 * wordSize))
4310 add(sp, sp, framesize - 2 * wordSize);
4311 else {
4312 mov(rscratch1, framesize - 2 * wordSize);
4313 add(sp, sp, rscratch1);
4314 }
4315 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4316 }
4317 }
4318
4319 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4320
4321 // Search for str1 in str2 and return index or -1
4322 void MacroAssembler::string_indexof(Register str2, Register str1,
4323 Register cnt2, Register cnt1,
4324 Register tmp1, Register tmp2,
4325 Register tmp3, Register tmp4,
4326 int icnt1, Register result, int ae) {
4327 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4328
4329 Register ch1 = rscratch1;
4330 Register ch2 = rscratch2;
4331 Register cnt1tmp = tmp1;
4332 Register cnt2tmp = tmp2;
4333 Register cnt1_neg = cnt1;
4334 Register cnt2_neg = cnt2;
4335 Register result_tmp = tmp4;
4336
4337 bool isL = ae == StrIntrinsicNode::LL;
4338
4339 bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL;
4340 bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU;
4341 int str1_chr_shift = str1_isL ? 0:1;
4342 int str2_chr_shift = str2_isL ? 0:1;
4343 int str1_chr_size = str1_isL ? 1:2;
4344 int str2_chr_size = str2_isL ? 1:2;
4345 chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4346 (chr_insn)&MacroAssembler::ldrh;
4347 chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4348 (chr_insn)&MacroAssembler::ldrh;
4349 chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw;
4350 chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr;
4351
4352 // Note, inline_string_indexOf() generates checks:
4353 // if (substr.count > string.count) return -1;
4354 // if (substr.count == 0) return 0;
4355
4356 // We have two strings, a source string in str2, cnt2 and a pattern string
4357 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4358
4359 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4360 // With a small pattern and source we use linear scan.
4361
4362 if (icnt1 == -1) {
4363 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4364 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4365 br(LO, LINEARSEARCH); // a byte array.
4366 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4367 br(HS, LINEARSEARCH);
4368 }
4369
4370 // The Boyer Moore alogorithm is based on the description here:-
4371 //
4372 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4373 //
4374 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4375 // and the 'Good Suffix' rule.
4376 //
4377 // These rules are essentially heuristics for how far we can shift the
4378 // pattern along the search string.
4379 //
4380 // The implementation here uses the 'Bad Character' rule only because of the
4381 // complexity of initialisation for the 'Good Suffix' rule.
4382 //
4383 // This is also known as the Boyer-Moore-Horspool algorithm:-
4384 //
4385 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4386 //
4387 // #define ASIZE 128
4388 //
4389 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4390 // int i, j;
4391 // unsigned c;
4392 // unsigned char bc[ASIZE];
4393 //
4394 // /* Preprocessing */
4395 // for (i = 0; i < ASIZE; ++i)
4396 // bc[i] = 0;
4397 // for (i = 0; i < m - 1; ) {
4398 // c = x[i];
4399 // ++i;
4400 // if (c < ASIZE) bc[c] = i;
4401 // }
4402 //
4403 // /* Searching */
4404 // j = 0;
4405 // while (j <= n - m) {
4406 // c = y[i+j];
4407 // if (x[m-1] == c)
4408 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4409 // if (i < 0) return j;
4410 // if (c < ASIZE)
4411 // j = j - bc[y[j+m-1]] + m;
4412 // else
4413 // j += 1; // Advance by 1 only if char >= ASIZE
4414 // }
4415 // }
4416
4417 if (icnt1 == -1) {
4418 BIND(BM);
4419
4420 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4421 Label BMADV, BMMATCH, BMCHECKEND;
4422
4423 Register cnt1end = tmp2;
4424 Register str2end = cnt2;
4425 Register skipch = tmp2;
4426
4427 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4428 // The presence of chars >= ASIZE in the target string does not affect
4429 // performance, but we must be careful not to initialise them in the stack
4430 // array.
4431 // The presence of chars >= ASIZE in the source string may adversely affect
4432 // performance since we can only advance by one when we encounter one.
4433
4434 stp(zr, zr, pre(sp, -128));
4435 for (int i = 1; i < 8; i++)
4436 stp(zr, zr, Address(sp, i*16));
4437
4438 mov(cnt1tmp, 0);
4439 sub(cnt1end, cnt1, 1);
4440 BIND(BCLOOP);
4441 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4442 cmp(ch1, 128);
4443 add(cnt1tmp, cnt1tmp, 1);
4444 br(HS, BCSKIP);
4445 strb(cnt1tmp, Address(sp, ch1));
4446 BIND(BCSKIP);
4447 cmp(cnt1tmp, cnt1end);
4448 br(LT, BCLOOP);
4449
4450 mov(result_tmp, str2);
4451
4452 sub(cnt2, cnt2, cnt1);
4453 add(str2end, str2, cnt2, LSL, str2_chr_shift);
4454 BIND(BMLOOPSTR2);
4455 sub(cnt1tmp, cnt1, 1);
4456 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4457 (this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4458 cmp(ch1, skipch);
4459 br(NE, BMSKIP);
4460 subs(cnt1tmp, cnt1tmp, 1);
4461 br(LT, BMMATCH);
4462 BIND(BMLOOPSTR1);
4463 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4464 (this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4465 cmp(ch1, ch2);
4466 br(NE, BMSKIP);
4467 subs(cnt1tmp, cnt1tmp, 1);
4468 br(GE, BMLOOPSTR1);
4469 BIND(BMMATCH);
4470 sub(result, str2, result_tmp);
4471 if (!str2_isL) lsr(result, result, 1);
4472 add(sp, sp, 128);
4473 b(DONE);
4474 BIND(BMADV);
4475 add(str2, str2, str2_chr_size);
4476 b(BMCHECKEND);
4477 BIND(BMSKIP);
4478 cmp(skipch, 128);
4479 br(HS, BMADV);
4480 ldrb(ch2, Address(sp, skipch));
4481 add(str2, str2, cnt1, LSL, str2_chr_shift);
4482 sub(str2, str2, ch2, LSL, str2_chr_shift);
4483 BIND(BMCHECKEND);
4484 cmp(str2, str2end);
4485 br(LE, BMLOOPSTR2);
4486 add(sp, sp, 128);
4487 b(NOMATCH);
4488 }
4489
4490 BIND(LINEARSEARCH);
4491 {
4492 Label DO1, DO2, DO3;
4493
4494 Register str2tmp = tmp2;
4495 Register first = tmp3;
4496
4497 if (icnt1 == -1)
4498 {
4499 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT;
4500
4501 cmp(cnt1, str1_isL == str2_isL ? 4 : 2);
4502 br(LT, DOSHORT);
4503
4504 sub(cnt2, cnt2, cnt1);
4505 mov(result_tmp, cnt2);
4506
4507 lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift)));
4508 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4509 sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift);
4510 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4511 (this->*str1_load_1chr)(first, Address(str1, cnt1_neg));
4512
4513 BIND(FIRST_LOOP);
4514 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4515 cmp(first, ch2);
4516 br(EQ, STR1_LOOP);
4517 BIND(STR2_NEXT);
4518 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4519 br(LE, FIRST_LOOP);
4520 b(NOMATCH);
4521
4522 BIND(STR1_LOOP);
4523 adds(cnt1tmp, cnt1_neg, str1_chr_size);
4524 add(cnt2tmp, cnt2_neg, str2_chr_size);
4525 br(GE, MATCH);
4526
4527 BIND(STR1_NEXT);
4528 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp));
4529 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4530 cmp(ch1, ch2);
4531 br(NE, STR2_NEXT);
4532 adds(cnt1tmp, cnt1tmp, str1_chr_size);
4533 add(cnt2tmp, cnt2tmp, str2_chr_size);
4534 br(LT, STR1_NEXT);
4535 b(MATCH);
4536
4537 BIND(DOSHORT);
4538 if (str1_isL == str2_isL) {
4539 cmp(cnt1, 2);
4540 br(LT, DO1);
4541 br(GT, DO3);
4542 }
4543 }
4544
4545 if (icnt1 == 4) {
4546 Label CH1_LOOP;
4547
4548 (this->*load_4chr)(ch1, str1);
4549 sub(cnt2, cnt2, 4);
4550 mov(result_tmp, cnt2);
4551 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4552 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4553
4554 BIND(CH1_LOOP);
4555 (this->*load_4chr)(ch2, Address(str2, cnt2_neg));
4556 cmp(ch1, ch2);
4557 br(EQ, MATCH);
4558 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4559 br(LE, CH1_LOOP);
4560 b(NOMATCH);
4561 }
4562
4563 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) {
4564 Label CH1_LOOP;
4565
4566 BIND(DO2);
4567 (this->*load_2chr)(ch1, str1);
4568 sub(cnt2, cnt2, 2);
4569 mov(result_tmp, cnt2);
4570 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4571 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4572
4573 BIND(CH1_LOOP);
4574 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4575 cmp(ch1, ch2);
4576 br(EQ, MATCH);
4577 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4578 br(LE, CH1_LOOP);
4579 b(NOMATCH);
4580 }
4581
4582 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) {
4583 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4584
4585 BIND(DO3);
4586 (this->*load_2chr)(first, str1);
4587 (this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size));
4588
4589 sub(cnt2, cnt2, 3);
4590 mov(result_tmp, cnt2);
4591 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4592 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4593
4594 BIND(FIRST_LOOP);
4595 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4596 cmpw(first, ch2);
4597 br(EQ, STR1_LOOP);
4598 BIND(STR2_NEXT);
4599 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4600 br(LE, FIRST_LOOP);
4601 b(NOMATCH);
4602
4603 BIND(STR1_LOOP);
4604 add(cnt2tmp, cnt2_neg, 2*str2_chr_size);
4605 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4606 cmp(ch1, ch2);
4607 br(NE, STR2_NEXT);
4608 b(MATCH);
4609 }
4610
4611 if (icnt1 == -1 || icnt1 == 1) {
4612 Label CH1_LOOP, HAS_ZERO;
4613 Label DO1_SHORT, DO1_LOOP;
4614
4615 BIND(DO1);
4616 (this->*str1_load_1chr)(ch1, str1);
4617 cmp(cnt2, 8);
4618 br(LT, DO1_SHORT);
4619
4620 if (str2_isL) {
4621 if (!str1_isL) {
4622 tst(ch1, 0xff00);
4623 br(NE, NOMATCH);
4624 }
4625 orr(ch1, ch1, ch1, LSL, 8);
4626 }
4627 orr(ch1, ch1, ch1, LSL, 16);
4628 orr(ch1, ch1, ch1, LSL, 32);
4629
4630 sub(cnt2, cnt2, 8/str2_chr_size);
4631 mov(result_tmp, cnt2);
4632 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4633 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4634
4635 mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001);
4636 BIND(CH1_LOOP);
4637 ldr(ch2, Address(str2, cnt2_neg));
4638 eor(ch2, ch1, ch2);
4639 sub(tmp1, ch2, tmp3);
4640 orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
4641 bics(tmp1, tmp1, tmp2);
4642 br(NE, HAS_ZERO);
4643 adds(cnt2_neg, cnt2_neg, 8);
4644 br(LT, CH1_LOOP);
4645
4646 cmp(cnt2_neg, 8);
4647 mov(cnt2_neg, 0);
4648 br(LT, CH1_LOOP);
4649 b(NOMATCH);
4650
4651 BIND(HAS_ZERO);
4652 rev(tmp1, tmp1);
4653 clz(tmp1, tmp1);
4654 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4655 b(MATCH);
4656
4657 BIND(DO1_SHORT);
4658 mov(result_tmp, cnt2);
4659 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4660 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4661 BIND(DO1_LOOP);
4662 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4663 cmpw(ch1, ch2);
4664 br(EQ, MATCH);
4665 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4666 br(LT, DO1_LOOP);
4667 }
4668 }
4669 BIND(NOMATCH);
4670 mov(result, -1);
4671 b(DONE);
4672 BIND(MATCH);
4673 add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift);
4674 BIND(DONE);
4675 }
4676
4677 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4678 typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn);
4679
4680 void MacroAssembler::string_indexof_char(Register str1, Register cnt1,
4681 Register ch, Register result,
4682 Register tmp1, Register tmp2, Register tmp3)
4683 {
4684 Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE;
4685 Register cnt1_neg = cnt1;
4686 Register ch1 = rscratch1;
4687 Register result_tmp = rscratch2;
4688
4689 cmp(cnt1, 4);
4690 br(LT, DO1_SHORT);
4691
4692 orr(ch, ch, ch, LSL, 16);
4693 orr(ch, ch, ch, LSL, 32);
4694
4695 sub(cnt1, cnt1, 4);
4696 mov(result_tmp, cnt1);
4697 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4698 sub(cnt1_neg, zr, cnt1, LSL, 1);
4699
4700 mov(tmp3, 0x0001000100010001);
4701
4702 BIND(CH1_LOOP);
4703 ldr(ch1, Address(str1, cnt1_neg));
4704 eor(ch1, ch, ch1);
4705 sub(tmp1, ch1, tmp3);
4706 orr(tmp2, ch1, 0x7fff7fff7fff7fff);
4707 bics(tmp1, tmp1, tmp2);
4708 br(NE, HAS_ZERO);
4709 adds(cnt1_neg, cnt1_neg, 8);
4710 br(LT, CH1_LOOP);
4711
4712 cmp(cnt1_neg, 8);
4713 mov(cnt1_neg, 0);
4714 br(LT, CH1_LOOP);
4715 b(NOMATCH);
4716
4717 BIND(HAS_ZERO);
4718 rev(tmp1, tmp1);
4719 clz(tmp1, tmp1);
4720 add(cnt1_neg, cnt1_neg, tmp1, LSR, 3);
4721 b(MATCH);
4722
4723 BIND(DO1_SHORT);
4724 mov(result_tmp, cnt1);
4725 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4726 sub(cnt1_neg, zr, cnt1, LSL, 1);
4727 BIND(DO1_LOOP);
4728 ldrh(ch1, Address(str1, cnt1_neg));
4729 cmpw(ch, ch1);
4730 br(EQ, MATCH);
4731 adds(cnt1_neg, cnt1_neg, 2);
4732 br(LT, DO1_LOOP);
4733 BIND(NOMATCH);
4734 mov(result, -1);
4735 b(DONE);
4736 BIND(MATCH);
4737 add(result, result_tmp, cnt1_neg, ASR, 1);
4738 BIND(DONE);
4739 }
4740
4741 // Compare strings.
4742 void MacroAssembler::string_compare(Register str1, Register str2,
4743 Register cnt1, Register cnt2, Register result,
4744 Register tmp1,
4745 FloatRegister vtmp, FloatRegister vtmpZ, int ae) {
4746 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4747 NEXT_WORD, DIFFERENCE;
4748
4749 bool isLL = ae == StrIntrinsicNode::LL;
4750 bool isLU = ae == StrIntrinsicNode::LU;
4751 bool isUL = ae == StrIntrinsicNode::UL;
4752
4753 bool str1_isL = isLL || isLU;
4754 bool str2_isL = isLL || isUL;
4755
4756 int str1_chr_shift = str1_isL ? 0 : 1;
4757 int str2_chr_shift = str2_isL ? 0 : 1;
4758 int str1_chr_size = str1_isL ? 1 : 2;
4759 int str2_chr_size = str2_isL ? 1 : 2;
4760
4761 chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4762 (chr_insn)&MacroAssembler::ldrh;
4763 chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4764 (chr_insn)&MacroAssembler::ldrh;
4765 uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw :
4766 (uxt_insn)&MacroAssembler::uxthw;
4767
4768 BLOCK_COMMENT("string_compare {");
4769
4770 // Bizzarely, the counts are passed in bytes, regardless of whether they
4771 // are L or U strings, however the result is always in characters.
4772 if (!str1_isL) asrw(cnt1, cnt1, 1);
4773 if (!str2_isL) asrw(cnt2, cnt2, 1);
4774
4775 // Compute the minimum of the string lengths and save the difference.
4776 subsw(tmp1, cnt1, cnt2);
4777 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4778
4779 // A very short string
4780 cmpw(cnt2, isLL ? 8:4);
4781 br(Assembler::LT, SHORT_STRING);
4782
4783 // Check if the strings start at the same location.
4784 cmp(str1, str2);
4785 br(Assembler::EQ, LENGTH_DIFF);
4786
4787 // Compare longwords
4788 {
4789 subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case
4790
4791 // Move both string pointers to the last longword of their
4792 // strings, negate the remaining count, and convert it to bytes.
4793 lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift)));
4794 lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift)));
4795 if (isLU || isUL) {
4796 sub(cnt1, zr, cnt2, LSL, str1_chr_shift);
4797 eor(vtmpZ, T16B, vtmpZ, vtmpZ);
4798 }
4799 sub(cnt2, zr, cnt2, LSL, str2_chr_shift);
4800
4801 // Loop, loading longwords and comparing them into rscratch2.
4802 bind(NEXT_WORD);
4803 if (isLU) {
4804 ldrs(vtmp, Address(str1, cnt1));
4805 zip1(vtmp, T8B, vtmp, vtmpZ);
4806 umov(result, vtmp, D, 0);
4807 } else {
4808 ldr(result, Address(str1, isUL ? cnt1:cnt2));
4809 }
4810 if (isUL) {
4811 ldrs(vtmp, Address(str2, cnt2));
4812 zip1(vtmp, T8B, vtmp, vtmpZ);
4813 umov(rscratch1, vtmp, D, 0);
4814 } else {
4815 ldr(rscratch1, Address(str2, cnt2));
4816 }
4817 adds(cnt2, cnt2, isUL ? 4:8);
4818 if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8);
4819 eor(rscratch2, result, rscratch1);
4820 cbnz(rscratch2, DIFFERENCE);
4821 br(Assembler::LT, NEXT_WORD);
4822
4823 // Last longword. In the case where length == 4 we compare the
4824 // same longword twice, but that's still faster than another
4825 // conditional branch.
4826
4827 if (isLU) {
4828 ldrs(vtmp, Address(str1));
4829 zip1(vtmp, T8B, vtmp, vtmpZ);
4830 umov(result, vtmp, D, 0);
4831 } else {
4832 ldr(result, Address(str1));
4833 }
4834 if (isUL) {
4835 ldrs(vtmp, Address(str2));
4836 zip1(vtmp, T8B, vtmp, vtmpZ);
4837 umov(rscratch1, vtmp, D, 0);
4838 } else {
4839 ldr(rscratch1, Address(str2));
4840 }
4841 eor(rscratch2, result, rscratch1);
4842 cbz(rscratch2, LENGTH_DIFF);
4843
4844 // Find the first different characters in the longwords and
4845 // compute their difference.
4846 bind(DIFFERENCE);
4847 rev(rscratch2, rscratch2);
4848 clz(rscratch2, rscratch2);
4849 andr(rscratch2, rscratch2, isLL ? -8 : -16);
4850 lsrv(result, result, rscratch2);
4851 (this->*ext_chr)(result, result);
4852 lsrv(rscratch1, rscratch1, rscratch2);
4853 (this->*ext_chr)(rscratch1, rscratch1);
4854 subw(result, result, rscratch1);
4855 b(DONE);
4856 }
4857
4858 bind(SHORT_STRING);
4859 // Is the minimum length zero?
4860 cbz(cnt2, LENGTH_DIFF);
4861
4862 bind(SHORT_LOOP);
4863 (this->*str1_load_chr)(result, Address(post(str1, str1_chr_size)));
4864 (this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size)));
4865 subw(result, result, cnt1);
4866 cbnz(result, DONE);
4867 sub(cnt2, cnt2, 1);
4868 cbnz(cnt2, SHORT_LOOP);
4869
4870 // Strings are equal up to min length. Return the length difference.
4871 bind(LENGTH_DIFF);
4872 mov(result, tmp1);
4873
4874 // That's it
4875 bind(DONE);
4876
4877 BLOCK_COMMENT("} string_compare");
4878 }
4879
4880 // This method checks if provided byte array contains byte with highest bit set.
4881 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) {
4882 // Simple and most common case of aligned small array which is not at the
4883 // end of memory page is placed here. All other cases are in stub.
4884 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4885 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4886 assert_different_registers(ary1, len, result);
4887
4888 cmpw(len, 0);
4889 br(LE, SET_RESULT);
4890 cmpw(len, 4 * wordSize);
4891 br(GE, STUB_LONG); // size > 32 then go to stub
4892
4893 int shift = 64 - exact_log2(os::vm_page_size());
4894 lsl(rscratch1, ary1, shift);
4895 mov(rscratch2, (size_t)(4 * wordSize) << shift);
4896 adds(rscratch2, rscratch1, rscratch2); // At end of page?
4897 br(CS, STUB); // at the end of page then go to stub
4898 subs(len, len, wordSize);
4899 br(LT, END);
4900
4901 BIND(LOOP);
4902 ldr(rscratch1, Address(post(ary1, wordSize)));
4903 tst(rscratch1, UPPER_BIT_MASK);
4904 br(NE, SET_RESULT);
4905 subs(len, len, wordSize);
4906 br(GE, LOOP);
4907 cmpw(len, -wordSize);
4908 br(EQ, SET_RESULT);
4909
4910 BIND(END);
4911 ldr(result, Address(ary1));
4912 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
4913 lslv(result, result, len);
4914 tst(result, UPPER_BIT_MASK);
4915 b(SET_RESULT);
4916
4917 BIND(STUB);
4918 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives());
4919 assert(has_neg.target() != NULL, "has_negatives stub has not been generated");
4920 trampoline_call(has_neg);
4921 b(DONE);
4922
4923 BIND(STUB_LONG);
4924 RuntimeAddress has_neg_long = RuntimeAddress(
4925 StubRoutines::aarch64::has_negatives_long());
4926 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated");
4927 trampoline_call(has_neg_long);
4928 b(DONE);
4929
4930 BIND(SET_RESULT);
4931 cset(result, NE); // set true or false
4932
4933 BIND(DONE);
4934 }
4935
4936 void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
4937 Register tmp4, Register tmp5, Register result,
4938 Register cnt1, int elem_size)
4939 {
4940 Label DONE;
4941 Register tmp1 = rscratch1;
4942 Register tmp2 = rscratch2;
4943 Register cnt2 = tmp2; // cnt2 only used in array length compare
4944 int elem_per_word = wordSize/elem_size;
4945 int log_elem_size = exact_log2(elem_size);
4946 int length_offset = arrayOopDesc::length_offset_in_bytes();
4947 int base_offset
4948 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
4949 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
4950
4951 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
4952 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
4953
4954 #ifndef PRODUCT
4955 {
4956 const char kind = (elem_size == 2) ? 'U' : 'L';
4957 char comment[64];
4958 snprintf(comment, sizeof comment, "array_equals%c{", kind);
4959 BLOCK_COMMENT(comment);
4960 }
4961 #endif
4962 if (UseSimpleArrayEquals) {
4963 Label NEXT_WORD, SHORT, SAME, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
4964 // if (a1==a2)
4965 // return true;
4966 // if (a==null || a2==null)
4967 // return false;
4968 // a1 & a2 == 0 means (some-pointer is null) or
4969 // (very-rare-or-even-probably-impossible-pointer-values)
4970 // so, we can save one branch in most cases
4971 cmpoop(a1, a2);
4972 br(EQ, SAME);
4973 eor(rscratch1, a1, a2);
4974 tst(a1, a2);
4975 mov(result, false);
4976 cbz(rscratch1, SAME);
4977 br(EQ, A_MIGHT_BE_NULL);
4978 // if (a1.length != a2.length)
4979 // return false;
4980 bind(A_IS_NOT_NULL);
4981 ldrw(cnt1, Address(a1, length_offset));
4982 ldrw(cnt2, Address(a2, length_offset));
4983 eorw(tmp5, cnt1, cnt2);
4984 cbnzw(tmp5, DONE);
4985 lea(a1, Address(a1, base_offset));
4986 lea(a2, Address(a2, base_offset));
4987 // Check for short strings, i.e. smaller than wordSize.
4988 subs(cnt1, cnt1, elem_per_word);
4989 br(Assembler::LT, SHORT);
4990 // Main 8 byte comparison loop.
4991 bind(NEXT_WORD); {
4992 ldr(tmp1, Address(post(a1, wordSize)));
4993 ldr(tmp2, Address(post(a2, wordSize)));
4994 subs(cnt1, cnt1, elem_per_word);
4995 eor(tmp5, tmp1, tmp2);
4996 cbnz(tmp5, DONE);
4997 } br(GT, NEXT_WORD);
4998 // Last longword. In the case where length == 4 we compare the
4999 // same longword twice, but that's still faster than another
5000 // conditional branch.
5001 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5002 // length == 4.
5003 if (log_elem_size > 0)
5004 lsl(cnt1, cnt1, log_elem_size);
5005 ldr(tmp3, Address(a1, cnt1));
5006 ldr(tmp4, Address(a2, cnt1));
5007 eor(tmp5, tmp3, tmp4);
5008 cbnz(tmp5, DONE);
5009 b(SAME);
5010 bind(A_MIGHT_BE_NULL);
5011 // in case both a1 and a2 are not-null, proceed with loads
5012 cbz(a1, DONE);
5013 cbz(a2, DONE);
5014 b(A_IS_NOT_NULL);
5015 bind(SHORT);
5016
5017 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5018 {
5019 ldrw(tmp1, Address(post(a1, 4)));
5020 ldrw(tmp2, Address(post(a2, 4)));
5021 eorw(tmp5, tmp1, tmp2);
5022 cbnzw(tmp5, DONE);
5023 }
5024 bind(TAIL03);
5025 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5026 {
5027 ldrh(tmp3, Address(post(a1, 2)));
5028 ldrh(tmp4, Address(post(a2, 2)));
5029 eorw(tmp5, tmp3, tmp4);
5030 cbnzw(tmp5, DONE);
5031 }
5032 bind(TAIL01);
5033 if (elem_size == 1) { // Only needed when comparing byte arrays.
5034 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5035 {
5036 ldrb(tmp1, a1);
5037 ldrb(tmp2, a2);
5038 eorw(tmp5, tmp1, tmp2);
5039 cbnzw(tmp5, DONE);
5040 }
5041 }
5042 bind(SAME);
5043 mov(result, true);
5044 } else {
5045 Label NEXT_DWORD, A_IS_NULL, SHORT, TAIL, TAIL2, STUB, EARLY_OUT,
5046 CSET_EQ, LAST_CHECK, LEN_IS_ZERO, SAME;
5047 cbz(a1, A_IS_NULL);
5048 ldrw(cnt1, Address(a1, length_offset));
5049 cbz(a2, A_IS_NULL);
5050 ldrw(cnt2, Address(a2, length_offset));
5051 mov(result, false);
5052 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5053 // faster to perform another branch before comparing a1 and a2
5054 cmp(cnt1, elem_per_word);
5055 br(LE, SHORT); // short or same
5056 cmpoop(a1, a2);
5057 br(EQ, SAME);
5058 ldr(tmp3, Address(pre(a1, base_offset)));
5059 cmp(cnt1, stubBytesThreshold);
5060 br(GE, STUB);
5061 ldr(tmp4, Address(pre(a2, base_offset)));
5062 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5063 cmp(cnt2, cnt1);
5064 br(NE, DONE);
5065
5066 // Main 16 byte comparison loop with 2 exits
5067 bind(NEXT_DWORD); {
5068 ldr(tmp1, Address(pre(a1, wordSize)));
5069 ldr(tmp2, Address(pre(a2, wordSize)));
5070 subs(cnt1, cnt1, 2 * elem_per_word);
5071 br(LE, TAIL);
5072 eor(tmp4, tmp3, tmp4);
5073 cbnz(tmp4, DONE);
5074 ldr(tmp3, Address(pre(a1, wordSize)));
5075 ldr(tmp4, Address(pre(a2, wordSize)));
5076 cmp(cnt1, elem_per_word);
5077 br(LE, TAIL2);
5078 cmp(tmp1, tmp2);
5079 } br(EQ, NEXT_DWORD);
5080 b(DONE);
5081
5082 bind(TAIL);
5083 eor(tmp4, tmp3, tmp4);
5084 eor(tmp2, tmp1, tmp2);
5085 lslv(tmp2, tmp2, tmp5);
5086 orr(tmp5, tmp4, tmp2);
5087 cmp(tmp5, zr);
5088 b(CSET_EQ);
5089
5090 bind(TAIL2);
5091 eor(tmp2, tmp1, tmp2);
5092 cbnz(tmp2, DONE);
5093 b(LAST_CHECK);
5094
5095 bind(STUB);
5096 ldr(tmp4, Address(pre(a2, base_offset)));
5097 cmp(cnt2, cnt1);
5098 br(NE, DONE);
5099 if (elem_size == 2) { // convert to byte counter
5100 lsl(cnt1, cnt1, 1);
5101 }
5102 eor(tmp5, tmp3, tmp4);
5103 cbnz(tmp5, DONE);
5104 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5105 assert(stub.target() != NULL, "array_equals_long stub has not been generated");
5106 trampoline_call(stub);
5107 b(DONE);
5108
5109 bind(SAME);
5110 mov(result, true);
5111 b(DONE);
5112 bind(A_IS_NULL);
5113 // a1 or a2 is null. if a2 == a2 then return true. else return false
5114 cmp(a1, a2);
5115 b(CSET_EQ);
5116 bind(EARLY_OUT);
5117 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5118 // so, if a2 == null => return false(0), else return true, so we can return a2
5119 mov(result, a2);
5120 b(DONE);
5121 bind(LEN_IS_ZERO);
5122 cmp(cnt2, zr);
5123 b(CSET_EQ);
5124 bind(SHORT);
5125 cbz(cnt1, LEN_IS_ZERO);
5126 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5127 ldr(tmp3, Address(a1, base_offset));
5128 ldr(tmp4, Address(a2, base_offset));
5129 bind(LAST_CHECK);
5130 eor(tmp4, tmp3, tmp4);
5131 lslv(tmp5, tmp4, tmp5);
5132 cmp(tmp5, zr);
5133 bind(CSET_EQ);
5134 cset(result, EQ);
5135 }
5136
5137 // That's it.
5138 bind(DONE);
5139
5140 BLOCK_COMMENT("} array_equals");
5141 }
5142
5143 // Compare Strings
5144
5145 // For Strings we're passed the address of the first characters in a1
5146 // and a2 and the length in cnt1.
5147 // elem_size is the element size in bytes: either 1 or 2.
5148 // There are two implementations. For arrays >= 8 bytes, all
5149 // comparisons (including the final one, which may overlap) are
5150 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5151 // halfword, then a short, and then a byte.
5152
5153 void MacroAssembler::string_equals(Register a1, Register a2,
5154 Register result, Register cnt1, int elem_size)
5155 {
5156 Label SAME, DONE, SHORT, NEXT_WORD;
5157 Register tmp1 = rscratch1;
5158 Register tmp2 = rscratch2;
5159 Register cnt2 = tmp2; // cnt2 only used in array length compare
5160
5161 assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte");
5162 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5163
5164 #ifndef PRODUCT
5165 {
5166 const char kind = (elem_size == 2) ? 'U' : 'L';
5167 char comment[64];
5168 snprintf(comment, sizeof comment, "{string_equals%c", kind);
5169 BLOCK_COMMENT(comment);
5170 }
5171 #endif
5172
5173 mov(result, false);
5174
5175 // Check for short strings, i.e. smaller than wordSize.
5176 subs(cnt1, cnt1, wordSize);
5177 br(Assembler::LT, SHORT);
5178 // Main 8 byte comparison loop.
5179 bind(NEXT_WORD); {
5180 ldr(tmp1, Address(post(a1, wordSize)));
5181 ldr(tmp2, Address(post(a2, wordSize)));
5182 subs(cnt1, cnt1, wordSize);
5183 eor(tmp1, tmp1, tmp2);
5184 cbnz(tmp1, DONE);
5185 } br(GT, NEXT_WORD);
5186 // Last longword. In the case where length == 4 we compare the
5187 // same longword twice, but that's still faster than another
5188 // conditional branch.
5189 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5190 // length == 4.
5191 ldr(tmp1, Address(a1, cnt1));
5192 ldr(tmp2, Address(a2, cnt1));
5193 eor(tmp2, tmp1, tmp2);
5194 cbnz(tmp2, DONE);
5195 b(SAME);
5196
5197 bind(SHORT);
5198 Label TAIL03, TAIL01;
5199
5200 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
5201 {
5202 ldrw(tmp1, Address(post(a1, 4)));
5203 ldrw(tmp2, Address(post(a2, 4)));
5204 eorw(tmp1, tmp1, tmp2);
5205 cbnzw(tmp1, DONE);
5206 }
5207 bind(TAIL03);
5208 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
5209 {
5210 ldrh(tmp1, Address(post(a1, 2)));
5211 ldrh(tmp2, Address(post(a2, 2)));
5212 eorw(tmp1, tmp1, tmp2);
5213 cbnzw(tmp1, DONE);
5214 }
5215 bind(TAIL01);
5216 if (elem_size == 1) { // Only needed when comparing 1-byte elements
5217 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5218 {
5219 ldrb(tmp1, a1);
5220 ldrb(tmp2, a2);
5221 eorw(tmp1, tmp1, tmp2);
5222 cbnzw(tmp1, DONE);
5223 }
5224 }
5225 // Arrays are equal.
5226 bind(SAME);
5227 mov(result, true);
5228
5229 // That's it.
5230 bind(DONE);
5231 BLOCK_COMMENT("} string_equals");
5232 }
5233
5234
5235 // The size of the blocks erased by the zero_blocks stub. We must
5236 // handle anything smaller than this ourselves in zero_words().
5237 const int MacroAssembler::zero_words_block_size = 8;
5238
5239 // zero_words() is used by C2 ClearArray patterns. It is as small as
5240 // possible, handling small word counts locally and delegating
5241 // anything larger to the zero_blocks stub. It is expanded many times
5242 // in compiled code, so it is important to keep it short.
5243
5244 // ptr: Address of a buffer to be zeroed.
5245 // cnt: Count in HeapWords.
5246 //
5247 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
5248 void MacroAssembler::zero_words(Register ptr, Register cnt)
5249 {
5250 assert(is_power_of_2(zero_words_block_size), "adjust this");
5251 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
5252
5253 BLOCK_COMMENT("zero_words {");
5254 cmp(cnt, zero_words_block_size);
5255 Label around, done, done16;
5256 br(LO, around);
5257 {
5258 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5259 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated");
5260 if (StubRoutines::aarch64::complete()) {
5261 trampoline_call(zero_blocks);
5262 } else {
5263 bl(zero_blocks);
5264 }
5265 }
5266 bind(around);
5267 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
5268 Label l;
5269 tbz(cnt, exact_log2(i), l);
5270 for (int j = 0; j < i; j += 2) {
5271 stp(zr, zr, post(ptr, 16));
5272 }
5273 bind(l);
5274 }
5275 {
5276 Label l;
5277 tbz(cnt, 0, l);
5278 str(zr, Address(ptr));
5279 bind(l);
5280 }
5281 BLOCK_COMMENT("} zero_words");
5282 }
5283
5284 // base: Address of a buffer to be zeroed, 8 bytes aligned.
5285 // cnt: Immediate count in HeapWords.
5286 #define SmallArraySize (18 * BytesPerLong)
5287 void MacroAssembler::zero_words(Register base, u_int64_t cnt)
5288 {
5289 BLOCK_COMMENT("zero_words {");
5290 int i = cnt & 1; // store any odd word to start
5291 if (i) str(zr, Address(base));
5292
5293 if (cnt <= SmallArraySize / BytesPerLong) {
5294 for (; i < (int)cnt; i += 2)
5295 stp(zr, zr, Address(base, i * wordSize));
5296 } else {
5297 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll
5298 int remainder = cnt % (2 * unroll);
5299 for (; i < remainder; i += 2)
5300 stp(zr, zr, Address(base, i * wordSize));
5301
5302 Label loop;
5303 Register cnt_reg = rscratch1;
5304 Register loop_base = rscratch2;
5305 cnt = cnt - remainder;
5306 mov(cnt_reg, cnt);
5307 // adjust base and prebias by -2 * wordSize so we can pre-increment
5308 add(loop_base, base, (remainder - 2) * wordSize);
5309 bind(loop);
5310 sub(cnt_reg, cnt_reg, 2 * unroll);
5311 for (i = 1; i < unroll; i++)
5312 stp(zr, zr, Address(loop_base, 2 * i * wordSize));
5313 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize)));
5314 cbnz(cnt_reg, loop);
5315 }
5316 BLOCK_COMMENT("} zero_words");
5317 }
5318
5319 // Zero blocks of memory by using DC ZVA.
5320 //
5321 // Aligns the base address first sufficently for DC ZVA, then uses
5322 // DC ZVA repeatedly for every full block. cnt is the size to be
5323 // zeroed in HeapWords. Returns the count of words left to be zeroed
5324 // in cnt.
5325 //
5326 // NOTE: This is intended to be used in the zero_blocks() stub. If
5327 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
5328 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
5329 Register tmp = rscratch1;
5330 Register tmp2 = rscratch2;
5331 int zva_length = VM_Version::zva_length();
5332 Label initial_table_end, loop_zva;
5333 Label fini;
5334
5335 // Base must be 16 byte aligned. If not just return and let caller handle it
5336 tst(base, 0x0f);
5337 br(Assembler::NE, fini);
5338 // Align base with ZVA length.
5339 neg(tmp, base);
5340 andr(tmp, tmp, zva_length - 1);
5341
5342 // tmp: the number of bytes to be filled to align the base with ZVA length.
5343 add(base, base, tmp);
5344 sub(cnt, cnt, tmp, Assembler::ASR, 3);
5345 adr(tmp2, initial_table_end);
5346 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
5347 br(tmp2);
5348
5349 for (int i = -zva_length + 16; i < 0; i += 16)
5350 stp(zr, zr, Address(base, i));
5351 bind(initial_table_end);
5352
5353 sub(cnt, cnt, zva_length >> 3);
5354 bind(loop_zva);
5355 dc(Assembler::ZVA, base);
5356 subs(cnt, cnt, zva_length >> 3);
5357 add(base, base, zva_length);
5358 br(Assembler::GE, loop_zva);
5359 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
5360 bind(fini);
5361 }
5362
5363 // base: Address of a buffer to be filled, 8 bytes aligned.
5364 // cnt: Count in 8-byte unit.
5365 // value: Value to be filled with.
5366 // base will point to the end of the buffer after filling.
5367 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
5368 {
5369 // Algorithm:
5370 //
5371 // scratch1 = cnt & 7;
5372 // cnt -= scratch1;
5373 // p += scratch1;
5374 // switch (scratch1) {
5375 // do {
5376 // cnt -= 8;
5377 // p[-8] = v;
5378 // case 7:
5379 // p[-7] = v;
5380 // case 6:
5381 // p[-6] = v;
5382 // // ...
5383 // case 1:
5384 // p[-1] = v;
5385 // case 0:
5386 // p += 8;
5387 // } while (cnt);
5388 // }
5389
5390 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
5391
5392 Label fini, skip, entry, loop;
5393 const int unroll = 8; // Number of stp instructions we'll unroll
5394
5395 cbz(cnt, fini);
5396 tbz(base, 3, skip);
5397 str(value, Address(post(base, 8)));
5398 sub(cnt, cnt, 1);
5399 bind(skip);
5400
5401 andr(rscratch1, cnt, (unroll-1) * 2);
5402 sub(cnt, cnt, rscratch1);
5403 add(base, base, rscratch1, Assembler::LSL, 3);
5404 adr(rscratch2, entry);
5405 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
5406 br(rscratch2);
5407
5408 bind(loop);
5409 add(base, base, unroll * 16);
5410 for (int i = -unroll; i < 0; i++)
5411 stp(value, value, Address(base, i * 16));
5412 bind(entry);
5413 subs(cnt, cnt, unroll * 2);
5414 br(Assembler::GE, loop);
5415
5416 tbz(cnt, 0, fini);
5417 str(value, Address(post(base, 8)));
5418 bind(fini);
5419 }
5420
5421 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and
5422 // java/lang/StringUTF16.compress.
5423 void MacroAssembler::encode_iso_array(Register src, Register dst,
5424 Register len, Register result,
5425 FloatRegister Vtmp1, FloatRegister Vtmp2,
5426 FloatRegister Vtmp3, FloatRegister Vtmp4)
5427 {
5428 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
5429 Register tmp1 = rscratch1;
5430
5431 mov(result, len); // Save initial len
5432
5433 #ifndef BUILTIN_SIM
5434 subs(len, len, 32);
5435 br(LT, LOOP_8);
5436
5437 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
5438 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
5439 // any char could not fit in a byte, so clear the FPSR so we can test it.
5440 clear_fpsr();
5441
5442 BIND(NEXT_32);
5443 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
5444 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
5445 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
5446 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
5447 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
5448 get_fpsr(tmp1);
5449 cbnzw(tmp1, LOOP_8);
5450 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
5451 subs(len, len, 32);
5452 add(src, src, 64);
5453 br(GE, NEXT_32);
5454
5455 BIND(LOOP_8);
5456 adds(len, len, 32-8);
5457 br(LT, LOOP_1);
5458 clear_fpsr(); // QC may be set from loop above, clear again
5459 BIND(NEXT_8);
5460 ld1(Vtmp1, T8H, src);
5461 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
5462 get_fpsr(tmp1);
5463 cbnzw(tmp1, LOOP_1);
5464 st1(Vtmp1, T8B, post(dst, 8));
5465 subs(len, len, 8);
5466 add(src, src, 16);
5467 br(GE, NEXT_8);
5468
5469 BIND(LOOP_1);
5470 adds(len, len, 8);
5471 br(LE, DONE);
5472 #else
5473 cbz(len, DONE);
5474 #endif
5475 BIND(NEXT_1);
5476 ldrh(tmp1, Address(post(src, 2)));
5477 tst(tmp1, 0xff00);
5478 br(NE, DONE);
5479 strb(tmp1, Address(post(dst, 1)));
5480 subs(len, len, 1);
5481 br(GT, NEXT_1);
5482
5483 BIND(DONE);
5484 sub(result, result, len); // Return index where we stopped
5485 // Return len == 0 if we processed all
5486 // characters
5487 }
5488
5489
5490 // Inflate byte[] array to char[].
5491 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
5492 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
5493 Register tmp4) {
5494 Label big, done;
5495
5496 assert_different_registers(src, dst, len, tmp4, rscratch1);
5497
5498 fmovd(vtmp1 , zr);
5499 lsrw(rscratch1, len, 3);
5500
5501 cbnzw(rscratch1, big);
5502
5503 // Short string: less than 8 bytes.
5504 {
5505 Label loop, around, tiny;
5506
5507 subsw(len, len, 4);
5508 andw(len, len, 3);
5509 br(LO, tiny);
5510
5511 // Use SIMD to do 4 bytes.
5512 ldrs(vtmp2, post(src, 4));
5513 zip1(vtmp3, T8B, vtmp2, vtmp1);
5514 strd(vtmp3, post(dst, 8));
5515
5516 cbzw(len, done);
5517
5518 // Do the remaining bytes by steam.
5519 bind(loop);
5520 ldrb(tmp4, post(src, 1));
5521 strh(tmp4, post(dst, 2));
5522 subw(len, len, 1);
5523
5524 bind(tiny);
5525 cbnz(len, loop);
5526
5527 bind(around);
5528 b(done);
5529 }
5530
5531 // Unpack the bytes 8 at a time.
5532 bind(big);
5533 andw(len, len, 7);
5534
5535 {
5536 Label loop, around;
5537
5538 bind(loop);
5539 ldrd(vtmp2, post(src, 8));
5540 sub(rscratch1, rscratch1, 1);
5541 zip1(vtmp3, T16B, vtmp2, vtmp1);
5542 st1(vtmp3, T8H, post(dst, 16));
5543 cbnz(rscratch1, loop);
5544
5545 bind(around);
5546 }
5547
5548 // Do the tail of up to 8 bytes.
5549 sub(src, src, 8);
5550 add(src, src, len, ext::uxtw, 0);
5551 ldrd(vtmp2, Address(src));
5552 sub(dst, dst, 16);
5553 add(dst, dst, len, ext::uxtw, 1);
5554 zip1(vtmp3, T16B, vtmp2, vtmp1);
5555 st1(vtmp3, T8H, Address(dst));
5556
5557 bind(done);
5558 }
5559
5560 // Compress char[] array to byte[].
5561 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
5562 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
5563 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
5564 Register result) {
5565 encode_iso_array(src, dst, len, result,
5566 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg);
5567 cmp(len, zr);
5568 csel(result, result, zr, EQ);
5569 }
5570
5571 // get_thread() can be called anywhere inside generated code so we
5572 // need to save whatever non-callee save context might get clobbered
5573 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
5574 // the call setup code.
5575 //
5576 // aarch64_get_thread_helper() clobbers only r0, r1, and flags.
5577 //
5578 void MacroAssembler::get_thread(Register dst) {
5579 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
5580 push(saved_regs, sp);
5581
5582 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5583 blrt(lr, 1, 0, 1);
5584 if (dst != c_rarg0) {
5585 mov(dst, c_rarg0);
5586 }
5587
5588 pop(saved_regs, sp);
5589 }