1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "jvm.h"
30 #include "asm/assembler.hpp"
31 #include "asm/assembler.inline.hpp"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/cardTable.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "nativeInst_aarch64.hpp"
40 #include "oops/accessDecorators.hpp"
41 #include "oops/compressedOops.inline.hpp"
42 #include "oops/klass.inline.hpp"
43 #include "oops/oop.hpp"
44 #include "opto/compile.hpp"
45 #include "opto/intrinsicnode.hpp"
46 #include "opto/node.hpp"
47 #include "runtime/biasedLocking.hpp"
48 #include "runtime/icache.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/jniHandles.inline.hpp"
51 #include "runtime/sharedRuntime.hpp"
52 #include "runtime/thread.hpp"
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 // Patch any kind of instruction; there may be several instructions.
65 // Return the total length (in bytes) of the instructions.
66 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
67 int instructions = 1;
68 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
69 long offset = (target - branch) >> 2;
70 unsigned insn = *(unsigned*)branch;
71 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
72 // Load register (literal)
73 Instruction_aarch64::spatch(branch, 23, 5, offset);
74 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
75 // Unconditional branch (immediate)
76 Instruction_aarch64::spatch(branch, 25, 0, offset);
77 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
78 // Conditional branch (immediate)
79 Instruction_aarch64::spatch(branch, 23, 5, offset);
80 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
81 // Compare & branch (immediate)
82 Instruction_aarch64::spatch(branch, 23, 5, offset);
83 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
84 // Test & branch (immediate)
85 Instruction_aarch64::spatch(branch, 18, 5, offset);
86 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
87 // PC-rel. addressing
88 offset = target-branch;
89 int shift = Instruction_aarch64::extract(insn, 31, 31);
90 if (shift) {
91 u_int64_t dest = (u_int64_t)target;
92 uint64_t pc_page = (uint64_t)branch >> 12;
93 uint64_t adr_page = (uint64_t)target >> 12;
94 unsigned offset_lo = dest & 0xfff;
95 offset = adr_page - pc_page;
96
97 // We handle 4 types of PC relative addressing
98 // 1 - adrp Rx, target_page
99 // ldr/str Ry, [Rx, #offset_in_page]
100 // 2 - adrp Rx, target_page
101 // add Ry, Rx, #offset_in_page
102 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
103 // movk Rx, #imm16<<32
104 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
105 // In the first 3 cases we must check that Rx is the same in the adrp and the
106 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end
107 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened
108 // to be followed by a random unrelated ldr/str, add or movk instruction.
109 //
110 unsigned insn2 = ((unsigned*)branch)[1];
111 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
112 Instruction_aarch64::extract(insn, 4, 0) ==
113 Instruction_aarch64::extract(insn2, 9, 5)) {
114 // Load/store register (unsigned immediate)
115 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
116 Instruction_aarch64::patch(branch + sizeof (unsigned),
117 21, 10, offset_lo >> size);
118 guarantee(((dest >> size) << size) == dest, "misaligned target");
119 instructions = 2;
120 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
121 Instruction_aarch64::extract(insn, 4, 0) ==
122 Instruction_aarch64::extract(insn2, 4, 0)) {
123 // add (immediate)
124 Instruction_aarch64::patch(branch + sizeof (unsigned),
125 21, 10, offset_lo);
126 instructions = 2;
127 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
128 Instruction_aarch64::extract(insn, 4, 0) ==
129 Instruction_aarch64::extract(insn2, 4, 0)) {
130 // movk #imm16<<32
131 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
132 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
133 long pc_page = (long)branch >> 12;
134 long adr_page = (long)dest >> 12;
135 offset = adr_page - pc_page;
136 instructions = 2;
137 }
138 }
139 int offset_lo = offset & 3;
140 offset >>= 2;
141 Instruction_aarch64::spatch(branch, 23, 5, offset);
142 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
143 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
144 u_int64_t dest = (u_int64_t)target;
145 // Move wide constant
146 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
147 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
148 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
149 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
150 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
151 assert(target_addr_for_insn(branch) == target, "should be");
152 instructions = 3;
153 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
154 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
155 // nothing to do
156 assert(target == 0, "did not expect to relocate target for polling page load");
157 } else {
158 ShouldNotReachHere();
159 }
160 return instructions * NativeInstruction::instruction_size;
161 }
162
163 int MacroAssembler::patch_oop(address insn_addr, address o) {
164 int instructions;
165 unsigned insn = *(unsigned*)insn_addr;
166 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
167
168 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
169 // narrow OOPs by setting the upper 16 bits in the first
170 // instruction.
171 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
172 // Move narrow OOP
173 narrowOop n = CompressedOops::encode((oop)o);
174 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
175 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
176 instructions = 2;
177 } else {
178 // Move wide OOP
179 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
180 uintptr_t dest = (uintptr_t)o;
181 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
182 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
183 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
184 instructions = 3;
185 }
186 return instructions * NativeInstruction::instruction_size;
187 }
188
189 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
190 // Metatdata pointers are either narrow (32 bits) or wide (48 bits).
191 // We encode narrow ones by setting the upper 16 bits in the first
192 // instruction.
193 NativeInstruction *insn = nativeInstruction_at(insn_addr);
194 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
195 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
196
197 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
198 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
199 return 2 * NativeInstruction::instruction_size;
200 }
201
202 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
203 long offset = 0;
204 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
205 // Load register (literal)
206 offset = Instruction_aarch64::sextract(insn, 23, 5);
207 return address(((uint64_t)insn_addr + (offset << 2)));
208 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
209 // Unconditional branch (immediate)
210 offset = Instruction_aarch64::sextract(insn, 25, 0);
211 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
212 // Conditional branch (immediate)
213 offset = Instruction_aarch64::sextract(insn, 23, 5);
214 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
215 // Compare & branch (immediate)
216 offset = Instruction_aarch64::sextract(insn, 23, 5);
217 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
218 // Test & branch (immediate)
219 offset = Instruction_aarch64::sextract(insn, 18, 5);
220 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
221 // PC-rel. addressing
222 offset = Instruction_aarch64::extract(insn, 30, 29);
223 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
224 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
225 if (shift) {
226 offset <<= shift;
227 uint64_t target_page = ((uint64_t)insn_addr) + offset;
228 target_page &= ((uint64_t)-1) << shift;
229 // Return the target address for the following sequences
230 // 1 - adrp Rx, target_page
231 // ldr/str Ry, [Rx, #offset_in_page]
232 // 2 - adrp Rx, target_page
233 // add Ry, Rx, #offset_in_page
234 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
235 // movk Rx, #imm12<<32
236 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
237 //
238 // In the first two cases we check that the register is the same and
239 // return the target_page + the offset within the page.
240 // Otherwise we assume it is a page aligned relocation and return
241 // the target page only.
242 //
243 unsigned insn2 = ((unsigned*)insn_addr)[1];
244 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
245 Instruction_aarch64::extract(insn, 4, 0) ==
246 Instruction_aarch64::extract(insn2, 9, 5)) {
247 // Load/store register (unsigned immediate)
248 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
249 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
250 return address(target_page + (byte_offset << size));
251 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
252 Instruction_aarch64::extract(insn, 4, 0) ==
253 Instruction_aarch64::extract(insn2, 4, 0)) {
254 // add (immediate)
255 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
256 return address(target_page + byte_offset);
257 } else {
258 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
259 Instruction_aarch64::extract(insn, 4, 0) ==
260 Instruction_aarch64::extract(insn2, 4, 0)) {
261 target_page = (target_page & 0xffffffff) |
262 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
263 }
264 return (address)target_page;
265 }
266 } else {
267 ShouldNotReachHere();
268 }
269 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
270 u_int32_t *insns = (u_int32_t *)insn_addr;
271 // Move wide constant: movz, movk, movk. See movptr().
272 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
273 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
274 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
275 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
276 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
277 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
278 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
279 return 0;
280 } else {
281 ShouldNotReachHere();
282 }
283 return address(((uint64_t)insn_addr + (offset << 2)));
284 }
285
286 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
287 dsb(Assembler::SY);
288 }
289
290 void MacroAssembler::safepoint_poll(Label& slow_path) {
291 if (SafepointMechanism::uses_thread_local_poll()) {
292 ldr(rscratch1, Address(rthread, Thread::polling_page_offset()));
293 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
294 } else {
295 unsigned long offset;
296 adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset);
297 ldrw(rscratch1, Address(rscratch1, offset));
298 assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code");
299 cbnz(rscratch1, slow_path);
300 }
301 }
302
303 // Just like safepoint_poll, but use an acquiring load for thread-
304 // local polling.
305 //
306 // We need an acquire here to ensure that any subsequent load of the
307 // global SafepointSynchronize::_state flag is ordered after this load
308 // of the local Thread::_polling page. We don't want this poll to
309 // return false (i.e. not safepointing) and a later poll of the global
310 // SafepointSynchronize::_state spuriously to return true.
311 //
312 // This is to avoid a race when we're in a native->Java transition
313 // racing the code which wakes up from a safepoint.
314 //
315 void MacroAssembler::safepoint_poll_acquire(Label& slow_path) {
316 if (SafepointMechanism::uses_thread_local_poll()) {
317 lea(rscratch1, Address(rthread, Thread::polling_page_offset()));
318 ldar(rscratch1, rscratch1);
319 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
320 } else {
321 safepoint_poll(slow_path);
322 }
323 }
324
325 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
326 // we must set sp to zero to clear frame
327 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
328
329 // must clear fp, so that compiled frames are not confused; it is
330 // possible that we need it only for debugging
331 if (clear_fp) {
332 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
333 }
334
335 // Always clear the pc because it could have been set by make_walkable()
336 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
337 }
338
339 // Calls to C land
340 //
341 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
342 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
343 // has to be reset to 0. This is required to allow proper stack traversal.
344 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
345 Register last_java_fp,
346 Register last_java_pc,
347 Register scratch) {
348
349 if (last_java_pc->is_valid()) {
350 str(last_java_pc, Address(rthread,
351 JavaThread::frame_anchor_offset()
352 + JavaFrameAnchor::last_Java_pc_offset()));
353 }
354
355 // determine last_java_sp register
356 if (last_java_sp == sp) {
357 mov(scratch, sp);
358 last_java_sp = scratch;
359 } else if (!last_java_sp->is_valid()) {
360 last_java_sp = esp;
361 }
362
363 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
364
365 // last_java_fp is optional
366 if (last_java_fp->is_valid()) {
367 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
368 }
369 }
370
371 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
372 Register last_java_fp,
373 address last_java_pc,
374 Register scratch) {
375 if (last_java_pc != NULL) {
376 adr(scratch, last_java_pc);
377 } else {
378 // FIXME: This is almost never correct. We should delete all
379 // cases of set_last_Java_frame with last_java_pc=NULL and use the
380 // correct return address instead.
381 adr(scratch, pc());
382 }
383
384 str(scratch, Address(rthread,
385 JavaThread::frame_anchor_offset()
386 + JavaFrameAnchor::last_Java_pc_offset()));
387
388 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
389 }
390
391 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
392 Register last_java_fp,
393 Label &L,
394 Register scratch) {
395 if (L.is_bound()) {
396 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
397 } else {
398 InstructionMark im(this);
399 L.add_patch_at(code(), locator());
400 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
401 }
402 }
403
404 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
405 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
406 assert(CodeCache::find_blob(entry.target()) != NULL,
407 "destination of far call not found in code cache");
408 if (far_branches()) {
409 unsigned long offset;
410 // We can use ADRP here because we know that the total size of
411 // the code cache cannot exceed 2Gb.
412 adrp(tmp, entry, offset);
413 add(tmp, tmp, offset);
414 if (cbuf) cbuf->set_insts_mark();
415 blr(tmp);
416 } else {
417 if (cbuf) cbuf->set_insts_mark();
418 bl(entry);
419 }
420 }
421
422 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
423 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
424 assert(CodeCache::find_blob(entry.target()) != NULL,
425 "destination of far call not found in code cache");
426 if (far_branches()) {
427 unsigned long offset;
428 // We can use ADRP here because we know that the total size of
429 // the code cache cannot exceed 2Gb.
430 adrp(tmp, entry, offset);
431 add(tmp, tmp, offset);
432 if (cbuf) cbuf->set_insts_mark();
433 br(tmp);
434 } else {
435 if (cbuf) cbuf->set_insts_mark();
436 b(entry);
437 }
438 }
439
440 void MacroAssembler::reserved_stack_check() {
441 // testing if reserved zone needs to be enabled
442 Label no_reserved_zone_enabling;
443
444 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
445 cmp(sp, rscratch1);
446 br(Assembler::LO, no_reserved_zone_enabling);
447
448 enter(); // LR and FP are live.
449 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone));
450 mov(c_rarg0, rthread);
451 blr(rscratch1);
452 leave();
453
454 // We have already removed our own frame.
455 // throw_delayed_StackOverflowError will think that it's been
456 // called by our caller.
457 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
458 br(rscratch1);
459 should_not_reach_here();
460
461 bind(no_reserved_zone_enabling);
462 }
463
464 int MacroAssembler::biased_locking_enter(Register lock_reg,
465 Register obj_reg,
466 Register swap_reg,
467 Register tmp_reg,
468 bool swap_reg_contains_mark,
469 Label& done,
470 Label* slow_case,
471 BiasedLockingCounters* counters) {
472 assert(UseBiasedLocking, "why call this otherwise?");
473 assert_different_registers(lock_reg, obj_reg, swap_reg);
474
475 if (PrintBiasedLockingStatistics && counters == NULL)
476 counters = BiasedLocking::counters();
477
478 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
479 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
480 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
481 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
482 Address saved_mark_addr(lock_reg, 0);
483
484 // Biased locking
485 // See whether the lock is currently biased toward our thread and
486 // whether the epoch is still valid
487 // Note that the runtime guarantees sufficient alignment of JavaThread
488 // pointers to allow age to be placed into low bits
489 // First check to see whether biasing is even enabled for this object
490 Label cas_label;
491 int null_check_offset = -1;
492 if (!swap_reg_contains_mark) {
493 null_check_offset = offset();
494 ldr(swap_reg, mark_addr);
495 }
496 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
497 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
498 br(Assembler::NE, cas_label);
499 // The bias pattern is present in the object's header. Need to check
500 // whether the bias owner and the epoch are both still current.
501 load_prototype_header(tmp_reg, obj_reg);
502 orr(tmp_reg, tmp_reg, rthread);
503 eor(tmp_reg, swap_reg, tmp_reg);
504 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
505 if (counters != NULL) {
506 Label around;
507 cbnz(tmp_reg, around);
508 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
509 b(done);
510 bind(around);
511 } else {
512 cbz(tmp_reg, done);
513 }
514
515 Label try_revoke_bias;
516 Label try_rebias;
517
518 // At this point we know that the header has the bias pattern and
519 // that we are not the bias owner in the current epoch. We need to
520 // figure out more details about the state of the header in order to
521 // know what operations can be legally performed on the object's
522 // header.
523
524 // If the low three bits in the xor result aren't clear, that means
525 // the prototype header is no longer biased and we have to revoke
526 // the bias on this object.
527 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
528 cbnz(rscratch1, try_revoke_bias);
529
530 // Biasing is still enabled for this data type. See whether the
531 // epoch of the current bias is still valid, meaning that the epoch
532 // bits of the mark word are equal to the epoch bits of the
533 // prototype header. (Note that the prototype header's epoch bits
534 // only change at a safepoint.) If not, attempt to rebias the object
535 // toward the current thread. Note that we must be absolutely sure
536 // that the current epoch is invalid in order to do this because
537 // otherwise the manipulations it performs on the mark word are
538 // illegal.
539 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
540 cbnz(rscratch1, try_rebias);
541
542 // The epoch of the current bias is still valid but we know nothing
543 // about the owner; it might be set or it might be clear. Try to
544 // acquire the bias of the object using an atomic operation. If this
545 // fails we will go in to the runtime to revoke the object's bias.
546 // Note that we first construct the presumed unbiased header so we
547 // don't accidentally blow away another thread's valid bias.
548 {
549 Label here;
550 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
551 andr(swap_reg, swap_reg, rscratch1);
552 orr(tmp_reg, swap_reg, rthread);
553 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
554 // If the biasing toward our thread failed, this means that
555 // another thread succeeded in biasing it toward itself and we
556 // need to revoke that bias. The revocation will occur in the
557 // interpreter runtime in the slow case.
558 bind(here);
559 if (counters != NULL) {
560 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
561 tmp_reg, rscratch1, rscratch2);
562 }
563 }
564 b(done);
565
566 bind(try_rebias);
567 // At this point we know the epoch has expired, meaning that the
568 // current "bias owner", if any, is actually invalid. Under these
569 // circumstances _only_, we are allowed to use the current header's
570 // value as the comparison value when doing the cas to acquire the
571 // bias in the current epoch. In other words, we allow transfer of
572 // the bias from one thread to another directly in this situation.
573 //
574 // FIXME: due to a lack of registers we currently blow away the age
575 // bits in this situation. Should attempt to preserve them.
576 {
577 Label here;
578 load_prototype_header(tmp_reg, obj_reg);
579 orr(tmp_reg, rthread, tmp_reg);
580 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
581 // If the biasing toward our thread failed, then another thread
582 // succeeded in biasing it toward itself and we need to revoke that
583 // bias. The revocation will occur in the runtime in the slow case.
584 bind(here);
585 if (counters != NULL) {
586 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
587 tmp_reg, rscratch1, rscratch2);
588 }
589 }
590 b(done);
591
592 bind(try_revoke_bias);
593 // The prototype mark in the klass doesn't have the bias bit set any
594 // more, indicating that objects of this data type are not supposed
595 // to be biased any more. We are going to try to reset the mark of
596 // this object to the prototype value and fall through to the
597 // CAS-based locking scheme. Note that if our CAS fails, it means
598 // that another thread raced us for the privilege of revoking the
599 // bias of this particular object, so it's okay to continue in the
600 // normal locking code.
601 //
602 // FIXME: due to a lack of registers we currently blow away the age
603 // bits in this situation. Should attempt to preserve them.
604 {
605 Label here, nope;
606 load_prototype_header(tmp_reg, obj_reg);
607 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
608 bind(here);
609
610 // Fall through to the normal CAS-based lock, because no matter what
611 // the result of the above CAS, some thread must have succeeded in
612 // removing the bias bit from the object's header.
613 if (counters != NULL) {
614 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
615 rscratch1, rscratch2);
616 }
617 bind(nope);
618 }
619
620 bind(cas_label);
621
622 return null_check_offset;
623 }
624
625 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
626 assert(UseBiasedLocking, "why call this otherwise?");
627
628 // Check for biased locking unlock case, which is a no-op
629 // Note: we do not have to check the thread ID for two reasons.
630 // First, the interpreter checks for IllegalMonitorStateException at
631 // a higher level. Second, if the bias was revoked while we held the
632 // lock, the object could not be rebiased toward another thread, so
633 // the bias bit would be clear.
634 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
635 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
636 cmp(temp_reg, markOopDesc::biased_lock_pattern);
637 br(Assembler::EQ, done);
638 }
639
640 static void pass_arg0(MacroAssembler* masm, Register arg) {
641 if (c_rarg0 != arg ) {
642 masm->mov(c_rarg0, arg);
643 }
644 }
645
646 static void pass_arg1(MacroAssembler* masm, Register arg) {
647 if (c_rarg1 != arg ) {
648 masm->mov(c_rarg1, arg);
649 }
650 }
651
652 static void pass_arg2(MacroAssembler* masm, Register arg) {
653 if (c_rarg2 != arg ) {
654 masm->mov(c_rarg2, arg);
655 }
656 }
657
658 static void pass_arg3(MacroAssembler* masm, Register arg) {
659 if (c_rarg3 != arg ) {
660 masm->mov(c_rarg3, arg);
661 }
662 }
663
664 void MacroAssembler::call_VM_base(Register oop_result,
665 Register java_thread,
666 Register last_java_sp,
667 address entry_point,
668 int number_of_arguments,
669 bool check_exceptions) {
670 // determine java_thread register
671 if (!java_thread->is_valid()) {
672 java_thread = rthread;
673 }
674
675 // determine last_java_sp register
676 if (!last_java_sp->is_valid()) {
677 last_java_sp = esp;
678 }
679
680 // debugging support
681 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
682 assert(java_thread == rthread, "unexpected register");
683 #ifdef ASSERT
684 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
685 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
686 #endif // ASSERT
687
688 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
689 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
690
691 // push java thread (becomes first argument of C function)
692
693 mov(c_rarg0, java_thread);
694
695 // set last Java frame before call
696 assert(last_java_sp != rfp, "can't use rfp");
697
698 Label l;
699 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
700
701 // do the call, remove parameters
702 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
703
704 // reset last Java frame
705 // Only interpreter should have to clear fp
706 reset_last_Java_frame(true);
707
708 // C++ interp handles this in the interpreter
709 check_and_handle_popframe(java_thread);
710 check_and_handle_earlyret(java_thread);
711
712 if (check_exceptions) {
713 // check for pending exceptions (java_thread is set upon return)
714 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
715 Label ok;
716 cbz(rscratch1, ok);
717 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
718 br(rscratch1);
719 bind(ok);
720 }
721
722 // get oop result if there is one and reset the value in the thread
723 if (oop_result->is_valid()) {
724 get_vm_result(oop_result, java_thread);
725 }
726 }
727
728 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
729 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
730 }
731
732 // Maybe emit a call via a trampoline. If the code cache is small
733 // trampolines won't be emitted.
734
735 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
736 assert(JavaThread::current()->is_Compiler_thread(), "just checking");
737 assert(entry.rspec().type() == relocInfo::runtime_call_type
738 || entry.rspec().type() == relocInfo::opt_virtual_call_type
739 || entry.rspec().type() == relocInfo::static_call_type
740 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
741
742 unsigned int start_offset = offset();
743 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
744 address stub = emit_trampoline_stub(start_offset, entry.target());
745 if (stub == NULL) {
746 return NULL; // CodeCache is full
747 }
748 }
749
750 if (cbuf) cbuf->set_insts_mark();
751 relocate(entry.rspec());
752 if (!far_branches()) {
753 bl(entry.target());
754 } else {
755 bl(pc());
756 }
757 // just need to return a non-null address
758 return pc();
759 }
760
761
762 // Emit a trampoline stub for a call to a target which is too far away.
763 //
764 // code sequences:
765 //
766 // call-site:
767 // branch-and-link to <destination> or <trampoline stub>
768 //
769 // Related trampoline stub for this call site in the stub section:
770 // load the call target from the constant pool
771 // branch (LR still points to the call site above)
772
773 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
774 address dest) {
775 address stub = start_a_stub(Compile::MAX_stubs_size/2);
776 if (stub == NULL) {
777 return NULL; // CodeBuffer::expand failed
778 }
779
780 // Create a trampoline stub relocation which relates this trampoline stub
781 // with the call instruction at insts_call_instruction_offset in the
782 // instructions code-section.
783 align(wordSize);
784 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
785 + insts_call_instruction_offset));
786 const int stub_start_offset = offset();
787
788 // Now, create the trampoline stub's code:
789 // - load the call
790 // - call
791 Label target;
792 ldr(rscratch1, target);
793 br(rscratch1);
794 bind(target);
795 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
796 "should be");
797 emit_int64((int64_t)dest);
798
799 const address stub_start_addr = addr_at(stub_start_offset);
800
801 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
802
803 end_a_stub();
804 return stub_start_addr;
805 }
806
807 address MacroAssembler::ic_call(address entry, jint method_index) {
808 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
809 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
810 // unsigned long offset;
811 // ldr_constant(rscratch2, const_ptr);
812 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
813 return trampoline_call(Address(entry, rh));
814 }
815
816 // Implementation of call_VM versions
817
818 void MacroAssembler::call_VM(Register oop_result,
819 address entry_point,
820 bool check_exceptions) {
821 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
822 }
823
824 void MacroAssembler::call_VM(Register oop_result,
825 address entry_point,
826 Register arg_1,
827 bool check_exceptions) {
828 pass_arg1(this, arg_1);
829 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
830 }
831
832 void MacroAssembler::call_VM(Register oop_result,
833 address entry_point,
834 Register arg_1,
835 Register arg_2,
836 bool check_exceptions) {
837 assert(arg_1 != c_rarg2, "smashed arg");
838 pass_arg2(this, arg_2);
839 pass_arg1(this, arg_1);
840 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
841 }
842
843 void MacroAssembler::call_VM(Register oop_result,
844 address entry_point,
845 Register arg_1,
846 Register arg_2,
847 Register arg_3,
848 bool check_exceptions) {
849 assert(arg_1 != c_rarg3, "smashed arg");
850 assert(arg_2 != c_rarg3, "smashed arg");
851 pass_arg3(this, arg_3);
852
853 assert(arg_1 != c_rarg2, "smashed arg");
854 pass_arg2(this, arg_2);
855
856 pass_arg1(this, arg_1);
857 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
858 }
859
860 void MacroAssembler::call_VM(Register oop_result,
861 Register last_java_sp,
862 address entry_point,
863 int number_of_arguments,
864 bool check_exceptions) {
865 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
866 }
867
868 void MacroAssembler::call_VM(Register oop_result,
869 Register last_java_sp,
870 address entry_point,
871 Register arg_1,
872 bool check_exceptions) {
873 pass_arg1(this, arg_1);
874 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
875 }
876
877 void MacroAssembler::call_VM(Register oop_result,
878 Register last_java_sp,
879 address entry_point,
880 Register arg_1,
881 Register arg_2,
882 bool check_exceptions) {
883
884 assert(arg_1 != c_rarg2, "smashed arg");
885 pass_arg2(this, arg_2);
886 pass_arg1(this, arg_1);
887 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
888 }
889
890 void MacroAssembler::call_VM(Register oop_result,
891 Register last_java_sp,
892 address entry_point,
893 Register arg_1,
894 Register arg_2,
895 Register arg_3,
896 bool check_exceptions) {
897 assert(arg_1 != c_rarg3, "smashed arg");
898 assert(arg_2 != c_rarg3, "smashed arg");
899 pass_arg3(this, arg_3);
900 assert(arg_1 != c_rarg2, "smashed arg");
901 pass_arg2(this, arg_2);
902 pass_arg1(this, arg_1);
903 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
904 }
905
906
907 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
908 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
909 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
910 verify_oop(oop_result, "broken oop in call_VM_base");
911 }
912
913 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
914 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
915 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
916 }
917
918 void MacroAssembler::align(int modulus) {
919 while (offset() % modulus != 0) nop();
920 }
921
922 // these are no-ops overridden by InterpreterMacroAssembler
923
924 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
925
926 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
927
928
929 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
930 Register tmp,
931 int offset) {
932 intptr_t value = *delayed_value_addr;
933 if (value != 0)
934 return RegisterOrConstant(value + offset);
935
936 // load indirectly to solve generation ordering problem
937 ldr(tmp, ExternalAddress((address) delayed_value_addr));
938
939 if (offset != 0)
940 add(tmp, tmp, offset);
941
942 return RegisterOrConstant(tmp);
943 }
944
945
946 void MacroAssembler:: notify(int type) {
947 if (type == bytecode_start) {
948 // set_last_Java_frame(esp, rfp, (address)NULL);
949 Assembler:: notify(type);
950 // reset_last_Java_frame(true);
951 }
952 else
953 Assembler:: notify(type);
954 }
955
956 // Look up the method for a megamorphic invokeinterface call.
957 // The target method is determined by <intf_klass, itable_index>.
958 // The receiver klass is in recv_klass.
959 // On success, the result will be in method_result, and execution falls through.
960 // On failure, execution transfers to the given label.
961 void MacroAssembler::lookup_interface_method(Register recv_klass,
962 Register intf_klass,
963 RegisterOrConstant itable_index,
964 Register method_result,
965 Register scan_temp,
966 Label& L_no_such_interface,
967 bool return_method) {
968 assert_different_registers(recv_klass, intf_klass, scan_temp);
969 assert_different_registers(method_result, intf_klass, scan_temp);
970 assert(recv_klass != method_result || !return_method,
971 "recv_klass can be destroyed when method isn't needed");
972 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
973 "caller must use same register for non-constant itable index as for method");
974
975 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
976 int vtable_base = in_bytes(Klass::vtable_start_offset());
977 int itentry_off = itableMethodEntry::method_offset_in_bytes();
978 int scan_step = itableOffsetEntry::size() * wordSize;
979 int vte_size = vtableEntry::size_in_bytes();
980 assert(vte_size == wordSize, "else adjust times_vte_scale");
981
982 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
983
984 // %%% Could store the aligned, prescaled offset in the klassoop.
985 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
986 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
987 add(scan_temp, scan_temp, vtable_base);
988
989 if (return_method) {
990 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
991 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
992 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
993 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
994 if (itentry_off)
995 add(recv_klass, recv_klass, itentry_off);
996 }
997
998 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
999 // if (scan->interface() == intf) {
1000 // result = (klass + scan->offset() + itable_index);
1001 // }
1002 // }
1003 Label search, found_method;
1004
1005 for (int peel = 1; peel >= 0; peel--) {
1006 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
1007 cmp(intf_klass, method_result);
1008
1009 if (peel) {
1010 br(Assembler::EQ, found_method);
1011 } else {
1012 br(Assembler::NE, search);
1013 // (invert the test to fall through to found_method...)
1014 }
1015
1016 if (!peel) break;
1017
1018 bind(search);
1019
1020 // Check that the previous entry is non-null. A null entry means that
1021 // the receiver class doesn't implement the interface, and wasn't the
1022 // same as when the caller was compiled.
1023 cbz(method_result, L_no_such_interface);
1024 add(scan_temp, scan_temp, scan_step);
1025 }
1026
1027 bind(found_method);
1028
1029 // Got a hit.
1030 if (return_method) {
1031 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
1032 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1033 }
1034 }
1035
1036 // virtual method calling
1037 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1038 RegisterOrConstant vtable_index,
1039 Register method_result) {
1040 const int base = in_bytes(Klass::vtable_start_offset());
1041 assert(vtableEntry::size() * wordSize == 8,
1042 "adjust the scaling in the code below");
1043 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
1044
1045 if (vtable_index.is_register()) {
1046 lea(method_result, Address(recv_klass,
1047 vtable_index.as_register(),
1048 Address::lsl(LogBytesPerWord)));
1049 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1050 } else {
1051 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1052 ldr(method_result,
1053 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1054 }
1055 }
1056
1057 void MacroAssembler::check_klass_subtype(Register sub_klass,
1058 Register super_klass,
1059 Register temp_reg,
1060 Label& L_success) {
1061 Label L_failure;
1062 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
1063 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
1064 bind(L_failure);
1065 }
1066
1067
1068 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1069 Register super_klass,
1070 Register temp_reg,
1071 Label* L_success,
1072 Label* L_failure,
1073 Label* L_slow_path,
1074 RegisterOrConstant super_check_offset) {
1075 assert_different_registers(sub_klass, super_klass, temp_reg);
1076 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1077 if (super_check_offset.is_register()) {
1078 assert_different_registers(sub_klass, super_klass,
1079 super_check_offset.as_register());
1080 } else if (must_load_sco) {
1081 assert(temp_reg != noreg, "supply either a temp or a register offset");
1082 }
1083
1084 Label L_fallthrough;
1085 int label_nulls = 0;
1086 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1087 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1088 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1089 assert(label_nulls <= 1, "at most one NULL in the batch");
1090
1091 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1092 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1093 Address super_check_offset_addr(super_klass, sco_offset);
1094
1095 // Hacked jmp, which may only be used just before L_fallthrough.
1096 #define final_jmp(label) \
1097 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1098 else b(label) /*omit semi*/
1099
1100 // If the pointers are equal, we are done (e.g., String[] elements).
1101 // This self-check enables sharing of secondary supertype arrays among
1102 // non-primary types such as array-of-interface. Otherwise, each such
1103 // type would need its own customized SSA.
1104 // We move this check to the front of the fast path because many
1105 // type checks are in fact trivially successful in this manner,
1106 // so we get a nicely predicted branch right at the start of the check.
1107 cmp(sub_klass, super_klass);
1108 br(Assembler::EQ, *L_success);
1109
1110 // Check the supertype display:
1111 if (must_load_sco) {
1112 ldrw(temp_reg, super_check_offset_addr);
1113 super_check_offset = RegisterOrConstant(temp_reg);
1114 }
1115 Address super_check_addr(sub_klass, super_check_offset);
1116 ldr(rscratch1, super_check_addr);
1117 cmp(super_klass, rscratch1); // load displayed supertype
1118
1119 // This check has worked decisively for primary supers.
1120 // Secondary supers are sought in the super_cache ('super_cache_addr').
1121 // (Secondary supers are interfaces and very deeply nested subtypes.)
1122 // This works in the same check above because of a tricky aliasing
1123 // between the super_cache and the primary super display elements.
1124 // (The 'super_check_addr' can address either, as the case requires.)
1125 // Note that the cache is updated below if it does not help us find
1126 // what we need immediately.
1127 // So if it was a primary super, we can just fail immediately.
1128 // Otherwise, it's the slow path for us (no success at this point).
1129
1130 if (super_check_offset.is_register()) {
1131 br(Assembler::EQ, *L_success);
1132 cmp(super_check_offset.as_register(), sc_offset);
1133 if (L_failure == &L_fallthrough) {
1134 br(Assembler::EQ, *L_slow_path);
1135 } else {
1136 br(Assembler::NE, *L_failure);
1137 final_jmp(*L_slow_path);
1138 }
1139 } else if (super_check_offset.as_constant() == sc_offset) {
1140 // Need a slow path; fast failure is impossible.
1141 if (L_slow_path == &L_fallthrough) {
1142 br(Assembler::EQ, *L_success);
1143 } else {
1144 br(Assembler::NE, *L_slow_path);
1145 final_jmp(*L_success);
1146 }
1147 } else {
1148 // No slow path; it's a fast decision.
1149 if (L_failure == &L_fallthrough) {
1150 br(Assembler::EQ, *L_success);
1151 } else {
1152 br(Assembler::NE, *L_failure);
1153 final_jmp(*L_success);
1154 }
1155 }
1156
1157 bind(L_fallthrough);
1158
1159 #undef final_jmp
1160 }
1161
1162 // These two are taken from x86, but they look generally useful
1163
1164 // scans count pointer sized words at [addr] for occurence of value,
1165 // generic
1166 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1167 Register scratch) {
1168 Label Lloop, Lexit;
1169 cbz(count, Lexit);
1170 bind(Lloop);
1171 ldr(scratch, post(addr, wordSize));
1172 cmp(value, scratch);
1173 br(EQ, Lexit);
1174 sub(count, count, 1);
1175 cbnz(count, Lloop);
1176 bind(Lexit);
1177 }
1178
1179 // scans count 4 byte words at [addr] for occurence of value,
1180 // generic
1181 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1182 Register scratch) {
1183 Label Lloop, Lexit;
1184 cbz(count, Lexit);
1185 bind(Lloop);
1186 ldrw(scratch, post(addr, wordSize));
1187 cmpw(value, scratch);
1188 br(EQ, Lexit);
1189 sub(count, count, 1);
1190 cbnz(count, Lloop);
1191 bind(Lexit);
1192 }
1193
1194 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1195 Register super_klass,
1196 Register temp_reg,
1197 Register temp2_reg,
1198 Label* L_success,
1199 Label* L_failure,
1200 bool set_cond_codes) {
1201 assert_different_registers(sub_klass, super_klass, temp_reg);
1202 if (temp2_reg != noreg)
1203 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1204 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1205
1206 Label L_fallthrough;
1207 int label_nulls = 0;
1208 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1209 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1210 assert(label_nulls <= 1, "at most one NULL in the batch");
1211
1212 // a couple of useful fields in sub_klass:
1213 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1214 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1215 Address secondary_supers_addr(sub_klass, ss_offset);
1216 Address super_cache_addr( sub_klass, sc_offset);
1217
1218 BLOCK_COMMENT("check_klass_subtype_slow_path");
1219
1220 // Do a linear scan of the secondary super-klass chain.
1221 // This code is rarely used, so simplicity is a virtue here.
1222 // The repne_scan instruction uses fixed registers, which we must spill.
1223 // Don't worry too much about pre-existing connections with the input regs.
1224
1225 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1226 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1227
1228 RegSet pushed_registers;
1229 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1230 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1231
1232 if (super_klass != r0 || UseCompressedOops) {
1233 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1234 }
1235
1236 push(pushed_registers, sp);
1237
1238 // Get super_klass value into r0 (even if it was in r5 or r2).
1239 if (super_klass != r0) {
1240 mov(r0, super_klass);
1241 }
1242
1243 #ifndef PRODUCT
1244 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1245 Address pst_counter_addr(rscratch2);
1246 ldr(rscratch1, pst_counter_addr);
1247 add(rscratch1, rscratch1, 1);
1248 str(rscratch1, pst_counter_addr);
1249 #endif //PRODUCT
1250
1251 // We will consult the secondary-super array.
1252 ldr(r5, secondary_supers_addr);
1253 // Load the array length.
1254 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1255 // Skip to start of data.
1256 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1257
1258 cmp(sp, zr); // Clear Z flag; SP is never zero
1259 // Scan R2 words at [R5] for an occurrence of R0.
1260 // Set NZ/Z based on last compare.
1261 repne_scan(r5, r0, r2, rscratch1);
1262
1263 // Unspill the temp. registers:
1264 pop(pushed_registers, sp);
1265
1266 br(Assembler::NE, *L_failure);
1267
1268 // Success. Cache the super we found and proceed in triumph.
1269 str(super_klass, super_cache_addr);
1270
1271 if (L_success != &L_fallthrough) {
1272 b(*L_success);
1273 }
1274
1275 #undef IS_A_TEMP
1276
1277 bind(L_fallthrough);
1278 }
1279
1280
1281 void MacroAssembler::verify_oop(Register reg, const char* s) {
1282 if (!VerifyOops) return;
1283
1284 // Pass register number to verify_oop_subroutine
1285 const char* b = NULL;
1286 {
1287 ResourceMark rm;
1288 stringStream ss;
1289 ss.print("verify_oop: %s: %s", reg->name(), s);
1290 b = code_string(ss.as_string());
1291 }
1292 BLOCK_COMMENT("verify_oop {");
1293
1294 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1295 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1296
1297 mov(r0, reg);
1298 mov(rscratch1, (address)b);
1299
1300 // call indirectly to solve generation ordering problem
1301 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1302 ldr(rscratch2, Address(rscratch2));
1303 blr(rscratch2);
1304
1305 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1306 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1307
1308 BLOCK_COMMENT("} verify_oop");
1309 }
1310
1311 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1312 if (!VerifyOops) return;
1313
1314 const char* b = NULL;
1315 {
1316 ResourceMark rm;
1317 stringStream ss;
1318 ss.print("verify_oop_addr: %s", s);
1319 b = code_string(ss.as_string());
1320 }
1321 BLOCK_COMMENT("verify_oop_addr {");
1322
1323 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1324 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1325
1326 // addr may contain sp so we will have to adjust it based on the
1327 // pushes that we just did.
1328 if (addr.uses(sp)) {
1329 lea(r0, addr);
1330 ldr(r0, Address(r0, 4 * wordSize));
1331 } else {
1332 ldr(r0, addr);
1333 }
1334 mov(rscratch1, (address)b);
1335
1336 // call indirectly to solve generation ordering problem
1337 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1338 ldr(rscratch2, Address(rscratch2));
1339 blr(rscratch2);
1340
1341 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1342 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1343
1344 BLOCK_COMMENT("} verify_oop_addr");
1345 }
1346
1347 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1348 int extra_slot_offset) {
1349 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1350 int stackElementSize = Interpreter::stackElementSize;
1351 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1352 #ifdef ASSERT
1353 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1354 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1355 #endif
1356 if (arg_slot.is_constant()) {
1357 return Address(esp, arg_slot.as_constant() * stackElementSize
1358 + offset);
1359 } else {
1360 add(rscratch1, esp, arg_slot.as_register(),
1361 ext::uxtx, exact_log2(stackElementSize));
1362 return Address(rscratch1, offset);
1363 }
1364 }
1365
1366 void MacroAssembler::call_VM_leaf_base(address entry_point,
1367 int number_of_arguments,
1368 Label *retaddr) {
1369 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1370 }
1371
1372 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1373 int number_of_gp_arguments,
1374 int number_of_fp_arguments,
1375 ret_type type,
1376 Label *retaddr) {
1377 Label E, L;
1378
1379 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1380
1381 // We add 1 to number_of_arguments because the thread in arg0 is
1382 // not counted
1383 mov(rscratch1, entry_point);
1384 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1385 if (retaddr)
1386 bind(*retaddr);
1387
1388 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1389 maybe_isb();
1390 }
1391
1392 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1393 call_VM_leaf_base(entry_point, number_of_arguments);
1394 }
1395
1396 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1397 pass_arg0(this, arg_0);
1398 call_VM_leaf_base(entry_point, 1);
1399 }
1400
1401 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1402 pass_arg0(this, arg_0);
1403 pass_arg1(this, arg_1);
1404 call_VM_leaf_base(entry_point, 2);
1405 }
1406
1407 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1408 Register arg_1, Register arg_2) {
1409 pass_arg0(this, arg_0);
1410 pass_arg1(this, arg_1);
1411 pass_arg2(this, arg_2);
1412 call_VM_leaf_base(entry_point, 3);
1413 }
1414
1415 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1416 pass_arg0(this, arg_0);
1417 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1418 }
1419
1420 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1421
1422 assert(arg_0 != c_rarg1, "smashed arg");
1423 pass_arg1(this, arg_1);
1424 pass_arg0(this, arg_0);
1425 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1426 }
1427
1428 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1429 assert(arg_0 != c_rarg2, "smashed arg");
1430 assert(arg_1 != c_rarg2, "smashed arg");
1431 pass_arg2(this, arg_2);
1432 assert(arg_0 != c_rarg1, "smashed arg");
1433 pass_arg1(this, arg_1);
1434 pass_arg0(this, arg_0);
1435 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1436 }
1437
1438 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1439 assert(arg_0 != c_rarg3, "smashed arg");
1440 assert(arg_1 != c_rarg3, "smashed arg");
1441 assert(arg_2 != c_rarg3, "smashed arg");
1442 pass_arg3(this, arg_3);
1443 assert(arg_0 != c_rarg2, "smashed arg");
1444 assert(arg_1 != c_rarg2, "smashed arg");
1445 pass_arg2(this, arg_2);
1446 assert(arg_0 != c_rarg1, "smashed arg");
1447 pass_arg1(this, arg_1);
1448 pass_arg0(this, arg_0);
1449 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1450 }
1451
1452 void MacroAssembler::null_check(Register reg, int offset) {
1453 if (needs_explicit_null_check(offset)) {
1454 // provoke OS NULL exception if reg = NULL by
1455 // accessing M[reg] w/o changing any registers
1456 // NOTE: this is plenty to provoke a segv
1457 ldr(zr, Address(reg));
1458 } else {
1459 // nothing to do, (later) access of M[reg + offset]
1460 // will provoke OS NULL exception if reg = NULL
1461 }
1462 }
1463
1464 // MacroAssembler protected routines needed to implement
1465 // public methods
1466
1467 void MacroAssembler::mov(Register r, Address dest) {
1468 code_section()->relocate(pc(), dest.rspec());
1469 u_int64_t imm64 = (u_int64_t)dest.target();
1470 movptr(r, imm64);
1471 }
1472
1473 // Move a constant pointer into r. In AArch64 mode the virtual
1474 // address space is 48 bits in size, so we only need three
1475 // instructions to create a patchable instruction sequence that can
1476 // reach anywhere.
1477 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1478 #ifndef PRODUCT
1479 {
1480 char buffer[64];
1481 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1482 block_comment(buffer);
1483 }
1484 #endif
1485 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1486 movz(r, imm64 & 0xffff);
1487 imm64 >>= 16;
1488 movk(r, imm64 & 0xffff, 16);
1489 imm64 >>= 16;
1490 movk(r, imm64 & 0xffff, 32);
1491 }
1492
1493 // Macro to mov replicated immediate to vector register.
1494 // Vd will get the following values for different arrangements in T
1495 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1496 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1497 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1498 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1499 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1500 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1501 // T1D/T2D: invalid
1502 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1503 assert(T != T1D && T != T2D, "invalid arrangement");
1504 if (T == T8B || T == T16B) {
1505 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1506 movi(Vd, T, imm32 & 0xff, 0);
1507 return;
1508 }
1509 u_int32_t nimm32 = ~imm32;
1510 if (T == T4H || T == T8H) {
1511 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1512 imm32 &= 0xffff;
1513 nimm32 &= 0xffff;
1514 }
1515 u_int32_t x = imm32;
1516 int movi_cnt = 0;
1517 int movn_cnt = 0;
1518 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1519 x = nimm32;
1520 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1521 if (movn_cnt < movi_cnt) imm32 = nimm32;
1522 unsigned lsl = 0;
1523 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1524 if (movn_cnt < movi_cnt)
1525 mvni(Vd, T, imm32 & 0xff, lsl);
1526 else
1527 movi(Vd, T, imm32 & 0xff, lsl);
1528 imm32 >>= 8; lsl += 8;
1529 while (imm32) {
1530 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1531 if (movn_cnt < movi_cnt)
1532 bici(Vd, T, imm32 & 0xff, lsl);
1533 else
1534 orri(Vd, T, imm32 & 0xff, lsl);
1535 lsl += 8; imm32 >>= 8;
1536 }
1537 }
1538
1539 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1540 {
1541 #ifndef PRODUCT
1542 {
1543 char buffer[64];
1544 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1545 block_comment(buffer);
1546 }
1547 #endif
1548 if (operand_valid_for_logical_immediate(false, imm64)) {
1549 orr(dst, zr, imm64);
1550 } else {
1551 // we can use a combination of MOVZ or MOVN with
1552 // MOVK to build up the constant
1553 u_int64_t imm_h[4];
1554 int zero_count = 0;
1555 int neg_count = 0;
1556 int i;
1557 for (i = 0; i < 4; i++) {
1558 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1559 if (imm_h[i] == 0) {
1560 zero_count++;
1561 } else if (imm_h[i] == 0xffffL) {
1562 neg_count++;
1563 }
1564 }
1565 if (zero_count == 4) {
1566 // one MOVZ will do
1567 movz(dst, 0);
1568 } else if (neg_count == 4) {
1569 // one MOVN will do
1570 movn(dst, 0);
1571 } else if (zero_count == 3) {
1572 for (i = 0; i < 4; i++) {
1573 if (imm_h[i] != 0L) {
1574 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1575 break;
1576 }
1577 }
1578 } else if (neg_count == 3) {
1579 // one MOVN will do
1580 for (int i = 0; i < 4; i++) {
1581 if (imm_h[i] != 0xffffL) {
1582 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1583 break;
1584 }
1585 }
1586 } else if (zero_count == 2) {
1587 // one MOVZ and one MOVK will do
1588 for (i = 0; i < 3; i++) {
1589 if (imm_h[i] != 0L) {
1590 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1591 i++;
1592 break;
1593 }
1594 }
1595 for (;i < 4; i++) {
1596 if (imm_h[i] != 0L) {
1597 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1598 }
1599 }
1600 } else if (neg_count == 2) {
1601 // one MOVN and one MOVK will do
1602 for (i = 0; i < 4; i++) {
1603 if (imm_h[i] != 0xffffL) {
1604 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1605 i++;
1606 break;
1607 }
1608 }
1609 for (;i < 4; i++) {
1610 if (imm_h[i] != 0xffffL) {
1611 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1612 }
1613 }
1614 } else if (zero_count == 1) {
1615 // one MOVZ and two MOVKs will do
1616 for (i = 0; i < 4; i++) {
1617 if (imm_h[i] != 0L) {
1618 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1619 i++;
1620 break;
1621 }
1622 }
1623 for (;i < 4; i++) {
1624 if (imm_h[i] != 0x0L) {
1625 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1626 }
1627 }
1628 } else if (neg_count == 1) {
1629 // one MOVN and two MOVKs will do
1630 for (i = 0; i < 4; i++) {
1631 if (imm_h[i] != 0xffffL) {
1632 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1633 i++;
1634 break;
1635 }
1636 }
1637 for (;i < 4; i++) {
1638 if (imm_h[i] != 0xffffL) {
1639 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1640 }
1641 }
1642 } else {
1643 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1644 movz(dst, (u_int32_t)imm_h[0], 0);
1645 for (i = 1; i < 4; i++) {
1646 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1647 }
1648 }
1649 }
1650 }
1651
1652 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1653 {
1654 #ifndef PRODUCT
1655 {
1656 char buffer[64];
1657 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1658 block_comment(buffer);
1659 }
1660 #endif
1661 if (operand_valid_for_logical_immediate(true, imm32)) {
1662 orrw(dst, zr, imm32);
1663 } else {
1664 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1665 // constant
1666 u_int32_t imm_h[2];
1667 imm_h[0] = imm32 & 0xffff;
1668 imm_h[1] = ((imm32 >> 16) & 0xffff);
1669 if (imm_h[0] == 0) {
1670 movzw(dst, imm_h[1], 16);
1671 } else if (imm_h[0] == 0xffff) {
1672 movnw(dst, imm_h[1] ^ 0xffff, 16);
1673 } else if (imm_h[1] == 0) {
1674 movzw(dst, imm_h[0], 0);
1675 } else if (imm_h[1] == 0xffff) {
1676 movnw(dst, imm_h[0] ^ 0xffff, 0);
1677 } else {
1678 // use a MOVZ and MOVK (makes it easier to debug)
1679 movzw(dst, imm_h[0], 0);
1680 movkw(dst, imm_h[1], 16);
1681 }
1682 }
1683 }
1684
1685 // Form an address from base + offset in Rd. Rd may or may
1686 // not actually be used: you must use the Address that is returned.
1687 // It is up to you to ensure that the shift provided matches the size
1688 // of your data.
1689 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1690 if (Address::offset_ok_for_immed(byte_offset, shift))
1691 // It fits; no need for any heroics
1692 return Address(base, byte_offset);
1693
1694 // Don't do anything clever with negative or misaligned offsets
1695 unsigned mask = (1 << shift) - 1;
1696 if (byte_offset < 0 || byte_offset & mask) {
1697 mov(Rd, byte_offset);
1698 add(Rd, base, Rd);
1699 return Address(Rd);
1700 }
1701
1702 // See if we can do this with two 12-bit offsets
1703 {
1704 unsigned long word_offset = byte_offset >> shift;
1705 unsigned long masked_offset = word_offset & 0xfff000;
1706 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1707 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1708 add(Rd, base, masked_offset << shift);
1709 word_offset -= masked_offset;
1710 return Address(Rd, word_offset << shift);
1711 }
1712 }
1713
1714 // Do it the hard way
1715 mov(Rd, byte_offset);
1716 add(Rd, base, Rd);
1717 return Address(Rd);
1718 }
1719
1720 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1721 if (UseLSE) {
1722 mov(tmp, 1);
1723 ldadd(Assembler::word, tmp, zr, counter_addr);
1724 return;
1725 }
1726 Label retry_load;
1727 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
1728 prfm(Address(counter_addr), PSTL1STRM);
1729 bind(retry_load);
1730 // flush and load exclusive from the memory location
1731 ldxrw(tmp, counter_addr);
1732 addw(tmp, tmp, 1);
1733 // if we store+flush with no intervening write tmp wil be zero
1734 stxrw(tmp2, tmp, counter_addr);
1735 cbnzw(tmp2, retry_load);
1736 }
1737
1738
1739 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1740 bool want_remainder, Register scratch)
1741 {
1742 // Full implementation of Java idiv and irem. The function
1743 // returns the (pc) offset of the div instruction - may be needed
1744 // for implicit exceptions.
1745 //
1746 // constraint : ra/rb =/= scratch
1747 // normal case
1748 //
1749 // input : ra: dividend
1750 // rb: divisor
1751 //
1752 // result: either
1753 // quotient (= ra idiv rb)
1754 // remainder (= ra irem rb)
1755
1756 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1757
1758 int idivl_offset = offset();
1759 if (! want_remainder) {
1760 sdivw(result, ra, rb);
1761 } else {
1762 sdivw(scratch, ra, rb);
1763 Assembler::msubw(result, scratch, rb, ra);
1764 }
1765
1766 return idivl_offset;
1767 }
1768
1769 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1770 bool want_remainder, Register scratch)
1771 {
1772 // Full implementation of Java ldiv and lrem. The function
1773 // returns the (pc) offset of the div instruction - may be needed
1774 // for implicit exceptions.
1775 //
1776 // constraint : ra/rb =/= scratch
1777 // normal case
1778 //
1779 // input : ra: dividend
1780 // rb: divisor
1781 //
1782 // result: either
1783 // quotient (= ra idiv rb)
1784 // remainder (= ra irem rb)
1785
1786 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1787
1788 int idivq_offset = offset();
1789 if (! want_remainder) {
1790 sdiv(result, ra, rb);
1791 } else {
1792 sdiv(scratch, ra, rb);
1793 Assembler::msub(result, scratch, rb, ra);
1794 }
1795
1796 return idivq_offset;
1797 }
1798
1799 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1800 address prev = pc() - NativeMembar::instruction_size;
1801 address last = code()->last_insn();
1802 if (last != NULL && nativeInstruction_at(last)->is_Membar() && prev == last) {
1803 NativeMembar *bar = NativeMembar_at(prev);
1804 // We are merging two memory barrier instructions. On AArch64 we
1805 // can do this simply by ORing them together.
1806 bar->set_kind(bar->get_kind() | order_constraint);
1807 BLOCK_COMMENT("merged membar");
1808 } else {
1809 code()->set_last_insn(pc());
1810 dmb(Assembler::barrier(order_constraint));
1811 }
1812 }
1813
1814 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
1815 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
1816 merge_ldst(rt, adr, size_in_bytes, is_store);
1817 code()->clear_last_insn();
1818 return true;
1819 } else {
1820 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
1821 const unsigned mask = size_in_bytes - 1;
1822 if (adr.getMode() == Address::base_plus_offset &&
1823 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
1824 code()->set_last_insn(pc());
1825 }
1826 return false;
1827 }
1828 }
1829
1830 void MacroAssembler::ldr(Register Rx, const Address &adr) {
1831 // We always try to merge two adjacent loads into one ldp.
1832 if (!try_merge_ldst(Rx, adr, 8, false)) {
1833 Assembler::ldr(Rx, adr);
1834 }
1835 }
1836
1837 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
1838 // We always try to merge two adjacent loads into one ldp.
1839 if (!try_merge_ldst(Rw, adr, 4, false)) {
1840 Assembler::ldrw(Rw, adr);
1841 }
1842 }
1843
1844 void MacroAssembler::str(Register Rx, const Address &adr) {
1845 // We always try to merge two adjacent stores into one stp.
1846 if (!try_merge_ldst(Rx, adr, 8, true)) {
1847 Assembler::str(Rx, adr);
1848 }
1849 }
1850
1851 void MacroAssembler::strw(Register Rw, const Address &adr) {
1852 // We always try to merge two adjacent stores into one stp.
1853 if (!try_merge_ldst(Rw, adr, 4, true)) {
1854 Assembler::strw(Rw, adr);
1855 }
1856 }
1857
1858 // MacroAssembler routines found actually to be needed
1859
1860 void MacroAssembler::push(Register src)
1861 {
1862 str(src, Address(pre(esp, -1 * wordSize)));
1863 }
1864
1865 void MacroAssembler::pop(Register dst)
1866 {
1867 ldr(dst, Address(post(esp, 1 * wordSize)));
1868 }
1869
1870 // Note: load_unsigned_short used to be called load_unsigned_word.
1871 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1872 int off = offset();
1873 ldrh(dst, src);
1874 return off;
1875 }
1876
1877 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1878 int off = offset();
1879 ldrb(dst, src);
1880 return off;
1881 }
1882
1883 int MacroAssembler::load_signed_short(Register dst, Address src) {
1884 int off = offset();
1885 ldrsh(dst, src);
1886 return off;
1887 }
1888
1889 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1890 int off = offset();
1891 ldrsb(dst, src);
1892 return off;
1893 }
1894
1895 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1896 int off = offset();
1897 ldrshw(dst, src);
1898 return off;
1899 }
1900
1901 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1902 int off = offset();
1903 ldrsbw(dst, src);
1904 return off;
1905 }
1906
1907 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1908 switch (size_in_bytes) {
1909 case 8: ldr(dst, src); break;
1910 case 4: ldrw(dst, src); break;
1911 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1912 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1913 default: ShouldNotReachHere();
1914 }
1915 }
1916
1917 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1918 switch (size_in_bytes) {
1919 case 8: str(src, dst); break;
1920 case 4: strw(src, dst); break;
1921 case 2: strh(src, dst); break;
1922 case 1: strb(src, dst); break;
1923 default: ShouldNotReachHere();
1924 }
1925 }
1926
1927 void MacroAssembler::decrementw(Register reg, int value)
1928 {
1929 if (value < 0) { incrementw(reg, -value); return; }
1930 if (value == 0) { return; }
1931 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1932 /* else */ {
1933 guarantee(reg != rscratch2, "invalid dst for register decrement");
1934 movw(rscratch2, (unsigned)value);
1935 subw(reg, reg, rscratch2);
1936 }
1937 }
1938
1939 void MacroAssembler::decrement(Register reg, int value)
1940 {
1941 if (value < 0) { increment(reg, -value); return; }
1942 if (value == 0) { return; }
1943 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1944 /* else */ {
1945 assert(reg != rscratch2, "invalid dst for register decrement");
1946 mov(rscratch2, (unsigned long)value);
1947 sub(reg, reg, rscratch2);
1948 }
1949 }
1950
1951 void MacroAssembler::decrementw(Address dst, int value)
1952 {
1953 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1954 if (dst.getMode() == Address::literal) {
1955 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
1956 lea(rscratch2, dst);
1957 dst = Address(rscratch2);
1958 }
1959 ldrw(rscratch1, dst);
1960 decrementw(rscratch1, value);
1961 strw(rscratch1, dst);
1962 }
1963
1964 void MacroAssembler::decrement(Address dst, int value)
1965 {
1966 assert(!dst.uses(rscratch1), "invalid address for decrement");
1967 if (dst.getMode() == Address::literal) {
1968 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
1969 lea(rscratch2, dst);
1970 dst = Address(rscratch2);
1971 }
1972 ldr(rscratch1, dst);
1973 decrement(rscratch1, value);
1974 str(rscratch1, dst);
1975 }
1976
1977 void MacroAssembler::incrementw(Register reg, int value)
1978 {
1979 if (value < 0) { decrementw(reg, -value); return; }
1980 if (value == 0) { return; }
1981 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1982 /* else */ {
1983 assert(reg != rscratch2, "invalid dst for register increment");
1984 movw(rscratch2, (unsigned)value);
1985 addw(reg, reg, rscratch2);
1986 }
1987 }
1988
1989 void MacroAssembler::increment(Register reg, int value)
1990 {
1991 if (value < 0) { decrement(reg, -value); return; }
1992 if (value == 0) { return; }
1993 if (value < (1 << 12)) { add(reg, reg, value); return; }
1994 /* else */ {
1995 assert(reg != rscratch2, "invalid dst for register increment");
1996 movw(rscratch2, (unsigned)value);
1997 add(reg, reg, rscratch2);
1998 }
1999 }
2000
2001 void MacroAssembler::incrementw(Address dst, int value)
2002 {
2003 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2004 if (dst.getMode() == Address::literal) {
2005 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2006 lea(rscratch2, dst);
2007 dst = Address(rscratch2);
2008 }
2009 ldrw(rscratch1, dst);
2010 incrementw(rscratch1, value);
2011 strw(rscratch1, dst);
2012 }
2013
2014 void MacroAssembler::increment(Address dst, int value)
2015 {
2016 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2017 if (dst.getMode() == Address::literal) {
2018 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2019 lea(rscratch2, dst);
2020 dst = Address(rscratch2);
2021 }
2022 ldr(rscratch1, dst);
2023 increment(rscratch1, value);
2024 str(rscratch1, dst);
2025 }
2026
2027
2028 void MacroAssembler::pusha() {
2029 push(0x7fffffff, sp);
2030 }
2031
2032 void MacroAssembler::popa() {
2033 pop(0x7fffffff, sp);
2034 }
2035
2036 // Push lots of registers in the bit set supplied. Don't push sp.
2037 // Return the number of words pushed
2038 int MacroAssembler::push(unsigned int bitset, Register stack) {
2039 int words_pushed = 0;
2040
2041 // Scan bitset to accumulate register pairs
2042 unsigned char regs[32];
2043 int count = 0;
2044 for (int reg = 0; reg <= 30; reg++) {
2045 if (1 & bitset)
2046 regs[count++] = reg;
2047 bitset >>= 1;
2048 }
2049 regs[count++] = zr->encoding_nocheck();
2050 count &= ~1; // Only push an even nuber of regs
2051
2052 if (count) {
2053 stp(as_Register(regs[0]), as_Register(regs[1]),
2054 Address(pre(stack, -count * wordSize)));
2055 words_pushed += 2;
2056 }
2057 for (int i = 2; i < count; i += 2) {
2058 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2059 Address(stack, i * wordSize));
2060 words_pushed += 2;
2061 }
2062
2063 assert(words_pushed == count, "oops, pushed != count");
2064
2065 return count;
2066 }
2067
2068 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2069 int words_pushed = 0;
2070
2071 // Scan bitset to accumulate register pairs
2072 unsigned char regs[32];
2073 int count = 0;
2074 for (int reg = 0; reg <= 30; reg++) {
2075 if (1 & bitset)
2076 regs[count++] = reg;
2077 bitset >>= 1;
2078 }
2079 regs[count++] = zr->encoding_nocheck();
2080 count &= ~1;
2081
2082 for (int i = 2; i < count; i += 2) {
2083 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2084 Address(stack, i * wordSize));
2085 words_pushed += 2;
2086 }
2087 if (count) {
2088 ldp(as_Register(regs[0]), as_Register(regs[1]),
2089 Address(post(stack, count * wordSize)));
2090 words_pushed += 2;
2091 }
2092
2093 assert(words_pushed == count, "oops, pushed != count");
2094
2095 return count;
2096 }
2097 #ifdef ASSERT
2098 void MacroAssembler::verify_heapbase(const char* msg) {
2099 #if 0
2100 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
2101 assert (Universe::heap() != NULL, "java heap should be initialized");
2102 if (CheckCompressedOops) {
2103 Label ok;
2104 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
2105 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2106 br(Assembler::EQ, ok);
2107 stop(msg);
2108 bind(ok);
2109 pop(1 << rscratch1->encoding(), sp);
2110 }
2111 #endif
2112 }
2113 #endif
2114
2115 void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) {
2116 Label done, not_weak;
2117 cbz(value, done); // Use NULL as-is.
2118
2119 STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
2120 tbz(r0, 0, not_weak); // Test for jweak tag.
2121
2122 // Resolve jweak.
2123 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, value,
2124 Address(value, -JNIHandles::weak_tag_value), tmp, thread);
2125 verify_oop(value);
2126 b(done);
2127
2128 bind(not_weak);
2129 // Resolve (untagged) jobject.
2130 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, value, Address(value, 0), tmp,
2131 thread);
2132 verify_oop(value);
2133 bind(done);
2134 }
2135
2136 void MacroAssembler::stop(const char* msg) {
2137 address ip = pc();
2138 pusha();
2139 mov(c_rarg0, (address)msg);
2140 mov(c_rarg1, (address)ip);
2141 mov(c_rarg2, sp);
2142 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
2143 // call(c_rarg3);
2144 blrt(c_rarg3, 3, 0, 1);
2145 hlt(0);
2146 }
2147
2148 void MacroAssembler::unimplemented(const char* what) {
2149 const char* buf = NULL;
2150 {
2151 ResourceMark rm;
2152 stringStream ss;
2153 ss.print("unimplemented: %s", what);
2154 buf = code_string(ss.as_string());
2155 }
2156 stop(buf);
2157 }
2158
2159 // If a constant does not fit in an immediate field, generate some
2160 // number of MOV instructions and then perform the operation.
2161 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
2162 add_sub_imm_insn insn1,
2163 add_sub_reg_insn insn2) {
2164 assert(Rd != zr, "Rd = zr and not setting flags?");
2165 if (operand_valid_for_add_sub_immediate((int)imm)) {
2166 (this->*insn1)(Rd, Rn, imm);
2167 } else {
2168 if (uabs(imm) < (1 << 24)) {
2169 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
2170 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
2171 } else {
2172 assert_different_registers(Rd, Rn);
2173 mov(Rd, (uint64_t)imm);
2174 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2175 }
2176 }
2177 }
2178
2179 // Seperate vsn which sets the flags. Optimisations are more restricted
2180 // because we must set the flags correctly.
2181 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
2182 add_sub_imm_insn insn1,
2183 add_sub_reg_insn insn2) {
2184 if (operand_valid_for_add_sub_immediate((int)imm)) {
2185 (this->*insn1)(Rd, Rn, imm);
2186 } else {
2187 assert_different_registers(Rd, Rn);
2188 assert(Rd != zr, "overflow in immediate operand");
2189 mov(Rd, (uint64_t)imm);
2190 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2191 }
2192 }
2193
2194
2195 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2196 if (increment.is_register()) {
2197 add(Rd, Rn, increment.as_register());
2198 } else {
2199 add(Rd, Rn, increment.as_constant());
2200 }
2201 }
2202
2203 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2204 if (increment.is_register()) {
2205 addw(Rd, Rn, increment.as_register());
2206 } else {
2207 addw(Rd, Rn, increment.as_constant());
2208 }
2209 }
2210
2211 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2212 if (decrement.is_register()) {
2213 sub(Rd, Rn, decrement.as_register());
2214 } else {
2215 sub(Rd, Rn, decrement.as_constant());
2216 }
2217 }
2218
2219 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2220 if (decrement.is_register()) {
2221 subw(Rd, Rn, decrement.as_register());
2222 } else {
2223 subw(Rd, Rn, decrement.as_constant());
2224 }
2225 }
2226
2227 void MacroAssembler::reinit_heapbase()
2228 {
2229 if (UseCompressedOops) {
2230 if (Universe::is_fully_initialized()) {
2231 mov(rheapbase, Universe::narrow_ptrs_base());
2232 } else {
2233 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2234 ldr(rheapbase, Address(rheapbase));
2235 }
2236 }
2237 }
2238
2239 // this simulates the behaviour of the x86 cmpxchg instruction using a
2240 // load linked/store conditional pair. we use the acquire/release
2241 // versions of these instructions so that we flush pending writes as
2242 // per Java semantics.
2243
2244 // n.b the x86 version assumes the old value to be compared against is
2245 // in rax and updates rax with the value located in memory if the
2246 // cmpxchg fails. we supply a register for the old value explicitly
2247
2248 // the aarch64 load linked/store conditional instructions do not
2249 // accept an offset. so, unlike x86, we must provide a plain register
2250 // to identify the memory word to be compared/exchanged rather than a
2251 // register+offset Address.
2252
2253 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2254 Label &succeed, Label *fail) {
2255 // oldv holds comparison value
2256 // newv holds value to write in exchange
2257 // addr identifies memory word to compare against/update
2258 if (UseLSE) {
2259 mov(tmp, oldv);
2260 casal(Assembler::xword, oldv, newv, addr);
2261 cmp(tmp, oldv);
2262 br(Assembler::EQ, succeed);
2263 membar(AnyAny);
2264 } else {
2265 Label retry_load, nope;
2266 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2267 prfm(Address(addr), PSTL1STRM);
2268 bind(retry_load);
2269 // flush and load exclusive from the memory location
2270 // and fail if it is not what we expect
2271 ldaxr(tmp, addr);
2272 cmp(tmp, oldv);
2273 br(Assembler::NE, nope);
2274 // if we store+flush with no intervening write tmp wil be zero
2275 stlxr(tmp, newv, addr);
2276 cbzw(tmp, succeed);
2277 // retry so we only ever return after a load fails to compare
2278 // ensures we don't return a stale value after a failed write.
2279 b(retry_load);
2280 // if the memory word differs we return it in oldv and signal a fail
2281 bind(nope);
2282 membar(AnyAny);
2283 mov(oldv, tmp);
2284 }
2285 if (fail)
2286 b(*fail);
2287 }
2288
2289 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
2290 Label &succeed, Label *fail) {
2291 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
2292 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
2293 }
2294
2295 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2296 Label &succeed, Label *fail) {
2297 // oldv holds comparison value
2298 // newv holds value to write in exchange
2299 // addr identifies memory word to compare against/update
2300 // tmp returns 0/1 for success/failure
2301 if (UseLSE) {
2302 mov(tmp, oldv);
2303 casal(Assembler::word, oldv, newv, addr);
2304 cmp(tmp, oldv);
2305 br(Assembler::EQ, succeed);
2306 membar(AnyAny);
2307 } else {
2308 Label retry_load, nope;
2309 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2310 prfm(Address(addr), PSTL1STRM);
2311 bind(retry_load);
2312 // flush and load exclusive from the memory location
2313 // and fail if it is not what we expect
2314 ldaxrw(tmp, addr);
2315 cmp(tmp, oldv);
2316 br(Assembler::NE, nope);
2317 // if we store+flush with no intervening write tmp wil be zero
2318 stlxrw(tmp, newv, addr);
2319 cbzw(tmp, succeed);
2320 // retry so we only ever return after a load fails to compare
2321 // ensures we don't return a stale value after a failed write.
2322 b(retry_load);
2323 // if the memory word differs we return it in oldv and signal a fail
2324 bind(nope);
2325 membar(AnyAny);
2326 mov(oldv, tmp);
2327 }
2328 if (fail)
2329 b(*fail);
2330 }
2331
2332 // A generic CAS; success or failure is in the EQ flag. A weak CAS
2333 // doesn't retry and may fail spuriously. If the oldval is wanted,
2334 // Pass a register for the result, otherwise pass noreg.
2335
2336 // Clobbers rscratch1
2337 void MacroAssembler::cmpxchg(Register addr, Register expected,
2338 Register new_val,
2339 enum operand_size size,
2340 bool acquire, bool release,
2341 bool weak,
2342 Register result) {
2343 if (result == noreg) result = rscratch1;
2344 if (UseLSE) {
2345 mov(result, expected);
2346 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
2347 cmp(result, expected);
2348 } else {
2349 BLOCK_COMMENT("cmpxchg {");
2350 Label retry_load, done;
2351 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2352 prfm(Address(addr), PSTL1STRM);
2353 bind(retry_load);
2354 load_exclusive(result, addr, size, acquire);
2355 if (size == xword)
2356 cmp(result, expected);
2357 else
2358 cmpw(result, expected);
2359 br(Assembler::NE, done);
2360 store_exclusive(rscratch1, new_val, addr, size, release);
2361 if (weak) {
2362 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
2363 } else {
2364 cbnzw(rscratch1, retry_load);
2365 }
2366 bind(done);
2367 BLOCK_COMMENT("} cmpxchg");
2368 }
2369 }
2370
2371 static bool different(Register a, RegisterOrConstant b, Register c) {
2372 if (b.is_constant())
2373 return a != c;
2374 else
2375 return a != b.as_register() && a != c && b.as_register() != c;
2376 }
2377
2378 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
2379 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
2380 if (UseLSE) { \
2381 prev = prev->is_valid() ? prev : zr; \
2382 if (incr.is_register()) { \
2383 AOP(sz, incr.as_register(), prev, addr); \
2384 } else { \
2385 mov(rscratch2, incr.as_constant()); \
2386 AOP(sz, rscratch2, prev, addr); \
2387 } \
2388 return; \
2389 } \
2390 Register result = rscratch2; \
2391 if (prev->is_valid()) \
2392 result = different(prev, incr, addr) ? prev : rscratch2; \
2393 \
2394 Label retry_load; \
2395 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2396 prfm(Address(addr), PSTL1STRM); \
2397 bind(retry_load); \
2398 LDXR(result, addr); \
2399 OP(rscratch1, result, incr); \
2400 STXR(rscratch2, rscratch1, addr); \
2401 cbnzw(rscratch2, retry_load); \
2402 if (prev->is_valid() && prev != result) { \
2403 IOP(prev, rscratch1, incr); \
2404 } \
2405 }
2406
2407 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
2408 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
2409 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
2410 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
2411
2412 #undef ATOMIC_OP
2413
2414 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
2415 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2416 if (UseLSE) { \
2417 prev = prev->is_valid() ? prev : zr; \
2418 AOP(sz, newv, prev, addr); \
2419 return; \
2420 } \
2421 Register result = rscratch2; \
2422 if (prev->is_valid()) \
2423 result = different(prev, newv, addr) ? prev : rscratch2; \
2424 \
2425 Label retry_load; \
2426 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2427 prfm(Address(addr), PSTL1STRM); \
2428 bind(retry_load); \
2429 LDXR(result, addr); \
2430 STXR(rscratch1, newv, addr); \
2431 cbnzw(rscratch1, retry_load); \
2432 if (prev->is_valid() && prev != result) \
2433 mov(prev, result); \
2434 }
2435
2436 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
2437 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
2438 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
2439 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
2440
2441 #undef ATOMIC_XCHG
2442
2443 #ifndef PRODUCT
2444 extern "C" void findpc(intptr_t x);
2445 #endif
2446
2447 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2448 {
2449 // In order to get locks to work, we need to fake a in_VM state
2450 if (ShowMessageBoxOnError ) {
2451 JavaThread* thread = JavaThread::current();
2452 JavaThreadState saved_state = thread->thread_state();
2453 thread->set_thread_state(_thread_in_vm);
2454 #ifndef PRODUCT
2455 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2456 ttyLocker ttyl;
2457 BytecodeCounter::print();
2458 }
2459 #endif
2460 if (os::message_box(msg, "Execution stopped, print registers?")) {
2461 ttyLocker ttyl;
2462 tty->print_cr(" pc = 0x%016lx", pc);
2463 #ifndef PRODUCT
2464 tty->cr();
2465 findpc(pc);
2466 tty->cr();
2467 #endif
2468 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2469 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2470 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2471 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2472 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2473 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2474 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2475 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2476 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2477 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2478 tty->print_cr("r10 = 0x%016lx", regs[10]);
2479 tty->print_cr("r11 = 0x%016lx", regs[11]);
2480 tty->print_cr("r12 = 0x%016lx", regs[12]);
2481 tty->print_cr("r13 = 0x%016lx", regs[13]);
2482 tty->print_cr("r14 = 0x%016lx", regs[14]);
2483 tty->print_cr("r15 = 0x%016lx", regs[15]);
2484 tty->print_cr("r16 = 0x%016lx", regs[16]);
2485 tty->print_cr("r17 = 0x%016lx", regs[17]);
2486 tty->print_cr("r18 = 0x%016lx", regs[18]);
2487 tty->print_cr("r19 = 0x%016lx", regs[19]);
2488 tty->print_cr("r20 = 0x%016lx", regs[20]);
2489 tty->print_cr("r21 = 0x%016lx", regs[21]);
2490 tty->print_cr("r22 = 0x%016lx", regs[22]);
2491 tty->print_cr("r23 = 0x%016lx", regs[23]);
2492 tty->print_cr("r24 = 0x%016lx", regs[24]);
2493 tty->print_cr("r25 = 0x%016lx", regs[25]);
2494 tty->print_cr("r26 = 0x%016lx", regs[26]);
2495 tty->print_cr("r27 = 0x%016lx", regs[27]);
2496 tty->print_cr("r28 = 0x%016lx", regs[28]);
2497 tty->print_cr("r30 = 0x%016lx", regs[30]);
2498 tty->print_cr("r31 = 0x%016lx", regs[31]);
2499 BREAKPOINT;
2500 }
2501 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2502 } else {
2503 ttyLocker ttyl;
2504 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2505 msg);
2506 assert(false, "DEBUG MESSAGE: %s", msg);
2507 }
2508 }
2509
2510 #ifdef BUILTIN_SIM
2511 // routine to generate an x86 prolog for a stub function which
2512 // bootstraps into the generated ARM code which directly follows the
2513 // stub
2514 //
2515 // the argument encodes the number of general and fp registers
2516 // passed by the caller and the callng convention (currently just
2517 // the number of general registers and assumes C argument passing)
2518
2519 extern "C" {
2520 int aarch64_stub_prolog_size();
2521 void aarch64_stub_prolog();
2522 void aarch64_prolog();
2523 }
2524
2525 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2526 address *prolog_ptr)
2527 {
2528 int calltype = (((ret_type & 0x3) << 8) |
2529 ((fp_arg_count & 0xf) << 4) |
2530 (gp_arg_count & 0xf));
2531
2532 // the addresses for the x86 to ARM entry code we need to use
2533 address start = pc();
2534 // printf("start = %lx\n", start);
2535 int byteCount = aarch64_stub_prolog_size();
2536 // printf("byteCount = %x\n", byteCount);
2537 int instructionCount = (byteCount + 3)/ 4;
2538 // printf("instructionCount = %x\n", instructionCount);
2539 for (int i = 0; i < instructionCount; i++) {
2540 nop();
2541 }
2542
2543 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2544
2545 // write the address of the setup routine and the call format at the
2546 // end of into the copied code
2547 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2548 if (prolog_ptr)
2549 patch_end[-2] = (u_int64_t)prolog_ptr;
2550 patch_end[-1] = calltype;
2551 }
2552 #endif
2553
2554 void MacroAssembler::push_call_clobbered_registers() {
2555 int step = 4 * wordSize;
2556 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2557 sub(sp, sp, step);
2558 mov(rscratch1, -step);
2559 // Push v0-v7, v16-v31.
2560 for (int i = 31; i>= 4; i -= 4) {
2561 if (i <= v7->encoding() || i >= v16->encoding())
2562 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
2563 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
2564 }
2565 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
2566 as_FloatRegister(3), T1D, Address(sp));
2567 }
2568
2569 void MacroAssembler::pop_call_clobbered_registers() {
2570 for (int i = 0; i < 32; i += 4) {
2571 if (i <= v7->encoding() || i >= v16->encoding())
2572 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
2573 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
2574 }
2575
2576 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2577 }
2578
2579 void MacroAssembler::push_CPU_state(bool save_vectors) {
2580 int step = (save_vectors ? 8 : 4) * wordSize;
2581 push(0x3fffffff, sp); // integer registers except lr & sp
2582 mov(rscratch1, -step);
2583 sub(sp, sp, step);
2584 for (int i = 28; i >= 4; i -= 4) {
2585 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
2586 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
2587 }
2588 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
2589 }
2590
2591 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2592 int step = (restore_vectors ? 8 : 4) * wordSize;
2593 for (int i = 0; i <= 28; i += 4)
2594 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
2595 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
2596 pop(0x3fffffff, sp); // integer registers except lr & sp
2597 }
2598
2599 /**
2600 * Helpers for multiply_to_len().
2601 */
2602 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2603 Register src1, Register src2) {
2604 adds(dest_lo, dest_lo, src1);
2605 adc(dest_hi, dest_hi, zr);
2606 adds(dest_lo, dest_lo, src2);
2607 adc(final_dest_hi, dest_hi, zr);
2608 }
2609
2610 // Generate an address from (r + r1 extend offset). "size" is the
2611 // size of the operand. The result may be in rscratch2.
2612 Address MacroAssembler::offsetted_address(Register r, Register r1,
2613 Address::extend ext, int offset, int size) {
2614 if (offset || (ext.shift() % size != 0)) {
2615 lea(rscratch2, Address(r, r1, ext));
2616 return Address(rscratch2, offset);
2617 } else {
2618 return Address(r, r1, ext);
2619 }
2620 }
2621
2622 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2623 {
2624 assert(offset >= 0, "spill to negative address?");
2625 // Offset reachable ?
2626 // Not aligned - 9 bits signed offset
2627 // Aligned - 12 bits unsigned offset shifted
2628 Register base = sp;
2629 if ((offset & (size-1)) && offset >= (1<<8)) {
2630 add(tmp, base, offset & ((1<<12)-1));
2631 base = tmp;
2632 offset &= -1<<12;
2633 }
2634
2635 if (offset >= (1<<12) * size) {
2636 add(tmp, base, offset & (((1<<12)-1)<<12));
2637 base = tmp;
2638 offset &= ~(((1<<12)-1)<<12);
2639 }
2640
2641 return Address(base, offset);
2642 }
2643
2644 // Checks whether offset is aligned.
2645 // Returns true if it is, else false.
2646 bool MacroAssembler::merge_alignment_check(Register base,
2647 size_t size,
2648 long cur_offset,
2649 long prev_offset) const {
2650 if (AvoidUnalignedAccesses) {
2651 if (base == sp) {
2652 // Checks whether low offset if aligned to pair of registers.
2653 long pair_mask = size * 2 - 1;
2654 long offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2655 return (offset & pair_mask) == 0;
2656 } else { // If base is not sp, we can't guarantee the access is aligned.
2657 return false;
2658 }
2659 } else {
2660 long mask = size - 1;
2661 // Load/store pair instruction only supports element size aligned offset.
2662 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
2663 }
2664 }
2665
2666 // Checks whether current and previous loads/stores can be merged.
2667 // Returns true if it can be merged, else false.
2668 bool MacroAssembler::ldst_can_merge(Register rt,
2669 const Address &adr,
2670 size_t cur_size_in_bytes,
2671 bool is_store) const {
2672 address prev = pc() - NativeInstruction::instruction_size;
2673 address last = code()->last_insn();
2674
2675 if (last == NULL || !nativeInstruction_at(last)->is_Imm_LdSt()) {
2676 return false;
2677 }
2678
2679 if (adr.getMode() != Address::base_plus_offset || prev != last) {
2680 return false;
2681 }
2682
2683 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2684 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
2685
2686 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
2687 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
2688
2689 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
2690 return false;
2691 }
2692
2693 long max_offset = 63 * prev_size_in_bytes;
2694 long min_offset = -64 * prev_size_in_bytes;
2695
2696 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
2697
2698 // Only same base can be merged.
2699 if (adr.base() != prev_ldst->base()) {
2700 return false;
2701 }
2702
2703 long cur_offset = adr.offset();
2704 long prev_offset = prev_ldst->offset();
2705 size_t diff = abs(cur_offset - prev_offset);
2706 if (diff != prev_size_in_bytes) {
2707 return false;
2708 }
2709
2710 // Following cases can not be merged:
2711 // ldr x2, [x2, #8]
2712 // ldr x3, [x2, #16]
2713 // or:
2714 // ldr x2, [x3, #8]
2715 // ldr x2, [x3, #16]
2716 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
2717 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
2718 return false;
2719 }
2720
2721 long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2722 // Offset range must be in ldp/stp instruction's range.
2723 if (low_offset > max_offset || low_offset < min_offset) {
2724 return false;
2725 }
2726
2727 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
2728 return true;
2729 }
2730
2731 return false;
2732 }
2733
2734 // Merge current load/store with previous load/store into ldp/stp.
2735 void MacroAssembler::merge_ldst(Register rt,
2736 const Address &adr,
2737 size_t cur_size_in_bytes,
2738 bool is_store) {
2739
2740 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
2741
2742 Register rt_low, rt_high;
2743 address prev = pc() - NativeInstruction::instruction_size;
2744 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2745
2746 long offset;
2747
2748 if (adr.offset() < prev_ldst->offset()) {
2749 offset = adr.offset();
2750 rt_low = rt;
2751 rt_high = prev_ldst->target();
2752 } else {
2753 offset = prev_ldst->offset();
2754 rt_low = prev_ldst->target();
2755 rt_high = rt;
2756 }
2757
2758 Address adr_p = Address(prev_ldst->base(), offset);
2759 // Overwrite previous generated binary.
2760 code_section()->set_end(prev);
2761
2762 const int sz = prev_ldst->size_in_bytes();
2763 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
2764 if (!is_store) {
2765 BLOCK_COMMENT("merged ldr pair");
2766 if (sz == 8) {
2767 ldp(rt_low, rt_high, adr_p);
2768 } else {
2769 ldpw(rt_low, rt_high, adr_p);
2770 }
2771 } else {
2772 BLOCK_COMMENT("merged str pair");
2773 if (sz == 8) {
2774 stp(rt_low, rt_high, adr_p);
2775 } else {
2776 stpw(rt_low, rt_high, adr_p);
2777 }
2778 }
2779 }
2780
2781 /**
2782 * Multiply 64 bit by 64 bit first loop.
2783 */
2784 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2785 Register y, Register y_idx, Register z,
2786 Register carry, Register product,
2787 Register idx, Register kdx) {
2788 //
2789 // jlong carry, x[], y[], z[];
2790 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2791 // huge_128 product = y[idx] * x[xstart] + carry;
2792 // z[kdx] = (jlong)product;
2793 // carry = (jlong)(product >>> 64);
2794 // }
2795 // z[xstart] = carry;
2796 //
2797
2798 Label L_first_loop, L_first_loop_exit;
2799 Label L_one_x, L_one_y, L_multiply;
2800
2801 subsw(xstart, xstart, 1);
2802 br(Assembler::MI, L_one_x);
2803
2804 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2805 ldr(x_xstart, Address(rscratch1));
2806 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2807
2808 bind(L_first_loop);
2809 subsw(idx, idx, 1);
2810 br(Assembler::MI, L_first_loop_exit);
2811 subsw(idx, idx, 1);
2812 br(Assembler::MI, L_one_y);
2813 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2814 ldr(y_idx, Address(rscratch1));
2815 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2816 bind(L_multiply);
2817
2818 // AArch64 has a multiply-accumulate instruction that we can't use
2819 // here because it has no way to process carries, so we have to use
2820 // separate add and adc instructions. Bah.
2821 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2822 mul(product, x_xstart, y_idx);
2823 adds(product, product, carry);
2824 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2825
2826 subw(kdx, kdx, 2);
2827 ror(product, product, 32); // back to big-endian
2828 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2829
2830 b(L_first_loop);
2831
2832 bind(L_one_y);
2833 ldrw(y_idx, Address(y, 0));
2834 b(L_multiply);
2835
2836 bind(L_one_x);
2837 ldrw(x_xstart, Address(x, 0));
2838 b(L_first_loop);
2839
2840 bind(L_first_loop_exit);
2841 }
2842
2843 /**
2844 * Multiply 128 bit by 128. Unrolled inner loop.
2845 *
2846 */
2847 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2848 Register carry, Register carry2,
2849 Register idx, Register jdx,
2850 Register yz_idx1, Register yz_idx2,
2851 Register tmp, Register tmp3, Register tmp4,
2852 Register tmp6, Register product_hi) {
2853
2854 // jlong carry, x[], y[], z[];
2855 // int kdx = ystart+1;
2856 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2857 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2858 // jlong carry2 = (jlong)(tmp3 >>> 64);
2859 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2860 // carry = (jlong)(tmp4 >>> 64);
2861 // z[kdx+idx+1] = (jlong)tmp3;
2862 // z[kdx+idx] = (jlong)tmp4;
2863 // }
2864 // idx += 2;
2865 // if (idx > 0) {
2866 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2867 // z[kdx+idx] = (jlong)yz_idx1;
2868 // carry = (jlong)(yz_idx1 >>> 64);
2869 // }
2870 //
2871
2872 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2873
2874 lsrw(jdx, idx, 2);
2875
2876 bind(L_third_loop);
2877
2878 subsw(jdx, jdx, 1);
2879 br(Assembler::MI, L_third_loop_exit);
2880 subw(idx, idx, 4);
2881
2882 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2883
2884 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2885
2886 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2887
2888 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2889 ror(yz_idx2, yz_idx2, 32);
2890
2891 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2892
2893 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2894 umulh(tmp4, product_hi, yz_idx1);
2895
2896 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2897 ror(rscratch2, rscratch2, 32);
2898
2899 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2900 umulh(carry2, product_hi, yz_idx2);
2901
2902 // propagate sum of both multiplications into carry:tmp4:tmp3
2903 adds(tmp3, tmp3, carry);
2904 adc(tmp4, tmp4, zr);
2905 adds(tmp3, tmp3, rscratch1);
2906 adcs(tmp4, tmp4, tmp);
2907 adc(carry, carry2, zr);
2908 adds(tmp4, tmp4, rscratch2);
2909 adc(carry, carry, zr);
2910
2911 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2912 ror(tmp4, tmp4, 32);
2913 stp(tmp4, tmp3, Address(tmp6, 0));
2914
2915 b(L_third_loop);
2916 bind (L_third_loop_exit);
2917
2918 andw (idx, idx, 0x3);
2919 cbz(idx, L_post_third_loop_done);
2920
2921 Label L_check_1;
2922 subsw(idx, idx, 2);
2923 br(Assembler::MI, L_check_1);
2924
2925 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2926 ldr(yz_idx1, Address(rscratch1, 0));
2927 ror(yz_idx1, yz_idx1, 32);
2928 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2929 umulh(tmp4, product_hi, yz_idx1);
2930 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2931 ldr(yz_idx2, Address(rscratch1, 0));
2932 ror(yz_idx2, yz_idx2, 32);
2933
2934 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2935
2936 ror(tmp3, tmp3, 32);
2937 str(tmp3, Address(rscratch1, 0));
2938
2939 bind (L_check_1);
2940
2941 andw (idx, idx, 0x1);
2942 subsw(idx, idx, 1);
2943 br(Assembler::MI, L_post_third_loop_done);
2944 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2945 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2946 umulh(carry2, tmp4, product_hi);
2947 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2948
2949 add2_with_carry(carry2, tmp3, tmp4, carry);
2950
2951 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2952 extr(carry, carry2, tmp3, 32);
2953
2954 bind(L_post_third_loop_done);
2955 }
2956
2957 /**
2958 * Code for BigInteger::multiplyToLen() instrinsic.
2959 *
2960 * r0: x
2961 * r1: xlen
2962 * r2: y
2963 * r3: ylen
2964 * r4: z
2965 * r5: zlen
2966 * r10: tmp1
2967 * r11: tmp2
2968 * r12: tmp3
2969 * r13: tmp4
2970 * r14: tmp5
2971 * r15: tmp6
2972 * r16: tmp7
2973 *
2974 */
2975 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2976 Register z, Register zlen,
2977 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2978 Register tmp5, Register tmp6, Register product_hi) {
2979
2980 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2981
2982 const Register idx = tmp1;
2983 const Register kdx = tmp2;
2984 const Register xstart = tmp3;
2985
2986 const Register y_idx = tmp4;
2987 const Register carry = tmp5;
2988 const Register product = xlen;
2989 const Register x_xstart = zlen; // reuse register
2990
2991 // First Loop.
2992 //
2993 // final static long LONG_MASK = 0xffffffffL;
2994 // int xstart = xlen - 1;
2995 // int ystart = ylen - 1;
2996 // long carry = 0;
2997 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2998 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
2999 // z[kdx] = (int)product;
3000 // carry = product >>> 32;
3001 // }
3002 // z[xstart] = (int)carry;
3003 //
3004
3005 movw(idx, ylen); // idx = ylen;
3006 movw(kdx, zlen); // kdx = xlen+ylen;
3007 mov(carry, zr); // carry = 0;
3008
3009 Label L_done;
3010
3011 movw(xstart, xlen);
3012 subsw(xstart, xstart, 1);
3013 br(Assembler::MI, L_done);
3014
3015 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
3016
3017 Label L_second_loop;
3018 cbzw(kdx, L_second_loop);
3019
3020 Label L_carry;
3021 subw(kdx, kdx, 1);
3022 cbzw(kdx, L_carry);
3023
3024 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3025 lsr(carry, carry, 32);
3026 subw(kdx, kdx, 1);
3027
3028 bind(L_carry);
3029 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3030
3031 // Second and third (nested) loops.
3032 //
3033 // for (int i = xstart-1; i >= 0; i--) { // Second loop
3034 // carry = 0;
3035 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
3036 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
3037 // (z[k] & LONG_MASK) + carry;
3038 // z[k] = (int)product;
3039 // carry = product >>> 32;
3040 // }
3041 // z[i] = (int)carry;
3042 // }
3043 //
3044 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
3045
3046 const Register jdx = tmp1;
3047
3048 bind(L_second_loop);
3049 mov(carry, zr); // carry = 0;
3050 movw(jdx, ylen); // j = ystart+1
3051
3052 subsw(xstart, xstart, 1); // i = xstart-1;
3053 br(Assembler::MI, L_done);
3054
3055 str(z, Address(pre(sp, -4 * wordSize)));
3056
3057 Label L_last_x;
3058 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
3059 subsw(xstart, xstart, 1); // i = xstart-1;
3060 br(Assembler::MI, L_last_x);
3061
3062 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
3063 ldr(product_hi, Address(rscratch1));
3064 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3065
3066 Label L_third_loop_prologue;
3067 bind(L_third_loop_prologue);
3068
3069 str(ylen, Address(sp, wordSize));
3070 stp(x, xstart, Address(sp, 2 * wordSize));
3071 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
3072 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
3073 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
3074 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
3075
3076 addw(tmp3, xlen, 1);
3077 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3078 subsw(tmp3, tmp3, 1);
3079 br(Assembler::MI, L_done);
3080
3081 lsr(carry, carry, 32);
3082 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3083 b(L_second_loop);
3084
3085 // Next infrequent code is moved outside loops.
3086 bind(L_last_x);
3087 ldrw(product_hi, Address(x, 0));
3088 b(L_third_loop_prologue);
3089
3090 bind(L_done);
3091 }
3092
3093 // Code for BigInteger::mulAdd instrinsic
3094 // out = r0
3095 // in = r1
3096 // offset = r2 (already out.length-offset)
3097 // len = r3
3098 // k = r4
3099 //
3100 // pseudo code from java implementation:
3101 // carry = 0;
3102 // offset = out.length-offset - 1;
3103 // for (int j=len-1; j >= 0; j--) {
3104 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
3105 // out[offset--] = (int)product;
3106 // carry = product >>> 32;
3107 // }
3108 // return (int)carry;
3109 void MacroAssembler::mul_add(Register out, Register in, Register offset,
3110 Register len, Register k) {
3111 Label LOOP, END;
3112 // pre-loop
3113 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
3114 csel(out, zr, out, Assembler::EQ);
3115 br(Assembler::EQ, END);
3116 add(in, in, len, LSL, 2); // in[j+1] address
3117 add(offset, out, offset, LSL, 2); // out[offset + 1] address
3118 mov(out, zr); // used to keep carry now
3119 BIND(LOOP);
3120 ldrw(rscratch1, Address(pre(in, -4)));
3121 madd(rscratch1, rscratch1, k, out);
3122 ldrw(rscratch2, Address(pre(offset, -4)));
3123 add(rscratch1, rscratch1, rscratch2);
3124 strw(rscratch1, Address(offset));
3125 lsr(out, rscratch1, 32);
3126 subs(len, len, 1);
3127 br(Assembler::NE, LOOP);
3128 BIND(END);
3129 }
3130
3131 /**
3132 * Emits code to update CRC-32 with a byte value according to constants in table
3133 *
3134 * @param [in,out]crc Register containing the crc.
3135 * @param [in]val Register containing the byte to fold into the CRC.
3136 * @param [in]table Register containing the table of crc constants.
3137 *
3138 * uint32_t crc;
3139 * val = crc_table[(val ^ crc) & 0xFF];
3140 * crc = val ^ (crc >> 8);
3141 *
3142 */
3143 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3144 eor(val, val, crc);
3145 andr(val, val, 0xff);
3146 ldrw(val, Address(table, val, Address::lsl(2)));
3147 eor(crc, val, crc, Assembler::LSR, 8);
3148 }
3149
3150 /**
3151 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
3152 *
3153 * @param [in,out]crc Register containing the crc.
3154 * @param [in]v Register containing the 32-bit to fold into the CRC.
3155 * @param [in]table0 Register containing table 0 of crc constants.
3156 * @param [in]table1 Register containing table 1 of crc constants.
3157 * @param [in]table2 Register containing table 2 of crc constants.
3158 * @param [in]table3 Register containing table 3 of crc constants.
3159 *
3160 * uint32_t crc;
3161 * v = crc ^ v
3162 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
3163 *
3164 */
3165 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
3166 Register table0, Register table1, Register table2, Register table3,
3167 bool upper) {
3168 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
3169 uxtb(tmp, v);
3170 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
3171 ubfx(tmp, v, 8, 8);
3172 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
3173 eor(crc, crc, tmp);
3174 ubfx(tmp, v, 16, 8);
3175 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
3176 eor(crc, crc, tmp);
3177 ubfx(tmp, v, 24, 8);
3178 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
3179 eor(crc, crc, tmp);
3180 }
3181
3182 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
3183 Register len, Register tmp0, Register tmp1, Register tmp2,
3184 Register tmp3) {
3185 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3186 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3187
3188 mvnw(crc, crc);
3189
3190 subs(len, len, 128);
3191 br(Assembler::GE, CRC_by64_pre);
3192 BIND(CRC_less64);
3193 adds(len, len, 128-32);
3194 br(Assembler::GE, CRC_by32_loop);
3195 BIND(CRC_less32);
3196 adds(len, len, 32-4);
3197 br(Assembler::GE, CRC_by4_loop);
3198 adds(len, len, 4);
3199 br(Assembler::GT, CRC_by1_loop);
3200 b(L_exit);
3201
3202 BIND(CRC_by32_loop);
3203 ldp(tmp0, tmp1, Address(post(buf, 16)));
3204 subs(len, len, 32);
3205 crc32x(crc, crc, tmp0);
3206 ldr(tmp2, Address(post(buf, 8)));
3207 crc32x(crc, crc, tmp1);
3208 ldr(tmp3, Address(post(buf, 8)));
3209 crc32x(crc, crc, tmp2);
3210 crc32x(crc, crc, tmp3);
3211 br(Assembler::GE, CRC_by32_loop);
3212 cmn(len, 32);
3213 br(Assembler::NE, CRC_less32);
3214 b(L_exit);
3215
3216 BIND(CRC_by4_loop);
3217 ldrw(tmp0, Address(post(buf, 4)));
3218 subs(len, len, 4);
3219 crc32w(crc, crc, tmp0);
3220 br(Assembler::GE, CRC_by4_loop);
3221 adds(len, len, 4);
3222 br(Assembler::LE, L_exit);
3223 BIND(CRC_by1_loop);
3224 ldrb(tmp0, Address(post(buf, 1)));
3225 subs(len, len, 1);
3226 crc32b(crc, crc, tmp0);
3227 br(Assembler::GT, CRC_by1_loop);
3228 b(L_exit);
3229
3230 BIND(CRC_by64_pre);
3231 sub(buf, buf, 8);
3232 ldp(tmp0, tmp1, Address(buf, 8));
3233 crc32x(crc, crc, tmp0);
3234 ldr(tmp2, Address(buf, 24));
3235 crc32x(crc, crc, tmp1);
3236 ldr(tmp3, Address(buf, 32));
3237 crc32x(crc, crc, tmp2);
3238 ldr(tmp0, Address(buf, 40));
3239 crc32x(crc, crc, tmp3);
3240 ldr(tmp1, Address(buf, 48));
3241 crc32x(crc, crc, tmp0);
3242 ldr(tmp2, Address(buf, 56));
3243 crc32x(crc, crc, tmp1);
3244 ldr(tmp3, Address(pre(buf, 64)));
3245
3246 b(CRC_by64_loop);
3247
3248 align(CodeEntryAlignment);
3249 BIND(CRC_by64_loop);
3250 subs(len, len, 64);
3251 crc32x(crc, crc, tmp2);
3252 ldr(tmp0, Address(buf, 8));
3253 crc32x(crc, crc, tmp3);
3254 ldr(tmp1, Address(buf, 16));
3255 crc32x(crc, crc, tmp0);
3256 ldr(tmp2, Address(buf, 24));
3257 crc32x(crc, crc, tmp1);
3258 ldr(tmp3, Address(buf, 32));
3259 crc32x(crc, crc, tmp2);
3260 ldr(tmp0, Address(buf, 40));
3261 crc32x(crc, crc, tmp3);
3262 ldr(tmp1, Address(buf, 48));
3263 crc32x(crc, crc, tmp0);
3264 ldr(tmp2, Address(buf, 56));
3265 crc32x(crc, crc, tmp1);
3266 ldr(tmp3, Address(pre(buf, 64)));
3267 br(Assembler::GE, CRC_by64_loop);
3268
3269 // post-loop
3270 crc32x(crc, crc, tmp2);
3271 crc32x(crc, crc, tmp3);
3272
3273 sub(len, len, 64);
3274 add(buf, buf, 8);
3275 cmn(len, 128);
3276 br(Assembler::NE, CRC_less64);
3277 BIND(L_exit);
3278 mvnw(crc, crc);
3279 }
3280
3281 /**
3282 * @param crc register containing existing CRC (32-bit)
3283 * @param buf register pointing to input byte buffer (byte*)
3284 * @param len register containing number of bytes
3285 * @param table register that will contain address of CRC table
3286 * @param tmp scratch register
3287 */
3288 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
3289 Register table0, Register table1, Register table2, Register table3,
3290 Register tmp, Register tmp2, Register tmp3) {
3291 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
3292 unsigned long offset;
3293
3294 if (UseCRC32) {
3295 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
3296 return;
3297 }
3298
3299 mvnw(crc, crc);
3300
3301 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
3302 if (offset) add(table0, table0, offset);
3303 add(table1, table0, 1*256*sizeof(juint));
3304 add(table2, table0, 2*256*sizeof(juint));
3305 add(table3, table0, 3*256*sizeof(juint));
3306
3307 if (UseNeon) {
3308 cmp(len, 64);
3309 br(Assembler::LT, L_by16);
3310 eor(v16, T16B, v16, v16);
3311
3312 Label L_fold;
3313
3314 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
3315
3316 ld1(v0, v1, T2D, post(buf, 32));
3317 ld1r(v4, T2D, post(tmp, 8));
3318 ld1r(v5, T2D, post(tmp, 8));
3319 ld1r(v6, T2D, post(tmp, 8));
3320 ld1r(v7, T2D, post(tmp, 8));
3321 mov(v16, T4S, 0, crc);
3322
3323 eor(v0, T16B, v0, v16);
3324 sub(len, len, 64);
3325
3326 BIND(L_fold);
3327 pmull(v22, T8H, v0, v5, T8B);
3328 pmull(v20, T8H, v0, v7, T8B);
3329 pmull(v23, T8H, v0, v4, T8B);
3330 pmull(v21, T8H, v0, v6, T8B);
3331
3332 pmull2(v18, T8H, v0, v5, T16B);
3333 pmull2(v16, T8H, v0, v7, T16B);
3334 pmull2(v19, T8H, v0, v4, T16B);
3335 pmull2(v17, T8H, v0, v6, T16B);
3336
3337 uzp1(v24, T8H, v20, v22);
3338 uzp2(v25, T8H, v20, v22);
3339 eor(v20, T16B, v24, v25);
3340
3341 uzp1(v26, T8H, v16, v18);
3342 uzp2(v27, T8H, v16, v18);
3343 eor(v16, T16B, v26, v27);
3344
3345 ushll2(v22, T4S, v20, T8H, 8);
3346 ushll(v20, T4S, v20, T4H, 8);
3347
3348 ushll2(v18, T4S, v16, T8H, 8);
3349 ushll(v16, T4S, v16, T4H, 8);
3350
3351 eor(v22, T16B, v23, v22);
3352 eor(v18, T16B, v19, v18);
3353 eor(v20, T16B, v21, v20);
3354 eor(v16, T16B, v17, v16);
3355
3356 uzp1(v17, T2D, v16, v20);
3357 uzp2(v21, T2D, v16, v20);
3358 eor(v17, T16B, v17, v21);
3359
3360 ushll2(v20, T2D, v17, T4S, 16);
3361 ushll(v16, T2D, v17, T2S, 16);
3362
3363 eor(v20, T16B, v20, v22);
3364 eor(v16, T16B, v16, v18);
3365
3366 uzp1(v17, T2D, v20, v16);
3367 uzp2(v21, T2D, v20, v16);
3368 eor(v28, T16B, v17, v21);
3369
3370 pmull(v22, T8H, v1, v5, T8B);
3371 pmull(v20, T8H, v1, v7, T8B);
3372 pmull(v23, T8H, v1, v4, T8B);
3373 pmull(v21, T8H, v1, v6, T8B);
3374
3375 pmull2(v18, T8H, v1, v5, T16B);
3376 pmull2(v16, T8H, v1, v7, T16B);
3377 pmull2(v19, T8H, v1, v4, T16B);
3378 pmull2(v17, T8H, v1, v6, T16B);
3379
3380 ld1(v0, v1, T2D, post(buf, 32));
3381
3382 uzp1(v24, T8H, v20, v22);
3383 uzp2(v25, T8H, v20, v22);
3384 eor(v20, T16B, v24, v25);
3385
3386 uzp1(v26, T8H, v16, v18);
3387 uzp2(v27, T8H, v16, v18);
3388 eor(v16, T16B, v26, v27);
3389
3390 ushll2(v22, T4S, v20, T8H, 8);
3391 ushll(v20, T4S, v20, T4H, 8);
3392
3393 ushll2(v18, T4S, v16, T8H, 8);
3394 ushll(v16, T4S, v16, T4H, 8);
3395
3396 eor(v22, T16B, v23, v22);
3397 eor(v18, T16B, v19, v18);
3398 eor(v20, T16B, v21, v20);
3399 eor(v16, T16B, v17, v16);
3400
3401 uzp1(v17, T2D, v16, v20);
3402 uzp2(v21, T2D, v16, v20);
3403 eor(v16, T16B, v17, v21);
3404
3405 ushll2(v20, T2D, v16, T4S, 16);
3406 ushll(v16, T2D, v16, T2S, 16);
3407
3408 eor(v20, T16B, v22, v20);
3409 eor(v16, T16B, v16, v18);
3410
3411 uzp1(v17, T2D, v20, v16);
3412 uzp2(v21, T2D, v20, v16);
3413 eor(v20, T16B, v17, v21);
3414
3415 shl(v16, T2D, v28, 1);
3416 shl(v17, T2D, v20, 1);
3417
3418 eor(v0, T16B, v0, v16);
3419 eor(v1, T16B, v1, v17);
3420
3421 subs(len, len, 32);
3422 br(Assembler::GE, L_fold);
3423
3424 mov(crc, 0);
3425 mov(tmp, v0, T1D, 0);
3426 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3427 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3428 mov(tmp, v0, T1D, 1);
3429 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3430 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3431 mov(tmp, v1, T1D, 0);
3432 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3433 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3434 mov(tmp, v1, T1D, 1);
3435 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3436 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3437
3438 add(len, len, 32);
3439 }
3440
3441 BIND(L_by16);
3442 subs(len, len, 16);
3443 br(Assembler::GE, L_by16_loop);
3444 adds(len, len, 16-4);
3445 br(Assembler::GE, L_by4_loop);
3446 adds(len, len, 4);
3447 br(Assembler::GT, L_by1_loop);
3448 b(L_exit);
3449
3450 BIND(L_by4_loop);
3451 ldrw(tmp, Address(post(buf, 4)));
3452 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
3453 subs(len, len, 4);
3454 br(Assembler::GE, L_by4_loop);
3455 adds(len, len, 4);
3456 br(Assembler::LE, L_exit);
3457 BIND(L_by1_loop);
3458 subs(len, len, 1);
3459 ldrb(tmp, Address(post(buf, 1)));
3460 update_byte_crc32(crc, tmp, table0);
3461 br(Assembler::GT, L_by1_loop);
3462 b(L_exit);
3463
3464 align(CodeEntryAlignment);
3465 BIND(L_by16_loop);
3466 subs(len, len, 16);
3467 ldp(tmp, tmp3, Address(post(buf, 16)));
3468 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3469 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3470 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
3471 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
3472 br(Assembler::GE, L_by16_loop);
3473 adds(len, len, 16-4);
3474 br(Assembler::GE, L_by4_loop);
3475 adds(len, len, 4);
3476 br(Assembler::GT, L_by1_loop);
3477 BIND(L_exit);
3478 mvnw(crc, crc);
3479 }
3480
3481 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
3482 Register len, Register tmp0, Register tmp1, Register tmp2,
3483 Register tmp3) {
3484 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3485 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3486
3487 subs(len, len, 128);
3488 br(Assembler::GE, CRC_by64_pre);
3489 BIND(CRC_less64);
3490 adds(len, len, 128-32);
3491 br(Assembler::GE, CRC_by32_loop);
3492 BIND(CRC_less32);
3493 adds(len, len, 32-4);
3494 br(Assembler::GE, CRC_by4_loop);
3495 adds(len, len, 4);
3496 br(Assembler::GT, CRC_by1_loop);
3497 b(L_exit);
3498
3499 BIND(CRC_by32_loop);
3500 ldp(tmp0, tmp1, Address(post(buf, 16)));
3501 subs(len, len, 32);
3502 crc32cx(crc, crc, tmp0);
3503 ldr(tmp2, Address(post(buf, 8)));
3504 crc32cx(crc, crc, tmp1);
3505 ldr(tmp3, Address(post(buf, 8)));
3506 crc32cx(crc, crc, tmp2);
3507 crc32cx(crc, crc, tmp3);
3508 br(Assembler::GE, CRC_by32_loop);
3509 cmn(len, 32);
3510 br(Assembler::NE, CRC_less32);
3511 b(L_exit);
3512
3513 BIND(CRC_by4_loop);
3514 ldrw(tmp0, Address(post(buf, 4)));
3515 subs(len, len, 4);
3516 crc32cw(crc, crc, tmp0);
3517 br(Assembler::GE, CRC_by4_loop);
3518 adds(len, len, 4);
3519 br(Assembler::LE, L_exit);
3520 BIND(CRC_by1_loop);
3521 ldrb(tmp0, Address(post(buf, 1)));
3522 subs(len, len, 1);
3523 crc32cb(crc, crc, tmp0);
3524 br(Assembler::GT, CRC_by1_loop);
3525 b(L_exit);
3526
3527 BIND(CRC_by64_pre);
3528 sub(buf, buf, 8);
3529 ldp(tmp0, tmp1, Address(buf, 8));
3530 crc32cx(crc, crc, tmp0);
3531 ldr(tmp2, Address(buf, 24));
3532 crc32cx(crc, crc, tmp1);
3533 ldr(tmp3, Address(buf, 32));
3534 crc32cx(crc, crc, tmp2);
3535 ldr(tmp0, Address(buf, 40));
3536 crc32cx(crc, crc, tmp3);
3537 ldr(tmp1, Address(buf, 48));
3538 crc32cx(crc, crc, tmp0);
3539 ldr(tmp2, Address(buf, 56));
3540 crc32cx(crc, crc, tmp1);
3541 ldr(tmp3, Address(pre(buf, 64)));
3542
3543 b(CRC_by64_loop);
3544
3545 align(CodeEntryAlignment);
3546 BIND(CRC_by64_loop);
3547 subs(len, len, 64);
3548 crc32cx(crc, crc, tmp2);
3549 ldr(tmp0, Address(buf, 8));
3550 crc32cx(crc, crc, tmp3);
3551 ldr(tmp1, Address(buf, 16));
3552 crc32cx(crc, crc, tmp0);
3553 ldr(tmp2, Address(buf, 24));
3554 crc32cx(crc, crc, tmp1);
3555 ldr(tmp3, Address(buf, 32));
3556 crc32cx(crc, crc, tmp2);
3557 ldr(tmp0, Address(buf, 40));
3558 crc32cx(crc, crc, tmp3);
3559 ldr(tmp1, Address(buf, 48));
3560 crc32cx(crc, crc, tmp0);
3561 ldr(tmp2, Address(buf, 56));
3562 crc32cx(crc, crc, tmp1);
3563 ldr(tmp3, Address(pre(buf, 64)));
3564 br(Assembler::GE, CRC_by64_loop);
3565
3566 // post-loop
3567 crc32cx(crc, crc, tmp2);
3568 crc32cx(crc, crc, tmp3);
3569
3570 sub(len, len, 64);
3571 add(buf, buf, 8);
3572 cmn(len, 128);
3573 br(Assembler::NE, CRC_less64);
3574 BIND(L_exit);
3575 }
3576
3577 /**
3578 * @param crc register containing existing CRC (32-bit)
3579 * @param buf register pointing to input byte buffer (byte*)
3580 * @param len register containing number of bytes
3581 * @param table register that will contain address of CRC table
3582 * @param tmp scratch register
3583 */
3584 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
3585 Register table0, Register table1, Register table2, Register table3,
3586 Register tmp, Register tmp2, Register tmp3) {
3587 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
3588 }
3589
3590
3591 SkipIfEqual::SkipIfEqual(
3592 MacroAssembler* masm, const bool* flag_addr, bool value) {
3593 _masm = masm;
3594 unsigned long offset;
3595 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3596 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3597 _masm->cbzw(rscratch1, _label);
3598 }
3599
3600 SkipIfEqual::~SkipIfEqual() {
3601 _masm->bind(_label);
3602 }
3603
3604 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3605 Address adr;
3606 switch(dst.getMode()) {
3607 case Address::base_plus_offset:
3608 // This is the expected mode, although we allow all the other
3609 // forms below.
3610 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3611 break;
3612 default:
3613 lea(rscratch2, dst);
3614 adr = Address(rscratch2);
3615 break;
3616 }
3617 ldr(rscratch1, adr);
3618 add(rscratch1, rscratch1, src);
3619 str(rscratch1, adr);
3620 }
3621
3622 void MacroAssembler::cmpptr(Register src1, Address src2) {
3623 unsigned long offset;
3624 adrp(rscratch1, src2, offset);
3625 ldr(rscratch1, Address(rscratch1, offset));
3626 cmp(src1, rscratch1);
3627 }
3628
3629 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
3630 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3631 bs->obj_equals(this, obj1, obj2);
3632 }
3633
3634 void MacroAssembler::load_klass(Register dst, Register src) {
3635 if (UseCompressedClassPointers) {
3636 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3637 decode_klass_not_null(dst);
3638 } else {
3639 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3640 }
3641 }
3642
3643 // ((OopHandle)result).resolve();
3644 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
3645 // OopHandle::resolve is an indirection.
3646 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT,
3647 result, Address(result, 0), tmp, noreg);
3648 }
3649
3650 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp) {
3651 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
3652 ldr(dst, Address(rmethod, Method::const_offset()));
3653 ldr(dst, Address(dst, ConstMethod::constants_offset()));
3654 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes()));
3655 ldr(dst, Address(dst, mirror_offset));
3656 resolve_oop_handle(dst, tmp);
3657 }
3658
3659 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3660 if (UseCompressedClassPointers) {
3661 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3662 if (Universe::narrow_klass_base() == NULL) {
3663 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3664 return;
3665 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3666 && Universe::narrow_klass_shift() == 0) {
3667 // Only the bottom 32 bits matter
3668 cmpw(trial_klass, tmp);
3669 return;
3670 }
3671 decode_klass_not_null(tmp);
3672 } else {
3673 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3674 }
3675 cmp(trial_klass, tmp);
3676 }
3677
3678 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3679 load_klass(dst, src);
3680 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3681 }
3682
3683 void MacroAssembler::store_klass(Register dst, Register src) {
3684 // FIXME: Should this be a store release? concurrent gcs assumes
3685 // klass length is valid if klass field is not null.
3686 if (UseCompressedClassPointers) {
3687 encode_klass_not_null(src);
3688 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3689 } else {
3690 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3691 }
3692 }
3693
3694 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3695 if (UseCompressedClassPointers) {
3696 // Store to klass gap in destination
3697 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3698 }
3699 }
3700
3701 // Algorithm must match CompressedOops::encode.
3702 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3703 #ifdef ASSERT
3704 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3705 #endif
3706 verify_oop(s, "broken oop in encode_heap_oop");
3707 if (Universe::narrow_oop_base() == NULL) {
3708 if (Universe::narrow_oop_shift() != 0) {
3709 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3710 lsr(d, s, LogMinObjAlignmentInBytes);
3711 } else {
3712 mov(d, s);
3713 }
3714 } else {
3715 subs(d, s, rheapbase);
3716 csel(d, d, zr, Assembler::HS);
3717 lsr(d, d, LogMinObjAlignmentInBytes);
3718
3719 /* Old algorithm: is this any worse?
3720 Label nonnull;
3721 cbnz(r, nonnull);
3722 sub(r, r, rheapbase);
3723 bind(nonnull);
3724 lsr(r, r, LogMinObjAlignmentInBytes);
3725 */
3726 }
3727 }
3728
3729 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3730 #ifdef ASSERT
3731 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3732 if (CheckCompressedOops) {
3733 Label ok;
3734 cbnz(r, ok);
3735 stop("null oop passed to encode_heap_oop_not_null");
3736 bind(ok);
3737 }
3738 #endif
3739 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3740 if (Universe::narrow_oop_base() != NULL) {
3741 sub(r, r, rheapbase);
3742 }
3743 if (Universe::narrow_oop_shift() != 0) {
3744 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3745 lsr(r, r, LogMinObjAlignmentInBytes);
3746 }
3747 }
3748
3749 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3750 #ifdef ASSERT
3751 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3752 if (CheckCompressedOops) {
3753 Label ok;
3754 cbnz(src, ok);
3755 stop("null oop passed to encode_heap_oop_not_null2");
3756 bind(ok);
3757 }
3758 #endif
3759 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3760
3761 Register data = src;
3762 if (Universe::narrow_oop_base() != NULL) {
3763 sub(dst, src, rheapbase);
3764 data = dst;
3765 }
3766 if (Universe::narrow_oop_shift() != 0) {
3767 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3768 lsr(dst, data, LogMinObjAlignmentInBytes);
3769 data = dst;
3770 }
3771 if (data == src)
3772 mov(dst, src);
3773 }
3774
3775 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3776 #ifdef ASSERT
3777 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3778 #endif
3779 if (Universe::narrow_oop_base() == NULL) {
3780 if (Universe::narrow_oop_shift() != 0 || d != s) {
3781 lsl(d, s, Universe::narrow_oop_shift());
3782 }
3783 } else {
3784 Label done;
3785 if (d != s)
3786 mov(d, s);
3787 cbz(s, done);
3788 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3789 bind(done);
3790 }
3791 verify_oop(d, "broken oop in decode_heap_oop");
3792 }
3793
3794 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3795 assert (UseCompressedOops, "should only be used for compressed headers");
3796 assert (Universe::heap() != NULL, "java heap should be initialized");
3797 // Cannot assert, unverified entry point counts instructions (see .ad file)
3798 // vtableStubs also counts instructions in pd_code_size_limit.
3799 // Also do not verify_oop as this is called by verify_oop.
3800 if (Universe::narrow_oop_shift() != 0) {
3801 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3802 if (Universe::narrow_oop_base() != NULL) {
3803 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3804 } else {
3805 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3806 }
3807 } else {
3808 assert (Universe::narrow_oop_base() == NULL, "sanity");
3809 }
3810 }
3811
3812 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3813 assert (UseCompressedOops, "should only be used for compressed headers");
3814 assert (Universe::heap() != NULL, "java heap should be initialized");
3815 // Cannot assert, unverified entry point counts instructions (see .ad file)
3816 // vtableStubs also counts instructions in pd_code_size_limit.
3817 // Also do not verify_oop as this is called by verify_oop.
3818 if (Universe::narrow_oop_shift() != 0) {
3819 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3820 if (Universe::narrow_oop_base() != NULL) {
3821 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3822 } else {
3823 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3824 }
3825 } else {
3826 assert (Universe::narrow_oop_base() == NULL, "sanity");
3827 if (dst != src) {
3828 mov(dst, src);
3829 }
3830 }
3831 }
3832
3833 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3834 if (Universe::narrow_klass_base() == NULL) {
3835 if (Universe::narrow_klass_shift() != 0) {
3836 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3837 lsr(dst, src, LogKlassAlignmentInBytes);
3838 } else {
3839 if (dst != src) mov(dst, src);
3840 }
3841 return;
3842 }
3843
3844 if (use_XOR_for_compressed_class_base) {
3845 if (Universe::narrow_klass_shift() != 0) {
3846 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3847 lsr(dst, dst, LogKlassAlignmentInBytes);
3848 } else {
3849 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3850 }
3851 return;
3852 }
3853
3854 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3855 && Universe::narrow_klass_shift() == 0) {
3856 movw(dst, src);
3857 return;
3858 }
3859
3860 #ifdef ASSERT
3861 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3862 #endif
3863
3864 Register rbase = dst;
3865 if (dst == src) rbase = rheapbase;
3866 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3867 sub(dst, src, rbase);
3868 if (Universe::narrow_klass_shift() != 0) {
3869 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3870 lsr(dst, dst, LogKlassAlignmentInBytes);
3871 }
3872 if (dst == src) reinit_heapbase();
3873 }
3874
3875 void MacroAssembler::encode_klass_not_null(Register r) {
3876 encode_klass_not_null(r, r);
3877 }
3878
3879 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3880 Register rbase = dst;
3881 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3882
3883 if (Universe::narrow_klass_base() == NULL) {
3884 if (Universe::narrow_klass_shift() != 0) {
3885 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3886 lsl(dst, src, LogKlassAlignmentInBytes);
3887 } else {
3888 if (dst != src) mov(dst, src);
3889 }
3890 return;
3891 }
3892
3893 if (use_XOR_for_compressed_class_base) {
3894 if (Universe::narrow_klass_shift() != 0) {
3895 lsl(dst, src, LogKlassAlignmentInBytes);
3896 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3897 } else {
3898 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3899 }
3900 return;
3901 }
3902
3903 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3904 && Universe::narrow_klass_shift() == 0) {
3905 if (dst != src)
3906 movw(dst, src);
3907 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3908 return;
3909 }
3910
3911 // Cannot assert, unverified entry point counts instructions (see .ad file)
3912 // vtableStubs also counts instructions in pd_code_size_limit.
3913 // Also do not verify_oop as this is called by verify_oop.
3914 if (dst == src) rbase = rheapbase;
3915 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3916 if (Universe::narrow_klass_shift() != 0) {
3917 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3918 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3919 } else {
3920 add(dst, rbase, src);
3921 }
3922 if (dst == src) reinit_heapbase();
3923 }
3924
3925 void MacroAssembler::decode_klass_not_null(Register r) {
3926 decode_klass_not_null(r, r);
3927 }
3928
3929 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3930 #ifdef ASSERT
3931 {
3932 ThreadInVMfromUnknown tiv;
3933 assert (UseCompressedOops, "should only be used for compressed oops");
3934 assert (Universe::heap() != NULL, "java heap should be initialized");
3935 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3936 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3937 }
3938 #endif
3939 int oop_index = oop_recorder()->find_index(obj);
3940 InstructionMark im(this);
3941 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3942 code_section()->relocate(inst_mark(), rspec);
3943 movz(dst, 0xDEAD, 16);
3944 movk(dst, 0xBEEF);
3945 }
3946
3947 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3948 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3949 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3950 int index = oop_recorder()->find_index(k);
3951 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3952
3953 InstructionMark im(this);
3954 RelocationHolder rspec = metadata_Relocation::spec(index);
3955 code_section()->relocate(inst_mark(), rspec);
3956 narrowKlass nk = Klass::encode_klass(k);
3957 movz(dst, (nk >> 16), 16);
3958 movk(dst, nk & 0xffff);
3959 }
3960
3961 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
3962 Register dst, Address src,
3963 Register tmp1, Register thread_tmp) {
3964 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
3965 decorators = AccessInternal::decorator_fixup(decorators);
3966 bool as_raw = (decorators & AS_RAW) != 0;
3967 if (as_raw) {
3968 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3969 } else {
3970 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3971 }
3972 }
3973
3974 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
3975 Address dst, Register src,
3976 Register tmp1, Register thread_tmp) {
3977 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
3978 decorators = AccessInternal::decorator_fixup(decorators);
3979 bool as_raw = (decorators & AS_RAW) != 0;
3980 if (as_raw) {
3981 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3982 } else {
3983 bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
3984 }
3985 }
3986
3987 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
3988 Register thread_tmp, DecoratorSet decorators) {
3989 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
3990 }
3991
3992 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
3993 Register thread_tmp, DecoratorSet decorators) {
3994 access_load_at(T_OBJECT, IN_HEAP | OOP_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
3995 }
3996
3997 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
3998 Register thread_tmp, DecoratorSet decorators) {
3999 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4000 }
4001
4002 // Used for storing NULLs.
4003 void MacroAssembler::store_heap_oop_null(Address dst) {
4004 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4005 }
4006
4007 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
4008 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
4009 int index = oop_recorder()->allocate_metadata_index(obj);
4010 RelocationHolder rspec = metadata_Relocation::spec(index);
4011 return Address((address)obj, rspec);
4012 }
4013
4014 // Move an oop into a register. immediate is true if we want
4015 // immediate instrcutions, i.e. we are not going to patch this
4016 // instruction while the code is being executed by another thread. In
4017 // that case we can use move immediates rather than the constant pool.
4018 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
4019 int oop_index;
4020 if (obj == NULL) {
4021 oop_index = oop_recorder()->allocate_oop_index(obj);
4022 } else {
4023 #ifdef ASSERT
4024 {
4025 ThreadInVMfromUnknown tiv;
4026 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
4027 }
4028 #endif
4029 oop_index = oop_recorder()->find_index(obj);
4030 }
4031 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4032 if (! immediate) {
4033 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
4034 ldr_constant(dst, Address(dummy, rspec));
4035 } else
4036 mov(dst, Address((address)obj, rspec));
4037 }
4038
4039 // Move a metadata address into a register.
4040 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
4041 int oop_index;
4042 if (obj == NULL) {
4043 oop_index = oop_recorder()->allocate_metadata_index(obj);
4044 } else {
4045 oop_index = oop_recorder()->find_index(obj);
4046 }
4047 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4048 mov(dst, Address((address)obj, rspec));
4049 }
4050
4051 Address MacroAssembler::constant_oop_address(jobject obj) {
4052 #ifdef ASSERT
4053 {
4054 ThreadInVMfromUnknown tiv;
4055 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4056 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
4057 }
4058 #endif
4059 int oop_index = oop_recorder()->find_index(obj);
4060 return Address((address)obj, oop_Relocation::spec(oop_index));
4061 }
4062
4063 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4064 void MacroAssembler::tlab_allocate(Register obj,
4065 Register var_size_in_bytes,
4066 int con_size_in_bytes,
4067 Register t1,
4068 Register t2,
4069 Label& slow_case) {
4070 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4071 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4072 }
4073
4074 // Defines obj, preserves var_size_in_bytes
4075 void MacroAssembler::eden_allocate(Register obj,
4076 Register var_size_in_bytes,
4077 int con_size_in_bytes,
4078 Register t1,
4079 Label& slow_case) {
4080 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4081 bs->eden_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4082 }
4083
4084 // Zero words; len is in bytes
4085 // Destroys all registers except addr
4086 // len must be a nonzero multiple of wordSize
4087 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) {
4088 assert_different_registers(addr, len, t1, rscratch1, rscratch2);
4089
4090 #ifdef ASSERT
4091 { Label L;
4092 tst(len, BytesPerWord - 1);
4093 br(Assembler::EQ, L);
4094 stop("len is not a multiple of BytesPerWord");
4095 bind(L);
4096 }
4097 #endif
4098
4099 #ifndef PRODUCT
4100 block_comment("zero memory");
4101 #endif
4102
4103 Label loop;
4104 Label entry;
4105
4106 // Algorithm:
4107 //
4108 // scratch1 = cnt & 7;
4109 // cnt -= scratch1;
4110 // p += scratch1;
4111 // switch (scratch1) {
4112 // do {
4113 // cnt -= 8;
4114 // p[-8] = 0;
4115 // case 7:
4116 // p[-7] = 0;
4117 // case 6:
4118 // p[-6] = 0;
4119 // // ...
4120 // case 1:
4121 // p[-1] = 0;
4122 // case 0:
4123 // p += 8;
4124 // } while (cnt);
4125 // }
4126
4127 const int unroll = 8; // Number of str(zr) instructions we'll unroll
4128
4129 lsr(len, len, LogBytesPerWord);
4130 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll
4131 sub(len, len, rscratch1); // cnt -= unroll
4132 // t1 always points to the end of the region we're about to zero
4133 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord);
4134 adr(rscratch2, entry);
4135 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2);
4136 br(rscratch2);
4137 bind(loop);
4138 sub(len, len, unroll);
4139 for (int i = -unroll; i < 0; i++)
4140 Assembler::str(zr, Address(t1, i * wordSize));
4141 bind(entry);
4142 add(t1, t1, unroll * wordSize);
4143 cbnz(len, loop);
4144 }
4145
4146 void MacroAssembler::verify_tlab() {
4147 #ifdef ASSERT
4148 if (UseTLAB && VerifyOops) {
4149 Label next, ok;
4150
4151 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4152
4153 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4154 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4155 cmp(rscratch2, rscratch1);
4156 br(Assembler::HS, next);
4157 STOP("assert(top >= start)");
4158 should_not_reach_here();
4159
4160 bind(next);
4161 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4162 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4163 cmp(rscratch2, rscratch1);
4164 br(Assembler::HS, ok);
4165 STOP("assert(top <= end)");
4166 should_not_reach_here();
4167
4168 bind(ok);
4169 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4170 }
4171 #endif
4172 }
4173
4174 // Writes to stack successive pages until offset reached to check for
4175 // stack overflow + shadow pages. This clobbers tmp.
4176 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4177 assert_different_registers(tmp, size, rscratch1);
4178 mov(tmp, sp);
4179 // Bang stack for total size given plus shadow page size.
4180 // Bang one page at a time because large size can bang beyond yellow and
4181 // red zones.
4182 Label loop;
4183 mov(rscratch1, os::vm_page_size());
4184 bind(loop);
4185 lea(tmp, Address(tmp, -os::vm_page_size()));
4186 subsw(size, size, rscratch1);
4187 str(size, Address(tmp));
4188 br(Assembler::GT, loop);
4189
4190 // Bang down shadow pages too.
4191 // At this point, (tmp-0) is the last address touched, so don't
4192 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4193 // was post-decremented.) Skip this address by starting at i=1, and
4194 // touch a few more pages below. N.B. It is important to touch all
4195 // the way down to and including i=StackShadowPages.
4196 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
4197 // this could be any sized move but this is can be a debugging crumb
4198 // so the bigger the better.
4199 lea(tmp, Address(tmp, -os::vm_page_size()));
4200 str(size, Address(tmp));
4201 }
4202 }
4203
4204
4205 // Move the address of the polling page into dest.
4206 void MacroAssembler::get_polling_page(Register dest, address page, relocInfo::relocType rtype) {
4207 if (SafepointMechanism::uses_thread_local_poll()) {
4208 ldr(dest, Address(rthread, Thread::polling_page_offset()));
4209 } else {
4210 unsigned long off;
4211 adrp(dest, Address(page, rtype), off);
4212 assert(off == 0, "polling page must be page aligned");
4213 }
4214 }
4215
4216 // Move the address of the polling page into r, then read the polling
4217 // page.
4218 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
4219 get_polling_page(r, page, rtype);
4220 return read_polling_page(r, rtype);
4221 }
4222
4223 // Read the polling page. The address of the polling page must
4224 // already be in r.
4225 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
4226 InstructionMark im(this);
4227 code_section()->relocate(inst_mark(), rtype);
4228 ldrw(zr, Address(r, 0));
4229 return inst_mark();
4230 }
4231
4232 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
4233 relocInfo::relocType rtype = dest.rspec().reloc()->type();
4234 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
4235 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
4236 unsigned long dest_page = (unsigned long)dest.target() >> 12;
4237 long offset_low = dest_page - low_page;
4238 long offset_high = dest_page - high_page;
4239
4240 assert(is_valid_AArch64_address(dest.target()), "bad address");
4241 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
4242
4243 InstructionMark im(this);
4244 code_section()->relocate(inst_mark(), dest.rspec());
4245 // 8143067: Ensure that the adrp can reach the dest from anywhere within
4246 // the code cache so that if it is relocated we know it will still reach
4247 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
4248 _adrp(reg1, dest.target());
4249 } else {
4250 unsigned long target = (unsigned long)dest.target();
4251 unsigned long adrp_target
4252 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
4253
4254 _adrp(reg1, (address)adrp_target);
4255 movk(reg1, target >> 32, 32);
4256 }
4257 byte_offset = (unsigned long)dest.target() & 0xfff;
4258 }
4259
4260 void MacroAssembler::load_byte_map_base(Register reg) {
4261 jbyte *byte_map_base =
4262 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
4263
4264 if (is_valid_AArch64_address((address)byte_map_base)) {
4265 // Strictly speaking the byte_map_base isn't an address at all,
4266 // and it might even be negative.
4267 unsigned long offset;
4268 adrp(reg, ExternalAddress((address)byte_map_base), offset);
4269 // We expect offset to be zero with most collectors.
4270 if (offset != 0) {
4271 add(reg, reg, offset);
4272 }
4273 } else {
4274 mov(reg, (uint64_t)byte_map_base);
4275 }
4276 }
4277
4278 void MacroAssembler::build_frame(int framesize) {
4279 assert(framesize > 0, "framesize must be > 0");
4280 if (framesize < ((1 << 9) + 2 * wordSize)) {
4281 sub(sp, sp, framesize);
4282 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4283 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4284 } else {
4285 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4286 if (PreserveFramePointer) mov(rfp, sp);
4287 if (framesize < ((1 << 12) + 2 * wordSize))
4288 sub(sp, sp, framesize - 2 * wordSize);
4289 else {
4290 mov(rscratch1, framesize - 2 * wordSize);
4291 sub(sp, sp, rscratch1);
4292 }
4293 }
4294 }
4295
4296 void MacroAssembler::remove_frame(int framesize) {
4297 assert(framesize > 0, "framesize must be > 0");
4298 if (framesize < ((1 << 9) + 2 * wordSize)) {
4299 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4300 add(sp, sp, framesize);
4301 } else {
4302 if (framesize < ((1 << 12) + 2 * wordSize))
4303 add(sp, sp, framesize - 2 * wordSize);
4304 else {
4305 mov(rscratch1, framesize - 2 * wordSize);
4306 add(sp, sp, rscratch1);
4307 }
4308 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4309 }
4310 }
4311
4312 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4313
4314 // Search for str1 in str2 and return index or -1
4315 void MacroAssembler::string_indexof(Register str2, Register str1,
4316 Register cnt2, Register cnt1,
4317 Register tmp1, Register tmp2,
4318 Register tmp3, Register tmp4,
4319 int icnt1, Register result, int ae) {
4320 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4321
4322 Register ch1 = rscratch1;
4323 Register ch2 = rscratch2;
4324 Register cnt1tmp = tmp1;
4325 Register cnt2tmp = tmp2;
4326 Register cnt1_neg = cnt1;
4327 Register cnt2_neg = cnt2;
4328 Register result_tmp = tmp4;
4329
4330 bool isL = ae == StrIntrinsicNode::LL;
4331
4332 bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL;
4333 bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU;
4334 int str1_chr_shift = str1_isL ? 0:1;
4335 int str2_chr_shift = str2_isL ? 0:1;
4336 int str1_chr_size = str1_isL ? 1:2;
4337 int str2_chr_size = str2_isL ? 1:2;
4338 chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4339 (chr_insn)&MacroAssembler::ldrh;
4340 chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4341 (chr_insn)&MacroAssembler::ldrh;
4342 chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw;
4343 chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr;
4344
4345 // Note, inline_string_indexOf() generates checks:
4346 // if (substr.count > string.count) return -1;
4347 // if (substr.count == 0) return 0;
4348
4349 // We have two strings, a source string in str2, cnt2 and a pattern string
4350 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4351
4352 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4353 // With a small pattern and source we use linear scan.
4354
4355 if (icnt1 == -1) {
4356 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4357 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4358 br(LO, LINEARSEARCH); // a byte array.
4359 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4360 br(HS, LINEARSEARCH);
4361 }
4362
4363 // The Boyer Moore alogorithm is based on the description here:-
4364 //
4365 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4366 //
4367 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4368 // and the 'Good Suffix' rule.
4369 //
4370 // These rules are essentially heuristics for how far we can shift the
4371 // pattern along the search string.
4372 //
4373 // The implementation here uses the 'Bad Character' rule only because of the
4374 // complexity of initialisation for the 'Good Suffix' rule.
4375 //
4376 // This is also known as the Boyer-Moore-Horspool algorithm:-
4377 //
4378 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4379 //
4380 // #define ASIZE 128
4381 //
4382 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4383 // int i, j;
4384 // unsigned c;
4385 // unsigned char bc[ASIZE];
4386 //
4387 // /* Preprocessing */
4388 // for (i = 0; i < ASIZE; ++i)
4389 // bc[i] = 0;
4390 // for (i = 0; i < m - 1; ) {
4391 // c = x[i];
4392 // ++i;
4393 // if (c < ASIZE) bc[c] = i;
4394 // }
4395 //
4396 // /* Searching */
4397 // j = 0;
4398 // while (j <= n - m) {
4399 // c = y[i+j];
4400 // if (x[m-1] == c)
4401 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4402 // if (i < 0) return j;
4403 // if (c < ASIZE)
4404 // j = j - bc[y[j+m-1]] + m;
4405 // else
4406 // j += 1; // Advance by 1 only if char >= ASIZE
4407 // }
4408 // }
4409
4410 if (icnt1 == -1) {
4411 BIND(BM);
4412
4413 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4414 Label BMADV, BMMATCH, BMCHECKEND;
4415
4416 Register cnt1end = tmp2;
4417 Register str2end = cnt2;
4418 Register skipch = tmp2;
4419
4420 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4421 // The presence of chars >= ASIZE in the target string does not affect
4422 // performance, but we must be careful not to initialise them in the stack
4423 // array.
4424 // The presence of chars >= ASIZE in the source string may adversely affect
4425 // performance since we can only advance by one when we encounter one.
4426
4427 stp(zr, zr, pre(sp, -128));
4428 for (int i = 1; i < 8; i++)
4429 stp(zr, zr, Address(sp, i*16));
4430
4431 mov(cnt1tmp, 0);
4432 sub(cnt1end, cnt1, 1);
4433 BIND(BCLOOP);
4434 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4435 cmp(ch1, 128);
4436 add(cnt1tmp, cnt1tmp, 1);
4437 br(HS, BCSKIP);
4438 strb(cnt1tmp, Address(sp, ch1));
4439 BIND(BCSKIP);
4440 cmp(cnt1tmp, cnt1end);
4441 br(LT, BCLOOP);
4442
4443 mov(result_tmp, str2);
4444
4445 sub(cnt2, cnt2, cnt1);
4446 add(str2end, str2, cnt2, LSL, str2_chr_shift);
4447 BIND(BMLOOPSTR2);
4448 sub(cnt1tmp, cnt1, 1);
4449 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4450 (this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4451 cmp(ch1, skipch);
4452 br(NE, BMSKIP);
4453 subs(cnt1tmp, cnt1tmp, 1);
4454 br(LT, BMMATCH);
4455 BIND(BMLOOPSTR1);
4456 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4457 (this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4458 cmp(ch1, ch2);
4459 br(NE, BMSKIP);
4460 subs(cnt1tmp, cnt1tmp, 1);
4461 br(GE, BMLOOPSTR1);
4462 BIND(BMMATCH);
4463 sub(result, str2, result_tmp);
4464 if (!str2_isL) lsr(result, result, 1);
4465 add(sp, sp, 128);
4466 b(DONE);
4467 BIND(BMADV);
4468 add(str2, str2, str2_chr_size);
4469 b(BMCHECKEND);
4470 BIND(BMSKIP);
4471 cmp(skipch, 128);
4472 br(HS, BMADV);
4473 ldrb(ch2, Address(sp, skipch));
4474 add(str2, str2, cnt1, LSL, str2_chr_shift);
4475 sub(str2, str2, ch2, LSL, str2_chr_shift);
4476 BIND(BMCHECKEND);
4477 cmp(str2, str2end);
4478 br(LE, BMLOOPSTR2);
4479 add(sp, sp, 128);
4480 b(NOMATCH);
4481 }
4482
4483 BIND(LINEARSEARCH);
4484 {
4485 Label DO1, DO2, DO3;
4486
4487 Register str2tmp = tmp2;
4488 Register first = tmp3;
4489
4490 if (icnt1 == -1)
4491 {
4492 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT;
4493
4494 cmp(cnt1, str1_isL == str2_isL ? 4 : 2);
4495 br(LT, DOSHORT);
4496
4497 sub(cnt2, cnt2, cnt1);
4498 mov(result_tmp, cnt2);
4499
4500 lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift)));
4501 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4502 sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift);
4503 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4504 (this->*str1_load_1chr)(first, Address(str1, cnt1_neg));
4505
4506 BIND(FIRST_LOOP);
4507 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4508 cmp(first, ch2);
4509 br(EQ, STR1_LOOP);
4510 BIND(STR2_NEXT);
4511 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4512 br(LE, FIRST_LOOP);
4513 b(NOMATCH);
4514
4515 BIND(STR1_LOOP);
4516 adds(cnt1tmp, cnt1_neg, str1_chr_size);
4517 add(cnt2tmp, cnt2_neg, str2_chr_size);
4518 br(GE, MATCH);
4519
4520 BIND(STR1_NEXT);
4521 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp));
4522 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4523 cmp(ch1, ch2);
4524 br(NE, STR2_NEXT);
4525 adds(cnt1tmp, cnt1tmp, str1_chr_size);
4526 add(cnt2tmp, cnt2tmp, str2_chr_size);
4527 br(LT, STR1_NEXT);
4528 b(MATCH);
4529
4530 BIND(DOSHORT);
4531 if (str1_isL == str2_isL) {
4532 cmp(cnt1, 2);
4533 br(LT, DO1);
4534 br(GT, DO3);
4535 }
4536 }
4537
4538 if (icnt1 == 4) {
4539 Label CH1_LOOP;
4540
4541 (this->*load_4chr)(ch1, str1);
4542 sub(cnt2, cnt2, 4);
4543 mov(result_tmp, cnt2);
4544 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4545 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4546
4547 BIND(CH1_LOOP);
4548 (this->*load_4chr)(ch2, Address(str2, cnt2_neg));
4549 cmp(ch1, ch2);
4550 br(EQ, MATCH);
4551 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4552 br(LE, CH1_LOOP);
4553 b(NOMATCH);
4554 }
4555
4556 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) {
4557 Label CH1_LOOP;
4558
4559 BIND(DO2);
4560 (this->*load_2chr)(ch1, str1);
4561 sub(cnt2, cnt2, 2);
4562 mov(result_tmp, cnt2);
4563 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4564 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4565
4566 BIND(CH1_LOOP);
4567 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4568 cmp(ch1, ch2);
4569 br(EQ, MATCH);
4570 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4571 br(LE, CH1_LOOP);
4572 b(NOMATCH);
4573 }
4574
4575 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) {
4576 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4577
4578 BIND(DO3);
4579 (this->*load_2chr)(first, str1);
4580 (this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size));
4581
4582 sub(cnt2, cnt2, 3);
4583 mov(result_tmp, cnt2);
4584 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4585 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4586
4587 BIND(FIRST_LOOP);
4588 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4589 cmpw(first, ch2);
4590 br(EQ, STR1_LOOP);
4591 BIND(STR2_NEXT);
4592 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4593 br(LE, FIRST_LOOP);
4594 b(NOMATCH);
4595
4596 BIND(STR1_LOOP);
4597 add(cnt2tmp, cnt2_neg, 2*str2_chr_size);
4598 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4599 cmp(ch1, ch2);
4600 br(NE, STR2_NEXT);
4601 b(MATCH);
4602 }
4603
4604 if (icnt1 == -1 || icnt1 == 1) {
4605 Label CH1_LOOP, HAS_ZERO;
4606 Label DO1_SHORT, DO1_LOOP;
4607
4608 BIND(DO1);
4609 (this->*str1_load_1chr)(ch1, str1);
4610 cmp(cnt2, 8);
4611 br(LT, DO1_SHORT);
4612
4613 if (str2_isL) {
4614 if (!str1_isL) {
4615 tst(ch1, 0xff00);
4616 br(NE, NOMATCH);
4617 }
4618 orr(ch1, ch1, ch1, LSL, 8);
4619 }
4620 orr(ch1, ch1, ch1, LSL, 16);
4621 orr(ch1, ch1, ch1, LSL, 32);
4622
4623 sub(cnt2, cnt2, 8/str2_chr_size);
4624 mov(result_tmp, cnt2);
4625 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4626 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4627
4628 mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001);
4629 BIND(CH1_LOOP);
4630 ldr(ch2, Address(str2, cnt2_neg));
4631 eor(ch2, ch1, ch2);
4632 sub(tmp1, ch2, tmp3);
4633 orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
4634 bics(tmp1, tmp1, tmp2);
4635 br(NE, HAS_ZERO);
4636 adds(cnt2_neg, cnt2_neg, 8);
4637 br(LT, CH1_LOOP);
4638
4639 cmp(cnt2_neg, 8);
4640 mov(cnt2_neg, 0);
4641 br(LT, CH1_LOOP);
4642 b(NOMATCH);
4643
4644 BIND(HAS_ZERO);
4645 rev(tmp1, tmp1);
4646 clz(tmp1, tmp1);
4647 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4648 b(MATCH);
4649
4650 BIND(DO1_SHORT);
4651 mov(result_tmp, cnt2);
4652 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4653 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4654 BIND(DO1_LOOP);
4655 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4656 cmpw(ch1, ch2);
4657 br(EQ, MATCH);
4658 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4659 br(LT, DO1_LOOP);
4660 }
4661 }
4662 BIND(NOMATCH);
4663 mov(result, -1);
4664 b(DONE);
4665 BIND(MATCH);
4666 add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift);
4667 BIND(DONE);
4668 }
4669
4670 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4671 typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn);
4672
4673 void MacroAssembler::string_indexof_char(Register str1, Register cnt1,
4674 Register ch, Register result,
4675 Register tmp1, Register tmp2, Register tmp3)
4676 {
4677 Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE;
4678 Register cnt1_neg = cnt1;
4679 Register ch1 = rscratch1;
4680 Register result_tmp = rscratch2;
4681
4682 cmp(cnt1, 4);
4683 br(LT, DO1_SHORT);
4684
4685 orr(ch, ch, ch, LSL, 16);
4686 orr(ch, ch, ch, LSL, 32);
4687
4688 sub(cnt1, cnt1, 4);
4689 mov(result_tmp, cnt1);
4690 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4691 sub(cnt1_neg, zr, cnt1, LSL, 1);
4692
4693 mov(tmp3, 0x0001000100010001);
4694
4695 BIND(CH1_LOOP);
4696 ldr(ch1, Address(str1, cnt1_neg));
4697 eor(ch1, ch, ch1);
4698 sub(tmp1, ch1, tmp3);
4699 orr(tmp2, ch1, 0x7fff7fff7fff7fff);
4700 bics(tmp1, tmp1, tmp2);
4701 br(NE, HAS_ZERO);
4702 adds(cnt1_neg, cnt1_neg, 8);
4703 br(LT, CH1_LOOP);
4704
4705 cmp(cnt1_neg, 8);
4706 mov(cnt1_neg, 0);
4707 br(LT, CH1_LOOP);
4708 b(NOMATCH);
4709
4710 BIND(HAS_ZERO);
4711 rev(tmp1, tmp1);
4712 clz(tmp1, tmp1);
4713 add(cnt1_neg, cnt1_neg, tmp1, LSR, 3);
4714 b(MATCH);
4715
4716 BIND(DO1_SHORT);
4717 mov(result_tmp, cnt1);
4718 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4719 sub(cnt1_neg, zr, cnt1, LSL, 1);
4720 BIND(DO1_LOOP);
4721 ldrh(ch1, Address(str1, cnt1_neg));
4722 cmpw(ch, ch1);
4723 br(EQ, MATCH);
4724 adds(cnt1_neg, cnt1_neg, 2);
4725 br(LT, DO1_LOOP);
4726 BIND(NOMATCH);
4727 mov(result, -1);
4728 b(DONE);
4729 BIND(MATCH);
4730 add(result, result_tmp, cnt1_neg, ASR, 1);
4731 BIND(DONE);
4732 }
4733
4734 // Compare strings.
4735 void MacroAssembler::string_compare(Register str1, Register str2,
4736 Register cnt1, Register cnt2, Register result,
4737 Register tmp1,
4738 FloatRegister vtmp, FloatRegister vtmpZ, int ae) {
4739 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4740 NEXT_WORD, DIFFERENCE;
4741
4742 bool isLL = ae == StrIntrinsicNode::LL;
4743 bool isLU = ae == StrIntrinsicNode::LU;
4744 bool isUL = ae == StrIntrinsicNode::UL;
4745
4746 bool str1_isL = isLL || isLU;
4747 bool str2_isL = isLL || isUL;
4748
4749 int str1_chr_shift = str1_isL ? 0 : 1;
4750 int str2_chr_shift = str2_isL ? 0 : 1;
4751 int str1_chr_size = str1_isL ? 1 : 2;
4752 int str2_chr_size = str2_isL ? 1 : 2;
4753
4754 chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4755 (chr_insn)&MacroAssembler::ldrh;
4756 chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4757 (chr_insn)&MacroAssembler::ldrh;
4758 uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw :
4759 (uxt_insn)&MacroAssembler::uxthw;
4760
4761 BLOCK_COMMENT("string_compare {");
4762
4763 // Bizzarely, the counts are passed in bytes, regardless of whether they
4764 // are L or U strings, however the result is always in characters.
4765 if (!str1_isL) asrw(cnt1, cnt1, 1);
4766 if (!str2_isL) asrw(cnt2, cnt2, 1);
4767
4768 // Compute the minimum of the string lengths and save the difference.
4769 subsw(tmp1, cnt1, cnt2);
4770 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4771
4772 // A very short string
4773 cmpw(cnt2, isLL ? 8:4);
4774 br(Assembler::LT, SHORT_STRING);
4775
4776 // Check if the strings start at the same location.
4777 cmp(str1, str2);
4778 br(Assembler::EQ, LENGTH_DIFF);
4779
4780 // Compare longwords
4781 {
4782 subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case
4783
4784 // Move both string pointers to the last longword of their
4785 // strings, negate the remaining count, and convert it to bytes.
4786 lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift)));
4787 lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift)));
4788 if (isLU || isUL) {
4789 sub(cnt1, zr, cnt2, LSL, str1_chr_shift);
4790 eor(vtmpZ, T16B, vtmpZ, vtmpZ);
4791 }
4792 sub(cnt2, zr, cnt2, LSL, str2_chr_shift);
4793
4794 // Loop, loading longwords and comparing them into rscratch2.
4795 bind(NEXT_WORD);
4796 if (isLU) {
4797 ldrs(vtmp, Address(str1, cnt1));
4798 zip1(vtmp, T8B, vtmp, vtmpZ);
4799 umov(result, vtmp, D, 0);
4800 } else {
4801 ldr(result, Address(str1, isUL ? cnt1:cnt2));
4802 }
4803 if (isUL) {
4804 ldrs(vtmp, Address(str2, cnt2));
4805 zip1(vtmp, T8B, vtmp, vtmpZ);
4806 umov(rscratch1, vtmp, D, 0);
4807 } else {
4808 ldr(rscratch1, Address(str2, cnt2));
4809 }
4810 adds(cnt2, cnt2, isUL ? 4:8);
4811 if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8);
4812 eor(rscratch2, result, rscratch1);
4813 cbnz(rscratch2, DIFFERENCE);
4814 br(Assembler::LT, NEXT_WORD);
4815
4816 // Last longword. In the case where length == 4 we compare the
4817 // same longword twice, but that's still faster than another
4818 // conditional branch.
4819
4820 if (isLU) {
4821 ldrs(vtmp, Address(str1));
4822 zip1(vtmp, T8B, vtmp, vtmpZ);
4823 umov(result, vtmp, D, 0);
4824 } else {
4825 ldr(result, Address(str1));
4826 }
4827 if (isUL) {
4828 ldrs(vtmp, Address(str2));
4829 zip1(vtmp, T8B, vtmp, vtmpZ);
4830 umov(rscratch1, vtmp, D, 0);
4831 } else {
4832 ldr(rscratch1, Address(str2));
4833 }
4834 eor(rscratch2, result, rscratch1);
4835 cbz(rscratch2, LENGTH_DIFF);
4836
4837 // Find the first different characters in the longwords and
4838 // compute their difference.
4839 bind(DIFFERENCE);
4840 rev(rscratch2, rscratch2);
4841 clz(rscratch2, rscratch2);
4842 andr(rscratch2, rscratch2, isLL ? -8 : -16);
4843 lsrv(result, result, rscratch2);
4844 (this->*ext_chr)(result, result);
4845 lsrv(rscratch1, rscratch1, rscratch2);
4846 (this->*ext_chr)(rscratch1, rscratch1);
4847 subw(result, result, rscratch1);
4848 b(DONE);
4849 }
4850
4851 bind(SHORT_STRING);
4852 // Is the minimum length zero?
4853 cbz(cnt2, LENGTH_DIFF);
4854
4855 bind(SHORT_LOOP);
4856 (this->*str1_load_chr)(result, Address(post(str1, str1_chr_size)));
4857 (this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size)));
4858 subw(result, result, cnt1);
4859 cbnz(result, DONE);
4860 sub(cnt2, cnt2, 1);
4861 cbnz(cnt2, SHORT_LOOP);
4862
4863 // Strings are equal up to min length. Return the length difference.
4864 bind(LENGTH_DIFF);
4865 mov(result, tmp1);
4866
4867 // That's it
4868 bind(DONE);
4869
4870 BLOCK_COMMENT("} string_compare");
4871 }
4872
4873 // This method checks if provided byte array contains byte with highest bit set.
4874 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) {
4875 // Simple and most common case of aligned small array which is not at the
4876 // end of memory page is placed here. All other cases are in stub.
4877 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4878 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4879 assert_different_registers(ary1, len, result);
4880
4881 cmpw(len, 0);
4882 br(LE, SET_RESULT);
4883 cmpw(len, 4 * wordSize);
4884 br(GE, STUB_LONG); // size > 32 then go to stub
4885
4886 int shift = 64 - exact_log2(os::vm_page_size());
4887 lsl(rscratch1, ary1, shift);
4888 mov(rscratch2, (size_t)(4 * wordSize) << shift);
4889 adds(rscratch2, rscratch1, rscratch2); // At end of page?
4890 br(CS, STUB); // at the end of page then go to stub
4891 subs(len, len, wordSize);
4892 br(LT, END);
4893
4894 BIND(LOOP);
4895 ldr(rscratch1, Address(post(ary1, wordSize)));
4896 tst(rscratch1, UPPER_BIT_MASK);
4897 br(NE, SET_RESULT);
4898 subs(len, len, wordSize);
4899 br(GE, LOOP);
4900 cmpw(len, -wordSize);
4901 br(EQ, SET_RESULT);
4902
4903 BIND(END);
4904 ldr(result, Address(ary1));
4905 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
4906 lslv(result, result, len);
4907 tst(result, UPPER_BIT_MASK);
4908 b(SET_RESULT);
4909
4910 BIND(STUB);
4911 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives());
4912 assert(has_neg.target() != NULL, "has_negatives stub has not been generated");
4913 trampoline_call(has_neg);
4914 b(DONE);
4915
4916 BIND(STUB_LONG);
4917 RuntimeAddress has_neg_long = RuntimeAddress(
4918 StubRoutines::aarch64::has_negatives_long());
4919 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated");
4920 trampoline_call(has_neg_long);
4921 b(DONE);
4922
4923 BIND(SET_RESULT);
4924 cset(result, NE); // set true or false
4925
4926 BIND(DONE);
4927 }
4928
4929 void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
4930 Register tmp4, Register tmp5, Register result,
4931 Register cnt1, int elem_size)
4932 {
4933 Label DONE;
4934 Register tmp1 = rscratch1;
4935 Register tmp2 = rscratch2;
4936 Register cnt2 = tmp2; // cnt2 only used in array length compare
4937 int elem_per_word = wordSize/elem_size;
4938 int log_elem_size = exact_log2(elem_size);
4939 int length_offset = arrayOopDesc::length_offset_in_bytes();
4940 int base_offset
4941 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
4942 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
4943
4944 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
4945 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
4946
4947 #ifndef PRODUCT
4948 {
4949 const char kind = (elem_size == 2) ? 'U' : 'L';
4950 char comment[64];
4951 snprintf(comment, sizeof comment, "array_equals%c{", kind);
4952 BLOCK_COMMENT(comment);
4953 }
4954 #endif
4955 if (UseSimpleArrayEquals) {
4956 Label NEXT_WORD, SHORT, SAME, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
4957 // if (a1==a2)
4958 // return true;
4959 // if (a==null || a2==null)
4960 // return false;
4961 // a1 & a2 == 0 means (some-pointer is null) or
4962 // (very-rare-or-even-probably-impossible-pointer-values)
4963 // so, we can save one branch in most cases
4964 cmpoop(a1, a2);
4965 br(EQ, SAME);
4966 eor(rscratch1, a1, a2);
4967 tst(a1, a2);
4968 mov(result, false);
4969 cbz(rscratch1, SAME);
4970 br(EQ, A_MIGHT_BE_NULL);
4971 // if (a1.length != a2.length)
4972 // return false;
4973 bind(A_IS_NOT_NULL);
4974 ldrw(cnt1, Address(a1, length_offset));
4975 ldrw(cnt2, Address(a2, length_offset));
4976 eorw(tmp5, cnt1, cnt2);
4977 cbnzw(tmp5, DONE);
4978 lea(a1, Address(a1, base_offset));
4979 lea(a2, Address(a2, base_offset));
4980 // Check for short strings, i.e. smaller than wordSize.
4981 subs(cnt1, cnt1, elem_per_word);
4982 br(Assembler::LT, SHORT);
4983 // Main 8 byte comparison loop.
4984 bind(NEXT_WORD); {
4985 ldr(tmp1, Address(post(a1, wordSize)));
4986 ldr(tmp2, Address(post(a2, wordSize)));
4987 subs(cnt1, cnt1, elem_per_word);
4988 eor(tmp5, tmp1, tmp2);
4989 cbnz(tmp5, DONE);
4990 } br(GT, NEXT_WORD);
4991 // Last longword. In the case where length == 4 we compare the
4992 // same longword twice, but that's still faster than another
4993 // conditional branch.
4994 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
4995 // length == 4.
4996 if (log_elem_size > 0)
4997 lsl(cnt1, cnt1, log_elem_size);
4998 ldr(tmp3, Address(a1, cnt1));
4999 ldr(tmp4, Address(a2, cnt1));
5000 eor(tmp5, tmp3, tmp4);
5001 cbnz(tmp5, DONE);
5002 b(SAME);
5003 bind(A_MIGHT_BE_NULL);
5004 // in case both a1 and a2 are not-null, proceed with loads
5005 cbz(a1, DONE);
5006 cbz(a2, DONE);
5007 b(A_IS_NOT_NULL);
5008 bind(SHORT);
5009
5010 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5011 {
5012 ldrw(tmp1, Address(post(a1, 4)));
5013 ldrw(tmp2, Address(post(a2, 4)));
5014 eorw(tmp5, tmp1, tmp2);
5015 cbnzw(tmp5, DONE);
5016 }
5017 bind(TAIL03);
5018 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5019 {
5020 ldrh(tmp3, Address(post(a1, 2)));
5021 ldrh(tmp4, Address(post(a2, 2)));
5022 eorw(tmp5, tmp3, tmp4);
5023 cbnzw(tmp5, DONE);
5024 }
5025 bind(TAIL01);
5026 if (elem_size == 1) { // Only needed when comparing byte arrays.
5027 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5028 {
5029 ldrb(tmp1, a1);
5030 ldrb(tmp2, a2);
5031 eorw(tmp5, tmp1, tmp2);
5032 cbnzw(tmp5, DONE);
5033 }
5034 }
5035 bind(SAME);
5036 mov(result, true);
5037 } else {
5038 Label NEXT_DWORD, A_IS_NULL, SHORT, TAIL, TAIL2, STUB, EARLY_OUT,
5039 CSET_EQ, LAST_CHECK, LEN_IS_ZERO, SAME;
5040 cbz(a1, A_IS_NULL);
5041 ldrw(cnt1, Address(a1, length_offset));
5042 cbz(a2, A_IS_NULL);
5043 ldrw(cnt2, Address(a2, length_offset));
5044 mov(result, false);
5045 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5046 // faster to perform another branch before comparing a1 and a2
5047 cmp(cnt1, elem_per_word);
5048 br(LE, SHORT); // short or same
5049 cmpoop(a1, a2);
5050 br(EQ, SAME);
5051 ldr(tmp3, Address(pre(a1, base_offset)));
5052 cmp(cnt1, stubBytesThreshold);
5053 br(GE, STUB);
5054 ldr(tmp4, Address(pre(a2, base_offset)));
5055 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5056 cmp(cnt2, cnt1);
5057 br(NE, DONE);
5058
5059 // Main 16 byte comparison loop with 2 exits
5060 bind(NEXT_DWORD); {
5061 ldr(tmp1, Address(pre(a1, wordSize)));
5062 ldr(tmp2, Address(pre(a2, wordSize)));
5063 subs(cnt1, cnt1, 2 * elem_per_word);
5064 br(LE, TAIL);
5065 eor(tmp4, tmp3, tmp4);
5066 cbnz(tmp4, DONE);
5067 ldr(tmp3, Address(pre(a1, wordSize)));
5068 ldr(tmp4, Address(pre(a2, wordSize)));
5069 cmp(cnt1, elem_per_word);
5070 br(LE, TAIL2);
5071 cmp(tmp1, tmp2);
5072 } br(EQ, NEXT_DWORD);
5073 b(DONE);
5074
5075 bind(TAIL);
5076 eor(tmp4, tmp3, tmp4);
5077 eor(tmp2, tmp1, tmp2);
5078 lslv(tmp2, tmp2, tmp5);
5079 orr(tmp5, tmp4, tmp2);
5080 cmp(tmp5, zr);
5081 b(CSET_EQ);
5082
5083 bind(TAIL2);
5084 eor(tmp2, tmp1, tmp2);
5085 cbnz(tmp2, DONE);
5086 b(LAST_CHECK);
5087
5088 bind(STUB);
5089 ldr(tmp4, Address(pre(a2, base_offset)));
5090 cmp(cnt2, cnt1);
5091 br(NE, DONE);
5092 if (elem_size == 2) { // convert to byte counter
5093 lsl(cnt1, cnt1, 1);
5094 }
5095 eor(tmp5, tmp3, tmp4);
5096 cbnz(tmp5, DONE);
5097 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5098 assert(stub.target() != NULL, "array_equals_long stub has not been generated");
5099 trampoline_call(stub);
5100 b(DONE);
5101
5102 bind(SAME);
5103 mov(result, true);
5104 b(DONE);
5105 bind(A_IS_NULL);
5106 // a1 or a2 is null. if a2 == a2 then return true. else return false
5107 cmp(a1, a2);
5108 b(CSET_EQ);
5109 bind(EARLY_OUT);
5110 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5111 // so, if a2 == null => return false(0), else return true, so we can return a2
5112 mov(result, a2);
5113 b(DONE);
5114 bind(LEN_IS_ZERO);
5115 cmp(cnt2, zr);
5116 b(CSET_EQ);
5117 bind(SHORT);
5118 cbz(cnt1, LEN_IS_ZERO);
5119 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5120 ldr(tmp3, Address(a1, base_offset));
5121 ldr(tmp4, Address(a2, base_offset));
5122 bind(LAST_CHECK);
5123 eor(tmp4, tmp3, tmp4);
5124 lslv(tmp5, tmp4, tmp5);
5125 cmp(tmp5, zr);
5126 bind(CSET_EQ);
5127 cset(result, EQ);
5128 }
5129
5130 // That's it.
5131 bind(DONE);
5132
5133 BLOCK_COMMENT("} array_equals");
5134 }
5135
5136 // Compare Strings
5137
5138 // For Strings we're passed the address of the first characters in a1
5139 // and a2 and the length in cnt1.
5140 // elem_size is the element size in bytes: either 1 or 2.
5141 // There are two implementations. For arrays >= 8 bytes, all
5142 // comparisons (including the final one, which may overlap) are
5143 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5144 // halfword, then a short, and then a byte.
5145
5146 void MacroAssembler::string_equals(Register a1, Register a2,
5147 Register result, Register cnt1, int elem_size)
5148 {
5149 Label SAME, DONE, SHORT, NEXT_WORD;
5150 Register tmp1 = rscratch1;
5151 Register tmp2 = rscratch2;
5152 Register cnt2 = tmp2; // cnt2 only used in array length compare
5153
5154 assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte");
5155 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5156
5157 #ifndef PRODUCT
5158 {
5159 const char kind = (elem_size == 2) ? 'U' : 'L';
5160 char comment[64];
5161 snprintf(comment, sizeof comment, "{string_equals%c", kind);
5162 BLOCK_COMMENT(comment);
5163 }
5164 #endif
5165
5166 mov(result, false);
5167
5168 // Check for short strings, i.e. smaller than wordSize.
5169 subs(cnt1, cnt1, wordSize);
5170 br(Assembler::LT, SHORT);
5171 // Main 8 byte comparison loop.
5172 bind(NEXT_WORD); {
5173 ldr(tmp1, Address(post(a1, wordSize)));
5174 ldr(tmp2, Address(post(a2, wordSize)));
5175 subs(cnt1, cnt1, wordSize);
5176 eor(tmp1, tmp1, tmp2);
5177 cbnz(tmp1, DONE);
5178 } br(GT, NEXT_WORD);
5179 // Last longword. In the case where length == 4 we compare the
5180 // same longword twice, but that's still faster than another
5181 // conditional branch.
5182 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5183 // length == 4.
5184 ldr(tmp1, Address(a1, cnt1));
5185 ldr(tmp2, Address(a2, cnt1));
5186 eor(tmp2, tmp1, tmp2);
5187 cbnz(tmp2, DONE);
5188 b(SAME);
5189
5190 bind(SHORT);
5191 Label TAIL03, TAIL01;
5192
5193 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
5194 {
5195 ldrw(tmp1, Address(post(a1, 4)));
5196 ldrw(tmp2, Address(post(a2, 4)));
5197 eorw(tmp1, tmp1, tmp2);
5198 cbnzw(tmp1, DONE);
5199 }
5200 bind(TAIL03);
5201 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
5202 {
5203 ldrh(tmp1, Address(post(a1, 2)));
5204 ldrh(tmp2, Address(post(a2, 2)));
5205 eorw(tmp1, tmp1, tmp2);
5206 cbnzw(tmp1, DONE);
5207 }
5208 bind(TAIL01);
5209 if (elem_size == 1) { // Only needed when comparing 1-byte elements
5210 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5211 {
5212 ldrb(tmp1, a1);
5213 ldrb(tmp2, a2);
5214 eorw(tmp1, tmp1, tmp2);
5215 cbnzw(tmp1, DONE);
5216 }
5217 }
5218 // Arrays are equal.
5219 bind(SAME);
5220 mov(result, true);
5221
5222 // That's it.
5223 bind(DONE);
5224 BLOCK_COMMENT("} string_equals");
5225 }
5226
5227
5228 // The size of the blocks erased by the zero_blocks stub. We must
5229 // handle anything smaller than this ourselves in zero_words().
5230 const int MacroAssembler::zero_words_block_size = 8;
5231
5232 // zero_words() is used by C2 ClearArray patterns. It is as small as
5233 // possible, handling small word counts locally and delegating
5234 // anything larger to the zero_blocks stub. It is expanded many times
5235 // in compiled code, so it is important to keep it short.
5236
5237 // ptr: Address of a buffer to be zeroed.
5238 // cnt: Count in HeapWords.
5239 //
5240 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
5241 void MacroAssembler::zero_words(Register ptr, Register cnt)
5242 {
5243 assert(is_power_of_2(zero_words_block_size), "adjust this");
5244 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
5245
5246 BLOCK_COMMENT("zero_words {");
5247 cmp(cnt, zero_words_block_size);
5248 Label around, done, done16;
5249 br(LO, around);
5250 {
5251 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5252 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated");
5253 if (StubRoutines::aarch64::complete()) {
5254 trampoline_call(zero_blocks);
5255 } else {
5256 bl(zero_blocks);
5257 }
5258 }
5259 bind(around);
5260 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
5261 Label l;
5262 tbz(cnt, exact_log2(i), l);
5263 for (int j = 0; j < i; j += 2) {
5264 stp(zr, zr, post(ptr, 16));
5265 }
5266 bind(l);
5267 }
5268 {
5269 Label l;
5270 tbz(cnt, 0, l);
5271 str(zr, Address(ptr));
5272 bind(l);
5273 }
5274 BLOCK_COMMENT("} zero_words");
5275 }
5276
5277 // base: Address of a buffer to be zeroed, 8 bytes aligned.
5278 // cnt: Immediate count in HeapWords.
5279 #define SmallArraySize (18 * BytesPerLong)
5280 void MacroAssembler::zero_words(Register base, u_int64_t cnt)
5281 {
5282 BLOCK_COMMENT("zero_words {");
5283 int i = cnt & 1; // store any odd word to start
5284 if (i) str(zr, Address(base));
5285
5286 if (cnt <= SmallArraySize / BytesPerLong) {
5287 for (; i < (int)cnt; i += 2)
5288 stp(zr, zr, Address(base, i * wordSize));
5289 } else {
5290 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll
5291 int remainder = cnt % (2 * unroll);
5292 for (; i < remainder; i += 2)
5293 stp(zr, zr, Address(base, i * wordSize));
5294
5295 Label loop;
5296 Register cnt_reg = rscratch1;
5297 Register loop_base = rscratch2;
5298 cnt = cnt - remainder;
5299 mov(cnt_reg, cnt);
5300 // adjust base and prebias by -2 * wordSize so we can pre-increment
5301 add(loop_base, base, (remainder - 2) * wordSize);
5302 bind(loop);
5303 sub(cnt_reg, cnt_reg, 2 * unroll);
5304 for (i = 1; i < unroll; i++)
5305 stp(zr, zr, Address(loop_base, 2 * i * wordSize));
5306 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize)));
5307 cbnz(cnt_reg, loop);
5308 }
5309 BLOCK_COMMENT("} zero_words");
5310 }
5311
5312 // Zero blocks of memory by using DC ZVA.
5313 //
5314 // Aligns the base address first sufficently for DC ZVA, then uses
5315 // DC ZVA repeatedly for every full block. cnt is the size to be
5316 // zeroed in HeapWords. Returns the count of words left to be zeroed
5317 // in cnt.
5318 //
5319 // NOTE: This is intended to be used in the zero_blocks() stub. If
5320 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
5321 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
5322 Register tmp = rscratch1;
5323 Register tmp2 = rscratch2;
5324 int zva_length = VM_Version::zva_length();
5325 Label initial_table_end, loop_zva;
5326 Label fini;
5327
5328 // Base must be 16 byte aligned. If not just return and let caller handle it
5329 tst(base, 0x0f);
5330 br(Assembler::NE, fini);
5331 // Align base with ZVA length.
5332 neg(tmp, base);
5333 andr(tmp, tmp, zva_length - 1);
5334
5335 // tmp: the number of bytes to be filled to align the base with ZVA length.
5336 add(base, base, tmp);
5337 sub(cnt, cnt, tmp, Assembler::ASR, 3);
5338 adr(tmp2, initial_table_end);
5339 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
5340 br(tmp2);
5341
5342 for (int i = -zva_length + 16; i < 0; i += 16)
5343 stp(zr, zr, Address(base, i));
5344 bind(initial_table_end);
5345
5346 sub(cnt, cnt, zva_length >> 3);
5347 bind(loop_zva);
5348 dc(Assembler::ZVA, base);
5349 subs(cnt, cnt, zva_length >> 3);
5350 add(base, base, zva_length);
5351 br(Assembler::GE, loop_zva);
5352 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
5353 bind(fini);
5354 }
5355
5356 // base: Address of a buffer to be filled, 8 bytes aligned.
5357 // cnt: Count in 8-byte unit.
5358 // value: Value to be filled with.
5359 // base will point to the end of the buffer after filling.
5360 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
5361 {
5362 // Algorithm:
5363 //
5364 // scratch1 = cnt & 7;
5365 // cnt -= scratch1;
5366 // p += scratch1;
5367 // switch (scratch1) {
5368 // do {
5369 // cnt -= 8;
5370 // p[-8] = v;
5371 // case 7:
5372 // p[-7] = v;
5373 // case 6:
5374 // p[-6] = v;
5375 // // ...
5376 // case 1:
5377 // p[-1] = v;
5378 // case 0:
5379 // p += 8;
5380 // } while (cnt);
5381 // }
5382
5383 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
5384
5385 Label fini, skip, entry, loop;
5386 const int unroll = 8; // Number of stp instructions we'll unroll
5387
5388 cbz(cnt, fini);
5389 tbz(base, 3, skip);
5390 str(value, Address(post(base, 8)));
5391 sub(cnt, cnt, 1);
5392 bind(skip);
5393
5394 andr(rscratch1, cnt, (unroll-1) * 2);
5395 sub(cnt, cnt, rscratch1);
5396 add(base, base, rscratch1, Assembler::LSL, 3);
5397 adr(rscratch2, entry);
5398 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
5399 br(rscratch2);
5400
5401 bind(loop);
5402 add(base, base, unroll * 16);
5403 for (int i = -unroll; i < 0; i++)
5404 stp(value, value, Address(base, i * 16));
5405 bind(entry);
5406 subs(cnt, cnt, unroll * 2);
5407 br(Assembler::GE, loop);
5408
5409 tbz(cnt, 0, fini);
5410 str(value, Address(post(base, 8)));
5411 bind(fini);
5412 }
5413
5414 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and
5415 // java/lang/StringUTF16.compress.
5416 void MacroAssembler::encode_iso_array(Register src, Register dst,
5417 Register len, Register result,
5418 FloatRegister Vtmp1, FloatRegister Vtmp2,
5419 FloatRegister Vtmp3, FloatRegister Vtmp4)
5420 {
5421 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
5422 Register tmp1 = rscratch1;
5423
5424 mov(result, len); // Save initial len
5425
5426 #ifndef BUILTIN_SIM
5427 subs(len, len, 32);
5428 br(LT, LOOP_8);
5429
5430 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
5431 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
5432 // any char could not fit in a byte, so clear the FPSR so we can test it.
5433 clear_fpsr();
5434
5435 BIND(NEXT_32);
5436 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
5437 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
5438 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
5439 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
5440 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
5441 get_fpsr(tmp1);
5442 cbnzw(tmp1, LOOP_8);
5443 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
5444 subs(len, len, 32);
5445 add(src, src, 64);
5446 br(GE, NEXT_32);
5447
5448 BIND(LOOP_8);
5449 adds(len, len, 32-8);
5450 br(LT, LOOP_1);
5451 clear_fpsr(); // QC may be set from loop above, clear again
5452 BIND(NEXT_8);
5453 ld1(Vtmp1, T8H, src);
5454 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
5455 get_fpsr(tmp1);
5456 cbnzw(tmp1, LOOP_1);
5457 st1(Vtmp1, T8B, post(dst, 8));
5458 subs(len, len, 8);
5459 add(src, src, 16);
5460 br(GE, NEXT_8);
5461
5462 BIND(LOOP_1);
5463 adds(len, len, 8);
5464 br(LE, DONE);
5465 #else
5466 cbz(len, DONE);
5467 #endif
5468 BIND(NEXT_1);
5469 ldrh(tmp1, Address(post(src, 2)));
5470 tst(tmp1, 0xff00);
5471 br(NE, DONE);
5472 strb(tmp1, Address(post(dst, 1)));
5473 subs(len, len, 1);
5474 br(GT, NEXT_1);
5475
5476 BIND(DONE);
5477 sub(result, result, len); // Return index where we stopped
5478 // Return len == 0 if we processed all
5479 // characters
5480 }
5481
5482
5483 // Inflate byte[] array to char[].
5484 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
5485 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
5486 Register tmp4) {
5487 Label big, done;
5488
5489 assert_different_registers(src, dst, len, tmp4, rscratch1);
5490
5491 fmovd(vtmp1 , zr);
5492 lsrw(rscratch1, len, 3);
5493
5494 cbnzw(rscratch1, big);
5495
5496 // Short string: less than 8 bytes.
5497 {
5498 Label loop, around, tiny;
5499
5500 subsw(len, len, 4);
5501 andw(len, len, 3);
5502 br(LO, tiny);
5503
5504 // Use SIMD to do 4 bytes.
5505 ldrs(vtmp2, post(src, 4));
5506 zip1(vtmp3, T8B, vtmp2, vtmp1);
5507 strd(vtmp3, post(dst, 8));
5508
5509 cbzw(len, done);
5510
5511 // Do the remaining bytes by steam.
5512 bind(loop);
5513 ldrb(tmp4, post(src, 1));
5514 strh(tmp4, post(dst, 2));
5515 subw(len, len, 1);
5516
5517 bind(tiny);
5518 cbnz(len, loop);
5519
5520 bind(around);
5521 b(done);
5522 }
5523
5524 // Unpack the bytes 8 at a time.
5525 bind(big);
5526 andw(len, len, 7);
5527
5528 {
5529 Label loop, around;
5530
5531 bind(loop);
5532 ldrd(vtmp2, post(src, 8));
5533 sub(rscratch1, rscratch1, 1);
5534 zip1(vtmp3, T16B, vtmp2, vtmp1);
5535 st1(vtmp3, T8H, post(dst, 16));
5536 cbnz(rscratch1, loop);
5537
5538 bind(around);
5539 }
5540
5541 // Do the tail of up to 8 bytes.
5542 sub(src, src, 8);
5543 add(src, src, len, ext::uxtw, 0);
5544 ldrd(vtmp2, Address(src));
5545 sub(dst, dst, 16);
5546 add(dst, dst, len, ext::uxtw, 1);
5547 zip1(vtmp3, T16B, vtmp2, vtmp1);
5548 st1(vtmp3, T8H, Address(dst));
5549
5550 bind(done);
5551 }
5552
5553 // Compress char[] array to byte[].
5554 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
5555 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
5556 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
5557 Register result) {
5558 encode_iso_array(src, dst, len, result,
5559 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg);
5560 cmp(len, zr);
5561 csel(result, result, zr, EQ);
5562 }
5563
5564 // get_thread() can be called anywhere inside generated code so we
5565 // need to save whatever non-callee save context might get clobbered
5566 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
5567 // the call setup code.
5568 //
5569 // aarch64_get_thread_helper() clobbers only r0, r1, and flags.
5570 //
5571 void MacroAssembler::get_thread(Register dst) {
5572 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
5573 push(saved_regs, sp);
5574
5575 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5576 blrt(lr, 1, 0, 1);
5577 if (dst != c_rarg0) {
5578 mov(dst, c_rarg0);
5579 }
5580
5581 pop(saved_regs, sp);
5582 }