1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "jvm.h" 27 #include "asm/assembler.hpp" 28 #include "asm/assembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "gc/shared/barrierSet.hpp" 31 #include "gc/shared/barrierSetAssembler.hpp" 32 #include "gc/shared/collectedHeap.inline.hpp" 33 #include "interpreter/interpreter.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "memory/universe.hpp" 36 #include "oops/accessDecorators.hpp" 37 #include "oops/klass.inline.hpp" 38 #include "prims/methodHandles.hpp" 39 #include "runtime/biasedLocking.hpp" 40 #include "runtime/flags/flagSetting.hpp" 41 #include "runtime/interfaceSupport.inline.hpp" 42 #include "runtime/objectMonitor.hpp" 43 #include "runtime/os.hpp" 44 #include "runtime/safepoint.hpp" 45 #include "runtime/safepointMechanism.hpp" 46 #include "runtime/sharedRuntime.hpp" 47 #include "runtime/stubRoutines.hpp" 48 #include "runtime/thread.hpp" 49 #include "utilities/macros.hpp" 50 #include "crc32c.h" 51 #ifdef COMPILER2 52 #include "opto/intrinsicnode.hpp" 53 #endif 54 55 #ifdef PRODUCT 56 #define BLOCK_COMMENT(str) /* nothing */ 57 #define STOP(error) stop(error) 58 #else 59 #define BLOCK_COMMENT(str) block_comment(str) 60 #define STOP(error) block_comment(error); stop(error) 61 #endif 62 63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 64 65 #ifdef ASSERT 66 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 67 #endif 68 69 static Assembler::Condition reverse[] = { 70 Assembler::noOverflow /* overflow = 0x0 */ , 71 Assembler::overflow /* noOverflow = 0x1 */ , 72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 76 Assembler::above /* belowEqual = 0x6 */ , 77 Assembler::belowEqual /* above = 0x7 */ , 78 Assembler::positive /* negative = 0x8 */ , 79 Assembler::negative /* positive = 0x9 */ , 80 Assembler::noParity /* parity = 0xa */ , 81 Assembler::parity /* noParity = 0xb */ , 82 Assembler::greaterEqual /* less = 0xc */ , 83 Assembler::less /* greaterEqual = 0xd */ , 84 Assembler::greater /* lessEqual = 0xe */ , 85 Assembler::lessEqual /* greater = 0xf, */ 86 87 }; 88 89 90 // Implementation of MacroAssembler 91 92 // First all the versions that have distinct versions depending on 32/64 bit 93 // Unless the difference is trivial (1 line or so). 94 95 #ifndef _LP64 96 97 // 32bit versions 98 99 Address MacroAssembler::as_Address(AddressLiteral adr) { 100 return Address(adr.target(), adr.rspec()); 101 } 102 103 Address MacroAssembler::as_Address(ArrayAddress adr) { 104 return Address::make_array(adr); 105 } 106 107 void MacroAssembler::call_VM_leaf_base(address entry_point, 108 int number_of_arguments) { 109 call(RuntimeAddress(entry_point)); 110 increment(rsp, number_of_arguments * wordSize); 111 } 112 113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 115 } 116 117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 119 } 120 121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) { 122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 123 } 124 125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) { 126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 127 } 128 129 void MacroAssembler::cmpoop(Address src1, jobject obj) { 130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 131 bs->obj_equals(this, src1, obj); 132 } 133 134 void MacroAssembler::cmpoop(Register src1, jobject obj) { 135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 136 bs->obj_equals(this, src1, obj); 137 } 138 139 void MacroAssembler::extend_sign(Register hi, Register lo) { 140 // According to Intel Doc. AP-526, "Integer Divide", p.18. 141 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 142 cdql(); 143 } else { 144 movl(hi, lo); 145 sarl(hi, 31); 146 } 147 } 148 149 void MacroAssembler::jC2(Register tmp, Label& L) { 150 // set parity bit if FPU flag C2 is set (via rax) 151 save_rax(tmp); 152 fwait(); fnstsw_ax(); 153 sahf(); 154 restore_rax(tmp); 155 // branch 156 jcc(Assembler::parity, L); 157 } 158 159 void MacroAssembler::jnC2(Register tmp, Label& L) { 160 // set parity bit if FPU flag C2 is set (via rax) 161 save_rax(tmp); 162 fwait(); fnstsw_ax(); 163 sahf(); 164 restore_rax(tmp); 165 // branch 166 jcc(Assembler::noParity, L); 167 } 168 169 // 32bit can do a case table jump in one instruction but we no longer allow the base 170 // to be installed in the Address class 171 void MacroAssembler::jump(ArrayAddress entry) { 172 jmp(as_Address(entry)); 173 } 174 175 // Note: y_lo will be destroyed 176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 177 // Long compare for Java (semantics as described in JVM spec.) 178 Label high, low, done; 179 180 cmpl(x_hi, y_hi); 181 jcc(Assembler::less, low); 182 jcc(Assembler::greater, high); 183 // x_hi is the return register 184 xorl(x_hi, x_hi); 185 cmpl(x_lo, y_lo); 186 jcc(Assembler::below, low); 187 jcc(Assembler::equal, done); 188 189 bind(high); 190 xorl(x_hi, x_hi); 191 increment(x_hi); 192 jmp(done); 193 194 bind(low); 195 xorl(x_hi, x_hi); 196 decrementl(x_hi); 197 198 bind(done); 199 } 200 201 void MacroAssembler::lea(Register dst, AddressLiteral src) { 202 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 203 } 204 205 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 206 // leal(dst, as_Address(adr)); 207 // see note in movl as to why we must use a move 208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 209 } 210 211 void MacroAssembler::leave() { 212 mov(rsp, rbp); 213 pop(rbp); 214 } 215 216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 217 // Multiplication of two Java long values stored on the stack 218 // as illustrated below. Result is in rdx:rax. 219 // 220 // rsp ---> [ ?? ] \ \ 221 // .... | y_rsp_offset | 222 // [ y_lo ] / (in bytes) | x_rsp_offset 223 // [ y_hi ] | (in bytes) 224 // .... | 225 // [ x_lo ] / 226 // [ x_hi ] 227 // .... 228 // 229 // Basic idea: lo(result) = lo(x_lo * y_lo) 230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 233 Label quick; 234 // load x_hi, y_hi and check if quick 235 // multiplication is possible 236 movl(rbx, x_hi); 237 movl(rcx, y_hi); 238 movl(rax, rbx); 239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 241 // do full multiplication 242 // 1st step 243 mull(y_lo); // x_hi * y_lo 244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 245 // 2nd step 246 movl(rax, x_lo); 247 mull(rcx); // x_lo * y_hi 248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 249 // 3rd step 250 bind(quick); // note: rbx, = 0 if quick multiply! 251 movl(rax, x_lo); 252 mull(y_lo); // x_lo * y_lo 253 addl(rdx, rbx); // correct hi(x_lo * y_lo) 254 } 255 256 void MacroAssembler::lneg(Register hi, Register lo) { 257 negl(lo); 258 adcl(hi, 0); 259 negl(hi); 260 } 261 262 void MacroAssembler::lshl(Register hi, Register lo) { 263 // Java shift left long support (semantics as described in JVM spec., p.305) 264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 265 // shift value is in rcx ! 266 assert(hi != rcx, "must not use rcx"); 267 assert(lo != rcx, "must not use rcx"); 268 const Register s = rcx; // shift count 269 const int n = BitsPerWord; 270 Label L; 271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 272 cmpl(s, n); // if (s < n) 273 jcc(Assembler::less, L); // else (s >= n) 274 movl(hi, lo); // x := x << n 275 xorl(lo, lo); 276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 277 bind(L); // s (mod n) < n 278 shldl(hi, lo); // x := x << s 279 shll(lo); 280 } 281 282 283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 286 assert(hi != rcx, "must not use rcx"); 287 assert(lo != rcx, "must not use rcx"); 288 const Register s = rcx; // shift count 289 const int n = BitsPerWord; 290 Label L; 291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 292 cmpl(s, n); // if (s < n) 293 jcc(Assembler::less, L); // else (s >= n) 294 movl(lo, hi); // x := x >> n 295 if (sign_extension) sarl(hi, 31); 296 else xorl(hi, hi); 297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 298 bind(L); // s (mod n) < n 299 shrdl(lo, hi); // x := x >> s 300 if (sign_extension) sarl(hi); 301 else shrl(hi); 302 } 303 304 void MacroAssembler::movoop(Register dst, jobject obj) { 305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 306 } 307 308 void MacroAssembler::movoop(Address dst, jobject obj) { 309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 310 } 311 312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 314 } 315 316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 318 } 319 320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 321 // scratch register is not used, 322 // it is defined to match parameters of 64-bit version of this method. 323 if (src.is_lval()) { 324 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 325 } else { 326 movl(dst, as_Address(src)); 327 } 328 } 329 330 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 331 movl(as_Address(dst), src); 332 } 333 334 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 335 movl(dst, as_Address(src)); 336 } 337 338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 339 void MacroAssembler::movptr(Address dst, intptr_t src) { 340 movl(dst, src); 341 } 342 343 344 void MacroAssembler::pop_callee_saved_registers() { 345 pop(rcx); 346 pop(rdx); 347 pop(rdi); 348 pop(rsi); 349 } 350 351 void MacroAssembler::pop_fTOS() { 352 fld_d(Address(rsp, 0)); 353 addl(rsp, 2 * wordSize); 354 } 355 356 void MacroAssembler::push_callee_saved_registers() { 357 push(rsi); 358 push(rdi); 359 push(rdx); 360 push(rcx); 361 } 362 363 void MacroAssembler::push_fTOS() { 364 subl(rsp, 2 * wordSize); 365 fstp_d(Address(rsp, 0)); 366 } 367 368 369 void MacroAssembler::pushoop(jobject obj) { 370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 371 } 372 373 void MacroAssembler::pushklass(Metadata* obj) { 374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 375 } 376 377 void MacroAssembler::pushptr(AddressLiteral src) { 378 if (src.is_lval()) { 379 push_literal32((int32_t)src.target(), src.rspec()); 380 } else { 381 pushl(as_Address(src)); 382 } 383 } 384 385 void MacroAssembler::set_word_if_not_zero(Register dst) { 386 xorl(dst, dst); 387 set_byte_if_not_zero(dst); 388 } 389 390 static void pass_arg0(MacroAssembler* masm, Register arg) { 391 masm->push(arg); 392 } 393 394 static void pass_arg1(MacroAssembler* masm, Register arg) { 395 masm->push(arg); 396 } 397 398 static void pass_arg2(MacroAssembler* masm, Register arg) { 399 masm->push(arg); 400 } 401 402 static void pass_arg3(MacroAssembler* masm, Register arg) { 403 masm->push(arg); 404 } 405 406 #ifndef PRODUCT 407 extern "C" void findpc(intptr_t x); 408 #endif 409 410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 411 // In order to get locks to work, we need to fake a in_VM state 412 JavaThread* thread = JavaThread::current(); 413 JavaThreadState saved_state = thread->thread_state(); 414 thread->set_thread_state(_thread_in_vm); 415 if (ShowMessageBoxOnError) { 416 JavaThread* thread = JavaThread::current(); 417 JavaThreadState saved_state = thread->thread_state(); 418 thread->set_thread_state(_thread_in_vm); 419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 420 ttyLocker ttyl; 421 BytecodeCounter::print(); 422 } 423 // To see where a verify_oop failed, get $ebx+40/X for this frame. 424 // This is the value of eip which points to where verify_oop will return. 425 if (os::message_box(msg, "Execution stopped, print registers?")) { 426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 427 BREAKPOINT; 428 } 429 } else { 430 ttyLocker ttyl; 431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 432 } 433 // Don't assert holding the ttyLock 434 assert(false, "DEBUG MESSAGE: %s", msg); 435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 436 } 437 438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 439 ttyLocker ttyl; 440 FlagSetting fs(Debugging, true); 441 tty->print_cr("eip = 0x%08x", eip); 442 #ifndef PRODUCT 443 if ((WizardMode || Verbose) && PrintMiscellaneous) { 444 tty->cr(); 445 findpc(eip); 446 tty->cr(); 447 } 448 #endif 449 #define PRINT_REG(rax) \ 450 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 451 PRINT_REG(rax); 452 PRINT_REG(rbx); 453 PRINT_REG(rcx); 454 PRINT_REG(rdx); 455 PRINT_REG(rdi); 456 PRINT_REG(rsi); 457 PRINT_REG(rbp); 458 PRINT_REG(rsp); 459 #undef PRINT_REG 460 // Print some words near top of staack. 461 int* dump_sp = (int*) rsp; 462 for (int col1 = 0; col1 < 8; col1++) { 463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 464 os::print_location(tty, *dump_sp++); 465 } 466 for (int row = 0; row < 16; row++) { 467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 468 for (int col = 0; col < 8; col++) { 469 tty->print(" 0x%08x", *dump_sp++); 470 } 471 tty->cr(); 472 } 473 // Print some instructions around pc: 474 Disassembler::decode((address)eip-64, (address)eip); 475 tty->print_cr("--------"); 476 Disassembler::decode((address)eip, (address)eip+32); 477 } 478 479 void MacroAssembler::stop(const char* msg) { 480 ExternalAddress message((address)msg); 481 // push address of message 482 pushptr(message.addr()); 483 { Label L; call(L, relocInfo::none); bind(L); } // push eip 484 pusha(); // push registers 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 486 hlt(); 487 } 488 489 void MacroAssembler::warn(const char* msg) { 490 push_CPU_state(); 491 492 ExternalAddress message((address) msg); 493 // push address of message 494 pushptr(message.addr()); 495 496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 497 addl(rsp, wordSize); // discard argument 498 pop_CPU_state(); 499 } 500 501 void MacroAssembler::print_state() { 502 { Label L; call(L, relocInfo::none); bind(L); } // push eip 503 pusha(); // push registers 504 505 push_CPU_state(); 506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 507 pop_CPU_state(); 508 509 popa(); 510 addl(rsp, wordSize); 511 } 512 513 #else // _LP64 514 515 // 64 bit versions 516 517 Address MacroAssembler::as_Address(AddressLiteral adr) { 518 // amd64 always does this as a pc-rel 519 // we can be absolute or disp based on the instruction type 520 // jmp/call are displacements others are absolute 521 assert(!adr.is_lval(), "must be rval"); 522 assert(reachable(adr), "must be"); 523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 524 525 } 526 527 Address MacroAssembler::as_Address(ArrayAddress adr) { 528 AddressLiteral base = adr.base(); 529 lea(rscratch1, base); 530 Address index = adr.index(); 531 assert(index._disp == 0, "must not have disp"); // maybe it can? 532 Address array(rscratch1, index._index, index._scale, index._disp); 533 return array; 534 } 535 536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 537 Label L, E; 538 539 #ifdef _WIN64 540 // Windows always allocates space for it's register args 541 assert(num_args <= 4, "only register arguments supported"); 542 subq(rsp, frame::arg_reg_save_area_bytes); 543 #endif 544 545 // Align stack if necessary 546 testl(rsp, 15); 547 jcc(Assembler::zero, L); 548 549 subq(rsp, 8); 550 { 551 call(RuntimeAddress(entry_point)); 552 } 553 addq(rsp, 8); 554 jmp(E); 555 556 bind(L); 557 { 558 call(RuntimeAddress(entry_point)); 559 } 560 561 bind(E); 562 563 #ifdef _WIN64 564 // restore stack pointer 565 addq(rsp, frame::arg_reg_save_area_bytes); 566 #endif 567 568 } 569 570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 571 assert(!src2.is_lval(), "should use cmpptr"); 572 573 if (reachable(src2)) { 574 cmpq(src1, as_Address(src2)); 575 } else { 576 lea(rscratch1, src2); 577 Assembler::cmpq(src1, Address(rscratch1, 0)); 578 } 579 } 580 581 int MacroAssembler::corrected_idivq(Register reg) { 582 // Full implementation of Java ldiv and lrem; checks for special 583 // case as described in JVM spec., p.243 & p.271. The function 584 // returns the (pc) offset of the idivl instruction - may be needed 585 // for implicit exceptions. 586 // 587 // normal case special case 588 // 589 // input : rax: dividend min_long 590 // reg: divisor (may not be eax/edx) -1 591 // 592 // output: rax: quotient (= rax idiv reg) min_long 593 // rdx: remainder (= rax irem reg) 0 594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 595 static const int64_t min_long = 0x8000000000000000; 596 Label normal_case, special_case; 597 598 // check for special case 599 cmp64(rax, ExternalAddress((address) &min_long)); 600 jcc(Assembler::notEqual, normal_case); 601 xorl(rdx, rdx); // prepare rdx for possible special case (where 602 // remainder = 0) 603 cmpq(reg, -1); 604 jcc(Assembler::equal, special_case); 605 606 // handle normal case 607 bind(normal_case); 608 cdqq(); 609 int idivq_offset = offset(); 610 idivq(reg); 611 612 // normal and special case exit 613 bind(special_case); 614 615 return idivq_offset; 616 } 617 618 void MacroAssembler::decrementq(Register reg, int value) { 619 if (value == min_jint) { subq(reg, value); return; } 620 if (value < 0) { incrementq(reg, -value); return; } 621 if (value == 0) { ; return; } 622 if (value == 1 && UseIncDec) { decq(reg) ; return; } 623 /* else */ { subq(reg, value) ; return; } 624 } 625 626 void MacroAssembler::decrementq(Address dst, int value) { 627 if (value == min_jint) { subq(dst, value); return; } 628 if (value < 0) { incrementq(dst, -value); return; } 629 if (value == 0) { ; return; } 630 if (value == 1 && UseIncDec) { decq(dst) ; return; } 631 /* else */ { subq(dst, value) ; return; } 632 } 633 634 void MacroAssembler::incrementq(AddressLiteral dst) { 635 if (reachable(dst)) { 636 incrementq(as_Address(dst)); 637 } else { 638 lea(rscratch1, dst); 639 incrementq(Address(rscratch1, 0)); 640 } 641 } 642 643 void MacroAssembler::incrementq(Register reg, int value) { 644 if (value == min_jint) { addq(reg, value); return; } 645 if (value < 0) { decrementq(reg, -value); return; } 646 if (value == 0) { ; return; } 647 if (value == 1 && UseIncDec) { incq(reg) ; return; } 648 /* else */ { addq(reg, value) ; return; } 649 } 650 651 void MacroAssembler::incrementq(Address dst, int value) { 652 if (value == min_jint) { addq(dst, value); return; } 653 if (value < 0) { decrementq(dst, -value); return; } 654 if (value == 0) { ; return; } 655 if (value == 1 && UseIncDec) { incq(dst) ; return; } 656 /* else */ { addq(dst, value) ; return; } 657 } 658 659 // 32bit can do a case table jump in one instruction but we no longer allow the base 660 // to be installed in the Address class 661 void MacroAssembler::jump(ArrayAddress entry) { 662 lea(rscratch1, entry.base()); 663 Address dispatch = entry.index(); 664 assert(dispatch._base == noreg, "must be"); 665 dispatch._base = rscratch1; 666 jmp(dispatch); 667 } 668 669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 670 ShouldNotReachHere(); // 64bit doesn't use two regs 671 cmpq(x_lo, y_lo); 672 } 673 674 void MacroAssembler::lea(Register dst, AddressLiteral src) { 675 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 676 } 677 678 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 680 movptr(dst, rscratch1); 681 } 682 683 void MacroAssembler::leave() { 684 // %%% is this really better? Why not on 32bit too? 685 emit_int8((unsigned char)0xC9); // LEAVE 686 } 687 688 void MacroAssembler::lneg(Register hi, Register lo) { 689 ShouldNotReachHere(); // 64bit doesn't use two regs 690 negq(lo); 691 } 692 693 void MacroAssembler::movoop(Register dst, jobject obj) { 694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 695 } 696 697 void MacroAssembler::movoop(Address dst, jobject obj) { 698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 699 movq(dst, rscratch1); 700 } 701 702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 704 } 705 706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 708 movq(dst, rscratch1); 709 } 710 711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 712 if (src.is_lval()) { 713 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 714 } else { 715 if (reachable(src)) { 716 movq(dst, as_Address(src)); 717 } else { 718 lea(scratch, src); 719 movq(dst, Address(scratch, 0)); 720 } 721 } 722 } 723 724 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 725 movq(as_Address(dst), src); 726 } 727 728 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 729 movq(dst, as_Address(src)); 730 } 731 732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 733 void MacroAssembler::movptr(Address dst, intptr_t src) { 734 mov64(rscratch1, src); 735 movq(dst, rscratch1); 736 } 737 738 // These are mostly for initializing NULL 739 void MacroAssembler::movptr(Address dst, int32_t src) { 740 movslq(dst, src); 741 } 742 743 void MacroAssembler::movptr(Register dst, int32_t src) { 744 mov64(dst, (intptr_t)src); 745 } 746 747 void MacroAssembler::pushoop(jobject obj) { 748 movoop(rscratch1, obj); 749 push(rscratch1); 750 } 751 752 void MacroAssembler::pushklass(Metadata* obj) { 753 mov_metadata(rscratch1, obj); 754 push(rscratch1); 755 } 756 757 void MacroAssembler::pushptr(AddressLiteral src) { 758 lea(rscratch1, src); 759 if (src.is_lval()) { 760 push(rscratch1); 761 } else { 762 pushq(Address(rscratch1, 0)); 763 } 764 } 765 766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 767 // we must set sp to zero to clear frame 768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 769 // must clear fp, so that compiled frames are not confused; it is 770 // possible that we need it only for debugging 771 if (clear_fp) { 772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 773 } 774 775 // Always clear the pc because it could have been set by make_walkable() 776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 777 vzeroupper(); 778 } 779 780 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 781 Register last_java_fp, 782 address last_java_pc) { 783 vzeroupper(); 784 // determine last_java_sp register 785 if (!last_java_sp->is_valid()) { 786 last_java_sp = rsp; 787 } 788 789 // last_java_fp is optional 790 if (last_java_fp->is_valid()) { 791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 792 last_java_fp); 793 } 794 795 // last_java_pc is optional 796 if (last_java_pc != NULL) { 797 Address java_pc(r15_thread, 798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 799 lea(rscratch1, InternalAddress(last_java_pc)); 800 movptr(java_pc, rscratch1); 801 } 802 803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 804 } 805 806 static void pass_arg0(MacroAssembler* masm, Register arg) { 807 if (c_rarg0 != arg ) { 808 masm->mov(c_rarg0, arg); 809 } 810 } 811 812 static void pass_arg1(MacroAssembler* masm, Register arg) { 813 if (c_rarg1 != arg ) { 814 masm->mov(c_rarg1, arg); 815 } 816 } 817 818 static void pass_arg2(MacroAssembler* masm, Register arg) { 819 if (c_rarg2 != arg ) { 820 masm->mov(c_rarg2, arg); 821 } 822 } 823 824 static void pass_arg3(MacroAssembler* masm, Register arg) { 825 if (c_rarg3 != arg ) { 826 masm->mov(c_rarg3, arg); 827 } 828 } 829 830 void MacroAssembler::stop(const char* msg) { 831 address rip = pc(); 832 pusha(); // get regs on stack 833 lea(c_rarg0, ExternalAddress((address) msg)); 834 lea(c_rarg1, InternalAddress(rip)); 835 movq(c_rarg2, rsp); // pass pointer to regs array 836 andq(rsp, -16); // align stack as required by ABI 837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 838 hlt(); 839 } 840 841 void MacroAssembler::warn(const char* msg) { 842 push(rbp); 843 movq(rbp, rsp); 844 andq(rsp, -16); // align stack as required by push_CPU_state and call 845 push_CPU_state(); // keeps alignment at 16 bytes 846 lea(c_rarg0, ExternalAddress((address) msg)); 847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning))); 848 call(rax); 849 pop_CPU_state(); 850 mov(rsp, rbp); 851 pop(rbp); 852 } 853 854 void MacroAssembler::print_state() { 855 address rip = pc(); 856 pusha(); // get regs on stack 857 push(rbp); 858 movq(rbp, rsp); 859 andq(rsp, -16); // align stack as required by push_CPU_state and call 860 push_CPU_state(); // keeps alignment at 16 bytes 861 862 lea(c_rarg0, InternalAddress(rip)); 863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 865 866 pop_CPU_state(); 867 mov(rsp, rbp); 868 pop(rbp); 869 popa(); 870 } 871 872 #ifndef PRODUCT 873 extern "C" void findpc(intptr_t x); 874 #endif 875 876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 877 // In order to get locks to work, we need to fake a in_VM state 878 if (ShowMessageBoxOnError) { 879 JavaThread* thread = JavaThread::current(); 880 JavaThreadState saved_state = thread->thread_state(); 881 thread->set_thread_state(_thread_in_vm); 882 #ifndef PRODUCT 883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 884 ttyLocker ttyl; 885 BytecodeCounter::print(); 886 } 887 #endif 888 // To see where a verify_oop failed, get $ebx+40/X for this frame. 889 // XXX correct this offset for amd64 890 // This is the value of eip which points to where verify_oop will return. 891 if (os::message_box(msg, "Execution stopped, print registers?")) { 892 print_state64(pc, regs); 893 BREAKPOINT; 894 assert(false, "start up GDB"); 895 } 896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 897 } else { 898 ttyLocker ttyl; 899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 900 msg); 901 assert(false, "DEBUG MESSAGE: %s", msg); 902 } 903 } 904 905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 906 ttyLocker ttyl; 907 FlagSetting fs(Debugging, true); 908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc); 909 #ifndef PRODUCT 910 tty->cr(); 911 findpc(pc); 912 tty->cr(); 913 #endif 914 #define PRINT_REG(rax, value) \ 915 { tty->print("%s = ", #rax); os::print_location(tty, value); } 916 PRINT_REG(rax, regs[15]); 917 PRINT_REG(rbx, regs[12]); 918 PRINT_REG(rcx, regs[14]); 919 PRINT_REG(rdx, regs[13]); 920 PRINT_REG(rdi, regs[8]); 921 PRINT_REG(rsi, regs[9]); 922 PRINT_REG(rbp, regs[10]); 923 PRINT_REG(rsp, regs[11]); 924 PRINT_REG(r8 , regs[7]); 925 PRINT_REG(r9 , regs[6]); 926 PRINT_REG(r10, regs[5]); 927 PRINT_REG(r11, regs[4]); 928 PRINT_REG(r12, regs[3]); 929 PRINT_REG(r13, regs[2]); 930 PRINT_REG(r14, regs[1]); 931 PRINT_REG(r15, regs[0]); 932 #undef PRINT_REG 933 // Print some words near top of staack. 934 int64_t* rsp = (int64_t*) regs[11]; 935 int64_t* dump_sp = rsp; 936 for (int col1 = 0; col1 < 8; col1++) { 937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 938 os::print_location(tty, *dump_sp++); 939 } 940 for (int row = 0; row < 25; row++) { 941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 942 for (int col = 0; col < 4; col++) { 943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++); 944 } 945 tty->cr(); 946 } 947 // Print some instructions around pc: 948 Disassembler::decode((address)pc-64, (address)pc); 949 tty->print_cr("--------"); 950 Disassembler::decode((address)pc, (address)pc+32); 951 } 952 953 #endif // _LP64 954 955 // Now versions that are common to 32/64 bit 956 957 void MacroAssembler::addptr(Register dst, int32_t imm32) { 958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 959 } 960 961 void MacroAssembler::addptr(Register dst, Register src) { 962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 963 } 964 965 void MacroAssembler::addptr(Address dst, Register src) { 966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 967 } 968 969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 970 if (reachable(src)) { 971 Assembler::addsd(dst, as_Address(src)); 972 } else { 973 lea(rscratch1, src); 974 Assembler::addsd(dst, Address(rscratch1, 0)); 975 } 976 } 977 978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 979 if (reachable(src)) { 980 addss(dst, as_Address(src)); 981 } else { 982 lea(rscratch1, src); 983 addss(dst, Address(rscratch1, 0)); 984 } 985 } 986 987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 988 if (reachable(src)) { 989 Assembler::addpd(dst, as_Address(src)); 990 } else { 991 lea(rscratch1, src); 992 Assembler::addpd(dst, Address(rscratch1, 0)); 993 } 994 } 995 996 void MacroAssembler::align(int modulus) { 997 align(modulus, offset()); 998 } 999 1000 void MacroAssembler::align(int modulus, int target) { 1001 if (target % modulus != 0) { 1002 nop(modulus - (target % modulus)); 1003 } 1004 } 1005 1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 1007 // Used in sign-masking with aligned address. 1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1009 if (reachable(src)) { 1010 Assembler::andpd(dst, as_Address(src)); 1011 } else { 1012 lea(rscratch1, src); 1013 Assembler::andpd(dst, Address(rscratch1, 0)); 1014 } 1015 } 1016 1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1018 // Used in sign-masking with aligned address. 1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1020 if (reachable(src)) { 1021 Assembler::andps(dst, as_Address(src)); 1022 } else { 1023 lea(rscratch1, src); 1024 Assembler::andps(dst, Address(rscratch1, 0)); 1025 } 1026 } 1027 1028 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1030 } 1031 1032 void MacroAssembler::atomic_incl(Address counter_addr) { 1033 if (os::is_MP()) 1034 lock(); 1035 incrementl(counter_addr); 1036 } 1037 1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1039 if (reachable(counter_addr)) { 1040 atomic_incl(as_Address(counter_addr)); 1041 } else { 1042 lea(scr, counter_addr); 1043 atomic_incl(Address(scr, 0)); 1044 } 1045 } 1046 1047 #ifdef _LP64 1048 void MacroAssembler::atomic_incq(Address counter_addr) { 1049 if (os::is_MP()) 1050 lock(); 1051 incrementq(counter_addr); 1052 } 1053 1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1055 if (reachable(counter_addr)) { 1056 atomic_incq(as_Address(counter_addr)); 1057 } else { 1058 lea(scr, counter_addr); 1059 atomic_incq(Address(scr, 0)); 1060 } 1061 } 1062 #endif 1063 1064 // Writes to stack successive pages until offset reached to check for 1065 // stack overflow + shadow pages. This clobbers tmp. 1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1067 movptr(tmp, rsp); 1068 // Bang stack for total size given plus shadow page size. 1069 // Bang one page at a time because large size can bang beyond yellow and 1070 // red zones. 1071 Label loop; 1072 bind(loop); 1073 movl(Address(tmp, (-os::vm_page_size())), size ); 1074 subptr(tmp, os::vm_page_size()); 1075 subl(size, os::vm_page_size()); 1076 jcc(Assembler::greater, loop); 1077 1078 // Bang down shadow pages too. 1079 // At this point, (tmp-0) is the last address touched, so don't 1080 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1081 // was post-decremented.) Skip this address by starting at i=1, and 1082 // touch a few more pages below. N.B. It is important to touch all 1083 // the way down including all pages in the shadow zone. 1084 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1085 // this could be any sized move but this is can be a debugging crumb 1086 // so the bigger the better. 1087 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1088 } 1089 } 1090 1091 void MacroAssembler::reserved_stack_check() { 1092 // testing if reserved zone needs to be enabled 1093 Label no_reserved_zone_enabling; 1094 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1095 NOT_LP64(get_thread(rsi);) 1096 1097 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1098 jcc(Assembler::below, no_reserved_zone_enabling); 1099 1100 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1101 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1102 should_not_reach_here(); 1103 1104 bind(no_reserved_zone_enabling); 1105 } 1106 1107 int MacroAssembler::biased_locking_enter(Register lock_reg, 1108 Register obj_reg, 1109 Register swap_reg, 1110 Register tmp_reg, 1111 bool swap_reg_contains_mark, 1112 Label& done, 1113 Label* slow_case, 1114 BiasedLockingCounters* counters) { 1115 assert(UseBiasedLocking, "why call this otherwise?"); 1116 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1117 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1118 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1119 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1120 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1121 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1122 1123 if (PrintBiasedLockingStatistics && counters == NULL) { 1124 counters = BiasedLocking::counters(); 1125 } 1126 // Biased locking 1127 // See whether the lock is currently biased toward our thread and 1128 // whether the epoch is still valid 1129 // Note that the runtime guarantees sufficient alignment of JavaThread 1130 // pointers to allow age to be placed into low bits 1131 // First check to see whether biasing is even enabled for this object 1132 Label cas_label; 1133 int null_check_offset = -1; 1134 if (!swap_reg_contains_mark) { 1135 null_check_offset = offset(); 1136 movptr(swap_reg, mark_addr); 1137 } 1138 movptr(tmp_reg, swap_reg); 1139 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1140 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1141 jcc(Assembler::notEqual, cas_label); 1142 // The bias pattern is present in the object's header. Need to check 1143 // whether the bias owner and the epoch are both still current. 1144 #ifndef _LP64 1145 // Note that because there is no current thread register on x86_32 we 1146 // need to store off the mark word we read out of the object to 1147 // avoid reloading it and needing to recheck invariants below. This 1148 // store is unfortunate but it makes the overall code shorter and 1149 // simpler. 1150 movptr(saved_mark_addr, swap_reg); 1151 #endif 1152 if (swap_reg_contains_mark) { 1153 null_check_offset = offset(); 1154 } 1155 load_prototype_header(tmp_reg, obj_reg); 1156 #ifdef _LP64 1157 orptr(tmp_reg, r15_thread); 1158 xorptr(tmp_reg, swap_reg); 1159 Register header_reg = tmp_reg; 1160 #else 1161 xorptr(tmp_reg, swap_reg); 1162 get_thread(swap_reg); 1163 xorptr(swap_reg, tmp_reg); 1164 Register header_reg = swap_reg; 1165 #endif 1166 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1167 if (counters != NULL) { 1168 cond_inc32(Assembler::zero, 1169 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1170 } 1171 jcc(Assembler::equal, done); 1172 1173 Label try_revoke_bias; 1174 Label try_rebias; 1175 1176 // At this point we know that the header has the bias pattern and 1177 // that we are not the bias owner in the current epoch. We need to 1178 // figure out more details about the state of the header in order to 1179 // know what operations can be legally performed on the object's 1180 // header. 1181 1182 // If the low three bits in the xor result aren't clear, that means 1183 // the prototype header is no longer biased and we have to revoke 1184 // the bias on this object. 1185 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1186 jccb(Assembler::notZero, try_revoke_bias); 1187 1188 // Biasing is still enabled for this data type. See whether the 1189 // epoch of the current bias is still valid, meaning that the epoch 1190 // bits of the mark word are equal to the epoch bits of the 1191 // prototype header. (Note that the prototype header's epoch bits 1192 // only change at a safepoint.) If not, attempt to rebias the object 1193 // toward the current thread. Note that we must be absolutely sure 1194 // that the current epoch is invalid in order to do this because 1195 // otherwise the manipulations it performs on the mark word are 1196 // illegal. 1197 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1198 jccb(Assembler::notZero, try_rebias); 1199 1200 // The epoch of the current bias is still valid but we know nothing 1201 // about the owner; it might be set or it might be clear. Try to 1202 // acquire the bias of the object using an atomic operation. If this 1203 // fails we will go in to the runtime to revoke the object's bias. 1204 // Note that we first construct the presumed unbiased header so we 1205 // don't accidentally blow away another thread's valid bias. 1206 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1207 andptr(swap_reg, 1208 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1209 #ifdef _LP64 1210 movptr(tmp_reg, swap_reg); 1211 orptr(tmp_reg, r15_thread); 1212 #else 1213 get_thread(tmp_reg); 1214 orptr(tmp_reg, swap_reg); 1215 #endif 1216 if (os::is_MP()) { 1217 lock(); 1218 } 1219 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1220 // If the biasing toward our thread failed, this means that 1221 // another thread succeeded in biasing it toward itself and we 1222 // need to revoke that bias. The revocation will occur in the 1223 // interpreter runtime in the slow case. 1224 if (counters != NULL) { 1225 cond_inc32(Assembler::zero, 1226 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1227 } 1228 if (slow_case != NULL) { 1229 jcc(Assembler::notZero, *slow_case); 1230 } 1231 jmp(done); 1232 1233 bind(try_rebias); 1234 // At this point we know the epoch has expired, meaning that the 1235 // current "bias owner", if any, is actually invalid. Under these 1236 // circumstances _only_, we are allowed to use the current header's 1237 // value as the comparison value when doing the cas to acquire the 1238 // bias in the current epoch. In other words, we allow transfer of 1239 // the bias from one thread to another directly in this situation. 1240 // 1241 // FIXME: due to a lack of registers we currently blow away the age 1242 // bits in this situation. Should attempt to preserve them. 1243 load_prototype_header(tmp_reg, obj_reg); 1244 #ifdef _LP64 1245 orptr(tmp_reg, r15_thread); 1246 #else 1247 get_thread(swap_reg); 1248 orptr(tmp_reg, swap_reg); 1249 movptr(swap_reg, saved_mark_addr); 1250 #endif 1251 if (os::is_MP()) { 1252 lock(); 1253 } 1254 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1255 // If the biasing toward our thread failed, then another thread 1256 // succeeded in biasing it toward itself and we need to revoke that 1257 // bias. The revocation will occur in the runtime in the slow case. 1258 if (counters != NULL) { 1259 cond_inc32(Assembler::zero, 1260 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1261 } 1262 if (slow_case != NULL) { 1263 jcc(Assembler::notZero, *slow_case); 1264 } 1265 jmp(done); 1266 1267 bind(try_revoke_bias); 1268 // The prototype mark in the klass doesn't have the bias bit set any 1269 // more, indicating that objects of this data type are not supposed 1270 // to be biased any more. We are going to try to reset the mark of 1271 // this object to the prototype value and fall through to the 1272 // CAS-based locking scheme. Note that if our CAS fails, it means 1273 // that another thread raced us for the privilege of revoking the 1274 // bias of this particular object, so it's okay to continue in the 1275 // normal locking code. 1276 // 1277 // FIXME: due to a lack of registers we currently blow away the age 1278 // bits in this situation. Should attempt to preserve them. 1279 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1280 load_prototype_header(tmp_reg, obj_reg); 1281 if (os::is_MP()) { 1282 lock(); 1283 } 1284 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1285 // Fall through to the normal CAS-based lock, because no matter what 1286 // the result of the above CAS, some thread must have succeeded in 1287 // removing the bias bit from the object's header. 1288 if (counters != NULL) { 1289 cond_inc32(Assembler::zero, 1290 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1291 } 1292 1293 bind(cas_label); 1294 1295 return null_check_offset; 1296 } 1297 1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1299 assert(UseBiasedLocking, "why call this otherwise?"); 1300 1301 // Check for biased locking unlock case, which is a no-op 1302 // Note: we do not have to check the thread ID for two reasons. 1303 // First, the interpreter checks for IllegalMonitorStateException at 1304 // a higher level. Second, if the bias was revoked while we held the 1305 // lock, the object could not be rebiased toward another thread, so 1306 // the bias bit would be clear. 1307 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1308 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1309 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1310 jcc(Assembler::equal, done); 1311 } 1312 1313 #ifdef COMPILER2 1314 1315 #if INCLUDE_RTM_OPT 1316 1317 // Update rtm_counters based on abort status 1318 // input: abort_status 1319 // rtm_counters (RTMLockingCounters*) 1320 // flags are killed 1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1322 1323 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1324 if (PrintPreciseRTMLockingStatistics) { 1325 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1326 Label check_abort; 1327 testl(abort_status, (1<<i)); 1328 jccb(Assembler::equal, check_abort); 1329 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1330 bind(check_abort); 1331 } 1332 } 1333 } 1334 1335 // Branch if (random & (count-1) != 0), count is 2^n 1336 // tmp, scr and flags are killed 1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1338 assert(tmp == rax, ""); 1339 assert(scr == rdx, ""); 1340 rdtsc(); // modifies EDX:EAX 1341 andptr(tmp, count-1); 1342 jccb(Assembler::notZero, brLabel); 1343 } 1344 1345 // Perform abort ratio calculation, set no_rtm bit if high ratio 1346 // input: rtm_counters_Reg (RTMLockingCounters* address) 1347 // tmpReg, rtm_counters_Reg and flags are killed 1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1349 Register rtm_counters_Reg, 1350 RTMLockingCounters* rtm_counters, 1351 Metadata* method_data) { 1352 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1353 1354 if (RTMLockingCalculationDelay > 0) { 1355 // Delay calculation 1356 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1357 testptr(tmpReg, tmpReg); 1358 jccb(Assembler::equal, L_done); 1359 } 1360 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1361 // Aborted transactions = abort_count * 100 1362 // All transactions = total_count * RTMTotalCountIncrRate 1363 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1364 1365 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1366 cmpptr(tmpReg, RTMAbortThreshold); 1367 jccb(Assembler::below, L_check_always_rtm2); 1368 imulptr(tmpReg, tmpReg, 100); 1369 1370 Register scrReg = rtm_counters_Reg; 1371 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1372 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1373 imulptr(scrReg, scrReg, RTMAbortRatio); 1374 cmpptr(tmpReg, scrReg); 1375 jccb(Assembler::below, L_check_always_rtm1); 1376 if (method_data != NULL) { 1377 // set rtm_state to "no rtm" in MDO 1378 mov_metadata(tmpReg, method_data); 1379 if (os::is_MP()) { 1380 lock(); 1381 } 1382 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1383 } 1384 jmpb(L_done); 1385 bind(L_check_always_rtm1); 1386 // Reload RTMLockingCounters* address 1387 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1388 bind(L_check_always_rtm2); 1389 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1390 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1391 jccb(Assembler::below, L_done); 1392 if (method_data != NULL) { 1393 // set rtm_state to "always rtm" in MDO 1394 mov_metadata(tmpReg, method_data); 1395 if (os::is_MP()) { 1396 lock(); 1397 } 1398 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1399 } 1400 bind(L_done); 1401 } 1402 1403 // Update counters and perform abort ratio calculation 1404 // input: abort_status_Reg 1405 // rtm_counters_Reg, flags are killed 1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1407 Register rtm_counters_Reg, 1408 RTMLockingCounters* rtm_counters, 1409 Metadata* method_data, 1410 bool profile_rtm) { 1411 1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1413 // update rtm counters based on rax value at abort 1414 // reads abort_status_Reg, updates flags 1415 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1416 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1417 if (profile_rtm) { 1418 // Save abort status because abort_status_Reg is used by following code. 1419 if (RTMRetryCount > 0) { 1420 push(abort_status_Reg); 1421 } 1422 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1423 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1424 // restore abort status 1425 if (RTMRetryCount > 0) { 1426 pop(abort_status_Reg); 1427 } 1428 } 1429 } 1430 1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1432 // inputs: retry_count_Reg 1433 // : abort_status_Reg 1434 // output: retry_count_Reg decremented by 1 1435 // flags are killed 1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1437 Label doneRetry; 1438 assert(abort_status_Reg == rax, ""); 1439 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1440 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1441 // if reason is in 0x6 and retry count != 0 then retry 1442 andptr(abort_status_Reg, 0x6); 1443 jccb(Assembler::zero, doneRetry); 1444 testl(retry_count_Reg, retry_count_Reg); 1445 jccb(Assembler::zero, doneRetry); 1446 pause(); 1447 decrementl(retry_count_Reg); 1448 jmp(retryLabel); 1449 bind(doneRetry); 1450 } 1451 1452 // Spin and retry if lock is busy, 1453 // inputs: box_Reg (monitor address) 1454 // : retry_count_Reg 1455 // output: retry_count_Reg decremented by 1 1456 // : clear z flag if retry count exceeded 1457 // tmp_Reg, scr_Reg, flags are killed 1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1459 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1460 Label SpinLoop, SpinExit, doneRetry; 1461 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1462 1463 testl(retry_count_Reg, retry_count_Reg); 1464 jccb(Assembler::zero, doneRetry); 1465 decrementl(retry_count_Reg); 1466 movptr(scr_Reg, RTMSpinLoopCount); 1467 1468 bind(SpinLoop); 1469 pause(); 1470 decrementl(scr_Reg); 1471 jccb(Assembler::lessEqual, SpinExit); 1472 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1473 testptr(tmp_Reg, tmp_Reg); 1474 jccb(Assembler::notZero, SpinLoop); 1475 1476 bind(SpinExit); 1477 jmp(retryLabel); 1478 bind(doneRetry); 1479 incrementl(retry_count_Reg); // clear z flag 1480 } 1481 1482 // Use RTM for normal stack locks 1483 // Input: objReg (object to lock) 1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1485 Register retry_on_abort_count_Reg, 1486 RTMLockingCounters* stack_rtm_counters, 1487 Metadata* method_data, bool profile_rtm, 1488 Label& DONE_LABEL, Label& IsInflated) { 1489 assert(UseRTMForStackLocks, "why call this otherwise?"); 1490 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1491 assert(tmpReg == rax, ""); 1492 assert(scrReg == rdx, ""); 1493 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1494 1495 if (RTMRetryCount > 0) { 1496 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1497 bind(L_rtm_retry); 1498 } 1499 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); 1500 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1501 jcc(Assembler::notZero, IsInflated); 1502 1503 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1504 Label L_noincrement; 1505 if (RTMTotalCountIncrRate > 1) { 1506 // tmpReg, scrReg and flags are killed 1507 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement); 1508 } 1509 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1510 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1511 bind(L_noincrement); 1512 } 1513 xbegin(L_on_abort); 1514 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword 1515 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1516 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1517 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1518 1519 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1520 if (UseRTMXendForLockBusy) { 1521 xend(); 1522 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1523 jmp(L_decrement_retry); 1524 } 1525 else { 1526 xabort(0); 1527 } 1528 bind(L_on_abort); 1529 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1530 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1531 } 1532 bind(L_decrement_retry); 1533 if (RTMRetryCount > 0) { 1534 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1535 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1536 } 1537 } 1538 1539 // Use RTM for inflating locks 1540 // inputs: objReg (object to lock) 1541 // boxReg (on-stack box address (displaced header location) - KILLED) 1542 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1544 Register scrReg, Register retry_on_busy_count_Reg, 1545 Register retry_on_abort_count_Reg, 1546 RTMLockingCounters* rtm_counters, 1547 Metadata* method_data, bool profile_rtm, 1548 Label& DONE_LABEL) { 1549 assert(UseRTMLocking, "why call this otherwise?"); 1550 assert(tmpReg == rax, ""); 1551 assert(scrReg == rdx, ""); 1552 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1553 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1554 1555 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1556 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1557 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1558 1559 if (RTMRetryCount > 0) { 1560 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1561 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1562 bind(L_rtm_retry); 1563 } 1564 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1565 Label L_noincrement; 1566 if (RTMTotalCountIncrRate > 1) { 1567 // tmpReg, scrReg and flags are killed 1568 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement); 1569 } 1570 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1571 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1572 bind(L_noincrement); 1573 } 1574 xbegin(L_on_abort); 1575 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); 1576 movptr(tmpReg, Address(tmpReg, owner_offset)); 1577 testptr(tmpReg, tmpReg); 1578 jcc(Assembler::zero, DONE_LABEL); 1579 if (UseRTMXendForLockBusy) { 1580 xend(); 1581 jmp(L_decrement_retry); 1582 } 1583 else { 1584 xabort(0); 1585 } 1586 bind(L_on_abort); 1587 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1588 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1589 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1590 } 1591 if (RTMRetryCount > 0) { 1592 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1593 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1594 } 1595 1596 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1597 testptr(tmpReg, tmpReg) ; 1598 jccb(Assembler::notZero, L_decrement_retry) ; 1599 1600 // Appears unlocked - try to swing _owner from null to non-null. 1601 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1602 #ifdef _LP64 1603 Register threadReg = r15_thread; 1604 #else 1605 get_thread(scrReg); 1606 Register threadReg = scrReg; 1607 #endif 1608 if (os::is_MP()) { 1609 lock(); 1610 } 1611 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1612 1613 if (RTMRetryCount > 0) { 1614 // success done else retry 1615 jccb(Assembler::equal, DONE_LABEL) ; 1616 bind(L_decrement_retry); 1617 // Spin and retry if lock is busy. 1618 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1619 } 1620 else { 1621 bind(L_decrement_retry); 1622 } 1623 } 1624 1625 #endif // INCLUDE_RTM_OPT 1626 1627 // Fast_Lock and Fast_Unlock used by C2 1628 1629 // Because the transitions from emitted code to the runtime 1630 // monitorenter/exit helper stubs are so slow it's critical that 1631 // we inline both the stack-locking fast-path and the inflated fast path. 1632 // 1633 // See also: cmpFastLock and cmpFastUnlock. 1634 // 1635 // What follows is a specialized inline transliteration of the code 1636 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1637 // another option would be to emit TrySlowEnter and TrySlowExit methods 1638 // at startup-time. These methods would accept arguments as 1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1640 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1642 // In practice, however, the # of lock sites is bounded and is usually small. 1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1644 // if the processor uses simple bimodal branch predictors keyed by EIP 1645 // Since the helper routines would be called from multiple synchronization 1646 // sites. 1647 // 1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1650 // to those specialized methods. That'd give us a mostly platform-independent 1651 // implementation that the JITs could optimize and inline at their pleasure. 1652 // Done correctly, the only time we'd need to cross to native could would be 1653 // to park() or unpark() threads. We'd also need a few more unsafe operators 1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1655 // (b) explicit barriers or fence operations. 1656 // 1657 // TODO: 1658 // 1659 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1660 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1661 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1662 // the lock operators would typically be faster than reifying Self. 1663 // 1664 // * Ideally I'd define the primitives as: 1665 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1666 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1667 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1668 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1669 // Furthermore the register assignments are overconstrained, possibly resulting in 1670 // sub-optimal code near the synchronization site. 1671 // 1672 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1673 // Alternately, use a better sp-proximity test. 1674 // 1675 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1676 // Either one is sufficient to uniquely identify a thread. 1677 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1678 // 1679 // * Intrinsify notify() and notifyAll() for the common cases where the 1680 // object is locked by the calling thread but the waitlist is empty. 1681 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1682 // 1683 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1684 // But beware of excessive branch density on AMD Opterons. 1685 // 1686 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1687 // or failure of the fast-path. If the fast-path fails then we pass 1688 // control to the slow-path, typically in C. In Fast_Lock and 1689 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1690 // will emit a conditional branch immediately after the node. 1691 // So we have branches to branches and lots of ICC.ZF games. 1692 // Instead, it might be better to have C2 pass a "FailureLabel" 1693 // into Fast_Lock and Fast_Unlock. In the case of success, control 1694 // will drop through the node. ICC.ZF is undefined at exit. 1695 // In the case of failure, the node will branch directly to the 1696 // FailureLabel 1697 1698 1699 // obj: object to lock 1700 // box: on-stack box address (displaced header location) - KILLED 1701 // rax,: tmp -- KILLED 1702 // scr: tmp -- KILLED 1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1704 Register scrReg, Register cx1Reg, Register cx2Reg, 1705 BiasedLockingCounters* counters, 1706 RTMLockingCounters* rtm_counters, 1707 RTMLockingCounters* stack_rtm_counters, 1708 Metadata* method_data, 1709 bool use_rtm, bool profile_rtm) { 1710 // Ensure the register assignments are disjoint 1711 assert(tmpReg == rax, ""); 1712 1713 if (use_rtm) { 1714 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1715 } else { 1716 assert(cx1Reg == noreg, ""); 1717 assert(cx2Reg == noreg, ""); 1718 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1719 } 1720 1721 if (counters != NULL) { 1722 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1723 } 1724 if (EmitSync & 1) { 1725 // set box->dhw = markOopDesc::unused_mark() 1726 // Force all sync thru slow-path: slow_enter() and slow_exit() 1727 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1728 cmpptr (rsp, (int32_t)NULL_WORD); 1729 } else { 1730 // Possible cases that we'll encounter in fast_lock 1731 // ------------------------------------------------ 1732 // * Inflated 1733 // -- unlocked 1734 // -- Locked 1735 // = by self 1736 // = by other 1737 // * biased 1738 // -- by Self 1739 // -- by other 1740 // * neutral 1741 // * stack-locked 1742 // -- by self 1743 // = sp-proximity test hits 1744 // = sp-proximity test generates false-negative 1745 // -- by other 1746 // 1747 1748 Label IsInflated, DONE_LABEL; 1749 1750 // it's stack-locked, biased or neutral 1751 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1752 // order to reduce the number of conditional branches in the most common cases. 1753 // Beware -- there's a subtle invariant that fetch of the markword 1754 // at [FETCH], below, will never observe a biased encoding (*101b). 1755 // If this invariant is not held we risk exclusion (safety) failure. 1756 if (UseBiasedLocking && !UseOptoBiasInlining) { 1757 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1758 } 1759 1760 #if INCLUDE_RTM_OPT 1761 if (UseRTMForStackLocks && use_rtm) { 1762 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1763 stack_rtm_counters, method_data, profile_rtm, 1764 DONE_LABEL, IsInflated); 1765 } 1766 #endif // INCLUDE_RTM_OPT 1767 1768 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH] 1769 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1770 jccb(Assembler::notZero, IsInflated); 1771 1772 // Attempt stack-locking ... 1773 orptr (tmpReg, markOopDesc::unlocked_value); 1774 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1775 if (os::is_MP()) { 1776 lock(); 1777 } 1778 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg 1779 if (counters != NULL) { 1780 cond_inc32(Assembler::equal, 1781 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1782 } 1783 jcc(Assembler::equal, DONE_LABEL); // Success 1784 1785 // Recursive locking. 1786 // The object is stack-locked: markword contains stack pointer to BasicLock. 1787 // Locked by current thread if difference with current SP is less than one page. 1788 subptr(tmpReg, rsp); 1789 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1790 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1791 movptr(Address(boxReg, 0), tmpReg); 1792 if (counters != NULL) { 1793 cond_inc32(Assembler::equal, 1794 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1795 } 1796 jmp(DONE_LABEL); 1797 1798 bind(IsInflated); 1799 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1800 1801 #if INCLUDE_RTM_OPT 1802 // Use the same RTM locking code in 32- and 64-bit VM. 1803 if (use_rtm) { 1804 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1805 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1806 } else { 1807 #endif // INCLUDE_RTM_OPT 1808 1809 #ifndef _LP64 1810 // The object is inflated. 1811 1812 // boxReg refers to the on-stack BasicLock in the current frame. 1813 // We'd like to write: 1814 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1815 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1816 // additional latency as we have another ST in the store buffer that must drain. 1817 1818 if (EmitSync & 8192) { 1819 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1820 get_thread (scrReg); 1821 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1822 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1823 if (os::is_MP()) { 1824 lock(); 1825 } 1826 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1827 } else 1828 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1829 // register juggle because we need tmpReg for cmpxchgptr below 1830 movptr(scrReg, boxReg); 1831 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1832 1833 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1834 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1835 // prefetchw [eax + Offset(_owner)-2] 1836 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1837 } 1838 1839 if ((EmitSync & 64) == 0) { 1840 // Optimistic form: consider XORL tmpReg,tmpReg 1841 movptr(tmpReg, NULL_WORD); 1842 } else { 1843 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1844 // Test-And-CAS instead of CAS 1845 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1846 testptr(tmpReg, tmpReg); // Locked ? 1847 jccb (Assembler::notZero, DONE_LABEL); 1848 } 1849 1850 // Appears unlocked - try to swing _owner from null to non-null. 1851 // Ideally, I'd manifest "Self" with get_thread and then attempt 1852 // to CAS the register containing Self into m->Owner. 1853 // But we don't have enough registers, so instead we can either try to CAS 1854 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1855 // we later store "Self" into m->Owner. Transiently storing a stack address 1856 // (rsp or the address of the box) into m->owner is harmless. 1857 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1858 if (os::is_MP()) { 1859 lock(); 1860 } 1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1862 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1863 // If we weren't able to swing _owner from NULL to the BasicLock 1864 // then take the slow path. 1865 jccb (Assembler::notZero, DONE_LABEL); 1866 // update _owner from BasicLock to thread 1867 get_thread (scrReg); // beware: clobbers ICCs 1868 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1869 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1870 1871 // If the CAS fails we can either retry or pass control to the slow-path. 1872 // We use the latter tactic. 1873 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1874 // If the CAS was successful ... 1875 // Self has acquired the lock 1876 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1877 // Intentional fall-through into DONE_LABEL ... 1878 } else { 1879 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1880 movptr(boxReg, tmpReg); 1881 1882 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1883 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1884 // prefetchw [eax + Offset(_owner)-2] 1885 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1886 } 1887 1888 if ((EmitSync & 64) == 0) { 1889 // Optimistic form 1890 xorptr (tmpReg, tmpReg); 1891 } else { 1892 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1893 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1894 testptr(tmpReg, tmpReg); // Locked ? 1895 jccb (Assembler::notZero, DONE_LABEL); 1896 } 1897 1898 // Appears unlocked - try to swing _owner from null to non-null. 1899 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1900 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1901 get_thread (scrReg); 1902 if (os::is_MP()) { 1903 lock(); 1904 } 1905 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1906 1907 // If the CAS fails we can either retry or pass control to the slow-path. 1908 // We use the latter tactic. 1909 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1910 // If the CAS was successful ... 1911 // Self has acquired the lock 1912 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1913 // Intentional fall-through into DONE_LABEL ... 1914 } 1915 #else // _LP64 1916 // It's inflated 1917 movq(scrReg, tmpReg); 1918 xorq(tmpReg, tmpReg); 1919 1920 if (os::is_MP()) { 1921 lock(); 1922 } 1923 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1924 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1925 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1926 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1927 // Intentional fall-through into DONE_LABEL ... 1928 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1929 #endif // _LP64 1930 #if INCLUDE_RTM_OPT 1931 } // use_rtm() 1932 #endif 1933 // DONE_LABEL is a hot target - we'd really like to place it at the 1934 // start of cache line by padding with NOPs. 1935 // See the AMD and Intel software optimization manuals for the 1936 // most efficient "long" NOP encodings. 1937 // Unfortunately none of our alignment mechanisms suffice. 1938 bind(DONE_LABEL); 1939 1940 // At DONE_LABEL the icc ZFlag is set as follows ... 1941 // Fast_Unlock uses the same protocol. 1942 // ZFlag == 1 -> Success 1943 // ZFlag == 0 -> Failure - force control through the slow-path 1944 } 1945 } 1946 1947 // obj: object to unlock 1948 // box: box address (displaced header location), killed. Must be EAX. 1949 // tmp: killed, cannot be obj nor box. 1950 // 1951 // Some commentary on balanced locking: 1952 // 1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1954 // Methods that don't have provably balanced locking are forced to run in the 1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1956 // The interpreter provides two properties: 1957 // I1: At return-time the interpreter automatically and quietly unlocks any 1958 // objects acquired the current activation (frame). Recall that the 1959 // interpreter maintains an on-stack list of locks currently held by 1960 // a frame. 1961 // I2: If a method attempts to unlock an object that is not held by the 1962 // the frame the interpreter throws IMSX. 1963 // 1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1965 // B() doesn't have provably balanced locking so it runs in the interpreter. 1966 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1967 // is still locked by A(). 1968 // 1969 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1971 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1973 // Arguably given that the spec legislates the JNI case as undefined our implementation 1974 // could reasonably *avoid* checking owner in Fast_Unlock(). 1975 // In the interest of performance we elide m->Owner==Self check in unlock. 1976 // A perfectly viable alternative is to elide the owner check except when 1977 // Xcheck:jni is enabled. 1978 1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1980 assert(boxReg == rax, ""); 1981 assert_different_registers(objReg, boxReg, tmpReg); 1982 1983 if (EmitSync & 4) { 1984 // Disable - inhibit all inlining. Force control through the slow-path 1985 cmpptr (rsp, 0); 1986 } else { 1987 Label DONE_LABEL, Stacked, CheckSucc; 1988 1989 // Critically, the biased locking test must have precedence over 1990 // and appear before the (box->dhw == 0) recursive stack-lock test. 1991 if (UseBiasedLocking && !UseOptoBiasInlining) { 1992 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1993 } 1994 1995 #if INCLUDE_RTM_OPT 1996 if (UseRTMForStackLocks && use_rtm) { 1997 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1998 Label L_regular_unlock; 1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword 2000 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 2001 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 2002 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 2003 xend(); // otherwise end... 2004 jmp(DONE_LABEL); // ... and we're done 2005 bind(L_regular_unlock); 2006 } 2007 #endif 2008 2009 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 2010 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 2011 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword 2012 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 2013 jccb (Assembler::zero, Stacked); 2014 2015 // It's inflated. 2016 #if INCLUDE_RTM_OPT 2017 if (use_rtm) { 2018 Label L_regular_inflated_unlock; 2019 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2020 movptr(boxReg, Address(tmpReg, owner_offset)); 2021 testptr(boxReg, boxReg); 2022 jccb(Assembler::notZero, L_regular_inflated_unlock); 2023 xend(); 2024 jmpb(DONE_LABEL); 2025 bind(L_regular_inflated_unlock); 2026 } 2027 #endif 2028 2029 // Despite our balanced locking property we still check that m->_owner == Self 2030 // as java routines or native JNI code called by this thread might 2031 // have released the lock. 2032 // Refer to the comments in synchronizer.cpp for how we might encode extra 2033 // state in _succ so we can avoid fetching EntryList|cxq. 2034 // 2035 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2036 // such as recursive enter and exit -- but we have to be wary of 2037 // I$ bloat, T$ effects and BP$ effects. 2038 // 2039 // If there's no contention try a 1-0 exit. That is, exit without 2040 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2041 // we detect and recover from the race that the 1-0 exit admits. 2042 // 2043 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2044 // before it STs null into _owner, releasing the lock. Updates 2045 // to data protected by the critical section must be visible before 2046 // we drop the lock (and thus before any other thread could acquire 2047 // the lock and observe the fields protected by the lock). 2048 // IA32's memory-model is SPO, so STs are ordered with respect to 2049 // each other and there's no need for an explicit barrier (fence). 2050 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2051 #ifndef _LP64 2052 get_thread (boxReg); 2053 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2054 // prefetchw [ebx + Offset(_owner)-2] 2055 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2056 } 2057 2058 // Note that we could employ various encoding schemes to reduce 2059 // the number of loads below (currently 4) to just 2 or 3. 2060 // Refer to the comments in synchronizer.cpp. 2061 // In practice the chain of fetches doesn't seem to impact performance, however. 2062 xorptr(boxReg, boxReg); 2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2064 // Attempt to reduce branch density - AMD's branch predictor. 2065 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2068 jccb (Assembler::notZero, DONE_LABEL); 2069 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2070 jmpb (DONE_LABEL); 2071 } else { 2072 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2073 jccb (Assembler::notZero, DONE_LABEL); 2074 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2075 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2076 jccb (Assembler::notZero, CheckSucc); 2077 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2078 jmpb (DONE_LABEL); 2079 } 2080 2081 // The Following code fragment (EmitSync & 65536) improves the performance of 2082 // contended applications and contended synchronization microbenchmarks. 2083 // Unfortunately the emission of the code - even though not executed - causes regressions 2084 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2085 // with an equal number of never-executed NOPs results in the same regression. 2086 // We leave it off by default. 2087 2088 if ((EmitSync & 65536) != 0) { 2089 Label LSuccess, LGoSlowPath ; 2090 2091 bind (CheckSucc); 2092 2093 // Optional pre-test ... it's safe to elide this 2094 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2095 jccb(Assembler::zero, LGoSlowPath); 2096 2097 // We have a classic Dekker-style idiom: 2098 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2099 // There are a number of ways to implement the barrier: 2100 // (1) lock:andl &m->_owner, 0 2101 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2102 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2103 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2104 // (2) If supported, an explicit MFENCE is appealing. 2105 // In older IA32 processors MFENCE is slower than lock:add or xchg 2106 // particularly if the write-buffer is full as might be the case if 2107 // if stores closely precede the fence or fence-equivalent instruction. 2108 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2109 // as the situation has changed with Nehalem and Shanghai. 2110 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2111 // The $lines underlying the top-of-stack should be in M-state. 2112 // The locked add instruction is serializing, of course. 2113 // (4) Use xchg, which is serializing 2114 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2115 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2116 // The integer condition codes will tell us if succ was 0. 2117 // Since _succ and _owner should reside in the same $line and 2118 // we just stored into _owner, it's likely that the $line 2119 // remains in M-state for the lock:orl. 2120 // 2121 // We currently use (3), although it's likely that switching to (2) 2122 // is correct for the future. 2123 2124 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2125 if (os::is_MP()) { 2126 lock(); addptr(Address(rsp, 0), 0); 2127 } 2128 // Ratify _succ remains non-null 2129 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2130 jccb (Assembler::notZero, LSuccess); 2131 2132 xorptr(boxReg, boxReg); // box is really EAX 2133 if (os::is_MP()) { lock(); } 2134 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2135 // There's no successor so we tried to regrab the lock with the 2136 // placeholder value. If that didn't work, then another thread 2137 // grabbed the lock so we're done (and exit was a success). 2138 jccb (Assembler::notEqual, LSuccess); 2139 // Since we're low on registers we installed rsp as a placeholding in _owner. 2140 // Now install Self over rsp. This is safe as we're transitioning from 2141 // non-null to non=null 2142 get_thread (boxReg); 2143 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2144 // Intentional fall-through into LGoSlowPath ... 2145 2146 bind (LGoSlowPath); 2147 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2148 jmpb (DONE_LABEL); 2149 2150 bind (LSuccess); 2151 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2152 jmpb (DONE_LABEL); 2153 } 2154 2155 bind (Stacked); 2156 // It's not inflated and it's not recursively stack-locked and it's not biased. 2157 // It must be stack-locked. 2158 // Try to reset the header to displaced header. 2159 // The "box" value on the stack is stable, so we can reload 2160 // and be assured we observe the same value as above. 2161 movptr(tmpReg, Address(boxReg, 0)); 2162 if (os::is_MP()) { 2163 lock(); 2164 } 2165 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box 2166 // Intention fall-thru into DONE_LABEL 2167 2168 // DONE_LABEL is a hot target - we'd really like to place it at the 2169 // start of cache line by padding with NOPs. 2170 // See the AMD and Intel software optimization manuals for the 2171 // most efficient "long" NOP encodings. 2172 // Unfortunately none of our alignment mechanisms suffice. 2173 if ((EmitSync & 65536) == 0) { 2174 bind (CheckSucc); 2175 } 2176 #else // _LP64 2177 // It's inflated 2178 if (EmitSync & 1024) { 2179 // Emit code to check that _owner == Self 2180 // We could fold the _owner test into subsequent code more efficiently 2181 // than using a stand-alone check, but since _owner checking is off by 2182 // default we don't bother. We also might consider predicating the 2183 // _owner==Self check on Xcheck:jni or running on a debug build. 2184 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2185 xorptr(boxReg, r15_thread); 2186 } else { 2187 xorptr(boxReg, boxReg); 2188 } 2189 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2190 jccb (Assembler::notZero, DONE_LABEL); 2191 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2192 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2193 jccb (Assembler::notZero, CheckSucc); 2194 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2195 jmpb (DONE_LABEL); 2196 2197 if ((EmitSync & 65536) == 0) { 2198 // Try to avoid passing control into the slow_path ... 2199 Label LSuccess, LGoSlowPath ; 2200 bind (CheckSucc); 2201 2202 // The following optional optimization can be elided if necessary 2203 // Effectively: if (succ == null) goto SlowPath 2204 // The code reduces the window for a race, however, 2205 // and thus benefits performance. 2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2207 jccb (Assembler::zero, LGoSlowPath); 2208 2209 xorptr(boxReg, boxReg); 2210 if ((EmitSync & 16) && os::is_MP()) { 2211 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2212 } else { 2213 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2214 if (os::is_MP()) { 2215 // Memory barrier/fence 2216 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2217 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2218 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2219 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2220 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2221 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2222 lock(); addl(Address(rsp, 0), 0); 2223 } 2224 } 2225 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2226 jccb (Assembler::notZero, LSuccess); 2227 2228 // Rare inopportune interleaving - race. 2229 // The successor vanished in the small window above. 2230 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2231 // We need to ensure progress and succession. 2232 // Try to reacquire the lock. 2233 // If that fails then the new owner is responsible for succession and this 2234 // thread needs to take no further action and can exit via the fast path (success). 2235 // If the re-acquire succeeds then pass control into the slow path. 2236 // As implemented, this latter mode is horrible because we generated more 2237 // coherence traffic on the lock *and* artifically extended the critical section 2238 // length while by virtue of passing control into the slow path. 2239 2240 // box is really RAX -- the following CMPXCHG depends on that binding 2241 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2242 if (os::is_MP()) { lock(); } 2243 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2244 // There's no successor so we tried to regrab the lock. 2245 // If that didn't work, then another thread grabbed the 2246 // lock so we're done (and exit was a success). 2247 jccb (Assembler::notEqual, LSuccess); 2248 // Intentional fall-through into slow-path 2249 2250 bind (LGoSlowPath); 2251 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2252 jmpb (DONE_LABEL); 2253 2254 bind (LSuccess); 2255 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2256 jmpb (DONE_LABEL); 2257 } 2258 2259 bind (Stacked); 2260 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2261 if (os::is_MP()) { lock(); } 2262 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box 2263 2264 if (EmitSync & 65536) { 2265 bind (CheckSucc); 2266 } 2267 #endif 2268 bind(DONE_LABEL); 2269 } 2270 } 2271 #endif // COMPILER2 2272 2273 void MacroAssembler::c2bool(Register x) { 2274 // implements x == 0 ? 0 : 1 2275 // note: must only look at least-significant byte of x 2276 // since C-style booleans are stored in one byte 2277 // only! (was bug) 2278 andl(x, 0xFF); 2279 setb(Assembler::notZero, x); 2280 } 2281 2282 // Wouldn't need if AddressLiteral version had new name 2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2284 Assembler::call(L, rtype); 2285 } 2286 2287 void MacroAssembler::call(Register entry) { 2288 Assembler::call(entry); 2289 } 2290 2291 void MacroAssembler::call(AddressLiteral entry) { 2292 if (reachable(entry)) { 2293 Assembler::call_literal(entry.target(), entry.rspec()); 2294 } else { 2295 lea(rscratch1, entry); 2296 Assembler::call(rscratch1); 2297 } 2298 } 2299 2300 void MacroAssembler::ic_call(address entry, jint method_index) { 2301 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2302 movptr(rax, (intptr_t)Universe::non_oop_word()); 2303 call(AddressLiteral(entry, rh)); 2304 } 2305 2306 // Implementation of call_VM versions 2307 2308 void MacroAssembler::call_VM(Register oop_result, 2309 address entry_point, 2310 bool check_exceptions) { 2311 Label C, E; 2312 call(C, relocInfo::none); 2313 jmp(E); 2314 2315 bind(C); 2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2317 ret(0); 2318 2319 bind(E); 2320 } 2321 2322 void MacroAssembler::call_VM(Register oop_result, 2323 address entry_point, 2324 Register arg_1, 2325 bool check_exceptions) { 2326 Label C, E; 2327 call(C, relocInfo::none); 2328 jmp(E); 2329 2330 bind(C); 2331 pass_arg1(this, arg_1); 2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2333 ret(0); 2334 2335 bind(E); 2336 } 2337 2338 void MacroAssembler::call_VM(Register oop_result, 2339 address entry_point, 2340 Register arg_1, 2341 Register arg_2, 2342 bool check_exceptions) { 2343 Label C, E; 2344 call(C, relocInfo::none); 2345 jmp(E); 2346 2347 bind(C); 2348 2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2350 2351 pass_arg2(this, arg_2); 2352 pass_arg1(this, arg_1); 2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2354 ret(0); 2355 2356 bind(E); 2357 } 2358 2359 void MacroAssembler::call_VM(Register oop_result, 2360 address entry_point, 2361 Register arg_1, 2362 Register arg_2, 2363 Register arg_3, 2364 bool check_exceptions) { 2365 Label C, E; 2366 call(C, relocInfo::none); 2367 jmp(E); 2368 2369 bind(C); 2370 2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2373 pass_arg3(this, arg_3); 2374 2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2376 pass_arg2(this, arg_2); 2377 2378 pass_arg1(this, arg_1); 2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2380 ret(0); 2381 2382 bind(E); 2383 } 2384 2385 void MacroAssembler::call_VM(Register oop_result, 2386 Register last_java_sp, 2387 address entry_point, 2388 int number_of_arguments, 2389 bool check_exceptions) { 2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2392 } 2393 2394 void MacroAssembler::call_VM(Register oop_result, 2395 Register last_java_sp, 2396 address entry_point, 2397 Register arg_1, 2398 bool check_exceptions) { 2399 pass_arg1(this, arg_1); 2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2401 } 2402 2403 void MacroAssembler::call_VM(Register oop_result, 2404 Register last_java_sp, 2405 address entry_point, 2406 Register arg_1, 2407 Register arg_2, 2408 bool check_exceptions) { 2409 2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2411 pass_arg2(this, arg_2); 2412 pass_arg1(this, arg_1); 2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2414 } 2415 2416 void MacroAssembler::call_VM(Register oop_result, 2417 Register last_java_sp, 2418 address entry_point, 2419 Register arg_1, 2420 Register arg_2, 2421 Register arg_3, 2422 bool check_exceptions) { 2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2425 pass_arg3(this, arg_3); 2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2427 pass_arg2(this, arg_2); 2428 pass_arg1(this, arg_1); 2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2430 } 2431 2432 void MacroAssembler::super_call_VM(Register oop_result, 2433 Register last_java_sp, 2434 address entry_point, 2435 int number_of_arguments, 2436 bool check_exceptions) { 2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2439 } 2440 2441 void MacroAssembler::super_call_VM(Register oop_result, 2442 Register last_java_sp, 2443 address entry_point, 2444 Register arg_1, 2445 bool check_exceptions) { 2446 pass_arg1(this, arg_1); 2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2448 } 2449 2450 void MacroAssembler::super_call_VM(Register oop_result, 2451 Register last_java_sp, 2452 address entry_point, 2453 Register arg_1, 2454 Register arg_2, 2455 bool check_exceptions) { 2456 2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2458 pass_arg2(this, arg_2); 2459 pass_arg1(this, arg_1); 2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2461 } 2462 2463 void MacroAssembler::super_call_VM(Register oop_result, 2464 Register last_java_sp, 2465 address entry_point, 2466 Register arg_1, 2467 Register arg_2, 2468 Register arg_3, 2469 bool check_exceptions) { 2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2472 pass_arg3(this, arg_3); 2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2474 pass_arg2(this, arg_2); 2475 pass_arg1(this, arg_1); 2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2477 } 2478 2479 void MacroAssembler::call_VM_base(Register oop_result, 2480 Register java_thread, 2481 Register last_java_sp, 2482 address entry_point, 2483 int number_of_arguments, 2484 bool check_exceptions) { 2485 // determine java_thread register 2486 if (!java_thread->is_valid()) { 2487 #ifdef _LP64 2488 java_thread = r15_thread; 2489 #else 2490 java_thread = rdi; 2491 get_thread(java_thread); 2492 #endif // LP64 2493 } 2494 // determine last_java_sp register 2495 if (!last_java_sp->is_valid()) { 2496 last_java_sp = rsp; 2497 } 2498 // debugging support 2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2501 #ifdef ASSERT 2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2503 // r12 is the heapbase. 2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2505 #endif // ASSERT 2506 2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2509 2510 // push java thread (becomes first argument of C function) 2511 2512 NOT_LP64(push(java_thread); number_of_arguments++); 2513 LP64_ONLY(mov(c_rarg0, r15_thread)); 2514 2515 // set last Java frame before call 2516 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2517 2518 // Only interpreter should have to set fp 2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2520 2521 // do the call, remove parameters 2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2523 2524 // restore the thread (cannot use the pushed argument since arguments 2525 // may be overwritten by C code generated by an optimizing compiler); 2526 // however can use the register value directly if it is callee saved. 2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2528 // rdi & rsi (also r15) are callee saved -> nothing to do 2529 #ifdef ASSERT 2530 guarantee(java_thread != rax, "change this code"); 2531 push(rax); 2532 { Label L; 2533 get_thread(rax); 2534 cmpptr(java_thread, rax); 2535 jcc(Assembler::equal, L); 2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2537 bind(L); 2538 } 2539 pop(rax); 2540 #endif 2541 } else { 2542 get_thread(java_thread); 2543 } 2544 // reset last Java frame 2545 // Only interpreter should have to clear fp 2546 reset_last_Java_frame(java_thread, true); 2547 2548 // C++ interp handles this in the interpreter 2549 check_and_handle_popframe(java_thread); 2550 check_and_handle_earlyret(java_thread); 2551 2552 if (check_exceptions) { 2553 // check for pending exceptions (java_thread is set upon return) 2554 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2555 #ifndef _LP64 2556 jump_cc(Assembler::notEqual, 2557 RuntimeAddress(StubRoutines::forward_exception_entry())); 2558 #else 2559 // This used to conditionally jump to forward_exception however it is 2560 // possible if we relocate that the branch will not reach. So we must jump 2561 // around so we can always reach 2562 2563 Label ok; 2564 jcc(Assembler::equal, ok); 2565 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2566 bind(ok); 2567 #endif // LP64 2568 } 2569 2570 // get oop result if there is one and reset the value in the thread 2571 if (oop_result->is_valid()) { 2572 get_vm_result(oop_result, java_thread); 2573 } 2574 } 2575 2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2577 2578 // Calculate the value for last_Java_sp 2579 // somewhat subtle. call_VM does an intermediate call 2580 // which places a return address on the stack just under the 2581 // stack pointer as the user finsihed with it. This allows 2582 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2583 // On 32bit we then have to push additional args on the stack to accomplish 2584 // the actual requested call. On 64bit call_VM only can use register args 2585 // so the only extra space is the return address that call_VM created. 2586 // This hopefully explains the calculations here. 2587 2588 #ifdef _LP64 2589 // We've pushed one address, correct last_Java_sp 2590 lea(rax, Address(rsp, wordSize)); 2591 #else 2592 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2593 #endif // LP64 2594 2595 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2596 2597 } 2598 2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2600 void MacroAssembler::call_VM_leaf0(address entry_point) { 2601 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2602 } 2603 2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2605 call_VM_leaf_base(entry_point, number_of_arguments); 2606 } 2607 2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2609 pass_arg0(this, arg_0); 2610 call_VM_leaf(entry_point, 1); 2611 } 2612 2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2614 2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2616 pass_arg1(this, arg_1); 2617 pass_arg0(this, arg_0); 2618 call_VM_leaf(entry_point, 2); 2619 } 2620 2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2622 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2623 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2624 pass_arg2(this, arg_2); 2625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2626 pass_arg1(this, arg_1); 2627 pass_arg0(this, arg_0); 2628 call_VM_leaf(entry_point, 3); 2629 } 2630 2631 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2632 pass_arg0(this, arg_0); 2633 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2634 } 2635 2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2637 2638 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2639 pass_arg1(this, arg_1); 2640 pass_arg0(this, arg_0); 2641 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2642 } 2643 2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2647 pass_arg2(this, arg_2); 2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2649 pass_arg1(this, arg_1); 2650 pass_arg0(this, arg_0); 2651 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2652 } 2653 2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2655 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2656 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2657 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2658 pass_arg3(this, arg_3); 2659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2661 pass_arg2(this, arg_2); 2662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2663 pass_arg1(this, arg_1); 2664 pass_arg0(this, arg_0); 2665 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2666 } 2667 2668 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2669 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2670 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2671 verify_oop(oop_result, "broken oop in call_VM_base"); 2672 } 2673 2674 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2675 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2676 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2677 } 2678 2679 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2680 } 2681 2682 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2683 } 2684 2685 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2686 if (reachable(src1)) { 2687 cmpl(as_Address(src1), imm); 2688 } else { 2689 lea(rscratch1, src1); 2690 cmpl(Address(rscratch1, 0), imm); 2691 } 2692 } 2693 2694 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2695 assert(!src2.is_lval(), "use cmpptr"); 2696 if (reachable(src2)) { 2697 cmpl(src1, as_Address(src2)); 2698 } else { 2699 lea(rscratch1, src2); 2700 cmpl(src1, Address(rscratch1, 0)); 2701 } 2702 } 2703 2704 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2705 Assembler::cmpl(src1, imm); 2706 } 2707 2708 void MacroAssembler::cmp32(Register src1, Address src2) { 2709 Assembler::cmpl(src1, src2); 2710 } 2711 2712 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2713 ucomisd(opr1, opr2); 2714 2715 Label L; 2716 if (unordered_is_less) { 2717 movl(dst, -1); 2718 jcc(Assembler::parity, L); 2719 jcc(Assembler::below , L); 2720 movl(dst, 0); 2721 jcc(Assembler::equal , L); 2722 increment(dst); 2723 } else { // unordered is greater 2724 movl(dst, 1); 2725 jcc(Assembler::parity, L); 2726 jcc(Assembler::above , L); 2727 movl(dst, 0); 2728 jcc(Assembler::equal , L); 2729 decrementl(dst); 2730 } 2731 bind(L); 2732 } 2733 2734 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2735 ucomiss(opr1, opr2); 2736 2737 Label L; 2738 if (unordered_is_less) { 2739 movl(dst, -1); 2740 jcc(Assembler::parity, L); 2741 jcc(Assembler::below , L); 2742 movl(dst, 0); 2743 jcc(Assembler::equal , L); 2744 increment(dst); 2745 } else { // unordered is greater 2746 movl(dst, 1); 2747 jcc(Assembler::parity, L); 2748 jcc(Assembler::above , L); 2749 movl(dst, 0); 2750 jcc(Assembler::equal , L); 2751 decrementl(dst); 2752 } 2753 bind(L); 2754 } 2755 2756 2757 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2758 if (reachable(src1)) { 2759 cmpb(as_Address(src1), imm); 2760 } else { 2761 lea(rscratch1, src1); 2762 cmpb(Address(rscratch1, 0), imm); 2763 } 2764 } 2765 2766 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2767 #ifdef _LP64 2768 if (src2.is_lval()) { 2769 movptr(rscratch1, src2); 2770 Assembler::cmpq(src1, rscratch1); 2771 } else if (reachable(src2)) { 2772 cmpq(src1, as_Address(src2)); 2773 } else { 2774 lea(rscratch1, src2); 2775 Assembler::cmpq(src1, Address(rscratch1, 0)); 2776 } 2777 #else 2778 if (src2.is_lval()) { 2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2780 } else { 2781 cmpl(src1, as_Address(src2)); 2782 } 2783 #endif // _LP64 2784 } 2785 2786 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2787 assert(src2.is_lval(), "not a mem-mem compare"); 2788 #ifdef _LP64 2789 // moves src2's literal address 2790 movptr(rscratch1, src2); 2791 Assembler::cmpq(src1, rscratch1); 2792 #else 2793 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2794 #endif // _LP64 2795 } 2796 2797 void MacroAssembler::cmpoop(Register src1, Register src2) { 2798 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 2799 bs->obj_equals(this, src1, src2); 2800 } 2801 2802 void MacroAssembler::cmpoop(Register src1, Address src2) { 2803 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 2804 bs->obj_equals(this, src1, src2); 2805 } 2806 2807 #ifdef _LP64 2808 void MacroAssembler::cmpoop(Register src1, jobject src2) { 2809 movoop(rscratch1, src2); 2810 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 2811 bs->obj_equals(this, src1, rscratch1); 2812 } 2813 #endif 2814 2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2816 if (reachable(adr)) { 2817 if (os::is_MP()) 2818 lock(); 2819 cmpxchgptr(reg, as_Address(adr)); 2820 } else { 2821 lea(rscratch1, adr); 2822 if (os::is_MP()) 2823 lock(); 2824 cmpxchgptr(reg, Address(rscratch1, 0)); 2825 } 2826 } 2827 2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2829 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2830 } 2831 2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2833 if (reachable(src)) { 2834 Assembler::comisd(dst, as_Address(src)); 2835 } else { 2836 lea(rscratch1, src); 2837 Assembler::comisd(dst, Address(rscratch1, 0)); 2838 } 2839 } 2840 2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2842 if (reachable(src)) { 2843 Assembler::comiss(dst, as_Address(src)); 2844 } else { 2845 lea(rscratch1, src); 2846 Assembler::comiss(dst, Address(rscratch1, 0)); 2847 } 2848 } 2849 2850 2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2852 Condition negated_cond = negate_condition(cond); 2853 Label L; 2854 jcc(negated_cond, L); 2855 pushf(); // Preserve flags 2856 atomic_incl(counter_addr); 2857 popf(); 2858 bind(L); 2859 } 2860 2861 int MacroAssembler::corrected_idivl(Register reg) { 2862 // Full implementation of Java idiv and irem; checks for 2863 // special case as described in JVM spec., p.243 & p.271. 2864 // The function returns the (pc) offset of the idivl 2865 // instruction - may be needed for implicit exceptions. 2866 // 2867 // normal case special case 2868 // 2869 // input : rax,: dividend min_int 2870 // reg: divisor (may not be rax,/rdx) -1 2871 // 2872 // output: rax,: quotient (= rax, idiv reg) min_int 2873 // rdx: remainder (= rax, irem reg) 0 2874 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2875 const int min_int = 0x80000000; 2876 Label normal_case, special_case; 2877 2878 // check for special case 2879 cmpl(rax, min_int); 2880 jcc(Assembler::notEqual, normal_case); 2881 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2882 cmpl(reg, -1); 2883 jcc(Assembler::equal, special_case); 2884 2885 // handle normal case 2886 bind(normal_case); 2887 cdql(); 2888 int idivl_offset = offset(); 2889 idivl(reg); 2890 2891 // normal and special case exit 2892 bind(special_case); 2893 2894 return idivl_offset; 2895 } 2896 2897 2898 2899 void MacroAssembler::decrementl(Register reg, int value) { 2900 if (value == min_jint) {subl(reg, value) ; return; } 2901 if (value < 0) { incrementl(reg, -value); return; } 2902 if (value == 0) { ; return; } 2903 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2904 /* else */ { subl(reg, value) ; return; } 2905 } 2906 2907 void MacroAssembler::decrementl(Address dst, int value) { 2908 if (value == min_jint) {subl(dst, value) ; return; } 2909 if (value < 0) { incrementl(dst, -value); return; } 2910 if (value == 0) { ; return; } 2911 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2912 /* else */ { subl(dst, value) ; return; } 2913 } 2914 2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2916 assert (shift_value > 0, "illegal shift value"); 2917 Label _is_positive; 2918 testl (reg, reg); 2919 jcc (Assembler::positive, _is_positive); 2920 int offset = (1 << shift_value) - 1 ; 2921 2922 if (offset == 1) { 2923 incrementl(reg); 2924 } else { 2925 addl(reg, offset); 2926 } 2927 2928 bind (_is_positive); 2929 sarl(reg, shift_value); 2930 } 2931 2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2933 if (reachable(src)) { 2934 Assembler::divsd(dst, as_Address(src)); 2935 } else { 2936 lea(rscratch1, src); 2937 Assembler::divsd(dst, Address(rscratch1, 0)); 2938 } 2939 } 2940 2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2942 if (reachable(src)) { 2943 Assembler::divss(dst, as_Address(src)); 2944 } else { 2945 lea(rscratch1, src); 2946 Assembler::divss(dst, Address(rscratch1, 0)); 2947 } 2948 } 2949 2950 // !defined(COMPILER2) is because of stupid core builds 2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2952 void MacroAssembler::empty_FPU_stack() { 2953 if (VM_Version::supports_mmx()) { 2954 emms(); 2955 } else { 2956 for (int i = 8; i-- > 0; ) ffree(i); 2957 } 2958 } 2959 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2960 2961 2962 void MacroAssembler::enter() { 2963 push(rbp); 2964 mov(rbp, rsp); 2965 } 2966 2967 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2968 void MacroAssembler::fat_nop() { 2969 if (UseAddressNop) { 2970 addr_nop_5(); 2971 } else { 2972 emit_int8(0x26); // es: 2973 emit_int8(0x2e); // cs: 2974 emit_int8(0x64); // fs: 2975 emit_int8(0x65); // gs: 2976 emit_int8((unsigned char)0x90); 2977 } 2978 } 2979 2980 void MacroAssembler::fcmp(Register tmp) { 2981 fcmp(tmp, 1, true, true); 2982 } 2983 2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2985 assert(!pop_right || pop_left, "usage error"); 2986 if (VM_Version::supports_cmov()) { 2987 assert(tmp == noreg, "unneeded temp"); 2988 if (pop_left) { 2989 fucomip(index); 2990 } else { 2991 fucomi(index); 2992 } 2993 if (pop_right) { 2994 fpop(); 2995 } 2996 } else { 2997 assert(tmp != noreg, "need temp"); 2998 if (pop_left) { 2999 if (pop_right) { 3000 fcompp(); 3001 } else { 3002 fcomp(index); 3003 } 3004 } else { 3005 fcom(index); 3006 } 3007 // convert FPU condition into eflags condition via rax, 3008 save_rax(tmp); 3009 fwait(); fnstsw_ax(); 3010 sahf(); 3011 restore_rax(tmp); 3012 } 3013 // condition codes set as follows: 3014 // 3015 // CF (corresponds to C0) if x < y 3016 // PF (corresponds to C2) if unordered 3017 // ZF (corresponds to C3) if x = y 3018 } 3019 3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3021 fcmp2int(dst, unordered_is_less, 1, true, true); 3022 } 3023 3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3025 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3026 Label L; 3027 if (unordered_is_less) { 3028 movl(dst, -1); 3029 jcc(Assembler::parity, L); 3030 jcc(Assembler::below , L); 3031 movl(dst, 0); 3032 jcc(Assembler::equal , L); 3033 increment(dst); 3034 } else { // unordered is greater 3035 movl(dst, 1); 3036 jcc(Assembler::parity, L); 3037 jcc(Assembler::above , L); 3038 movl(dst, 0); 3039 jcc(Assembler::equal , L); 3040 decrementl(dst); 3041 } 3042 bind(L); 3043 } 3044 3045 void MacroAssembler::fld_d(AddressLiteral src) { 3046 fld_d(as_Address(src)); 3047 } 3048 3049 void MacroAssembler::fld_s(AddressLiteral src) { 3050 fld_s(as_Address(src)); 3051 } 3052 3053 void MacroAssembler::fld_x(AddressLiteral src) { 3054 Assembler::fld_x(as_Address(src)); 3055 } 3056 3057 void MacroAssembler::fldcw(AddressLiteral src) { 3058 Assembler::fldcw(as_Address(src)); 3059 } 3060 3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3062 if (reachable(src)) { 3063 Assembler::mulpd(dst, as_Address(src)); 3064 } else { 3065 lea(rscratch1, src); 3066 Assembler::mulpd(dst, Address(rscratch1, 0)); 3067 } 3068 } 3069 3070 void MacroAssembler::increase_precision() { 3071 subptr(rsp, BytesPerWord); 3072 fnstcw(Address(rsp, 0)); 3073 movl(rax, Address(rsp, 0)); 3074 orl(rax, 0x300); 3075 push(rax); 3076 fldcw(Address(rsp, 0)); 3077 pop(rax); 3078 } 3079 3080 void MacroAssembler::restore_precision() { 3081 fldcw(Address(rsp, 0)); 3082 addptr(rsp, BytesPerWord); 3083 } 3084 3085 void MacroAssembler::fpop() { 3086 ffree(); 3087 fincstp(); 3088 } 3089 3090 void MacroAssembler::load_float(Address src) { 3091 if (UseSSE >= 1) { 3092 movflt(xmm0, src); 3093 } else { 3094 LP64_ONLY(ShouldNotReachHere()); 3095 NOT_LP64(fld_s(src)); 3096 } 3097 } 3098 3099 void MacroAssembler::store_float(Address dst) { 3100 if (UseSSE >= 1) { 3101 movflt(dst, xmm0); 3102 } else { 3103 LP64_ONLY(ShouldNotReachHere()); 3104 NOT_LP64(fstp_s(dst)); 3105 } 3106 } 3107 3108 void MacroAssembler::load_double(Address src) { 3109 if (UseSSE >= 2) { 3110 movdbl(xmm0, src); 3111 } else { 3112 LP64_ONLY(ShouldNotReachHere()); 3113 NOT_LP64(fld_d(src)); 3114 } 3115 } 3116 3117 void MacroAssembler::store_double(Address dst) { 3118 if (UseSSE >= 2) { 3119 movdbl(dst, xmm0); 3120 } else { 3121 LP64_ONLY(ShouldNotReachHere()); 3122 NOT_LP64(fstp_d(dst)); 3123 } 3124 } 3125 3126 void MacroAssembler::fremr(Register tmp) { 3127 save_rax(tmp); 3128 { Label L; 3129 bind(L); 3130 fprem(); 3131 fwait(); fnstsw_ax(); 3132 #ifdef _LP64 3133 testl(rax, 0x400); 3134 jcc(Assembler::notEqual, L); 3135 #else 3136 sahf(); 3137 jcc(Assembler::parity, L); 3138 #endif // _LP64 3139 } 3140 restore_rax(tmp); 3141 // Result is in ST0. 3142 // Note: fxch & fpop to get rid of ST1 3143 // (otherwise FPU stack could overflow eventually) 3144 fxch(1); 3145 fpop(); 3146 } 3147 3148 // dst = c = a * b + c 3149 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3150 Assembler::vfmadd231sd(c, a, b); 3151 if (dst != c) { 3152 movdbl(dst, c); 3153 } 3154 } 3155 3156 // dst = c = a * b + c 3157 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3158 Assembler::vfmadd231ss(c, a, b); 3159 if (dst != c) { 3160 movflt(dst, c); 3161 } 3162 } 3163 3164 // dst = c = a * b + c 3165 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 3166 Assembler::vfmadd231pd(c, a, b, vector_len); 3167 if (dst != c) { 3168 vmovdqu(dst, c); 3169 } 3170 } 3171 3172 // dst = c = a * b + c 3173 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 3174 Assembler::vfmadd231ps(c, a, b, vector_len); 3175 if (dst != c) { 3176 vmovdqu(dst, c); 3177 } 3178 } 3179 3180 // dst = c = a * b + c 3181 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 3182 Assembler::vfmadd231pd(c, a, b, vector_len); 3183 if (dst != c) { 3184 vmovdqu(dst, c); 3185 } 3186 } 3187 3188 // dst = c = a * b + c 3189 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 3190 Assembler::vfmadd231ps(c, a, b, vector_len); 3191 if (dst != c) { 3192 vmovdqu(dst, c); 3193 } 3194 } 3195 3196 void MacroAssembler::incrementl(AddressLiteral dst) { 3197 if (reachable(dst)) { 3198 incrementl(as_Address(dst)); 3199 } else { 3200 lea(rscratch1, dst); 3201 incrementl(Address(rscratch1, 0)); 3202 } 3203 } 3204 3205 void MacroAssembler::incrementl(ArrayAddress dst) { 3206 incrementl(as_Address(dst)); 3207 } 3208 3209 void MacroAssembler::incrementl(Register reg, int value) { 3210 if (value == min_jint) {addl(reg, value) ; return; } 3211 if (value < 0) { decrementl(reg, -value); return; } 3212 if (value == 0) { ; return; } 3213 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3214 /* else */ { addl(reg, value) ; return; } 3215 } 3216 3217 void MacroAssembler::incrementl(Address dst, int value) { 3218 if (value == min_jint) {addl(dst, value) ; return; } 3219 if (value < 0) { decrementl(dst, -value); return; } 3220 if (value == 0) { ; return; } 3221 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3222 /* else */ { addl(dst, value) ; return; } 3223 } 3224 3225 void MacroAssembler::jump(AddressLiteral dst) { 3226 if (reachable(dst)) { 3227 jmp_literal(dst.target(), dst.rspec()); 3228 } else { 3229 lea(rscratch1, dst); 3230 jmp(rscratch1); 3231 } 3232 } 3233 3234 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3235 if (reachable(dst)) { 3236 InstructionMark im(this); 3237 relocate(dst.reloc()); 3238 const int short_size = 2; 3239 const int long_size = 6; 3240 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3241 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3242 // 0111 tttn #8-bit disp 3243 emit_int8(0x70 | cc); 3244 emit_int8((offs - short_size) & 0xFF); 3245 } else { 3246 // 0000 1111 1000 tttn #32-bit disp 3247 emit_int8(0x0F); 3248 emit_int8((unsigned char)(0x80 | cc)); 3249 emit_int32(offs - long_size); 3250 } 3251 } else { 3252 #ifdef ASSERT 3253 warning("reversing conditional branch"); 3254 #endif /* ASSERT */ 3255 Label skip; 3256 jccb(reverse[cc], skip); 3257 lea(rscratch1, dst); 3258 Assembler::jmp(rscratch1); 3259 bind(skip); 3260 } 3261 } 3262 3263 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3264 if (reachable(src)) { 3265 Assembler::ldmxcsr(as_Address(src)); 3266 } else { 3267 lea(rscratch1, src); 3268 Assembler::ldmxcsr(Address(rscratch1, 0)); 3269 } 3270 } 3271 3272 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3273 int off; 3274 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3275 off = offset(); 3276 movsbl(dst, src); // movsxb 3277 } else { 3278 off = load_unsigned_byte(dst, src); 3279 shll(dst, 24); 3280 sarl(dst, 24); 3281 } 3282 return off; 3283 } 3284 3285 // Note: load_signed_short used to be called load_signed_word. 3286 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3287 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3288 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3289 int MacroAssembler::load_signed_short(Register dst, Address src) { 3290 int off; 3291 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3292 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3293 // version but this is what 64bit has always done. This seems to imply 3294 // that users are only using 32bits worth. 3295 off = offset(); 3296 movswl(dst, src); // movsxw 3297 } else { 3298 off = load_unsigned_short(dst, src); 3299 shll(dst, 16); 3300 sarl(dst, 16); 3301 } 3302 return off; 3303 } 3304 3305 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3306 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3307 // and "3.9 Partial Register Penalties", p. 22). 3308 int off; 3309 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3310 off = offset(); 3311 movzbl(dst, src); // movzxb 3312 } else { 3313 xorl(dst, dst); 3314 off = offset(); 3315 movb(dst, src); 3316 } 3317 return off; 3318 } 3319 3320 // Note: load_unsigned_short used to be called load_unsigned_word. 3321 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3322 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3323 // and "3.9 Partial Register Penalties", p. 22). 3324 int off; 3325 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3326 off = offset(); 3327 movzwl(dst, src); // movzxw 3328 } else { 3329 xorl(dst, dst); 3330 off = offset(); 3331 movw(dst, src); 3332 } 3333 return off; 3334 } 3335 3336 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3337 switch (size_in_bytes) { 3338 #ifndef _LP64 3339 case 8: 3340 assert(dst2 != noreg, "second dest register required"); 3341 movl(dst, src); 3342 movl(dst2, src.plus_disp(BytesPerInt)); 3343 break; 3344 #else 3345 case 8: movq(dst, src); break; 3346 #endif 3347 case 4: movl(dst, src); break; 3348 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3349 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3350 default: ShouldNotReachHere(); 3351 } 3352 } 3353 3354 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3355 switch (size_in_bytes) { 3356 #ifndef _LP64 3357 case 8: 3358 assert(src2 != noreg, "second source register required"); 3359 movl(dst, src); 3360 movl(dst.plus_disp(BytesPerInt), src2); 3361 break; 3362 #else 3363 case 8: movq(dst, src); break; 3364 #endif 3365 case 4: movl(dst, src); break; 3366 case 2: movw(dst, src); break; 3367 case 1: movb(dst, src); break; 3368 default: ShouldNotReachHere(); 3369 } 3370 } 3371 3372 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3373 if (reachable(dst)) { 3374 movl(as_Address(dst), src); 3375 } else { 3376 lea(rscratch1, dst); 3377 movl(Address(rscratch1, 0), src); 3378 } 3379 } 3380 3381 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3382 if (reachable(src)) { 3383 movl(dst, as_Address(src)); 3384 } else { 3385 lea(rscratch1, src); 3386 movl(dst, Address(rscratch1, 0)); 3387 } 3388 } 3389 3390 // C++ bool manipulation 3391 3392 void MacroAssembler::movbool(Register dst, Address src) { 3393 if(sizeof(bool) == 1) 3394 movb(dst, src); 3395 else if(sizeof(bool) == 2) 3396 movw(dst, src); 3397 else if(sizeof(bool) == 4) 3398 movl(dst, src); 3399 else 3400 // unsupported 3401 ShouldNotReachHere(); 3402 } 3403 3404 void MacroAssembler::movbool(Address dst, bool boolconst) { 3405 if(sizeof(bool) == 1) 3406 movb(dst, (int) boolconst); 3407 else if(sizeof(bool) == 2) 3408 movw(dst, (int) boolconst); 3409 else if(sizeof(bool) == 4) 3410 movl(dst, (int) boolconst); 3411 else 3412 // unsupported 3413 ShouldNotReachHere(); 3414 } 3415 3416 void MacroAssembler::movbool(Address dst, Register src) { 3417 if(sizeof(bool) == 1) 3418 movb(dst, src); 3419 else if(sizeof(bool) == 2) 3420 movw(dst, src); 3421 else if(sizeof(bool) == 4) 3422 movl(dst, src); 3423 else 3424 // unsupported 3425 ShouldNotReachHere(); 3426 } 3427 3428 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3429 movb(as_Address(dst), src); 3430 } 3431 3432 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3433 if (reachable(src)) { 3434 movdl(dst, as_Address(src)); 3435 } else { 3436 lea(rscratch1, src); 3437 movdl(dst, Address(rscratch1, 0)); 3438 } 3439 } 3440 3441 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3442 if (reachable(src)) { 3443 movq(dst, as_Address(src)); 3444 } else { 3445 lea(rscratch1, src); 3446 movq(dst, Address(rscratch1, 0)); 3447 } 3448 } 3449 3450 void MacroAssembler::setvectmask(Register dst, Register src) { 3451 Assembler::movl(dst, 1); 3452 Assembler::shlxl(dst, dst, src); 3453 Assembler::decl(dst); 3454 Assembler::kmovdl(k1, dst); 3455 Assembler::movl(dst, src); 3456 } 3457 3458 void MacroAssembler::restorevectmask() { 3459 Assembler::knotwl(k1, k0); 3460 } 3461 3462 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3463 if (reachable(src)) { 3464 if (UseXmmLoadAndClearUpper) { 3465 movsd (dst, as_Address(src)); 3466 } else { 3467 movlpd(dst, as_Address(src)); 3468 } 3469 } else { 3470 lea(rscratch1, src); 3471 if (UseXmmLoadAndClearUpper) { 3472 movsd (dst, Address(rscratch1, 0)); 3473 } else { 3474 movlpd(dst, Address(rscratch1, 0)); 3475 } 3476 } 3477 } 3478 3479 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3480 if (reachable(src)) { 3481 movss(dst, as_Address(src)); 3482 } else { 3483 lea(rscratch1, src); 3484 movss(dst, Address(rscratch1, 0)); 3485 } 3486 } 3487 3488 void MacroAssembler::movptr(Register dst, Register src) { 3489 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3490 } 3491 3492 void MacroAssembler::movptr(Register dst, Address src) { 3493 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3494 } 3495 3496 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3497 void MacroAssembler::movptr(Register dst, intptr_t src) { 3498 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3499 } 3500 3501 void MacroAssembler::movptr(Address dst, Register src) { 3502 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3503 } 3504 3505 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3506 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3507 Assembler::vextractf32x4(dst, src, 0); 3508 } else { 3509 Assembler::movdqu(dst, src); 3510 } 3511 } 3512 3513 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3514 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3515 Assembler::vinsertf32x4(dst, dst, src, 0); 3516 } else { 3517 Assembler::movdqu(dst, src); 3518 } 3519 } 3520 3521 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3522 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3523 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3524 } else { 3525 Assembler::movdqu(dst, src); 3526 } 3527 } 3528 3529 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 3530 if (reachable(src)) { 3531 movdqu(dst, as_Address(src)); 3532 } else { 3533 lea(scratchReg, src); 3534 movdqu(dst, Address(scratchReg, 0)); 3535 } 3536 } 3537 3538 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3539 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3540 vextractf64x4_low(dst, src); 3541 } else { 3542 Assembler::vmovdqu(dst, src); 3543 } 3544 } 3545 3546 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3547 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3548 vinsertf64x4_low(dst, src); 3549 } else { 3550 Assembler::vmovdqu(dst, src); 3551 } 3552 } 3553 3554 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3555 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3556 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3557 } 3558 else { 3559 Assembler::vmovdqu(dst, src); 3560 } 3561 } 3562 3563 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3564 if (reachable(src)) { 3565 vmovdqu(dst, as_Address(src)); 3566 } 3567 else { 3568 lea(rscratch1, src); 3569 vmovdqu(dst, Address(rscratch1, 0)); 3570 } 3571 } 3572 3573 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3574 if (reachable(src)) { 3575 Assembler::movdqa(dst, as_Address(src)); 3576 } else { 3577 lea(rscratch1, src); 3578 Assembler::movdqa(dst, Address(rscratch1, 0)); 3579 } 3580 } 3581 3582 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3583 if (reachable(src)) { 3584 Assembler::movsd(dst, as_Address(src)); 3585 } else { 3586 lea(rscratch1, src); 3587 Assembler::movsd(dst, Address(rscratch1, 0)); 3588 } 3589 } 3590 3591 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3592 if (reachable(src)) { 3593 Assembler::movss(dst, as_Address(src)); 3594 } else { 3595 lea(rscratch1, src); 3596 Assembler::movss(dst, Address(rscratch1, 0)); 3597 } 3598 } 3599 3600 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3601 if (reachable(src)) { 3602 Assembler::mulsd(dst, as_Address(src)); 3603 } else { 3604 lea(rscratch1, src); 3605 Assembler::mulsd(dst, Address(rscratch1, 0)); 3606 } 3607 } 3608 3609 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3610 if (reachable(src)) { 3611 Assembler::mulss(dst, as_Address(src)); 3612 } else { 3613 lea(rscratch1, src); 3614 Assembler::mulss(dst, Address(rscratch1, 0)); 3615 } 3616 } 3617 3618 void MacroAssembler::null_check(Register reg, int offset) { 3619 if (needs_explicit_null_check(offset)) { 3620 // provoke OS NULL exception if reg = NULL by 3621 // accessing M[reg] w/o changing any (non-CC) registers 3622 // NOTE: cmpl is plenty here to provoke a segv 3623 cmpptr(rax, Address(reg, 0)); 3624 // Note: should probably use testl(rax, Address(reg, 0)); 3625 // may be shorter code (however, this version of 3626 // testl needs to be implemented first) 3627 } else { 3628 // nothing to do, (later) access of M[reg + offset] 3629 // will provoke OS NULL exception if reg = NULL 3630 } 3631 } 3632 3633 void MacroAssembler::os_breakpoint() { 3634 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3635 // (e.g., MSVC can't call ps() otherwise) 3636 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3637 } 3638 3639 void MacroAssembler::unimplemented(const char* what) { 3640 const char* buf = NULL; 3641 { 3642 ResourceMark rm; 3643 stringStream ss; 3644 ss.print("unimplemented: %s", what); 3645 buf = code_string(ss.as_string()); 3646 } 3647 stop(buf); 3648 } 3649 3650 #ifdef _LP64 3651 #define XSTATE_BV 0x200 3652 #endif 3653 3654 void MacroAssembler::pop_CPU_state() { 3655 pop_FPU_state(); 3656 pop_IU_state(); 3657 } 3658 3659 void MacroAssembler::pop_FPU_state() { 3660 #ifndef _LP64 3661 frstor(Address(rsp, 0)); 3662 #else 3663 fxrstor(Address(rsp, 0)); 3664 #endif 3665 addptr(rsp, FPUStateSizeInWords * wordSize); 3666 } 3667 3668 void MacroAssembler::pop_IU_state() { 3669 popa(); 3670 LP64_ONLY(addq(rsp, 8)); 3671 popf(); 3672 } 3673 3674 // Save Integer and Float state 3675 // Warning: Stack must be 16 byte aligned (64bit) 3676 void MacroAssembler::push_CPU_state() { 3677 push_IU_state(); 3678 push_FPU_state(); 3679 } 3680 3681 void MacroAssembler::push_FPU_state() { 3682 subptr(rsp, FPUStateSizeInWords * wordSize); 3683 #ifndef _LP64 3684 fnsave(Address(rsp, 0)); 3685 fwait(); 3686 #else 3687 fxsave(Address(rsp, 0)); 3688 #endif // LP64 3689 } 3690 3691 void MacroAssembler::push_IU_state() { 3692 // Push flags first because pusha kills them 3693 pushf(); 3694 // Make sure rsp stays 16-byte aligned 3695 LP64_ONLY(subq(rsp, 8)); 3696 pusha(); 3697 } 3698 3699 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3700 if (!java_thread->is_valid()) { 3701 java_thread = rdi; 3702 get_thread(java_thread); 3703 } 3704 // we must set sp to zero to clear frame 3705 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3706 if (clear_fp) { 3707 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3708 } 3709 3710 // Always clear the pc because it could have been set by make_walkable() 3711 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3712 3713 vzeroupper(); 3714 } 3715 3716 void MacroAssembler::restore_rax(Register tmp) { 3717 if (tmp == noreg) pop(rax); 3718 else if (tmp != rax) mov(rax, tmp); 3719 } 3720 3721 void MacroAssembler::round_to(Register reg, int modulus) { 3722 addptr(reg, modulus - 1); 3723 andptr(reg, -modulus); 3724 } 3725 3726 void MacroAssembler::save_rax(Register tmp) { 3727 if (tmp == noreg) push(rax); 3728 else if (tmp != rax) mov(tmp, rax); 3729 } 3730 3731 // Write serialization page so VM thread can do a pseudo remote membar. 3732 // We use the current thread pointer to calculate a thread specific 3733 // offset to write to within the page. This minimizes bus traffic 3734 // due to cache line collision. 3735 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3736 movl(tmp, thread); 3737 shrl(tmp, os::get_serialize_page_shift_count()); 3738 andl(tmp, (os::vm_page_size() - sizeof(int))); 3739 3740 Address index(noreg, tmp, Address::times_1); 3741 ExternalAddress page(os::get_memory_serialize_page()); 3742 3743 // Size of store must match masking code above 3744 movl(as_Address(ArrayAddress(page, index)), tmp); 3745 } 3746 3747 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) { 3748 if (SafepointMechanism::uses_thread_local_poll()) { 3749 #ifdef _LP64 3750 assert(thread_reg == r15_thread, "should be"); 3751 #else 3752 if (thread_reg == noreg) { 3753 thread_reg = temp_reg; 3754 get_thread(thread_reg); 3755 } 3756 #endif 3757 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit()); 3758 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll 3759 } else { 3760 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()), 3761 SafepointSynchronize::_not_synchronized); 3762 jcc(Assembler::notEqual, slow_path); 3763 } 3764 } 3765 3766 // Calls to C land 3767 // 3768 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3769 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3770 // has to be reset to 0. This is required to allow proper stack traversal. 3771 void MacroAssembler::set_last_Java_frame(Register java_thread, 3772 Register last_java_sp, 3773 Register last_java_fp, 3774 address last_java_pc) { 3775 vzeroupper(); 3776 // determine java_thread register 3777 if (!java_thread->is_valid()) { 3778 java_thread = rdi; 3779 get_thread(java_thread); 3780 } 3781 // determine last_java_sp register 3782 if (!last_java_sp->is_valid()) { 3783 last_java_sp = rsp; 3784 } 3785 3786 // last_java_fp is optional 3787 3788 if (last_java_fp->is_valid()) { 3789 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3790 } 3791 3792 // last_java_pc is optional 3793 3794 if (last_java_pc != NULL) { 3795 lea(Address(java_thread, 3796 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3797 InternalAddress(last_java_pc)); 3798 3799 } 3800 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3801 } 3802 3803 void MacroAssembler::shlptr(Register dst, int imm8) { 3804 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3805 } 3806 3807 void MacroAssembler::shrptr(Register dst, int imm8) { 3808 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3809 } 3810 3811 void MacroAssembler::sign_extend_byte(Register reg) { 3812 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3813 movsbl(reg, reg); // movsxb 3814 } else { 3815 shll(reg, 24); 3816 sarl(reg, 24); 3817 } 3818 } 3819 3820 void MacroAssembler::sign_extend_short(Register reg) { 3821 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3822 movswl(reg, reg); // movsxw 3823 } else { 3824 shll(reg, 16); 3825 sarl(reg, 16); 3826 } 3827 } 3828 3829 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3830 assert(reachable(src), "Address should be reachable"); 3831 testl(dst, as_Address(src)); 3832 } 3833 3834 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3835 int dst_enc = dst->encoding(); 3836 int src_enc = src->encoding(); 3837 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3838 Assembler::pcmpeqb(dst, src); 3839 } else if ((dst_enc < 16) && (src_enc < 16)) { 3840 Assembler::pcmpeqb(dst, src); 3841 } else if (src_enc < 16) { 3842 subptr(rsp, 64); 3843 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3844 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3845 Assembler::pcmpeqb(xmm0, src); 3846 movdqu(dst, xmm0); 3847 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3848 addptr(rsp, 64); 3849 } else if (dst_enc < 16) { 3850 subptr(rsp, 64); 3851 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3852 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3853 Assembler::pcmpeqb(dst, xmm0); 3854 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3855 addptr(rsp, 64); 3856 } else { 3857 subptr(rsp, 64); 3858 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3859 subptr(rsp, 64); 3860 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3861 movdqu(xmm0, src); 3862 movdqu(xmm1, dst); 3863 Assembler::pcmpeqb(xmm1, xmm0); 3864 movdqu(dst, xmm1); 3865 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3866 addptr(rsp, 64); 3867 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3868 addptr(rsp, 64); 3869 } 3870 } 3871 3872 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3873 int dst_enc = dst->encoding(); 3874 int src_enc = src->encoding(); 3875 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3876 Assembler::pcmpeqw(dst, src); 3877 } else if ((dst_enc < 16) && (src_enc < 16)) { 3878 Assembler::pcmpeqw(dst, src); 3879 } else if (src_enc < 16) { 3880 subptr(rsp, 64); 3881 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3882 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3883 Assembler::pcmpeqw(xmm0, src); 3884 movdqu(dst, xmm0); 3885 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3886 addptr(rsp, 64); 3887 } else if (dst_enc < 16) { 3888 subptr(rsp, 64); 3889 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3890 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3891 Assembler::pcmpeqw(dst, xmm0); 3892 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3893 addptr(rsp, 64); 3894 } else { 3895 subptr(rsp, 64); 3896 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3897 subptr(rsp, 64); 3898 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3899 movdqu(xmm0, src); 3900 movdqu(xmm1, dst); 3901 Assembler::pcmpeqw(xmm1, xmm0); 3902 movdqu(dst, xmm1); 3903 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3904 addptr(rsp, 64); 3905 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3906 addptr(rsp, 64); 3907 } 3908 } 3909 3910 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3911 int dst_enc = dst->encoding(); 3912 if (dst_enc < 16) { 3913 Assembler::pcmpestri(dst, src, imm8); 3914 } else { 3915 subptr(rsp, 64); 3916 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3917 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3918 Assembler::pcmpestri(xmm0, src, imm8); 3919 movdqu(dst, xmm0); 3920 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3921 addptr(rsp, 64); 3922 } 3923 } 3924 3925 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3926 int dst_enc = dst->encoding(); 3927 int src_enc = src->encoding(); 3928 if ((dst_enc < 16) && (src_enc < 16)) { 3929 Assembler::pcmpestri(dst, src, imm8); 3930 } else if (src_enc < 16) { 3931 subptr(rsp, 64); 3932 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3933 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3934 Assembler::pcmpestri(xmm0, src, imm8); 3935 movdqu(dst, xmm0); 3936 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3937 addptr(rsp, 64); 3938 } else if (dst_enc < 16) { 3939 subptr(rsp, 64); 3940 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3941 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3942 Assembler::pcmpestri(dst, xmm0, imm8); 3943 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3944 addptr(rsp, 64); 3945 } else { 3946 subptr(rsp, 64); 3947 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3948 subptr(rsp, 64); 3949 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3950 movdqu(xmm0, src); 3951 movdqu(xmm1, dst); 3952 Assembler::pcmpestri(xmm1, xmm0, imm8); 3953 movdqu(dst, xmm1); 3954 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3955 addptr(rsp, 64); 3956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3957 addptr(rsp, 64); 3958 } 3959 } 3960 3961 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3962 int dst_enc = dst->encoding(); 3963 int src_enc = src->encoding(); 3964 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3965 Assembler::pmovzxbw(dst, src); 3966 } else if ((dst_enc < 16) && (src_enc < 16)) { 3967 Assembler::pmovzxbw(dst, src); 3968 } else if (src_enc < 16) { 3969 subptr(rsp, 64); 3970 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3971 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3972 Assembler::pmovzxbw(xmm0, src); 3973 movdqu(dst, xmm0); 3974 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3975 addptr(rsp, 64); 3976 } else if (dst_enc < 16) { 3977 subptr(rsp, 64); 3978 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3979 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3980 Assembler::pmovzxbw(dst, xmm0); 3981 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3982 addptr(rsp, 64); 3983 } else { 3984 subptr(rsp, 64); 3985 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3986 subptr(rsp, 64); 3987 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3988 movdqu(xmm0, src); 3989 movdqu(xmm1, dst); 3990 Assembler::pmovzxbw(xmm1, xmm0); 3991 movdqu(dst, xmm1); 3992 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3993 addptr(rsp, 64); 3994 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3995 addptr(rsp, 64); 3996 } 3997 } 3998 3999 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 4000 int dst_enc = dst->encoding(); 4001 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4002 Assembler::pmovzxbw(dst, src); 4003 } else if (dst_enc < 16) { 4004 Assembler::pmovzxbw(dst, src); 4005 } else { 4006 subptr(rsp, 64); 4007 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4008 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4009 Assembler::pmovzxbw(xmm0, src); 4010 movdqu(dst, xmm0); 4011 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4012 addptr(rsp, 64); 4013 } 4014 } 4015 4016 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 4017 int src_enc = src->encoding(); 4018 if (src_enc < 16) { 4019 Assembler::pmovmskb(dst, src); 4020 } else { 4021 subptr(rsp, 64); 4022 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4023 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4024 Assembler::pmovmskb(dst, xmm0); 4025 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4026 addptr(rsp, 64); 4027 } 4028 } 4029 4030 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 4031 int dst_enc = dst->encoding(); 4032 int src_enc = src->encoding(); 4033 if ((dst_enc < 16) && (src_enc < 16)) { 4034 Assembler::ptest(dst, src); 4035 } else if (src_enc < 16) { 4036 subptr(rsp, 64); 4037 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4038 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4039 Assembler::ptest(xmm0, src); 4040 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4041 addptr(rsp, 64); 4042 } else if (dst_enc < 16) { 4043 subptr(rsp, 64); 4044 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4045 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4046 Assembler::ptest(dst, xmm0); 4047 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4048 addptr(rsp, 64); 4049 } else { 4050 subptr(rsp, 64); 4051 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4052 subptr(rsp, 64); 4053 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4054 movdqu(xmm0, src); 4055 movdqu(xmm1, dst); 4056 Assembler::ptest(xmm1, xmm0); 4057 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4058 addptr(rsp, 64); 4059 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4060 addptr(rsp, 64); 4061 } 4062 } 4063 4064 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4065 if (reachable(src)) { 4066 Assembler::sqrtsd(dst, as_Address(src)); 4067 } else { 4068 lea(rscratch1, src); 4069 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4070 } 4071 } 4072 4073 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4074 if (reachable(src)) { 4075 Assembler::sqrtss(dst, as_Address(src)); 4076 } else { 4077 lea(rscratch1, src); 4078 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4079 } 4080 } 4081 4082 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4083 if (reachable(src)) { 4084 Assembler::subsd(dst, as_Address(src)); 4085 } else { 4086 lea(rscratch1, src); 4087 Assembler::subsd(dst, Address(rscratch1, 0)); 4088 } 4089 } 4090 4091 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4092 if (reachable(src)) { 4093 Assembler::subss(dst, as_Address(src)); 4094 } else { 4095 lea(rscratch1, src); 4096 Assembler::subss(dst, Address(rscratch1, 0)); 4097 } 4098 } 4099 4100 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4101 if (reachable(src)) { 4102 Assembler::ucomisd(dst, as_Address(src)); 4103 } else { 4104 lea(rscratch1, src); 4105 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4106 } 4107 } 4108 4109 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4110 if (reachable(src)) { 4111 Assembler::ucomiss(dst, as_Address(src)); 4112 } else { 4113 lea(rscratch1, src); 4114 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4115 } 4116 } 4117 4118 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4119 // Used in sign-bit flipping with aligned address. 4120 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4121 if (reachable(src)) { 4122 Assembler::xorpd(dst, as_Address(src)); 4123 } else { 4124 lea(rscratch1, src); 4125 Assembler::xorpd(dst, Address(rscratch1, 0)); 4126 } 4127 } 4128 4129 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4130 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4131 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4132 } 4133 else { 4134 Assembler::xorpd(dst, src); 4135 } 4136 } 4137 4138 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4139 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4140 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4141 } else { 4142 Assembler::xorps(dst, src); 4143 } 4144 } 4145 4146 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4147 // Used in sign-bit flipping with aligned address. 4148 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4149 if (reachable(src)) { 4150 Assembler::xorps(dst, as_Address(src)); 4151 } else { 4152 lea(rscratch1, src); 4153 Assembler::xorps(dst, Address(rscratch1, 0)); 4154 } 4155 } 4156 4157 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4158 // Used in sign-bit flipping with aligned address. 4159 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4160 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4161 if (reachable(src)) { 4162 Assembler::pshufb(dst, as_Address(src)); 4163 } else { 4164 lea(rscratch1, src); 4165 Assembler::pshufb(dst, Address(rscratch1, 0)); 4166 } 4167 } 4168 4169 // AVX 3-operands instructions 4170 4171 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4172 if (reachable(src)) { 4173 vaddsd(dst, nds, as_Address(src)); 4174 } else { 4175 lea(rscratch1, src); 4176 vaddsd(dst, nds, Address(rscratch1, 0)); 4177 } 4178 } 4179 4180 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4181 if (reachable(src)) { 4182 vaddss(dst, nds, as_Address(src)); 4183 } else { 4184 lea(rscratch1, src); 4185 vaddss(dst, nds, Address(rscratch1, 0)); 4186 } 4187 } 4188 4189 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4190 int dst_enc = dst->encoding(); 4191 int nds_enc = nds->encoding(); 4192 int src_enc = src->encoding(); 4193 if ((dst_enc < 16) && (nds_enc < 16)) { 4194 vandps(dst, nds, negate_field, vector_len); 4195 } else if ((src_enc < 16) && (dst_enc < 16)) { 4196 evmovdqul(src, nds, Assembler::AVX_512bit); 4197 vandps(dst, src, negate_field, vector_len); 4198 } else if (src_enc < 16) { 4199 evmovdqul(src, nds, Assembler::AVX_512bit); 4200 vandps(src, src, negate_field, vector_len); 4201 evmovdqul(dst, src, Assembler::AVX_512bit); 4202 } else if (dst_enc < 16) { 4203 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4204 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4205 vandps(dst, xmm0, negate_field, vector_len); 4206 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4207 } else { 4208 if (src_enc != dst_enc) { 4209 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4210 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4211 vandps(xmm0, xmm0, negate_field, vector_len); 4212 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4213 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4214 } else { 4215 subptr(rsp, 64); 4216 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4217 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4218 vandps(xmm0, xmm0, negate_field, vector_len); 4219 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4220 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4221 addptr(rsp, 64); 4222 } 4223 } 4224 } 4225 4226 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4227 int dst_enc = dst->encoding(); 4228 int nds_enc = nds->encoding(); 4229 int src_enc = src->encoding(); 4230 if ((dst_enc < 16) && (nds_enc < 16)) { 4231 vandpd(dst, nds, negate_field, vector_len); 4232 } else if ((src_enc < 16) && (dst_enc < 16)) { 4233 evmovdqul(src, nds, Assembler::AVX_512bit); 4234 vandpd(dst, src, negate_field, vector_len); 4235 } else if (src_enc < 16) { 4236 evmovdqul(src, nds, Assembler::AVX_512bit); 4237 vandpd(src, src, negate_field, vector_len); 4238 evmovdqul(dst, src, Assembler::AVX_512bit); 4239 } else if (dst_enc < 16) { 4240 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4241 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4242 vandpd(dst, xmm0, negate_field, vector_len); 4243 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4244 } else { 4245 if (src_enc != dst_enc) { 4246 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4247 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4248 vandpd(xmm0, xmm0, negate_field, vector_len); 4249 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4250 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4251 } else { 4252 subptr(rsp, 64); 4253 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4254 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4255 vandpd(xmm0, xmm0, negate_field, vector_len); 4256 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4257 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4258 addptr(rsp, 64); 4259 } 4260 } 4261 } 4262 4263 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4264 int dst_enc = dst->encoding(); 4265 int nds_enc = nds->encoding(); 4266 int src_enc = src->encoding(); 4267 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4268 Assembler::vpaddb(dst, nds, src, vector_len); 4269 } else if ((dst_enc < 16) && (src_enc < 16)) { 4270 Assembler::vpaddb(dst, dst, src, vector_len); 4271 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4272 // use nds as scratch for src 4273 evmovdqul(nds, src, Assembler::AVX_512bit); 4274 Assembler::vpaddb(dst, dst, nds, vector_len); 4275 } else if ((src_enc < 16) && (nds_enc < 16)) { 4276 // use nds as scratch for dst 4277 evmovdqul(nds, dst, Assembler::AVX_512bit); 4278 Assembler::vpaddb(nds, nds, src, vector_len); 4279 evmovdqul(dst, nds, Assembler::AVX_512bit); 4280 } else if (dst_enc < 16) { 4281 // use nds as scatch for xmm0 to hold src 4282 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4283 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4284 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4285 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4286 } else { 4287 // worse case scenario, all regs are in the upper bank 4288 subptr(rsp, 64); 4289 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4290 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4291 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4292 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4293 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4294 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4295 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4296 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4297 addptr(rsp, 64); 4298 } 4299 } 4300 4301 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4302 int dst_enc = dst->encoding(); 4303 int nds_enc = nds->encoding(); 4304 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4305 Assembler::vpaddb(dst, nds, src, vector_len); 4306 } else if (dst_enc < 16) { 4307 Assembler::vpaddb(dst, dst, src, vector_len); 4308 } else if (nds_enc < 16) { 4309 // implies dst_enc in upper bank with src as scratch 4310 evmovdqul(nds, dst, Assembler::AVX_512bit); 4311 Assembler::vpaddb(nds, nds, src, vector_len); 4312 evmovdqul(dst, nds, Assembler::AVX_512bit); 4313 } else { 4314 // worse case scenario, all regs in upper bank 4315 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4316 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4317 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4318 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4319 } 4320 } 4321 4322 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4323 int dst_enc = dst->encoding(); 4324 int nds_enc = nds->encoding(); 4325 int src_enc = src->encoding(); 4326 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4327 Assembler::vpaddw(dst, nds, src, vector_len); 4328 } else if ((dst_enc < 16) && (src_enc < 16)) { 4329 Assembler::vpaddw(dst, dst, src, vector_len); 4330 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4331 // use nds as scratch for src 4332 evmovdqul(nds, src, Assembler::AVX_512bit); 4333 Assembler::vpaddw(dst, dst, nds, vector_len); 4334 } else if ((src_enc < 16) && (nds_enc < 16)) { 4335 // use nds as scratch for dst 4336 evmovdqul(nds, dst, Assembler::AVX_512bit); 4337 Assembler::vpaddw(nds, nds, src, vector_len); 4338 evmovdqul(dst, nds, Assembler::AVX_512bit); 4339 } else if (dst_enc < 16) { 4340 // use nds as scatch for xmm0 to hold src 4341 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4342 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4343 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4344 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4345 } else { 4346 // worse case scenario, all regs are in the upper bank 4347 subptr(rsp, 64); 4348 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4349 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4350 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4351 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4352 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4353 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4354 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4355 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4356 addptr(rsp, 64); 4357 } 4358 } 4359 4360 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4361 int dst_enc = dst->encoding(); 4362 int nds_enc = nds->encoding(); 4363 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4364 Assembler::vpaddw(dst, nds, src, vector_len); 4365 } else if (dst_enc < 16) { 4366 Assembler::vpaddw(dst, dst, src, vector_len); 4367 } else if (nds_enc < 16) { 4368 // implies dst_enc in upper bank with src as scratch 4369 evmovdqul(nds, dst, Assembler::AVX_512bit); 4370 Assembler::vpaddw(nds, nds, src, vector_len); 4371 evmovdqul(dst, nds, Assembler::AVX_512bit); 4372 } else { 4373 // worse case scenario, all regs in upper bank 4374 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4375 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4376 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4377 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4378 } 4379 } 4380 4381 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4382 if (reachable(src)) { 4383 Assembler::vpand(dst, nds, as_Address(src), vector_len); 4384 } else { 4385 lea(rscratch1, src); 4386 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len); 4387 } 4388 } 4389 4390 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4391 int dst_enc = dst->encoding(); 4392 int src_enc = src->encoding(); 4393 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4394 Assembler::vpbroadcastw(dst, src); 4395 } else if ((dst_enc < 16) && (src_enc < 16)) { 4396 Assembler::vpbroadcastw(dst, src); 4397 } else if (src_enc < 16) { 4398 subptr(rsp, 64); 4399 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4400 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4401 Assembler::vpbroadcastw(xmm0, src); 4402 movdqu(dst, xmm0); 4403 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4404 addptr(rsp, 64); 4405 } else if (dst_enc < 16) { 4406 subptr(rsp, 64); 4407 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4408 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4409 Assembler::vpbroadcastw(dst, xmm0); 4410 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4411 addptr(rsp, 64); 4412 } else { 4413 subptr(rsp, 64); 4414 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4415 subptr(rsp, 64); 4416 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4417 movdqu(xmm0, src); 4418 movdqu(xmm1, dst); 4419 Assembler::vpbroadcastw(xmm1, xmm0); 4420 movdqu(dst, xmm1); 4421 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4422 addptr(rsp, 64); 4423 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4424 addptr(rsp, 64); 4425 } 4426 } 4427 4428 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4429 int dst_enc = dst->encoding(); 4430 int nds_enc = nds->encoding(); 4431 int src_enc = src->encoding(); 4432 assert(dst_enc == nds_enc, ""); 4433 if ((dst_enc < 16) && (src_enc < 16)) { 4434 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4435 } else if (src_enc < 16) { 4436 subptr(rsp, 64); 4437 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4438 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4439 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4440 movdqu(dst, xmm0); 4441 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4442 addptr(rsp, 64); 4443 } else if (dst_enc < 16) { 4444 subptr(rsp, 64); 4445 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4446 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4447 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4448 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4449 addptr(rsp, 64); 4450 } else { 4451 subptr(rsp, 64); 4452 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4453 subptr(rsp, 64); 4454 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4455 movdqu(xmm0, src); 4456 movdqu(xmm1, dst); 4457 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4458 movdqu(dst, xmm1); 4459 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4460 addptr(rsp, 64); 4461 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4462 addptr(rsp, 64); 4463 } 4464 } 4465 4466 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4467 int dst_enc = dst->encoding(); 4468 int nds_enc = nds->encoding(); 4469 int src_enc = src->encoding(); 4470 assert(dst_enc == nds_enc, ""); 4471 if ((dst_enc < 16) && (src_enc < 16)) { 4472 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4473 } else if (src_enc < 16) { 4474 subptr(rsp, 64); 4475 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4476 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4477 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4478 movdqu(dst, xmm0); 4479 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4480 addptr(rsp, 64); 4481 } else if (dst_enc < 16) { 4482 subptr(rsp, 64); 4483 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4484 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4485 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4486 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4487 addptr(rsp, 64); 4488 } else { 4489 subptr(rsp, 64); 4490 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4491 subptr(rsp, 64); 4492 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4493 movdqu(xmm0, src); 4494 movdqu(xmm1, dst); 4495 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4496 movdqu(dst, xmm1); 4497 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4498 addptr(rsp, 64); 4499 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4500 addptr(rsp, 64); 4501 } 4502 } 4503 4504 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4505 int dst_enc = dst->encoding(); 4506 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4507 Assembler::vpmovzxbw(dst, src, vector_len); 4508 } else if (dst_enc < 16) { 4509 Assembler::vpmovzxbw(dst, src, vector_len); 4510 } else { 4511 subptr(rsp, 64); 4512 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4513 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4514 Assembler::vpmovzxbw(xmm0, src, vector_len); 4515 movdqu(dst, xmm0); 4516 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4517 addptr(rsp, 64); 4518 } 4519 } 4520 4521 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4522 int src_enc = src->encoding(); 4523 if (src_enc < 16) { 4524 Assembler::vpmovmskb(dst, src); 4525 } else { 4526 subptr(rsp, 64); 4527 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4528 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4529 Assembler::vpmovmskb(dst, xmm0); 4530 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4531 addptr(rsp, 64); 4532 } 4533 } 4534 4535 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4536 int dst_enc = dst->encoding(); 4537 int nds_enc = nds->encoding(); 4538 int src_enc = src->encoding(); 4539 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4540 Assembler::vpmullw(dst, nds, src, vector_len); 4541 } else if ((dst_enc < 16) && (src_enc < 16)) { 4542 Assembler::vpmullw(dst, dst, src, vector_len); 4543 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4544 // use nds as scratch for src 4545 evmovdqul(nds, src, Assembler::AVX_512bit); 4546 Assembler::vpmullw(dst, dst, nds, vector_len); 4547 } else if ((src_enc < 16) && (nds_enc < 16)) { 4548 // use nds as scratch for dst 4549 evmovdqul(nds, dst, Assembler::AVX_512bit); 4550 Assembler::vpmullw(nds, nds, src, vector_len); 4551 evmovdqul(dst, nds, Assembler::AVX_512bit); 4552 } else if (dst_enc < 16) { 4553 // use nds as scatch for xmm0 to hold src 4554 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4555 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4556 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4557 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4558 } else { 4559 // worse case scenario, all regs are in the upper bank 4560 subptr(rsp, 64); 4561 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4562 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4563 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4564 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4565 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4566 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4567 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4568 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4569 addptr(rsp, 64); 4570 } 4571 } 4572 4573 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4574 int dst_enc = dst->encoding(); 4575 int nds_enc = nds->encoding(); 4576 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4577 Assembler::vpmullw(dst, nds, src, vector_len); 4578 } else if (dst_enc < 16) { 4579 Assembler::vpmullw(dst, dst, src, vector_len); 4580 } else if (nds_enc < 16) { 4581 // implies dst_enc in upper bank with src as scratch 4582 evmovdqul(nds, dst, Assembler::AVX_512bit); 4583 Assembler::vpmullw(nds, nds, src, vector_len); 4584 evmovdqul(dst, nds, Assembler::AVX_512bit); 4585 } else { 4586 // worse case scenario, all regs in upper bank 4587 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4588 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4589 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4590 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4591 } 4592 } 4593 4594 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4595 int dst_enc = dst->encoding(); 4596 int nds_enc = nds->encoding(); 4597 int src_enc = src->encoding(); 4598 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4599 Assembler::vpsubb(dst, nds, src, vector_len); 4600 } else if ((dst_enc < 16) && (src_enc < 16)) { 4601 Assembler::vpsubb(dst, dst, src, vector_len); 4602 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4603 // use nds as scratch for src 4604 evmovdqul(nds, src, Assembler::AVX_512bit); 4605 Assembler::vpsubb(dst, dst, nds, vector_len); 4606 } else if ((src_enc < 16) && (nds_enc < 16)) { 4607 // use nds as scratch for dst 4608 evmovdqul(nds, dst, Assembler::AVX_512bit); 4609 Assembler::vpsubb(nds, nds, src, vector_len); 4610 evmovdqul(dst, nds, Assembler::AVX_512bit); 4611 } else if (dst_enc < 16) { 4612 // use nds as scatch for xmm0 to hold src 4613 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4614 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4615 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4616 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4617 } else { 4618 // worse case scenario, all regs are in the upper bank 4619 subptr(rsp, 64); 4620 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4621 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4622 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4623 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4624 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4625 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4626 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4627 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4628 addptr(rsp, 64); 4629 } 4630 } 4631 4632 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4633 int dst_enc = dst->encoding(); 4634 int nds_enc = nds->encoding(); 4635 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4636 Assembler::vpsubb(dst, nds, src, vector_len); 4637 } else if (dst_enc < 16) { 4638 Assembler::vpsubb(dst, dst, src, vector_len); 4639 } else if (nds_enc < 16) { 4640 // implies dst_enc in upper bank with src as scratch 4641 evmovdqul(nds, dst, Assembler::AVX_512bit); 4642 Assembler::vpsubb(nds, nds, src, vector_len); 4643 evmovdqul(dst, nds, Assembler::AVX_512bit); 4644 } else { 4645 // worse case scenario, all regs in upper bank 4646 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4647 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4648 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4649 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4650 } 4651 } 4652 4653 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4654 int dst_enc = dst->encoding(); 4655 int nds_enc = nds->encoding(); 4656 int src_enc = src->encoding(); 4657 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4658 Assembler::vpsubw(dst, nds, src, vector_len); 4659 } else if ((dst_enc < 16) && (src_enc < 16)) { 4660 Assembler::vpsubw(dst, dst, src, vector_len); 4661 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4662 // use nds as scratch for src 4663 evmovdqul(nds, src, Assembler::AVX_512bit); 4664 Assembler::vpsubw(dst, dst, nds, vector_len); 4665 } else if ((src_enc < 16) && (nds_enc < 16)) { 4666 // use nds as scratch for dst 4667 evmovdqul(nds, dst, Assembler::AVX_512bit); 4668 Assembler::vpsubw(nds, nds, src, vector_len); 4669 evmovdqul(dst, nds, Assembler::AVX_512bit); 4670 } else if (dst_enc < 16) { 4671 // use nds as scatch for xmm0 to hold src 4672 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4673 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4674 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4675 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4676 } else { 4677 // worse case scenario, all regs are in the upper bank 4678 subptr(rsp, 64); 4679 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4680 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4681 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4682 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4683 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4684 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4685 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4686 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4687 addptr(rsp, 64); 4688 } 4689 } 4690 4691 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4692 int dst_enc = dst->encoding(); 4693 int nds_enc = nds->encoding(); 4694 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4695 Assembler::vpsubw(dst, nds, src, vector_len); 4696 } else if (dst_enc < 16) { 4697 Assembler::vpsubw(dst, dst, src, vector_len); 4698 } else if (nds_enc < 16) { 4699 // implies dst_enc in upper bank with src as scratch 4700 evmovdqul(nds, dst, Assembler::AVX_512bit); 4701 Assembler::vpsubw(nds, nds, src, vector_len); 4702 evmovdqul(dst, nds, Assembler::AVX_512bit); 4703 } else { 4704 // worse case scenario, all regs in upper bank 4705 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4706 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4707 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4708 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4709 } 4710 } 4711 4712 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4713 int dst_enc = dst->encoding(); 4714 int nds_enc = nds->encoding(); 4715 int shift_enc = shift->encoding(); 4716 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4717 Assembler::vpsraw(dst, nds, shift, vector_len); 4718 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4719 Assembler::vpsraw(dst, dst, shift, vector_len); 4720 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4721 // use nds_enc as scratch with shift 4722 evmovdqul(nds, shift, Assembler::AVX_512bit); 4723 Assembler::vpsraw(dst, dst, nds, vector_len); 4724 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4725 // use nds as scratch with dst 4726 evmovdqul(nds, dst, Assembler::AVX_512bit); 4727 Assembler::vpsraw(nds, nds, shift, vector_len); 4728 evmovdqul(dst, nds, Assembler::AVX_512bit); 4729 } else if (dst_enc < 16) { 4730 // use nds to save a copy of xmm0 and hold shift 4731 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4732 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4733 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4734 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4735 } else if (nds_enc < 16) { 4736 // use nds as dest as temps 4737 evmovdqul(nds, dst, Assembler::AVX_512bit); 4738 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4739 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4740 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4741 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4742 evmovdqul(dst, nds, Assembler::AVX_512bit); 4743 } else { 4744 // worse case scenario, all regs are in the upper bank 4745 subptr(rsp, 64); 4746 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4747 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4748 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4749 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4750 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4751 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4752 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4753 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4754 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4755 addptr(rsp, 64); 4756 } 4757 } 4758 4759 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4760 int dst_enc = dst->encoding(); 4761 int nds_enc = nds->encoding(); 4762 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4763 Assembler::vpsraw(dst, nds, shift, vector_len); 4764 } else if (dst_enc < 16) { 4765 Assembler::vpsraw(dst, dst, shift, vector_len); 4766 } else if (nds_enc < 16) { 4767 // use nds as scratch 4768 evmovdqul(nds, dst, Assembler::AVX_512bit); 4769 Assembler::vpsraw(nds, nds, shift, vector_len); 4770 evmovdqul(dst, nds, Assembler::AVX_512bit); 4771 } else { 4772 // use nds as scratch for xmm0 4773 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4774 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4775 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4776 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4777 } 4778 } 4779 4780 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4781 int dst_enc = dst->encoding(); 4782 int nds_enc = nds->encoding(); 4783 int shift_enc = shift->encoding(); 4784 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4785 Assembler::vpsrlw(dst, nds, shift, vector_len); 4786 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4787 Assembler::vpsrlw(dst, dst, shift, vector_len); 4788 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4789 // use nds_enc as scratch with shift 4790 evmovdqul(nds, shift, Assembler::AVX_512bit); 4791 Assembler::vpsrlw(dst, dst, nds, vector_len); 4792 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4793 // use nds as scratch with dst 4794 evmovdqul(nds, dst, Assembler::AVX_512bit); 4795 Assembler::vpsrlw(nds, nds, shift, vector_len); 4796 evmovdqul(dst, nds, Assembler::AVX_512bit); 4797 } else if (dst_enc < 16) { 4798 // use nds to save a copy of xmm0 and hold shift 4799 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4800 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4801 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4802 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4803 } else if (nds_enc < 16) { 4804 // use nds as dest as temps 4805 evmovdqul(nds, dst, Assembler::AVX_512bit); 4806 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4807 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4808 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4809 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4810 evmovdqul(dst, nds, Assembler::AVX_512bit); 4811 } else { 4812 // worse case scenario, all regs are in the upper bank 4813 subptr(rsp, 64); 4814 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4815 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4816 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4817 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4818 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4819 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4820 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4821 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4822 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4823 addptr(rsp, 64); 4824 } 4825 } 4826 4827 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4828 int dst_enc = dst->encoding(); 4829 int nds_enc = nds->encoding(); 4830 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4831 Assembler::vpsrlw(dst, nds, shift, vector_len); 4832 } else if (dst_enc < 16) { 4833 Assembler::vpsrlw(dst, dst, shift, vector_len); 4834 } else if (nds_enc < 16) { 4835 // use nds as scratch 4836 evmovdqul(nds, dst, Assembler::AVX_512bit); 4837 Assembler::vpsrlw(nds, nds, shift, vector_len); 4838 evmovdqul(dst, nds, Assembler::AVX_512bit); 4839 } else { 4840 // use nds as scratch for xmm0 4841 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4842 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4843 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4844 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4845 } 4846 } 4847 4848 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4849 int dst_enc = dst->encoding(); 4850 int nds_enc = nds->encoding(); 4851 int shift_enc = shift->encoding(); 4852 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4853 Assembler::vpsllw(dst, nds, shift, vector_len); 4854 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4855 Assembler::vpsllw(dst, dst, shift, vector_len); 4856 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4857 // use nds_enc as scratch with shift 4858 evmovdqul(nds, shift, Assembler::AVX_512bit); 4859 Assembler::vpsllw(dst, dst, nds, vector_len); 4860 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4861 // use nds as scratch with dst 4862 evmovdqul(nds, dst, Assembler::AVX_512bit); 4863 Assembler::vpsllw(nds, nds, shift, vector_len); 4864 evmovdqul(dst, nds, Assembler::AVX_512bit); 4865 } else if (dst_enc < 16) { 4866 // use nds to save a copy of xmm0 and hold shift 4867 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4868 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4869 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4870 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4871 } else if (nds_enc < 16) { 4872 // use nds as dest as temps 4873 evmovdqul(nds, dst, Assembler::AVX_512bit); 4874 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4875 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4876 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4877 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4878 evmovdqul(dst, nds, Assembler::AVX_512bit); 4879 } else { 4880 // worse case scenario, all regs are in the upper bank 4881 subptr(rsp, 64); 4882 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4883 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4884 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4885 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4886 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4887 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4888 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4889 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4890 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4891 addptr(rsp, 64); 4892 } 4893 } 4894 4895 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4896 int dst_enc = dst->encoding(); 4897 int nds_enc = nds->encoding(); 4898 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4899 Assembler::vpsllw(dst, nds, shift, vector_len); 4900 } else if (dst_enc < 16) { 4901 Assembler::vpsllw(dst, dst, shift, vector_len); 4902 } else if (nds_enc < 16) { 4903 // use nds as scratch 4904 evmovdqul(nds, dst, Assembler::AVX_512bit); 4905 Assembler::vpsllw(nds, nds, shift, vector_len); 4906 evmovdqul(dst, nds, Assembler::AVX_512bit); 4907 } else { 4908 // use nds as scratch for xmm0 4909 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4910 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4911 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4912 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4913 } 4914 } 4915 4916 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4917 int dst_enc = dst->encoding(); 4918 int src_enc = src->encoding(); 4919 if ((dst_enc < 16) && (src_enc < 16)) { 4920 Assembler::vptest(dst, src); 4921 } else if (src_enc < 16) { 4922 subptr(rsp, 64); 4923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4924 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4925 Assembler::vptest(xmm0, src); 4926 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4927 addptr(rsp, 64); 4928 } else if (dst_enc < 16) { 4929 subptr(rsp, 64); 4930 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4931 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4932 Assembler::vptest(dst, xmm0); 4933 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4934 addptr(rsp, 64); 4935 } else { 4936 subptr(rsp, 64); 4937 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4938 subptr(rsp, 64); 4939 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4940 movdqu(xmm0, src); 4941 movdqu(xmm1, dst); 4942 Assembler::vptest(xmm1, xmm0); 4943 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4944 addptr(rsp, 64); 4945 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4946 addptr(rsp, 64); 4947 } 4948 } 4949 4950 // This instruction exists within macros, ergo we cannot control its input 4951 // when emitted through those patterns. 4952 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4953 if (VM_Version::supports_avx512nobw()) { 4954 int dst_enc = dst->encoding(); 4955 int src_enc = src->encoding(); 4956 if (dst_enc == src_enc) { 4957 if (dst_enc < 16) { 4958 Assembler::punpcklbw(dst, src); 4959 } else { 4960 subptr(rsp, 64); 4961 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4962 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4963 Assembler::punpcklbw(xmm0, xmm0); 4964 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4965 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4966 addptr(rsp, 64); 4967 } 4968 } else { 4969 if ((src_enc < 16) && (dst_enc < 16)) { 4970 Assembler::punpcklbw(dst, src); 4971 } else if (src_enc < 16) { 4972 subptr(rsp, 64); 4973 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4974 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4975 Assembler::punpcklbw(xmm0, src); 4976 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4977 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4978 addptr(rsp, 64); 4979 } else if (dst_enc < 16) { 4980 subptr(rsp, 64); 4981 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4982 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4983 Assembler::punpcklbw(dst, xmm0); 4984 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4985 addptr(rsp, 64); 4986 } else { 4987 subptr(rsp, 64); 4988 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4989 subptr(rsp, 64); 4990 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4991 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4992 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4993 Assembler::punpcklbw(xmm0, xmm1); 4994 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4995 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4996 addptr(rsp, 64); 4997 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4998 addptr(rsp, 64); 4999 } 5000 } 5001 } else { 5002 Assembler::punpcklbw(dst, src); 5003 } 5004 } 5005 5006 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) { 5007 if (VM_Version::supports_avx512vl()) { 5008 Assembler::pshufd(dst, src, mode); 5009 } else { 5010 int dst_enc = dst->encoding(); 5011 if (dst_enc < 16) { 5012 Assembler::pshufd(dst, src, mode); 5013 } else { 5014 subptr(rsp, 64); 5015 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5016 Assembler::pshufd(xmm0, src, mode); 5017 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5018 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5019 addptr(rsp, 64); 5020 } 5021 } 5022 } 5023 5024 // This instruction exists within macros, ergo we cannot control its input 5025 // when emitted through those patterns. 5026 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 5027 if (VM_Version::supports_avx512nobw()) { 5028 int dst_enc = dst->encoding(); 5029 int src_enc = src->encoding(); 5030 if (dst_enc == src_enc) { 5031 if (dst_enc < 16) { 5032 Assembler::pshuflw(dst, src, mode); 5033 } else { 5034 subptr(rsp, 64); 5035 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5036 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5037 Assembler::pshuflw(xmm0, xmm0, mode); 5038 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5039 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5040 addptr(rsp, 64); 5041 } 5042 } else { 5043 if ((src_enc < 16) && (dst_enc < 16)) { 5044 Assembler::pshuflw(dst, src, mode); 5045 } else if (src_enc < 16) { 5046 subptr(rsp, 64); 5047 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5048 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5049 Assembler::pshuflw(xmm0, src, mode); 5050 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5051 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5052 addptr(rsp, 64); 5053 } else if (dst_enc < 16) { 5054 subptr(rsp, 64); 5055 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5056 evmovdqul(xmm0, src, Assembler::AVX_512bit); 5057 Assembler::pshuflw(dst, xmm0, mode); 5058 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5059 addptr(rsp, 64); 5060 } else { 5061 subptr(rsp, 64); 5062 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5063 subptr(rsp, 64); 5064 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 5065 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5066 evmovdqul(xmm1, src, Assembler::AVX_512bit); 5067 Assembler::pshuflw(xmm0, xmm1, mode); 5068 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5069 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 5070 addptr(rsp, 64); 5071 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5072 addptr(rsp, 64); 5073 } 5074 } 5075 } else { 5076 Assembler::pshuflw(dst, src, mode); 5077 } 5078 } 5079 5080 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5081 if (reachable(src)) { 5082 vandpd(dst, nds, as_Address(src), vector_len); 5083 } else { 5084 lea(rscratch1, src); 5085 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 5086 } 5087 } 5088 5089 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5090 if (reachable(src)) { 5091 vandps(dst, nds, as_Address(src), vector_len); 5092 } else { 5093 lea(rscratch1, src); 5094 vandps(dst, nds, Address(rscratch1, 0), vector_len); 5095 } 5096 } 5097 5098 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5099 if (reachable(src)) { 5100 vdivsd(dst, nds, as_Address(src)); 5101 } else { 5102 lea(rscratch1, src); 5103 vdivsd(dst, nds, Address(rscratch1, 0)); 5104 } 5105 } 5106 5107 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5108 if (reachable(src)) { 5109 vdivss(dst, nds, as_Address(src)); 5110 } else { 5111 lea(rscratch1, src); 5112 vdivss(dst, nds, Address(rscratch1, 0)); 5113 } 5114 } 5115 5116 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5117 if (reachable(src)) { 5118 vmulsd(dst, nds, as_Address(src)); 5119 } else { 5120 lea(rscratch1, src); 5121 vmulsd(dst, nds, Address(rscratch1, 0)); 5122 } 5123 } 5124 5125 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5126 if (reachable(src)) { 5127 vmulss(dst, nds, as_Address(src)); 5128 } else { 5129 lea(rscratch1, src); 5130 vmulss(dst, nds, Address(rscratch1, 0)); 5131 } 5132 } 5133 5134 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5135 if (reachable(src)) { 5136 vsubsd(dst, nds, as_Address(src)); 5137 } else { 5138 lea(rscratch1, src); 5139 vsubsd(dst, nds, Address(rscratch1, 0)); 5140 } 5141 } 5142 5143 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5144 if (reachable(src)) { 5145 vsubss(dst, nds, as_Address(src)); 5146 } else { 5147 lea(rscratch1, src); 5148 vsubss(dst, nds, Address(rscratch1, 0)); 5149 } 5150 } 5151 5152 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5153 int nds_enc = nds->encoding(); 5154 int dst_enc = dst->encoding(); 5155 bool dst_upper_bank = (dst_enc > 15); 5156 bool nds_upper_bank = (nds_enc > 15); 5157 if (VM_Version::supports_avx512novl() && 5158 (nds_upper_bank || dst_upper_bank)) { 5159 if (dst_upper_bank) { 5160 subptr(rsp, 64); 5161 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5162 movflt(xmm0, nds); 5163 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5164 movflt(dst, xmm0); 5165 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5166 addptr(rsp, 64); 5167 } else { 5168 movflt(dst, nds); 5169 vxorps(dst, dst, src, Assembler::AVX_128bit); 5170 } 5171 } else { 5172 vxorps(dst, nds, src, Assembler::AVX_128bit); 5173 } 5174 } 5175 5176 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5177 int nds_enc = nds->encoding(); 5178 int dst_enc = dst->encoding(); 5179 bool dst_upper_bank = (dst_enc > 15); 5180 bool nds_upper_bank = (nds_enc > 15); 5181 if (VM_Version::supports_avx512novl() && 5182 (nds_upper_bank || dst_upper_bank)) { 5183 if (dst_upper_bank) { 5184 subptr(rsp, 64); 5185 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5186 movdbl(xmm0, nds); 5187 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5188 movdbl(dst, xmm0); 5189 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5190 addptr(rsp, 64); 5191 } else { 5192 movdbl(dst, nds); 5193 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5194 } 5195 } else { 5196 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5197 } 5198 } 5199 5200 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5201 if (reachable(src)) { 5202 vxorpd(dst, nds, as_Address(src), vector_len); 5203 } else { 5204 lea(rscratch1, src); 5205 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5206 } 5207 } 5208 5209 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5210 if (reachable(src)) { 5211 vxorps(dst, nds, as_Address(src), vector_len); 5212 } else { 5213 lea(rscratch1, src); 5214 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5215 } 5216 } 5217 5218 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { 5219 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); 5220 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code 5221 // The inverted mask is sign-extended 5222 andptr(possibly_jweak, inverted_jweak_mask); 5223 } 5224 5225 void MacroAssembler::resolve_jobject(Register value, 5226 Register thread, 5227 Register tmp) { 5228 assert_different_registers(value, thread, tmp); 5229 Label done, not_weak; 5230 testptr(value, value); 5231 jcc(Assembler::zero, done); // Use NULL as-is. 5232 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag. 5233 jcc(Assembler::zero, not_weak); 5234 // Resolve jweak. 5235 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 5236 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread); 5237 verify_oop(value); 5238 jmp(done); 5239 bind(not_weak); 5240 // Resolve (untagged) jobject. 5241 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, 5242 value, Address(value, 0), tmp, thread); 5243 verify_oop(value); 5244 bind(done); 5245 } 5246 5247 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5248 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5249 } 5250 5251 // Force generation of a 4 byte immediate value even if it fits into 8bit 5252 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5253 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5254 } 5255 5256 void MacroAssembler::subptr(Register dst, Register src) { 5257 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5258 } 5259 5260 // C++ bool manipulation 5261 void MacroAssembler::testbool(Register dst) { 5262 if(sizeof(bool) == 1) 5263 testb(dst, 0xff); 5264 else if(sizeof(bool) == 2) { 5265 // testw implementation needed for two byte bools 5266 ShouldNotReachHere(); 5267 } else if(sizeof(bool) == 4) 5268 testl(dst, dst); 5269 else 5270 // unsupported 5271 ShouldNotReachHere(); 5272 } 5273 5274 void MacroAssembler::testptr(Register dst, Register src) { 5275 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5276 } 5277 5278 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5279 void MacroAssembler::tlab_allocate(Register thread, Register obj, 5280 Register var_size_in_bytes, 5281 int con_size_in_bytes, 5282 Register t1, 5283 Register t2, 5284 Label& slow_case) { 5285 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5286 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 5287 } 5288 5289 // Defines obj, preserves var_size_in_bytes 5290 void MacroAssembler::eden_allocate(Register thread, Register obj, 5291 Register var_size_in_bytes, 5292 int con_size_in_bytes, 5293 Register t1, 5294 Label& slow_case) { 5295 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5296 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case); 5297 } 5298 5299 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5300 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5301 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5302 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5303 Label done; 5304 5305 testptr(length_in_bytes, length_in_bytes); 5306 jcc(Assembler::zero, done); 5307 5308 // initialize topmost word, divide index by 2, check if odd and test if zero 5309 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5310 #ifdef ASSERT 5311 { 5312 Label L; 5313 testptr(length_in_bytes, BytesPerWord - 1); 5314 jcc(Assembler::zero, L); 5315 stop("length must be a multiple of BytesPerWord"); 5316 bind(L); 5317 } 5318 #endif 5319 Register index = length_in_bytes; 5320 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5321 if (UseIncDec) { 5322 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5323 } else { 5324 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5325 shrptr(index, 1); 5326 } 5327 #ifndef _LP64 5328 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5329 { 5330 Label even; 5331 // note: if index was a multiple of 8, then it cannot 5332 // be 0 now otherwise it must have been 0 before 5333 // => if it is even, we don't need to check for 0 again 5334 jcc(Assembler::carryClear, even); 5335 // clear topmost word (no jump would be needed if conditional assignment worked here) 5336 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5337 // index could be 0 now, must check again 5338 jcc(Assembler::zero, done); 5339 bind(even); 5340 } 5341 #endif // !_LP64 5342 // initialize remaining object fields: index is a multiple of 2 now 5343 { 5344 Label loop; 5345 bind(loop); 5346 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5347 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5348 decrement(index); 5349 jcc(Assembler::notZero, loop); 5350 } 5351 5352 bind(done); 5353 } 5354 5355 // Look up the method for a megamorphic invokeinterface call. 5356 // The target method is determined by <intf_klass, itable_index>. 5357 // The receiver klass is in recv_klass. 5358 // On success, the result will be in method_result, and execution falls through. 5359 // On failure, execution transfers to the given label. 5360 void MacroAssembler::lookup_interface_method(Register recv_klass, 5361 Register intf_klass, 5362 RegisterOrConstant itable_index, 5363 Register method_result, 5364 Register scan_temp, 5365 Label& L_no_such_interface, 5366 bool return_method) { 5367 assert_different_registers(recv_klass, intf_klass, scan_temp); 5368 assert_different_registers(method_result, intf_klass, scan_temp); 5369 assert(recv_klass != method_result || !return_method, 5370 "recv_klass can be destroyed when method isn't needed"); 5371 5372 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5373 "caller must use same register for non-constant itable index as for method"); 5374 5375 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5376 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5377 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5378 int scan_step = itableOffsetEntry::size() * wordSize; 5379 int vte_size = vtableEntry::size_in_bytes(); 5380 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5381 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5382 5383 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5384 5385 // %%% Could store the aligned, prescaled offset in the klassoop. 5386 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5387 5388 if (return_method) { 5389 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5390 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5391 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5392 } 5393 5394 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5395 // if (scan->interface() == intf) { 5396 // result = (klass + scan->offset() + itable_index); 5397 // } 5398 // } 5399 Label search, found_method; 5400 5401 for (int peel = 1; peel >= 0; peel--) { 5402 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5403 cmpptr(intf_klass, method_result); 5404 5405 if (peel) { 5406 jccb(Assembler::equal, found_method); 5407 } else { 5408 jccb(Assembler::notEqual, search); 5409 // (invert the test to fall through to found_method...) 5410 } 5411 5412 if (!peel) break; 5413 5414 bind(search); 5415 5416 // Check that the previous entry is non-null. A null entry means that 5417 // the receiver class doesn't implement the interface, and wasn't the 5418 // same as when the caller was compiled. 5419 testptr(method_result, method_result); 5420 jcc(Assembler::zero, L_no_such_interface); 5421 addptr(scan_temp, scan_step); 5422 } 5423 5424 bind(found_method); 5425 5426 if (return_method) { 5427 // Got a hit. 5428 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5429 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5430 } 5431 } 5432 5433 5434 // virtual method calling 5435 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5436 RegisterOrConstant vtable_index, 5437 Register method_result) { 5438 const int base = in_bytes(Klass::vtable_start_offset()); 5439 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5440 Address vtable_entry_addr(recv_klass, 5441 vtable_index, Address::times_ptr, 5442 base + vtableEntry::method_offset_in_bytes()); 5443 movptr(method_result, vtable_entry_addr); 5444 } 5445 5446 5447 void MacroAssembler::check_klass_subtype(Register sub_klass, 5448 Register super_klass, 5449 Register temp_reg, 5450 Label& L_success) { 5451 Label L_failure; 5452 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5453 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5454 bind(L_failure); 5455 } 5456 5457 5458 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5459 Register super_klass, 5460 Register temp_reg, 5461 Label* L_success, 5462 Label* L_failure, 5463 Label* L_slow_path, 5464 RegisterOrConstant super_check_offset) { 5465 assert_different_registers(sub_klass, super_klass, temp_reg); 5466 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5467 if (super_check_offset.is_register()) { 5468 assert_different_registers(sub_klass, super_klass, 5469 super_check_offset.as_register()); 5470 } else if (must_load_sco) { 5471 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5472 } 5473 5474 Label L_fallthrough; 5475 int label_nulls = 0; 5476 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5477 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5478 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5479 assert(label_nulls <= 1, "at most one NULL in the batch"); 5480 5481 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5482 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5483 Address super_check_offset_addr(super_klass, sco_offset); 5484 5485 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5486 // range of a jccb. If this routine grows larger, reconsider at 5487 // least some of these. 5488 #define local_jcc(assembler_cond, label) \ 5489 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5490 else jcc( assembler_cond, label) /*omit semi*/ 5491 5492 // Hacked jmp, which may only be used just before L_fallthrough. 5493 #define final_jmp(label) \ 5494 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5495 else jmp(label) /*omit semi*/ 5496 5497 // If the pointers are equal, we are done (e.g., String[] elements). 5498 // This self-check enables sharing of secondary supertype arrays among 5499 // non-primary types such as array-of-interface. Otherwise, each such 5500 // type would need its own customized SSA. 5501 // We move this check to the front of the fast path because many 5502 // type checks are in fact trivially successful in this manner, 5503 // so we get a nicely predicted branch right at the start of the check. 5504 cmpptr(sub_klass, super_klass); 5505 local_jcc(Assembler::equal, *L_success); 5506 5507 // Check the supertype display: 5508 if (must_load_sco) { 5509 // Positive movl does right thing on LP64. 5510 movl(temp_reg, super_check_offset_addr); 5511 super_check_offset = RegisterOrConstant(temp_reg); 5512 } 5513 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5514 cmpptr(super_klass, super_check_addr); // load displayed supertype 5515 5516 // This check has worked decisively for primary supers. 5517 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5518 // (Secondary supers are interfaces and very deeply nested subtypes.) 5519 // This works in the same check above because of a tricky aliasing 5520 // between the super_cache and the primary super display elements. 5521 // (The 'super_check_addr' can address either, as the case requires.) 5522 // Note that the cache is updated below if it does not help us find 5523 // what we need immediately. 5524 // So if it was a primary super, we can just fail immediately. 5525 // Otherwise, it's the slow path for us (no success at this point). 5526 5527 if (super_check_offset.is_register()) { 5528 local_jcc(Assembler::equal, *L_success); 5529 cmpl(super_check_offset.as_register(), sc_offset); 5530 if (L_failure == &L_fallthrough) { 5531 local_jcc(Assembler::equal, *L_slow_path); 5532 } else { 5533 local_jcc(Assembler::notEqual, *L_failure); 5534 final_jmp(*L_slow_path); 5535 } 5536 } else if (super_check_offset.as_constant() == sc_offset) { 5537 // Need a slow path; fast failure is impossible. 5538 if (L_slow_path == &L_fallthrough) { 5539 local_jcc(Assembler::equal, *L_success); 5540 } else { 5541 local_jcc(Assembler::notEqual, *L_slow_path); 5542 final_jmp(*L_success); 5543 } 5544 } else { 5545 // No slow path; it's a fast decision. 5546 if (L_failure == &L_fallthrough) { 5547 local_jcc(Assembler::equal, *L_success); 5548 } else { 5549 local_jcc(Assembler::notEqual, *L_failure); 5550 final_jmp(*L_success); 5551 } 5552 } 5553 5554 bind(L_fallthrough); 5555 5556 #undef local_jcc 5557 #undef final_jmp 5558 } 5559 5560 5561 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5562 Register super_klass, 5563 Register temp_reg, 5564 Register temp2_reg, 5565 Label* L_success, 5566 Label* L_failure, 5567 bool set_cond_codes) { 5568 assert_different_registers(sub_klass, super_klass, temp_reg); 5569 if (temp2_reg != noreg) 5570 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5571 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5572 5573 Label L_fallthrough; 5574 int label_nulls = 0; 5575 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5576 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5577 assert(label_nulls <= 1, "at most one NULL in the batch"); 5578 5579 // a couple of useful fields in sub_klass: 5580 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5581 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5582 Address secondary_supers_addr(sub_klass, ss_offset); 5583 Address super_cache_addr( sub_klass, sc_offset); 5584 5585 // Do a linear scan of the secondary super-klass chain. 5586 // This code is rarely used, so simplicity is a virtue here. 5587 // The repne_scan instruction uses fixed registers, which we must spill. 5588 // Don't worry too much about pre-existing connections with the input regs. 5589 5590 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5591 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5592 5593 // Get super_klass value into rax (even if it was in rdi or rcx). 5594 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5595 if (super_klass != rax || UseCompressedOops) { 5596 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5597 mov(rax, super_klass); 5598 } 5599 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5600 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5601 5602 #ifndef PRODUCT 5603 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5604 ExternalAddress pst_counter_addr((address) pst_counter); 5605 NOT_LP64( incrementl(pst_counter_addr) ); 5606 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5607 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5608 #endif //PRODUCT 5609 5610 // We will consult the secondary-super array. 5611 movptr(rdi, secondary_supers_addr); 5612 // Load the array length. (Positive movl does right thing on LP64.) 5613 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5614 // Skip to start of data. 5615 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5616 5617 // Scan RCX words at [RDI] for an occurrence of RAX. 5618 // Set NZ/Z based on last compare. 5619 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5620 // not change flags (only scas instruction which is repeated sets flags). 5621 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5622 5623 testptr(rax,rax); // Set Z = 0 5624 repne_scan(); 5625 5626 // Unspill the temp. registers: 5627 if (pushed_rdi) pop(rdi); 5628 if (pushed_rcx) pop(rcx); 5629 if (pushed_rax) pop(rax); 5630 5631 if (set_cond_codes) { 5632 // Special hack for the AD files: rdi is guaranteed non-zero. 5633 assert(!pushed_rdi, "rdi must be left non-NULL"); 5634 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5635 } 5636 5637 if (L_failure == &L_fallthrough) 5638 jccb(Assembler::notEqual, *L_failure); 5639 else jcc(Assembler::notEqual, *L_failure); 5640 5641 // Success. Cache the super we found and proceed in triumph. 5642 movptr(super_cache_addr, super_klass); 5643 5644 if (L_success != &L_fallthrough) { 5645 jmp(*L_success); 5646 } 5647 5648 #undef IS_A_TEMP 5649 5650 bind(L_fallthrough); 5651 } 5652 5653 5654 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5655 if (VM_Version::supports_cmov()) { 5656 cmovl(cc, dst, src); 5657 } else { 5658 Label L; 5659 jccb(negate_condition(cc), L); 5660 movl(dst, src); 5661 bind(L); 5662 } 5663 } 5664 5665 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5666 if (VM_Version::supports_cmov()) { 5667 cmovl(cc, dst, src); 5668 } else { 5669 Label L; 5670 jccb(negate_condition(cc), L); 5671 movl(dst, src); 5672 bind(L); 5673 } 5674 } 5675 5676 void MacroAssembler::verify_oop(Register reg, const char* s) { 5677 if (!VerifyOops) return; 5678 5679 // Pass register number to verify_oop_subroutine 5680 const char* b = NULL; 5681 { 5682 ResourceMark rm; 5683 stringStream ss; 5684 ss.print("verify_oop: %s: %s", reg->name(), s); 5685 b = code_string(ss.as_string()); 5686 } 5687 BLOCK_COMMENT("verify_oop {"); 5688 #ifdef _LP64 5689 push(rscratch1); // save r10, trashed by movptr() 5690 #endif 5691 push(rax); // save rax, 5692 push(reg); // pass register argument 5693 ExternalAddress buffer((address) b); 5694 // avoid using pushptr, as it modifies scratch registers 5695 // and our contract is not to modify anything 5696 movptr(rax, buffer.addr()); 5697 push(rax); 5698 // call indirectly to solve generation ordering problem 5699 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5700 call(rax); 5701 // Caller pops the arguments (oop, message) and restores rax, r10 5702 BLOCK_COMMENT("} verify_oop"); 5703 } 5704 5705 5706 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 5707 Register tmp, 5708 int offset) { 5709 intptr_t value = *delayed_value_addr; 5710 if (value != 0) 5711 return RegisterOrConstant(value + offset); 5712 5713 // load indirectly to solve generation ordering problem 5714 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 5715 5716 #ifdef ASSERT 5717 { Label L; 5718 testptr(tmp, tmp); 5719 if (WizardMode) { 5720 const char* buf = NULL; 5721 { 5722 ResourceMark rm; 5723 stringStream ss; 5724 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 5725 buf = code_string(ss.as_string()); 5726 } 5727 jcc(Assembler::notZero, L); 5728 STOP(buf); 5729 } else { 5730 jccb(Assembler::notZero, L); 5731 hlt(); 5732 } 5733 bind(L); 5734 } 5735 #endif 5736 5737 if (offset != 0) 5738 addptr(tmp, offset); 5739 5740 return RegisterOrConstant(tmp); 5741 } 5742 5743 5744 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 5745 int extra_slot_offset) { 5746 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 5747 int stackElementSize = Interpreter::stackElementSize; 5748 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 5749 #ifdef ASSERT 5750 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 5751 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 5752 #endif 5753 Register scale_reg = noreg; 5754 Address::ScaleFactor scale_factor = Address::no_scale; 5755 if (arg_slot.is_constant()) { 5756 offset += arg_slot.as_constant() * stackElementSize; 5757 } else { 5758 scale_reg = arg_slot.as_register(); 5759 scale_factor = Address::times(stackElementSize); 5760 } 5761 offset += wordSize; // return PC is on stack 5762 return Address(rsp, scale_reg, scale_factor, offset); 5763 } 5764 5765 5766 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 5767 if (!VerifyOops) return; 5768 5769 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 5770 // Pass register number to verify_oop_subroutine 5771 const char* b = NULL; 5772 { 5773 ResourceMark rm; 5774 stringStream ss; 5775 ss.print("verify_oop_addr: %s", s); 5776 b = code_string(ss.as_string()); 5777 } 5778 #ifdef _LP64 5779 push(rscratch1); // save r10, trashed by movptr() 5780 #endif 5781 push(rax); // save rax, 5782 // addr may contain rsp so we will have to adjust it based on the push 5783 // we just did (and on 64 bit we do two pushes) 5784 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 5785 // stores rax into addr which is backwards of what was intended. 5786 if (addr.uses(rsp)) { 5787 lea(rax, addr); 5788 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 5789 } else { 5790 pushptr(addr); 5791 } 5792 5793 ExternalAddress buffer((address) b); 5794 // pass msg argument 5795 // avoid using pushptr, as it modifies scratch registers 5796 // and our contract is not to modify anything 5797 movptr(rax, buffer.addr()); 5798 push(rax); 5799 5800 // call indirectly to solve generation ordering problem 5801 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5802 call(rax); 5803 // Caller pops the arguments (addr, message) and restores rax, r10. 5804 } 5805 5806 void MacroAssembler::verify_tlab() { 5807 #ifdef ASSERT 5808 if (UseTLAB && VerifyOops) { 5809 Label next, ok; 5810 Register t1 = rsi; 5811 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 5812 5813 push(t1); 5814 NOT_LP64(push(thread_reg)); 5815 NOT_LP64(get_thread(thread_reg)); 5816 5817 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5818 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5819 jcc(Assembler::aboveEqual, next); 5820 STOP("assert(top >= start)"); 5821 should_not_reach_here(); 5822 5823 bind(next); 5824 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5825 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5826 jcc(Assembler::aboveEqual, ok); 5827 STOP("assert(top <= end)"); 5828 should_not_reach_here(); 5829 5830 bind(ok); 5831 NOT_LP64(pop(thread_reg)); 5832 pop(t1); 5833 } 5834 #endif 5835 } 5836 5837 class ControlWord { 5838 public: 5839 int32_t _value; 5840 5841 int rounding_control() const { return (_value >> 10) & 3 ; } 5842 int precision_control() const { return (_value >> 8) & 3 ; } 5843 bool precision() const { return ((_value >> 5) & 1) != 0; } 5844 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5845 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5846 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5847 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5848 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5849 5850 void print() const { 5851 // rounding control 5852 const char* rc; 5853 switch (rounding_control()) { 5854 case 0: rc = "round near"; break; 5855 case 1: rc = "round down"; break; 5856 case 2: rc = "round up "; break; 5857 case 3: rc = "chop "; break; 5858 }; 5859 // precision control 5860 const char* pc; 5861 switch (precision_control()) { 5862 case 0: pc = "24 bits "; break; 5863 case 1: pc = "reserved"; break; 5864 case 2: pc = "53 bits "; break; 5865 case 3: pc = "64 bits "; break; 5866 }; 5867 // flags 5868 char f[9]; 5869 f[0] = ' '; 5870 f[1] = ' '; 5871 f[2] = (precision ()) ? 'P' : 'p'; 5872 f[3] = (underflow ()) ? 'U' : 'u'; 5873 f[4] = (overflow ()) ? 'O' : 'o'; 5874 f[5] = (zero_divide ()) ? 'Z' : 'z'; 5875 f[6] = (denormalized()) ? 'D' : 'd'; 5876 f[7] = (invalid ()) ? 'I' : 'i'; 5877 f[8] = '\x0'; 5878 // output 5879 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 5880 } 5881 5882 }; 5883 5884 class StatusWord { 5885 public: 5886 int32_t _value; 5887 5888 bool busy() const { return ((_value >> 15) & 1) != 0; } 5889 bool C3() const { return ((_value >> 14) & 1) != 0; } 5890 bool C2() const { return ((_value >> 10) & 1) != 0; } 5891 bool C1() const { return ((_value >> 9) & 1) != 0; } 5892 bool C0() const { return ((_value >> 8) & 1) != 0; } 5893 int top() const { return (_value >> 11) & 7 ; } 5894 bool error_status() const { return ((_value >> 7) & 1) != 0; } 5895 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 5896 bool precision() const { return ((_value >> 5) & 1) != 0; } 5897 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5898 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5899 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5900 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5901 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5902 5903 void print() const { 5904 // condition codes 5905 char c[5]; 5906 c[0] = (C3()) ? '3' : '-'; 5907 c[1] = (C2()) ? '2' : '-'; 5908 c[2] = (C1()) ? '1' : '-'; 5909 c[3] = (C0()) ? '0' : '-'; 5910 c[4] = '\x0'; 5911 // flags 5912 char f[9]; 5913 f[0] = (error_status()) ? 'E' : '-'; 5914 f[1] = (stack_fault ()) ? 'S' : '-'; 5915 f[2] = (precision ()) ? 'P' : '-'; 5916 f[3] = (underflow ()) ? 'U' : '-'; 5917 f[4] = (overflow ()) ? 'O' : '-'; 5918 f[5] = (zero_divide ()) ? 'Z' : '-'; 5919 f[6] = (denormalized()) ? 'D' : '-'; 5920 f[7] = (invalid ()) ? 'I' : '-'; 5921 f[8] = '\x0'; 5922 // output 5923 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 5924 } 5925 5926 }; 5927 5928 class TagWord { 5929 public: 5930 int32_t _value; 5931 5932 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 5933 5934 void print() const { 5935 printf("%04x", _value & 0xFFFF); 5936 } 5937 5938 }; 5939 5940 class FPU_Register { 5941 public: 5942 int32_t _m0; 5943 int32_t _m1; 5944 int16_t _ex; 5945 5946 bool is_indefinite() const { 5947 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 5948 } 5949 5950 void print() const { 5951 char sign = (_ex < 0) ? '-' : '+'; 5952 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 5953 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 5954 }; 5955 5956 }; 5957 5958 class FPU_State { 5959 public: 5960 enum { 5961 register_size = 10, 5962 number_of_registers = 8, 5963 register_mask = 7 5964 }; 5965 5966 ControlWord _control_word; 5967 StatusWord _status_word; 5968 TagWord _tag_word; 5969 int32_t _error_offset; 5970 int32_t _error_selector; 5971 int32_t _data_offset; 5972 int32_t _data_selector; 5973 int8_t _register[register_size * number_of_registers]; 5974 5975 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 5976 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 5977 5978 const char* tag_as_string(int tag) const { 5979 switch (tag) { 5980 case 0: return "valid"; 5981 case 1: return "zero"; 5982 case 2: return "special"; 5983 case 3: return "empty"; 5984 } 5985 ShouldNotReachHere(); 5986 return NULL; 5987 } 5988 5989 void print() const { 5990 // print computation registers 5991 { int t = _status_word.top(); 5992 for (int i = 0; i < number_of_registers; i++) { 5993 int j = (i - t) & register_mask; 5994 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 5995 st(j)->print(); 5996 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 5997 } 5998 } 5999 printf("\n"); 6000 // print control registers 6001 printf("ctrl = "); _control_word.print(); printf("\n"); 6002 printf("stat = "); _status_word .print(); printf("\n"); 6003 printf("tags = "); _tag_word .print(); printf("\n"); 6004 } 6005 6006 }; 6007 6008 class Flag_Register { 6009 public: 6010 int32_t _value; 6011 6012 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6013 bool direction() const { return ((_value >> 10) & 1) != 0; } 6014 bool sign() const { return ((_value >> 7) & 1) != 0; } 6015 bool zero() const { return ((_value >> 6) & 1) != 0; } 6016 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6017 bool parity() const { return ((_value >> 2) & 1) != 0; } 6018 bool carry() const { return ((_value >> 0) & 1) != 0; } 6019 6020 void print() const { 6021 // flags 6022 char f[8]; 6023 f[0] = (overflow ()) ? 'O' : '-'; 6024 f[1] = (direction ()) ? 'D' : '-'; 6025 f[2] = (sign ()) ? 'S' : '-'; 6026 f[3] = (zero ()) ? 'Z' : '-'; 6027 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6028 f[5] = (parity ()) ? 'P' : '-'; 6029 f[6] = (carry ()) ? 'C' : '-'; 6030 f[7] = '\x0'; 6031 // output 6032 printf("%08x flags = %s", _value, f); 6033 } 6034 6035 }; 6036 6037 class IU_Register { 6038 public: 6039 int32_t _value; 6040 6041 void print() const { 6042 printf("%08x %11d", _value, _value); 6043 } 6044 6045 }; 6046 6047 class IU_State { 6048 public: 6049 Flag_Register _eflags; 6050 IU_Register _rdi; 6051 IU_Register _rsi; 6052 IU_Register _rbp; 6053 IU_Register _rsp; 6054 IU_Register _rbx; 6055 IU_Register _rdx; 6056 IU_Register _rcx; 6057 IU_Register _rax; 6058 6059 void print() const { 6060 // computation registers 6061 printf("rax, = "); _rax.print(); printf("\n"); 6062 printf("rbx, = "); _rbx.print(); printf("\n"); 6063 printf("rcx = "); _rcx.print(); printf("\n"); 6064 printf("rdx = "); _rdx.print(); printf("\n"); 6065 printf("rdi = "); _rdi.print(); printf("\n"); 6066 printf("rsi = "); _rsi.print(); printf("\n"); 6067 printf("rbp, = "); _rbp.print(); printf("\n"); 6068 printf("rsp = "); _rsp.print(); printf("\n"); 6069 printf("\n"); 6070 // control registers 6071 printf("flgs = "); _eflags.print(); printf("\n"); 6072 } 6073 }; 6074 6075 6076 class CPU_State { 6077 public: 6078 FPU_State _fpu_state; 6079 IU_State _iu_state; 6080 6081 void print() const { 6082 printf("--------------------------------------------------\n"); 6083 _iu_state .print(); 6084 printf("\n"); 6085 _fpu_state.print(); 6086 printf("--------------------------------------------------\n"); 6087 } 6088 6089 }; 6090 6091 6092 static void _print_CPU_state(CPU_State* state) { 6093 state->print(); 6094 }; 6095 6096 6097 void MacroAssembler::print_CPU_state() { 6098 push_CPU_state(); 6099 push(rsp); // pass CPU state 6100 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6101 addptr(rsp, wordSize); // discard argument 6102 pop_CPU_state(); 6103 } 6104 6105 6106 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6107 static int counter = 0; 6108 FPU_State* fs = &state->_fpu_state; 6109 counter++; 6110 // For leaf calls, only verify that the top few elements remain empty. 6111 // We only need 1 empty at the top for C2 code. 6112 if( stack_depth < 0 ) { 6113 if( fs->tag_for_st(7) != 3 ) { 6114 printf("FPR7 not empty\n"); 6115 state->print(); 6116 assert(false, "error"); 6117 return false; 6118 } 6119 return true; // All other stack states do not matter 6120 } 6121 6122 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6123 "bad FPU control word"); 6124 6125 // compute stack depth 6126 int i = 0; 6127 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6128 int d = i; 6129 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6130 // verify findings 6131 if (i != FPU_State::number_of_registers) { 6132 // stack not contiguous 6133 printf("%s: stack not contiguous at ST%d\n", s, i); 6134 state->print(); 6135 assert(false, "error"); 6136 return false; 6137 } 6138 // check if computed stack depth corresponds to expected stack depth 6139 if (stack_depth < 0) { 6140 // expected stack depth is -stack_depth or less 6141 if (d > -stack_depth) { 6142 // too many elements on the stack 6143 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6144 state->print(); 6145 assert(false, "error"); 6146 return false; 6147 } 6148 } else { 6149 // expected stack depth is stack_depth 6150 if (d != stack_depth) { 6151 // wrong stack depth 6152 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6153 state->print(); 6154 assert(false, "error"); 6155 return false; 6156 } 6157 } 6158 // everything is cool 6159 return true; 6160 } 6161 6162 6163 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6164 if (!VerifyFPU) return; 6165 push_CPU_state(); 6166 push(rsp); // pass CPU state 6167 ExternalAddress msg((address) s); 6168 // pass message string s 6169 pushptr(msg.addr()); 6170 push(stack_depth); // pass stack depth 6171 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6172 addptr(rsp, 3 * wordSize); // discard arguments 6173 // check for error 6174 { Label L; 6175 testl(rax, rax); 6176 jcc(Assembler::notZero, L); 6177 int3(); // break if error condition 6178 bind(L); 6179 } 6180 pop_CPU_state(); 6181 } 6182 6183 void MacroAssembler::restore_cpu_control_state_after_jni() { 6184 // Either restore the MXCSR register after returning from the JNI Call 6185 // or verify that it wasn't changed (with -Xcheck:jni flag). 6186 if (VM_Version::supports_sse()) { 6187 if (RestoreMXCSROnJNICalls) { 6188 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6189 } else if (CheckJNICalls) { 6190 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6191 } 6192 } 6193 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6194 vzeroupper(); 6195 // Reset k1 to 0xffff. 6196 if (VM_Version::supports_evex()) { 6197 push(rcx); 6198 movl(rcx, 0xffff); 6199 kmovwl(k1, rcx); 6200 pop(rcx); 6201 } 6202 6203 #ifndef _LP64 6204 // Either restore the x87 floating pointer control word after returning 6205 // from the JNI call or verify that it wasn't changed. 6206 if (CheckJNICalls) { 6207 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6208 } 6209 #endif // _LP64 6210 } 6211 6212 // ((OopHandle)result).resolve(); 6213 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { 6214 assert_different_registers(result, tmp); 6215 6216 // Only 64 bit platforms support GCs that require a tmp register 6217 // Only IN_HEAP loads require a thread_tmp register 6218 // OopHandle::resolve is an indirection like jobject. 6219 access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, 6220 result, Address(result, 0), tmp, /*tmp_thread*/noreg); 6221 } 6222 6223 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) { 6224 // get mirror 6225 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6226 movptr(mirror, Address(method, Method::const_offset())); 6227 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6228 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6229 movptr(mirror, Address(mirror, mirror_offset)); 6230 resolve_oop_handle(mirror, tmp); 6231 } 6232 6233 void MacroAssembler::load_klass(Register dst, Register src) { 6234 #ifdef _LP64 6235 if (UseCompressedClassPointers) { 6236 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6237 decode_klass_not_null(dst); 6238 } else 6239 #endif 6240 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6241 } 6242 6243 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6244 load_klass(dst, src); 6245 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6246 } 6247 6248 void MacroAssembler::store_klass(Register dst, Register src) { 6249 #ifdef _LP64 6250 if (UseCompressedClassPointers) { 6251 encode_klass_not_null(src); 6252 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6253 } else 6254 #endif 6255 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6256 } 6257 6258 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 6259 Register tmp1, Register thread_tmp) { 6260 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 6261 decorators = AccessInternal::decorator_fixup(decorators); 6262 bool as_raw = (decorators & AS_RAW) != 0; 6263 if (as_raw) { 6264 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 6265 } else { 6266 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 6267 } 6268 } 6269 6270 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src, 6271 Register tmp1, Register tmp2) { 6272 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 6273 decorators = AccessInternal::decorator_fixup(decorators); 6274 bool as_raw = (decorators & AS_RAW) != 0; 6275 if (as_raw) { 6276 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2); 6277 } else { 6278 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2); 6279 } 6280 } 6281 6282 void MacroAssembler::resolve_for_read(DecoratorSet decorators, Register obj) { 6283 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 6284 return bs->resolve_for_read(this, decorators, obj); 6285 } 6286 6287 void MacroAssembler::resolve_for_write(DecoratorSet decorators, Register obj) { 6288 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 6289 return bs->resolve_for_write(this, decorators, obj); 6290 } 6291 6292 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 6293 Register thread_tmp, DecoratorSet decorators) { 6294 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 6295 } 6296 6297 // Doesn't do verfication, generates fixed size code 6298 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 6299 Register thread_tmp, DecoratorSet decorators) { 6300 access_load_at(T_OBJECT, IN_HEAP | OOP_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); 6301 } 6302 6303 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1, 6304 Register tmp2, DecoratorSet decorators) { 6305 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2); 6306 } 6307 6308 // Used for storing NULLs. 6309 void MacroAssembler::store_heap_oop_null(Address dst) { 6310 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg); 6311 } 6312 6313 #ifdef _LP64 6314 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6315 if (UseCompressedClassPointers) { 6316 // Store to klass gap in destination 6317 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6318 } 6319 } 6320 6321 #ifdef ASSERT 6322 void MacroAssembler::verify_heapbase(const char* msg) { 6323 assert (UseCompressedOops, "should be compressed"); 6324 assert (Universe::heap() != NULL, "java heap should be initialized"); 6325 if (CheckCompressedOops) { 6326 Label ok; 6327 push(rscratch1); // cmpptr trashes rscratch1 6328 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6329 jcc(Assembler::equal, ok); 6330 STOP(msg); 6331 bind(ok); 6332 pop(rscratch1); 6333 } 6334 } 6335 #endif 6336 6337 // Algorithm must match oop.inline.hpp encode_heap_oop. 6338 void MacroAssembler::encode_heap_oop(Register r) { 6339 #ifdef ASSERT 6340 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6341 #endif 6342 verify_oop(r, "broken oop in encode_heap_oop"); 6343 if (Universe::narrow_oop_base() == NULL) { 6344 if (Universe::narrow_oop_shift() != 0) { 6345 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6346 shrq(r, LogMinObjAlignmentInBytes); 6347 } 6348 return; 6349 } 6350 testq(r, r); 6351 cmovq(Assembler::equal, r, r12_heapbase); 6352 subq(r, r12_heapbase); 6353 shrq(r, LogMinObjAlignmentInBytes); 6354 } 6355 6356 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6357 #ifdef ASSERT 6358 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6359 if (CheckCompressedOops) { 6360 Label ok; 6361 testq(r, r); 6362 jcc(Assembler::notEqual, ok); 6363 STOP("null oop passed to encode_heap_oop_not_null"); 6364 bind(ok); 6365 } 6366 #endif 6367 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6368 if (Universe::narrow_oop_base() != NULL) { 6369 subq(r, r12_heapbase); 6370 } 6371 if (Universe::narrow_oop_shift() != 0) { 6372 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6373 shrq(r, LogMinObjAlignmentInBytes); 6374 } 6375 } 6376 6377 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6378 #ifdef ASSERT 6379 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6380 if (CheckCompressedOops) { 6381 Label ok; 6382 testq(src, src); 6383 jcc(Assembler::notEqual, ok); 6384 STOP("null oop passed to encode_heap_oop_not_null2"); 6385 bind(ok); 6386 } 6387 #endif 6388 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6389 if (dst != src) { 6390 movq(dst, src); 6391 } 6392 if (Universe::narrow_oop_base() != NULL) { 6393 subq(dst, r12_heapbase); 6394 } 6395 if (Universe::narrow_oop_shift() != 0) { 6396 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6397 shrq(dst, LogMinObjAlignmentInBytes); 6398 } 6399 } 6400 6401 void MacroAssembler::decode_heap_oop(Register r) { 6402 #ifdef ASSERT 6403 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6404 #endif 6405 if (Universe::narrow_oop_base() == NULL) { 6406 if (Universe::narrow_oop_shift() != 0) { 6407 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6408 shlq(r, LogMinObjAlignmentInBytes); 6409 } 6410 } else { 6411 Label done; 6412 shlq(r, LogMinObjAlignmentInBytes); 6413 jccb(Assembler::equal, done); 6414 addq(r, r12_heapbase); 6415 bind(done); 6416 } 6417 verify_oop(r, "broken oop in decode_heap_oop"); 6418 } 6419 6420 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6421 // Note: it will change flags 6422 assert (UseCompressedOops, "should only be used for compressed headers"); 6423 assert (Universe::heap() != NULL, "java heap should be initialized"); 6424 // Cannot assert, unverified entry point counts instructions (see .ad file) 6425 // vtableStubs also counts instructions in pd_code_size_limit. 6426 // Also do not verify_oop as this is called by verify_oop. 6427 if (Universe::narrow_oop_shift() != 0) { 6428 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6429 shlq(r, LogMinObjAlignmentInBytes); 6430 if (Universe::narrow_oop_base() != NULL) { 6431 addq(r, r12_heapbase); 6432 } 6433 } else { 6434 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6435 } 6436 } 6437 6438 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6439 // Note: it will change flags 6440 assert (UseCompressedOops, "should only be used for compressed headers"); 6441 assert (Universe::heap() != NULL, "java heap should be initialized"); 6442 // Cannot assert, unverified entry point counts instructions (see .ad file) 6443 // vtableStubs also counts instructions in pd_code_size_limit. 6444 // Also do not verify_oop as this is called by verify_oop. 6445 if (Universe::narrow_oop_shift() != 0) { 6446 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6447 if (LogMinObjAlignmentInBytes == Address::times_8) { 6448 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6449 } else { 6450 if (dst != src) { 6451 movq(dst, src); 6452 } 6453 shlq(dst, LogMinObjAlignmentInBytes); 6454 if (Universe::narrow_oop_base() != NULL) { 6455 addq(dst, r12_heapbase); 6456 } 6457 } 6458 } else { 6459 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6460 if (dst != src) { 6461 movq(dst, src); 6462 } 6463 } 6464 } 6465 6466 void MacroAssembler::encode_klass_not_null(Register r) { 6467 if (Universe::narrow_klass_base() != NULL) { 6468 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6469 assert(r != r12_heapbase, "Encoding a klass in r12"); 6470 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6471 subq(r, r12_heapbase); 6472 } 6473 if (Universe::narrow_klass_shift() != 0) { 6474 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6475 shrq(r, LogKlassAlignmentInBytes); 6476 } 6477 if (Universe::narrow_klass_base() != NULL) { 6478 reinit_heapbase(); 6479 } 6480 } 6481 6482 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6483 if (dst == src) { 6484 encode_klass_not_null(src); 6485 } else { 6486 if (Universe::narrow_klass_base() != NULL) { 6487 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6488 negq(dst); 6489 addq(dst, src); 6490 } else { 6491 movptr(dst, src); 6492 } 6493 if (Universe::narrow_klass_shift() != 0) { 6494 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6495 shrq(dst, LogKlassAlignmentInBytes); 6496 } 6497 } 6498 } 6499 6500 // Function instr_size_for_decode_klass_not_null() counts the instructions 6501 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6502 // when (Universe::heap() != NULL). Hence, if the instructions they 6503 // generate change, then this method needs to be updated. 6504 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6505 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6506 if (Universe::narrow_klass_base() != NULL) { 6507 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6508 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6509 } else { 6510 // longest load decode klass function, mov64, leaq 6511 return 16; 6512 } 6513 } 6514 6515 // !!! If the instructions that get generated here change then function 6516 // instr_size_for_decode_klass_not_null() needs to get updated. 6517 void MacroAssembler::decode_klass_not_null(Register r) { 6518 // Note: it will change flags 6519 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6520 assert(r != r12_heapbase, "Decoding a klass in r12"); 6521 // Cannot assert, unverified entry point counts instructions (see .ad file) 6522 // vtableStubs also counts instructions in pd_code_size_limit. 6523 // Also do not verify_oop as this is called by verify_oop. 6524 if (Universe::narrow_klass_shift() != 0) { 6525 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6526 shlq(r, LogKlassAlignmentInBytes); 6527 } 6528 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6529 if (Universe::narrow_klass_base() != NULL) { 6530 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6531 addq(r, r12_heapbase); 6532 reinit_heapbase(); 6533 } 6534 } 6535 6536 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6537 // Note: it will change flags 6538 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6539 if (dst == src) { 6540 decode_klass_not_null(dst); 6541 } else { 6542 // Cannot assert, unverified entry point counts instructions (see .ad file) 6543 // vtableStubs also counts instructions in pd_code_size_limit. 6544 // Also do not verify_oop as this is called by verify_oop. 6545 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6546 if (Universe::narrow_klass_shift() != 0) { 6547 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6548 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6549 leaq(dst, Address(dst, src, Address::times_8, 0)); 6550 } else { 6551 addq(dst, src); 6552 } 6553 } 6554 } 6555 6556 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6557 assert (UseCompressedOops, "should only be used for compressed headers"); 6558 assert (Universe::heap() != NULL, "java heap should be initialized"); 6559 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6560 int oop_index = oop_recorder()->find_index(obj); 6561 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6562 mov_narrow_oop(dst, oop_index, rspec); 6563 } 6564 6565 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6566 assert (UseCompressedOops, "should only be used for compressed headers"); 6567 assert (Universe::heap() != NULL, "java heap should be initialized"); 6568 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6569 int oop_index = oop_recorder()->find_index(obj); 6570 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6571 mov_narrow_oop(dst, oop_index, rspec); 6572 } 6573 6574 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6575 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6576 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6577 int klass_index = oop_recorder()->find_index(k); 6578 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6579 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6580 } 6581 6582 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6583 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6584 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6585 int klass_index = oop_recorder()->find_index(k); 6586 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6587 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6588 } 6589 6590 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6591 assert (UseCompressedOops, "should only be used for compressed headers"); 6592 assert (Universe::heap() != NULL, "java heap should be initialized"); 6593 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6594 int oop_index = oop_recorder()->find_index(obj); 6595 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6596 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6597 } 6598 6599 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6600 assert (UseCompressedOops, "should only be used for compressed headers"); 6601 assert (Universe::heap() != NULL, "java heap should be initialized"); 6602 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6603 int oop_index = oop_recorder()->find_index(obj); 6604 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6605 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6606 } 6607 6608 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6609 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6610 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6611 int klass_index = oop_recorder()->find_index(k); 6612 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6613 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6614 } 6615 6616 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6617 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6618 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6619 int klass_index = oop_recorder()->find_index(k); 6620 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6621 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6622 } 6623 6624 void MacroAssembler::reinit_heapbase() { 6625 if (UseCompressedOops || UseCompressedClassPointers) { 6626 if (Universe::heap() != NULL) { 6627 if (Universe::narrow_oop_base() == NULL) { 6628 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6629 } else { 6630 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6631 } 6632 } else { 6633 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6634 } 6635 } 6636 } 6637 6638 #endif // _LP64 6639 6640 // C2 compiled method's prolog code. 6641 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6642 6643 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6644 // NativeJump::patch_verified_entry will be able to patch out the entry 6645 // code safely. The push to verify stack depth is ok at 5 bytes, 6646 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6647 // stack bang then we must use the 6 byte frame allocation even if 6648 // we have no frame. :-( 6649 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6650 6651 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6652 // Remove word for return addr 6653 framesize -= wordSize; 6654 stack_bang_size -= wordSize; 6655 6656 // Calls to C2R adapters often do not accept exceptional returns. 6657 // We require that their callers must bang for them. But be careful, because 6658 // some VM calls (such as call site linkage) can use several kilobytes of 6659 // stack. But the stack safety zone should account for that. 6660 // See bugs 4446381, 4468289, 4497237. 6661 if (stack_bang_size > 0) { 6662 generate_stack_overflow_check(stack_bang_size); 6663 6664 // We always push rbp, so that on return to interpreter rbp, will be 6665 // restored correctly and we can correct the stack. 6666 push(rbp); 6667 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6668 if (PreserveFramePointer) { 6669 mov(rbp, rsp); 6670 } 6671 // Remove word for ebp 6672 framesize -= wordSize; 6673 6674 // Create frame 6675 if (framesize) { 6676 subptr(rsp, framesize); 6677 } 6678 } else { 6679 // Create frame (force generation of a 4 byte immediate value) 6680 subptr_imm32(rsp, framesize); 6681 6682 // Save RBP register now. 6683 framesize -= wordSize; 6684 movptr(Address(rsp, framesize), rbp); 6685 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6686 if (PreserveFramePointer) { 6687 movptr(rbp, rsp); 6688 if (framesize > 0) { 6689 addptr(rbp, framesize); 6690 } 6691 } 6692 } 6693 6694 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6695 framesize -= wordSize; 6696 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6697 } 6698 6699 #ifndef _LP64 6700 // If method sets FPU control word do it now 6701 if (fp_mode_24b) { 6702 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6703 } 6704 if (UseSSE >= 2 && VerifyFPU) { 6705 verify_FPU(0, "FPU stack must be clean on entry"); 6706 } 6707 #endif 6708 6709 #ifdef ASSERT 6710 if (VerifyStackAtCalls) { 6711 Label L; 6712 push(rax); 6713 mov(rax, rsp); 6714 andptr(rax, StackAlignmentInBytes-1); 6715 cmpptr(rax, StackAlignmentInBytes-wordSize); 6716 pop(rax); 6717 jcc(Assembler::equal, L); 6718 STOP("Stack is not properly aligned!"); 6719 bind(L); 6720 } 6721 #endif 6722 6723 } 6724 6725 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers 6726 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) { 6727 // cnt - number of qwords (8-byte words). 6728 // base - start address, qword aligned. 6729 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end; 6730 if (UseAVX >= 2) { 6731 vpxor(xtmp, xtmp, xtmp, AVX_256bit); 6732 } else { 6733 pxor(xtmp, xtmp); 6734 } 6735 jmp(L_zero_64_bytes); 6736 6737 BIND(L_loop); 6738 if (UseAVX >= 2) { 6739 vmovdqu(Address(base, 0), xtmp); 6740 vmovdqu(Address(base, 32), xtmp); 6741 } else { 6742 movdqu(Address(base, 0), xtmp); 6743 movdqu(Address(base, 16), xtmp); 6744 movdqu(Address(base, 32), xtmp); 6745 movdqu(Address(base, 48), xtmp); 6746 } 6747 addptr(base, 64); 6748 6749 BIND(L_zero_64_bytes); 6750 subptr(cnt, 8); 6751 jccb(Assembler::greaterEqual, L_loop); 6752 addptr(cnt, 4); 6753 jccb(Assembler::less, L_tail); 6754 // Copy trailing 32 bytes 6755 if (UseAVX >= 2) { 6756 vmovdqu(Address(base, 0), xtmp); 6757 } else { 6758 movdqu(Address(base, 0), xtmp); 6759 movdqu(Address(base, 16), xtmp); 6760 } 6761 addptr(base, 32); 6762 subptr(cnt, 4); 6763 6764 BIND(L_tail); 6765 addptr(cnt, 4); 6766 jccb(Assembler::lessEqual, L_end); 6767 decrement(cnt); 6768 6769 BIND(L_sloop); 6770 movq(Address(base, 0), xtmp); 6771 addptr(base, 8); 6772 decrement(cnt); 6773 jccb(Assembler::greaterEqual, L_sloop); 6774 BIND(L_end); 6775 } 6776 6777 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) { 6778 // cnt - number of qwords (8-byte words). 6779 // base - start address, qword aligned. 6780 // is_large - if optimizers know cnt is larger than InitArrayShortSize 6781 assert(base==rdi, "base register must be edi for rep stos"); 6782 assert(tmp==rax, "tmp register must be eax for rep stos"); 6783 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 6784 assert(InitArrayShortSize % BytesPerLong == 0, 6785 "InitArrayShortSize should be the multiple of BytesPerLong"); 6786 6787 Label DONE; 6788 6789 if (!is_large || !UseXMMForObjInit) { 6790 xorptr(tmp, tmp); 6791 } 6792 6793 if (!is_large) { 6794 Label LOOP, LONG; 6795 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 6796 jccb(Assembler::greater, LONG); 6797 6798 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 6799 6800 decrement(cnt); 6801 jccb(Assembler::negative, DONE); // Zero length 6802 6803 // Use individual pointer-sized stores for small counts: 6804 BIND(LOOP); 6805 movptr(Address(base, cnt, Address::times_ptr), tmp); 6806 decrement(cnt); 6807 jccb(Assembler::greaterEqual, LOOP); 6808 jmpb(DONE); 6809 6810 BIND(LONG); 6811 } 6812 6813 // Use longer rep-prefixed ops for non-small counts: 6814 if (UseFastStosb) { 6815 shlptr(cnt, 3); // convert to number of bytes 6816 rep_stosb(); 6817 } else if (UseXMMForObjInit) { 6818 movptr(tmp, base); 6819 xmm_clear_mem(tmp, cnt, xtmp); 6820 } else { 6821 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 6822 rep_stos(); 6823 } 6824 6825 BIND(DONE); 6826 } 6827 6828 #ifdef COMPILER2 6829 6830 // IndexOf for constant substrings with size >= 8 chars 6831 // which don't need to be loaded through stack. 6832 void MacroAssembler::string_indexofC8(Register str1, Register str2, 6833 Register cnt1, Register cnt2, 6834 int int_cnt2, Register result, 6835 XMMRegister vec, Register tmp, 6836 int ae) { 6837 ShortBranchVerifier sbv(this); 6838 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 6839 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 6840 6841 // This method uses the pcmpestri instruction with bound registers 6842 // inputs: 6843 // xmm - substring 6844 // rax - substring length (elements count) 6845 // mem - scanned string 6846 // rdx - string length (elements count) 6847 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6848 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 6849 // outputs: 6850 // rcx - matched index in string 6851 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6852 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 6853 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 6854 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 6855 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 6856 6857 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 6858 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 6859 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 6860 6861 // Note, inline_string_indexOf() generates checks: 6862 // if (substr.count > string.count) return -1; 6863 // if (substr.count == 0) return 0; 6864 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 6865 6866 // Load substring. 6867 if (ae == StrIntrinsicNode::UL) { 6868 pmovzxbw(vec, Address(str2, 0)); 6869 } else { 6870 movdqu(vec, Address(str2, 0)); 6871 } 6872 movl(cnt2, int_cnt2); 6873 movptr(result, str1); // string addr 6874 6875 if (int_cnt2 > stride) { 6876 jmpb(SCAN_TO_SUBSTR); 6877 6878 // Reload substr for rescan, this code 6879 // is executed only for large substrings (> 8 chars) 6880 bind(RELOAD_SUBSTR); 6881 if (ae == StrIntrinsicNode::UL) { 6882 pmovzxbw(vec, Address(str2, 0)); 6883 } else { 6884 movdqu(vec, Address(str2, 0)); 6885 } 6886 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 6887 6888 bind(RELOAD_STR); 6889 // We came here after the beginning of the substring was 6890 // matched but the rest of it was not so we need to search 6891 // again. Start from the next element after the previous match. 6892 6893 // cnt2 is number of substring reminding elements and 6894 // cnt1 is number of string reminding elements when cmp failed. 6895 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 6896 subl(cnt1, cnt2); 6897 addl(cnt1, int_cnt2); 6898 movl(cnt2, int_cnt2); // Now restore cnt2 6899 6900 decrementl(cnt1); // Shift to next element 6901 cmpl(cnt1, cnt2); 6902 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6903 6904 addptr(result, (1<<scale1)); 6905 6906 } // (int_cnt2 > 8) 6907 6908 // Scan string for start of substr in 16-byte vectors 6909 bind(SCAN_TO_SUBSTR); 6910 pcmpestri(vec, Address(result, 0), mode); 6911 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6912 subl(cnt1, stride); 6913 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6914 cmpl(cnt1, cnt2); 6915 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6916 addptr(result, 16); 6917 jmpb(SCAN_TO_SUBSTR); 6918 6919 // Found a potential substr 6920 bind(FOUND_CANDIDATE); 6921 // Matched whole vector if first element matched (tmp(rcx) == 0). 6922 if (int_cnt2 == stride) { 6923 jccb(Assembler::overflow, RET_FOUND); // OF == 1 6924 } else { // int_cnt2 > 8 6925 jccb(Assembler::overflow, FOUND_SUBSTR); 6926 } 6927 // After pcmpestri tmp(rcx) contains matched element index 6928 // Compute start addr of substr 6929 lea(result, Address(result, tmp, scale1)); 6930 6931 // Make sure string is still long enough 6932 subl(cnt1, tmp); 6933 cmpl(cnt1, cnt2); 6934 if (int_cnt2 == stride) { 6935 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6936 } else { // int_cnt2 > 8 6937 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 6938 } 6939 // Left less then substring. 6940 6941 bind(RET_NOT_FOUND); 6942 movl(result, -1); 6943 jmp(EXIT); 6944 6945 if (int_cnt2 > stride) { 6946 // This code is optimized for the case when whole substring 6947 // is matched if its head is matched. 6948 bind(MATCH_SUBSTR_HEAD); 6949 pcmpestri(vec, Address(result, 0), mode); 6950 // Reload only string if does not match 6951 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 6952 6953 Label CONT_SCAN_SUBSTR; 6954 // Compare the rest of substring (> 8 chars). 6955 bind(FOUND_SUBSTR); 6956 // First 8 chars are already matched. 6957 negptr(cnt2); 6958 addptr(cnt2, stride); 6959 6960 bind(SCAN_SUBSTR); 6961 subl(cnt1, stride); 6962 cmpl(cnt2, -stride); // Do not read beyond substring 6963 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 6964 // Back-up strings to avoid reading beyond substring: 6965 // cnt1 = cnt1 - cnt2 + 8 6966 addl(cnt1, cnt2); // cnt2 is negative 6967 addl(cnt1, stride); 6968 movl(cnt2, stride); negptr(cnt2); 6969 bind(CONT_SCAN_SUBSTR); 6970 if (int_cnt2 < (int)G) { 6971 int tail_off1 = int_cnt2<<scale1; 6972 int tail_off2 = int_cnt2<<scale2; 6973 if (ae == StrIntrinsicNode::UL) { 6974 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 6975 } else { 6976 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 6977 } 6978 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 6979 } else { 6980 // calculate index in register to avoid integer overflow (int_cnt2*2) 6981 movl(tmp, int_cnt2); 6982 addptr(tmp, cnt2); 6983 if (ae == StrIntrinsicNode::UL) { 6984 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 6985 } else { 6986 movdqu(vec, Address(str2, tmp, scale2, 0)); 6987 } 6988 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 6989 } 6990 // Need to reload strings pointers if not matched whole vector 6991 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6992 addptr(cnt2, stride); 6993 jcc(Assembler::negative, SCAN_SUBSTR); 6994 // Fall through if found full substring 6995 6996 } // (int_cnt2 > 8) 6997 6998 bind(RET_FOUND); 6999 // Found result if we matched full small substring. 7000 // Compute substr offset 7001 subptr(result, str1); 7002 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7003 shrl(result, 1); // index 7004 } 7005 bind(EXIT); 7006 7007 } // string_indexofC8 7008 7009 // Small strings are loaded through stack if they cross page boundary. 7010 void MacroAssembler::string_indexof(Register str1, Register str2, 7011 Register cnt1, Register cnt2, 7012 int int_cnt2, Register result, 7013 XMMRegister vec, Register tmp, 7014 int ae) { 7015 ShortBranchVerifier sbv(this); 7016 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7017 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7018 7019 // 7020 // int_cnt2 is length of small (< 8 chars) constant substring 7021 // or (-1) for non constant substring in which case its length 7022 // is in cnt2 register. 7023 // 7024 // Note, inline_string_indexOf() generates checks: 7025 // if (substr.count > string.count) return -1; 7026 // if (substr.count == 0) return 0; 7027 // 7028 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7029 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7030 // This method uses the pcmpestri instruction with bound registers 7031 // inputs: 7032 // xmm - substring 7033 // rax - substring length (elements count) 7034 // mem - scanned string 7035 // rdx - string length (elements count) 7036 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7037 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7038 // outputs: 7039 // rcx - matched index in string 7040 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7041 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7042 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7043 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7044 7045 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7046 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7047 FOUND_CANDIDATE; 7048 7049 { //======================================================== 7050 // We don't know where these strings are located 7051 // and we can't read beyond them. Load them through stack. 7052 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7053 7054 movptr(tmp, rsp); // save old SP 7055 7056 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7057 if (int_cnt2 == (1>>scale2)) { // One byte 7058 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7059 load_unsigned_byte(result, Address(str2, 0)); 7060 movdl(vec, result); // move 32 bits 7061 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7062 // Not enough header space in 32-bit VM: 12+3 = 15. 7063 movl(result, Address(str2, -1)); 7064 shrl(result, 8); 7065 movdl(vec, result); // move 32 bits 7066 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7067 load_unsigned_short(result, Address(str2, 0)); 7068 movdl(vec, result); // move 32 bits 7069 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7070 movdl(vec, Address(str2, 0)); // move 32 bits 7071 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7072 movq(vec, Address(str2, 0)); // move 64 bits 7073 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7074 // Array header size is 12 bytes in 32-bit VM 7075 // + 6 bytes for 3 chars == 18 bytes, 7076 // enough space to load vec and shift. 7077 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7078 if (ae == StrIntrinsicNode::UL) { 7079 int tail_off = int_cnt2-8; 7080 pmovzxbw(vec, Address(str2, tail_off)); 7081 psrldq(vec, -2*tail_off); 7082 } 7083 else { 7084 int tail_off = int_cnt2*(1<<scale2); 7085 movdqu(vec, Address(str2, tail_off-16)); 7086 psrldq(vec, 16-tail_off); 7087 } 7088 } 7089 } else { // not constant substring 7090 cmpl(cnt2, stride); 7091 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7092 7093 // We can read beyond string if srt+16 does not cross page boundary 7094 // since heaps are aligned and mapped by pages. 7095 assert(os::vm_page_size() < (int)G, "default page should be small"); 7096 movl(result, str2); // We need only low 32 bits 7097 andl(result, (os::vm_page_size()-1)); 7098 cmpl(result, (os::vm_page_size()-16)); 7099 jccb(Assembler::belowEqual, CHECK_STR); 7100 7101 // Move small strings to stack to allow load 16 bytes into vec. 7102 subptr(rsp, 16); 7103 int stk_offset = wordSize-(1<<scale2); 7104 push(cnt2); 7105 7106 bind(COPY_SUBSTR); 7107 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7108 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7109 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7110 } else if (ae == StrIntrinsicNode::UU) { 7111 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7112 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7113 } 7114 decrement(cnt2); 7115 jccb(Assembler::notZero, COPY_SUBSTR); 7116 7117 pop(cnt2); 7118 movptr(str2, rsp); // New substring address 7119 } // non constant 7120 7121 bind(CHECK_STR); 7122 cmpl(cnt1, stride); 7123 jccb(Assembler::aboveEqual, BIG_STRINGS); 7124 7125 // Check cross page boundary. 7126 movl(result, str1); // We need only low 32 bits 7127 andl(result, (os::vm_page_size()-1)); 7128 cmpl(result, (os::vm_page_size()-16)); 7129 jccb(Assembler::belowEqual, BIG_STRINGS); 7130 7131 subptr(rsp, 16); 7132 int stk_offset = -(1<<scale1); 7133 if (int_cnt2 < 0) { // not constant 7134 push(cnt2); 7135 stk_offset += wordSize; 7136 } 7137 movl(cnt2, cnt1); 7138 7139 bind(COPY_STR); 7140 if (ae == StrIntrinsicNode::LL) { 7141 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7142 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7143 } else { 7144 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7145 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7146 } 7147 decrement(cnt2); 7148 jccb(Assembler::notZero, COPY_STR); 7149 7150 if (int_cnt2 < 0) { // not constant 7151 pop(cnt2); 7152 } 7153 movptr(str1, rsp); // New string address 7154 7155 bind(BIG_STRINGS); 7156 // Load substring. 7157 if (int_cnt2 < 0) { // -1 7158 if (ae == StrIntrinsicNode::UL) { 7159 pmovzxbw(vec, Address(str2, 0)); 7160 } else { 7161 movdqu(vec, Address(str2, 0)); 7162 } 7163 push(cnt2); // substr count 7164 push(str2); // substr addr 7165 push(str1); // string addr 7166 } else { 7167 // Small (< 8 chars) constant substrings are loaded already. 7168 movl(cnt2, int_cnt2); 7169 } 7170 push(tmp); // original SP 7171 7172 } // Finished loading 7173 7174 //======================================================== 7175 // Start search 7176 // 7177 7178 movptr(result, str1); // string addr 7179 7180 if (int_cnt2 < 0) { // Only for non constant substring 7181 jmpb(SCAN_TO_SUBSTR); 7182 7183 // SP saved at sp+0 7184 // String saved at sp+1*wordSize 7185 // Substr saved at sp+2*wordSize 7186 // Substr count saved at sp+3*wordSize 7187 7188 // Reload substr for rescan, this code 7189 // is executed only for large substrings (> 8 chars) 7190 bind(RELOAD_SUBSTR); 7191 movptr(str2, Address(rsp, 2*wordSize)); 7192 movl(cnt2, Address(rsp, 3*wordSize)); 7193 if (ae == StrIntrinsicNode::UL) { 7194 pmovzxbw(vec, Address(str2, 0)); 7195 } else { 7196 movdqu(vec, Address(str2, 0)); 7197 } 7198 // We came here after the beginning of the substring was 7199 // matched but the rest of it was not so we need to search 7200 // again. Start from the next element after the previous match. 7201 subptr(str1, result); // Restore counter 7202 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7203 shrl(str1, 1); 7204 } 7205 addl(cnt1, str1); 7206 decrementl(cnt1); // Shift to next element 7207 cmpl(cnt1, cnt2); 7208 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7209 7210 addptr(result, (1<<scale1)); 7211 } // non constant 7212 7213 // Scan string for start of substr in 16-byte vectors 7214 bind(SCAN_TO_SUBSTR); 7215 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7216 pcmpestri(vec, Address(result, 0), mode); 7217 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7218 subl(cnt1, stride); 7219 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7220 cmpl(cnt1, cnt2); 7221 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7222 addptr(result, 16); 7223 7224 bind(ADJUST_STR); 7225 cmpl(cnt1, stride); // Do not read beyond string 7226 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7227 // Back-up string to avoid reading beyond string. 7228 lea(result, Address(result, cnt1, scale1, -16)); 7229 movl(cnt1, stride); 7230 jmpb(SCAN_TO_SUBSTR); 7231 7232 // Found a potential substr 7233 bind(FOUND_CANDIDATE); 7234 // After pcmpestri tmp(rcx) contains matched element index 7235 7236 // Make sure string is still long enough 7237 subl(cnt1, tmp); 7238 cmpl(cnt1, cnt2); 7239 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7240 // Left less then substring. 7241 7242 bind(RET_NOT_FOUND); 7243 movl(result, -1); 7244 jmpb(CLEANUP); 7245 7246 bind(FOUND_SUBSTR); 7247 // Compute start addr of substr 7248 lea(result, Address(result, tmp, scale1)); 7249 if (int_cnt2 > 0) { // Constant substring 7250 // Repeat search for small substring (< 8 chars) 7251 // from new point without reloading substring. 7252 // Have to check that we don't read beyond string. 7253 cmpl(tmp, stride-int_cnt2); 7254 jccb(Assembler::greater, ADJUST_STR); 7255 // Fall through if matched whole substring. 7256 } else { // non constant 7257 assert(int_cnt2 == -1, "should be != 0"); 7258 7259 addl(tmp, cnt2); 7260 // Found result if we matched whole substring. 7261 cmpl(tmp, stride); 7262 jccb(Assembler::lessEqual, RET_FOUND); 7263 7264 // Repeat search for small substring (<= 8 chars) 7265 // from new point 'str1' without reloading substring. 7266 cmpl(cnt2, stride); 7267 // Have to check that we don't read beyond string. 7268 jccb(Assembler::lessEqual, ADJUST_STR); 7269 7270 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7271 // Compare the rest of substring (> 8 chars). 7272 movptr(str1, result); 7273 7274 cmpl(tmp, cnt2); 7275 // First 8 chars are already matched. 7276 jccb(Assembler::equal, CHECK_NEXT); 7277 7278 bind(SCAN_SUBSTR); 7279 pcmpestri(vec, Address(str1, 0), mode); 7280 // Need to reload strings pointers if not matched whole vector 7281 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7282 7283 bind(CHECK_NEXT); 7284 subl(cnt2, stride); 7285 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7286 addptr(str1, 16); 7287 if (ae == StrIntrinsicNode::UL) { 7288 addptr(str2, 8); 7289 } else { 7290 addptr(str2, 16); 7291 } 7292 subl(cnt1, stride); 7293 cmpl(cnt2, stride); // Do not read beyond substring 7294 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7295 // Back-up strings to avoid reading beyond substring. 7296 7297 if (ae == StrIntrinsicNode::UL) { 7298 lea(str2, Address(str2, cnt2, scale2, -8)); 7299 lea(str1, Address(str1, cnt2, scale1, -16)); 7300 } else { 7301 lea(str2, Address(str2, cnt2, scale2, -16)); 7302 lea(str1, Address(str1, cnt2, scale1, -16)); 7303 } 7304 subl(cnt1, cnt2); 7305 movl(cnt2, stride); 7306 addl(cnt1, stride); 7307 bind(CONT_SCAN_SUBSTR); 7308 if (ae == StrIntrinsicNode::UL) { 7309 pmovzxbw(vec, Address(str2, 0)); 7310 } else { 7311 movdqu(vec, Address(str2, 0)); 7312 } 7313 jmp(SCAN_SUBSTR); 7314 7315 bind(RET_FOUND_LONG); 7316 movptr(str1, Address(rsp, wordSize)); 7317 } // non constant 7318 7319 bind(RET_FOUND); 7320 // Compute substr offset 7321 subptr(result, str1); 7322 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7323 shrl(result, 1); // index 7324 } 7325 bind(CLEANUP); 7326 pop(rsp); // restore SP 7327 7328 } // string_indexof 7329 7330 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7331 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7332 ShortBranchVerifier sbv(this); 7333 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7334 7335 int stride = 8; 7336 7337 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7338 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7339 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7340 FOUND_SEQ_CHAR, DONE_LABEL; 7341 7342 movptr(result, str1); 7343 if (UseAVX >= 2) { 7344 cmpl(cnt1, stride); 7345 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7346 cmpl(cnt1, 2*stride); 7347 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7348 movdl(vec1, ch); 7349 vpbroadcastw(vec1, vec1); 7350 vpxor(vec2, vec2); 7351 movl(tmp, cnt1); 7352 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7353 andl(cnt1,0x0000000F); //tail count (in chars) 7354 7355 bind(SCAN_TO_16_CHAR_LOOP); 7356 vmovdqu(vec3, Address(result, 0)); 7357 vpcmpeqw(vec3, vec3, vec1, 1); 7358 vptest(vec2, vec3); 7359 jcc(Assembler::carryClear, FOUND_CHAR); 7360 addptr(result, 32); 7361 subl(tmp, 2*stride); 7362 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7363 jmp(SCAN_TO_8_CHAR); 7364 bind(SCAN_TO_8_CHAR_INIT); 7365 movdl(vec1, ch); 7366 pshuflw(vec1, vec1, 0x00); 7367 pshufd(vec1, vec1, 0); 7368 pxor(vec2, vec2); 7369 } 7370 bind(SCAN_TO_8_CHAR); 7371 cmpl(cnt1, stride); 7372 if (UseAVX >= 2) { 7373 jcc(Assembler::less, SCAN_TO_CHAR); 7374 } else { 7375 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7376 movdl(vec1, ch); 7377 pshuflw(vec1, vec1, 0x00); 7378 pshufd(vec1, vec1, 0); 7379 pxor(vec2, vec2); 7380 } 7381 movl(tmp, cnt1); 7382 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7383 andl(cnt1,0x00000007); //tail count (in chars) 7384 7385 bind(SCAN_TO_8_CHAR_LOOP); 7386 movdqu(vec3, Address(result, 0)); 7387 pcmpeqw(vec3, vec1); 7388 ptest(vec2, vec3); 7389 jcc(Assembler::carryClear, FOUND_CHAR); 7390 addptr(result, 16); 7391 subl(tmp, stride); 7392 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7393 bind(SCAN_TO_CHAR); 7394 testl(cnt1, cnt1); 7395 jcc(Assembler::zero, RET_NOT_FOUND); 7396 bind(SCAN_TO_CHAR_LOOP); 7397 load_unsigned_short(tmp, Address(result, 0)); 7398 cmpl(ch, tmp); 7399 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7400 addptr(result, 2); 7401 subl(cnt1, 1); 7402 jccb(Assembler::zero, RET_NOT_FOUND); 7403 jmp(SCAN_TO_CHAR_LOOP); 7404 7405 bind(RET_NOT_FOUND); 7406 movl(result, -1); 7407 jmpb(DONE_LABEL); 7408 7409 bind(FOUND_CHAR); 7410 if (UseAVX >= 2) { 7411 vpmovmskb(tmp, vec3); 7412 } else { 7413 pmovmskb(tmp, vec3); 7414 } 7415 bsfl(ch, tmp); 7416 addl(result, ch); 7417 7418 bind(FOUND_SEQ_CHAR); 7419 subptr(result, str1); 7420 shrl(result, 1); 7421 7422 bind(DONE_LABEL); 7423 } // string_indexof_char 7424 7425 // helper function for string_compare 7426 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7427 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7428 Address::ScaleFactor scale2, Register index, int ae) { 7429 if (ae == StrIntrinsicNode::LL) { 7430 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7431 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7432 } else if (ae == StrIntrinsicNode::UU) { 7433 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7434 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7435 } else { 7436 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7437 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7438 } 7439 } 7440 7441 // Compare strings, used for char[] and byte[]. 7442 void MacroAssembler::string_compare(Register str1, Register str2, 7443 Register cnt1, Register cnt2, Register result, 7444 XMMRegister vec1, int ae) { 7445 ShortBranchVerifier sbv(this); 7446 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7447 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7448 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7449 int stride2x2 = 0x40; 7450 Address::ScaleFactor scale = Address::no_scale; 7451 Address::ScaleFactor scale1 = Address::no_scale; 7452 Address::ScaleFactor scale2 = Address::no_scale; 7453 7454 if (ae != StrIntrinsicNode::LL) { 7455 stride2x2 = 0x20; 7456 } 7457 7458 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7459 shrl(cnt2, 1); 7460 } 7461 // Compute the minimum of the string lengths and the 7462 // difference of the string lengths (stack). 7463 // Do the conditional move stuff 7464 movl(result, cnt1); 7465 subl(cnt1, cnt2); 7466 push(cnt1); 7467 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7468 7469 // Is the minimum length zero? 7470 testl(cnt2, cnt2); 7471 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7472 if (ae == StrIntrinsicNode::LL) { 7473 // Load first bytes 7474 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7475 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7476 } else if (ae == StrIntrinsicNode::UU) { 7477 // Load first characters 7478 load_unsigned_short(result, Address(str1, 0)); 7479 load_unsigned_short(cnt1, Address(str2, 0)); 7480 } else { 7481 load_unsigned_byte(result, Address(str1, 0)); 7482 load_unsigned_short(cnt1, Address(str2, 0)); 7483 } 7484 subl(result, cnt1); 7485 jcc(Assembler::notZero, POP_LABEL); 7486 7487 if (ae == StrIntrinsicNode::UU) { 7488 // Divide length by 2 to get number of chars 7489 shrl(cnt2, 1); 7490 } 7491 cmpl(cnt2, 1); 7492 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7493 7494 // Check if the strings start at the same location and setup scale and stride 7495 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7496 cmpptr(str1, str2); 7497 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7498 if (ae == StrIntrinsicNode::LL) { 7499 scale = Address::times_1; 7500 stride = 16; 7501 } else { 7502 scale = Address::times_2; 7503 stride = 8; 7504 } 7505 } else { 7506 scale1 = Address::times_1; 7507 scale2 = Address::times_2; 7508 // scale not used 7509 stride = 8; 7510 } 7511 7512 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7513 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7514 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7515 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7516 Label COMPARE_TAIL_LONG; 7517 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7518 7519 int pcmpmask = 0x19; 7520 if (ae == StrIntrinsicNode::LL) { 7521 pcmpmask &= ~0x01; 7522 } 7523 7524 // Setup to compare 16-chars (32-bytes) vectors, 7525 // start from first character again because it has aligned address. 7526 if (ae == StrIntrinsicNode::LL) { 7527 stride2 = 32; 7528 } else { 7529 stride2 = 16; 7530 } 7531 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7532 adr_stride = stride << scale; 7533 } else { 7534 adr_stride1 = 8; //stride << scale1; 7535 adr_stride2 = 16; //stride << scale2; 7536 } 7537 7538 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7539 // rax and rdx are used by pcmpestri as elements counters 7540 movl(result, cnt2); 7541 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7542 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7543 7544 // fast path : compare first 2 8-char vectors. 7545 bind(COMPARE_16_CHARS); 7546 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7547 movdqu(vec1, Address(str1, 0)); 7548 } else { 7549 pmovzxbw(vec1, Address(str1, 0)); 7550 } 7551 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7552 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7553 7554 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7555 movdqu(vec1, Address(str1, adr_stride)); 7556 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7557 } else { 7558 pmovzxbw(vec1, Address(str1, adr_stride1)); 7559 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7560 } 7561 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7562 addl(cnt1, stride); 7563 7564 // Compare the characters at index in cnt1 7565 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7566 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7567 subl(result, cnt2); 7568 jmp(POP_LABEL); 7569 7570 // Setup the registers to start vector comparison loop 7571 bind(COMPARE_WIDE_VECTORS); 7572 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7573 lea(str1, Address(str1, result, scale)); 7574 lea(str2, Address(str2, result, scale)); 7575 } else { 7576 lea(str1, Address(str1, result, scale1)); 7577 lea(str2, Address(str2, result, scale2)); 7578 } 7579 subl(result, stride2); 7580 subl(cnt2, stride2); 7581 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7582 negptr(result); 7583 7584 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7585 bind(COMPARE_WIDE_VECTORS_LOOP); 7586 7587 #ifdef _LP64 7588 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7589 cmpl(cnt2, stride2x2); 7590 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7591 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7592 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7593 7594 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7595 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7596 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7597 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7598 } else { 7599 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7600 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7601 } 7602 kortestql(k7, k7); 7603 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7604 addptr(result, stride2x2); // update since we already compared at this addr 7605 subl(cnt2, stride2x2); // and sub the size too 7606 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7607 7608 vpxor(vec1, vec1); 7609 jmpb(COMPARE_WIDE_TAIL); 7610 }//if (VM_Version::supports_avx512vlbw()) 7611 #endif // _LP64 7612 7613 7614 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7615 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7616 vmovdqu(vec1, Address(str1, result, scale)); 7617 vpxor(vec1, Address(str2, result, scale)); 7618 } else { 7619 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7620 vpxor(vec1, Address(str2, result, scale2)); 7621 } 7622 vptest(vec1, vec1); 7623 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7624 addptr(result, stride2); 7625 subl(cnt2, stride2); 7626 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7627 // clean upper bits of YMM registers 7628 vpxor(vec1, vec1); 7629 7630 // compare wide vectors tail 7631 bind(COMPARE_WIDE_TAIL); 7632 testptr(result, result); 7633 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7634 7635 movl(result, stride2); 7636 movl(cnt2, result); 7637 negptr(result); 7638 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7639 7640 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 7641 bind(VECTOR_NOT_EQUAL); 7642 // clean upper bits of YMM registers 7643 vpxor(vec1, vec1); 7644 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7645 lea(str1, Address(str1, result, scale)); 7646 lea(str2, Address(str2, result, scale)); 7647 } else { 7648 lea(str1, Address(str1, result, scale1)); 7649 lea(str2, Address(str2, result, scale2)); 7650 } 7651 jmp(COMPARE_16_CHARS); 7652 7653 // Compare tail chars, length between 1 to 15 chars 7654 bind(COMPARE_TAIL_LONG); 7655 movl(cnt2, result); 7656 cmpl(cnt2, stride); 7657 jcc(Assembler::less, COMPARE_SMALL_STR); 7658 7659 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7660 movdqu(vec1, Address(str1, 0)); 7661 } else { 7662 pmovzxbw(vec1, Address(str1, 0)); 7663 } 7664 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7665 jcc(Assembler::below, COMPARE_INDEX_CHAR); 7666 subptr(cnt2, stride); 7667 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7668 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7669 lea(str1, Address(str1, result, scale)); 7670 lea(str2, Address(str2, result, scale)); 7671 } else { 7672 lea(str1, Address(str1, result, scale1)); 7673 lea(str2, Address(str2, result, scale2)); 7674 } 7675 negptr(cnt2); 7676 jmpb(WHILE_HEAD_LABEL); 7677 7678 bind(COMPARE_SMALL_STR); 7679 } else if (UseSSE42Intrinsics) { 7680 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 7681 int pcmpmask = 0x19; 7682 // Setup to compare 8-char (16-byte) vectors, 7683 // start from first character again because it has aligned address. 7684 movl(result, cnt2); 7685 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 7686 if (ae == StrIntrinsicNode::LL) { 7687 pcmpmask &= ~0x01; 7688 } 7689 jcc(Assembler::zero, COMPARE_TAIL); 7690 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7691 lea(str1, Address(str1, result, scale)); 7692 lea(str2, Address(str2, result, scale)); 7693 } else { 7694 lea(str1, Address(str1, result, scale1)); 7695 lea(str2, Address(str2, result, scale2)); 7696 } 7697 negptr(result); 7698 7699 // pcmpestri 7700 // inputs: 7701 // vec1- substring 7702 // rax - negative string length (elements count) 7703 // mem - scanned string 7704 // rdx - string length (elements count) 7705 // pcmpmask - cmp mode: 11000 (string compare with negated result) 7706 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 7707 // outputs: 7708 // rcx - first mismatched element index 7709 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7710 7711 bind(COMPARE_WIDE_VECTORS); 7712 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7713 movdqu(vec1, Address(str1, result, scale)); 7714 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7715 } else { 7716 pmovzxbw(vec1, Address(str1, result, scale1)); 7717 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7718 } 7719 // After pcmpestri cnt1(rcx) contains mismatched element index 7720 7721 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 7722 addptr(result, stride); 7723 subptr(cnt2, stride); 7724 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 7725 7726 // compare wide vectors tail 7727 testptr(result, result); 7728 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7729 7730 movl(cnt2, stride); 7731 movl(result, stride); 7732 negptr(result); 7733 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7734 movdqu(vec1, Address(str1, result, scale)); 7735 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7736 } else { 7737 pmovzxbw(vec1, Address(str1, result, scale1)); 7738 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7739 } 7740 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 7741 7742 // Mismatched characters in the vectors 7743 bind(VECTOR_NOT_EQUAL); 7744 addptr(cnt1, result); 7745 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7746 subl(result, cnt2); 7747 jmpb(POP_LABEL); 7748 7749 bind(COMPARE_TAIL); // limit is zero 7750 movl(cnt2, result); 7751 // Fallthru to tail compare 7752 } 7753 // Shift str2 and str1 to the end of the arrays, negate min 7754 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7755 lea(str1, Address(str1, cnt2, scale)); 7756 lea(str2, Address(str2, cnt2, scale)); 7757 } else { 7758 lea(str1, Address(str1, cnt2, scale1)); 7759 lea(str2, Address(str2, cnt2, scale2)); 7760 } 7761 decrementl(cnt2); // first character was compared already 7762 negptr(cnt2); 7763 7764 // Compare the rest of the elements 7765 bind(WHILE_HEAD_LABEL); 7766 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 7767 subl(result, cnt1); 7768 jccb(Assembler::notZero, POP_LABEL); 7769 increment(cnt2); 7770 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 7771 7772 // Strings are equal up to min length. Return the length difference. 7773 bind(LENGTH_DIFF_LABEL); 7774 pop(result); 7775 if (ae == StrIntrinsicNode::UU) { 7776 // Divide diff by 2 to get number of chars 7777 sarl(result, 1); 7778 } 7779 jmpb(DONE_LABEL); 7780 7781 #ifdef _LP64 7782 if (VM_Version::supports_avx512vlbw()) { 7783 7784 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 7785 7786 kmovql(cnt1, k7); 7787 notq(cnt1); 7788 bsfq(cnt2, cnt1); 7789 if (ae != StrIntrinsicNode::LL) { 7790 // Divide diff by 2 to get number of chars 7791 sarl(cnt2, 1); 7792 } 7793 addq(result, cnt2); 7794 if (ae == StrIntrinsicNode::LL) { 7795 load_unsigned_byte(cnt1, Address(str2, result)); 7796 load_unsigned_byte(result, Address(str1, result)); 7797 } else if (ae == StrIntrinsicNode::UU) { 7798 load_unsigned_short(cnt1, Address(str2, result, scale)); 7799 load_unsigned_short(result, Address(str1, result, scale)); 7800 } else { 7801 load_unsigned_short(cnt1, Address(str2, result, scale2)); 7802 load_unsigned_byte(result, Address(str1, result, scale1)); 7803 } 7804 subl(result, cnt1); 7805 jmpb(POP_LABEL); 7806 }//if (VM_Version::supports_avx512vlbw()) 7807 #endif // _LP64 7808 7809 // Discard the stored length difference 7810 bind(POP_LABEL); 7811 pop(cnt1); 7812 7813 // That's it 7814 bind(DONE_LABEL); 7815 if(ae == StrIntrinsicNode::UL) { 7816 negl(result); 7817 } 7818 7819 } 7820 7821 // Search for Non-ASCII character (Negative byte value) in a byte array, 7822 // return true if it has any and false otherwise. 7823 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 7824 // @HotSpotIntrinsicCandidate 7825 // private static boolean hasNegatives(byte[] ba, int off, int len) { 7826 // for (int i = off; i < off + len; i++) { 7827 // if (ba[i] < 0) { 7828 // return true; 7829 // } 7830 // } 7831 // return false; 7832 // } 7833 void MacroAssembler::has_negatives(Register ary1, Register len, 7834 Register result, Register tmp1, 7835 XMMRegister vec1, XMMRegister vec2) { 7836 // rsi: byte array 7837 // rcx: len 7838 // rax: result 7839 ShortBranchVerifier sbv(this); 7840 assert_different_registers(ary1, len, result, tmp1); 7841 assert_different_registers(vec1, vec2); 7842 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 7843 7844 // len == 0 7845 testl(len, len); 7846 jcc(Assembler::zero, FALSE_LABEL); 7847 7848 if ((UseAVX > 2) && // AVX512 7849 VM_Version::supports_avx512vlbw() && 7850 VM_Version::supports_bmi2()) { 7851 7852 set_vector_masking(); // opening of the stub context for programming mask registers 7853 7854 Label test_64_loop, test_tail; 7855 Register tmp3_aliased = len; 7856 7857 movl(tmp1, len); 7858 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 7859 7860 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 7861 andl(len, ~(64 - 1)); // vector count (in chars) 7862 jccb(Assembler::zero, test_tail); 7863 7864 lea(ary1, Address(ary1, len, Address::times_1)); 7865 negptr(len); 7866 7867 bind(test_64_loop); 7868 // Check whether our 64 elements of size byte contain negatives 7869 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 7870 kortestql(k2, k2); 7871 jcc(Assembler::notZero, TRUE_LABEL); 7872 7873 addptr(len, 64); 7874 jccb(Assembler::notZero, test_64_loop); 7875 7876 7877 bind(test_tail); 7878 // bail out when there is nothing to be done 7879 testl(tmp1, -1); 7880 jcc(Assembler::zero, FALSE_LABEL); 7881 7882 // Save k1 7883 kmovql(k3, k1); 7884 7885 // ~(~0 << len) applied up to two times (for 32-bit scenario) 7886 #ifdef _LP64 7887 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 7888 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 7889 notq(tmp3_aliased); 7890 kmovql(k1, tmp3_aliased); 7891 #else 7892 Label k_init; 7893 jmp(k_init); 7894 7895 // We could not read 64-bits from a general purpose register thus we move 7896 // data required to compose 64 1's to the instruction stream 7897 // We emit 64 byte wide series of elements from 0..63 which later on would 7898 // be used as a compare targets with tail count contained in tmp1 register. 7899 // Result would be a k1 register having tmp1 consecutive number or 1 7900 // counting from least significant bit. 7901 address tmp = pc(); 7902 emit_int64(0x0706050403020100); 7903 emit_int64(0x0F0E0D0C0B0A0908); 7904 emit_int64(0x1716151413121110); 7905 emit_int64(0x1F1E1D1C1B1A1918); 7906 emit_int64(0x2726252423222120); 7907 emit_int64(0x2F2E2D2C2B2A2928); 7908 emit_int64(0x3736353433323130); 7909 emit_int64(0x3F3E3D3C3B3A3938); 7910 7911 bind(k_init); 7912 lea(len, InternalAddress(tmp)); 7913 // create mask to test for negative byte inside a vector 7914 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 7915 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 7916 7917 #endif 7918 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 7919 ktestq(k2, k1); 7920 // Restore k1 7921 kmovql(k1, k3); 7922 jcc(Assembler::notZero, TRUE_LABEL); 7923 7924 jmp(FALSE_LABEL); 7925 7926 clear_vector_masking(); // closing of the stub context for programming mask registers 7927 } else { 7928 movl(result, len); // copy 7929 7930 if (UseAVX == 2 && UseSSE >= 2) { 7931 // With AVX2, use 32-byte vector compare 7932 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 7933 7934 // Compare 32-byte vectors 7935 andl(result, 0x0000001f); // tail count (in bytes) 7936 andl(len, 0xffffffe0); // vector count (in bytes) 7937 jccb(Assembler::zero, COMPARE_TAIL); 7938 7939 lea(ary1, Address(ary1, len, Address::times_1)); 7940 negptr(len); 7941 7942 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 7943 movdl(vec2, tmp1); 7944 vpbroadcastd(vec2, vec2); 7945 7946 bind(COMPARE_WIDE_VECTORS); 7947 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 7948 vptest(vec1, vec2); 7949 jccb(Assembler::notZero, TRUE_LABEL); 7950 addptr(len, 32); 7951 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 7952 7953 testl(result, result); 7954 jccb(Assembler::zero, FALSE_LABEL); 7955 7956 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 7957 vptest(vec1, vec2); 7958 jccb(Assembler::notZero, TRUE_LABEL); 7959 jmpb(FALSE_LABEL); 7960 7961 bind(COMPARE_TAIL); // len is zero 7962 movl(len, result); 7963 // Fallthru to tail compare 7964 } else if (UseSSE42Intrinsics) { 7965 // With SSE4.2, use double quad vector compare 7966 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 7967 7968 // Compare 16-byte vectors 7969 andl(result, 0x0000000f); // tail count (in bytes) 7970 andl(len, 0xfffffff0); // vector count (in bytes) 7971 jccb(Assembler::zero, COMPARE_TAIL); 7972 7973 lea(ary1, Address(ary1, len, Address::times_1)); 7974 negptr(len); 7975 7976 movl(tmp1, 0x80808080); 7977 movdl(vec2, tmp1); 7978 pshufd(vec2, vec2, 0); 7979 7980 bind(COMPARE_WIDE_VECTORS); 7981 movdqu(vec1, Address(ary1, len, Address::times_1)); 7982 ptest(vec1, vec2); 7983 jccb(Assembler::notZero, TRUE_LABEL); 7984 addptr(len, 16); 7985 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 7986 7987 testl(result, result); 7988 jccb(Assembler::zero, FALSE_LABEL); 7989 7990 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 7991 ptest(vec1, vec2); 7992 jccb(Assembler::notZero, TRUE_LABEL); 7993 jmpb(FALSE_LABEL); 7994 7995 bind(COMPARE_TAIL); // len is zero 7996 movl(len, result); 7997 // Fallthru to tail compare 7998 } 7999 } 8000 // Compare 4-byte vectors 8001 andl(len, 0xfffffffc); // vector count (in bytes) 8002 jccb(Assembler::zero, COMPARE_CHAR); 8003 8004 lea(ary1, Address(ary1, len, Address::times_1)); 8005 negptr(len); 8006 8007 bind(COMPARE_VECTORS); 8008 movl(tmp1, Address(ary1, len, Address::times_1)); 8009 andl(tmp1, 0x80808080); 8010 jccb(Assembler::notZero, TRUE_LABEL); 8011 addptr(len, 4); 8012 jcc(Assembler::notZero, COMPARE_VECTORS); 8013 8014 // Compare trailing char (final 2 bytes), if any 8015 bind(COMPARE_CHAR); 8016 testl(result, 0x2); // tail char 8017 jccb(Assembler::zero, COMPARE_BYTE); 8018 load_unsigned_short(tmp1, Address(ary1, 0)); 8019 andl(tmp1, 0x00008080); 8020 jccb(Assembler::notZero, TRUE_LABEL); 8021 subptr(result, 2); 8022 lea(ary1, Address(ary1, 2)); 8023 8024 bind(COMPARE_BYTE); 8025 testl(result, 0x1); // tail byte 8026 jccb(Assembler::zero, FALSE_LABEL); 8027 load_unsigned_byte(tmp1, Address(ary1, 0)); 8028 andl(tmp1, 0x00000080); 8029 jccb(Assembler::notEqual, TRUE_LABEL); 8030 jmpb(FALSE_LABEL); 8031 8032 bind(TRUE_LABEL); 8033 movl(result, 1); // return true 8034 jmpb(DONE); 8035 8036 bind(FALSE_LABEL); 8037 xorl(result, result); // return false 8038 8039 // That's it 8040 bind(DONE); 8041 if (UseAVX >= 2 && UseSSE >= 2) { 8042 // clean upper bits of YMM registers 8043 vpxor(vec1, vec1); 8044 vpxor(vec2, vec2); 8045 } 8046 } 8047 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8048 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8049 Register limit, Register result, Register chr, 8050 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8051 ShortBranchVerifier sbv(this); 8052 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8053 8054 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8055 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8056 8057 if (is_array_equ) { 8058 // Check the input args 8059 cmpoop(ary1, ary2); 8060 jcc(Assembler::equal, TRUE_LABEL); 8061 8062 // Need additional checks for arrays_equals. 8063 testptr(ary1, ary1); 8064 jcc(Assembler::zero, FALSE_LABEL); 8065 testptr(ary2, ary2); 8066 jcc(Assembler::zero, FALSE_LABEL); 8067 8068 // Check the lengths 8069 movl(limit, Address(ary1, length_offset)); 8070 cmpl(limit, Address(ary2, length_offset)); 8071 jcc(Assembler::notEqual, FALSE_LABEL); 8072 } 8073 8074 // count == 0 8075 testl(limit, limit); 8076 jcc(Assembler::zero, TRUE_LABEL); 8077 8078 if (is_array_equ) { 8079 // Load array address 8080 lea(ary1, Address(ary1, base_offset)); 8081 lea(ary2, Address(ary2, base_offset)); 8082 } 8083 8084 if (is_array_equ && is_char) { 8085 // arrays_equals when used for char[]. 8086 shll(limit, 1); // byte count != 0 8087 } 8088 movl(result, limit); // copy 8089 8090 if (UseAVX >= 2) { 8091 // With AVX2, use 32-byte vector compare 8092 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8093 8094 // Compare 32-byte vectors 8095 andl(result, 0x0000001f); // tail count (in bytes) 8096 andl(limit, 0xffffffe0); // vector count (in bytes) 8097 jcc(Assembler::zero, COMPARE_TAIL); 8098 8099 lea(ary1, Address(ary1, limit, Address::times_1)); 8100 lea(ary2, Address(ary2, limit, Address::times_1)); 8101 negptr(limit); 8102 8103 bind(COMPARE_WIDE_VECTORS); 8104 8105 #ifdef _LP64 8106 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8107 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8108 8109 cmpl(limit, -64); 8110 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8111 8112 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8113 8114 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8115 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8116 kortestql(k7, k7); 8117 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8118 addptr(limit, 64); // update since we already compared at this addr 8119 cmpl(limit, -64); 8120 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8121 8122 // At this point we may still need to compare -limit+result bytes. 8123 // We could execute the next two instruction and just continue via non-wide path: 8124 // cmpl(limit, 0); 8125 // jcc(Assembler::equal, COMPARE_TAIL); // true 8126 // But since we stopped at the points ary{1,2}+limit which are 8127 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8128 // (|limit| <= 32 and result < 32), 8129 // we may just compare the last 64 bytes. 8130 // 8131 addptr(result, -64); // it is safe, bc we just came from this area 8132 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8133 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8134 kortestql(k7, k7); 8135 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8136 8137 jmp(TRUE_LABEL); 8138 8139 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8140 8141 }//if (VM_Version::supports_avx512vlbw()) 8142 #endif //_LP64 8143 8144 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8145 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8146 vpxor(vec1, vec2); 8147 8148 vptest(vec1, vec1); 8149 jcc(Assembler::notZero, FALSE_LABEL); 8150 addptr(limit, 32); 8151 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8152 8153 testl(result, result); 8154 jcc(Assembler::zero, TRUE_LABEL); 8155 8156 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8157 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8158 vpxor(vec1, vec2); 8159 8160 vptest(vec1, vec1); 8161 jccb(Assembler::notZero, FALSE_LABEL); 8162 jmpb(TRUE_LABEL); 8163 8164 bind(COMPARE_TAIL); // limit is zero 8165 movl(limit, result); 8166 // Fallthru to tail compare 8167 } else if (UseSSE42Intrinsics) { 8168 // With SSE4.2, use double quad vector compare 8169 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8170 8171 // Compare 16-byte vectors 8172 andl(result, 0x0000000f); // tail count (in bytes) 8173 andl(limit, 0xfffffff0); // vector count (in bytes) 8174 jcc(Assembler::zero, COMPARE_TAIL); 8175 8176 lea(ary1, Address(ary1, limit, Address::times_1)); 8177 lea(ary2, Address(ary2, limit, Address::times_1)); 8178 negptr(limit); 8179 8180 bind(COMPARE_WIDE_VECTORS); 8181 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8182 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8183 pxor(vec1, vec2); 8184 8185 ptest(vec1, vec1); 8186 jcc(Assembler::notZero, FALSE_LABEL); 8187 addptr(limit, 16); 8188 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8189 8190 testl(result, result); 8191 jcc(Assembler::zero, TRUE_LABEL); 8192 8193 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8194 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8195 pxor(vec1, vec2); 8196 8197 ptest(vec1, vec1); 8198 jccb(Assembler::notZero, FALSE_LABEL); 8199 jmpb(TRUE_LABEL); 8200 8201 bind(COMPARE_TAIL); // limit is zero 8202 movl(limit, result); 8203 // Fallthru to tail compare 8204 } 8205 8206 // Compare 4-byte vectors 8207 andl(limit, 0xfffffffc); // vector count (in bytes) 8208 jccb(Assembler::zero, COMPARE_CHAR); 8209 8210 lea(ary1, Address(ary1, limit, Address::times_1)); 8211 lea(ary2, Address(ary2, limit, Address::times_1)); 8212 negptr(limit); 8213 8214 bind(COMPARE_VECTORS); 8215 movl(chr, Address(ary1, limit, Address::times_1)); 8216 cmpl(chr, Address(ary2, limit, Address::times_1)); 8217 jccb(Assembler::notEqual, FALSE_LABEL); 8218 addptr(limit, 4); 8219 jcc(Assembler::notZero, COMPARE_VECTORS); 8220 8221 // Compare trailing char (final 2 bytes), if any 8222 bind(COMPARE_CHAR); 8223 testl(result, 0x2); // tail char 8224 jccb(Assembler::zero, COMPARE_BYTE); 8225 load_unsigned_short(chr, Address(ary1, 0)); 8226 load_unsigned_short(limit, Address(ary2, 0)); 8227 cmpl(chr, limit); 8228 jccb(Assembler::notEqual, FALSE_LABEL); 8229 8230 if (is_array_equ && is_char) { 8231 bind(COMPARE_BYTE); 8232 } else { 8233 lea(ary1, Address(ary1, 2)); 8234 lea(ary2, Address(ary2, 2)); 8235 8236 bind(COMPARE_BYTE); 8237 testl(result, 0x1); // tail byte 8238 jccb(Assembler::zero, TRUE_LABEL); 8239 load_unsigned_byte(chr, Address(ary1, 0)); 8240 load_unsigned_byte(limit, Address(ary2, 0)); 8241 cmpl(chr, limit); 8242 jccb(Assembler::notEqual, FALSE_LABEL); 8243 } 8244 bind(TRUE_LABEL); 8245 movl(result, 1); // return true 8246 jmpb(DONE); 8247 8248 bind(FALSE_LABEL); 8249 xorl(result, result); // return false 8250 8251 // That's it 8252 bind(DONE); 8253 if (UseAVX >= 2) { 8254 // clean upper bits of YMM registers 8255 vpxor(vec1, vec1); 8256 vpxor(vec2, vec2); 8257 } 8258 } 8259 8260 #endif 8261 8262 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8263 Register to, Register value, Register count, 8264 Register rtmp, XMMRegister xtmp) { 8265 ShortBranchVerifier sbv(this); 8266 assert_different_registers(to, value, count, rtmp); 8267 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8268 Label L_fill_2_bytes, L_fill_4_bytes; 8269 8270 int shift = -1; 8271 switch (t) { 8272 case T_BYTE: 8273 shift = 2; 8274 break; 8275 case T_SHORT: 8276 shift = 1; 8277 break; 8278 case T_INT: 8279 shift = 0; 8280 break; 8281 default: ShouldNotReachHere(); 8282 } 8283 8284 if (t == T_BYTE) { 8285 andl(value, 0xff); 8286 movl(rtmp, value); 8287 shll(rtmp, 8); 8288 orl(value, rtmp); 8289 } 8290 if (t == T_SHORT) { 8291 andl(value, 0xffff); 8292 } 8293 if (t == T_BYTE || t == T_SHORT) { 8294 movl(rtmp, value); 8295 shll(rtmp, 16); 8296 orl(value, rtmp); 8297 } 8298 8299 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8300 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8301 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8302 // align source address at 4 bytes address boundary 8303 if (t == T_BYTE) { 8304 // One byte misalignment happens only for byte arrays 8305 testptr(to, 1); 8306 jccb(Assembler::zero, L_skip_align1); 8307 movb(Address(to, 0), value); 8308 increment(to); 8309 decrement(count); 8310 BIND(L_skip_align1); 8311 } 8312 // Two bytes misalignment happens only for byte and short (char) arrays 8313 testptr(to, 2); 8314 jccb(Assembler::zero, L_skip_align2); 8315 movw(Address(to, 0), value); 8316 addptr(to, 2); 8317 subl(count, 1<<(shift-1)); 8318 BIND(L_skip_align2); 8319 } 8320 if (UseSSE < 2) { 8321 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8322 // Fill 32-byte chunks 8323 subl(count, 8 << shift); 8324 jcc(Assembler::less, L_check_fill_8_bytes); 8325 align(16); 8326 8327 BIND(L_fill_32_bytes_loop); 8328 8329 for (int i = 0; i < 32; i += 4) { 8330 movl(Address(to, i), value); 8331 } 8332 8333 addptr(to, 32); 8334 subl(count, 8 << shift); 8335 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8336 BIND(L_check_fill_8_bytes); 8337 addl(count, 8 << shift); 8338 jccb(Assembler::zero, L_exit); 8339 jmpb(L_fill_8_bytes); 8340 8341 // 8342 // length is too short, just fill qwords 8343 // 8344 BIND(L_fill_8_bytes_loop); 8345 movl(Address(to, 0), value); 8346 movl(Address(to, 4), value); 8347 addptr(to, 8); 8348 BIND(L_fill_8_bytes); 8349 subl(count, 1 << (shift + 1)); 8350 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8351 // fall through to fill 4 bytes 8352 } else { 8353 Label L_fill_32_bytes; 8354 if (!UseUnalignedLoadStores) { 8355 // align to 8 bytes, we know we are 4 byte aligned to start 8356 testptr(to, 4); 8357 jccb(Assembler::zero, L_fill_32_bytes); 8358 movl(Address(to, 0), value); 8359 addptr(to, 4); 8360 subl(count, 1<<shift); 8361 } 8362 BIND(L_fill_32_bytes); 8363 { 8364 assert( UseSSE >= 2, "supported cpu only" ); 8365 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8366 if (UseAVX > 2) { 8367 movl(rtmp, 0xffff); 8368 kmovwl(k1, rtmp); 8369 } 8370 movdl(xtmp, value); 8371 if (UseAVX > 2 && UseUnalignedLoadStores) { 8372 // Fill 64-byte chunks 8373 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8374 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8375 8376 subl(count, 16 << shift); 8377 jcc(Assembler::less, L_check_fill_32_bytes); 8378 align(16); 8379 8380 BIND(L_fill_64_bytes_loop); 8381 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8382 addptr(to, 64); 8383 subl(count, 16 << shift); 8384 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8385 8386 BIND(L_check_fill_32_bytes); 8387 addl(count, 8 << shift); 8388 jccb(Assembler::less, L_check_fill_8_bytes); 8389 vmovdqu(Address(to, 0), xtmp); 8390 addptr(to, 32); 8391 subl(count, 8 << shift); 8392 8393 BIND(L_check_fill_8_bytes); 8394 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8395 // Fill 64-byte chunks 8396 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8397 vpbroadcastd(xtmp, xtmp); 8398 8399 subl(count, 16 << shift); 8400 jcc(Assembler::less, L_check_fill_32_bytes); 8401 align(16); 8402 8403 BIND(L_fill_64_bytes_loop); 8404 vmovdqu(Address(to, 0), xtmp); 8405 vmovdqu(Address(to, 32), xtmp); 8406 addptr(to, 64); 8407 subl(count, 16 << shift); 8408 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8409 8410 BIND(L_check_fill_32_bytes); 8411 addl(count, 8 << shift); 8412 jccb(Assembler::less, L_check_fill_8_bytes); 8413 vmovdqu(Address(to, 0), xtmp); 8414 addptr(to, 32); 8415 subl(count, 8 << shift); 8416 8417 BIND(L_check_fill_8_bytes); 8418 // clean upper bits of YMM registers 8419 movdl(xtmp, value); 8420 pshufd(xtmp, xtmp, 0); 8421 } else { 8422 // Fill 32-byte chunks 8423 pshufd(xtmp, xtmp, 0); 8424 8425 subl(count, 8 << shift); 8426 jcc(Assembler::less, L_check_fill_8_bytes); 8427 align(16); 8428 8429 BIND(L_fill_32_bytes_loop); 8430 8431 if (UseUnalignedLoadStores) { 8432 movdqu(Address(to, 0), xtmp); 8433 movdqu(Address(to, 16), xtmp); 8434 } else { 8435 movq(Address(to, 0), xtmp); 8436 movq(Address(to, 8), xtmp); 8437 movq(Address(to, 16), xtmp); 8438 movq(Address(to, 24), xtmp); 8439 } 8440 8441 addptr(to, 32); 8442 subl(count, 8 << shift); 8443 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8444 8445 BIND(L_check_fill_8_bytes); 8446 } 8447 addl(count, 8 << shift); 8448 jccb(Assembler::zero, L_exit); 8449 jmpb(L_fill_8_bytes); 8450 8451 // 8452 // length is too short, just fill qwords 8453 // 8454 BIND(L_fill_8_bytes_loop); 8455 movq(Address(to, 0), xtmp); 8456 addptr(to, 8); 8457 BIND(L_fill_8_bytes); 8458 subl(count, 1 << (shift + 1)); 8459 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8460 } 8461 } 8462 // fill trailing 4 bytes 8463 BIND(L_fill_4_bytes); 8464 testl(count, 1<<shift); 8465 jccb(Assembler::zero, L_fill_2_bytes); 8466 movl(Address(to, 0), value); 8467 if (t == T_BYTE || t == T_SHORT) { 8468 addptr(to, 4); 8469 BIND(L_fill_2_bytes); 8470 // fill trailing 2 bytes 8471 testl(count, 1<<(shift-1)); 8472 jccb(Assembler::zero, L_fill_byte); 8473 movw(Address(to, 0), value); 8474 if (t == T_BYTE) { 8475 addptr(to, 2); 8476 BIND(L_fill_byte); 8477 // fill trailing byte 8478 testl(count, 1); 8479 jccb(Assembler::zero, L_exit); 8480 movb(Address(to, 0), value); 8481 } else { 8482 BIND(L_fill_byte); 8483 } 8484 } else { 8485 BIND(L_fill_2_bytes); 8486 } 8487 BIND(L_exit); 8488 } 8489 8490 // encode char[] to byte[] in ISO_8859_1 8491 //@HotSpotIntrinsicCandidate 8492 //private static int implEncodeISOArray(byte[] sa, int sp, 8493 //byte[] da, int dp, int len) { 8494 // int i = 0; 8495 // for (; i < len; i++) { 8496 // char c = StringUTF16.getChar(sa, sp++); 8497 // if (c > '\u00FF') 8498 // break; 8499 // da[dp++] = (byte)c; 8500 // } 8501 // return i; 8502 //} 8503 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8504 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8505 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8506 Register tmp5, Register result) { 8507 8508 // rsi: src 8509 // rdi: dst 8510 // rdx: len 8511 // rcx: tmp5 8512 // rax: result 8513 ShortBranchVerifier sbv(this); 8514 assert_different_registers(src, dst, len, tmp5, result); 8515 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8516 8517 // set result 8518 xorl(result, result); 8519 // check for zero length 8520 testl(len, len); 8521 jcc(Assembler::zero, L_done); 8522 8523 movl(result, len); 8524 8525 // Setup pointers 8526 lea(src, Address(src, len, Address::times_2)); // char[] 8527 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8528 negptr(len); 8529 8530 if (UseSSE42Intrinsics || UseAVX >= 2) { 8531 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8532 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8533 8534 if (UseAVX >= 2) { 8535 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8536 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8537 movdl(tmp1Reg, tmp5); 8538 vpbroadcastd(tmp1Reg, tmp1Reg); 8539 jmp(L_chars_32_check); 8540 8541 bind(L_copy_32_chars); 8542 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8543 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8544 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8545 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8546 jccb(Assembler::notZero, L_copy_32_chars_exit); 8547 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8548 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8549 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8550 8551 bind(L_chars_32_check); 8552 addptr(len, 32); 8553 jcc(Assembler::lessEqual, L_copy_32_chars); 8554 8555 bind(L_copy_32_chars_exit); 8556 subptr(len, 16); 8557 jccb(Assembler::greater, L_copy_16_chars_exit); 8558 8559 } else if (UseSSE42Intrinsics) { 8560 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8561 movdl(tmp1Reg, tmp5); 8562 pshufd(tmp1Reg, tmp1Reg, 0); 8563 jmpb(L_chars_16_check); 8564 } 8565 8566 bind(L_copy_16_chars); 8567 if (UseAVX >= 2) { 8568 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8569 vptest(tmp2Reg, tmp1Reg); 8570 jcc(Assembler::notZero, L_copy_16_chars_exit); 8571 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8572 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8573 } else { 8574 if (UseAVX > 0) { 8575 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8576 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8577 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8578 } else { 8579 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8580 por(tmp2Reg, tmp3Reg); 8581 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8582 por(tmp2Reg, tmp4Reg); 8583 } 8584 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8585 jccb(Assembler::notZero, L_copy_16_chars_exit); 8586 packuswb(tmp3Reg, tmp4Reg); 8587 } 8588 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8589 8590 bind(L_chars_16_check); 8591 addptr(len, 16); 8592 jcc(Assembler::lessEqual, L_copy_16_chars); 8593 8594 bind(L_copy_16_chars_exit); 8595 if (UseAVX >= 2) { 8596 // clean upper bits of YMM registers 8597 vpxor(tmp2Reg, tmp2Reg); 8598 vpxor(tmp3Reg, tmp3Reg); 8599 vpxor(tmp4Reg, tmp4Reg); 8600 movdl(tmp1Reg, tmp5); 8601 pshufd(tmp1Reg, tmp1Reg, 0); 8602 } 8603 subptr(len, 8); 8604 jccb(Assembler::greater, L_copy_8_chars_exit); 8605 8606 bind(L_copy_8_chars); 8607 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8608 ptest(tmp3Reg, tmp1Reg); 8609 jccb(Assembler::notZero, L_copy_8_chars_exit); 8610 packuswb(tmp3Reg, tmp1Reg); 8611 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8612 addptr(len, 8); 8613 jccb(Assembler::lessEqual, L_copy_8_chars); 8614 8615 bind(L_copy_8_chars_exit); 8616 subptr(len, 8); 8617 jccb(Assembler::zero, L_done); 8618 } 8619 8620 bind(L_copy_1_char); 8621 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8622 testl(tmp5, 0xff00); // check if Unicode char 8623 jccb(Assembler::notZero, L_copy_1_char_exit); 8624 movb(Address(dst, len, Address::times_1, 0), tmp5); 8625 addptr(len, 1); 8626 jccb(Assembler::less, L_copy_1_char); 8627 8628 bind(L_copy_1_char_exit); 8629 addptr(result, len); // len is negative count of not processed elements 8630 8631 bind(L_done); 8632 } 8633 8634 #ifdef _LP64 8635 /** 8636 * Helper for multiply_to_len(). 8637 */ 8638 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8639 addq(dest_lo, src1); 8640 adcq(dest_hi, 0); 8641 addq(dest_lo, src2); 8642 adcq(dest_hi, 0); 8643 } 8644 8645 /** 8646 * Multiply 64 bit by 64 bit first loop. 8647 */ 8648 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8649 Register y, Register y_idx, Register z, 8650 Register carry, Register product, 8651 Register idx, Register kdx) { 8652 // 8653 // jlong carry, x[], y[], z[]; 8654 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8655 // huge_128 product = y[idx] * x[xstart] + carry; 8656 // z[kdx] = (jlong)product; 8657 // carry = (jlong)(product >>> 64); 8658 // } 8659 // z[xstart] = carry; 8660 // 8661 8662 Label L_first_loop, L_first_loop_exit; 8663 Label L_one_x, L_one_y, L_multiply; 8664 8665 decrementl(xstart); 8666 jcc(Assembler::negative, L_one_x); 8667 8668 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8669 rorq(x_xstart, 32); // convert big-endian to little-endian 8670 8671 bind(L_first_loop); 8672 decrementl(idx); 8673 jcc(Assembler::negative, L_first_loop_exit); 8674 decrementl(idx); 8675 jcc(Assembler::negative, L_one_y); 8676 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8677 rorq(y_idx, 32); // convert big-endian to little-endian 8678 bind(L_multiply); 8679 movq(product, x_xstart); 8680 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 8681 addq(product, carry); 8682 adcq(rdx, 0); 8683 subl(kdx, 2); 8684 movl(Address(z, kdx, Address::times_4, 4), product); 8685 shrq(product, 32); 8686 movl(Address(z, kdx, Address::times_4, 0), product); 8687 movq(carry, rdx); 8688 jmp(L_first_loop); 8689 8690 bind(L_one_y); 8691 movl(y_idx, Address(y, 0)); 8692 jmp(L_multiply); 8693 8694 bind(L_one_x); 8695 movl(x_xstart, Address(x, 0)); 8696 jmp(L_first_loop); 8697 8698 bind(L_first_loop_exit); 8699 } 8700 8701 /** 8702 * Multiply 64 bit by 64 bit and add 128 bit. 8703 */ 8704 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 8705 Register yz_idx, Register idx, 8706 Register carry, Register product, int offset) { 8707 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 8708 // z[kdx] = (jlong)product; 8709 8710 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 8711 rorq(yz_idx, 32); // convert big-endian to little-endian 8712 movq(product, x_xstart); 8713 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 8714 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 8715 rorq(yz_idx, 32); // convert big-endian to little-endian 8716 8717 add2_with_carry(rdx, product, carry, yz_idx); 8718 8719 movl(Address(z, idx, Address::times_4, offset+4), product); 8720 shrq(product, 32); 8721 movl(Address(z, idx, Address::times_4, offset), product); 8722 8723 } 8724 8725 /** 8726 * Multiply 128 bit by 128 bit. Unrolled inner loop. 8727 */ 8728 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 8729 Register yz_idx, Register idx, Register jdx, 8730 Register carry, Register product, 8731 Register carry2) { 8732 // jlong carry, x[], y[], z[]; 8733 // int kdx = ystart+1; 8734 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 8735 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 8736 // z[kdx+idx+1] = (jlong)product; 8737 // jlong carry2 = (jlong)(product >>> 64); 8738 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 8739 // z[kdx+idx] = (jlong)product; 8740 // carry = (jlong)(product >>> 64); 8741 // } 8742 // idx += 2; 8743 // if (idx > 0) { 8744 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 8745 // z[kdx+idx] = (jlong)product; 8746 // carry = (jlong)(product >>> 64); 8747 // } 8748 // 8749 8750 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 8751 8752 movl(jdx, idx); 8753 andl(jdx, 0xFFFFFFFC); 8754 shrl(jdx, 2); 8755 8756 bind(L_third_loop); 8757 subl(jdx, 1); 8758 jcc(Assembler::negative, L_third_loop_exit); 8759 subl(idx, 4); 8760 8761 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 8762 movq(carry2, rdx); 8763 8764 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 8765 movq(carry, rdx); 8766 jmp(L_third_loop); 8767 8768 bind (L_third_loop_exit); 8769 8770 andl (idx, 0x3); 8771 jcc(Assembler::zero, L_post_third_loop_done); 8772 8773 Label L_check_1; 8774 subl(idx, 2); 8775 jcc(Assembler::negative, L_check_1); 8776 8777 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 8778 movq(carry, rdx); 8779 8780 bind (L_check_1); 8781 addl (idx, 0x2); 8782 andl (idx, 0x1); 8783 subl(idx, 1); 8784 jcc(Assembler::negative, L_post_third_loop_done); 8785 8786 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 8787 movq(product, x_xstart); 8788 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 8789 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 8790 8791 add2_with_carry(rdx, product, yz_idx, carry); 8792 8793 movl(Address(z, idx, Address::times_4, 0), product); 8794 shrq(product, 32); 8795 8796 shlq(rdx, 32); 8797 orq(product, rdx); 8798 movq(carry, product); 8799 8800 bind(L_post_third_loop_done); 8801 } 8802 8803 /** 8804 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 8805 * 8806 */ 8807 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 8808 Register carry, Register carry2, 8809 Register idx, Register jdx, 8810 Register yz_idx1, Register yz_idx2, 8811 Register tmp, Register tmp3, Register tmp4) { 8812 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 8813 8814 // jlong carry, x[], y[], z[]; 8815 // int kdx = ystart+1; 8816 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 8817 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 8818 // jlong carry2 = (jlong)(tmp3 >>> 64); 8819 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 8820 // carry = (jlong)(tmp4 >>> 64); 8821 // z[kdx+idx+1] = (jlong)tmp3; 8822 // z[kdx+idx] = (jlong)tmp4; 8823 // } 8824 // idx += 2; 8825 // if (idx > 0) { 8826 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 8827 // z[kdx+idx] = (jlong)yz_idx1; 8828 // carry = (jlong)(yz_idx1 >>> 64); 8829 // } 8830 // 8831 8832 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 8833 8834 movl(jdx, idx); 8835 andl(jdx, 0xFFFFFFFC); 8836 shrl(jdx, 2); 8837 8838 bind(L_third_loop); 8839 subl(jdx, 1); 8840 jcc(Assembler::negative, L_third_loop_exit); 8841 subl(idx, 4); 8842 8843 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 8844 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 8845 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 8846 rorxq(yz_idx2, yz_idx2, 32); 8847 8848 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 8849 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 8850 8851 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 8852 rorxq(yz_idx1, yz_idx1, 32); 8853 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 8854 rorxq(yz_idx2, yz_idx2, 32); 8855 8856 if (VM_Version::supports_adx()) { 8857 adcxq(tmp3, carry); 8858 adoxq(tmp3, yz_idx1); 8859 8860 adcxq(tmp4, tmp); 8861 adoxq(tmp4, yz_idx2); 8862 8863 movl(carry, 0); // does not affect flags 8864 adcxq(carry2, carry); 8865 adoxq(carry2, carry); 8866 } else { 8867 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 8868 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 8869 } 8870 movq(carry, carry2); 8871 8872 movl(Address(z, idx, Address::times_4, 12), tmp3); 8873 shrq(tmp3, 32); 8874 movl(Address(z, idx, Address::times_4, 8), tmp3); 8875 8876 movl(Address(z, idx, Address::times_4, 4), tmp4); 8877 shrq(tmp4, 32); 8878 movl(Address(z, idx, Address::times_4, 0), tmp4); 8879 8880 jmp(L_third_loop); 8881 8882 bind (L_third_loop_exit); 8883 8884 andl (idx, 0x3); 8885 jcc(Assembler::zero, L_post_third_loop_done); 8886 8887 Label L_check_1; 8888 subl(idx, 2); 8889 jcc(Assembler::negative, L_check_1); 8890 8891 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 8892 rorxq(yz_idx1, yz_idx1, 32); 8893 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 8894 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 8895 rorxq(yz_idx2, yz_idx2, 32); 8896 8897 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 8898 8899 movl(Address(z, idx, Address::times_4, 4), tmp3); 8900 shrq(tmp3, 32); 8901 movl(Address(z, idx, Address::times_4, 0), tmp3); 8902 movq(carry, tmp4); 8903 8904 bind (L_check_1); 8905 addl (idx, 0x2); 8906 andl (idx, 0x1); 8907 subl(idx, 1); 8908 jcc(Assembler::negative, L_post_third_loop_done); 8909 movl(tmp4, Address(y, idx, Address::times_4, 0)); 8910 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 8911 movl(tmp4, Address(z, idx, Address::times_4, 0)); 8912 8913 add2_with_carry(carry2, tmp3, tmp4, carry); 8914 8915 movl(Address(z, idx, Address::times_4, 0), tmp3); 8916 shrq(tmp3, 32); 8917 8918 shlq(carry2, 32); 8919 orq(tmp3, carry2); 8920 movq(carry, tmp3); 8921 8922 bind(L_post_third_loop_done); 8923 } 8924 8925 /** 8926 * Code for BigInteger::multiplyToLen() instrinsic. 8927 * 8928 * rdi: x 8929 * rax: xlen 8930 * rsi: y 8931 * rcx: ylen 8932 * r8: z 8933 * r11: zlen 8934 * r12: tmp1 8935 * r13: tmp2 8936 * r14: tmp3 8937 * r15: tmp4 8938 * rbx: tmp5 8939 * 8940 */ 8941 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 8942 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 8943 ShortBranchVerifier sbv(this); 8944 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 8945 8946 push(tmp1); 8947 push(tmp2); 8948 push(tmp3); 8949 push(tmp4); 8950 push(tmp5); 8951 8952 push(xlen); 8953 push(zlen); 8954 8955 const Register idx = tmp1; 8956 const Register kdx = tmp2; 8957 const Register xstart = tmp3; 8958 8959 const Register y_idx = tmp4; 8960 const Register carry = tmp5; 8961 const Register product = xlen; 8962 const Register x_xstart = zlen; // reuse register 8963 8964 // First Loop. 8965 // 8966 // final static long LONG_MASK = 0xffffffffL; 8967 // int xstart = xlen - 1; 8968 // int ystart = ylen - 1; 8969 // long carry = 0; 8970 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8971 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 8972 // z[kdx] = (int)product; 8973 // carry = product >>> 32; 8974 // } 8975 // z[xstart] = (int)carry; 8976 // 8977 8978 movl(idx, ylen); // idx = ylen; 8979 movl(kdx, zlen); // kdx = xlen+ylen; 8980 xorq(carry, carry); // carry = 0; 8981 8982 Label L_done; 8983 8984 movl(xstart, xlen); 8985 decrementl(xstart); 8986 jcc(Assembler::negative, L_done); 8987 8988 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 8989 8990 Label L_second_loop; 8991 testl(kdx, kdx); 8992 jcc(Assembler::zero, L_second_loop); 8993 8994 Label L_carry; 8995 subl(kdx, 1); 8996 jcc(Assembler::zero, L_carry); 8997 8998 movl(Address(z, kdx, Address::times_4, 0), carry); 8999 shrq(carry, 32); 9000 subl(kdx, 1); 9001 9002 bind(L_carry); 9003 movl(Address(z, kdx, Address::times_4, 0), carry); 9004 9005 // Second and third (nested) loops. 9006 // 9007 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9008 // carry = 0; 9009 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9010 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9011 // (z[k] & LONG_MASK) + carry; 9012 // z[k] = (int)product; 9013 // carry = product >>> 32; 9014 // } 9015 // z[i] = (int)carry; 9016 // } 9017 // 9018 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9019 9020 const Register jdx = tmp1; 9021 9022 bind(L_second_loop); 9023 xorl(carry, carry); // carry = 0; 9024 movl(jdx, ylen); // j = ystart+1 9025 9026 subl(xstart, 1); // i = xstart-1; 9027 jcc(Assembler::negative, L_done); 9028 9029 push (z); 9030 9031 Label L_last_x; 9032 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9033 subl(xstart, 1); // i = xstart-1; 9034 jcc(Assembler::negative, L_last_x); 9035 9036 if (UseBMI2Instructions) { 9037 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9038 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9039 } else { 9040 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9041 rorq(x_xstart, 32); // convert big-endian to little-endian 9042 } 9043 9044 Label L_third_loop_prologue; 9045 bind(L_third_loop_prologue); 9046 9047 push (x); 9048 push (xstart); 9049 push (ylen); 9050 9051 9052 if (UseBMI2Instructions) { 9053 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9054 } else { // !UseBMI2Instructions 9055 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9056 } 9057 9058 pop(ylen); 9059 pop(xlen); 9060 pop(x); 9061 pop(z); 9062 9063 movl(tmp3, xlen); 9064 addl(tmp3, 1); 9065 movl(Address(z, tmp3, Address::times_4, 0), carry); 9066 subl(tmp3, 1); 9067 jccb(Assembler::negative, L_done); 9068 9069 shrq(carry, 32); 9070 movl(Address(z, tmp3, Address::times_4, 0), carry); 9071 jmp(L_second_loop); 9072 9073 // Next infrequent code is moved outside loops. 9074 bind(L_last_x); 9075 if (UseBMI2Instructions) { 9076 movl(rdx, Address(x, 0)); 9077 } else { 9078 movl(x_xstart, Address(x, 0)); 9079 } 9080 jmp(L_third_loop_prologue); 9081 9082 bind(L_done); 9083 9084 pop(zlen); 9085 pop(xlen); 9086 9087 pop(tmp5); 9088 pop(tmp4); 9089 pop(tmp3); 9090 pop(tmp2); 9091 pop(tmp1); 9092 } 9093 9094 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9095 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9096 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9097 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9098 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9099 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9100 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9101 Label SAME_TILL_END, DONE; 9102 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9103 9104 //scale is in rcx in both Win64 and Unix 9105 ShortBranchVerifier sbv(this); 9106 9107 shlq(length); 9108 xorq(result, result); 9109 9110 if ((UseAVX > 2) && 9111 VM_Version::supports_avx512vlbw()) { 9112 set_vector_masking(); // opening of the stub context for programming mask registers 9113 cmpq(length, 64); 9114 jcc(Assembler::less, VECTOR32_TAIL); 9115 movq(tmp1, length); 9116 andq(tmp1, 0x3F); // tail count 9117 andq(length, ~(0x3F)); //vector count 9118 9119 bind(VECTOR64_LOOP); 9120 // AVX512 code to compare 64 byte vectors. 9121 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9122 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9123 kortestql(k7, k7); 9124 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9125 addq(result, 64); 9126 subq(length, 64); 9127 jccb(Assembler::notZero, VECTOR64_LOOP); 9128 9129 //bind(VECTOR64_TAIL); 9130 testq(tmp1, tmp1); 9131 jcc(Assembler::zero, SAME_TILL_END); 9132 9133 bind(VECTOR64_TAIL); 9134 // AVX512 code to compare upto 63 byte vectors. 9135 // Save k1 9136 kmovql(k3, k1); 9137 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9138 shlxq(tmp2, tmp2, tmp1); 9139 notq(tmp2); 9140 kmovql(k1, tmp2); 9141 9142 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9143 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9144 9145 ktestql(k7, k1); 9146 // Restore k1 9147 kmovql(k1, k3); 9148 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9149 9150 bind(VECTOR64_NOT_EQUAL); 9151 kmovql(tmp1, k7); 9152 notq(tmp1); 9153 tzcntq(tmp1, tmp1); 9154 addq(result, tmp1); 9155 shrq(result); 9156 jmp(DONE); 9157 bind(VECTOR32_TAIL); 9158 clear_vector_masking(); // closing of the stub context for programming mask registers 9159 } 9160 9161 cmpq(length, 8); 9162 jcc(Assembler::equal, VECTOR8_LOOP); 9163 jcc(Assembler::less, VECTOR4_TAIL); 9164 9165 if (UseAVX >= 2) { 9166 9167 cmpq(length, 16); 9168 jcc(Assembler::equal, VECTOR16_LOOP); 9169 jcc(Assembler::less, VECTOR8_LOOP); 9170 9171 cmpq(length, 32); 9172 jccb(Assembler::less, VECTOR16_TAIL); 9173 9174 subq(length, 32); 9175 bind(VECTOR32_LOOP); 9176 vmovdqu(rymm0, Address(obja, result)); 9177 vmovdqu(rymm1, Address(objb, result)); 9178 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9179 vptest(rymm2, rymm2); 9180 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9181 addq(result, 32); 9182 subq(length, 32); 9183 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9184 addq(length, 32); 9185 jcc(Assembler::equal, SAME_TILL_END); 9186 //falling through if less than 32 bytes left //close the branch here. 9187 9188 bind(VECTOR16_TAIL); 9189 cmpq(length, 16); 9190 jccb(Assembler::less, VECTOR8_TAIL); 9191 bind(VECTOR16_LOOP); 9192 movdqu(rymm0, Address(obja, result)); 9193 movdqu(rymm1, Address(objb, result)); 9194 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9195 ptest(rymm2, rymm2); 9196 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9197 addq(result, 16); 9198 subq(length, 16); 9199 jcc(Assembler::equal, SAME_TILL_END); 9200 //falling through if less than 16 bytes left 9201 } else {//regular intrinsics 9202 9203 cmpq(length, 16); 9204 jccb(Assembler::less, VECTOR8_TAIL); 9205 9206 subq(length, 16); 9207 bind(VECTOR16_LOOP); 9208 movdqu(rymm0, Address(obja, result)); 9209 movdqu(rymm1, Address(objb, result)); 9210 pxor(rymm0, rymm1); 9211 ptest(rymm0, rymm0); 9212 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9213 addq(result, 16); 9214 subq(length, 16); 9215 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9216 addq(length, 16); 9217 jcc(Assembler::equal, SAME_TILL_END); 9218 //falling through if less than 16 bytes left 9219 } 9220 9221 bind(VECTOR8_TAIL); 9222 cmpq(length, 8); 9223 jccb(Assembler::less, VECTOR4_TAIL); 9224 bind(VECTOR8_LOOP); 9225 movq(tmp1, Address(obja, result)); 9226 movq(tmp2, Address(objb, result)); 9227 xorq(tmp1, tmp2); 9228 testq(tmp1, tmp1); 9229 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9230 addq(result, 8); 9231 subq(length, 8); 9232 jcc(Assembler::equal, SAME_TILL_END); 9233 //falling through if less than 8 bytes left 9234 9235 bind(VECTOR4_TAIL); 9236 cmpq(length, 4); 9237 jccb(Assembler::less, BYTES_TAIL); 9238 bind(VECTOR4_LOOP); 9239 movl(tmp1, Address(obja, result)); 9240 xorl(tmp1, Address(objb, result)); 9241 testl(tmp1, tmp1); 9242 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9243 addq(result, 4); 9244 subq(length, 4); 9245 jcc(Assembler::equal, SAME_TILL_END); 9246 //falling through if less than 4 bytes left 9247 9248 bind(BYTES_TAIL); 9249 bind(BYTES_LOOP); 9250 load_unsigned_byte(tmp1, Address(obja, result)); 9251 load_unsigned_byte(tmp2, Address(objb, result)); 9252 xorl(tmp1, tmp2); 9253 testl(tmp1, tmp1); 9254 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9255 decq(length); 9256 jccb(Assembler::zero, SAME_TILL_END); 9257 incq(result); 9258 load_unsigned_byte(tmp1, Address(obja, result)); 9259 load_unsigned_byte(tmp2, Address(objb, result)); 9260 xorl(tmp1, tmp2); 9261 testl(tmp1, tmp1); 9262 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9263 decq(length); 9264 jccb(Assembler::zero, SAME_TILL_END); 9265 incq(result); 9266 load_unsigned_byte(tmp1, Address(obja, result)); 9267 load_unsigned_byte(tmp2, Address(objb, result)); 9268 xorl(tmp1, tmp2); 9269 testl(tmp1, tmp1); 9270 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9271 jmpb(SAME_TILL_END); 9272 9273 if (UseAVX >= 2) { 9274 bind(VECTOR32_NOT_EQUAL); 9275 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9276 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9277 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9278 vpmovmskb(tmp1, rymm0); 9279 bsfq(tmp1, tmp1); 9280 addq(result, tmp1); 9281 shrq(result); 9282 jmpb(DONE); 9283 } 9284 9285 bind(VECTOR16_NOT_EQUAL); 9286 if (UseAVX >= 2) { 9287 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9288 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9289 pxor(rymm0, rymm2); 9290 } else { 9291 pcmpeqb(rymm2, rymm2); 9292 pxor(rymm0, rymm1); 9293 pcmpeqb(rymm0, rymm1); 9294 pxor(rymm0, rymm2); 9295 } 9296 pmovmskb(tmp1, rymm0); 9297 bsfq(tmp1, tmp1); 9298 addq(result, tmp1); 9299 shrq(result); 9300 jmpb(DONE); 9301 9302 bind(VECTOR8_NOT_EQUAL); 9303 bind(VECTOR4_NOT_EQUAL); 9304 bsfq(tmp1, tmp1); 9305 shrq(tmp1, 3); 9306 addq(result, tmp1); 9307 bind(BYTES_NOT_EQUAL); 9308 shrq(result); 9309 jmpb(DONE); 9310 9311 bind(SAME_TILL_END); 9312 mov64(result, -1); 9313 9314 bind(DONE); 9315 } 9316 9317 //Helper functions for square_to_len() 9318 9319 /** 9320 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9321 * Preserves x and z and modifies rest of the registers. 9322 */ 9323 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9324 // Perform square and right shift by 1 9325 // Handle odd xlen case first, then for even xlen do the following 9326 // jlong carry = 0; 9327 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9328 // huge_128 product = x[j:j+1] * x[j:j+1]; 9329 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9330 // z[i+2:i+3] = (jlong)(product >>> 1); 9331 // carry = (jlong)product; 9332 // } 9333 9334 xorq(tmp5, tmp5); // carry 9335 xorq(rdxReg, rdxReg); 9336 xorl(tmp1, tmp1); // index for x 9337 xorl(tmp4, tmp4); // index for z 9338 9339 Label L_first_loop, L_first_loop_exit; 9340 9341 testl(xlen, 1); 9342 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9343 9344 // Square and right shift by 1 the odd element using 32 bit multiply 9345 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9346 imulq(raxReg, raxReg); 9347 shrq(raxReg, 1); 9348 adcq(tmp5, 0); 9349 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9350 incrementl(tmp1); 9351 addl(tmp4, 2); 9352 9353 // Square and right shift by 1 the rest using 64 bit multiply 9354 bind(L_first_loop); 9355 cmpptr(tmp1, xlen); 9356 jccb(Assembler::equal, L_first_loop_exit); 9357 9358 // Square 9359 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9360 rorq(raxReg, 32); // convert big-endian to little-endian 9361 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9362 9363 // Right shift by 1 and save carry 9364 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9365 rcrq(rdxReg, 1); 9366 rcrq(raxReg, 1); 9367 adcq(tmp5, 0); 9368 9369 // Store result in z 9370 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9371 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9372 9373 // Update indices for x and z 9374 addl(tmp1, 2); 9375 addl(tmp4, 4); 9376 jmp(L_first_loop); 9377 9378 bind(L_first_loop_exit); 9379 } 9380 9381 9382 /** 9383 * Perform the following multiply add operation using BMI2 instructions 9384 * carry:sum = sum + op1*op2 + carry 9385 * op2 should be in rdx 9386 * op2 is preserved, all other registers are modified 9387 */ 9388 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9389 // assert op2 is rdx 9390 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9391 addq(sum, carry); 9392 adcq(tmp2, 0); 9393 addq(sum, op1); 9394 adcq(tmp2, 0); 9395 movq(carry, tmp2); 9396 } 9397 9398 /** 9399 * Perform the following multiply add operation: 9400 * carry:sum = sum + op1*op2 + carry 9401 * Preserves op1, op2 and modifies rest of registers 9402 */ 9403 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9404 // rdx:rax = op1 * op2 9405 movq(raxReg, op2); 9406 mulq(op1); 9407 9408 // rdx:rax = sum + carry + rdx:rax 9409 addq(sum, carry); 9410 adcq(rdxReg, 0); 9411 addq(sum, raxReg); 9412 adcq(rdxReg, 0); 9413 9414 // carry:sum = rdx:sum 9415 movq(carry, rdxReg); 9416 } 9417 9418 /** 9419 * Add 64 bit long carry into z[] with carry propogation. 9420 * Preserves z and carry register values and modifies rest of registers. 9421 * 9422 */ 9423 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9424 Label L_fourth_loop, L_fourth_loop_exit; 9425 9426 movl(tmp1, 1); 9427 subl(zlen, 2); 9428 addq(Address(z, zlen, Address::times_4, 0), carry); 9429 9430 bind(L_fourth_loop); 9431 jccb(Assembler::carryClear, L_fourth_loop_exit); 9432 subl(zlen, 2); 9433 jccb(Assembler::negative, L_fourth_loop_exit); 9434 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9435 jmp(L_fourth_loop); 9436 bind(L_fourth_loop_exit); 9437 } 9438 9439 /** 9440 * Shift z[] left by 1 bit. 9441 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9442 * 9443 */ 9444 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9445 9446 Label L_fifth_loop, L_fifth_loop_exit; 9447 9448 // Fifth loop 9449 // Perform primitiveLeftShift(z, zlen, 1) 9450 9451 const Register prev_carry = tmp1; 9452 const Register new_carry = tmp4; 9453 const Register value = tmp2; 9454 const Register zidx = tmp3; 9455 9456 // int zidx, carry; 9457 // long value; 9458 // carry = 0; 9459 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9460 // (carry:value) = (z[i] << 1) | carry ; 9461 // z[i] = value; 9462 // } 9463 9464 movl(zidx, zlen); 9465 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9466 9467 bind(L_fifth_loop); 9468 decl(zidx); // Use decl to preserve carry flag 9469 decl(zidx); 9470 jccb(Assembler::negative, L_fifth_loop_exit); 9471 9472 if (UseBMI2Instructions) { 9473 movq(value, Address(z, zidx, Address::times_4, 0)); 9474 rclq(value, 1); 9475 rorxq(value, value, 32); 9476 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9477 } 9478 else { 9479 // clear new_carry 9480 xorl(new_carry, new_carry); 9481 9482 // Shift z[i] by 1, or in previous carry and save new carry 9483 movq(value, Address(z, zidx, Address::times_4, 0)); 9484 shlq(value, 1); 9485 adcl(new_carry, 0); 9486 9487 orq(value, prev_carry); 9488 rorq(value, 0x20); 9489 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9490 9491 // Set previous carry = new carry 9492 movl(prev_carry, new_carry); 9493 } 9494 jmp(L_fifth_loop); 9495 9496 bind(L_fifth_loop_exit); 9497 } 9498 9499 9500 /** 9501 * Code for BigInteger::squareToLen() intrinsic 9502 * 9503 * rdi: x 9504 * rsi: len 9505 * r8: z 9506 * rcx: zlen 9507 * r12: tmp1 9508 * r13: tmp2 9509 * r14: tmp3 9510 * r15: tmp4 9511 * rbx: tmp5 9512 * 9513 */ 9514 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9515 9516 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9517 push(tmp1); 9518 push(tmp2); 9519 push(tmp3); 9520 push(tmp4); 9521 push(tmp5); 9522 9523 // First loop 9524 // Store the squares, right shifted one bit (i.e., divided by 2). 9525 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9526 9527 // Add in off-diagonal sums. 9528 // 9529 // Second, third (nested) and fourth loops. 9530 // zlen +=2; 9531 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9532 // carry = 0; 9533 // long op2 = x[xidx:xidx+1]; 9534 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9535 // k -= 2; 9536 // long op1 = x[j:j+1]; 9537 // long sum = z[k:k+1]; 9538 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9539 // z[k:k+1] = sum; 9540 // } 9541 // add_one_64(z, k, carry, tmp_regs); 9542 // } 9543 9544 const Register carry = tmp5; 9545 const Register sum = tmp3; 9546 const Register op1 = tmp4; 9547 Register op2 = tmp2; 9548 9549 push(zlen); 9550 push(len); 9551 addl(zlen,2); 9552 bind(L_second_loop); 9553 xorq(carry, carry); 9554 subl(zlen, 4); 9555 subl(len, 2); 9556 push(zlen); 9557 push(len); 9558 cmpl(len, 0); 9559 jccb(Assembler::lessEqual, L_second_loop_exit); 9560 9561 // Multiply an array by one 64 bit long. 9562 if (UseBMI2Instructions) { 9563 op2 = rdxReg; 9564 movq(op2, Address(x, len, Address::times_4, 0)); 9565 rorxq(op2, op2, 32); 9566 } 9567 else { 9568 movq(op2, Address(x, len, Address::times_4, 0)); 9569 rorq(op2, 32); 9570 } 9571 9572 bind(L_third_loop); 9573 decrementl(len); 9574 jccb(Assembler::negative, L_third_loop_exit); 9575 decrementl(len); 9576 jccb(Assembler::negative, L_last_x); 9577 9578 movq(op1, Address(x, len, Address::times_4, 0)); 9579 rorq(op1, 32); 9580 9581 bind(L_multiply); 9582 subl(zlen, 2); 9583 movq(sum, Address(z, zlen, Address::times_4, 0)); 9584 9585 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9586 if (UseBMI2Instructions) { 9587 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9588 } 9589 else { 9590 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9591 } 9592 9593 movq(Address(z, zlen, Address::times_4, 0), sum); 9594 9595 jmp(L_third_loop); 9596 bind(L_third_loop_exit); 9597 9598 // Fourth loop 9599 // Add 64 bit long carry into z with carry propogation. 9600 // Uses offsetted zlen. 9601 add_one_64(z, zlen, carry, tmp1); 9602 9603 pop(len); 9604 pop(zlen); 9605 jmp(L_second_loop); 9606 9607 // Next infrequent code is moved outside loops. 9608 bind(L_last_x); 9609 movl(op1, Address(x, 0)); 9610 jmp(L_multiply); 9611 9612 bind(L_second_loop_exit); 9613 pop(len); 9614 pop(zlen); 9615 pop(len); 9616 pop(zlen); 9617 9618 // Fifth loop 9619 // Shift z left 1 bit. 9620 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9621 9622 // z[zlen-1] |= x[len-1] & 1; 9623 movl(tmp3, Address(x, len, Address::times_4, -4)); 9624 andl(tmp3, 1); 9625 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9626 9627 pop(tmp5); 9628 pop(tmp4); 9629 pop(tmp3); 9630 pop(tmp2); 9631 pop(tmp1); 9632 } 9633 9634 /** 9635 * Helper function for mul_add() 9636 * Multiply the in[] by int k and add to out[] starting at offset offs using 9637 * 128 bit by 32 bit multiply and return the carry in tmp5. 9638 * Only quad int aligned length of in[] is operated on in this function. 9639 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9640 * This function preserves out, in and k registers. 9641 * len and offset point to the appropriate index in "in" & "out" correspondingly 9642 * tmp5 has the carry. 9643 * other registers are temporary and are modified. 9644 * 9645 */ 9646 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9647 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9648 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9649 9650 Label L_first_loop, L_first_loop_exit; 9651 9652 movl(tmp1, len); 9653 shrl(tmp1, 2); 9654 9655 bind(L_first_loop); 9656 subl(tmp1, 1); 9657 jccb(Assembler::negative, L_first_loop_exit); 9658 9659 subl(len, 4); 9660 subl(offset, 4); 9661 9662 Register op2 = tmp2; 9663 const Register sum = tmp3; 9664 const Register op1 = tmp4; 9665 const Register carry = tmp5; 9666 9667 if (UseBMI2Instructions) { 9668 op2 = rdxReg; 9669 } 9670 9671 movq(op1, Address(in, len, Address::times_4, 8)); 9672 rorq(op1, 32); 9673 movq(sum, Address(out, offset, Address::times_4, 8)); 9674 rorq(sum, 32); 9675 if (UseBMI2Instructions) { 9676 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9677 } 9678 else { 9679 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9680 } 9681 // Store back in big endian from little endian 9682 rorq(sum, 0x20); 9683 movq(Address(out, offset, Address::times_4, 8), sum); 9684 9685 movq(op1, Address(in, len, Address::times_4, 0)); 9686 rorq(op1, 32); 9687 movq(sum, Address(out, offset, Address::times_4, 0)); 9688 rorq(sum, 32); 9689 if (UseBMI2Instructions) { 9690 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9691 } 9692 else { 9693 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9694 } 9695 // Store back in big endian from little endian 9696 rorq(sum, 0x20); 9697 movq(Address(out, offset, Address::times_4, 0), sum); 9698 9699 jmp(L_first_loop); 9700 bind(L_first_loop_exit); 9701 } 9702 9703 /** 9704 * Code for BigInteger::mulAdd() intrinsic 9705 * 9706 * rdi: out 9707 * rsi: in 9708 * r11: offs (out.length - offset) 9709 * rcx: len 9710 * r8: k 9711 * r12: tmp1 9712 * r13: tmp2 9713 * r14: tmp3 9714 * r15: tmp4 9715 * rbx: tmp5 9716 * Multiply the in[] by word k and add to out[], return the carry in rax 9717 */ 9718 void MacroAssembler::mul_add(Register out, Register in, Register offs, 9719 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 9720 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9721 9722 Label L_carry, L_last_in, L_done; 9723 9724 // carry = 0; 9725 // for (int j=len-1; j >= 0; j--) { 9726 // long product = (in[j] & LONG_MASK) * kLong + 9727 // (out[offs] & LONG_MASK) + carry; 9728 // out[offs--] = (int)product; 9729 // carry = product >>> 32; 9730 // } 9731 // 9732 push(tmp1); 9733 push(tmp2); 9734 push(tmp3); 9735 push(tmp4); 9736 push(tmp5); 9737 9738 Register op2 = tmp2; 9739 const Register sum = tmp3; 9740 const Register op1 = tmp4; 9741 const Register carry = tmp5; 9742 9743 if (UseBMI2Instructions) { 9744 op2 = rdxReg; 9745 movl(op2, k); 9746 } 9747 else { 9748 movl(op2, k); 9749 } 9750 9751 xorq(carry, carry); 9752 9753 //First loop 9754 9755 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 9756 //The carry is in tmp5 9757 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 9758 9759 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 9760 decrementl(len); 9761 jccb(Assembler::negative, L_carry); 9762 decrementl(len); 9763 jccb(Assembler::negative, L_last_in); 9764 9765 movq(op1, Address(in, len, Address::times_4, 0)); 9766 rorq(op1, 32); 9767 9768 subl(offs, 2); 9769 movq(sum, Address(out, offs, Address::times_4, 0)); 9770 rorq(sum, 32); 9771 9772 if (UseBMI2Instructions) { 9773 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9774 } 9775 else { 9776 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9777 } 9778 9779 // Store back in big endian from little endian 9780 rorq(sum, 0x20); 9781 movq(Address(out, offs, Address::times_4, 0), sum); 9782 9783 testl(len, len); 9784 jccb(Assembler::zero, L_carry); 9785 9786 //Multiply the last in[] entry, if any 9787 bind(L_last_in); 9788 movl(op1, Address(in, 0)); 9789 movl(sum, Address(out, offs, Address::times_4, -4)); 9790 9791 movl(raxReg, k); 9792 mull(op1); //tmp4 * eax -> edx:eax 9793 addl(sum, carry); 9794 adcl(rdxReg, 0); 9795 addl(sum, raxReg); 9796 adcl(rdxReg, 0); 9797 movl(carry, rdxReg); 9798 9799 movl(Address(out, offs, Address::times_4, -4), sum); 9800 9801 bind(L_carry); 9802 //return tmp5/carry as carry in rax 9803 movl(rax, carry); 9804 9805 bind(L_done); 9806 pop(tmp5); 9807 pop(tmp4); 9808 pop(tmp3); 9809 pop(tmp2); 9810 pop(tmp1); 9811 } 9812 #endif 9813 9814 /** 9815 * Emits code to update CRC-32 with a byte value according to constants in table 9816 * 9817 * @param [in,out]crc Register containing the crc. 9818 * @param [in]val Register containing the byte to fold into the CRC. 9819 * @param [in]table Register containing the table of crc constants. 9820 * 9821 * uint32_t crc; 9822 * val = crc_table[(val ^ crc) & 0xFF]; 9823 * crc = val ^ (crc >> 8); 9824 * 9825 */ 9826 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 9827 xorl(val, crc); 9828 andl(val, 0xFF); 9829 shrl(crc, 8); // unsigned shift 9830 xorl(crc, Address(table, val, Address::times_4, 0)); 9831 } 9832 9833 /** 9834 * Fold four 128-bit data chunks 9835 */ 9836 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 9837 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64] 9838 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0] 9839 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */); 9840 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */); 9841 } 9842 9843 /** 9844 * Fold 128-bit data chunk 9845 */ 9846 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 9847 if (UseAVX > 0) { 9848 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 9849 vpclmulldq(xcrc, xK, xcrc); // [63:0] 9850 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 9851 pxor(xcrc, xtmp); 9852 } else { 9853 movdqa(xtmp, xcrc); 9854 pclmulhdq(xtmp, xK); // [123:64] 9855 pclmulldq(xcrc, xK); // [63:0] 9856 pxor(xcrc, xtmp); 9857 movdqu(xtmp, Address(buf, offset)); 9858 pxor(xcrc, xtmp); 9859 } 9860 } 9861 9862 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 9863 if (UseAVX > 0) { 9864 vpclmulhdq(xtmp, xK, xcrc); 9865 vpclmulldq(xcrc, xK, xcrc); 9866 pxor(xcrc, xbuf); 9867 pxor(xcrc, xtmp); 9868 } else { 9869 movdqa(xtmp, xcrc); 9870 pclmulhdq(xtmp, xK); 9871 pclmulldq(xcrc, xK); 9872 pxor(xcrc, xbuf); 9873 pxor(xcrc, xtmp); 9874 } 9875 } 9876 9877 /** 9878 * 8-bit folds to compute 32-bit CRC 9879 * 9880 * uint64_t xcrc; 9881 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 9882 */ 9883 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 9884 movdl(tmp, xcrc); 9885 andl(tmp, 0xFF); 9886 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 9887 psrldq(xcrc, 1); // unsigned shift one byte 9888 pxor(xcrc, xtmp); 9889 } 9890 9891 /** 9892 * uint32_t crc; 9893 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 9894 */ 9895 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 9896 movl(tmp, crc); 9897 andl(tmp, 0xFF); 9898 shrl(crc, 8); 9899 xorl(crc, Address(table, tmp, Address::times_4, 0)); 9900 } 9901 9902 /** 9903 * @param crc register containing existing CRC (32-bit) 9904 * @param buf register pointing to input byte buffer (byte*) 9905 * @param len register containing number of bytes 9906 * @param table register that will contain address of CRC table 9907 * @param tmp scratch register 9908 */ 9909 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 9910 assert_different_registers(crc, buf, len, table, tmp, rax); 9911 9912 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 9913 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 9914 9915 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 9916 // context for the registers used, where all instructions below are using 128-bit mode 9917 // On EVEX without VL and BW, these instructions will all be AVX. 9918 if (VM_Version::supports_avx512vlbw()) { 9919 movl(tmp, 0xffff); 9920 kmovwl(k1, tmp); 9921 } 9922 9923 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 9924 notl(crc); // ~crc 9925 cmpl(len, 16); 9926 jcc(Assembler::less, L_tail); 9927 9928 // Align buffer to 16 bytes 9929 movl(tmp, buf); 9930 andl(tmp, 0xF); 9931 jccb(Assembler::zero, L_aligned); 9932 subl(tmp, 16); 9933 addl(len, tmp); 9934 9935 align(4); 9936 BIND(L_align_loop); 9937 movsbl(rax, Address(buf, 0)); // load byte with sign extension 9938 update_byte_crc32(crc, rax, table); 9939 increment(buf); 9940 incrementl(tmp); 9941 jccb(Assembler::less, L_align_loop); 9942 9943 BIND(L_aligned); 9944 movl(tmp, len); // save 9945 shrl(len, 4); 9946 jcc(Assembler::zero, L_tail_restore); 9947 9948 // Fold total 512 bits of polynomial on each iteration 9949 if (VM_Version::supports_vpclmulqdq()) { 9950 Label Parallel_loop, L_No_Parallel; 9951 9952 cmpl(len, 8); 9953 jccb(Assembler::less, L_No_Parallel); 9954 9955 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 9956 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit); 9957 movdl(xmm5, crc); 9958 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit); 9959 addptr(buf, 64); 9960 subl(len, 7); 9961 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits 9962 9963 BIND(Parallel_loop); 9964 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0); 9965 addptr(buf, 64); 9966 subl(len, 4); 9967 jcc(Assembler::greater, Parallel_loop); 9968 9969 vextracti64x2(xmm2, xmm1, 0x01); 9970 vextracti64x2(xmm3, xmm1, 0x02); 9971 vextracti64x2(xmm4, xmm1, 0x03); 9972 jmp(L_fold_512b); 9973 9974 BIND(L_No_Parallel); 9975 } 9976 // Fold crc into first bytes of vector 9977 movdqa(xmm1, Address(buf, 0)); 9978 movdl(rax, xmm1); 9979 xorl(crc, rax); 9980 if (VM_Version::supports_sse4_1()) { 9981 pinsrd(xmm1, crc, 0); 9982 } else { 9983 pinsrw(xmm1, crc, 0); 9984 shrl(crc, 16); 9985 pinsrw(xmm1, crc, 1); 9986 } 9987 addptr(buf, 16); 9988 subl(len, 4); // len > 0 9989 jcc(Assembler::less, L_fold_tail); 9990 9991 movdqa(xmm2, Address(buf, 0)); 9992 movdqa(xmm3, Address(buf, 16)); 9993 movdqa(xmm4, Address(buf, 32)); 9994 addptr(buf, 48); 9995 subl(len, 3); 9996 jcc(Assembler::lessEqual, L_fold_512b); 9997 9998 // Fold total 512 bits of polynomial on each iteration, 9999 // 128 bits per each of 4 parallel streams. 10000 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10001 10002 align(32); 10003 BIND(L_fold_512b_loop); 10004 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10005 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10006 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10007 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10008 addptr(buf, 64); 10009 subl(len, 4); 10010 jcc(Assembler::greater, L_fold_512b_loop); 10011 10012 // Fold 512 bits to 128 bits. 10013 BIND(L_fold_512b); 10014 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10015 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10016 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10017 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10018 10019 // Fold the rest of 128 bits data chunks 10020 BIND(L_fold_tail); 10021 addl(len, 3); 10022 jccb(Assembler::lessEqual, L_fold_128b); 10023 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10024 10025 BIND(L_fold_tail_loop); 10026 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10027 addptr(buf, 16); 10028 decrementl(len); 10029 jccb(Assembler::greater, L_fold_tail_loop); 10030 10031 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10032 BIND(L_fold_128b); 10033 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10034 if (UseAVX > 0) { 10035 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10036 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10037 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10038 } else { 10039 movdqa(xmm2, xmm0); 10040 pclmulqdq(xmm2, xmm1, 0x1); 10041 movdqa(xmm3, xmm0); 10042 pand(xmm3, xmm2); 10043 pclmulqdq(xmm0, xmm3, 0x1); 10044 } 10045 psrldq(xmm1, 8); 10046 psrldq(xmm2, 4); 10047 pxor(xmm0, xmm1); 10048 pxor(xmm0, xmm2); 10049 10050 // 8 8-bit folds to compute 32-bit CRC. 10051 for (int j = 0; j < 4; j++) { 10052 fold_8bit_crc32(xmm0, table, xmm1, rax); 10053 } 10054 movdl(crc, xmm0); // mov 32 bits to general register 10055 for (int j = 0; j < 4; j++) { 10056 fold_8bit_crc32(crc, table, rax); 10057 } 10058 10059 BIND(L_tail_restore); 10060 movl(len, tmp); // restore 10061 BIND(L_tail); 10062 andl(len, 0xf); 10063 jccb(Assembler::zero, L_exit); 10064 10065 // Fold the rest of bytes 10066 align(4); 10067 BIND(L_tail_loop); 10068 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10069 update_byte_crc32(crc, rax, table); 10070 increment(buf); 10071 decrementl(len); 10072 jccb(Assembler::greater, L_tail_loop); 10073 10074 BIND(L_exit); 10075 notl(crc); // ~c 10076 } 10077 10078 #ifdef _LP64 10079 // S. Gueron / Information Processing Letters 112 (2012) 184 10080 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10081 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10082 // Output: the 64-bit carry-less product of B * CONST 10083 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10084 Register tmp1, Register tmp2, Register tmp3) { 10085 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10086 if (n > 0) { 10087 addq(tmp3, n * 256 * 8); 10088 } 10089 // Q1 = TABLEExt[n][B & 0xFF]; 10090 movl(tmp1, in); 10091 andl(tmp1, 0x000000FF); 10092 shll(tmp1, 3); 10093 addq(tmp1, tmp3); 10094 movq(tmp1, Address(tmp1, 0)); 10095 10096 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10097 movl(tmp2, in); 10098 shrl(tmp2, 8); 10099 andl(tmp2, 0x000000FF); 10100 shll(tmp2, 3); 10101 addq(tmp2, tmp3); 10102 movq(tmp2, Address(tmp2, 0)); 10103 10104 shlq(tmp2, 8); 10105 xorq(tmp1, tmp2); 10106 10107 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10108 movl(tmp2, in); 10109 shrl(tmp2, 16); 10110 andl(tmp2, 0x000000FF); 10111 shll(tmp2, 3); 10112 addq(tmp2, tmp3); 10113 movq(tmp2, Address(tmp2, 0)); 10114 10115 shlq(tmp2, 16); 10116 xorq(tmp1, tmp2); 10117 10118 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10119 shrl(in, 24); 10120 andl(in, 0x000000FF); 10121 shll(in, 3); 10122 addq(in, tmp3); 10123 movq(in, Address(in, 0)); 10124 10125 shlq(in, 24); 10126 xorq(in, tmp1); 10127 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10128 } 10129 10130 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10131 Register in_out, 10132 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10133 XMMRegister w_xtmp2, 10134 Register tmp1, 10135 Register n_tmp2, Register n_tmp3) { 10136 if (is_pclmulqdq_supported) { 10137 movdl(w_xtmp1, in_out); // modified blindly 10138 10139 movl(tmp1, const_or_pre_comp_const_index); 10140 movdl(w_xtmp2, tmp1); 10141 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10142 10143 movdq(in_out, w_xtmp1); 10144 } else { 10145 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10146 } 10147 } 10148 10149 // Recombination Alternative 2: No bit-reflections 10150 // T1 = (CRC_A * U1) << 1 10151 // T2 = (CRC_B * U2) << 1 10152 // C1 = T1 >> 32 10153 // C2 = T2 >> 32 10154 // T1 = T1 & 0xFFFFFFFF 10155 // T2 = T2 & 0xFFFFFFFF 10156 // T1 = CRC32(0, T1) 10157 // T2 = CRC32(0, T2) 10158 // C1 = C1 ^ T1 10159 // C2 = C2 ^ T2 10160 // CRC = C1 ^ C2 ^ CRC_C 10161 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10162 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10163 Register tmp1, Register tmp2, 10164 Register n_tmp3) { 10165 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10166 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10167 shlq(in_out, 1); 10168 movl(tmp1, in_out); 10169 shrq(in_out, 32); 10170 xorl(tmp2, tmp2); 10171 crc32(tmp2, tmp1, 4); 10172 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10173 shlq(in1, 1); 10174 movl(tmp1, in1); 10175 shrq(in1, 32); 10176 xorl(tmp2, tmp2); 10177 crc32(tmp2, tmp1, 4); 10178 xorl(in1, tmp2); 10179 xorl(in_out, in1); 10180 xorl(in_out, in2); 10181 } 10182 10183 // Set N to predefined value 10184 // Subtract from a lenght of a buffer 10185 // execute in a loop: 10186 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10187 // for i = 1 to N do 10188 // CRC_A = CRC32(CRC_A, A[i]) 10189 // CRC_B = CRC32(CRC_B, B[i]) 10190 // CRC_C = CRC32(CRC_C, C[i]) 10191 // end for 10192 // Recombine 10193 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10194 Register in_out1, Register in_out2, Register in_out3, 10195 Register tmp1, Register tmp2, Register tmp3, 10196 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10197 Register tmp4, Register tmp5, 10198 Register n_tmp6) { 10199 Label L_processPartitions; 10200 Label L_processPartition; 10201 Label L_exit; 10202 10203 bind(L_processPartitions); 10204 cmpl(in_out1, 3 * size); 10205 jcc(Assembler::less, L_exit); 10206 xorl(tmp1, tmp1); 10207 xorl(tmp2, tmp2); 10208 movq(tmp3, in_out2); 10209 addq(tmp3, size); 10210 10211 bind(L_processPartition); 10212 crc32(in_out3, Address(in_out2, 0), 8); 10213 crc32(tmp1, Address(in_out2, size), 8); 10214 crc32(tmp2, Address(in_out2, size * 2), 8); 10215 addq(in_out2, 8); 10216 cmpq(in_out2, tmp3); 10217 jcc(Assembler::less, L_processPartition); 10218 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10219 w_xtmp1, w_xtmp2, w_xtmp3, 10220 tmp4, tmp5, 10221 n_tmp6); 10222 addq(in_out2, 2 * size); 10223 subl(in_out1, 3 * size); 10224 jmp(L_processPartitions); 10225 10226 bind(L_exit); 10227 } 10228 #else 10229 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10230 Register tmp1, Register tmp2, Register tmp3, 10231 XMMRegister xtmp1, XMMRegister xtmp2) { 10232 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10233 if (n > 0) { 10234 addl(tmp3, n * 256 * 8); 10235 } 10236 // Q1 = TABLEExt[n][B & 0xFF]; 10237 movl(tmp1, in_out); 10238 andl(tmp1, 0x000000FF); 10239 shll(tmp1, 3); 10240 addl(tmp1, tmp3); 10241 movq(xtmp1, Address(tmp1, 0)); 10242 10243 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10244 movl(tmp2, in_out); 10245 shrl(tmp2, 8); 10246 andl(tmp2, 0x000000FF); 10247 shll(tmp2, 3); 10248 addl(tmp2, tmp3); 10249 movq(xtmp2, Address(tmp2, 0)); 10250 10251 psllq(xtmp2, 8); 10252 pxor(xtmp1, xtmp2); 10253 10254 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10255 movl(tmp2, in_out); 10256 shrl(tmp2, 16); 10257 andl(tmp2, 0x000000FF); 10258 shll(tmp2, 3); 10259 addl(tmp2, tmp3); 10260 movq(xtmp2, Address(tmp2, 0)); 10261 10262 psllq(xtmp2, 16); 10263 pxor(xtmp1, xtmp2); 10264 10265 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10266 shrl(in_out, 24); 10267 andl(in_out, 0x000000FF); 10268 shll(in_out, 3); 10269 addl(in_out, tmp3); 10270 movq(xtmp2, Address(in_out, 0)); 10271 10272 psllq(xtmp2, 24); 10273 pxor(xtmp1, xtmp2); // Result in CXMM 10274 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10275 } 10276 10277 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10278 Register in_out, 10279 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10280 XMMRegister w_xtmp2, 10281 Register tmp1, 10282 Register n_tmp2, Register n_tmp3) { 10283 if (is_pclmulqdq_supported) { 10284 movdl(w_xtmp1, in_out); 10285 10286 movl(tmp1, const_or_pre_comp_const_index); 10287 movdl(w_xtmp2, tmp1); 10288 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10289 // Keep result in XMM since GPR is 32 bit in length 10290 } else { 10291 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10292 } 10293 } 10294 10295 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10296 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10297 Register tmp1, Register tmp2, 10298 Register n_tmp3) { 10299 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10300 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10301 10302 psllq(w_xtmp1, 1); 10303 movdl(tmp1, w_xtmp1); 10304 psrlq(w_xtmp1, 32); 10305 movdl(in_out, w_xtmp1); 10306 10307 xorl(tmp2, tmp2); 10308 crc32(tmp2, tmp1, 4); 10309 xorl(in_out, tmp2); 10310 10311 psllq(w_xtmp2, 1); 10312 movdl(tmp1, w_xtmp2); 10313 psrlq(w_xtmp2, 32); 10314 movdl(in1, w_xtmp2); 10315 10316 xorl(tmp2, tmp2); 10317 crc32(tmp2, tmp1, 4); 10318 xorl(in1, tmp2); 10319 xorl(in_out, in1); 10320 xorl(in_out, in2); 10321 } 10322 10323 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10324 Register in_out1, Register in_out2, Register in_out3, 10325 Register tmp1, Register tmp2, Register tmp3, 10326 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10327 Register tmp4, Register tmp5, 10328 Register n_tmp6) { 10329 Label L_processPartitions; 10330 Label L_processPartition; 10331 Label L_exit; 10332 10333 bind(L_processPartitions); 10334 cmpl(in_out1, 3 * size); 10335 jcc(Assembler::less, L_exit); 10336 xorl(tmp1, tmp1); 10337 xorl(tmp2, tmp2); 10338 movl(tmp3, in_out2); 10339 addl(tmp3, size); 10340 10341 bind(L_processPartition); 10342 crc32(in_out3, Address(in_out2, 0), 4); 10343 crc32(tmp1, Address(in_out2, size), 4); 10344 crc32(tmp2, Address(in_out2, size*2), 4); 10345 crc32(in_out3, Address(in_out2, 0+4), 4); 10346 crc32(tmp1, Address(in_out2, size+4), 4); 10347 crc32(tmp2, Address(in_out2, size*2+4), 4); 10348 addl(in_out2, 8); 10349 cmpl(in_out2, tmp3); 10350 jcc(Assembler::less, L_processPartition); 10351 10352 push(tmp3); 10353 push(in_out1); 10354 push(in_out2); 10355 tmp4 = tmp3; 10356 tmp5 = in_out1; 10357 n_tmp6 = in_out2; 10358 10359 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10360 w_xtmp1, w_xtmp2, w_xtmp3, 10361 tmp4, tmp5, 10362 n_tmp6); 10363 10364 pop(in_out2); 10365 pop(in_out1); 10366 pop(tmp3); 10367 10368 addl(in_out2, 2 * size); 10369 subl(in_out1, 3 * size); 10370 jmp(L_processPartitions); 10371 10372 bind(L_exit); 10373 } 10374 #endif //LP64 10375 10376 #ifdef _LP64 10377 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10378 // Input: A buffer I of L bytes. 10379 // Output: the CRC32C value of the buffer. 10380 // Notations: 10381 // Write L = 24N + r, with N = floor (L/24). 10382 // r = L mod 24 (0 <= r < 24). 10383 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10384 // N quadwords, and R consists of r bytes. 10385 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10386 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10387 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10388 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10389 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10390 Register tmp1, Register tmp2, Register tmp3, 10391 Register tmp4, Register tmp5, Register tmp6, 10392 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10393 bool is_pclmulqdq_supported) { 10394 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10395 Label L_wordByWord; 10396 Label L_byteByByteProlog; 10397 Label L_byteByByte; 10398 Label L_exit; 10399 10400 if (is_pclmulqdq_supported ) { 10401 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10402 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10403 10404 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10405 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10406 10407 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10408 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10409 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10410 } else { 10411 const_or_pre_comp_const_index[0] = 1; 10412 const_or_pre_comp_const_index[1] = 0; 10413 10414 const_or_pre_comp_const_index[2] = 3; 10415 const_or_pre_comp_const_index[3] = 2; 10416 10417 const_or_pre_comp_const_index[4] = 5; 10418 const_or_pre_comp_const_index[5] = 4; 10419 } 10420 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10421 in2, in1, in_out, 10422 tmp1, tmp2, tmp3, 10423 w_xtmp1, w_xtmp2, w_xtmp3, 10424 tmp4, tmp5, 10425 tmp6); 10426 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10427 in2, in1, in_out, 10428 tmp1, tmp2, tmp3, 10429 w_xtmp1, w_xtmp2, w_xtmp3, 10430 tmp4, tmp5, 10431 tmp6); 10432 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10433 in2, in1, in_out, 10434 tmp1, tmp2, tmp3, 10435 w_xtmp1, w_xtmp2, w_xtmp3, 10436 tmp4, tmp5, 10437 tmp6); 10438 movl(tmp1, in2); 10439 andl(tmp1, 0x00000007); 10440 negl(tmp1); 10441 addl(tmp1, in2); 10442 addq(tmp1, in1); 10443 10444 BIND(L_wordByWord); 10445 cmpq(in1, tmp1); 10446 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10447 crc32(in_out, Address(in1, 0), 4); 10448 addq(in1, 4); 10449 jmp(L_wordByWord); 10450 10451 BIND(L_byteByByteProlog); 10452 andl(in2, 0x00000007); 10453 movl(tmp2, 1); 10454 10455 BIND(L_byteByByte); 10456 cmpl(tmp2, in2); 10457 jccb(Assembler::greater, L_exit); 10458 crc32(in_out, Address(in1, 0), 1); 10459 incq(in1); 10460 incl(tmp2); 10461 jmp(L_byteByByte); 10462 10463 BIND(L_exit); 10464 } 10465 #else 10466 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10467 Register tmp1, Register tmp2, Register tmp3, 10468 Register tmp4, Register tmp5, Register tmp6, 10469 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10470 bool is_pclmulqdq_supported) { 10471 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10472 Label L_wordByWord; 10473 Label L_byteByByteProlog; 10474 Label L_byteByByte; 10475 Label L_exit; 10476 10477 if (is_pclmulqdq_supported) { 10478 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10479 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10480 10481 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10482 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10483 10484 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10485 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10486 } else { 10487 const_or_pre_comp_const_index[0] = 1; 10488 const_or_pre_comp_const_index[1] = 0; 10489 10490 const_or_pre_comp_const_index[2] = 3; 10491 const_or_pre_comp_const_index[3] = 2; 10492 10493 const_or_pre_comp_const_index[4] = 5; 10494 const_or_pre_comp_const_index[5] = 4; 10495 } 10496 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10497 in2, in1, in_out, 10498 tmp1, tmp2, tmp3, 10499 w_xtmp1, w_xtmp2, w_xtmp3, 10500 tmp4, tmp5, 10501 tmp6); 10502 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10503 in2, in1, in_out, 10504 tmp1, tmp2, tmp3, 10505 w_xtmp1, w_xtmp2, w_xtmp3, 10506 tmp4, tmp5, 10507 tmp6); 10508 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10509 in2, in1, in_out, 10510 tmp1, tmp2, tmp3, 10511 w_xtmp1, w_xtmp2, w_xtmp3, 10512 tmp4, tmp5, 10513 tmp6); 10514 movl(tmp1, in2); 10515 andl(tmp1, 0x00000007); 10516 negl(tmp1); 10517 addl(tmp1, in2); 10518 addl(tmp1, in1); 10519 10520 BIND(L_wordByWord); 10521 cmpl(in1, tmp1); 10522 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10523 crc32(in_out, Address(in1,0), 4); 10524 addl(in1, 4); 10525 jmp(L_wordByWord); 10526 10527 BIND(L_byteByByteProlog); 10528 andl(in2, 0x00000007); 10529 movl(tmp2, 1); 10530 10531 BIND(L_byteByByte); 10532 cmpl(tmp2, in2); 10533 jccb(Assembler::greater, L_exit); 10534 movb(tmp1, Address(in1, 0)); 10535 crc32(in_out, tmp1, 1); 10536 incl(in1); 10537 incl(tmp2); 10538 jmp(L_byteByByte); 10539 10540 BIND(L_exit); 10541 } 10542 #endif // LP64 10543 #undef BIND 10544 #undef BLOCK_COMMENT 10545 10546 // Compress char[] array to byte[]. 10547 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10548 // @HotSpotIntrinsicCandidate 10549 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10550 // for (int i = 0; i < len; i++) { 10551 // int c = src[srcOff++]; 10552 // if (c >>> 8 != 0) { 10553 // return 0; 10554 // } 10555 // dst[dstOff++] = (byte)c; 10556 // } 10557 // return len; 10558 // } 10559 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10560 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10561 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10562 Register tmp5, Register result) { 10563 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10564 10565 // rsi: src 10566 // rdi: dst 10567 // rdx: len 10568 // rcx: tmp5 10569 // rax: result 10570 10571 // rsi holds start addr of source char[] to be compressed 10572 // rdi holds start addr of destination byte[] 10573 // rdx holds length 10574 10575 assert(len != result, ""); 10576 10577 // save length for return 10578 push(len); 10579 10580 if ((UseAVX > 2) && // AVX512 10581 VM_Version::supports_avx512vlbw() && 10582 VM_Version::supports_bmi2()) { 10583 10584 set_vector_masking(); // opening of the stub context for programming mask registers 10585 10586 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero; 10587 10588 // alignement 10589 Label post_alignement; 10590 10591 // if length of the string is less than 16, handle it in an old fashioned 10592 // way 10593 testl(len, -32); 10594 jcc(Assembler::zero, below_threshold); 10595 10596 // First check whether a character is compressable ( <= 0xFF). 10597 // Create mask to test for Unicode chars inside zmm vector 10598 movl(result, 0x00FF); 10599 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10600 10601 // Save k1 10602 kmovql(k3, k1); 10603 10604 testl(len, -64); 10605 jcc(Assembler::zero, post_alignement); 10606 10607 movl(tmp5, dst); 10608 andl(tmp5, (32 - 1)); 10609 negl(tmp5); 10610 andl(tmp5, (32 - 1)); 10611 10612 // bail out when there is nothing to be done 10613 testl(tmp5, 0xFFFFFFFF); 10614 jcc(Assembler::zero, post_alignement); 10615 10616 // ~(~0 << len), where len is the # of remaining elements to process 10617 movl(result, 0xFFFFFFFF); 10618 shlxl(result, result, tmp5); 10619 notl(result); 10620 kmovdl(k1, result); 10621 10622 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10623 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10624 ktestd(k2, k1); 10625 jcc(Assembler::carryClear, restore_k1_return_zero); 10626 10627 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10628 10629 addptr(src, tmp5); 10630 addptr(src, tmp5); 10631 addptr(dst, tmp5); 10632 subl(len, tmp5); 10633 10634 bind(post_alignement); 10635 // end of alignement 10636 10637 movl(tmp5, len); 10638 andl(tmp5, (32 - 1)); // tail count (in chars) 10639 andl(len, ~(32 - 1)); // vector count (in chars) 10640 jcc(Assembler::zero, copy_loop_tail); 10641 10642 lea(src, Address(src, len, Address::times_2)); 10643 lea(dst, Address(dst, len, Address::times_1)); 10644 negptr(len); 10645 10646 bind(copy_32_loop); 10647 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10648 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10649 kortestdl(k2, k2); 10650 jcc(Assembler::carryClear, restore_k1_return_zero); 10651 10652 // All elements in current processed chunk are valid candidates for 10653 // compression. Write a truncated byte elements to the memory. 10654 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10655 addptr(len, 32); 10656 jcc(Assembler::notZero, copy_32_loop); 10657 10658 bind(copy_loop_tail); 10659 // bail out when there is nothing to be done 10660 testl(tmp5, 0xFFFFFFFF); 10661 // Restore k1 10662 kmovql(k1, k3); 10663 jcc(Assembler::zero, return_length); 10664 10665 movl(len, tmp5); 10666 10667 // ~(~0 << len), where len is the # of remaining elements to process 10668 movl(result, 0xFFFFFFFF); 10669 shlxl(result, result, len); 10670 notl(result); 10671 10672 kmovdl(k1, result); 10673 10674 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10675 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10676 ktestd(k2, k1); 10677 jcc(Assembler::carryClear, restore_k1_return_zero); 10678 10679 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10680 // Restore k1 10681 kmovql(k1, k3); 10682 jmp(return_length); 10683 10684 bind(restore_k1_return_zero); 10685 // Restore k1 10686 kmovql(k1, k3); 10687 jmp(return_zero); 10688 10689 clear_vector_masking(); // closing of the stub context for programming mask registers 10690 } 10691 if (UseSSE42Intrinsics) { 10692 Label copy_32_loop, copy_16, copy_tail; 10693 10694 bind(below_threshold); 10695 10696 movl(result, len); 10697 10698 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10699 10700 // vectored compression 10701 andl(len, 0xfffffff0); // vector count (in chars) 10702 andl(result, 0x0000000f); // tail count (in chars) 10703 testl(len, len); 10704 jccb(Assembler::zero, copy_16); 10705 10706 // compress 16 chars per iter 10707 movdl(tmp1Reg, tmp5); 10708 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10709 pxor(tmp4Reg, tmp4Reg); 10710 10711 lea(src, Address(src, len, Address::times_2)); 10712 lea(dst, Address(dst, len, Address::times_1)); 10713 negptr(len); 10714 10715 bind(copy_32_loop); 10716 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 10717 por(tmp4Reg, tmp2Reg); 10718 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 10719 por(tmp4Reg, tmp3Reg); 10720 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 10721 jcc(Assembler::notZero, return_zero); 10722 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 10723 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 10724 addptr(len, 16); 10725 jcc(Assembler::notZero, copy_32_loop); 10726 10727 // compress next vector of 8 chars (if any) 10728 bind(copy_16); 10729 movl(len, result); 10730 andl(len, 0xfffffff8); // vector count (in chars) 10731 andl(result, 0x00000007); // tail count (in chars) 10732 testl(len, len); 10733 jccb(Assembler::zero, copy_tail); 10734 10735 movdl(tmp1Reg, tmp5); 10736 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10737 pxor(tmp3Reg, tmp3Reg); 10738 10739 movdqu(tmp2Reg, Address(src, 0)); 10740 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 10741 jccb(Assembler::notZero, return_zero); 10742 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 10743 movq(Address(dst, 0), tmp2Reg); 10744 addptr(src, 16); 10745 addptr(dst, 8); 10746 10747 bind(copy_tail); 10748 movl(len, result); 10749 } 10750 // compress 1 char per iter 10751 testl(len, len); 10752 jccb(Assembler::zero, return_length); 10753 lea(src, Address(src, len, Address::times_2)); 10754 lea(dst, Address(dst, len, Address::times_1)); 10755 negptr(len); 10756 10757 bind(copy_chars_loop); 10758 load_unsigned_short(result, Address(src, len, Address::times_2)); 10759 testl(result, 0xff00); // check if Unicode char 10760 jccb(Assembler::notZero, return_zero); 10761 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 10762 increment(len); 10763 jcc(Assembler::notZero, copy_chars_loop); 10764 10765 // if compression succeeded, return length 10766 bind(return_length); 10767 pop(result); 10768 jmpb(done); 10769 10770 // if compression failed, return 0 10771 bind(return_zero); 10772 xorl(result, result); 10773 addptr(rsp, wordSize); 10774 10775 bind(done); 10776 } 10777 10778 // Inflate byte[] array to char[]. 10779 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 10780 // @HotSpotIntrinsicCandidate 10781 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 10782 // for (int i = 0; i < len; i++) { 10783 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 10784 // } 10785 // } 10786 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 10787 XMMRegister tmp1, Register tmp2) { 10788 Label copy_chars_loop, done, below_threshold; 10789 // rsi: src 10790 // rdi: dst 10791 // rdx: len 10792 // rcx: tmp2 10793 10794 // rsi holds start addr of source byte[] to be inflated 10795 // rdi holds start addr of destination char[] 10796 // rdx holds length 10797 assert_different_registers(src, dst, len, tmp2); 10798 10799 if ((UseAVX > 2) && // AVX512 10800 VM_Version::supports_avx512vlbw() && 10801 VM_Version::supports_bmi2()) { 10802 10803 set_vector_masking(); // opening of the stub context for programming mask registers 10804 10805 Label copy_32_loop, copy_tail; 10806 Register tmp3_aliased = len; 10807 10808 // if length of the string is less than 16, handle it in an old fashioned 10809 // way 10810 testl(len, -16); 10811 jcc(Assembler::zero, below_threshold); 10812 10813 // In order to use only one arithmetic operation for the main loop we use 10814 // this pre-calculation 10815 movl(tmp2, len); 10816 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 10817 andl(len, -32); // vector count 10818 jccb(Assembler::zero, copy_tail); 10819 10820 lea(src, Address(src, len, Address::times_1)); 10821 lea(dst, Address(dst, len, Address::times_2)); 10822 negptr(len); 10823 10824 10825 // inflate 32 chars per iter 10826 bind(copy_32_loop); 10827 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 10828 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 10829 addptr(len, 32); 10830 jcc(Assembler::notZero, copy_32_loop); 10831 10832 bind(copy_tail); 10833 // bail out when there is nothing to be done 10834 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 10835 jcc(Assembler::zero, done); 10836 10837 // Save k1 10838 kmovql(k2, k1); 10839 10840 // ~(~0 << length), where length is the # of remaining elements to process 10841 movl(tmp3_aliased, -1); 10842 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 10843 notl(tmp3_aliased); 10844 kmovdl(k1, tmp3_aliased); 10845 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 10846 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 10847 10848 // Restore k1 10849 kmovql(k1, k2); 10850 jmp(done); 10851 10852 clear_vector_masking(); // closing of the stub context for programming mask registers 10853 } 10854 if (UseSSE42Intrinsics) { 10855 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 10856 10857 movl(tmp2, len); 10858 10859 if (UseAVX > 1) { 10860 andl(tmp2, (16 - 1)); 10861 andl(len, -16); 10862 jccb(Assembler::zero, copy_new_tail); 10863 } else { 10864 andl(tmp2, 0x00000007); // tail count (in chars) 10865 andl(len, 0xfffffff8); // vector count (in chars) 10866 jccb(Assembler::zero, copy_tail); 10867 } 10868 10869 // vectored inflation 10870 lea(src, Address(src, len, Address::times_1)); 10871 lea(dst, Address(dst, len, Address::times_2)); 10872 negptr(len); 10873 10874 if (UseAVX > 1) { 10875 bind(copy_16_loop); 10876 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 10877 vmovdqu(Address(dst, len, Address::times_2), tmp1); 10878 addptr(len, 16); 10879 jcc(Assembler::notZero, copy_16_loop); 10880 10881 bind(below_threshold); 10882 bind(copy_new_tail); 10883 if ((UseAVX > 2) && 10884 VM_Version::supports_avx512vlbw() && 10885 VM_Version::supports_bmi2()) { 10886 movl(tmp2, len); 10887 } else { 10888 movl(len, tmp2); 10889 } 10890 andl(tmp2, 0x00000007); 10891 andl(len, 0xFFFFFFF8); 10892 jccb(Assembler::zero, copy_tail); 10893 10894 pmovzxbw(tmp1, Address(src, 0)); 10895 movdqu(Address(dst, 0), tmp1); 10896 addptr(src, 8); 10897 addptr(dst, 2 * 8); 10898 10899 jmp(copy_tail, true); 10900 } 10901 10902 // inflate 8 chars per iter 10903 bind(copy_8_loop); 10904 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 10905 movdqu(Address(dst, len, Address::times_2), tmp1); 10906 addptr(len, 8); 10907 jcc(Assembler::notZero, copy_8_loop); 10908 10909 bind(copy_tail); 10910 movl(len, tmp2); 10911 10912 cmpl(len, 4); 10913 jccb(Assembler::less, copy_bytes); 10914 10915 movdl(tmp1, Address(src, 0)); // load 4 byte chars 10916 pmovzxbw(tmp1, tmp1); 10917 movq(Address(dst, 0), tmp1); 10918 subptr(len, 4); 10919 addptr(src, 4); 10920 addptr(dst, 8); 10921 10922 bind(copy_bytes); 10923 } 10924 testl(len, len); 10925 jccb(Assembler::zero, done); 10926 lea(src, Address(src, len, Address::times_1)); 10927 lea(dst, Address(dst, len, Address::times_2)); 10928 negptr(len); 10929 10930 // inflate 1 char per iter 10931 bind(copy_chars_loop); 10932 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 10933 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 10934 increment(len); 10935 jcc(Assembler::notZero, copy_chars_loop); 10936 10937 bind(done); 10938 } 10939 10940 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 10941 switch (cond) { 10942 // Note some conditions are synonyms for others 10943 case Assembler::zero: return Assembler::notZero; 10944 case Assembler::notZero: return Assembler::zero; 10945 case Assembler::less: return Assembler::greaterEqual; 10946 case Assembler::lessEqual: return Assembler::greater; 10947 case Assembler::greater: return Assembler::lessEqual; 10948 case Assembler::greaterEqual: return Assembler::less; 10949 case Assembler::below: return Assembler::aboveEqual; 10950 case Assembler::belowEqual: return Assembler::above; 10951 case Assembler::above: return Assembler::belowEqual; 10952 case Assembler::aboveEqual: return Assembler::below; 10953 case Assembler::overflow: return Assembler::noOverflow; 10954 case Assembler::noOverflow: return Assembler::overflow; 10955 case Assembler::negative: return Assembler::positive; 10956 case Assembler::positive: return Assembler::negative; 10957 case Assembler::parity: return Assembler::noParity; 10958 case Assembler::noParity: return Assembler::parity; 10959 } 10960 ShouldNotReachHere(); return Assembler::overflow; 10961 } 10962 10963 SkipIfEqual::SkipIfEqual( 10964 MacroAssembler* masm, const bool* flag_addr, bool value) { 10965 _masm = masm; 10966 _masm->cmp8(ExternalAddress((address)flag_addr), value); 10967 _masm->jcc(Assembler::equal, _label); 10968 } 10969 10970 SkipIfEqual::~SkipIfEqual() { 10971 _masm->bind(_label); 10972 } 10973 10974 // 32-bit Windows has its own fast-path implementation 10975 // of get_thread 10976 #if !defined(WIN32) || defined(_LP64) 10977 10978 // This is simply a call to Thread::current() 10979 void MacroAssembler::get_thread(Register thread) { 10980 if (thread != rax) { 10981 push(rax); 10982 } 10983 LP64_ONLY(push(rdi);) 10984 LP64_ONLY(push(rsi);) 10985 push(rdx); 10986 push(rcx); 10987 #ifdef _LP64 10988 push(r8); 10989 push(r9); 10990 push(r10); 10991 push(r11); 10992 #endif 10993 10994 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 10995 10996 #ifdef _LP64 10997 pop(r11); 10998 pop(r10); 10999 pop(r9); 11000 pop(r8); 11001 #endif 11002 pop(rcx); 11003 pop(rdx); 11004 LP64_ONLY(pop(rsi);) 11005 LP64_ONLY(pop(rdi);) 11006 if (thread != rax) { 11007 mov(thread, rax); 11008 pop(rax); 11009 } 11010 } 11011 11012 #endif