1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // jobjects
297 void clear_jweak_tag(Register possibly_jweak);
298 void resolve_jobject(Register value, Register thread, Register tmp);
299
300 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
301 void c2bool(Register x);
302
303 // C++ bool manipulation
304
305 void movbool(Register dst, Address src);
306 void movbool(Address dst, bool boolconst);
307 void movbool(Address dst, Register src);
308 void testbool(Register dst);
309
310 void resolve_oop_handle(Register result, Register tmp = rscratch2);
311 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
312
313 // oop manipulations
314 void load_klass(Register dst, Register src);
315 void store_klass(Register dst, Register src);
316
317 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
318 Register tmp1, Register thread_tmp);
319 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
320 Register tmp1, Register tmp2);
321
322 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
323 Register thread_tmp = noreg, DecoratorSet decorators = 0);
324 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
325 Register thread_tmp = noreg, DecoratorSet decorators = 0);
326 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
327 Register tmp2 = noreg, DecoratorSet decorators = 0);
328
329 // Used for storing NULL. All other oop constants should be
330 // stored using routines that take a jobject.
331 void store_heap_oop_null(Address dst);
332
333 void load_prototype_header(Register dst, Register src);
334
335 #ifdef _LP64
336 void store_klass_gap(Register dst, Register src);
337
338 // This dummy is to prevent a call to store_heap_oop from
339 // converting a zero (like NULL) into a Register by giving
340 // the compiler two choices it can't resolve
341
342 void store_heap_oop(Address dst, void* dummy);
343
344 void encode_heap_oop(Register r);
345 void decode_heap_oop(Register r);
346 void encode_heap_oop_not_null(Register r);
347 void decode_heap_oop_not_null(Register r);
348 void encode_heap_oop_not_null(Register dst, Register src);
349 void decode_heap_oop_not_null(Register dst, Register src);
350
351 void set_narrow_oop(Register dst, jobject obj);
352 void set_narrow_oop(Address dst, jobject obj);
353 void cmp_narrow_oop(Register dst, jobject obj);
354 void cmp_narrow_oop(Address dst, jobject obj);
355
356 void encode_klass_not_null(Register r);
357 void decode_klass_not_null(Register r);
358 void encode_klass_not_null(Register dst, Register src);
359 void decode_klass_not_null(Register dst, Register src);
360 void set_narrow_klass(Register dst, Klass* k);
361 void set_narrow_klass(Address dst, Klass* k);
362 void cmp_narrow_klass(Register dst, Klass* k);
363 void cmp_narrow_klass(Address dst, Klass* k);
364
365 // Returns the byte size of the instructions generated by decode_klass_not_null()
366 // when compressed klass pointers are being used.
367 static int instr_size_for_decode_klass_not_null();
368
369 // if heap base register is used - reinit it with the correct value
370 void reinit_heapbase();
371
372 DEBUG_ONLY(void verify_heapbase(const char* msg);)
373
374 #endif // _LP64
375
376 // Int division/remainder for Java
377 // (as idivl, but checks for special case as described in JVM spec.)
378 // returns idivl instruction offset for implicit exception handling
379 int corrected_idivl(Register reg);
380
381 // Long division/remainder for Java
382 // (as idivq, but checks for special case as described in JVM spec.)
383 // returns idivq instruction offset for implicit exception handling
384 int corrected_idivq(Register reg);
385
386 void int3();
387
388 // Long operation macros for a 32bit cpu
389 // Long negation for Java
390 void lneg(Register hi, Register lo);
391
392 // Long multiplication for Java
393 // (destroys contents of eax, ebx, ecx and edx)
394 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
395
396 // Long shifts for Java
397 // (semantics as described in JVM spec.)
398 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
399 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
400
401 // Long compare for Java
402 // (semantics as described in JVM spec.)
403 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
404
405
406 // misc
407
408 // Sign extension
409 void sign_extend_short(Register reg);
410 void sign_extend_byte(Register reg);
411
412 // Division by power of 2, rounding towards 0
413 void division_with_shift(Register reg, int shift_value);
414
415 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
416 //
417 // CF (corresponds to C0) if x < y
418 // PF (corresponds to C2) if unordered
419 // ZF (corresponds to C3) if x = y
420 //
421 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
422 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
423 void fcmp(Register tmp);
424 // Variant of the above which allows y to be further down the stack
425 // and which only pops x and y if specified. If pop_right is
426 // specified then pop_left must also be specified.
427 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
428
429 // Floating-point comparison for Java
430 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
431 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
432 // (semantics as described in JVM spec.)
433 void fcmp2int(Register dst, bool unordered_is_less);
434 // Variant of the above which allows y to be further down the stack
435 // and which only pops x and y if specified. If pop_right is
436 // specified then pop_left must also be specified.
437 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
438
439 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
440 // tmp is a temporary register, if none is available use noreg
441 void fremr(Register tmp);
442
443 // dst = c = a * b + c
444 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
445 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
446
447 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
448 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
449 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
450 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
451
452
453 // same as fcmp2int, but using SSE2
454 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456
457 // branch to L if FPU flag C2 is set/not set
458 // tmp is a temporary register, if none is available use noreg
459 void jC2 (Register tmp, Label& L);
460 void jnC2(Register tmp, Label& L);
461
462 // Pop ST (ffree & fincstp combined)
463 void fpop();
464
465 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
466 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
467 void load_float(Address src);
468
469 // Store float value to 'address'. If UseSSE >= 1, the value is stored
470 // from register xmm0. Otherwise, the value is stored from the FPU stack.
471 void store_float(Address dst);
472
473 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
474 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
475 void load_double(Address src);
476
477 // Store double value to 'address'. If UseSSE >= 2, the value is stored
478 // from register xmm0. Otherwise, the value is stored from the FPU stack.
479 void store_double(Address dst);
480
481 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
482 void push_fTOS();
483
484 // pops double TOS element from CPU stack and pushes on FPU stack
485 void pop_fTOS();
486
487 void empty_FPU_stack();
488
489 void push_IU_state();
490 void pop_IU_state();
491
492 void push_FPU_state();
493 void pop_FPU_state();
494
495 void push_CPU_state();
496 void pop_CPU_state();
497
498 // Round up to a power of two
499 void round_to(Register reg, int modulus);
500
501 // Callee saved registers handling
502 void push_callee_saved_registers();
503 void pop_callee_saved_registers();
504
505 // allocation
506 void eden_allocate(
507 Register thread, // Current thread
508 Register obj, // result: pointer to object after successful allocation
509 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
510 int con_size_in_bytes, // object size in bytes if known at compile time
511 Register t1, // temp register
512 Label& slow_case // continuation point if fast allocation fails
513 );
514 void tlab_allocate(
515 Register thread, // Current thread
516 Register obj, // result: pointer to object after successful allocation
517 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
518 int con_size_in_bytes, // object size in bytes if known at compile time
519 Register t1, // temp register
520 Register t2, // temp register
521 Label& slow_case // continuation point if fast allocation fails
522 );
523 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
524
525 // interface method calling
526 void lookup_interface_method(Register recv_klass,
527 Register intf_klass,
528 RegisterOrConstant itable_index,
529 Register method_result,
530 Register scan_temp,
531 Label& no_such_interface,
532 bool return_method = true);
533
534 // virtual method calling
535 void lookup_virtual_method(Register recv_klass,
536 RegisterOrConstant vtable_index,
537 Register method_result);
538
539 // Test sub_klass against super_klass, with fast and slow paths.
540
541 // The fast path produces a tri-state answer: yes / no / maybe-slow.
542 // One of the three labels can be NULL, meaning take the fall-through.
543 // If super_check_offset is -1, the value is loaded up from super_klass.
544 // No registers are killed, except temp_reg.
545 void check_klass_subtype_fast_path(Register sub_klass,
546 Register super_klass,
547 Register temp_reg,
548 Label* L_success,
549 Label* L_failure,
550 Label* L_slow_path,
551 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
552
553 // The rest of the type check; must be wired to a corresponding fast path.
554 // It does not repeat the fast path logic, so don't use it standalone.
555 // The temp_reg and temp2_reg can be noreg, if no temps are available.
556 // Updates the sub's secondary super cache as necessary.
557 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
558 void check_klass_subtype_slow_path(Register sub_klass,
559 Register super_klass,
560 Register temp_reg,
561 Register temp2_reg,
562 Label* L_success,
563 Label* L_failure,
564 bool set_cond_codes = false);
565
566 // Simplified, combined version, good for typical uses.
567 // Falls through on failure.
568 void check_klass_subtype(Register sub_klass,
569 Register super_klass,
570 Register temp_reg,
571 Label& L_success);
572
573 // method handles (JSR 292)
574 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
575
576 //----
577 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
578
579 // Debugging
580
581 // only if +VerifyOops
582 // TODO: Make these macros with file and line like sparc version!
583 void verify_oop(Register reg, const char* s = "broken oop");
584 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
585
586 // TODO: verify method and klass metadata (compare against vptr?)
587 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
588 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
589
590 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
591 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
592
593 // only if +VerifyFPU
594 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
595
596 // Verify or restore cpu control state after JNI call
597 void restore_cpu_control_state_after_jni();
598
599 // prints msg, dumps registers and stops execution
600 void stop(const char* msg);
601
602 // prints msg and continues
603 void warn(const char* msg);
604
605 // dumps registers and other state
606 void print_state();
607
608 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
609 static void debug64(char* msg, int64_t pc, int64_t regs[]);
610 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
611 static void print_state64(int64_t pc, int64_t regs[]);
612
613 void os_breakpoint();
614
615 void untested() { stop("untested"); }
616
617 void unimplemented(const char* what = "");
618
619 void should_not_reach_here() { stop("should not reach here"); }
620
621 void print_CPU_state();
622
623 // Stack overflow checking
624 void bang_stack_with_offset(int offset) {
625 // stack grows down, caller passes positive offset
626 assert(offset > 0, "must bang with negative offset");
627 movl(Address(rsp, (-offset)), rax);
628 }
629
630 // Writes to stack successive pages until offset reached to check for
631 // stack overflow + shadow pages. Also, clobbers tmp
632 void bang_stack_size(Register size, Register tmp);
633
634 // Check for reserved stack access in method being exited (for JIT)
635 void reserved_stack_check();
636
637 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
638 Register tmp,
639 int offset);
640
641 // Support for serializing memory accesses between threads
642 void serialize_memory(Register thread, Register tmp);
643
644 // If thread_reg is != noreg the code assumes the register passed contains
645 // the thread (required on 64 bit).
646 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
647
648 void verify_tlab();
649
650 // Biased locking support
651 // lock_reg and obj_reg must be loaded up with the appropriate values.
652 // swap_reg must be rax, and is killed.
653 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
654 // be killed; if not supplied, push/pop will be used internally to
655 // allocate a temporary (inefficient, avoid if possible).
656 // Optional slow case is for implementations (interpreter and C1) which branch to
657 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
658 // Returns offset of first potentially-faulting instruction for null
659 // check info (currently consumed only by C1). If
660 // swap_reg_contains_mark is true then returns -1 as it is assumed
661 // the calling code has already passed any potential faults.
662 int biased_locking_enter(Register lock_reg, Register obj_reg,
663 Register swap_reg, Register tmp_reg,
664 bool swap_reg_contains_mark,
665 Label& done, Label* slow_case = NULL,
666 BiasedLockingCounters* counters = NULL);
667 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
668 #ifdef COMPILER2
669 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
670 // See full desription in macroAssembler_x86.cpp.
671 void fast_lock(Register obj, Register box, Register tmp,
672 Register scr, Register cx1, Register cx2,
673 BiasedLockingCounters* counters,
674 RTMLockingCounters* rtm_counters,
675 RTMLockingCounters* stack_rtm_counters,
676 Metadata* method_data,
677 bool use_rtm, bool profile_rtm);
678 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
679 #if INCLUDE_RTM_OPT
680 void rtm_counters_update(Register abort_status, Register rtm_counters);
681 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
682 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
683 RTMLockingCounters* rtm_counters,
684 Metadata* method_data);
685 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
686 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
687 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
688 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
689 void rtm_stack_locking(Register obj, Register tmp, Register scr,
690 Register retry_on_abort_count,
691 RTMLockingCounters* stack_rtm_counters,
692 Metadata* method_data, bool profile_rtm,
693 Label& DONE_LABEL, Label& IsInflated);
694 void rtm_inflated_locking(Register obj, Register box, Register tmp,
695 Register scr, Register retry_on_busy_count,
696 Register retry_on_abort_count,
697 RTMLockingCounters* rtm_counters,
698 Metadata* method_data, bool profile_rtm,
699 Label& DONE_LABEL);
700 #endif
701 #endif
702
703 Condition negate_condition(Condition cond);
704
705 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
706 // operands. In general the names are modified to avoid hiding the instruction in Assembler
707 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
708 // here in MacroAssembler. The major exception to this rule is call
709
710 // Arithmetics
711
712
713 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
714 void addptr(Address dst, Register src);
715
716 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
717 void addptr(Register dst, int32_t src);
718 void addptr(Register dst, Register src);
719 void addptr(Register dst, RegisterOrConstant src) {
720 if (src.is_constant()) addptr(dst, (int) src.as_constant());
721 else addptr(dst, src.as_register());
722 }
723
724 void andptr(Register dst, int32_t src);
725 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
726
727 void cmp8(AddressLiteral src1, int imm);
728
729 // renamed to drag out the casting of address to int32_t/intptr_t
730 void cmp32(Register src1, int32_t imm);
731
732 void cmp32(AddressLiteral src1, int32_t imm);
733 // compare reg - mem, or reg - &mem
734 void cmp32(Register src1, AddressLiteral src2);
735
736 void cmp32(Register src1, Address src2);
737
738 #ifndef _LP64
739 void cmpklass(Address dst, Metadata* obj);
740 void cmpklass(Register dst, Metadata* obj);
741 void cmpoop(Address dst, jobject obj);
742 void cmpoop_raw(Address dst, jobject obj);
743 #endif // _LP64
744
745 void cmpoop(Register src1, Register src2);
746 void cmpoop(Register src1, Address src2);
747 void cmpoop(Register dst, jobject obj);
748 void cmpoop_raw(Register dst, jobject obj);
749
750 // NOTE src2 must be the lval. This is NOT an mem-mem compare
751 void cmpptr(Address src1, AddressLiteral src2);
752
753 void cmpptr(Register src1, AddressLiteral src2);
754
755 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
756 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758
759 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
760 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
761
762 // cmp64 to avoild hiding cmpq
763 void cmp64(Register src1, AddressLiteral src);
764
765 void cmpxchgptr(Register reg, Address adr);
766
767 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
768
769
770 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
771 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
772
773
774 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
775
776 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
777
778 void shlptr(Register dst, int32_t shift);
779 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
780
781 void shrptr(Register dst, int32_t shift);
782 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
783
784 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
785 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
786
787 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
788
789 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
790 void subptr(Register dst, int32_t src);
791 // Force generation of a 4 byte immediate value even if it fits into 8bit
792 void subptr_imm32(Register dst, int32_t src);
793 void subptr(Register dst, Register src);
794 void subptr(Register dst, RegisterOrConstant src) {
795 if (src.is_constant()) subptr(dst, (int) src.as_constant());
796 else subptr(dst, src.as_register());
797 }
798
799 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
800 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
801
802 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
803 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
804
805 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
806
807
808
809 // Helper functions for statistics gathering.
810 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
811 void cond_inc32(Condition cond, AddressLiteral counter_addr);
812 // Unconditional atomic increment.
813 void atomic_incl(Address counter_addr);
814 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
815 #ifdef _LP64
816 void atomic_incq(Address counter_addr);
817 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
818 #endif
819 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
820 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
821
822 void lea(Register dst, AddressLiteral adr);
823 void lea(Address dst, AddressLiteral adr);
824 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
825
826 void leal32(Register dst, Address src) { leal(dst, src); }
827
828 // Import other testl() methods from the parent class or else
829 // they will be hidden by the following overriding declaration.
830 using Assembler::testl;
831 void testl(Register dst, AddressLiteral src);
832
833 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
834 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
835 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
836 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
837
838 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
839 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
840 void testptr(Register src1, Register src2);
841
842 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
843 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
844
845 // Calls
846
847 void call(Label& L, relocInfo::relocType rtype);
848 void call(Register entry);
849
850 // NOTE: this call transfers to the effective address of entry NOT
851 // the address contained by entry. This is because this is more natural
852 // for jumps/calls.
853 void call(AddressLiteral entry);
854
855 // Emit the CompiledIC call idiom
856 void ic_call(address entry, jint method_index = 0);
857
858 // Jumps
859
860 // NOTE: these jumps tranfer to the effective address of dst NOT
861 // the address contained by dst. This is because this is more natural
862 // for jumps/calls.
863 void jump(AddressLiteral dst);
864 void jump_cc(Condition cc, AddressLiteral dst);
865
866 // 32bit can do a case table jump in one instruction but we no longer allow the base
867 // to be installed in the Address class. This jump will tranfers to the address
868 // contained in the location described by entry (not the address of entry)
869 void jump(ArrayAddress entry);
870
871 // Floating
872
873 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
874 void andpd(XMMRegister dst, AddressLiteral src);
875 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
876
877 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
878 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
879 void andps(XMMRegister dst, AddressLiteral src);
880
881 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
882 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
883 void comiss(XMMRegister dst, AddressLiteral src);
884
885 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
886 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
887 void comisd(XMMRegister dst, AddressLiteral src);
888
889 void fadd_s(Address src) { Assembler::fadd_s(src); }
890 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
891
892 void fldcw(Address src) { Assembler::fldcw(src); }
893 void fldcw(AddressLiteral src);
894
895 void fld_s(int index) { Assembler::fld_s(index); }
896 void fld_s(Address src) { Assembler::fld_s(src); }
897 void fld_s(AddressLiteral src);
898
899 void fld_d(Address src) { Assembler::fld_d(src); }
900 void fld_d(AddressLiteral src);
901
902 void fld_x(Address src) { Assembler::fld_x(src); }
903 void fld_x(AddressLiteral src);
904
905 void fmul_s(Address src) { Assembler::fmul_s(src); }
906 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
907
908 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
909 void ldmxcsr(AddressLiteral src);
910
911 #ifdef _LP64
912 private:
913 void sha256_AVX2_one_round_compute(
914 Register reg_old_h,
915 Register reg_a,
916 Register reg_b,
917 Register reg_c,
918 Register reg_d,
919 Register reg_e,
920 Register reg_f,
921 Register reg_g,
922 Register reg_h,
923 int iter);
924 void sha256_AVX2_four_rounds_compute_first(int start);
925 void sha256_AVX2_four_rounds_compute_last(int start);
926 void sha256_AVX2_one_round_and_sched(
927 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
928 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
929 XMMRegister xmm_2, /* ymm6 */
930 XMMRegister xmm_3, /* ymm7 */
931 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
932 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
933 Register reg_c, /* edi */
934 Register reg_d, /* esi */
935 Register reg_e, /* r8d */
936 Register reg_f, /* r9d */
937 Register reg_g, /* r10d */
938 Register reg_h, /* r11d */
939 int iter);
940
941 void addm(int disp, Register r1, Register r2);
942
943 public:
944 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
945 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
946 Register buf, Register state, Register ofs, Register limit, Register rsp,
947 bool multi_block, XMMRegister shuf_mask);
948 #endif
949
950 #ifdef _LP64
951 private:
952 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
953 Register e, Register f, Register g, Register h, int iteration);
954
955 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
956 Register a, Register b, Register c, Register d, Register e, Register f,
957 Register g, Register h, int iteration);
958
959 void addmq(int disp, Register r1, Register r2);
960 public:
961 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
962 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
963 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
964 XMMRegister shuf_mask);
965 #endif
966
967 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
968 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
969 Register buf, Register state, Register ofs, Register limit, Register rsp,
970 bool multi_block);
971
972 #ifdef _LP64
973 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
974 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
975 Register buf, Register state, Register ofs, Register limit, Register rsp,
976 bool multi_block, XMMRegister shuf_mask);
977 #else
978 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
979 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
980 Register buf, Register state, Register ofs, Register limit, Register rsp,
981 bool multi_block);
982 #endif
983
984 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
985 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
986 Register rax, Register rcx, Register rdx, Register tmp);
987
988 #ifdef _LP64
989 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
990 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
991 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
992
993 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
994 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
995 Register rax, Register rcx, Register rdx, Register r11);
996
997 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
998 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
999 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1000
1001 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1002 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1003 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1004 Register tmp3, Register tmp4);
1005
1006 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1007 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1008 Register rax, Register rcx, Register rdx, Register tmp1,
1009 Register tmp2, Register tmp3, Register tmp4);
1010 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1011 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1012 Register rax, Register rcx, Register rdx, Register tmp1,
1013 Register tmp2, Register tmp3, Register tmp4);
1014 #else
1015 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017 Register rax, Register rcx, Register rdx, Register tmp1);
1018
1019 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021 Register rax, Register rcx, Register rdx, Register tmp);
1022
1023 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1024 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1025 Register rdx, Register tmp);
1026
1027 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1028 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1029 Register rax, Register rbx, Register rdx);
1030
1031 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033 Register rax, Register rcx, Register rdx, Register tmp);
1034
1035 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1036 Register edx, Register ebx, Register esi, Register edi,
1037 Register ebp, Register esp);
1038
1039 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1040 Register esi, Register edi, Register ebp, Register esp);
1041
1042 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1043 Register edx, Register ebx, Register esi, Register edi,
1044 Register ebp, Register esp);
1045
1046 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1047 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1048 Register rax, Register rcx, Register rdx, Register tmp);
1049 #endif
1050
1051 void increase_precision();
1052 void restore_precision();
1053
1054 private:
1055
1056 // these are private because users should be doing movflt/movdbl
1057
1058 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1059 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1060 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1061 void movss(XMMRegister dst, AddressLiteral src);
1062
1063 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1064 void movlpd(XMMRegister dst, AddressLiteral src);
1065
1066 public:
1067
1068 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1069 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1070 void addsd(XMMRegister dst, AddressLiteral src);
1071
1072 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1073 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1074 void addss(XMMRegister dst, AddressLiteral src);
1075
1076 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1077 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1078 void addpd(XMMRegister dst, AddressLiteral src);
1079
1080 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1081 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1082 void divsd(XMMRegister dst, AddressLiteral src);
1083
1084 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1085 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1086 void divss(XMMRegister dst, AddressLiteral src);
1087
1088 // Move Unaligned Double Quadword
1089 void movdqu(Address dst, XMMRegister src);
1090 void movdqu(XMMRegister dst, Address src);
1091 void movdqu(XMMRegister dst, XMMRegister src);
1092 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1093 // AVX Unaligned forms
1094 void vmovdqu(Address dst, XMMRegister src);
1095 void vmovdqu(XMMRegister dst, Address src);
1096 void vmovdqu(XMMRegister dst, XMMRegister src);
1097 void vmovdqu(XMMRegister dst, AddressLiteral src);
1098
1099 // Move Aligned Double Quadword
1100 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1101 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1102 void movdqa(XMMRegister dst, AddressLiteral src);
1103
1104 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1105 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1106 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1107 void movsd(XMMRegister dst, AddressLiteral src);
1108
1109 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1110 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1111 void mulpd(XMMRegister dst, AddressLiteral src);
1112
1113 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1114 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1115 void mulsd(XMMRegister dst, AddressLiteral src);
1116
1117 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1118 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1119 void mulss(XMMRegister dst, AddressLiteral src);
1120
1121 // Carry-Less Multiplication Quadword
1122 void pclmulldq(XMMRegister dst, XMMRegister src) {
1123 // 0x00 - multiply lower 64 bits [0:63]
1124 Assembler::pclmulqdq(dst, src, 0x00);
1125 }
1126 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1127 // 0x11 - multiply upper 64 bits [64:127]
1128 Assembler::pclmulqdq(dst, src, 0x11);
1129 }
1130
1131 void pcmpeqb(XMMRegister dst, XMMRegister src);
1132 void pcmpeqw(XMMRegister dst, XMMRegister src);
1133
1134 void pcmpestri(XMMRegister dst, Address src, int imm8);
1135 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1136
1137 void pmovzxbw(XMMRegister dst, XMMRegister src);
1138 void pmovzxbw(XMMRegister dst, Address src);
1139
1140 void pmovmskb(Register dst, XMMRegister src);
1141
1142 void ptest(XMMRegister dst, XMMRegister src);
1143
1144 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1145 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1146 void sqrtsd(XMMRegister dst, AddressLiteral src);
1147
1148 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1149 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1150 void sqrtss(XMMRegister dst, AddressLiteral src);
1151
1152 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1153 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1154 void subsd(XMMRegister dst, AddressLiteral src);
1155
1156 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1157 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1158 void subss(XMMRegister dst, AddressLiteral src);
1159
1160 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1161 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1162 void ucomiss(XMMRegister dst, AddressLiteral src);
1163
1164 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1165 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1166 void ucomisd(XMMRegister dst, AddressLiteral src);
1167
1168 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1169 void xorpd(XMMRegister dst, XMMRegister src);
1170 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1171 void xorpd(XMMRegister dst, AddressLiteral src);
1172
1173 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1174 void xorps(XMMRegister dst, XMMRegister src);
1175 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1176 void xorps(XMMRegister dst, AddressLiteral src);
1177
1178 // Shuffle Bytes
1179 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1180 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1181 void pshufb(XMMRegister dst, AddressLiteral src);
1182 // AVX 3-operands instructions
1183
1184 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1185 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1186 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1187
1188 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1189 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1190 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1191
1192 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1193 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1194
1195 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1196 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1197
1198 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1199 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1200
1201 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1202 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1203 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1204
1205 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1206
1207 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1208 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1209
1210 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1211 void vpmovmskb(Register dst, XMMRegister src);
1212
1213 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1214 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1215
1216 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1217 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1218
1219 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1220 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1221
1222 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1223 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1224
1225 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1226 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1227
1228 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1229 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1230
1231 void vptest(XMMRegister dst, XMMRegister src);
1232
1233 void punpcklbw(XMMRegister dst, XMMRegister src);
1234 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1235
1236 void pshufd(XMMRegister dst, Address src, int mode);
1237 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1238
1239 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1240 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1241
1242 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1243 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1244 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1245
1246 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1247 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1248 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1249
1250 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1251 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1252 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1253
1254 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1255 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1256 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1257
1258 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1259 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1260 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1261
1262 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1263 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1264 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1265
1266 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1267 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1268 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1269
1270 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1271 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1272 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1273
1274 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1275 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1276
1277 // AVX Vector instructions
1278
1279 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1280 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1281 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1282
1283 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1284 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1285 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1286
1287 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1288 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1289 Assembler::vpxor(dst, nds, src, vector_len);
1290 else
1291 Assembler::vxorpd(dst, nds, src, vector_len);
1292 }
1293 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1294 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1295 Assembler::vpxor(dst, nds, src, vector_len);
1296 else
1297 Assembler::vxorpd(dst, nds, src, vector_len);
1298 }
1299
1300 // Simple version for AVX2 256bit vectors
1301 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1302 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1303
1304 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1305 if (UseAVX > 2) {
1306 Assembler::vinserti32x4(dst, dst, src, imm8);
1307 } else if (UseAVX > 1) {
1308 // vinserti128 is available only in AVX2
1309 Assembler::vinserti128(dst, nds, src, imm8);
1310 } else {
1311 Assembler::vinsertf128(dst, nds, src, imm8);
1312 }
1313 }
1314
1315 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1316 if (UseAVX > 2) {
1317 Assembler::vinserti32x4(dst, dst, src, imm8);
1318 } else if (UseAVX > 1) {
1319 // vinserti128 is available only in AVX2
1320 Assembler::vinserti128(dst, nds, src, imm8);
1321 } else {
1322 Assembler::vinsertf128(dst, nds, src, imm8);
1323 }
1324 }
1325
1326 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1327 if (UseAVX > 2) {
1328 Assembler::vextracti32x4(dst, src, imm8);
1329 } else if (UseAVX > 1) {
1330 // vextracti128 is available only in AVX2
1331 Assembler::vextracti128(dst, src, imm8);
1332 } else {
1333 Assembler::vextractf128(dst, src, imm8);
1334 }
1335 }
1336
1337 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1338 if (UseAVX > 2) {
1339 Assembler::vextracti32x4(dst, src, imm8);
1340 } else if (UseAVX > 1) {
1341 // vextracti128 is available only in AVX2
1342 Assembler::vextracti128(dst, src, imm8);
1343 } else {
1344 Assembler::vextractf128(dst, src, imm8);
1345 }
1346 }
1347
1348 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1349 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1350 vinserti128(dst, dst, src, 1);
1351 }
1352 void vinserti128_high(XMMRegister dst, Address src) {
1353 vinserti128(dst, dst, src, 1);
1354 }
1355 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1356 vextracti128(dst, src, 1);
1357 }
1358 void vextracti128_high(Address dst, XMMRegister src) {
1359 vextracti128(dst, src, 1);
1360 }
1361
1362 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1363 if (UseAVX > 2) {
1364 Assembler::vinsertf32x4(dst, dst, src, 1);
1365 } else {
1366 Assembler::vinsertf128(dst, dst, src, 1);
1367 }
1368 }
1369
1370 void vinsertf128_high(XMMRegister dst, Address src) {
1371 if (UseAVX > 2) {
1372 Assembler::vinsertf32x4(dst, dst, src, 1);
1373 } else {
1374 Assembler::vinsertf128(dst, dst, src, 1);
1375 }
1376 }
1377
1378 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1379 if (UseAVX > 2) {
1380 Assembler::vextractf32x4(dst, src, 1);
1381 } else {
1382 Assembler::vextractf128(dst, src, 1);
1383 }
1384 }
1385
1386 void vextractf128_high(Address dst, XMMRegister src) {
1387 if (UseAVX > 2) {
1388 Assembler::vextractf32x4(dst, src, 1);
1389 } else {
1390 Assembler::vextractf128(dst, src, 1);
1391 }
1392 }
1393
1394 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1395 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1396 Assembler::vinserti64x4(dst, dst, src, 1);
1397 }
1398 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1399 Assembler::vinsertf64x4(dst, dst, src, 1);
1400 }
1401 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1402 Assembler::vextracti64x4(dst, src, 1);
1403 }
1404 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1405 Assembler::vextractf64x4(dst, src, 1);
1406 }
1407 void vextractf64x4_high(Address dst, XMMRegister src) {
1408 Assembler::vextractf64x4(dst, src, 1);
1409 }
1410 void vinsertf64x4_high(XMMRegister dst, Address src) {
1411 Assembler::vinsertf64x4(dst, dst, src, 1);
1412 }
1413
1414 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1415 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1416 vinserti128(dst, dst, src, 0);
1417 }
1418 void vinserti128_low(XMMRegister dst, Address src) {
1419 vinserti128(dst, dst, src, 0);
1420 }
1421 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1422 vextracti128(dst, src, 0);
1423 }
1424 void vextracti128_low(Address dst, XMMRegister src) {
1425 vextracti128(dst, src, 0);
1426 }
1427
1428 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1429 if (UseAVX > 2) {
1430 Assembler::vinsertf32x4(dst, dst, src, 0);
1431 } else {
1432 Assembler::vinsertf128(dst, dst, src, 0);
1433 }
1434 }
1435
1436 void vinsertf128_low(XMMRegister dst, Address src) {
1437 if (UseAVX > 2) {
1438 Assembler::vinsertf32x4(dst, dst, src, 0);
1439 } else {
1440 Assembler::vinsertf128(dst, dst, src, 0);
1441 }
1442 }
1443
1444 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1445 if (UseAVX > 2) {
1446 Assembler::vextractf32x4(dst, src, 0);
1447 } else {
1448 Assembler::vextractf128(dst, src, 0);
1449 }
1450 }
1451
1452 void vextractf128_low(Address dst, XMMRegister src) {
1453 if (UseAVX > 2) {
1454 Assembler::vextractf32x4(dst, src, 0);
1455 } else {
1456 Assembler::vextractf128(dst, src, 0);
1457 }
1458 }
1459
1460 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1461 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1462 Assembler::vinserti64x4(dst, dst, src, 0);
1463 }
1464 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1465 Assembler::vinsertf64x4(dst, dst, src, 0);
1466 }
1467 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1468 Assembler::vextracti64x4(dst, src, 0);
1469 }
1470 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1471 Assembler::vextractf64x4(dst, src, 0);
1472 }
1473 void vextractf64x4_low(Address dst, XMMRegister src) {
1474 Assembler::vextractf64x4(dst, src, 0);
1475 }
1476 void vinsertf64x4_low(XMMRegister dst, Address src) {
1477 Assembler::vinsertf64x4(dst, dst, src, 0);
1478 }
1479
1480 // Carry-Less Multiplication Quadword
1481 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1482 // 0x00 - multiply lower 64 bits [0:63]
1483 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1484 }
1485 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1486 // 0x11 - multiply upper 64 bits [64:127]
1487 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1488 }
1489 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1490 // 0x00 - multiply lower 64 bits [0:63]
1491 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1492 }
1493 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1494 // 0x11 - multiply upper 64 bits [64:127]
1495 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1496 }
1497
1498 // Data
1499
1500 void cmov32( Condition cc, Register dst, Address src);
1501 void cmov32( Condition cc, Register dst, Register src);
1502
1503 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1504
1505 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1506 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1507
1508 void movoop(Register dst, jobject obj);
1509 void movoop(Address dst, jobject obj);
1510
1511 void mov_metadata(Register dst, Metadata* obj);
1512 void mov_metadata(Address dst, Metadata* obj);
1513
1514 void movptr(ArrayAddress dst, Register src);
1515 // can this do an lea?
1516 void movptr(Register dst, ArrayAddress src);
1517
1518 void movptr(Register dst, Address src);
1519
1520 #ifdef _LP64
1521 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1522 #else
1523 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1524 #endif
1525
1526 void movptr(Register dst, intptr_t src);
1527 void movptr(Register dst, Register src);
1528 void movptr(Address dst, intptr_t src);
1529
1530 void movptr(Address dst, Register src);
1531
1532 void movptr(Register dst, RegisterOrConstant src) {
1533 if (src.is_constant()) movptr(dst, src.as_constant());
1534 else movptr(dst, src.as_register());
1535 }
1536
1537 #ifdef _LP64
1538 // Generally the next two are only used for moving NULL
1539 // Although there are situations in initializing the mark word where
1540 // they could be used. They are dangerous.
1541
1542 // They only exist on LP64 so that int32_t and intptr_t are not the same
1543 // and we have ambiguous declarations.
1544
1545 void movptr(Address dst, int32_t imm32);
1546 void movptr(Register dst, int32_t imm32);
1547 #endif // _LP64
1548
1549 // to avoid hiding movl
1550 void mov32(AddressLiteral dst, Register src);
1551 void mov32(Register dst, AddressLiteral src);
1552
1553 // to avoid hiding movb
1554 void movbyte(ArrayAddress dst, int src);
1555
1556 // Import other mov() methods from the parent class or else
1557 // they will be hidden by the following overriding declaration.
1558 using Assembler::movdl;
1559 using Assembler::movq;
1560 void movdl(XMMRegister dst, AddressLiteral src);
1561 void movq(XMMRegister dst, AddressLiteral src);
1562
1563 // Can push value or effective address
1564 void pushptr(AddressLiteral src);
1565
1566 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1567 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1568
1569 void pushoop(jobject obj);
1570 void pushklass(Metadata* obj);
1571
1572 // sign extend as need a l to ptr sized element
1573 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1574 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1575
1576 // C2 compiled method's prolog code.
1577 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1578
1579 // clear memory of size 'cnt' qwords, starting at 'base';
1580 // if 'is_large' is set, do not try to produce short loop
1581 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1582
1583 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1584 void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1585
1586 #ifdef COMPILER2
1587 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1588 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1589
1590 // IndexOf strings.
1591 // Small strings are loaded through stack if they cross page boundary.
1592 void string_indexof(Register str1, Register str2,
1593 Register cnt1, Register cnt2,
1594 int int_cnt2, Register result,
1595 XMMRegister vec, Register tmp,
1596 int ae);
1597
1598 // IndexOf for constant substrings with size >= 8 elements
1599 // which don't need to be loaded through stack.
1600 void string_indexofC8(Register str1, Register str2,
1601 Register cnt1, Register cnt2,
1602 int int_cnt2, Register result,
1603 XMMRegister vec, Register tmp,
1604 int ae);
1605
1606 // Smallest code: we don't need to load through stack,
1607 // check string tail.
1608
1609 // helper function for string_compare
1610 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1611 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1612 Address::ScaleFactor scale2, Register index, int ae);
1613 // Compare strings.
1614 void string_compare(Register str1, Register str2,
1615 Register cnt1, Register cnt2, Register result,
1616 XMMRegister vec1, int ae);
1617
1618 // Search for Non-ASCII character (Negative byte value) in a byte array,
1619 // return true if it has any and false otherwise.
1620 void has_negatives(Register ary1, Register len,
1621 Register result, Register tmp1,
1622 XMMRegister vec1, XMMRegister vec2);
1623
1624 // Compare char[] or byte[] arrays.
1625 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1626 Register limit, Register result, Register chr,
1627 XMMRegister vec1, XMMRegister vec2, bool is_char);
1628
1629 #endif
1630
1631 // Fill primitive arrays
1632 void generate_fill(BasicType t, bool aligned,
1633 Register to, Register value, Register count,
1634 Register rtmp, XMMRegister xtmp);
1635
1636 void encode_iso_array(Register src, Register dst, Register len,
1637 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1638 XMMRegister tmp4, Register tmp5, Register result);
1639
1640 #ifdef _LP64
1641 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1642 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1643 Register y, Register y_idx, Register z,
1644 Register carry, Register product,
1645 Register idx, Register kdx);
1646 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1647 Register yz_idx, Register idx,
1648 Register carry, Register product, int offset);
1649 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1650 Register carry, Register carry2,
1651 Register idx, Register jdx,
1652 Register yz_idx1, Register yz_idx2,
1653 Register tmp, Register tmp3, Register tmp4);
1654 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1655 Register yz_idx, Register idx, Register jdx,
1656 Register carry, Register product,
1657 Register carry2);
1658 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1659 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1660 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1661 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1662 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1663 Register tmp2);
1664 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1665 Register rdxReg, Register raxReg);
1666 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1667 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1668 Register tmp3, Register tmp4);
1669 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1670 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1671
1672 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1673 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1674 Register raxReg);
1675 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1676 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1677 Register raxReg);
1678 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1679 Register result, Register tmp1, Register tmp2,
1680 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1681 #endif
1682
1683 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1684 void update_byte_crc32(Register crc, Register val, Register table);
1685 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1686 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1687 // Note on a naming convention:
1688 // Prefix w = register only used on a Westmere+ architecture
1689 // Prefix n = register only used on a Nehalem architecture
1690 #ifdef _LP64
1691 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1692 Register tmp1, Register tmp2, Register tmp3);
1693 #else
1694 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1695 Register tmp1, Register tmp2, Register tmp3,
1696 XMMRegister xtmp1, XMMRegister xtmp2);
1697 #endif
1698 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1699 Register in_out,
1700 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1701 XMMRegister w_xtmp2,
1702 Register tmp1,
1703 Register n_tmp2, Register n_tmp3);
1704 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1705 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1706 Register tmp1, Register tmp2,
1707 Register n_tmp3);
1708 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1709 Register in_out1, Register in_out2, Register in_out3,
1710 Register tmp1, Register tmp2, Register tmp3,
1711 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1712 Register tmp4, Register tmp5,
1713 Register n_tmp6);
1714 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1715 Register tmp1, Register tmp2, Register tmp3,
1716 Register tmp4, Register tmp5, Register tmp6,
1717 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1718 bool is_pclmulqdq_supported);
1719 // Fold 128-bit data chunk
1720 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1721 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1722 // Fold 8-bit data
1723 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1724 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1725 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1726
1727 // Compress char[] array to byte[].
1728 void char_array_compress(Register src, Register dst, Register len,
1729 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1730 XMMRegister tmp4, Register tmp5, Register result);
1731
1732 // Inflate byte[] array to char[].
1733 void byte_array_inflate(Register src, Register dst, Register len,
1734 XMMRegister tmp1, Register tmp2);
1735
1736 };
1737
1738 /**
1739 * class SkipIfEqual:
1740 *
1741 * Instantiating this class will result in assembly code being output that will
1742 * jump around any code emitted between the creation of the instance and it's
1743 * automatic destruction at the end of a scope block, depending on the value of
1744 * the flag passed to the constructor, which will be checked at run-time.
1745 */
1746 class SkipIfEqual {
1747 private:
1748 MacroAssembler* _masm;
1749 Label _label;
1750
1751 public:
1752 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1753 ~SkipIfEqual();
1754 };
1755
1756 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP