1 /* 2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #ifndef _WINDOWS 27 #include "alloca.h" 28 #endif 29 #include "asm/macroAssembler.hpp" 30 #include "asm/macroAssembler.inline.hpp" 31 #include "code/debugInfoRec.hpp" 32 #include "code/icBuffer.hpp" 33 #include "code/nativeInst.hpp" 34 #include "code/vtableStubs.hpp" 35 #include "gc/shared/gcLocker.hpp" 36 #include "interpreter/interpreter.hpp" 37 #include "logging/log.hpp" 38 #include "memory/resourceArea.hpp" 39 #include "oops/compiledICHolder.hpp" 40 #include "runtime/safepointMechanism.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 #include "runtime/vframeArray.hpp" 43 #include "utilities/align.hpp" 44 #include "utilities/formatBuffer.hpp" 45 #include "vm_version_x86.hpp" 46 #include "vmreg_x86.inline.hpp" 47 #ifdef COMPILER1 48 #include "c1/c1_Runtime1.hpp" 49 #endif 50 #ifdef COMPILER2 51 #include "opto/runtime.hpp" 52 #endif 53 #if INCLUDE_JVMCI 54 #include "jvmci/jvmciJavaClasses.hpp" 55 #endif 56 57 #define __ masm-> 58 59 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; 60 61 class SimpleRuntimeFrame { 62 63 public: 64 65 // Most of the runtime stubs have this simple frame layout. 66 // This class exists to make the layout shared in one place. 67 // Offsets are for compiler stack slots, which are jints. 68 enum layout { 69 // The frame sender code expects that rbp will be in the "natural" place and 70 // will override any oopMap setting for it. We must therefore force the layout 71 // so that it agrees with the frame sender code. 72 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, 73 rbp_off2, 74 return_off, return_off2, 75 framesize 76 }; 77 }; 78 79 class RegisterSaver { 80 // Capture info about frame layout. Layout offsets are in jint 81 // units because compiler frame slots are jints. 82 #define XSAVE_AREA_BEGIN 160 83 #define XSAVE_AREA_YMM_BEGIN 576 84 #define XSAVE_AREA_ZMM_BEGIN 1152 85 #define XSAVE_AREA_UPPERBANK 1664 86 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off 87 #define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off 88 #define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off 89 enum layout { 90 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area 91 xmm_off = fpu_state_off + XSAVE_AREA_BEGIN/BytesPerInt, // offset in fxsave save area 92 DEF_XMM_OFFS(0), 93 DEF_XMM_OFFS(1), 94 // 2..15 are implied in range usage 95 ymm_off = xmm_off + (XSAVE_AREA_YMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt, 96 DEF_YMM_OFFS(0), 97 DEF_YMM_OFFS(1), 98 // 2..15 are implied in range usage 99 zmm_high = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt, 100 zmm_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt, 101 DEF_ZMM_OFFS(16), 102 DEF_ZMM_OFFS(17), 103 // 18..31 are implied in range usage 104 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), 105 fpu_stateH_end, 106 r15_off, r15H_off, 107 r14_off, r14H_off, 108 r13_off, r13H_off, 109 r12_off, r12H_off, 110 r11_off, r11H_off, 111 r10_off, r10H_off, 112 r9_off, r9H_off, 113 r8_off, r8H_off, 114 rdi_off, rdiH_off, 115 rsi_off, rsiH_off, 116 ignore_off, ignoreH_off, // extra copy of rbp 117 rsp_off, rspH_off, 118 rbx_off, rbxH_off, 119 rdx_off, rdxH_off, 120 rcx_off, rcxH_off, 121 rax_off, raxH_off, 122 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state 123 align_off, alignH_off, 124 flags_off, flagsH_off, 125 // The frame sender code expects that rbp will be in the "natural" place and 126 // will override any oopMap setting for it. We must therefore force the layout 127 // so that it agrees with the frame sender code. 128 rbp_off, rbpH_off, // copy of rbp we will restore 129 return_off, returnH_off, // slot for return address 130 reg_save_size // size in compiler stack slots 131 }; 132 133 public: 134 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false); 135 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); 136 137 // Offsets into the register save area 138 // Used by deoptimization when it is managing result register 139 // values on its own 140 141 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; } 142 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; } 143 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; } 144 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; } 145 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; } 146 147 // During deoptimization only the result registers need to be restored, 148 // all the other values have already been extracted. 149 static void restore_result_registers(MacroAssembler* masm); 150 }; 151 152 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { 153 int off = 0; 154 int num_xmm_regs = XMMRegisterImpl::number_of_registers; 155 if (UseAVX < 3) { 156 num_xmm_regs = num_xmm_regs/2; 157 } 158 #if COMPILER2_OR_JVMCI 159 if (save_vectors) { 160 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX"); 161 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); 162 } 163 #else 164 assert(!save_vectors, "vectors are generated only by C2 and JVMCI"); 165 #endif 166 167 // Always make the frame size 16-byte aligned, both vector and non vector stacks are always allocated 168 int frame_size_in_bytes = align_up(reg_save_size*BytesPerInt, num_xmm_regs); 169 // OopMap frame size is in compiler stack slots (jint's) not bytes or words 170 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; 171 // CodeBlob frame size is in words. 172 int frame_size_in_words = frame_size_in_bytes / wordSize; 173 *total_frame_words = frame_size_in_words; 174 175 // Save registers, fpu state, and flags. 176 // We assume caller has already pushed the return address onto the 177 // stack, so rsp is 8-byte aligned here. 178 // We push rpb twice in this sequence because we want the real rbp 179 // to be under the return like a normal enter. 180 181 __ enter(); // rsp becomes 16-byte aligned here 182 __ push_CPU_state(); // Push a multiple of 16 bytes 183 184 // push cpu state handles this on EVEX enabled targets 185 if (save_vectors) { 186 // Save upper half of YMM registers(0..15) 187 int base_addr = XSAVE_AREA_YMM_BEGIN; 188 for (int n = 0; n < 16; n++) { 189 __ vextractf128_high(Address(rsp, base_addr+n*16), as_XMMRegister(n)); 190 } 191 if (VM_Version::supports_evex()) { 192 // Save upper half of ZMM registers(0..15) 193 base_addr = XSAVE_AREA_ZMM_BEGIN; 194 for (int n = 0; n < 16; n++) { 195 __ vextractf64x4_high(Address(rsp, base_addr+n*32), as_XMMRegister(n)); 196 } 197 // Save full ZMM registers(16..num_xmm_regs) 198 base_addr = XSAVE_AREA_UPPERBANK; 199 off = 0; 200 int vector_len = Assembler::AVX_512bit; 201 for (int n = 16; n < num_xmm_regs; n++) { 202 __ evmovdqul(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n), vector_len); 203 } 204 } 205 } else { 206 if (VM_Version::supports_evex()) { 207 // Save upper bank of ZMM registers(16..31) for double/float usage 208 int base_addr = XSAVE_AREA_UPPERBANK; 209 off = 0; 210 for (int n = 16; n < num_xmm_regs; n++) { 211 __ movsd(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n)); 212 } 213 } 214 } 215 __ vzeroupper(); 216 if (frame::arg_reg_save_area_bytes != 0) { 217 // Allocate argument register save area 218 __ subptr(rsp, frame::arg_reg_save_area_bytes); 219 } 220 221 // Set an oopmap for the call site. This oopmap will map all 222 // oop-registers and debug-info registers as callee-saved. This 223 // will allow deoptimization at this safepoint to find all possible 224 // debug-info recordings, as well as let GC find all oops. 225 226 OopMapSet *oop_maps = new OopMapSet(); 227 OopMap* map = new OopMap(frame_size_in_slots, 0); 228 229 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x)) 230 231 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg()); 232 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg()); 233 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg()); 234 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg()); 235 // rbp location is known implicitly by the frame sender code, needs no oopmap 236 // and the location where rbp was saved by is ignored 237 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg()); 238 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg()); 239 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg()); 240 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg()); 241 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg()); 242 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg()); 243 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg()); 244 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg()); 245 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg()); 246 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg()); 247 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15, 248 // on EVEX enabled targets, we get it included in the xsave area 249 off = xmm0_off; 250 int delta = xmm1_off - off; 251 for (int n = 0; n < 16; n++) { 252 XMMRegister xmm_name = as_XMMRegister(n); 253 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()); 254 off += delta; 255 } 256 if(UseAVX > 2) { 257 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets 258 off = zmm16_off; 259 delta = zmm17_off - off; 260 for (int n = 16; n < num_xmm_regs; n++) { 261 XMMRegister zmm_name = as_XMMRegister(n); 262 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()); 263 off += delta; 264 } 265 } 266 267 #if COMPILER2_OR_JVMCI 268 if (save_vectors) { 269 off = ymm0_off; 270 int delta = ymm1_off - off; 271 for (int n = 0; n < 16; n++) { 272 XMMRegister ymm_name = as_XMMRegister(n); 273 map->set_callee_saved(STACK_OFFSET(off), ymm_name->as_VMReg()->next(4)); 274 off += delta; 275 } 276 } 277 #endif // COMPILER2_OR_JVMCI 278 279 // %%% These should all be a waste but we'll keep things as they were for now 280 if (true) { 281 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next()); 282 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next()); 283 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next()); 284 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next()); 285 // rbp location is known implicitly by the frame sender code, needs no oopmap 286 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next()); 287 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next()); 288 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next()); 289 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next()); 290 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next()); 291 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next()); 292 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next()); 293 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next()); 294 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next()); 295 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next()); 296 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15, 297 // on EVEX enabled targets, we get it included in the xsave area 298 off = xmm0H_off; 299 delta = xmm1H_off - off; 300 for (int n = 0; n < 16; n++) { 301 XMMRegister xmm_name = as_XMMRegister(n); 302 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next()); 303 off += delta; 304 } 305 if (UseAVX > 2) { 306 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets 307 off = zmm16H_off; 308 delta = zmm17H_off - off; 309 for (int n = 16; n < num_xmm_regs; n++) { 310 XMMRegister zmm_name = as_XMMRegister(n); 311 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next()); 312 off += delta; 313 } 314 } 315 } 316 317 return map; 318 } 319 320 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { 321 int num_xmm_regs = XMMRegisterImpl::number_of_registers; 322 if (UseAVX < 3) { 323 num_xmm_regs = num_xmm_regs/2; 324 } 325 if (frame::arg_reg_save_area_bytes != 0) { 326 // Pop arg register save area 327 __ addptr(rsp, frame::arg_reg_save_area_bytes); 328 } 329 330 #if COMPILER2_OR_JVMCI 331 if (restore_vectors) { 332 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX"); 333 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); 334 } 335 #else 336 assert(!restore_vectors, "vectors are generated only by C2"); 337 #endif 338 339 __ vzeroupper(); 340 341 // On EVEX enabled targets everything is handled in pop fpu state 342 if (restore_vectors) { 343 // Restore upper half of YMM registers (0..15) 344 int base_addr = XSAVE_AREA_YMM_BEGIN; 345 for (int n = 0; n < 16; n++) { 346 __ vinsertf128_high(as_XMMRegister(n), Address(rsp, base_addr+n*16)); 347 } 348 if (VM_Version::supports_evex()) { 349 // Restore upper half of ZMM registers (0..15) 350 base_addr = XSAVE_AREA_ZMM_BEGIN; 351 for (int n = 0; n < 16; n++) { 352 __ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, base_addr+n*32)); 353 } 354 // Restore full ZMM registers(16..num_xmm_regs) 355 base_addr = XSAVE_AREA_UPPERBANK; 356 int vector_len = Assembler::AVX_512bit; 357 int off = 0; 358 for (int n = 16; n < num_xmm_regs; n++) { 359 __ evmovdqul(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)), vector_len); 360 } 361 } 362 } else { 363 if (VM_Version::supports_evex()) { 364 // Restore upper bank of ZMM registers(16..31) for double/float usage 365 int base_addr = XSAVE_AREA_UPPERBANK; 366 int off = 0; 367 for (int n = 16; n < num_xmm_regs; n++) { 368 __ movsd(as_XMMRegister(n), Address(rsp, base_addr+(off++*64))); 369 } 370 } 371 } 372 373 // Recover CPU state 374 __ pop_CPU_state(); 375 // Get the rbp described implicitly by the calling convention (no oopMap) 376 __ pop(rbp); 377 } 378 379 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { 380 381 // Just restore result register. Only used by deoptimization. By 382 // now any callee save register that needs to be restored to a c2 383 // caller of the deoptee has been extracted into the vframeArray 384 // and will be stuffed into the c2i adapter we create for later 385 // restoration so only result registers need to be restored here. 386 387 // Restore fp result register 388 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes())); 389 // Restore integer result register 390 __ movptr(rax, Address(rsp, rax_offset_in_bytes())); 391 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes())); 392 393 // Pop all of the register save are off the stack except the return address 394 __ addptr(rsp, return_offset_in_bytes()); 395 } 396 397 // Is vector's size (in bytes) bigger than a size saved by default? 398 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. 399 bool SharedRuntime::is_wide_vector(int size) { 400 return size > 16; 401 } 402 403 size_t SharedRuntime::trampoline_size() { 404 return 16; 405 } 406 407 void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) { 408 __ jump(RuntimeAddress(destination)); 409 } 410 411 // The java_calling_convention describes stack locations as ideal slots on 412 // a frame with no abi restrictions. Since we must observe abi restrictions 413 // (like the placement of the register window) the slots must be biased by 414 // the following value. 415 static int reg2offset_in(VMReg r) { 416 // Account for saved rbp and return address 417 // This should really be in_preserve_stack_slots 418 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; 419 } 420 421 static int reg2offset_out(VMReg r) { 422 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 423 } 424 425 // --------------------------------------------------------------------------- 426 // Read the array of BasicTypes from a signature, and compute where the 427 // arguments should go. Values in the VMRegPair regs array refer to 4-byte 428 // quantities. Values less than VMRegImpl::stack0 are registers, those above 429 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer 430 // as framesizes are fixed. 431 // VMRegImpl::stack0 refers to the first slot 0(sp). 432 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register 433 // up to RegisterImpl::number_of_registers) are the 64-bit 434 // integer registers. 435 436 // Note: the INPUTS in sig_bt are in units of Java argument words, which are 437 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit 438 // units regardless of build. Of course for i486 there is no 64 bit build 439 440 // The Java calling convention is a "shifted" version of the C ABI. 441 // By skipping the first C ABI register we can call non-static jni methods 442 // with small numbers of arguments without having to shuffle the arguments 443 // at all. Since we control the java ABI we ought to at least get some 444 // advantage out of it. 445 446 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, 447 VMRegPair *regs, 448 int total_args_passed, 449 int is_outgoing) { 450 451 // Create the mapping between argument positions and 452 // registers. 453 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { 454 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5 455 }; 456 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = { 457 j_farg0, j_farg1, j_farg2, j_farg3, 458 j_farg4, j_farg5, j_farg6, j_farg7 459 }; 460 461 462 uint int_args = 0; 463 uint fp_args = 0; 464 uint stk_args = 0; // inc by 2 each time 465 466 for (int i = 0; i < total_args_passed; i++) { 467 switch (sig_bt[i]) { 468 case T_BOOLEAN: 469 case T_CHAR: 470 case T_BYTE: 471 case T_SHORT: 472 case T_INT: 473 if (int_args < Argument::n_int_register_parameters_j) { 474 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 475 } else { 476 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 477 stk_args += 2; 478 } 479 break; 480 case T_VOID: 481 // halves of T_LONG or T_DOUBLE 482 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 483 regs[i].set_bad(); 484 break; 485 case T_LONG: 486 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); 487 // fall through 488 case T_OBJECT: 489 case T_ARRAY: 490 case T_ADDRESS: 491 if (int_args < Argument::n_int_register_parameters_j) { 492 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); 493 } else { 494 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 495 stk_args += 2; 496 } 497 break; 498 case T_FLOAT: 499 if (fp_args < Argument::n_float_register_parameters_j) { 500 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); 501 } else { 502 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 503 stk_args += 2; 504 } 505 break; 506 case T_DOUBLE: 507 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); 508 if (fp_args < Argument::n_float_register_parameters_j) { 509 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); 510 } else { 511 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 512 stk_args += 2; 513 } 514 break; 515 default: 516 ShouldNotReachHere(); 517 break; 518 } 519 } 520 521 return align_up(stk_args, 2); 522 } 523 524 // Patch the callers callsite with entry to compiled code if it exists. 525 static void patch_callers_callsite(MacroAssembler *masm) { 526 Label L; 527 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); 528 __ jcc(Assembler::equal, L); 529 530 // Save the current stack pointer 531 __ mov(r13, rsp); 532 // Schedule the branch target address early. 533 // Call into the VM to patch the caller, then jump to compiled callee 534 // rax isn't live so capture return address while we easily can 535 __ movptr(rax, Address(rsp, 0)); 536 537 // align stack so push_CPU_state doesn't fault 538 __ andptr(rsp, -(StackAlignmentInBytes)); 539 __ push_CPU_state(); 540 __ vzeroupper(); 541 // VM needs caller's callsite 542 // VM needs target method 543 // This needs to be a long call since we will relocate this adapter to 544 // the codeBuffer and it may not reach 545 546 // Allocate argument register save area 547 if (frame::arg_reg_save_area_bytes != 0) { 548 __ subptr(rsp, frame::arg_reg_save_area_bytes); 549 } 550 __ mov(c_rarg0, rbx); 551 __ mov(c_rarg1, rax); 552 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); 553 554 // De-allocate argument register save area 555 if (frame::arg_reg_save_area_bytes != 0) { 556 __ addptr(rsp, frame::arg_reg_save_area_bytes); 557 } 558 559 __ vzeroupper(); 560 __ pop_CPU_state(); 561 // restore sp 562 __ mov(rsp, r13); 563 __ bind(L); 564 } 565 566 567 static void gen_c2i_adapter(MacroAssembler *masm, 568 int total_args_passed, 569 int comp_args_on_stack, 570 const BasicType *sig_bt, 571 const VMRegPair *regs, 572 Label& skip_fixup) { 573 // Before we get into the guts of the C2I adapter, see if we should be here 574 // at all. We've come from compiled code and are attempting to jump to the 575 // interpreter, which means the caller made a static call to get here 576 // (vcalls always get a compiled target if there is one). Check for a 577 // compiled target. If there is one, we need to patch the caller's call. 578 patch_callers_callsite(masm); 579 580 __ bind(skip_fixup); 581 582 // Since all args are passed on the stack, total_args_passed * 583 // Interpreter::stackElementSize is the space we need. Plus 1 because 584 // we also account for the return address location since 585 // we store it first rather than hold it in rax across all the shuffling 586 587 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize; 588 589 // stack is aligned, keep it that way 590 extraspace = align_up(extraspace, 2*wordSize); 591 592 // Get return address 593 __ pop(rax); 594 595 // set senderSP value 596 __ mov(r13, rsp); 597 598 __ subptr(rsp, extraspace); 599 600 // Store the return address in the expected location 601 __ movptr(Address(rsp, 0), rax); 602 603 // Now write the args into the outgoing interpreter space 604 for (int i = 0; i < total_args_passed; i++) { 605 if (sig_bt[i] == T_VOID) { 606 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 607 continue; 608 } 609 610 // offset to start parameters 611 int st_off = (total_args_passed - i) * Interpreter::stackElementSize; 612 int next_off = st_off - Interpreter::stackElementSize; 613 614 // Say 4 args: 615 // i st_off 616 // 0 32 T_LONG 617 // 1 24 T_VOID 618 // 2 16 T_OBJECT 619 // 3 8 T_BOOL 620 // - 0 return address 621 // 622 // However to make thing extra confusing. Because we can fit a long/double in 623 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter 624 // leaves one slot empty and only stores to a single slot. In this case the 625 // slot that is occupied is the T_VOID slot. See I said it was confusing. 626 627 VMReg r_1 = regs[i].first(); 628 VMReg r_2 = regs[i].second(); 629 if (!r_1->is_valid()) { 630 assert(!r_2->is_valid(), ""); 631 continue; 632 } 633 if (r_1->is_stack()) { 634 // memory to memory use rax 635 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; 636 if (!r_2->is_valid()) { 637 // sign extend?? 638 __ movl(rax, Address(rsp, ld_off)); 639 __ movptr(Address(rsp, st_off), rax); 640 641 } else { 642 643 __ movq(rax, Address(rsp, ld_off)); 644 645 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG 646 // T_DOUBLE and T_LONG use two slots in the interpreter 647 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 648 // ld_off == LSW, ld_off+wordSize == MSW 649 // st_off == MSW, next_off == LSW 650 __ movq(Address(rsp, next_off), rax); 651 #ifdef ASSERT 652 // Overwrite the unused slot with known junk 653 __ mov64(rax, CONST64(0xdeadffffdeadaaaa)); 654 __ movptr(Address(rsp, st_off), rax); 655 #endif /* ASSERT */ 656 } else { 657 __ movq(Address(rsp, st_off), rax); 658 } 659 } 660 } else if (r_1->is_Register()) { 661 Register r = r_1->as_Register(); 662 if (!r_2->is_valid()) { 663 // must be only an int (or less ) so move only 32bits to slot 664 // why not sign extend?? 665 __ movl(Address(rsp, st_off), r); 666 } else { 667 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG 668 // T_DOUBLE and T_LONG use two slots in the interpreter 669 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 670 // long/double in gpr 671 #ifdef ASSERT 672 // Overwrite the unused slot with known junk 673 __ mov64(rax, CONST64(0xdeadffffdeadaaab)); 674 __ movptr(Address(rsp, st_off), rax); 675 #endif /* ASSERT */ 676 __ movq(Address(rsp, next_off), r); 677 } else { 678 __ movptr(Address(rsp, st_off), r); 679 } 680 } 681 } else { 682 assert(r_1->is_XMMRegister(), ""); 683 if (!r_2->is_valid()) { 684 // only a float use just part of the slot 685 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister()); 686 } else { 687 #ifdef ASSERT 688 // Overwrite the unused slot with known junk 689 __ mov64(rax, CONST64(0xdeadffffdeadaaac)); 690 __ movptr(Address(rsp, st_off), rax); 691 #endif /* ASSERT */ 692 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister()); 693 } 694 } 695 } 696 697 // Schedule the branch target address early. 698 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset()))); 699 __ jmp(rcx); 700 } 701 702 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, 703 address code_start, address code_end, 704 Label& L_ok) { 705 Label L_fail; 706 __ lea(temp_reg, ExternalAddress(code_start)); 707 __ cmpptr(pc_reg, temp_reg); 708 __ jcc(Assembler::belowEqual, L_fail); 709 __ lea(temp_reg, ExternalAddress(code_end)); 710 __ cmpptr(pc_reg, temp_reg); 711 __ jcc(Assembler::below, L_ok); 712 __ bind(L_fail); 713 } 714 715 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, 716 int total_args_passed, 717 int comp_args_on_stack, 718 const BasicType *sig_bt, 719 const VMRegPair *regs) { 720 721 // Note: r13 contains the senderSP on entry. We must preserve it since 722 // we may do a i2c -> c2i transition if we lose a race where compiled 723 // code goes non-entrant while we get args ready. 724 // In addition we use r13 to locate all the interpreter args as 725 // we must align the stack to 16 bytes on an i2c entry else we 726 // lose alignment we expect in all compiled code and register 727 // save code can segv when fxsave instructions find improperly 728 // aligned stack pointer. 729 730 // Adapters can be frameless because they do not require the caller 731 // to perform additional cleanup work, such as correcting the stack pointer. 732 // An i2c adapter is frameless because the *caller* frame, which is interpreted, 733 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), 734 // even if a callee has modified the stack pointer. 735 // A c2i adapter is frameless because the *callee* frame, which is interpreted, 736 // routinely repairs its caller's stack pointer (from sender_sp, which is set 737 // up via the senderSP register). 738 // In other words, if *either* the caller or callee is interpreted, we can 739 // get the stack pointer repaired after a call. 740 // This is why c2i and i2c adapters cannot be indefinitely composed. 741 // In particular, if a c2i adapter were to somehow call an i2c adapter, 742 // both caller and callee would be compiled methods, and neither would 743 // clean up the stack pointer changes performed by the two adapters. 744 // If this happens, control eventually transfers back to the compiled 745 // caller, but with an uncorrected stack, causing delayed havoc. 746 747 // Pick up the return address 748 __ movptr(rax, Address(rsp, 0)); 749 750 if (VerifyAdapterCalls && 751 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { 752 // So, let's test for cascading c2i/i2c adapters right now. 753 // assert(Interpreter::contains($return_addr) || 754 // StubRoutines::contains($return_addr), 755 // "i2c adapter must return to an interpreter frame"); 756 __ block_comment("verify_i2c { "); 757 Label L_ok; 758 if (Interpreter::code() != NULL) 759 range_check(masm, rax, r11, 760 Interpreter::code()->code_start(), Interpreter::code()->code_end(), 761 L_ok); 762 if (StubRoutines::code1() != NULL) 763 range_check(masm, rax, r11, 764 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), 765 L_ok); 766 if (StubRoutines::code2() != NULL) 767 range_check(masm, rax, r11, 768 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), 769 L_ok); 770 const char* msg = "i2c adapter must return to an interpreter frame"; 771 __ block_comment(msg); 772 __ stop(msg); 773 __ bind(L_ok); 774 __ block_comment("} verify_i2ce "); 775 } 776 777 // Must preserve original SP for loading incoming arguments because 778 // we need to align the outgoing SP for compiled code. 779 __ movptr(r11, rsp); 780 781 // Cut-out for having no stack args. Since up to 2 int/oop args are passed 782 // in registers, we will occasionally have no stack args. 783 int comp_words_on_stack = 0; 784 if (comp_args_on_stack) { 785 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in 786 // registers are below. By subtracting stack0, we either get a negative 787 // number (all values in registers) or the maximum stack slot accessed. 788 789 // Convert 4-byte c2 stack slots to words. 790 comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; 791 // Round up to miminum stack alignment, in wordSize 792 comp_words_on_stack = align_up(comp_words_on_stack, 2); 793 __ subptr(rsp, comp_words_on_stack * wordSize); 794 } 795 796 797 // Ensure compiled code always sees stack at proper alignment 798 __ andptr(rsp, -16); 799 800 // push the return address and misalign the stack that youngest frame always sees 801 // as far as the placement of the call instruction 802 __ push(rax); 803 804 // Put saved SP in another register 805 const Register saved_sp = rax; 806 __ movptr(saved_sp, r11); 807 808 // Will jump to the compiled code just as if compiled code was doing it. 809 // Pre-load the register-jump target early, to schedule it better. 810 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset()))); 811 812 #if INCLUDE_JVMCI 813 if (EnableJVMCI || UseAOT) { 814 // check if this call should be routed towards a specific entry point 815 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0); 816 Label no_alternative_target; 817 __ jcc(Assembler::equal, no_alternative_target); 818 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset()))); 819 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0); 820 __ bind(no_alternative_target); 821 } 822 #endif // INCLUDE_JVMCI 823 824 // Now generate the shuffle code. Pick up all register args and move the 825 // rest through the floating point stack top. 826 for (int i = 0; i < total_args_passed; i++) { 827 if (sig_bt[i] == T_VOID) { 828 // Longs and doubles are passed in native word order, but misaligned 829 // in the 32-bit build. 830 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 831 continue; 832 } 833 834 // Pick up 0, 1 or 2 words from SP+offset. 835 836 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), 837 "scrambled load targets?"); 838 // Load in argument order going down. 839 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize; 840 // Point to interpreter value (vs. tag) 841 int next_off = ld_off - Interpreter::stackElementSize; 842 // 843 // 844 // 845 VMReg r_1 = regs[i].first(); 846 VMReg r_2 = regs[i].second(); 847 if (!r_1->is_valid()) { 848 assert(!r_2->is_valid(), ""); 849 continue; 850 } 851 if (r_1->is_stack()) { 852 // Convert stack slot to an SP offset (+ wordSize to account for return address ) 853 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize; 854 855 // We can use r13 as a temp here because compiled code doesn't need r13 as an input 856 // and if we end up going thru a c2i because of a miss a reasonable value of r13 857 // will be generated. 858 if (!r_2->is_valid()) { 859 // sign extend??? 860 __ movl(r13, Address(saved_sp, ld_off)); 861 __ movptr(Address(rsp, st_off), r13); 862 } else { 863 // 864 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE 865 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case 866 // So we must adjust where to pick up the data to match the interpreter. 867 // 868 // Interpreter local[n] == MSW, local[n+1] == LSW however locals 869 // are accessed as negative so LSW is at LOW address 870 871 // ld_off is MSW so get LSW 872 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 873 next_off : ld_off; 874 __ movq(r13, Address(saved_sp, offset)); 875 // st_off is LSW (i.e. reg.first()) 876 __ movq(Address(rsp, st_off), r13); 877 } 878 } else if (r_1->is_Register()) { // Register argument 879 Register r = r_1->as_Register(); 880 assert(r != rax, "must be different"); 881 if (r_2->is_valid()) { 882 // 883 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE 884 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case 885 // So we must adjust where to pick up the data to match the interpreter. 886 887 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 888 next_off : ld_off; 889 890 // this can be a misaligned move 891 __ movq(r, Address(saved_sp, offset)); 892 } else { 893 // sign extend and use a full word? 894 __ movl(r, Address(saved_sp, ld_off)); 895 } 896 } else { 897 if (!r_2->is_valid()) { 898 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off)); 899 } else { 900 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off)); 901 } 902 } 903 } 904 905 // 6243940 We might end up in handle_wrong_method if 906 // the callee is deoptimized as we race thru here. If that 907 // happens we don't want to take a safepoint because the 908 // caller frame will look interpreted and arguments are now 909 // "compiled" so it is much better to make this transition 910 // invisible to the stack walking code. Unfortunately if 911 // we try and find the callee by normal means a safepoint 912 // is possible. So we stash the desired callee in the thread 913 // and the vm will find there should this case occur. 914 915 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx); 916 917 // put Method* where a c2i would expect should we end up there 918 // only needed becaus eof c2 resolve stubs return Method* as a result in 919 // rax 920 __ mov(rax, rbx); 921 __ jmp(r11); 922 } 923 924 // --------------------------------------------------------------- 925 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, 926 int total_args_passed, 927 int comp_args_on_stack, 928 const BasicType *sig_bt, 929 const VMRegPair *regs, 930 AdapterFingerPrint* fingerprint) { 931 address i2c_entry = __ pc(); 932 933 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); 934 935 // ------------------------------------------------------------------------- 936 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls 937 // to the interpreter. The args start out packed in the compiled layout. They 938 // need to be unpacked into the interpreter layout. This will almost always 939 // require some stack space. We grow the current (compiled) stack, then repack 940 // the args. We finally end in a jump to the generic interpreter entry point. 941 // On exit from the interpreter, the interpreter will restore our SP (lest the 942 // compiled code, which relys solely on SP and not RBP, get sick). 943 944 address c2i_unverified_entry = __ pc(); 945 Label skip_fixup; 946 Label ok; 947 948 Register holder = rax; 949 Register receiver = j_rarg0; 950 Register temp = rbx; 951 952 { 953 __ load_klass(temp, receiver); 954 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset())); 955 __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset())); 956 __ jcc(Assembler::equal, ok); 957 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 958 959 __ bind(ok); 960 // Method might have been compiled since the call site was patched to 961 // interpreted if that is the case treat it as a miss so we can get 962 // the call site corrected. 963 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); 964 __ jcc(Assembler::equal, skip_fixup); 965 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 966 } 967 968 address c2i_entry = __ pc(); 969 970 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); 971 972 __ flush(); 973 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); 974 } 975 976 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, 977 VMRegPair *regs, 978 VMRegPair *regs2, 979 int total_args_passed) { 980 assert(regs2 == NULL, "not needed on x86"); 981 // We return the amount of VMRegImpl stack slots we need to reserve for all 982 // the arguments NOT counting out_preserve_stack_slots. 983 984 // NOTE: These arrays will have to change when c1 is ported 985 #ifdef _WIN64 986 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { 987 c_rarg0, c_rarg1, c_rarg2, c_rarg3 988 }; 989 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { 990 c_farg0, c_farg1, c_farg2, c_farg3 991 }; 992 #else 993 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { 994 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5 995 }; 996 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { 997 c_farg0, c_farg1, c_farg2, c_farg3, 998 c_farg4, c_farg5, c_farg6, c_farg7 999 }; 1000 #endif // _WIN64 1001 1002 1003 uint int_args = 0; 1004 uint fp_args = 0; 1005 uint stk_args = 0; // inc by 2 each time 1006 1007 for (int i = 0; i < total_args_passed; i++) { 1008 switch (sig_bt[i]) { 1009 case T_BOOLEAN: 1010 case T_CHAR: 1011 case T_BYTE: 1012 case T_SHORT: 1013 case T_INT: 1014 if (int_args < Argument::n_int_register_parameters_c) { 1015 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 1016 #ifdef _WIN64 1017 fp_args++; 1018 // Allocate slots for callee to stuff register args the stack. 1019 stk_args += 2; 1020 #endif 1021 } else { 1022 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 1023 stk_args += 2; 1024 } 1025 break; 1026 case T_LONG: 1027 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); 1028 // fall through 1029 case T_OBJECT: 1030 case T_ARRAY: 1031 case T_ADDRESS: 1032 case T_METADATA: 1033 if (int_args < Argument::n_int_register_parameters_c) { 1034 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); 1035 #ifdef _WIN64 1036 fp_args++; 1037 stk_args += 2; 1038 #endif 1039 } else { 1040 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 1041 stk_args += 2; 1042 } 1043 break; 1044 case T_FLOAT: 1045 if (fp_args < Argument::n_float_register_parameters_c) { 1046 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); 1047 #ifdef _WIN64 1048 int_args++; 1049 // Allocate slots for callee to stuff register args the stack. 1050 stk_args += 2; 1051 #endif 1052 } else { 1053 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 1054 stk_args += 2; 1055 } 1056 break; 1057 case T_DOUBLE: 1058 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); 1059 if (fp_args < Argument::n_float_register_parameters_c) { 1060 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); 1061 #ifdef _WIN64 1062 int_args++; 1063 // Allocate slots for callee to stuff register args the stack. 1064 stk_args += 2; 1065 #endif 1066 } else { 1067 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 1068 stk_args += 2; 1069 } 1070 break; 1071 case T_VOID: // Halves of longs and doubles 1072 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 1073 regs[i].set_bad(); 1074 break; 1075 default: 1076 ShouldNotReachHere(); 1077 break; 1078 } 1079 } 1080 #ifdef _WIN64 1081 // windows abi requires that we always allocate enough stack space 1082 // for 4 64bit registers to be stored down. 1083 if (stk_args < 8) { 1084 stk_args = 8; 1085 } 1086 #endif // _WIN64 1087 1088 return stk_args; 1089 } 1090 1091 // On 64 bit we will store integer like items to the stack as 1092 // 64 bits items (sparc abi) even though java would only store 1093 // 32bits for a parameter. On 32bit it will simply be 32 bits 1094 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 1095 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1096 if (src.first()->is_stack()) { 1097 if (dst.first()->is_stack()) { 1098 // stack to stack 1099 __ movslq(rax, Address(rbp, reg2offset_in(src.first()))); 1100 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1101 } else { 1102 // stack to reg 1103 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1104 } 1105 } else if (dst.first()->is_stack()) { 1106 // reg to stack 1107 // Do we really have to sign extend??? 1108 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); 1109 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1110 } else { 1111 // Do we really have to sign extend??? 1112 // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); 1113 if (dst.first() != src.first()) { 1114 __ movq(dst.first()->as_Register(), src.first()->as_Register()); 1115 } 1116 } 1117 } 1118 1119 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1120 if (src.first()->is_stack()) { 1121 if (dst.first()->is_stack()) { 1122 // stack to stack 1123 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1124 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1125 } else { 1126 // stack to reg 1127 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1128 } 1129 } else if (dst.first()->is_stack()) { 1130 // reg to stack 1131 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1132 } else { 1133 if (dst.first() != src.first()) { 1134 __ movq(dst.first()->as_Register(), src.first()->as_Register()); 1135 } 1136 } 1137 } 1138 1139 // An oop arg. Must pass a handle not the oop itself 1140 static void object_move(MacroAssembler* masm, 1141 OopMap* map, 1142 int oop_handle_offset, 1143 int framesize_in_slots, 1144 VMRegPair src, 1145 VMRegPair dst, 1146 bool is_receiver, 1147 int* receiver_offset) { 1148 1149 // must pass a handle. First figure out the location we use as a handle 1150 1151 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); 1152 1153 // See if oop is NULL if it is we need no handle 1154 1155 if (src.first()->is_stack()) { 1156 1157 // Oop is already on the stack as an argument 1158 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1159 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1160 if (is_receiver) { 1161 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1162 } 1163 1164 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); 1165 __ lea(rHandle, Address(rbp, reg2offset_in(src.first()))); 1166 // conditionally move a NULL 1167 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); 1168 } else { 1169 1170 // Oop is in an a register we must store it to the space we reserve 1171 // on the stack for oop_handles and pass a handle if oop is non-NULL 1172 1173 const Register rOop = src.first()->as_Register(); 1174 int oop_slot; 1175 if (rOop == j_rarg0) 1176 oop_slot = 0; 1177 else if (rOop == j_rarg1) 1178 oop_slot = 1; 1179 else if (rOop == j_rarg2) 1180 oop_slot = 2; 1181 else if (rOop == j_rarg3) 1182 oop_slot = 3; 1183 else if (rOop == j_rarg4) 1184 oop_slot = 4; 1185 else { 1186 assert(rOop == j_rarg5, "wrong register"); 1187 oop_slot = 5; 1188 } 1189 1190 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 1191 int offset = oop_slot*VMRegImpl::stack_slot_size; 1192 1193 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1194 // Store oop in handle area, may be NULL 1195 __ movptr(Address(rsp, offset), rOop); 1196 if (is_receiver) { 1197 *receiver_offset = offset; 1198 } 1199 1200 __ cmpptr(rOop, (int32_t)NULL_WORD); 1201 __ lea(rHandle, Address(rsp, offset)); 1202 // conditionally move a NULL from the handle area where it was just stored 1203 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); 1204 } 1205 1206 // If arg is on the stack then place it otherwise it is already in correct reg. 1207 if (dst.first()->is_stack()) { 1208 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); 1209 } 1210 } 1211 1212 // A float arg may have to do float reg int reg conversion 1213 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1214 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 1215 1216 // The calling conventions assures us that each VMregpair is either 1217 // all really one physical register or adjacent stack slots. 1218 // This greatly simplifies the cases here compared to sparc. 1219 1220 if (src.first()->is_stack()) { 1221 if (dst.first()->is_stack()) { 1222 __ movl(rax, Address(rbp, reg2offset_in(src.first()))); 1223 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); 1224 } else { 1225 // stack to reg 1226 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 1227 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); 1228 } 1229 } else if (dst.first()->is_stack()) { 1230 // reg to stack 1231 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 1232 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 1233 } else { 1234 // reg to reg 1235 // In theory these overlap but the ordering is such that this is likely a nop 1236 if ( src.first() != dst.first()) { 1237 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 1238 } 1239 } 1240 } 1241 1242 // A long move 1243 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1244 1245 // The calling conventions assures us that each VMregpair is either 1246 // all really one physical register or adjacent stack slots. 1247 // This greatly simplifies the cases here compared to sparc. 1248 1249 if (src.is_single_phys_reg() ) { 1250 if (dst.is_single_phys_reg()) { 1251 if (dst.first() != src.first()) { 1252 __ mov(dst.first()->as_Register(), src.first()->as_Register()); 1253 } 1254 } else { 1255 assert(dst.is_single_reg(), "not a stack pair"); 1256 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1257 } 1258 } else if (dst.is_single_phys_reg()) { 1259 assert(src.is_single_reg(), "not a stack pair"); 1260 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); 1261 } else { 1262 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 1263 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1264 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1265 } 1266 } 1267 1268 // A double move 1269 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1270 1271 // The calling conventions assures us that each VMregpair is either 1272 // all really one physical register or adjacent stack slots. 1273 // This greatly simplifies the cases here compared to sparc. 1274 1275 if (src.is_single_phys_reg() ) { 1276 if (dst.is_single_phys_reg()) { 1277 // In theory these overlap but the ordering is such that this is likely a nop 1278 if ( src.first() != dst.first()) { 1279 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 1280 } 1281 } else { 1282 assert(dst.is_single_reg(), "not a stack pair"); 1283 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 1284 } 1285 } else if (dst.is_single_phys_reg()) { 1286 assert(src.is_single_reg(), "not a stack pair"); 1287 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); 1288 } else { 1289 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 1290 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1291 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1292 } 1293 } 1294 1295 1296 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1297 // We always ignore the frame_slots arg and just use the space just below frame pointer 1298 // which by this time is free to use 1299 switch (ret_type) { 1300 case T_FLOAT: 1301 __ movflt(Address(rbp, -wordSize), xmm0); 1302 break; 1303 case T_DOUBLE: 1304 __ movdbl(Address(rbp, -wordSize), xmm0); 1305 break; 1306 case T_VOID: break; 1307 default: { 1308 __ movptr(Address(rbp, -wordSize), rax); 1309 } 1310 } 1311 } 1312 1313 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1314 // We always ignore the frame_slots arg and just use the space just below frame pointer 1315 // which by this time is free to use 1316 switch (ret_type) { 1317 case T_FLOAT: 1318 __ movflt(xmm0, Address(rbp, -wordSize)); 1319 break; 1320 case T_DOUBLE: 1321 __ movdbl(xmm0, Address(rbp, -wordSize)); 1322 break; 1323 case T_VOID: break; 1324 default: { 1325 __ movptr(rax, Address(rbp, -wordSize)); 1326 } 1327 } 1328 } 1329 1330 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1331 for ( int i = first_arg ; i < arg_count ; i++ ) { 1332 if (args[i].first()->is_Register()) { 1333 __ push(args[i].first()->as_Register()); 1334 } else if (args[i].first()->is_XMMRegister()) { 1335 __ subptr(rsp, 2*wordSize); 1336 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister()); 1337 } 1338 } 1339 } 1340 1341 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1342 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { 1343 if (args[i].first()->is_Register()) { 1344 __ pop(args[i].first()->as_Register()); 1345 } else if (args[i].first()->is_XMMRegister()) { 1346 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0)); 1347 __ addptr(rsp, 2*wordSize); 1348 } 1349 } 1350 } 1351 1352 1353 static void save_or_restore_arguments(MacroAssembler* masm, 1354 const int stack_slots, 1355 const int total_in_args, 1356 const int arg_save_area, 1357 OopMap* map, 1358 VMRegPair* in_regs, 1359 BasicType* in_sig_bt) { 1360 // if map is non-NULL then the code should store the values, 1361 // otherwise it should load them. 1362 int slot = arg_save_area; 1363 // Save down double word first 1364 for ( int i = 0; i < total_in_args; i++) { 1365 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) { 1366 int offset = slot * VMRegImpl::stack_slot_size; 1367 slot += VMRegImpl::slots_per_word; 1368 assert(slot <= stack_slots, "overflow"); 1369 if (map != NULL) { 1370 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); 1371 } else { 1372 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); 1373 } 1374 } 1375 if (in_regs[i].first()->is_Register() && 1376 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { 1377 int offset = slot * VMRegImpl::stack_slot_size; 1378 if (map != NULL) { 1379 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); 1380 if (in_sig_bt[i] == T_ARRAY) { 1381 map->set_oop(VMRegImpl::stack2reg(slot));; 1382 } 1383 } else { 1384 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); 1385 } 1386 slot += VMRegImpl::slots_per_word; 1387 } 1388 } 1389 // Save or restore single word registers 1390 for ( int i = 0; i < total_in_args; i++) { 1391 if (in_regs[i].first()->is_Register()) { 1392 int offset = slot * VMRegImpl::stack_slot_size; 1393 slot++; 1394 assert(slot <= stack_slots, "overflow"); 1395 1396 // Value is in an input register pass we must flush it to the stack 1397 const Register reg = in_regs[i].first()->as_Register(); 1398 switch (in_sig_bt[i]) { 1399 case T_BOOLEAN: 1400 case T_CHAR: 1401 case T_BYTE: 1402 case T_SHORT: 1403 case T_INT: 1404 if (map != NULL) { 1405 __ movl(Address(rsp, offset), reg); 1406 } else { 1407 __ movl(reg, Address(rsp, offset)); 1408 } 1409 break; 1410 case T_ARRAY: 1411 case T_LONG: 1412 // handled above 1413 break; 1414 case T_OBJECT: 1415 default: ShouldNotReachHere(); 1416 } 1417 } else if (in_regs[i].first()->is_XMMRegister()) { 1418 if (in_sig_bt[i] == T_FLOAT) { 1419 int offset = slot * VMRegImpl::stack_slot_size; 1420 slot++; 1421 assert(slot <= stack_slots, "overflow"); 1422 if (map != NULL) { 1423 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); 1424 } else { 1425 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); 1426 } 1427 } 1428 } else if (in_regs[i].first()->is_stack()) { 1429 if (in_sig_bt[i] == T_ARRAY && map != NULL) { 1430 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1431 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); 1432 } 1433 } 1434 } 1435 } 1436 1437 1438 // Check GCLocker::needs_gc and enter the runtime if it's true. This 1439 // keeps a new JNI critical region from starting until a GC has been 1440 // forced. Save down any oops in registers and describe them in an 1441 // OopMap. 1442 static void check_needs_gc_for_critical_native(MacroAssembler* masm, 1443 int stack_slots, 1444 int total_c_args, 1445 int total_in_args, 1446 int arg_save_area, 1447 OopMapSet* oop_maps, 1448 VMRegPair* in_regs, 1449 BasicType* in_sig_bt) { 1450 __ block_comment("check GCLocker::needs_gc"); 1451 Label cont; 1452 __ cmp8(ExternalAddress((address)GCLocker::needs_gc_address()), false); 1453 __ jcc(Assembler::equal, cont); 1454 1455 // Save down any incoming oops and call into the runtime to halt for a GC 1456 1457 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1458 save_or_restore_arguments(masm, stack_slots, total_in_args, 1459 arg_save_area, map, in_regs, in_sig_bt); 1460 1461 address the_pc = __ pc(); 1462 oop_maps->add_gc_map( __ offset(), map); 1463 __ set_last_Java_frame(rsp, noreg, the_pc); 1464 1465 __ block_comment("block_for_jni_critical"); 1466 __ movptr(c_rarg0, r15_thread); 1467 __ mov(r12, rsp); // remember sp 1468 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 1469 __ andptr(rsp, -16); // align stack as required by ABI 1470 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical))); 1471 __ mov(rsp, r12); // restore sp 1472 __ reinit_heapbase(); 1473 1474 __ reset_last_Java_frame(false); 1475 1476 save_or_restore_arguments(masm, stack_slots, total_in_args, 1477 arg_save_area, NULL, in_regs, in_sig_bt); 1478 __ bind(cont); 1479 #ifdef ASSERT 1480 if (StressCriticalJNINatives) { 1481 // Stress register saving 1482 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1483 save_or_restore_arguments(masm, stack_slots, total_in_args, 1484 arg_save_area, map, in_regs, in_sig_bt); 1485 // Destroy argument registers 1486 for (int i = 0; i < total_in_args - 1; i++) { 1487 if (in_regs[i].first()->is_Register()) { 1488 const Register reg = in_regs[i].first()->as_Register(); 1489 __ xorptr(reg, reg); 1490 } else if (in_regs[i].first()->is_XMMRegister()) { 1491 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister()); 1492 } else if (in_regs[i].first()->is_FloatRegister()) { 1493 ShouldNotReachHere(); 1494 } else if (in_regs[i].first()->is_stack()) { 1495 // Nothing to do 1496 } else { 1497 ShouldNotReachHere(); 1498 } 1499 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) { 1500 i++; 1501 } 1502 } 1503 1504 save_or_restore_arguments(masm, stack_slots, total_in_args, 1505 arg_save_area, NULL, in_regs, in_sig_bt); 1506 } 1507 #endif 1508 } 1509 1510 // Unpack an array argument into a pointer to the body and the length 1511 // if the array is non-null, otherwise pass 0 for both. 1512 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { 1513 Register tmp_reg = rax; 1514 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg, 1515 "possible collision"); 1516 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg, 1517 "possible collision"); 1518 1519 __ block_comment("unpack_array_argument {"); 1520 1521 // Pass the length, ptr pair 1522 Label is_null, done; 1523 VMRegPair tmp; 1524 tmp.set_ptr(tmp_reg->as_VMReg()); 1525 if (reg.first()->is_stack()) { 1526 // Load the arg up from the stack 1527 move_ptr(masm, reg, tmp); 1528 reg = tmp; 1529 } 1530 __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); 1531 __ jccb(Assembler::equal, is_null); 1532 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type))); 1533 move_ptr(masm, tmp, body_arg); 1534 // load the length relative to the body. 1535 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() - 1536 arrayOopDesc::base_offset_in_bytes(in_elem_type))); 1537 move32_64(masm, tmp, length_arg); 1538 __ jmpb(done); 1539 __ bind(is_null); 1540 // Pass zeros 1541 __ xorptr(tmp_reg, tmp_reg); 1542 move_ptr(masm, tmp, body_arg); 1543 move32_64(masm, tmp, length_arg); 1544 __ bind(done); 1545 1546 __ block_comment("} unpack_array_argument"); 1547 } 1548 1549 1550 // Different signatures may require very different orders for the move 1551 // to avoid clobbering other arguments. There's no simple way to 1552 // order them safely. Compute a safe order for issuing stores and 1553 // break any cycles in those stores. This code is fairly general but 1554 // it's not necessary on the other platforms so we keep it in the 1555 // platform dependent code instead of moving it into a shared file. 1556 // (See bugs 7013347 & 7145024.) 1557 // Note that this code is specific to LP64. 1558 class ComputeMoveOrder: public StackObj { 1559 class MoveOperation: public ResourceObj { 1560 friend class ComputeMoveOrder; 1561 private: 1562 VMRegPair _src; 1563 VMRegPair _dst; 1564 int _src_index; 1565 int _dst_index; 1566 bool _processed; 1567 MoveOperation* _next; 1568 MoveOperation* _prev; 1569 1570 static int get_id(VMRegPair r) { 1571 return r.first()->value(); 1572 } 1573 1574 public: 1575 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): 1576 _src(src) 1577 , _src_index(src_index) 1578 , _dst(dst) 1579 , _dst_index(dst_index) 1580 , _next(NULL) 1581 , _prev(NULL) 1582 , _processed(false) { 1583 } 1584 1585 VMRegPair src() const { return _src; } 1586 int src_id() const { return get_id(src()); } 1587 int src_index() const { return _src_index; } 1588 VMRegPair dst() const { return _dst; } 1589 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; } 1590 int dst_index() const { return _dst_index; } 1591 int dst_id() const { return get_id(dst()); } 1592 MoveOperation* next() const { return _next; } 1593 MoveOperation* prev() const { return _prev; } 1594 void set_processed() { _processed = true; } 1595 bool is_processed() const { return _processed; } 1596 1597 // insert 1598 void break_cycle(VMRegPair temp_register) { 1599 // create a new store following the last store 1600 // to move from the temp_register to the original 1601 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst()); 1602 1603 // break the cycle of links and insert new_store at the end 1604 // break the reverse link. 1605 MoveOperation* p = prev(); 1606 assert(p->next() == this, "must be"); 1607 _prev = NULL; 1608 p->_next = new_store; 1609 new_store->_prev = p; 1610 1611 // change the original store to save it's value in the temp. 1612 set_dst(-1, temp_register); 1613 } 1614 1615 void link(GrowableArray<MoveOperation*>& killer) { 1616 // link this store in front the store that it depends on 1617 MoveOperation* n = killer.at_grow(src_id(), NULL); 1618 if (n != NULL) { 1619 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet"); 1620 _next = n; 1621 n->_prev = this; 1622 } 1623 } 1624 }; 1625 1626 private: 1627 GrowableArray<MoveOperation*> edges; 1628 1629 public: 1630 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, 1631 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) { 1632 // Move operations where the dest is the stack can all be 1633 // scheduled first since they can't interfere with the other moves. 1634 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { 1635 if (in_sig_bt[i] == T_ARRAY) { 1636 c_arg--; 1637 if (out_regs[c_arg].first()->is_stack() && 1638 out_regs[c_arg + 1].first()->is_stack()) { 1639 arg_order.push(i); 1640 arg_order.push(c_arg); 1641 } else { 1642 if (out_regs[c_arg].first()->is_stack() || 1643 in_regs[i].first() == out_regs[c_arg].first()) { 1644 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]); 1645 } else { 1646 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); 1647 } 1648 } 1649 } else if (in_sig_bt[i] == T_VOID) { 1650 arg_order.push(i); 1651 arg_order.push(c_arg); 1652 } else { 1653 if (out_regs[c_arg].first()->is_stack() || 1654 in_regs[i].first() == out_regs[c_arg].first()) { 1655 arg_order.push(i); 1656 arg_order.push(c_arg); 1657 } else { 1658 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); 1659 } 1660 } 1661 } 1662 // Break any cycles in the register moves and emit the in the 1663 // proper order. 1664 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg); 1665 for (int i = 0; i < stores->length(); i++) { 1666 arg_order.push(stores->at(i)->src_index()); 1667 arg_order.push(stores->at(i)->dst_index()); 1668 } 1669 } 1670 1671 // Collected all the move operations 1672 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { 1673 if (src.first() == dst.first()) return; 1674 edges.append(new MoveOperation(src_index, src, dst_index, dst)); 1675 } 1676 1677 // Walk the edges breaking cycles between moves. The result list 1678 // can be walked in order to produce the proper set of loads 1679 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) { 1680 // Record which moves kill which values 1681 GrowableArray<MoveOperation*> killer; 1682 for (int i = 0; i < edges.length(); i++) { 1683 MoveOperation* s = edges.at(i); 1684 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer"); 1685 killer.at_put_grow(s->dst_id(), s, NULL); 1686 } 1687 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL, 1688 "make sure temp isn't in the registers that are killed"); 1689 1690 // create links between loads and stores 1691 for (int i = 0; i < edges.length(); i++) { 1692 edges.at(i)->link(killer); 1693 } 1694 1695 // at this point, all the move operations are chained together 1696 // in a doubly linked list. Processing it backwards finds 1697 // the beginning of the chain, forwards finds the end. If there's 1698 // a cycle it can be broken at any point, so pick an edge and walk 1699 // backward until the list ends or we end where we started. 1700 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>(); 1701 for (int e = 0; e < edges.length(); e++) { 1702 MoveOperation* s = edges.at(e); 1703 if (!s->is_processed()) { 1704 MoveOperation* start = s; 1705 // search for the beginning of the chain or cycle 1706 while (start->prev() != NULL && start->prev() != s) { 1707 start = start->prev(); 1708 } 1709 if (start->prev() == s) { 1710 start->break_cycle(temp_register); 1711 } 1712 // walk the chain forward inserting to store list 1713 while (start != NULL) { 1714 stores->append(start); 1715 start->set_processed(); 1716 start = start->next(); 1717 } 1718 } 1719 } 1720 return stores; 1721 } 1722 }; 1723 1724 static void verify_oop_args(MacroAssembler* masm, 1725 const methodHandle& method, 1726 const BasicType* sig_bt, 1727 const VMRegPair* regs) { 1728 Register temp_reg = rbx; // not part of any compiled calling seq 1729 if (VerifyOops) { 1730 for (int i = 0; i < method->size_of_parameters(); i++) { 1731 if (sig_bt[i] == T_OBJECT || 1732 sig_bt[i] == T_ARRAY) { 1733 VMReg r = regs[i].first(); 1734 assert(r->is_valid(), "bad oop arg"); 1735 if (r->is_stack()) { 1736 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1737 __ verify_oop(temp_reg); 1738 } else { 1739 __ verify_oop(r->as_Register()); 1740 } 1741 } 1742 } 1743 } 1744 } 1745 1746 static void gen_special_dispatch(MacroAssembler* masm, 1747 const methodHandle& method, 1748 const BasicType* sig_bt, 1749 const VMRegPair* regs) { 1750 verify_oop_args(masm, method, sig_bt, regs); 1751 vmIntrinsics::ID iid = method->intrinsic_id(); 1752 1753 // Now write the args into the outgoing interpreter space 1754 bool has_receiver = false; 1755 Register receiver_reg = noreg; 1756 int member_arg_pos = -1; 1757 Register member_reg = noreg; 1758 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); 1759 if (ref_kind != 0) { 1760 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument 1761 member_reg = rbx; // known to be free at this point 1762 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); 1763 } else if (iid == vmIntrinsics::_invokeBasic) { 1764 has_receiver = true; 1765 } else { 1766 fatal("unexpected intrinsic id %d", iid); 1767 } 1768 1769 if (member_reg != noreg) { 1770 // Load the member_arg into register, if necessary. 1771 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); 1772 VMReg r = regs[member_arg_pos].first(); 1773 if (r->is_stack()) { 1774 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1775 } else { 1776 // no data motion is needed 1777 member_reg = r->as_Register(); 1778 } 1779 } 1780 1781 if (has_receiver) { 1782 // Make sure the receiver is loaded into a register. 1783 assert(method->size_of_parameters() > 0, "oob"); 1784 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); 1785 VMReg r = regs[0].first(); 1786 assert(r->is_valid(), "bad receiver arg"); 1787 if (r->is_stack()) { 1788 // Porting note: This assumes that compiled calling conventions always 1789 // pass the receiver oop in a register. If this is not true on some 1790 // platform, pick a temp and load the receiver from stack. 1791 fatal("receiver always in a register"); 1792 receiver_reg = j_rarg0; // known to be free at this point 1793 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1794 } else { 1795 // no data motion is needed 1796 receiver_reg = r->as_Register(); 1797 } 1798 } 1799 1800 // Figure out which address we are really jumping to: 1801 MethodHandles::generate_method_handle_dispatch(masm, iid, 1802 receiver_reg, member_reg, /*for_compiler_entry:*/ true); 1803 } 1804 1805 // --------------------------------------------------------------------------- 1806 // Generate a native wrapper for a given method. The method takes arguments 1807 // in the Java compiled code convention, marshals them to the native 1808 // convention (handlizes oops, etc), transitions to native, makes the call, 1809 // returns to java state (possibly blocking), unhandlizes any result and 1810 // returns. 1811 // 1812 // Critical native functions are a shorthand for the use of 1813 // GetPrimtiveArrayCritical and disallow the use of any other JNI 1814 // functions. The wrapper is expected to unpack the arguments before 1815 // passing them to the callee and perform checks before and after the 1816 // native call to ensure that they GCLocker 1817 // lock_critical/unlock_critical semantics are followed. Some other 1818 // parts of JNI setup are skipped like the tear down of the JNI handle 1819 // block and the check for pending exceptions it's impossible for them 1820 // to be thrown. 1821 // 1822 // They are roughly structured like this: 1823 // if (GCLocker::needs_gc()) 1824 // SharedRuntime::block_for_jni_critical(); 1825 // tranistion to thread_in_native 1826 // unpack arrray arguments and call native entry point 1827 // check for safepoint in progress 1828 // check if any thread suspend flags are set 1829 // call into JVM and possible unlock the JNI critical 1830 // if a GC was suppressed while in the critical native. 1831 // transition back to thread_in_Java 1832 // return to caller 1833 // 1834 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, 1835 const methodHandle& method, 1836 int compile_id, 1837 BasicType* in_sig_bt, 1838 VMRegPair* in_regs, 1839 BasicType ret_type) { 1840 if (method->is_method_handle_intrinsic()) { 1841 vmIntrinsics::ID iid = method->intrinsic_id(); 1842 intptr_t start = (intptr_t)__ pc(); 1843 int vep_offset = ((intptr_t)__ pc()) - start; 1844 gen_special_dispatch(masm, 1845 method, 1846 in_sig_bt, 1847 in_regs); 1848 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period 1849 __ flush(); 1850 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually 1851 return nmethod::new_native_nmethod(method, 1852 compile_id, 1853 masm->code(), 1854 vep_offset, 1855 frame_complete, 1856 stack_slots / VMRegImpl::slots_per_word, 1857 in_ByteSize(-1), 1858 in_ByteSize(-1), 1859 (OopMapSet*)NULL); 1860 } 1861 bool is_critical_native = true; 1862 address native_func = method->critical_native_function(); 1863 if (native_func == NULL) { 1864 native_func = method->native_function(); 1865 is_critical_native = false; 1866 } 1867 assert(native_func != NULL, "must have function"); 1868 1869 // An OopMap for lock (and class if static) 1870 OopMapSet *oop_maps = new OopMapSet(); 1871 intptr_t start = (intptr_t)__ pc(); 1872 1873 // We have received a description of where all the java arg are located 1874 // on entry to the wrapper. We need to convert these args to where 1875 // the jni function will expect them. To figure out where they go 1876 // we convert the java signature to a C signature by inserting 1877 // the hidden arguments as arg[0] and possibly arg[1] (static method) 1878 1879 const int total_in_args = method->size_of_parameters(); 1880 int total_c_args = total_in_args; 1881 if (!is_critical_native) { 1882 total_c_args += 1; 1883 if (method->is_static()) { 1884 total_c_args++; 1885 } 1886 } else { 1887 for (int i = 0; i < total_in_args; i++) { 1888 if (in_sig_bt[i] == T_ARRAY) { 1889 total_c_args++; 1890 } 1891 } 1892 } 1893 1894 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); 1895 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); 1896 BasicType* in_elem_bt = NULL; 1897 1898 int argc = 0; 1899 if (!is_critical_native) { 1900 out_sig_bt[argc++] = T_ADDRESS; 1901 if (method->is_static()) { 1902 out_sig_bt[argc++] = T_OBJECT; 1903 } 1904 1905 for (int i = 0; i < total_in_args ; i++ ) { 1906 out_sig_bt[argc++] = in_sig_bt[i]; 1907 } 1908 } else { 1909 Thread* THREAD = Thread::current(); 1910 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); 1911 SignatureStream ss(method->signature()); 1912 for (int i = 0; i < total_in_args ; i++ ) { 1913 if (in_sig_bt[i] == T_ARRAY) { 1914 // Arrays are passed as int, elem* pair 1915 out_sig_bt[argc++] = T_INT; 1916 out_sig_bt[argc++] = T_ADDRESS; 1917 Symbol* atype = ss.as_symbol(CHECK_NULL); 1918 const char* at = atype->as_C_string(); 1919 if (strlen(at) == 2) { 1920 assert(at[0] == '[', "must be"); 1921 switch (at[1]) { 1922 case 'B': in_elem_bt[i] = T_BYTE; break; 1923 case 'C': in_elem_bt[i] = T_CHAR; break; 1924 case 'D': in_elem_bt[i] = T_DOUBLE; break; 1925 case 'F': in_elem_bt[i] = T_FLOAT; break; 1926 case 'I': in_elem_bt[i] = T_INT; break; 1927 case 'J': in_elem_bt[i] = T_LONG; break; 1928 case 'S': in_elem_bt[i] = T_SHORT; break; 1929 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; 1930 default: ShouldNotReachHere(); 1931 } 1932 } 1933 } else { 1934 out_sig_bt[argc++] = in_sig_bt[i]; 1935 in_elem_bt[i] = T_VOID; 1936 } 1937 if (in_sig_bt[i] != T_VOID) { 1938 assert(in_sig_bt[i] == ss.type(), "must match"); 1939 ss.next(); 1940 } 1941 } 1942 } 1943 1944 // Now figure out where the args must be stored and how much stack space 1945 // they require. 1946 int out_arg_slots; 1947 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 1948 1949 // Compute framesize for the wrapper. We need to handlize all oops in 1950 // incoming registers 1951 1952 // Calculate the total number of stack slots we will need. 1953 1954 // First count the abi requirement plus all of the outgoing args 1955 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 1956 1957 // Now the space for the inbound oop handle area 1958 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers 1959 if (is_critical_native) { 1960 // Critical natives may have to call out so they need a save area 1961 // for register arguments. 1962 int double_slots = 0; 1963 int single_slots = 0; 1964 for ( int i = 0; i < total_in_args; i++) { 1965 if (in_regs[i].first()->is_Register()) { 1966 const Register reg = in_regs[i].first()->as_Register(); 1967 switch (in_sig_bt[i]) { 1968 case T_BOOLEAN: 1969 case T_BYTE: 1970 case T_SHORT: 1971 case T_CHAR: 1972 case T_INT: single_slots++; break; 1973 case T_ARRAY: // specific to LP64 (7145024) 1974 case T_LONG: double_slots++; break; 1975 default: ShouldNotReachHere(); 1976 } 1977 } else if (in_regs[i].first()->is_XMMRegister()) { 1978 switch (in_sig_bt[i]) { 1979 case T_FLOAT: single_slots++; break; 1980 case T_DOUBLE: double_slots++; break; 1981 default: ShouldNotReachHere(); 1982 } 1983 } else if (in_regs[i].first()->is_FloatRegister()) { 1984 ShouldNotReachHere(); 1985 } 1986 } 1987 total_save_slots = double_slots * 2 + single_slots; 1988 // align the save area 1989 if (double_slots != 0) { 1990 stack_slots = align_up(stack_slots, 2); 1991 } 1992 } 1993 1994 int oop_handle_offset = stack_slots; 1995 stack_slots += total_save_slots; 1996 1997 // Now any space we need for handlizing a klass if static method 1998 1999 int klass_slot_offset = 0; 2000 int klass_offset = -1; 2001 int lock_slot_offset = 0; 2002 bool is_static = false; 2003 2004 if (method->is_static()) { 2005 klass_slot_offset = stack_slots; 2006 stack_slots += VMRegImpl::slots_per_word; 2007 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; 2008 is_static = true; 2009 } 2010 2011 // Plus a lock if needed 2012 2013 if (method->is_synchronized()) { 2014 lock_slot_offset = stack_slots; 2015 stack_slots += VMRegImpl::slots_per_word; 2016 } 2017 2018 // Now a place (+2) to save return values or temp during shuffling 2019 // + 4 for return address (which we own) and saved rbp 2020 stack_slots += 6; 2021 2022 // Ok The space we have allocated will look like: 2023 // 2024 // 2025 // FP-> | | 2026 // |---------------------| 2027 // | 2 slots for moves | 2028 // |---------------------| 2029 // | lock box (if sync) | 2030 // |---------------------| <- lock_slot_offset 2031 // | klass (if static) | 2032 // |---------------------| <- klass_slot_offset 2033 // | oopHandle area | 2034 // |---------------------| <- oop_handle_offset (6 java arg registers) 2035 // | outbound memory | 2036 // | based arguments | 2037 // | | 2038 // |---------------------| 2039 // | | 2040 // SP-> | out_preserved_slots | 2041 // 2042 // 2043 2044 2045 // Now compute actual number of stack words we need rounding to make 2046 // stack properly aligned. 2047 stack_slots = align_up(stack_slots, StackAlignmentInSlots); 2048 2049 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2050 2051 // First thing make an ic check to see if we should even be here 2052 2053 // We are free to use all registers as temps without saving them and 2054 // restoring them except rbp. rbp is the only callee save register 2055 // as far as the interpreter and the compiler(s) are concerned. 2056 2057 2058 const Register ic_reg = rax; 2059 const Register receiver = j_rarg0; 2060 2061 Label hit; 2062 Label exception_pending; 2063 2064 assert_different_registers(ic_reg, receiver, rscratch1); 2065 __ verify_oop(receiver); 2066 __ load_klass(rscratch1, receiver); 2067 __ cmpq(ic_reg, rscratch1); 2068 __ jcc(Assembler::equal, hit); 2069 2070 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 2071 2072 // Verified entry point must be aligned 2073 __ align(8); 2074 2075 __ bind(hit); 2076 2077 int vep_offset = ((intptr_t)__ pc()) - start; 2078 2079 #ifdef COMPILER1 2080 // For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available. 2081 if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) { 2082 inline_check_hashcode_from_object_header(masm, method, j_rarg0 /*obj_reg*/, rax /*result*/); 2083 } 2084 #endif // COMPILER1 2085 2086 // The instruction at the verified entry point must be 5 bytes or longer 2087 // because it can be patched on the fly by make_non_entrant. The stack bang 2088 // instruction fits that requirement. 2089 2090 // Generate stack overflow check 2091 2092 if (UseStackBanging) { 2093 __ bang_stack_with_offset((int)JavaThread::stack_shadow_zone_size()); 2094 } else { 2095 // need a 5 byte instruction to allow MT safe patching to non-entrant 2096 __ fat_nop(); 2097 } 2098 2099 // Generate a new frame for the wrapper. 2100 __ enter(); 2101 // -2 because return address is already present and so is saved rbp 2102 __ subptr(rsp, stack_size - 2*wordSize); 2103 2104 // Frame is now completed as far as size and linkage. 2105 int frame_complete = ((intptr_t)__ pc()) - start; 2106 2107 if (UseRTMLocking) { 2108 // Abort RTM transaction before calling JNI 2109 // because critical section will be large and will be 2110 // aborted anyway. Also nmethod could be deoptimized. 2111 __ xabort(0); 2112 } 2113 2114 #ifdef ASSERT 2115 { 2116 Label L; 2117 __ mov(rax, rsp); 2118 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI) 2119 __ cmpptr(rax, rsp); 2120 __ jcc(Assembler::equal, L); 2121 __ stop("improperly aligned stack"); 2122 __ bind(L); 2123 } 2124 #endif /* ASSERT */ 2125 2126 2127 // We use r14 as the oop handle for the receiver/klass 2128 // It is callee save so it survives the call to native 2129 2130 const Register oop_handle_reg = r14; 2131 2132 if (is_critical_native) { 2133 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, 2134 oop_handle_offset, oop_maps, in_regs, in_sig_bt); 2135 } 2136 2137 // 2138 // We immediately shuffle the arguments so that any vm call we have to 2139 // make from here on out (sync slow path, jvmti, etc.) we will have 2140 // captured the oops from our caller and have a valid oopMap for 2141 // them. 2142 2143 // ----------------- 2144 // The Grand Shuffle 2145 2146 // The Java calling convention is either equal (linux) or denser (win64) than the 2147 // c calling convention. However the because of the jni_env argument the c calling 2148 // convention always has at least one more (and two for static) arguments than Java. 2149 // Therefore if we move the args from java -> c backwards then we will never have 2150 // a register->register conflict and we don't have to build a dependency graph 2151 // and figure out how to break any cycles. 2152 // 2153 2154 // Record esp-based slot for receiver on stack for non-static methods 2155 int receiver_offset = -1; 2156 2157 // This is a trick. We double the stack slots so we can claim 2158 // the oops in the caller's frame. Since we are sure to have 2159 // more args than the caller doubling is enough to make 2160 // sure we can capture all the incoming oop args from the 2161 // caller. 2162 // 2163 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 2164 2165 // Mark location of rbp (someday) 2166 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp)); 2167 2168 // Use eax, ebx as temporaries during any memory-memory moves we have to do 2169 // All inbound args are referenced based on rbp and all outbound args via rsp. 2170 2171 2172 #ifdef ASSERT 2173 bool reg_destroyed[RegisterImpl::number_of_registers]; 2174 bool freg_destroyed[XMMRegisterImpl::number_of_registers]; 2175 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2176 reg_destroyed[r] = false; 2177 } 2178 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) { 2179 freg_destroyed[f] = false; 2180 } 2181 2182 #endif /* ASSERT */ 2183 2184 // This may iterate in two different directions depending on the 2185 // kind of native it is. The reason is that for regular JNI natives 2186 // the incoming and outgoing registers are offset upwards and for 2187 // critical natives they are offset down. 2188 GrowableArray<int> arg_order(2 * total_in_args); 2189 VMRegPair tmp_vmreg; 2190 tmp_vmreg.set2(rbx->as_VMReg()); 2191 2192 if (!is_critical_native) { 2193 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { 2194 arg_order.push(i); 2195 arg_order.push(c_arg); 2196 } 2197 } else { 2198 // Compute a valid move order, using tmp_vmreg to break any cycles 2199 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); 2200 } 2201 2202 int temploc = -1; 2203 for (int ai = 0; ai < arg_order.length(); ai += 2) { 2204 int i = arg_order.at(ai); 2205 int c_arg = arg_order.at(ai + 1); 2206 __ block_comment(err_msg("move %d -> %d", i, c_arg)); 2207 if (c_arg == -1) { 2208 assert(is_critical_native, "should only be required for critical natives"); 2209 // This arg needs to be moved to a temporary 2210 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); 2211 in_regs[i] = tmp_vmreg; 2212 temploc = i; 2213 continue; 2214 } else if (i == -1) { 2215 assert(is_critical_native, "should only be required for critical natives"); 2216 // Read from the temporary location 2217 assert(temploc != -1, "must be valid"); 2218 i = temploc; 2219 temploc = -1; 2220 } 2221 #ifdef ASSERT 2222 if (in_regs[i].first()->is_Register()) { 2223 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); 2224 } else if (in_regs[i].first()->is_XMMRegister()) { 2225 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!"); 2226 } 2227 if (out_regs[c_arg].first()->is_Register()) { 2228 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2229 } else if (out_regs[c_arg].first()->is_XMMRegister()) { 2230 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; 2231 } 2232 #endif /* ASSERT */ 2233 switch (in_sig_bt[i]) { 2234 case T_ARRAY: 2235 if (is_critical_native) { 2236 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); 2237 c_arg++; 2238 #ifdef ASSERT 2239 if (out_regs[c_arg].first()->is_Register()) { 2240 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2241 } else if (out_regs[c_arg].first()->is_XMMRegister()) { 2242 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; 2243 } 2244 #endif 2245 break; 2246 } 2247 case T_OBJECT: 2248 assert(!is_critical_native, "no oop arguments"); 2249 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], 2250 ((i == 0) && (!is_static)), 2251 &receiver_offset); 2252 break; 2253 case T_VOID: 2254 break; 2255 2256 case T_FLOAT: 2257 float_move(masm, in_regs[i], out_regs[c_arg]); 2258 break; 2259 2260 case T_DOUBLE: 2261 assert( i + 1 < total_in_args && 2262 in_sig_bt[i + 1] == T_VOID && 2263 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 2264 double_move(masm, in_regs[i], out_regs[c_arg]); 2265 break; 2266 2267 case T_LONG : 2268 long_move(masm, in_regs[i], out_regs[c_arg]); 2269 break; 2270 2271 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 2272 2273 default: 2274 move32_64(masm, in_regs[i], out_regs[c_arg]); 2275 } 2276 } 2277 2278 int c_arg; 2279 2280 // Pre-load a static method's oop into r14. Used both by locking code and 2281 // the normal JNI call code. 2282 if (!is_critical_native) { 2283 // point c_arg at the first arg that is already loaded in case we 2284 // need to spill before we call out 2285 c_arg = total_c_args - total_in_args; 2286 2287 if (method->is_static()) { 2288 2289 // load oop into a register 2290 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror())); 2291 2292 // Now handlize the static class mirror it's known not-null. 2293 __ movptr(Address(rsp, klass_offset), oop_handle_reg); 2294 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); 2295 2296 // Now get the handle 2297 __ lea(oop_handle_reg, Address(rsp, klass_offset)); 2298 // store the klass handle as second argument 2299 __ movptr(c_rarg1, oop_handle_reg); 2300 // and protect the arg if we must spill 2301 c_arg--; 2302 } 2303 } else { 2304 // For JNI critical methods we need to save all registers in save_args. 2305 c_arg = 0; 2306 } 2307 2308 // Change state to native (we save the return address in the thread, since it might not 2309 // be pushed on the stack when we do a a stack traversal). It is enough that the pc() 2310 // points into the right code segment. It does not have to be the correct return pc. 2311 // We use the same pc/oopMap repeatedly when we call out 2312 2313 intptr_t the_pc = (intptr_t) __ pc(); 2314 oop_maps->add_gc_map(the_pc - start, map); 2315 2316 __ set_last_Java_frame(rsp, noreg, (address)the_pc); 2317 2318 2319 // We have all of the arguments setup at this point. We must not touch any register 2320 // argument registers at this point (what if we save/restore them there are no oop? 2321 2322 { 2323 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 2324 // protect the args we've loaded 2325 save_args(masm, total_c_args, c_arg, out_regs); 2326 __ mov_metadata(c_rarg1, method()); 2327 __ call_VM_leaf( 2328 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), 2329 r15_thread, c_rarg1); 2330 restore_args(masm, total_c_args, c_arg, out_regs); 2331 } 2332 2333 // RedefineClasses() tracing support for obsolete method entry 2334 if (log_is_enabled(Trace, redefine, class, obsolete)) { 2335 // protect the args we've loaded 2336 save_args(masm, total_c_args, c_arg, out_regs); 2337 __ mov_metadata(c_rarg1, method()); 2338 __ call_VM_leaf( 2339 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), 2340 r15_thread, c_rarg1); 2341 restore_args(masm, total_c_args, c_arg, out_regs); 2342 } 2343 2344 // Lock a synchronized method 2345 2346 // Register definitions used by locking and unlocking 2347 2348 const Register swap_reg = rax; // Must use rax for cmpxchg instruction 2349 const Register obj_reg = rbx; // Will contain the oop 2350 const Register lock_reg = r13; // Address of compiler lock object (BasicLock) 2351 const Register old_hdr = r13; // value of old header at unlock time 2352 2353 Label slow_path_lock; 2354 Label lock_done; 2355 2356 if (method->is_synchronized()) { 2357 assert(!is_critical_native, "unhandled"); 2358 2359 2360 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); 2361 2362 // Get the handle (the 2nd argument) 2363 __ mov(oop_handle_reg, c_rarg1); 2364 2365 // Get address of the box 2366 2367 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2368 2369 // Load the oop from the handle 2370 __ movptr(obj_reg, Address(oop_handle_reg, 0)); 2371 2372 if (UseBiasedLocking) { 2373 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock); 2374 } 2375 2376 // Load immediate 1 into swap_reg %rax 2377 __ movl(swap_reg, 1); 2378 2379 // Load (object->mark() | 1) into swap_reg %rax 2380 __ orptr(swap_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 2381 2382 // Save (object->mark() | 1) into BasicLock's displaced header 2383 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); 2384 2385 if (os::is_MP()) { 2386 __ lock(); 2387 } 2388 2389 // src -> dest iff dest == rax else rax <- dest 2390 __ cmpxchgptr(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 2391 __ jcc(Assembler::equal, lock_done); 2392 2393 // Hmm should this move to the slow path code area??? 2394 2395 // Test if the oopMark is an obvious stack pointer, i.e., 2396 // 1) (mark & 3) == 0, and 2397 // 2) rsp <= mark < mark + os::pagesize() 2398 // These 3 tests can be done by evaluating the following 2399 // expression: ((mark - rsp) & (3 - os::vm_page_size())), 2400 // assuming both stack pointer and pagesize have their 2401 // least significant 2 bits clear. 2402 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg 2403 2404 __ subptr(swap_reg, rsp); 2405 __ andptr(swap_reg, 3 - os::vm_page_size()); 2406 2407 // Save the test result, for recursive case, the result is zero 2408 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); 2409 __ jcc(Assembler::notEqual, slow_path_lock); 2410 2411 // Slow path will re-enter here 2412 2413 __ bind(lock_done); 2414 } 2415 2416 2417 // Finally just about ready to make the JNI call 2418 2419 2420 // get JNIEnv* which is first argument to native 2421 if (!is_critical_native) { 2422 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset()))); 2423 } 2424 2425 // Now set thread in native 2426 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native); 2427 2428 __ call(RuntimeAddress(native_func)); 2429 2430 // Verify or restore cpu control state after JNI call 2431 __ restore_cpu_control_state_after_jni(); 2432 2433 // Unpack native results. 2434 switch (ret_type) { 2435 case T_BOOLEAN: __ c2bool(rax); break; 2436 case T_CHAR : __ movzwl(rax, rax); break; 2437 case T_BYTE : __ sign_extend_byte (rax); break; 2438 case T_SHORT : __ sign_extend_short(rax); break; 2439 case T_INT : /* nothing to do */ break; 2440 case T_DOUBLE : 2441 case T_FLOAT : 2442 // Result is in xmm0 we'll save as needed 2443 break; 2444 case T_ARRAY: // Really a handle 2445 case T_OBJECT: // Really a handle 2446 break; // can't de-handlize until after safepoint check 2447 case T_VOID: break; 2448 case T_LONG: break; 2449 default : ShouldNotReachHere(); 2450 } 2451 2452 // Switch thread to "native transition" state before reading the synchronization state. 2453 // This additional state is necessary because reading and testing the synchronization 2454 // state is not atomic w.r.t. GC, as this scenario demonstrates: 2455 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. 2456 // VM thread changes sync state to synchronizing and suspends threads for GC. 2457 // Thread A is resumed to finish this native method, but doesn't block here since it 2458 // didn't see any synchronization is progress, and escapes. 2459 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans); 2460 2461 if(os::is_MP()) { 2462 if (UseMembar) { 2463 // Force this write out before the read below 2464 __ membar(Assembler::Membar_mask_bits( 2465 Assembler::LoadLoad | Assembler::LoadStore | 2466 Assembler::StoreLoad | Assembler::StoreStore)); 2467 } else { 2468 // Write serialization page so VM thread can do a pseudo remote membar. 2469 // We use the current thread pointer to calculate a thread specific 2470 // offset to write to within the page. This minimizes bus traffic 2471 // due to cache line collision. 2472 __ serialize_memory(r15_thread, rcx); 2473 } 2474 } 2475 2476 Label after_transition; 2477 2478 // check for safepoint operation in progress and/or pending suspend requests 2479 { 2480 Label Continue; 2481 Label slow_path; 2482 2483 __ safepoint_poll(slow_path, r15_thread, rscratch1); 2484 2485 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0); 2486 __ jcc(Assembler::equal, Continue); 2487 __ bind(slow_path); 2488 2489 // Don't use call_VM as it will see a possible pending exception and forward it 2490 // and never return here preventing us from clearing _last_native_pc down below. 2491 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are 2492 // preserved and correspond to the bcp/locals pointers. So we do a runtime call 2493 // by hand. 2494 // 2495 __ vzeroupper(); 2496 save_native_result(masm, ret_type, stack_slots); 2497 __ mov(c_rarg0, r15_thread); 2498 __ mov(r12, rsp); // remember sp 2499 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2500 __ andptr(rsp, -16); // align stack as required by ABI 2501 if (!is_critical_native) { 2502 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); 2503 } else { 2504 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); 2505 } 2506 __ mov(rsp, r12); // restore sp 2507 __ reinit_heapbase(); 2508 // Restore any method result value 2509 restore_native_result(masm, ret_type, stack_slots); 2510 2511 if (is_critical_native) { 2512 // The call above performed the transition to thread_in_Java so 2513 // skip the transition logic below. 2514 __ jmpb(after_transition); 2515 } 2516 2517 __ bind(Continue); 2518 } 2519 2520 // change thread state 2521 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java); 2522 __ bind(after_transition); 2523 2524 Label reguard; 2525 Label reguard_done; 2526 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_reserved_disabled); 2527 __ jcc(Assembler::equal, reguard); 2528 __ bind(reguard_done); 2529 2530 // native result if any is live 2531 2532 // Unlock 2533 Label unlock_done; 2534 Label slow_path_unlock; 2535 if (method->is_synchronized()) { 2536 2537 // Get locked oop from the handle we passed to jni 2538 __ movptr(obj_reg, Address(oop_handle_reg, 0)); 2539 2540 Label done; 2541 2542 if (UseBiasedLocking) { 2543 __ biased_locking_exit(obj_reg, old_hdr, done); 2544 } 2545 2546 // Simple recursive lock? 2547 2548 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD); 2549 __ jcc(Assembler::equal, done); 2550 2551 // Must save rax if if it is live now because cmpxchg must use it 2552 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { 2553 save_native_result(masm, ret_type, stack_slots); 2554 } 2555 2556 2557 // get address of the stack lock 2558 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2559 // get old displaced header 2560 __ movptr(old_hdr, Address(rax, 0)); 2561 2562 // Atomic swap old header if oop still contains the stack lock 2563 if (os::is_MP()) { 2564 __ lock(); 2565 } 2566 __ cmpxchgptr(old_hdr, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 2567 __ jcc(Assembler::notEqual, slow_path_unlock); 2568 2569 // slow path re-enters here 2570 __ bind(unlock_done); 2571 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { 2572 restore_native_result(masm, ret_type, stack_slots); 2573 } 2574 2575 __ bind(done); 2576 2577 } 2578 { 2579 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 2580 save_native_result(masm, ret_type, stack_slots); 2581 __ mov_metadata(c_rarg1, method()); 2582 __ call_VM_leaf( 2583 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), 2584 r15_thread, c_rarg1); 2585 restore_native_result(masm, ret_type, stack_slots); 2586 } 2587 2588 __ reset_last_Java_frame(false); 2589 2590 // Unbox oop result, e.g. JNIHandles::resolve value. 2591 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { 2592 __ resolve_jobject(rax /* value */, 2593 r15_thread /* thread */, 2594 rcx /* tmp */); 2595 } 2596 2597 if (CheckJNICalls) { 2598 // clear_pending_jni_exception_check 2599 __ movptr(Address(r15_thread, JavaThread::pending_jni_exception_check_fn_offset()), NULL_WORD); 2600 } 2601 2602 if (!is_critical_native) { 2603 // reset handle block 2604 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset())); 2605 __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD); 2606 } 2607 2608 // pop our frame 2609 2610 __ leave(); 2611 2612 if (!is_critical_native) { 2613 // Any exception pending? 2614 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2615 __ jcc(Assembler::notEqual, exception_pending); 2616 } 2617 2618 // Return 2619 2620 __ ret(0); 2621 2622 // Unexpected paths are out of line and go here 2623 2624 if (!is_critical_native) { 2625 // forward the exception 2626 __ bind(exception_pending); 2627 2628 // and forward the exception 2629 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2630 } 2631 2632 // Slow path locking & unlocking 2633 if (method->is_synchronized()) { 2634 2635 // BEGIN Slow path lock 2636 __ bind(slow_path_lock); 2637 2638 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM 2639 // args are (oop obj, BasicLock* lock, JavaThread* thread) 2640 2641 // protect the args we've loaded 2642 save_args(masm, total_c_args, c_arg, out_regs); 2643 2644 __ mov(c_rarg0, obj_reg); 2645 __ mov(c_rarg1, lock_reg); 2646 __ mov(c_rarg2, r15_thread); 2647 2648 // Not a leaf but we have last_Java_frame setup as we want 2649 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); 2650 restore_args(masm, total_c_args, c_arg, out_regs); 2651 2652 #ifdef ASSERT 2653 { Label L; 2654 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2655 __ jcc(Assembler::equal, L); 2656 __ stop("no pending exception allowed on exit from monitorenter"); 2657 __ bind(L); 2658 } 2659 #endif 2660 __ jmp(lock_done); 2661 2662 // END Slow path lock 2663 2664 // BEGIN Slow path unlock 2665 __ bind(slow_path_unlock); 2666 2667 // If we haven't already saved the native result we must save it now as xmm registers 2668 // are still exposed. 2669 __ vzeroupper(); 2670 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { 2671 save_native_result(masm, ret_type, stack_slots); 2672 } 2673 2674 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2675 2676 __ mov(c_rarg0, obj_reg); 2677 __ mov(c_rarg2, r15_thread); 2678 __ mov(r12, rsp); // remember sp 2679 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2680 __ andptr(rsp, -16); // align stack as required by ABI 2681 2682 // Save pending exception around call to VM (which contains an EXCEPTION_MARK) 2683 // NOTE that obj_reg == rbx currently 2684 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset()))); 2685 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2686 2687 // args are (oop obj, BasicLock* lock, JavaThread* thread) 2688 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C))); 2689 __ mov(rsp, r12); // restore sp 2690 __ reinit_heapbase(); 2691 #ifdef ASSERT 2692 { 2693 Label L; 2694 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD); 2695 __ jcc(Assembler::equal, L); 2696 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); 2697 __ bind(L); 2698 } 2699 #endif /* ASSERT */ 2700 2701 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx); 2702 2703 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { 2704 restore_native_result(masm, ret_type, stack_slots); 2705 } 2706 __ jmp(unlock_done); 2707 2708 // END Slow path unlock 2709 2710 } // synchronized 2711 2712 // SLOW PATH Reguard the stack if needed 2713 2714 __ bind(reguard); 2715 __ vzeroupper(); 2716 save_native_result(masm, ret_type, stack_slots); 2717 __ mov(r12, rsp); // remember sp 2718 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2719 __ andptr(rsp, -16); // align stack as required by ABI 2720 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages))); 2721 __ mov(rsp, r12); // restore sp 2722 __ reinit_heapbase(); 2723 restore_native_result(masm, ret_type, stack_slots); 2724 // and continue 2725 __ jmp(reguard_done); 2726 2727 2728 2729 __ flush(); 2730 2731 nmethod *nm = nmethod::new_native_nmethod(method, 2732 compile_id, 2733 masm->code(), 2734 vep_offset, 2735 frame_complete, 2736 stack_slots / VMRegImpl::slots_per_word, 2737 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), 2738 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), 2739 oop_maps); 2740 2741 if (is_critical_native) { 2742 nm->set_lazy_critical_native(true); 2743 } 2744 2745 return nm; 2746 2747 } 2748 2749 // this function returns the adjust size (in number of words) to a c2i adapter 2750 // activation for use during deoptimization 2751 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) { 2752 return (callee_locals - callee_parameters) * Interpreter::stackElementWords; 2753 } 2754 2755 2756 uint SharedRuntime::out_preserve_stack_slots() { 2757 return 0; 2758 } 2759 2760 //------------------------------generate_deopt_blob---------------------------- 2761 void SharedRuntime::generate_deopt_blob() { 2762 // Allocate space for the code 2763 ResourceMark rm; 2764 // Setup code generation tools 2765 int pad = 0; 2766 #if INCLUDE_JVMCI 2767 if (EnableJVMCI || UseAOT) { 2768 pad += 512; // Increase the buffer size when compiling for JVMCI 2769 } 2770 #endif 2771 CodeBuffer buffer("deopt_blob", 2048+pad, 1024); 2772 MacroAssembler* masm = new MacroAssembler(&buffer); 2773 int frame_size_in_words; 2774 OopMap* map = NULL; 2775 OopMapSet *oop_maps = new OopMapSet(); 2776 2777 // ------------- 2778 // This code enters when returning to a de-optimized nmethod. A return 2779 // address has been pushed on the the stack, and return values are in 2780 // registers. 2781 // If we are doing a normal deopt then we were called from the patched 2782 // nmethod from the point we returned to the nmethod. So the return 2783 // address on the stack is wrong by NativeCall::instruction_size 2784 // We will adjust the value so it looks like we have the original return 2785 // address on the stack (like when we eagerly deoptimized). 2786 // In the case of an exception pending when deoptimizing, we enter 2787 // with a return address on the stack that points after the call we patched 2788 // into the exception handler. We have the following register state from, 2789 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). 2790 // rax: exception oop 2791 // rbx: exception handler 2792 // rdx: throwing pc 2793 // So in this case we simply jam rdx into the useless return address and 2794 // the stack looks just like we want. 2795 // 2796 // At this point we need to de-opt. We save the argument return 2797 // registers. We call the first C routine, fetch_unroll_info(). This 2798 // routine captures the return values and returns a structure which 2799 // describes the current frame size and the sizes of all replacement frames. 2800 // The current frame is compiled code and may contain many inlined 2801 // functions, each with their own JVM state. We pop the current frame, then 2802 // push all the new frames. Then we call the C routine unpack_frames() to 2803 // populate these frames. Finally unpack_frames() returns us the new target 2804 // address. Notice that callee-save registers are BLOWN here; they have 2805 // already been captured in the vframeArray at the time the return PC was 2806 // patched. 2807 address start = __ pc(); 2808 Label cont; 2809 2810 // Prolog for non exception case! 2811 2812 // Save everything in sight. 2813 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2814 2815 // Normal deoptimization. Save exec mode for unpack_frames. 2816 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved 2817 __ jmp(cont); 2818 2819 int reexecute_offset = __ pc() - start; 2820 #if INCLUDE_JVMCI && !defined(COMPILER1) 2821 if (EnableJVMCI && UseJVMCICompiler) { 2822 // JVMCI does not use this kind of deoptimization 2823 __ should_not_reach_here(); 2824 } 2825 #endif 2826 2827 // Reexecute case 2828 // return address is the pc describes what bci to do re-execute at 2829 2830 // No need to update map as each call to save_live_registers will produce identical oopmap 2831 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2832 2833 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved 2834 __ jmp(cont); 2835 2836 #if INCLUDE_JVMCI 2837 Label after_fetch_unroll_info_call; 2838 int implicit_exception_uncommon_trap_offset = 0; 2839 int uncommon_trap_offset = 0; 2840 2841 if (EnableJVMCI || UseAOT) { 2842 implicit_exception_uncommon_trap_offset = __ pc() - start; 2843 2844 __ pushptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset()))); 2845 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())), (int32_t)NULL_WORD); 2846 2847 uncommon_trap_offset = __ pc() - start; 2848 2849 // Save everything in sight. 2850 RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2851 // fetch_unroll_info needs to call last_java_frame() 2852 __ set_last_Java_frame(noreg, noreg, NULL); 2853 2854 __ movl(c_rarg1, Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset()))); 2855 __ movl(Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset())), -1); 2856 2857 __ movl(r14, (int32_t)Deoptimization::Unpack_reexecute); 2858 __ mov(c_rarg0, r15_thread); 2859 __ movl(c_rarg2, r14); // exec mode 2860 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); 2861 oop_maps->add_gc_map( __ pc()-start, map->deep_copy()); 2862 2863 __ reset_last_Java_frame(false); 2864 2865 __ jmp(after_fetch_unroll_info_call); 2866 } // EnableJVMCI 2867 #endif // INCLUDE_JVMCI 2868 2869 int exception_offset = __ pc() - start; 2870 2871 // Prolog for exception case 2872 2873 // all registers are dead at this entry point, except for rax, and 2874 // rdx which contain the exception oop and exception pc 2875 // respectively. Set them in TLS and fall thru to the 2876 // unpack_with_exception_in_tls entry point. 2877 2878 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); 2879 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax); 2880 2881 int exception_in_tls_offset = __ pc() - start; 2882 2883 // new implementation because exception oop is now passed in JavaThread 2884 2885 // Prolog for exception case 2886 // All registers must be preserved because they might be used by LinearScan 2887 // Exceptiop oop and throwing PC are passed in JavaThread 2888 // tos: stack at point of call to method that threw the exception (i.e. only 2889 // args are on the stack, no return address) 2890 2891 // make room on stack for the return address 2892 // It will be patched later with the throwing pc. The correct value is not 2893 // available now because loading it from memory would destroy registers. 2894 __ push(0); 2895 2896 // Save everything in sight. 2897 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2898 2899 // Now it is safe to overwrite any register 2900 2901 // Deopt during an exception. Save exec mode for unpack_frames. 2902 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved 2903 2904 // load throwing pc from JavaThread and patch it as the return address 2905 // of the current frame. Then clear the field in JavaThread 2906 2907 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 2908 __ movptr(Address(rbp, wordSize), rdx); 2909 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 2910 2911 #ifdef ASSERT 2912 // verify that there is really an exception oop in JavaThread 2913 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 2914 __ verify_oop(rax); 2915 2916 // verify that there is no pending exception 2917 Label no_pending_exception; 2918 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); 2919 __ testptr(rax, rax); 2920 __ jcc(Assembler::zero, no_pending_exception); 2921 __ stop("must not have pending exception here"); 2922 __ bind(no_pending_exception); 2923 #endif 2924 2925 __ bind(cont); 2926 2927 // Call C code. Need thread and this frame, but NOT official VM entry 2928 // crud. We cannot block on this call, no GC can happen. 2929 // 2930 // UnrollBlock* fetch_unroll_info(JavaThread* thread) 2931 2932 // fetch_unroll_info needs to call last_java_frame(). 2933 2934 __ set_last_Java_frame(noreg, noreg, NULL); 2935 #ifdef ASSERT 2936 { Label L; 2937 __ cmpptr(Address(r15_thread, 2938 JavaThread::last_Java_fp_offset()), 2939 (int32_t)0); 2940 __ jcc(Assembler::equal, L); 2941 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); 2942 __ bind(L); 2943 } 2944 #endif // ASSERT 2945 __ mov(c_rarg0, r15_thread); 2946 __ movl(c_rarg1, r14); // exec_mode 2947 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); 2948 2949 // Need to have an oopmap that tells fetch_unroll_info where to 2950 // find any register it might need. 2951 oop_maps->add_gc_map(__ pc() - start, map); 2952 2953 __ reset_last_Java_frame(false); 2954 2955 #if INCLUDE_JVMCI 2956 if (EnableJVMCI || UseAOT) { 2957 __ bind(after_fetch_unroll_info_call); 2958 } 2959 #endif 2960 2961 // Load UnrollBlock* into rdi 2962 __ mov(rdi, rax); 2963 2964 __ movl(r14, Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes())); 2965 Label noException; 2966 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending? 2967 __ jcc(Assembler::notEqual, noException); 2968 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 2969 // QQQ this is useless it was NULL above 2970 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 2971 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 2972 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 2973 2974 __ verify_oop(rax); 2975 2976 // Overwrite the result registers with the exception results. 2977 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 2978 // I think this is useless 2979 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx); 2980 2981 __ bind(noException); 2982 2983 // Only register save data is on the stack. 2984 // Now restore the result registers. Everything else is either dead 2985 // or captured in the vframeArray. 2986 RegisterSaver::restore_result_registers(masm); 2987 2988 // All of the register save area has been popped of the stack. Only the 2989 // return address remains. 2990 2991 // Pop all the frames we must move/replace. 2992 // 2993 // Frame picture (youngest to oldest) 2994 // 1: self-frame (no frame link) 2995 // 2: deopting frame (no frame link) 2996 // 3: caller of deopting frame (could be compiled/interpreted). 2997 // 2998 // Note: by leaving the return address of self-frame on the stack 2999 // and using the size of frame 2 to adjust the stack 3000 // when we are done the return to frame 3 will still be on the stack. 3001 3002 // Pop deoptimized frame 3003 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); 3004 __ addptr(rsp, rcx); 3005 3006 // rsp should be pointing at the return address to the caller (3) 3007 3008 // Pick up the initial fp we should save 3009 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) 3010 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); 3011 3012 #ifdef ASSERT 3013 // Compilers generate code that bang the stack by as much as the 3014 // interpreter would need. So this stack banging should never 3015 // trigger a fault. Verify that it does not on non product builds. 3016 if (UseStackBanging) { 3017 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); 3018 __ bang_stack_size(rbx, rcx); 3019 } 3020 #endif 3021 3022 // Load address of array of frame pcs into rcx 3023 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 3024 3025 // Trash the old pc 3026 __ addptr(rsp, wordSize); 3027 3028 // Load address of array of frame sizes into rsi 3029 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); 3030 3031 // Load counter into rdx 3032 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); 3033 3034 // Now adjust the caller's stack to make up for the extra locals 3035 // but record the original sp so that we can save it in the skeletal interpreter 3036 // frame and the stack walking of interpreter_sender will get the unextended sp 3037 // value and not the "real" sp value. 3038 3039 const Register sender_sp = r8; 3040 3041 __ mov(sender_sp, rsp); 3042 __ movl(rbx, Address(rdi, 3043 Deoptimization::UnrollBlock:: 3044 caller_adjustment_offset_in_bytes())); 3045 __ subptr(rsp, rbx); 3046 3047 // Push interpreter frames in a loop 3048 Label loop; 3049 __ bind(loop); 3050 __ movptr(rbx, Address(rsi, 0)); // Load frame size 3051 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand 3052 __ pushptr(Address(rcx, 0)); // Save return address 3053 __ enter(); // Save old & set new ebp 3054 __ subptr(rsp, rbx); // Prolog 3055 // This value is corrected by layout_activation_impl 3056 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); 3057 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable 3058 __ mov(sender_sp, rsp); // Pass sender_sp to next frame 3059 __ addptr(rsi, wordSize); // Bump array pointer (sizes) 3060 __ addptr(rcx, wordSize); // Bump array pointer (pcs) 3061 __ decrementl(rdx); // Decrement counter 3062 __ jcc(Assembler::notZero, loop); 3063 __ pushptr(Address(rcx, 0)); // Save final return address 3064 3065 // Re-push self-frame 3066 __ enter(); // Save old & set new ebp 3067 3068 // Allocate a full sized register save area. 3069 // Return address and rbp are in place, so we allocate two less words. 3070 __ subptr(rsp, (frame_size_in_words - 2) * wordSize); 3071 3072 // Restore frame locals after moving the frame 3073 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0); 3074 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 3075 3076 // Call C code. Need thread but NOT official VM entry 3077 // crud. We cannot block on this call, no GC can happen. Call should 3078 // restore return values to their stack-slots with the new SP. 3079 // 3080 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) 3081 3082 // Use rbp because the frames look interpreted now 3083 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. 3084 // Don't need the precise return PC here, just precise enough to point into this code blob. 3085 address the_pc = __ pc(); 3086 __ set_last_Java_frame(noreg, rbp, the_pc); 3087 3088 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI 3089 __ mov(c_rarg0, r15_thread); 3090 __ movl(c_rarg1, r14); // second arg: exec_mode 3091 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 3092 // Revert SP alignment after call since we're going to do some SP relative addressing below 3093 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset())); 3094 3095 // Set an oopmap for the call site 3096 // Use the same PC we used for the last java frame 3097 oop_maps->add_gc_map(the_pc - start, 3098 new OopMap( frame_size_in_words, 0 )); 3099 3100 // Clear fp AND pc 3101 __ reset_last_Java_frame(true); 3102 3103 // Collect return values 3104 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes())); 3105 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes())); 3106 // I think this is useless (throwing pc?) 3107 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes())); 3108 3109 // Pop self-frame. 3110 __ leave(); // Epilog 3111 3112 // Jump to interpreter 3113 __ ret(0); 3114 3115 // Make sure all code is generated 3116 masm->flush(); 3117 3118 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); 3119 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); 3120 #if INCLUDE_JVMCI 3121 if (EnableJVMCI || UseAOT) { 3122 _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset); 3123 _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset); 3124 } 3125 #endif 3126 } 3127 3128 #ifdef COMPILER2 3129 //------------------------------generate_uncommon_trap_blob-------------------- 3130 void SharedRuntime::generate_uncommon_trap_blob() { 3131 // Allocate space for the code 3132 ResourceMark rm; 3133 // Setup code generation tools 3134 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); 3135 MacroAssembler* masm = new MacroAssembler(&buffer); 3136 3137 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 3138 3139 address start = __ pc(); 3140 3141 if (UseRTMLocking) { 3142 // Abort RTM transaction before possible nmethod deoptimization. 3143 __ xabort(0); 3144 } 3145 3146 // Push self-frame. We get here with a return address on the 3147 // stack, so rsp is 8-byte aligned until we allocate our frame. 3148 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog! 3149 3150 // No callee saved registers. rbp is assumed implicitly saved 3151 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); 3152 3153 // compiler left unloaded_class_index in j_rarg0 move to where the 3154 // runtime expects it. 3155 __ movl(c_rarg1, j_rarg0); 3156 3157 __ set_last_Java_frame(noreg, noreg, NULL); 3158 3159 // Call C code. Need thread but NOT official VM entry 3160 // crud. We cannot block on this call, no GC can happen. Call should 3161 // capture callee-saved registers as well as return values. 3162 // Thread is in rdi already. 3163 // 3164 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); 3165 3166 __ mov(c_rarg0, r15_thread); 3167 __ movl(c_rarg2, Deoptimization::Unpack_uncommon_trap); 3168 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); 3169 3170 // Set an oopmap for the call site 3171 OopMapSet* oop_maps = new OopMapSet(); 3172 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); 3173 3174 // location of rbp is known implicitly by the frame sender code 3175 3176 oop_maps->add_gc_map(__ pc() - start, map); 3177 3178 __ reset_last_Java_frame(false); 3179 3180 // Load UnrollBlock* into rdi 3181 __ mov(rdi, rax); 3182 3183 #ifdef ASSERT 3184 { Label L; 3185 __ cmpptr(Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()), 3186 (int32_t)Deoptimization::Unpack_uncommon_trap); 3187 __ jcc(Assembler::equal, L); 3188 __ stop("SharedRuntime::generate_deopt_blob: expected Unpack_uncommon_trap"); 3189 __ bind(L); 3190 } 3191 #endif 3192 3193 // Pop all the frames we must move/replace. 3194 // 3195 // Frame picture (youngest to oldest) 3196 // 1: self-frame (no frame link) 3197 // 2: deopting frame (no frame link) 3198 // 3: caller of deopting frame (could be compiled/interpreted). 3199 3200 // Pop self-frame. We have no frame, and must rely only on rax and rsp. 3201 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog! 3202 3203 // Pop deoptimized frame (int) 3204 __ movl(rcx, Address(rdi, 3205 Deoptimization::UnrollBlock:: 3206 size_of_deoptimized_frame_offset_in_bytes())); 3207 __ addptr(rsp, rcx); 3208 3209 // rsp should be pointing at the return address to the caller (3) 3210 3211 // Pick up the initial fp we should save 3212 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) 3213 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); 3214 3215 #ifdef ASSERT 3216 // Compilers generate code that bang the stack by as much as the 3217 // interpreter would need. So this stack banging should never 3218 // trigger a fault. Verify that it does not on non product builds. 3219 if (UseStackBanging) { 3220 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); 3221 __ bang_stack_size(rbx, rcx); 3222 } 3223 #endif 3224 3225 // Load address of array of frame pcs into rcx (address*) 3226 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 3227 3228 // Trash the return pc 3229 __ addptr(rsp, wordSize); 3230 3231 // Load address of array of frame sizes into rsi (intptr_t*) 3232 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes())); 3233 3234 // Counter 3235 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int) 3236 3237 // Now adjust the caller's stack to make up for the extra locals but 3238 // record the original sp so that we can save it in the skeletal 3239 // interpreter frame and the stack walking of interpreter_sender 3240 // will get the unextended sp value and not the "real" sp value. 3241 3242 const Register sender_sp = r8; 3243 3244 __ mov(sender_sp, rsp); 3245 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int) 3246 __ subptr(rsp, rbx); 3247 3248 // Push interpreter frames in a loop 3249 Label loop; 3250 __ bind(loop); 3251 __ movptr(rbx, Address(rsi, 0)); // Load frame size 3252 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand 3253 __ pushptr(Address(rcx, 0)); // Save return address 3254 __ enter(); // Save old & set new rbp 3255 __ subptr(rsp, rbx); // Prolog 3256 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), 3257 sender_sp); // Make it walkable 3258 // This value is corrected by layout_activation_impl 3259 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); 3260 __ mov(sender_sp, rsp); // Pass sender_sp to next frame 3261 __ addptr(rsi, wordSize); // Bump array pointer (sizes) 3262 __ addptr(rcx, wordSize); // Bump array pointer (pcs) 3263 __ decrementl(rdx); // Decrement counter 3264 __ jcc(Assembler::notZero, loop); 3265 __ pushptr(Address(rcx, 0)); // Save final return address 3266 3267 // Re-push self-frame 3268 __ enter(); // Save old & set new rbp 3269 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt); 3270 // Prolog 3271 3272 // Use rbp because the frames look interpreted now 3273 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. 3274 // Don't need the precise return PC here, just precise enough to point into this code blob. 3275 address the_pc = __ pc(); 3276 __ set_last_Java_frame(noreg, rbp, the_pc); 3277 3278 // Call C code. Need thread but NOT official VM entry 3279 // crud. We cannot block on this call, no GC can happen. Call should 3280 // restore return values to their stack-slots with the new SP. 3281 // Thread is in rdi already. 3282 // 3283 // BasicType unpack_frames(JavaThread* thread, int exec_mode); 3284 3285 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI 3286 __ mov(c_rarg0, r15_thread); 3287 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap); 3288 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 3289 3290 // Set an oopmap for the call site 3291 // Use the same PC we used for the last java frame 3292 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 3293 3294 // Clear fp AND pc 3295 __ reset_last_Java_frame(true); 3296 3297 // Pop self-frame. 3298 __ leave(); // Epilog 3299 3300 // Jump to interpreter 3301 __ ret(0); 3302 3303 // Make sure all code is generated 3304 masm->flush(); 3305 3306 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, 3307 SimpleRuntimeFrame::framesize >> 1); 3308 } 3309 #endif // COMPILER2 3310 3311 3312 //------------------------------generate_handler_blob------ 3313 // 3314 // Generate a special Compile2Runtime blob that saves all registers, 3315 // and setup oopmap. 3316 // 3317 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { 3318 assert(StubRoutines::forward_exception_entry() != NULL, 3319 "must be generated before"); 3320 3321 ResourceMark rm; 3322 OopMapSet *oop_maps = new OopMapSet(); 3323 OopMap* map; 3324 3325 // Allocate space for the code. Setup code generation tools. 3326 CodeBuffer buffer("handler_blob", 2048, 1024); 3327 MacroAssembler* masm = new MacroAssembler(&buffer); 3328 3329 address start = __ pc(); 3330 address call_pc = NULL; 3331 int frame_size_in_words; 3332 bool cause_return = (poll_type == POLL_AT_RETURN); 3333 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP); 3334 3335 if (UseRTMLocking) { 3336 // Abort RTM transaction before calling runtime 3337 // because critical section will be large and will be 3338 // aborted anyway. Also nmethod could be deoptimized. 3339 __ xabort(0); 3340 } 3341 3342 // Make room for return address (or push it again) 3343 if (!cause_return) { 3344 __ push(rbx); 3345 } 3346 3347 // Save registers, fpu state, and flags 3348 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors); 3349 3350 // The following is basically a call_VM. However, we need the precise 3351 // address of the call in order to generate an oopmap. Hence, we do all the 3352 // work outselves. 3353 3354 __ set_last_Java_frame(noreg, noreg, NULL); 3355 3356 // The return address must always be correct so that frame constructor never 3357 // sees an invalid pc. 3358 3359 if (!cause_return) { 3360 // Get the return pc saved by the signal handler and stash it in its appropriate place on the stack. 3361 // Additionally, rbx is a callee saved register and we can look at it later to determine 3362 // if someone changed the return address for us! 3363 __ movptr(rbx, Address(r15_thread, JavaThread::saved_exception_pc_offset())); 3364 __ movptr(Address(rbp, wordSize), rbx); 3365 } 3366 3367 // Do the call 3368 __ mov(c_rarg0, r15_thread); 3369 __ call(RuntimeAddress(call_ptr)); 3370 3371 // Set an oopmap for the call site. This oopmap will map all 3372 // oop-registers and debug-info registers as callee-saved. This 3373 // will allow deoptimization at this safepoint to find all possible 3374 // debug-info recordings, as well as let GC find all oops. 3375 3376 oop_maps->add_gc_map( __ pc() - start, map); 3377 3378 Label noException; 3379 3380 __ reset_last_Java_frame(false); 3381 3382 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 3383 __ jcc(Assembler::equal, noException); 3384 3385 // Exception pending 3386 3387 RegisterSaver::restore_live_registers(masm, save_vectors); 3388 3389 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 3390 3391 // No exception case 3392 __ bind(noException); 3393 3394 Label no_adjust, bail, no_prefix, not_special; 3395 if (SafepointMechanism::uses_thread_local_poll() && !cause_return) { 3396 // If our stashed return pc was modified by the runtime we avoid touching it 3397 __ cmpptr(rbx, Address(rbp, wordSize)); 3398 __ jccb(Assembler::notEqual, no_adjust); 3399 3400 // Skip over the poll instruction. 3401 // See NativeInstruction::is_safepoint_poll() 3402 // Possible encodings: 3403 // 85 00 test %eax,(%rax) 3404 // 85 01 test %eax,(%rcx) 3405 // 85 02 test %eax,(%rdx) 3406 // 85 03 test %eax,(%rbx) 3407 // 85 06 test %eax,(%rsi) 3408 // 85 07 test %eax,(%rdi) 3409 // 3410 // 41 85 00 test %eax,(%r8) 3411 // 41 85 01 test %eax,(%r9) 3412 // 41 85 02 test %eax,(%r10) 3413 // 41 85 03 test %eax,(%r11) 3414 // 41 85 06 test %eax,(%r14) 3415 // 41 85 07 test %eax,(%r15) 3416 // 3417 // 85 04 24 test %eax,(%rsp) 3418 // 41 85 04 24 test %eax,(%r12) 3419 // 85 45 00 test %eax,0x0(%rbp) 3420 // 41 85 45 00 test %eax,0x0(%r13) 3421 3422 __ cmpb(Address(rbx, 0), NativeTstRegMem::instruction_rex_b_prefix); 3423 __ jcc(Assembler::notEqual, no_prefix); 3424 __ addptr(rbx, 1); 3425 __ bind(no_prefix); 3426 #ifdef ASSERT 3427 __ movptr(rax, rbx); // remember where 0x85 should be, for verification below 3428 #endif 3429 // r12/r13/rsp/rbp base encoding takes 3 bytes with the following register values: 3430 // r12/rsp 0x04 3431 // r13/rbp 0x05 3432 __ movzbq(rcx, Address(rbx, 1)); 3433 __ andptr(rcx, 0x07); // looking for 0x04 .. 0x05 3434 __ subptr(rcx, 4); // looking for 0x00 .. 0x01 3435 __ cmpptr(rcx, 1); 3436 __ jcc(Assembler::above, not_special); 3437 __ addptr(rbx, 1); 3438 __ bind(not_special); 3439 #ifdef ASSERT 3440 // Verify the correct encoding of the poll we're about to skip. 3441 __ cmpb(Address(rax, 0), NativeTstRegMem::instruction_code_memXregl); 3442 __ jcc(Assembler::notEqual, bail); 3443 // Mask out the modrm bits 3444 __ testb(Address(rax, 1), NativeTstRegMem::modrm_mask); 3445 // rax encodes to 0, so if the bits are nonzero it's incorrect 3446 __ jcc(Assembler::notZero, bail); 3447 #endif 3448 // Adjust return pc forward to step over the safepoint poll instruction 3449 __ addptr(rbx, 2); 3450 __ movptr(Address(rbp, wordSize), rbx); 3451 } 3452 3453 __ bind(no_adjust); 3454 // Normal exit, restore registers and exit. 3455 RegisterSaver::restore_live_registers(masm, save_vectors); 3456 __ ret(0); 3457 3458 #ifdef ASSERT 3459 __ bind(bail); 3460 __ stop("Attempting to adjust pc to skip safepoint poll but the return point is not what we expected"); 3461 #endif 3462 3463 // Make sure all code is generated 3464 masm->flush(); 3465 3466 // Fill-out other meta info 3467 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); 3468 } 3469 3470 // 3471 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss 3472 // 3473 // Generate a stub that calls into vm to find out the proper destination 3474 // of a java call. All the argument registers are live at this point 3475 // but since this is generic code we don't know what they are and the caller 3476 // must do any gc of the args. 3477 // 3478 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { 3479 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3480 3481 // allocate space for the code 3482 ResourceMark rm; 3483 3484 CodeBuffer buffer(name, 1000, 512); 3485 MacroAssembler* masm = new MacroAssembler(&buffer); 3486 3487 int frame_size_in_words; 3488 3489 OopMapSet *oop_maps = new OopMapSet(); 3490 OopMap* map = NULL; 3491 3492 int start = __ offset(); 3493 3494 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 3495 3496 int frame_complete = __ offset(); 3497 3498 __ set_last_Java_frame(noreg, noreg, NULL); 3499 3500 __ mov(c_rarg0, r15_thread); 3501 3502 __ call(RuntimeAddress(destination)); 3503 3504 3505 // Set an oopmap for the call site. 3506 // We need this not only for callee-saved registers, but also for volatile 3507 // registers that the compiler might be keeping live across a safepoint. 3508 3509 oop_maps->add_gc_map( __ offset() - start, map); 3510 3511 // rax contains the address we are going to jump to assuming no exception got installed 3512 3513 // clear last_Java_sp 3514 __ reset_last_Java_frame(false); 3515 // check for pending exceptions 3516 Label pending; 3517 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 3518 __ jcc(Assembler::notEqual, pending); 3519 3520 // get the returned Method* 3521 __ get_vm_result_2(rbx, r15_thread); 3522 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx); 3523 3524 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 3525 3526 RegisterSaver::restore_live_registers(masm); 3527 3528 // We are back the the original state on entry and ready to go. 3529 3530 __ jmp(rax); 3531 3532 // Pending exception after the safepoint 3533 3534 __ bind(pending); 3535 3536 RegisterSaver::restore_live_registers(masm); 3537 3538 // exception pending => remove activation and forward to exception handler 3539 3540 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD); 3541 3542 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); 3543 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 3544 3545 // ------------- 3546 // make sure all code is generated 3547 masm->flush(); 3548 3549 // return the blob 3550 // frame_size_words or bytes?? 3551 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); 3552 } 3553 3554 3555 //------------------------------Montgomery multiplication------------------------ 3556 // 3557 3558 #ifndef _WINDOWS 3559 3560 #define ASM_SUBTRACT 3561 3562 #ifdef ASM_SUBTRACT 3563 // Subtract 0:b from carry:a. Return carry. 3564 static unsigned long 3565 sub(unsigned long a[], unsigned long b[], unsigned long carry, long len) { 3566 long i = 0, cnt = len; 3567 unsigned long tmp; 3568 asm volatile("clc; " 3569 "0: ; " 3570 "mov (%[b], %[i], 8), %[tmp]; " 3571 "sbb %[tmp], (%[a], %[i], 8); " 3572 "inc %[i]; dec %[cnt]; " 3573 "jne 0b; " 3574 "mov %[carry], %[tmp]; sbb $0, %[tmp]; " 3575 : [i]"+r"(i), [cnt]"+r"(cnt), [tmp]"=&r"(tmp) 3576 : [a]"r"(a), [b]"r"(b), [carry]"r"(carry) 3577 : "memory"); 3578 return tmp; 3579 } 3580 #else // ASM_SUBTRACT 3581 typedef int __attribute__((mode(TI))) int128; 3582 3583 // Subtract 0:b from carry:a. Return carry. 3584 static unsigned long 3585 sub(unsigned long a[], unsigned long b[], unsigned long carry, int len) { 3586 int128 tmp = 0; 3587 int i; 3588 for (i = 0; i < len; i++) { 3589 tmp += a[i]; 3590 tmp -= b[i]; 3591 a[i] = tmp; 3592 tmp >>= 64; 3593 assert(-1 <= tmp && tmp <= 0, "invariant"); 3594 } 3595 return tmp + carry; 3596 } 3597 #endif // ! ASM_SUBTRACT 3598 3599 // Multiply (unsigned) Long A by Long B, accumulating the double- 3600 // length result into the accumulator formed of T0, T1, and T2. 3601 #define MACC(A, B, T0, T1, T2) \ 3602 do { \ 3603 unsigned long hi, lo; \ 3604 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4" \ 3605 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \ 3606 : "r"(A), "a"(B) : "cc"); \ 3607 } while(0) 3608 3609 // As above, but add twice the double-length result into the 3610 // accumulator. 3611 #define MACC2(A, B, T0, T1, T2) \ 3612 do { \ 3613 unsigned long hi, lo; \ 3614 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4; " \ 3615 "add %%rax, %2; adc %%rdx, %3; adc $0, %4" \ 3616 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \ 3617 : "r"(A), "a"(B) : "cc"); \ 3618 } while(0) 3619 3620 // Fast Montgomery multiplication. The derivation of the algorithm is 3621 // in A Cryptographic Library for the Motorola DSP56000, 3622 // Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237. 3623 3624 static void __attribute__((noinline)) 3625 montgomery_multiply(unsigned long a[], unsigned long b[], unsigned long n[], 3626 unsigned long m[], unsigned long inv, int len) { 3627 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator 3628 int i; 3629 3630 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); 3631 3632 for (i = 0; i < len; i++) { 3633 int j; 3634 for (j = 0; j < i; j++) { 3635 MACC(a[j], b[i-j], t0, t1, t2); 3636 MACC(m[j], n[i-j], t0, t1, t2); 3637 } 3638 MACC(a[i], b[0], t0, t1, t2); 3639 m[i] = t0 * inv; 3640 MACC(m[i], n[0], t0, t1, t2); 3641 3642 assert(t0 == 0, "broken Montgomery multiply"); 3643 3644 t0 = t1; t1 = t2; t2 = 0; 3645 } 3646 3647 for (i = len; i < 2*len; i++) { 3648 int j; 3649 for (j = i-len+1; j < len; j++) { 3650 MACC(a[j], b[i-j], t0, t1, t2); 3651 MACC(m[j], n[i-j], t0, t1, t2); 3652 } 3653 m[i-len] = t0; 3654 t0 = t1; t1 = t2; t2 = 0; 3655 } 3656 3657 while (t0) 3658 t0 = sub(m, n, t0, len); 3659 } 3660 3661 // Fast Montgomery squaring. This uses asymptotically 25% fewer 3662 // multiplies so it should be up to 25% faster than Montgomery 3663 // multiplication. However, its loop control is more complex and it 3664 // may actually run slower on some machines. 3665 3666 static void __attribute__((noinline)) 3667 montgomery_square(unsigned long a[], unsigned long n[], 3668 unsigned long m[], unsigned long inv, int len) { 3669 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator 3670 int i; 3671 3672 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); 3673 3674 for (i = 0; i < len; i++) { 3675 int j; 3676 int end = (i+1)/2; 3677 for (j = 0; j < end; j++) { 3678 MACC2(a[j], a[i-j], t0, t1, t2); 3679 MACC(m[j], n[i-j], t0, t1, t2); 3680 } 3681 if ((i & 1) == 0) { 3682 MACC(a[j], a[j], t0, t1, t2); 3683 } 3684 for (; j < i; j++) { 3685 MACC(m[j], n[i-j], t0, t1, t2); 3686 } 3687 m[i] = t0 * inv; 3688 MACC(m[i], n[0], t0, t1, t2); 3689 3690 assert(t0 == 0, "broken Montgomery square"); 3691 3692 t0 = t1; t1 = t2; t2 = 0; 3693 } 3694 3695 for (i = len; i < 2*len; i++) { 3696 int start = i-len+1; 3697 int end = start + (len - start)/2; 3698 int j; 3699 for (j = start; j < end; j++) { 3700 MACC2(a[j], a[i-j], t0, t1, t2); 3701 MACC(m[j], n[i-j], t0, t1, t2); 3702 } 3703 if ((i & 1) == 0) { 3704 MACC(a[j], a[j], t0, t1, t2); 3705 } 3706 for (; j < len; j++) { 3707 MACC(m[j], n[i-j], t0, t1, t2); 3708 } 3709 m[i-len] = t0; 3710 t0 = t1; t1 = t2; t2 = 0; 3711 } 3712 3713 while (t0) 3714 t0 = sub(m, n, t0, len); 3715 } 3716 3717 // Swap words in a longword. 3718 static unsigned long swap(unsigned long x) { 3719 return (x << 32) | (x >> 32); 3720 } 3721 3722 // Copy len longwords from s to d, word-swapping as we go. The 3723 // destination array is reversed. 3724 static void reverse_words(unsigned long *s, unsigned long *d, int len) { 3725 d += len; 3726 while(len-- > 0) { 3727 d--; 3728 *d = swap(*s); 3729 s++; 3730 } 3731 } 3732 3733 // The threshold at which squaring is advantageous was determined 3734 // experimentally on an i7-3930K (Ivy Bridge) CPU @ 3.5GHz. 3735 #define MONTGOMERY_SQUARING_THRESHOLD 64 3736 3737 void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints, 3738 jint len, jlong inv, 3739 jint *m_ints) { 3740 assert(len % 2 == 0, "array length in montgomery_multiply must be even"); 3741 int longwords = len/2; 3742 3743 // Make very sure we don't use so much space that the stack might 3744 // overflow. 512 jints corresponds to an 16384-bit integer and 3745 // will use here a total of 8k bytes of stack space. 3746 int total_allocation = longwords * sizeof (unsigned long) * 4; 3747 guarantee(total_allocation <= 8192, "must be"); 3748 unsigned long *scratch = (unsigned long *)alloca(total_allocation); 3749 3750 // Local scratch arrays 3751 unsigned long 3752 *a = scratch + 0 * longwords, 3753 *b = scratch + 1 * longwords, 3754 *n = scratch + 2 * longwords, 3755 *m = scratch + 3 * longwords; 3756 3757 reverse_words((unsigned long *)a_ints, a, longwords); 3758 reverse_words((unsigned long *)b_ints, b, longwords); 3759 reverse_words((unsigned long *)n_ints, n, longwords); 3760 3761 ::montgomery_multiply(a, b, n, m, (unsigned long)inv, longwords); 3762 3763 reverse_words(m, (unsigned long *)m_ints, longwords); 3764 } 3765 3766 void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints, 3767 jint len, jlong inv, 3768 jint *m_ints) { 3769 assert(len % 2 == 0, "array length in montgomery_square must be even"); 3770 int longwords = len/2; 3771 3772 // Make very sure we don't use so much space that the stack might 3773 // overflow. 512 jints corresponds to an 16384-bit integer and 3774 // will use here a total of 6k bytes of stack space. 3775 int total_allocation = longwords * sizeof (unsigned long) * 3; 3776 guarantee(total_allocation <= 8192, "must be"); 3777 unsigned long *scratch = (unsigned long *)alloca(total_allocation); 3778 3779 // Local scratch arrays 3780 unsigned long 3781 *a = scratch + 0 * longwords, 3782 *n = scratch + 1 * longwords, 3783 *m = scratch + 2 * longwords; 3784 3785 reverse_words((unsigned long *)a_ints, a, longwords); 3786 reverse_words((unsigned long *)n_ints, n, longwords); 3787 3788 if (len >= MONTGOMERY_SQUARING_THRESHOLD) { 3789 ::montgomery_square(a, n, m, (unsigned long)inv, longwords); 3790 } else { 3791 ::montgomery_multiply(a, a, n, m, (unsigned long)inv, longwords); 3792 } 3793 3794 reverse_words(m, (unsigned long *)m_ints, longwords); 3795 } 3796 3797 #endif // WINDOWS 3798 3799 #ifdef COMPILER2 3800 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame 3801 // 3802 //------------------------------generate_exception_blob--------------------------- 3803 // creates exception blob at the end 3804 // Using exception blob, this code is jumped from a compiled method. 3805 // (see emit_exception_handler in x86_64.ad file) 3806 // 3807 // Given an exception pc at a call we call into the runtime for the 3808 // handler in this method. This handler might merely restore state 3809 // (i.e. callee save registers) unwind the frame and jump to the 3810 // exception handler for the nmethod if there is no Java level handler 3811 // for the nmethod. 3812 // 3813 // This code is entered with a jmp. 3814 // 3815 // Arguments: 3816 // rax: exception oop 3817 // rdx: exception pc 3818 // 3819 // Results: 3820 // rax: exception oop 3821 // rdx: exception pc in caller or ??? 3822 // destination: exception handler of caller 3823 // 3824 // Note: the exception pc MUST be at a call (precise debug information) 3825 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved. 3826 // 3827 3828 void OptoRuntime::generate_exception_blob() { 3829 assert(!OptoRuntime::is_callee_saved_register(RDX_num), ""); 3830 assert(!OptoRuntime::is_callee_saved_register(RAX_num), ""); 3831 assert(!OptoRuntime::is_callee_saved_register(RCX_num), ""); 3832 3833 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 3834 3835 // Allocate space for the code 3836 ResourceMark rm; 3837 // Setup code generation tools 3838 CodeBuffer buffer("exception_blob", 2048, 1024); 3839 MacroAssembler* masm = new MacroAssembler(&buffer); 3840 3841 3842 address start = __ pc(); 3843 3844 // Exception pc is 'return address' for stack walker 3845 __ push(rdx); 3846 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog 3847 3848 // Save callee-saved registers. See x86_64.ad. 3849 3850 // rbp is an implicitly saved callee saved register (i.e., the calling 3851 // convention will save/restore it in the prolog/epilog). Other than that 3852 // there are no callee save registers now that adapter frames are gone. 3853 3854 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); 3855 3856 // Store exception in Thread object. We cannot pass any arguments to the 3857 // handle_exception call, since we do not want to make any assumption 3858 // about the size of the frame where the exception happened in. 3859 // c_rarg0 is either rdi (Linux) or rcx (Windows). 3860 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax); 3861 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); 3862 3863 // This call does all the hard work. It checks if an exception handler 3864 // exists in the method. 3865 // If so, it returns the handler address. 3866 // If not, it prepares for stack-unwinding, restoring the callee-save 3867 // registers of the frame being removed. 3868 // 3869 // address OptoRuntime::handle_exception_C(JavaThread* thread) 3870 3871 // At a method handle call, the stack may not be properly aligned 3872 // when returning with an exception. 3873 address the_pc = __ pc(); 3874 __ set_last_Java_frame(noreg, noreg, the_pc); 3875 __ mov(c_rarg0, r15_thread); 3876 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack 3877 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); 3878 3879 // Set an oopmap for the call site. This oopmap will only be used if we 3880 // are unwinding the stack. Hence, all locations will be dead. 3881 // Callee-saved registers will be the same as the frame above (i.e., 3882 // handle_exception_stub), since they were restored when we got the 3883 // exception. 3884 3885 OopMapSet* oop_maps = new OopMapSet(); 3886 3887 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 3888 3889 __ reset_last_Java_frame(false); 3890 3891 // Restore callee-saved registers 3892 3893 // rbp is an implicitly saved callee-saved register (i.e., the calling 3894 // convention will save restore it in prolog/epilog) Other than that 3895 // there are no callee save registers now that adapter frames are gone. 3896 3897 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt)); 3898 3899 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog 3900 __ pop(rdx); // No need for exception pc anymore 3901 3902 // rax: exception handler 3903 3904 // We have a handler in rax (could be deopt blob). 3905 __ mov(r8, rax); 3906 3907 // Get the exception oop 3908 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 3909 // Get the exception pc in case we are deoptimized 3910 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 3911 #ifdef ASSERT 3912 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD); 3913 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD); 3914 #endif 3915 // Clear the exception oop so GC no longer processes it as a root. 3916 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD); 3917 3918 // rax: exception oop 3919 // r8: exception handler 3920 // rdx: exception pc 3921 // Jump to handler 3922 3923 __ jmp(r8); 3924 3925 // Make sure all code is generated 3926 masm->flush(); 3927 3928 // Set exception blob 3929 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); 3930 } 3931 #endif // COMPILER2