1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 virtual void call_VM_leaf_base(
51 address entry_point, // the entry point
52 int number_of_arguments, // the number of arguments to pop after the call
53 Label *retaddr = NULL
54 );
55
56 virtual void call_VM_leaf_base(
57 address entry_point, // the entry point
58 int number_of_arguments, // the number of arguments to pop after the call
59 Label &retaddr) {
60 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
61 }
62
63 // This is the base routine called by the different versions of call_VM. The interpreter
64 // may customize this version by overriding it for its purposes (e.g., to save/restore
65 // additional registers when doing a VM call).
66 //
67 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
68 // returns the register which contains the thread upon return. If a thread register has been
69 // specified, the return value will correspond to that register. If no last_java_sp is specified
70 // (noreg) than rsp will be used instead.
71 virtual void call_VM_base( // returns the register containing the thread upon return
72 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
73 Register java_thread, // the thread if computed before ; use noreg otherwise
74 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
75 address entry_point, // the entry point
76 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
77 bool check_exceptions // whether to check for pending exceptions after return
78 );
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // True if an XOR can be used to expand narrow klass references.
83 bool use_XOR_for_compressed_class_base;
84
85 public:
86 MacroAssembler(CodeBuffer* code) : Assembler(code) {
87 use_XOR_for_compressed_class_base
88 = (operand_valid_for_logical_immediate(false /*is32*/,
89 (uint64_t)Universe::narrow_klass_base())
90 && ((uint64_t)Universe::narrow_klass_base()
91 > (1UL << log2_intptr(Universe::narrow_klass_range()))));
92 }
93
94 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
95 // The implementation is only non-empty for the InterpreterMacroAssembler,
96 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
97 virtual void check_and_handle_popframe(Register java_thread);
98 virtual void check_and_handle_earlyret(Register java_thread);
99
100 void safepoint_poll(Label& slow_path);
101 void safepoint_poll_acquire(Label& slow_path);
102
103 // Biased locking support
104 // lock_reg and obj_reg must be loaded up with the appropriate values.
105 // swap_reg is killed.
106 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
107 // Optional slow case is for implementations (interpreter and C1) which branch to
108 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
109 // Returns offset of first potentially-faulting instruction for null
110 // check info (currently consumed only by C1). If
111 // swap_reg_contains_mark is true then returns -1 as it is assumed
112 // the calling code has already passed any potential faults.
113 int biased_locking_enter(Register lock_reg, Register obj_reg,
114 Register swap_reg, Register tmp_reg,
115 bool swap_reg_contains_mark,
116 Label& done, Label* slow_case = NULL,
117 BiasedLockingCounters* counters = NULL);
118 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
119
120
121 // Helper functions for statistics gathering.
122 // Unconditional atomic increment.
123 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
124 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
125 lea(tmp1, counter_addr);
126 atomic_incw(tmp1, tmp2, tmp3);
127 }
128 // Load Effective Address
129 void lea(Register r, const Address &a) {
130 InstructionMark im(this);
131 code_section()->relocate(inst_mark(), a.rspec());
132 a.lea(this, r);
133 }
134
135 void addmw(Address a, Register incr, Register scratch) {
136 ldrw(scratch, a);
137 addw(scratch, scratch, incr);
138 strw(scratch, a);
139 }
140
141 // Add constant to memory word
142 void addmw(Address a, int imm, Register scratch) {
143 ldrw(scratch, a);
144 if (imm > 0)
145 addw(scratch, scratch, (unsigned)imm);
146 else
147 subw(scratch, scratch, (unsigned)-imm);
148 strw(scratch, a);
149 }
150
151 void bind(Label& L) {
152 Assembler::bind(L);
153 code()->clear_last_insn();
154 }
155
156 void membar(Membar_mask_bits order_constraint);
157
158 using Assembler::ldr;
159 using Assembler::str;
160
161 void ldr(Register Rx, const Address &adr);
162 void ldrw(Register Rw, const Address &adr);
163 void str(Register Rx, const Address &adr);
164 void strw(Register Rx, const Address &adr);
165
166 // Frame creation and destruction shared between JITs.
167 void build_frame(int framesize);
168 void remove_frame(int framesize);
169
170 virtual void _call_Unimplemented(address call_site) {
171 mov(rscratch2, call_site);
172 haltsim();
173 }
174
175 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
176
177 virtual void notify(int type);
178
179 // aliases defined in AARCH64 spec
180
181 template<class T>
182 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
183
184 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
185 inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
186
187 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
188 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
189
190 void cset(Register Rd, Assembler::Condition cond) {
191 csinc(Rd, zr, zr, ~cond);
192 }
193 void csetw(Register Rd, Assembler::Condition cond) {
194 csincw(Rd, zr, zr, ~cond);
195 }
196
197 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
198 csneg(Rd, Rn, Rn, ~cond);
199 }
200 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
201 csnegw(Rd, Rn, Rn, ~cond);
202 }
203
204 inline void movw(Register Rd, Register Rn) {
205 if (Rd == sp || Rn == sp) {
206 addw(Rd, Rn, 0U);
207 } else {
208 orrw(Rd, zr, Rn);
209 }
210 }
211 inline void mov(Register Rd, Register Rn) {
212 assert(Rd != r31_sp && Rn != r31_sp, "should be");
213 if (Rd == Rn) {
214 } else if (Rd == sp || Rn == sp) {
215 add(Rd, Rn, 0U);
216 } else {
217 orr(Rd, zr, Rn);
218 }
219 }
220
221 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
222 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
223
224 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
225 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
226
227 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
228 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
229
230 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
231 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
232 }
233 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
234 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
235 }
236
237 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
238 bfmw(Rd, Rn, lsb, (lsb + width - 1));
239 }
240 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
241 bfm(Rd, Rn, lsb , (lsb + width - 1));
242 }
243
244 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
245 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
246 }
247 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
248 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
249 }
250
251 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
253 }
254 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
255 sbfm(Rd, Rn, lsb , (lsb + width - 1));
256 }
257
258 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
259 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
260 }
261 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
262 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
263 }
264
265 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
267 }
268 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 ubfm(Rd, Rn, lsb , (lsb + width - 1));
270 }
271
272 inline void asrw(Register Rd, Register Rn, unsigned imm) {
273 sbfmw(Rd, Rn, imm, 31);
274 }
275
276 inline void asr(Register Rd, Register Rn, unsigned imm) {
277 sbfm(Rd, Rn, imm, 63);
278 }
279
280 inline void lslw(Register Rd, Register Rn, unsigned imm) {
281 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
282 }
283
284 inline void lsl(Register Rd, Register Rn, unsigned imm) {
285 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
286 }
287
288 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
289 ubfmw(Rd, Rn, imm, 31);
290 }
291
292 inline void lsr(Register Rd, Register Rn, unsigned imm) {
293 ubfm(Rd, Rn, imm, 63);
294 }
295
296 inline void rorw(Register Rd, Register Rn, unsigned imm) {
297 extrw(Rd, Rn, Rn, imm);
298 }
299
300 inline void ror(Register Rd, Register Rn, unsigned imm) {
301 extr(Rd, Rn, Rn, imm);
302 }
303
304 inline void sxtbw(Register Rd, Register Rn) {
305 sbfmw(Rd, Rn, 0, 7);
306 }
307 inline void sxthw(Register Rd, Register Rn) {
308 sbfmw(Rd, Rn, 0, 15);
309 }
310 inline void sxtb(Register Rd, Register Rn) {
311 sbfm(Rd, Rn, 0, 7);
312 }
313 inline void sxth(Register Rd, Register Rn) {
314 sbfm(Rd, Rn, 0, 15);
315 }
316 inline void sxtw(Register Rd, Register Rn) {
317 sbfm(Rd, Rn, 0, 31);
318 }
319
320 inline void uxtbw(Register Rd, Register Rn) {
321 ubfmw(Rd, Rn, 0, 7);
322 }
323 inline void uxthw(Register Rd, Register Rn) {
324 ubfmw(Rd, Rn, 0, 15);
325 }
326 inline void uxtb(Register Rd, Register Rn) {
327 ubfm(Rd, Rn, 0, 7);
328 }
329 inline void uxth(Register Rd, Register Rn) {
330 ubfm(Rd, Rn, 0, 15);
331 }
332 inline void uxtw(Register Rd, Register Rn) {
333 ubfm(Rd, Rn, 0, 31);
334 }
335
336 inline void cmnw(Register Rn, Register Rm) {
337 addsw(zr, Rn, Rm);
338 }
339 inline void cmn(Register Rn, Register Rm) {
340 adds(zr, Rn, Rm);
341 }
342
343 inline void cmpw(Register Rn, Register Rm) {
344 subsw(zr, Rn, Rm);
345 }
346 inline void cmp(Register Rn, Register Rm) {
347 subs(zr, Rn, Rm);
348 }
349
350 inline void negw(Register Rd, Register Rn) {
351 subw(Rd, zr, Rn);
352 }
353
354 inline void neg(Register Rd, Register Rn) {
355 sub(Rd, zr, Rn);
356 }
357
358 inline void negsw(Register Rd, Register Rn) {
359 subsw(Rd, zr, Rn);
360 }
361
362 inline void negs(Register Rd, Register Rn) {
363 subs(Rd, zr, Rn);
364 }
365
366 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
367 addsw(zr, Rn, Rm, kind, shift);
368 }
369 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
370 adds(zr, Rn, Rm, kind, shift);
371 }
372
373 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
374 subsw(zr, Rn, Rm, kind, shift);
375 }
376 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
377 subs(zr, Rn, Rm, kind, shift);
378 }
379
380 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
381 subw(Rd, zr, Rn, kind, shift);
382 }
383
384 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
385 sub(Rd, zr, Rn, kind, shift);
386 }
387
388 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
389 subsw(Rd, zr, Rn, kind, shift);
390 }
391
392 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
393 subs(Rd, zr, Rn, kind, shift);
394 }
395
396 inline void mnegw(Register Rd, Register Rn, Register Rm) {
397 msubw(Rd, Rn, Rm, zr);
398 }
399 inline void mneg(Register Rd, Register Rn, Register Rm) {
400 msub(Rd, Rn, Rm, zr);
401 }
402
403 inline void mulw(Register Rd, Register Rn, Register Rm) {
404 maddw(Rd, Rn, Rm, zr);
405 }
406 inline void mul(Register Rd, Register Rn, Register Rm) {
407 madd(Rd, Rn, Rm, zr);
408 }
409
410 inline void smnegl(Register Rd, Register Rn, Register Rm) {
411 smsubl(Rd, Rn, Rm, zr);
412 }
413 inline void smull(Register Rd, Register Rn, Register Rm) {
414 smaddl(Rd, Rn, Rm, zr);
415 }
416
417 inline void umnegl(Register Rd, Register Rn, Register Rm) {
418 umsubl(Rd, Rn, Rm, zr);
419 }
420 inline void umull(Register Rd, Register Rn, Register Rm) {
421 umaddl(Rd, Rn, Rm, zr);
422 }
423
424 #define WRAP(INSN) \
425 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
426 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
427 nop(); \
428 Assembler::INSN(Rd, Rn, Rm, Ra); \
429 }
430
431 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
432 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
433 #undef WRAP
434
435
436 // macro assembly operations needed for aarch64
437
438 // first two private routines for loading 32 bit or 64 bit constants
439 private:
440
441 void mov_immediate64(Register dst, u_int64_t imm64);
442 void mov_immediate32(Register dst, u_int32_t imm32);
443
444 int push(unsigned int bitset, Register stack);
445 int pop(unsigned int bitset, Register stack);
446
447 void mov(Register dst, Address a);
448
449 public:
450 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
451 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
452
453 // Push and pop everything that might be clobbered by a native
454 // runtime call except rscratch1 and rscratch2. (They are always
455 // scratch, so we don't have to protect them.) Only save the lower
456 // 64 bits of each vector register.
457 void push_call_clobbered_registers();
458 void pop_call_clobbered_registers();
459 void push_call_clobbered_fp_registers();
460 void pop_call_clobbered_fp_registers();
461
462 // now mov instructions for loading absolute addresses and 32 or
463 // 64 bit integers
464
465 inline void mov(Register dst, address addr)
466 {
467 mov_immediate64(dst, (u_int64_t)addr);
468 }
469
470 inline void mov(Register dst, u_int64_t imm64)
471 {
472 mov_immediate64(dst, imm64);
473 }
474
475 inline void movw(Register dst, u_int32_t imm32)
476 {
477 mov_immediate32(dst, imm32);
478 }
479
480 inline void mov(Register dst, long l)
481 {
482 mov(dst, (u_int64_t)l);
483 }
484
485 inline void mov(Register dst, int i)
486 {
487 mov(dst, (long)i);
488 }
489
490 void mov(Register dst, RegisterOrConstant src) {
491 if (src.is_register())
492 mov(dst, src.as_register());
493 else
494 mov(dst, src.as_constant());
495 }
496
497 void movptr(Register r, uintptr_t imm64);
498
499 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
500
501 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
502 orr(Vd, T, Vn, Vn);
503 }
504
505 public:
506
507 // Generalized Test Bit And Branch, including a "far" variety which
508 // spans more than 32KiB.
509 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
510 assert(cond == EQ || cond == NE, "must be");
511
512 if (far)
513 cond = ~cond;
514
515 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
516 if (cond == Assembler::EQ)
517 branch = &Assembler::tbz;
518 else
519 branch = &Assembler::tbnz;
520
521 if (far) {
522 Label L;
523 (this->*branch)(Rt, bitpos, L);
524 b(dest);
525 bind(L);
526 } else {
527 (this->*branch)(Rt, bitpos, dest);
528 }
529 }
530
531 // macro instructions for accessing and updating floating point
532 // status register
533 //
534 // FPSR : op1 == 011
535 // CRn == 0100
536 // CRm == 0100
537 // op2 == 001
538
539 inline void get_fpsr(Register reg)
540 {
541 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
542 }
543
544 inline void set_fpsr(Register reg)
545 {
546 msr(0b011, 0b0100, 0b0100, 0b001, reg);
547 }
548
549 inline void clear_fpsr()
550 {
551 msr(0b011, 0b0100, 0b0100, 0b001, zr);
552 }
553
554 // DCZID_EL0: op1 == 011
555 // CRn == 0000
556 // CRm == 0000
557 // op2 == 111
558 inline void get_dczid_el0(Register reg)
559 {
560 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
561 }
562
563 // CTR_EL0: op1 == 011
564 // CRn == 0000
565 // CRm == 0000
566 // op2 == 001
567 inline void get_ctr_el0(Register reg)
568 {
569 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
570 }
571
572 // idiv variant which deals with MINLONG as dividend and -1 as divisor
573 int corrected_idivl(Register result, Register ra, Register rb,
574 bool want_remainder, Register tmp = rscratch1);
575 int corrected_idivq(Register result, Register ra, Register rb,
576 bool want_remainder, Register tmp = rscratch1);
577
578 // Support for NULL-checks
579 //
580 // Generates code that causes a NULL OS exception if the content of reg is NULL.
581 // If the accessed location is M[reg + offset] and the offset is known, provide the
582 // offset. No explicit code generation is needed if the offset is within a certain
583 // range (0 <= offset <= page_size).
584
585 virtual void null_check(Register reg, int offset = -1);
586 static bool needs_explicit_null_check(intptr_t offset);
587
588 static address target_addr_for_insn(address insn_addr, unsigned insn);
589 static address target_addr_for_insn(address insn_addr) {
590 unsigned insn = *(unsigned*)insn_addr;
591 return target_addr_for_insn(insn_addr, insn);
592 }
593
594 // Required platform-specific helpers for Label::patch_instructions.
595 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
596 static int pd_patch_instruction_size(address branch, address target);
597 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
598 pd_patch_instruction_size(branch, target);
599 }
600 static address pd_call_destination(address branch) {
601 return target_addr_for_insn(branch);
602 }
603 #ifndef PRODUCT
604 static void pd_print_patched_instruction(address branch);
605 #endif
606
607 static int patch_oop(address insn_addr, address o);
608 static int patch_narrow_klass(address insn_addr, narrowKlass n);
609
610 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
611
612 // The following 4 methods return the offset of the appropriate move instruction
613
614 // Support for fast byte/short loading with zero extension (depending on particular CPU)
615 int load_unsigned_byte(Register dst, Address src);
616 int load_unsigned_short(Register dst, Address src);
617
618 // Support for fast byte/short loading with sign extension (depending on particular CPU)
619 int load_signed_byte(Register dst, Address src);
620 int load_signed_short(Register dst, Address src);
621
622 int load_signed_byte32(Register dst, Address src);
623 int load_signed_short32(Register dst, Address src);
624
625 // Support for sign-extension (hi:lo = extend_sign(lo))
626 void extend_sign(Register hi, Register lo);
627
628 // Load and store values by size and signed-ness
629 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
630 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
631
632 // Support for inc/dec with optimal instruction selection depending on value
633
634 // x86_64 aliases an unqualified register/address increment and
635 // decrement to call incrementq and decrementq but also supports
636 // explicitly sized calls to incrementq/decrementq or
637 // incrementl/decrementl
638
639 // for aarch64 the proper convention would be to use
640 // increment/decrement for 64 bit operatons and
641 // incrementw/decrementw for 32 bit operations. so when porting
642 // x86_64 code we can leave calls to increment/decrement as is,
643 // replace incrementq/decrementq with increment/decrement and
644 // replace incrementl/decrementl with incrementw/decrementw.
645
646 // n.b. increment/decrement calls with an Address destination will
647 // need to use a scratch register to load the value to be
648 // incremented. increment/decrement calls which add or subtract a
649 // constant value greater than 2^12 will need to use a 2nd scratch
650 // register to hold the constant. so, a register increment/decrement
651 // may trash rscratch2 and an address increment/decrement trash
652 // rscratch and rscratch2
653
654 void decrementw(Address dst, int value = 1);
655 void decrementw(Register reg, int value = 1);
656
657 void decrement(Register reg, int value = 1);
658 void decrement(Address dst, int value = 1);
659
660 void incrementw(Address dst, int value = 1);
661 void incrementw(Register reg, int value = 1);
662
663 void increment(Register reg, int value = 1);
664 void increment(Address dst, int value = 1);
665
666
667 // Alignment
668 void align(int modulus);
669
670 // Stack frame creation/removal
671 void enter()
672 {
673 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
674 mov(rfp, sp);
675 }
676 void leave()
677 {
678 mov(sp, rfp);
679 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
680 }
681
682 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
683 // The pointer will be loaded into the thread register.
684 void get_thread(Register thread);
685
686
687 // Support for VM calls
688 //
689 // It is imperative that all calls into the VM are handled via the call_VM macros.
690 // They make sure that the stack linkage is setup correctly. call_VM's correspond
691 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
692
693
694 void call_VM(Register oop_result,
695 address entry_point,
696 bool check_exceptions = true);
697 void call_VM(Register oop_result,
698 address entry_point,
699 Register arg_1,
700 bool check_exceptions = true);
701 void call_VM(Register oop_result,
702 address entry_point,
703 Register arg_1, Register arg_2,
704 bool check_exceptions = true);
705 void call_VM(Register oop_result,
706 address entry_point,
707 Register arg_1, Register arg_2, Register arg_3,
708 bool check_exceptions = true);
709
710 // Overloadings with last_Java_sp
711 void call_VM(Register oop_result,
712 Register last_java_sp,
713 address entry_point,
714 int number_of_arguments = 0,
715 bool check_exceptions = true);
716 void call_VM(Register oop_result,
717 Register last_java_sp,
718 address entry_point,
719 Register arg_1, bool
720 check_exceptions = true);
721 void call_VM(Register oop_result,
722 Register last_java_sp,
723 address entry_point,
724 Register arg_1, Register arg_2,
725 bool check_exceptions = true);
726 void call_VM(Register oop_result,
727 Register last_java_sp,
728 address entry_point,
729 Register arg_1, Register arg_2, Register arg_3,
730 bool check_exceptions = true);
731
732 void get_vm_result (Register oop_result, Register thread);
733 void get_vm_result_2(Register metadata_result, Register thread);
734
735 // These always tightly bind to MacroAssembler::call_VM_base
736 // bypassing the virtual implementation
737 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
738 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
739 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
740 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
741 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
742
743 void call_VM_leaf(address entry_point,
744 int number_of_arguments = 0);
745 void call_VM_leaf(address entry_point,
746 Register arg_1);
747 void call_VM_leaf(address entry_point,
748 Register arg_1, Register arg_2);
749 void call_VM_leaf(address entry_point,
750 Register arg_1, Register arg_2, Register arg_3);
751
752 // These always tightly bind to MacroAssembler::call_VM_leaf_base
753 // bypassing the virtual implementation
754 void super_call_VM_leaf(address entry_point);
755 void super_call_VM_leaf(address entry_point, Register arg_1);
756 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
757 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
758 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
759
760 // last Java Frame (fills frame anchor)
761 void set_last_Java_frame(Register last_java_sp,
762 Register last_java_fp,
763 address last_java_pc,
764 Register scratch);
765
766 void set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 Label &last_java_pc,
769 Register scratch);
770
771 void set_last_Java_frame(Register last_java_sp,
772 Register last_java_fp,
773 Register last_java_pc,
774 Register scratch);
775
776 void reset_last_Java_frame(Register thread);
777
778 // thread in the default location (rthread)
779 void reset_last_Java_frame(bool clear_fp);
780
781 // Stores
782 void store_check(Register obj); // store check for obj - register is destroyed afterwards
783 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
784
785 void resolve_jobject(Register value, Register thread, Register tmp);
786
787 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
788 void c2bool(Register x);
789
790 // oop manipulations
791 void load_klass(Register dst, Register src);
792 void store_klass(Register dst, Register src);
793 void cmp_klass(Register oop, Register trial_klass, Register tmp);
794
795 void resolve_oop_handle(Register result, Register tmp = r5);
796 void load_mirror(Register dst, Register method, Register tmp = r5);
797
798 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
799 Register tmp1, Register tmp_thread);
800
801 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
802 Register tmp1, Register tmp_thread);
803
804 // Resolves obj for access. Result is placed in the same register.
805 // All other registers are preserved.
806 void resolve(DecoratorSet decorators, Register obj);
807
808 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
809 Register thread_tmp = noreg, DecoratorSet decorators = 0);
810
811 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
812 Register thread_tmp = noreg, DecoratorSet decorators = 0);
813 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
814 Register tmp_thread = noreg, DecoratorSet decorators = 0);
815
816 // currently unimplemented
817 // Used for storing NULL. All other oop constants should be
818 // stored using routines that take a jobject.
819 void store_heap_oop_null(Address dst);
820
821 void load_prototype_header(Register dst, Register src);
822
823 void store_klass_gap(Register dst, Register src);
824
825 // This dummy is to prevent a call to store_heap_oop from
826 // converting a zero (like NULL) into a Register by giving
827 // the compiler two choices it can't resolve
828
829 void store_heap_oop(Address dst, void* dummy);
830
831 void encode_heap_oop(Register d, Register s);
832 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
833 void decode_heap_oop(Register d, Register s);
834 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
835 void encode_heap_oop_not_null(Register r);
836 void decode_heap_oop_not_null(Register r);
837 void encode_heap_oop_not_null(Register dst, Register src);
838 void decode_heap_oop_not_null(Register dst, Register src);
839
840 void set_narrow_oop(Register dst, jobject obj);
841
842 void encode_klass_not_null(Register r);
843 void decode_klass_not_null(Register r);
844 void encode_klass_not_null(Register dst, Register src);
845 void decode_klass_not_null(Register dst, Register src);
846
847 void set_narrow_klass(Register dst, Klass* k);
848
849 // if heap base register is used - reinit it with the correct value
850 void reinit_heapbase();
851
852 DEBUG_ONLY(void verify_heapbase(const char* msg);)
853
854 void push_CPU_state(bool save_vectors = false);
855 void pop_CPU_state(bool restore_vectors = false) ;
856
857 // Round up to a power of two
858 void round_to(Register reg, int modulus);
859
860 // allocation
861 void eden_allocate(
862 Register obj, // result: pointer to object after successful allocation
863 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
864 int con_size_in_bytes, // object size in bytes if known at compile time
865 Register t1, // temp register
866 Label& slow_case // continuation point if fast allocation fails
867 );
868 void tlab_allocate(
869 Register obj, // result: pointer to object after successful allocation
870 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
871 int con_size_in_bytes, // object size in bytes if known at compile time
872 Register t1, // temp register
873 Register t2, // temp register
874 Label& slow_case // continuation point if fast allocation fails
875 );
876 void zero_memory(Register addr, Register len, Register t1);
877 void verify_tlab();
878
879 // interface method calling
880 void lookup_interface_method(Register recv_klass,
881 Register intf_klass,
882 RegisterOrConstant itable_index,
883 Register method_result,
884 Register scan_temp,
885 Label& no_such_interface,
886 bool return_method = true);
887
888 // virtual method calling
889 // n.b. x86 allows RegisterOrConstant for vtable_index
890 void lookup_virtual_method(Register recv_klass,
891 RegisterOrConstant vtable_index,
892 Register method_result);
893
894 // Test sub_klass against super_klass, with fast and slow paths.
895
896 // The fast path produces a tri-state answer: yes / no / maybe-slow.
897 // One of the three labels can be NULL, meaning take the fall-through.
898 // If super_check_offset is -1, the value is loaded up from super_klass.
899 // No registers are killed, except temp_reg.
900 void check_klass_subtype_fast_path(Register sub_klass,
901 Register super_klass,
902 Register temp_reg,
903 Label* L_success,
904 Label* L_failure,
905 Label* L_slow_path,
906 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
907
908 // The rest of the type check; must be wired to a corresponding fast path.
909 // It does not repeat the fast path logic, so don't use it standalone.
910 // The temp_reg and temp2_reg can be noreg, if no temps are available.
911 // Updates the sub's secondary super cache as necessary.
912 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
913 void check_klass_subtype_slow_path(Register sub_klass,
914 Register super_klass,
915 Register temp_reg,
916 Register temp2_reg,
917 Label* L_success,
918 Label* L_failure,
919 bool set_cond_codes = false);
920
921 // Simplified, combined version, good for typical uses.
922 // Falls through on failure.
923 void check_klass_subtype(Register sub_klass,
924 Register super_klass,
925 Register temp_reg,
926 Label& L_success);
927
928 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
929
930
931 // Debugging
932
933 // only if +VerifyOops
934 void verify_oop(Register reg, const char* s = "broken oop");
935 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
936
937 // TODO: verify method and klass metadata (compare against vptr?)
938 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
939 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
940
941 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
942 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
943
944 // only if +VerifyFPU
945 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
946
947 // prints msg, dumps registers and stops execution
948 void stop(const char* msg);
949
950 // prints msg and continues
951 void warn(const char* msg);
952
953 static void debug64(char* msg, int64_t pc, int64_t regs[]);
954
955 void untested() { stop("untested"); }
956
957 void unimplemented(const char* what = "");
958
959 void should_not_reach_here() { stop("should not reach here"); }
960
961 // Stack overflow checking
962 void bang_stack_with_offset(int offset) {
963 // stack grows down, caller passes positive offset
964 assert(offset > 0, "must bang with negative offset");
965 sub(rscratch2, sp, offset);
966 str(zr, Address(rscratch2));
967 }
968
969 // Writes to stack successive pages until offset reached to check for
970 // stack overflow + shadow pages. Also, clobbers tmp
971 void bang_stack_size(Register size, Register tmp);
972
973 // Check for reserved stack access in method being exited (for JIT)
974 void reserved_stack_check();
975
976 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
977 Register tmp,
978 int offset);
979
980 // Support for serializing memory accesses between threads
981 void serialize_memory(Register thread, Register tmp);
982
983 // Arithmetics
984
985 void addptr(const Address &dst, int32_t src);
986 void cmpptr(Register src1, Address src2);
987
988 void cmpoop(Register obj1, Register obj2);
989
990 // Various forms of CAS
991
992 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
993 Label &suceed, Label *fail);
994 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
995 Label &suceed, Label *fail);
996
997 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
998 Label &suceed, Label *fail);
999
1000 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1001 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1002 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1003 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1004
1005 void atomic_xchg(Register prev, Register newv, Register addr);
1006 void atomic_xchgw(Register prev, Register newv, Register addr);
1007 void atomic_xchgal(Register prev, Register newv, Register addr);
1008 void atomic_xchgalw(Register prev, Register newv, Register addr);
1009
1010 void orptr(Address adr, RegisterOrConstant src) {
1011 ldr(rscratch1, adr);
1012 if (src.is_register())
1013 orr(rscratch1, rscratch1, src.as_register());
1014 else
1015 orr(rscratch1, rscratch1, src.as_constant());
1016 str(rscratch1, adr);
1017 }
1018
1019 // A generic CAS; success or failure is in the EQ flag.
1020 // Clobbers rscratch1
1021 void cmpxchg(Register addr, Register expected, Register new_val,
1022 enum operand_size size,
1023 bool acquire, bool release, bool weak,
1024 Register result);
1025 private:
1026 void compare_eq(Register rn, Register rm, enum operand_size size);
1027
1028 public:
1029 // Calls
1030
1031 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1032
1033 static bool far_branches() {
1034 return ReservedCodeCacheSize > branch_range || UseAOT;
1035 }
1036
1037 // Jumps that can reach anywhere in the code cache.
1038 // Trashes tmp.
1039 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1040 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1041
1042 static int far_branch_size() {
1043 if (far_branches()) {
1044 return 3 * 4; // adrp, add, br
1045 } else {
1046 return 4;
1047 }
1048 }
1049
1050 // Emit the CompiledIC call idiom
1051 address ic_call(address entry, jint method_index = 0);
1052
1053 public:
1054
1055 // Data
1056
1057 void mov_metadata(Register dst, Metadata* obj);
1058 Address allocate_metadata_address(Metadata* obj);
1059 Address constant_oop_address(jobject obj);
1060
1061 void movoop(Register dst, jobject obj, bool immediate = false);
1062
1063 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1064 void kernel_crc32(Register crc, Register buf, Register len,
1065 Register table0, Register table1, Register table2, Register table3,
1066 Register tmp, Register tmp2, Register tmp3);
1067 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1068 void kernel_crc32c(Register crc, Register buf, Register len,
1069 Register table0, Register table1, Register table2, Register table3,
1070 Register tmp, Register tmp2, Register tmp3);
1071
1072 // Stack push and pop individual 64 bit registers
1073 void push(Register src);
1074 void pop(Register dst);
1075
1076 // push all registers onto the stack
1077 void pusha();
1078 void popa();
1079
1080 void repne_scan(Register addr, Register value, Register count,
1081 Register scratch);
1082 void repne_scanw(Register addr, Register value, Register count,
1083 Register scratch);
1084
1085 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1086 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1087
1088 // If a constant does not fit in an immediate field, generate some
1089 // number of MOV instructions and then perform the operation
1090 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1091 add_sub_imm_insn insn1,
1092 add_sub_reg_insn insn2);
1093 // Seperate vsn which sets the flags
1094 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1095 add_sub_imm_insn insn1,
1096 add_sub_reg_insn insn2);
1097
1098 #define WRAP(INSN) \
1099 void INSN(Register Rd, Register Rn, unsigned imm) { \
1100 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1101 } \
1102 \
1103 void INSN(Register Rd, Register Rn, Register Rm, \
1104 enum shift_kind kind, unsigned shift = 0) { \
1105 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1106 } \
1107 \
1108 void INSN(Register Rd, Register Rn, Register Rm) { \
1109 Assembler::INSN(Rd, Rn, Rm); \
1110 } \
1111 \
1112 void INSN(Register Rd, Register Rn, Register Rm, \
1113 ext::operation option, int amount = 0) { \
1114 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1115 }
1116
1117 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1118
1119 #undef WRAP
1120 #define WRAP(INSN) \
1121 void INSN(Register Rd, Register Rn, unsigned imm) { \
1122 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1123 } \
1124 \
1125 void INSN(Register Rd, Register Rn, Register Rm, \
1126 enum shift_kind kind, unsigned shift = 0) { \
1127 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1128 } \
1129 \
1130 void INSN(Register Rd, Register Rn, Register Rm) { \
1131 Assembler::INSN(Rd, Rn, Rm); \
1132 } \
1133 \
1134 void INSN(Register Rd, Register Rn, Register Rm, \
1135 ext::operation option, int amount = 0) { \
1136 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1137 }
1138
1139 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1140
1141 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1142 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1143 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1144 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1145
1146 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1147
1148 void tableswitch(Register index, jint lowbound, jint highbound,
1149 Label &jumptable, Label &jumptable_end, int stride = 1) {
1150 adr(rscratch1, jumptable);
1151 subsw(rscratch2, index, lowbound);
1152 subsw(zr, rscratch2, highbound - lowbound);
1153 br(Assembler::HS, jumptable_end);
1154 add(rscratch1, rscratch1, rscratch2,
1155 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1156 br(rscratch1);
1157 }
1158
1159 // Form an address from base + offset in Rd. Rd may or may not
1160 // actually be used: you must use the Address that is returned. It
1161 // is up to you to ensure that the shift provided matches the size
1162 // of your data.
1163 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1164
1165 // Return true iff an address is within the 48-bit AArch64 address
1166 // space.
1167 bool is_valid_AArch64_address(address a) {
1168 return ((uint64_t)a >> 48) == 0;
1169 }
1170
1171 // Load the base of the cardtable byte map into reg.
1172 void load_byte_map_base(Register reg);
1173
1174 // Prolog generator routines to support switch between x86 code and
1175 // generated ARM code
1176
1177 // routine to generate an x86 prolog for a stub function which
1178 // bootstraps into the generated ARM code which directly follows the
1179 // stub
1180 //
1181
1182 public:
1183 // enum used for aarch64--x86 linkage to define return type of x86 function
1184 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1185
1186 #ifdef BUILTIN_SIM
1187 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1188 #else
1189 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1190 #endif
1191
1192 // special version of call_VM_leaf_base needed for aarch64 simulator
1193 // where we need to specify both the gp and fp arg counts and the
1194 // return type so that the linkage routine from aarch64 to x86 and
1195 // back knows which aarch64 registers to copy to x86 registers and
1196 // which x86 result register to copy back to an aarch64 register
1197
1198 void call_VM_leaf_base1(
1199 address entry_point, // the entry point
1200 int number_of_gp_arguments, // the number of gp reg arguments to pass
1201 int number_of_fp_arguments, // the number of fp reg arguments to pass
1202 ret_type type, // the return type for the call
1203 Label* retaddr = NULL
1204 );
1205
1206 void ldr_constant(Register dest, const Address &const_addr) {
1207 if (NearCpool) {
1208 ldr(dest, const_addr);
1209 } else {
1210 unsigned long offset;
1211 adrp(dest, InternalAddress(const_addr.target()), offset);
1212 ldr(dest, Address(dest, offset));
1213 }
1214 }
1215
1216 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1217 address read_polling_page(Register r, relocInfo::relocType rtype);
1218 void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1219
1220 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1221 void update_byte_crc32(Register crc, Register val, Register table);
1222 void update_word_crc32(Register crc, Register v, Register tmp,
1223 Register table0, Register table1, Register table2, Register table3,
1224 bool upper = false);
1225
1226 void string_compare(Register str1, Register str2,
1227 Register cnt1, Register cnt2, Register result,
1228 Register tmp1, Register tmp2, FloatRegister vtmp1,
1229 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1230
1231 void has_negatives(Register ary1, Register len, Register result);
1232
1233 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1234 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1235
1236 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1237 int elem_size);
1238
1239 void fill_words(Register base, Register cnt, Register value);
1240 void zero_words(Register base, u_int64_t cnt);
1241 void zero_words(Register ptr, Register cnt);
1242 void zero_dcache_blocks(Register base, Register cnt);
1243
1244 static const int zero_words_block_size;
1245
1246 void byte_array_inflate(Register src, Register dst, Register len,
1247 FloatRegister vtmp1, FloatRegister vtmp2,
1248 FloatRegister vtmp3, Register tmp4);
1249
1250 void char_array_compress(Register src, Register dst, Register len,
1251 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1252 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1253 Register result);
1254
1255 void encode_iso_array(Register src, Register dst,
1256 Register len, Register result,
1257 FloatRegister Vtmp1, FloatRegister Vtmp2,
1258 FloatRegister Vtmp3, FloatRegister Vtmp4);
1259 void string_indexof(Register str1, Register str2,
1260 Register cnt1, Register cnt2,
1261 Register tmp1, Register tmp2,
1262 Register tmp3, Register tmp4,
1263 Register tmp5, Register tmp6,
1264 int int_cnt1, Register result, int ae);
1265 void string_indexof_char(Register str1, Register cnt1,
1266 Register ch, Register result,
1267 Register tmp1, Register tmp2, Register tmp3);
1268 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1269 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1270 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1271 FloatRegister tmpC4, Register tmp1, Register tmp2,
1272 Register tmp3, Register tmp4, Register tmp5);
1273 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1274 address pio2, address dsin_coef, address dcos_coef);
1275 private:
1276 // begin trigonometric functions support block
1277 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1278 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1279 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1280 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1281 // end trigonometric functions support block
1282 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1283 Register src1, Register src2);
1284 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1285 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1286 }
1287 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1288 Register y, Register y_idx, Register z,
1289 Register carry, Register product,
1290 Register idx, Register kdx);
1291 void multiply_128_x_128_loop(Register y, Register z,
1292 Register carry, Register carry2,
1293 Register idx, Register jdx,
1294 Register yz_idx1, Register yz_idx2,
1295 Register tmp, Register tmp3, Register tmp4,
1296 Register tmp7, Register product_hi);
1297 void kernel_crc32_using_crc32(Register crc, Register buf,
1298 Register len, Register tmp0, Register tmp1, Register tmp2,
1299 Register tmp3);
1300 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1301 Register len, Register tmp0, Register tmp1, Register tmp2,
1302 Register tmp3);
1303 public:
1304 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1305 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1306 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1307 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1308 // ISB may be needed because of a safepoint
1309 void maybe_isb() { isb(); }
1310
1311 private:
1312 // Return the effective address r + (r1 << ext) + offset.
1313 // Uses rscratch2.
1314 Address offsetted_address(Register r, Register r1, Address::extend ext,
1315 int offset, int size);
1316
1317 private:
1318 // Returns an address on the stack which is reachable with a ldr/str of size
1319 // Uses rscratch2 if the address is not directly reachable
1320 Address spill_address(int size, int offset, Register tmp=rscratch2);
1321
1322 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1323
1324 // Check whether two loads/stores can be merged into ldp/stp.
1325 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1326
1327 // Merge current load/store with previous load/store into ldp/stp.
1328 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1329
1330 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1331 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1332
1333 public:
1334 void spill(Register Rx, bool is64, int offset) {
1335 if (is64) {
1336 str(Rx, spill_address(8, offset));
1337 } else {
1338 strw(Rx, spill_address(4, offset));
1339 }
1340 }
1341 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1342 str(Vx, T, spill_address(1 << (int)T, offset));
1343 }
1344 void unspill(Register Rx, bool is64, int offset) {
1345 if (is64) {
1346 ldr(Rx, spill_address(8, offset));
1347 } else {
1348 ldrw(Rx, spill_address(4, offset));
1349 }
1350 }
1351 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1352 ldr(Vx, T, spill_address(1 << (int)T, offset));
1353 }
1354 void spill_copy128(int src_offset, int dst_offset,
1355 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1356 if (src_offset < 512 && (src_offset & 7) == 0 &&
1357 dst_offset < 512 && (dst_offset & 7) == 0) {
1358 ldp(tmp1, tmp2, Address(sp, src_offset));
1359 stp(tmp1, tmp2, Address(sp, dst_offset));
1360 } else {
1361 unspill(tmp1, true, src_offset);
1362 spill(tmp1, true, dst_offset);
1363 unspill(tmp1, true, src_offset+8);
1364 spill(tmp1, true, dst_offset+8);
1365 }
1366 }
1367 };
1368
1369 #ifdef ASSERT
1370 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1371 #endif
1372
1373 /**
1374 * class SkipIfEqual:
1375 *
1376 * Instantiating this class will result in assembly code being output that will
1377 * jump around any code emitted between the creation of the instance and it's
1378 * automatic destruction at the end of a scope block, depending on the value of
1379 * the flag passed to the constructor, which will be checked at run-time.
1380 */
1381 class SkipIfEqual {
1382 private:
1383 MacroAssembler* _masm;
1384 Label _label;
1385
1386 public:
1387 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1388 ~SkipIfEqual();
1389 };
1390
1391 struct tableswitch {
1392 Register _reg;
1393 int _insn_index; jint _first_key; jint _last_key;
1394 Label _after;
1395 Label _branches;
1396 };
1397
1398 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP