1 //
2 // Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 source_hpp %{
530 #if INCLUDE_ZGC
531 #include "gc/z/zBarrierSetAssembler.hpp"
532 #endif
533 #if INCLUDE_SHENANDOAHGC
534 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
535 #endif
536 %}
537
538 //----------SOURCE BLOCK-------------------------------------------------------
539 // This is a block of C++ code which provides values, functions, and
540 // definitions necessary in the rest of the architecture description
541 source %{
542 #define RELOC_IMM64 Assembler::imm_operand
543 #define RELOC_DISP32 Assembler::disp32_operand
544
545 #define __ _masm.
546
547 static bool generate_vzeroupper(Compile* C) {
548 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
549 }
550
551 static int clear_avx_size() {
552 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
553 }
554
555 // !!!!! Special hack to get all types of calls to specify the byte offset
556 // from the start of the call to the point where the return address
557 // will point.
558 int MachCallStaticJavaNode::ret_addr_offset()
559 {
560 int offset = 5; // 5 bytes from start of call to where return address points
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 int MachCallDynamicJavaNode::ret_addr_offset()
566 {
567 int offset = 15; // 15 bytes from start of call to where return address points
568 offset += clear_avx_size();
569 return offset;
570 }
571
572 int MachCallRuntimeNode::ret_addr_offset() {
573 int offset = 13; // movq r10,#addr; callq (r10)
574 offset += clear_avx_size();
575 return offset;
576 }
577
578 // Indicate if the safepoint node needs the polling page as an input,
579 // it does if the polling page is more than disp32 away.
580 bool SafePointNode::needs_polling_address_input()
581 {
582 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
583 }
584
585 //
586 // Compute padding required for nodes which need alignment
587 //
588
589 // The address of the call instruction needs to be 4-byte aligned to
590 // ensure that it does not span a cache line so that it can be patched.
591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
592 {
593 current_offset += clear_avx_size(); // skip vzeroupper
594 current_offset += 1; // skip call opcode byte
595 return align_up(current_offset, alignment_required()) - current_offset;
596 }
597
598 // The address of the call instruction needs to be 4-byte aligned to
599 // ensure that it does not span a cache line so that it can be patched.
600 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
601 {
602 current_offset += clear_avx_size(); // skip vzeroupper
603 current_offset += 11; // skip movq instruction + call opcode byte
604 return align_up(current_offset, alignment_required()) - current_offset;
605 }
606
607 // EMIT_RM()
608 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
609 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
610 cbuf.insts()->emit_int8(c);
611 }
612
613 // EMIT_CC()
614 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
615 unsigned char c = (unsigned char) (f1 | f2);
616 cbuf.insts()->emit_int8(c);
617 }
618
619 // EMIT_OPCODE()
620 void emit_opcode(CodeBuffer &cbuf, int code) {
621 cbuf.insts()->emit_int8((unsigned char) code);
622 }
623
624 // EMIT_OPCODE() w/ relocation information
625 void emit_opcode(CodeBuffer &cbuf,
626 int code, relocInfo::relocType reloc, int offset, int format)
627 {
628 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
629 emit_opcode(cbuf, code);
630 }
631
632 // EMIT_D8()
633 void emit_d8(CodeBuffer &cbuf, int d8) {
634 cbuf.insts()->emit_int8((unsigned char) d8);
635 }
636
637 // EMIT_D16()
638 void emit_d16(CodeBuffer &cbuf, int d16) {
639 cbuf.insts()->emit_int16(d16);
640 }
641
642 // EMIT_D32()
643 void emit_d32(CodeBuffer &cbuf, int d32) {
644 cbuf.insts()->emit_int32(d32);
645 }
646
647 // EMIT_D64()
648 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
649 cbuf.insts()->emit_int64(d64);
650 }
651
652 // emit 32 bit value and construct relocation entry from relocInfo::relocType
653 void emit_d32_reloc(CodeBuffer& cbuf,
654 int d32,
655 relocInfo::relocType reloc,
656 int format)
657 {
658 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
659 cbuf.relocate(cbuf.insts_mark(), reloc, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 // emit 32 bit value and construct relocation entry from RelocationHolder
664 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
665 #ifdef ASSERT
666 if (rspec.reloc()->type() == relocInfo::oop_type &&
667 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
668 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
669 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
670 }
671 #endif
672 cbuf.relocate(cbuf.insts_mark(), rspec, format);
673 cbuf.insts()->emit_int32(d32);
674 }
675
676 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
677 address next_ip = cbuf.insts_end() + 4;
678 emit_d32_reloc(cbuf, (int) (addr - next_ip),
679 external_word_Relocation::spec(addr),
680 RELOC_DISP32);
681 }
682
683
684 // emit 64 bit value and construct relocation entry from relocInfo::relocType
685 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
686 cbuf.relocate(cbuf.insts_mark(), reloc, format);
687 cbuf.insts()->emit_int64(d64);
688 }
689
690 // emit 64 bit value and construct relocation entry from RelocationHolder
691 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
692 #ifdef ASSERT
693 if (rspec.reloc()->type() == relocInfo::oop_type &&
694 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
695 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
696 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
697 "cannot embed scavengable oops in code");
698 }
699 #endif
700 cbuf.relocate(cbuf.insts_mark(), rspec, format);
701 cbuf.insts()->emit_int64(d64);
702 }
703
704 // Access stack slot for load or store
705 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
706 {
707 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
708 if (-0x80 <= disp && disp < 0x80) {
709 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
710 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
711 emit_d8(cbuf, disp); // Displacement // R/M byte
712 } else {
713 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
714 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
715 emit_d32(cbuf, disp); // Displacement // R/M byte
716 }
717 }
718
719 // rRegI ereg, memory mem) %{ // emit_reg_mem
720 void encode_RegMem(CodeBuffer &cbuf,
721 int reg,
722 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
723 {
724 assert(disp_reloc == relocInfo::none, "cannot have disp");
725 int regenc = reg & 7;
726 int baseenc = base & 7;
727 int indexenc = index & 7;
728
729 // There is no index & no scale, use form without SIB byte
730 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
731 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
732 if (disp == 0 && base != RBP_enc && base != R13_enc) {
733 emit_rm(cbuf, 0x0, regenc, baseenc); // *
734 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
735 // If 8-bit displacement, mode 0x1
736 emit_rm(cbuf, 0x1, regenc, baseenc); // *
737 emit_d8(cbuf, disp);
738 } else {
739 // If 32-bit displacement
740 if (base == -1) { // Special flag for absolute address
741 emit_rm(cbuf, 0x0, regenc, 0x5); // *
742 if (disp_reloc != relocInfo::none) {
743 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
744 } else {
745 emit_d32(cbuf, disp);
746 }
747 } else {
748 // Normal base + offset
749 emit_rm(cbuf, 0x2, regenc, baseenc); // *
750 if (disp_reloc != relocInfo::none) {
751 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
752 } else {
753 emit_d32(cbuf, disp);
754 }
755 }
756 }
757 } else {
758 // Else, encode with the SIB byte
759 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
760 if (disp == 0 && base != RBP_enc && base != R13_enc) {
761 // If no displacement
762 emit_rm(cbuf, 0x0, regenc, 0x4); // *
763 emit_rm(cbuf, scale, indexenc, baseenc);
764 } else {
765 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
766 // If 8-bit displacement, mode 0x1
767 emit_rm(cbuf, 0x1, regenc, 0x4); // *
768 emit_rm(cbuf, scale, indexenc, baseenc);
769 emit_d8(cbuf, disp);
770 } else {
771 // If 32-bit displacement
772 if (base == 0x04 ) {
773 emit_rm(cbuf, 0x2, regenc, 0x4);
774 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
775 } else {
776 emit_rm(cbuf, 0x2, regenc, 0x4);
777 emit_rm(cbuf, scale, indexenc, baseenc); // *
778 }
779 if (disp_reloc != relocInfo::none) {
780 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
781 } else {
782 emit_d32(cbuf, disp);
783 }
784 }
785 }
786 }
787 }
788
789 // This could be in MacroAssembler but it's fairly C2 specific
790 void emit_cmpfp_fixup(MacroAssembler& _masm) {
791 Label exit;
792 __ jccb(Assembler::noParity, exit);
793 __ pushf();
794 //
795 // comiss/ucomiss instructions set ZF,PF,CF flags and
796 // zero OF,AF,SF for NaN values.
797 // Fixup flags by zeroing ZF,PF so that compare of NaN
798 // values returns 'less than' result (CF is set).
799 // Leave the rest of flags unchanged.
800 //
801 // 7 6 5 4 3 2 1 0
802 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
803 // 0 0 1 0 1 0 1 1 (0x2B)
804 //
805 __ andq(Address(rsp, 0), 0xffffff2b);
806 __ popf();
807 __ bind(exit);
808 }
809
810 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
811 Label done;
812 __ movl(dst, -1);
813 __ jcc(Assembler::parity, done);
814 __ jcc(Assembler::below, done);
815 __ setb(Assembler::notEqual, dst);
816 __ movzbl(dst, dst);
817 __ bind(done);
818 }
819
820
821 //=============================================================================
822 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
823
824 int Compile::ConstantTable::calculate_table_base_offset() const {
825 return 0; // absolute addressing, no offset
826 }
827
828 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
829 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
830 ShouldNotReachHere();
831 }
832
833 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
834 // Empty encoding
835 }
836
837 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
838 return 0;
839 }
840
841 #ifndef PRODUCT
842 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
843 st->print("# MachConstantBaseNode (empty encoding)");
844 }
845 #endif
846
847
848 //=============================================================================
849 #ifndef PRODUCT
850 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
851 Compile* C = ra_->C;
852
853 int framesize = C->frame_size_in_bytes();
854 int bangsize = C->bang_size_in_bytes();
855 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
856 // Remove wordSize for return addr which is already pushed.
857 framesize -= wordSize;
858
859 if (C->need_stack_bang(bangsize)) {
860 framesize -= wordSize;
861 st->print("# stack bang (%d bytes)", bangsize);
862 st->print("\n\t");
863 st->print("pushq rbp\t# Save rbp");
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
867 }
868 if (framesize) {
869 st->print("\n\t");
870 st->print("subq rsp, #%d\t# Create frame",framesize);
871 }
872 } else {
873 st->print("subq rsp, #%d\t# Create frame",framesize);
874 st->print("\n\t");
875 framesize -= wordSize;
876 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
877 if (PreserveFramePointer) {
878 st->print("\n\t");
879 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
880 if (framesize > 0) {
881 st->print("\n\t");
882 st->print("addq rbp, #%d", framesize);
883 }
884 }
885 }
886
887 if (VerifyStackAtCalls) {
888 st->print("\n\t");
889 framesize -= wordSize;
890 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
891 #ifdef ASSERT
892 st->print("\n\t");
893 st->print("# stack alignment check");
894 #endif
895 }
896 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
897 st->print("\n\t");
898 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
899 st->print("\n\t");
900 st->print("je fast_entry\t");
901 st->print("\n\t");
902 st->print("call #nmethod_entry_barrier_stub\t");
903 st->print("\n\tfast_entry:");
904 }
905 st->cr();
906 }
907 #endif
908
909 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
910 Compile* C = ra_->C;
911 MacroAssembler _masm(&cbuf);
912
913 int framesize = C->frame_size_in_bytes();
914 int bangsize = C->bang_size_in_bytes();
915
916 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
917
918 C->set_frame_complete(cbuf.insts_size());
919
920 if (C->has_mach_constant_base_node()) {
921 // NOTE: We set the table base offset here because users might be
922 // emitted before MachConstantBaseNode.
923 Compile::ConstantTable& constant_table = C->constant_table();
924 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
925 }
926 }
927
928 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
929 {
930 return MachNode::size(ra_); // too many variables; just compute it
931 // the hard way
932 }
933
934 int MachPrologNode::reloc() const
935 {
936 return 0; // a large enough number
937 }
938
939 //=============================================================================
940 #ifndef PRODUCT
941 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
942 {
943 Compile* C = ra_->C;
944 if (generate_vzeroupper(C)) {
945 st->print("vzeroupper");
946 st->cr(); st->print("\t");
947 }
948
949 int framesize = C->frame_size_in_bytes();
950 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
951 // Remove word for return adr already pushed
952 // and RBP
953 framesize -= 2*wordSize;
954
955 if (framesize) {
956 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
957 st->print("\t");
958 }
959
960 st->print_cr("popq rbp");
961 if (do_polling() && C->is_method_compilation()) {
962 st->print("\t");
963 if (SafepointMechanism::uses_thread_local_poll()) {
964 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
965 "testl rax, [rscratch1]\t"
966 "# Safepoint: poll for GC");
967 } else if (Assembler::is_polling_page_far()) {
968 st->print_cr("movq rscratch1, #polling_page_address\n\t"
969 "testl rax, [rscratch1]\t"
970 "# Safepoint: poll for GC");
971 } else {
972 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
973 "# Safepoint: poll for GC");
974 }
975 }
976 }
977 #endif
978
979 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
980 {
981 Compile* C = ra_->C;
982 MacroAssembler _masm(&cbuf);
983
984 if (generate_vzeroupper(C)) {
985 // Clear upper bits of YMM registers when current compiled code uses
986 // wide vectors to avoid AVX <-> SSE transition penalty during call.
987 __ vzeroupper();
988 }
989
990 int framesize = C->frame_size_in_bytes();
991 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
992 // Remove word for return adr already pushed
993 // and RBP
994 framesize -= 2*wordSize;
995
996 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
997
998 if (framesize) {
999 emit_opcode(cbuf, Assembler::REX_W);
1000 if (framesize < 0x80) {
1001 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1002 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1003 emit_d8(cbuf, framesize);
1004 } else {
1005 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1006 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1007 emit_d32(cbuf, framesize);
1008 }
1009 }
1010
1011 // popq rbp
1012 emit_opcode(cbuf, 0x58 | RBP_enc);
1013
1014 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1015 __ reserved_stack_check();
1016 }
1017
1018 if (do_polling() && C->is_method_compilation()) {
1019 MacroAssembler _masm(&cbuf);
1020 if (SafepointMechanism::uses_thread_local_poll()) {
1021 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1022 __ relocate(relocInfo::poll_return_type);
1023 __ testl(rax, Address(rscratch1, 0));
1024 } else {
1025 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1026 if (Assembler::is_polling_page_far()) {
1027 __ lea(rscratch1, polling_page);
1028 __ relocate(relocInfo::poll_return_type);
1029 __ testl(rax, Address(rscratch1, 0));
1030 } else {
1031 __ testl(rax, polling_page);
1032 }
1033 }
1034 }
1035 }
1036
1037 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1038 {
1039 return MachNode::size(ra_); // too many variables; just compute it
1040 // the hard way
1041 }
1042
1043 int MachEpilogNode::reloc() const
1044 {
1045 return 2; // a large enough number
1046 }
1047
1048 const Pipeline* MachEpilogNode::pipeline() const
1049 {
1050 return MachNode::pipeline_class();
1051 }
1052
1053 int MachEpilogNode::safepoint_offset() const
1054 {
1055 return 0;
1056 }
1057
1058 //=============================================================================
1059
1060 enum RC {
1061 rc_bad,
1062 rc_int,
1063 rc_float,
1064 rc_stack
1065 };
1066
1067 static enum RC rc_class(OptoReg::Name reg)
1068 {
1069 if( !OptoReg::is_valid(reg) ) return rc_bad;
1070
1071 if (OptoReg::is_stack(reg)) return rc_stack;
1072
1073 VMReg r = OptoReg::as_VMReg(reg);
1074
1075 if (r->is_Register()) return rc_int;
1076
1077 assert(r->is_XMMRegister(), "must be");
1078 return rc_float;
1079 }
1080
1081 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1082 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1083 int src_hi, int dst_hi, uint ireg, outputStream* st);
1084
1085 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1086 int stack_offset, int reg, uint ireg, outputStream* st);
1087
1088 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1089 int dst_offset, uint ireg, outputStream* st) {
1090 if (cbuf) {
1091 MacroAssembler _masm(cbuf);
1092 switch (ireg) {
1093 case Op_VecS:
1094 __ movq(Address(rsp, -8), rax);
1095 __ movl(rax, Address(rsp, src_offset));
1096 __ movl(Address(rsp, dst_offset), rax);
1097 __ movq(rax, Address(rsp, -8));
1098 break;
1099 case Op_VecD:
1100 __ pushq(Address(rsp, src_offset));
1101 __ popq (Address(rsp, dst_offset));
1102 break;
1103 case Op_VecX:
1104 __ pushq(Address(rsp, src_offset));
1105 __ popq (Address(rsp, dst_offset));
1106 __ pushq(Address(rsp, src_offset+8));
1107 __ popq (Address(rsp, dst_offset+8));
1108 break;
1109 case Op_VecY:
1110 __ vmovdqu(Address(rsp, -32), xmm0);
1111 __ vmovdqu(xmm0, Address(rsp, src_offset));
1112 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1113 __ vmovdqu(xmm0, Address(rsp, -32));
1114 break;
1115 case Op_VecZ:
1116 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1117 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1118 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1119 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1120 break;
1121 default:
1122 ShouldNotReachHere();
1123 }
1124 #ifndef PRODUCT
1125 } else {
1126 switch (ireg) {
1127 case Op_VecS:
1128 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1129 "movl rax, [rsp + #%d]\n\t"
1130 "movl [rsp + #%d], rax\n\t"
1131 "movq rax, [rsp - #8]",
1132 src_offset, dst_offset);
1133 break;
1134 case Op_VecD:
1135 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1136 "popq [rsp + #%d]",
1137 src_offset, dst_offset);
1138 break;
1139 case Op_VecX:
1140 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1141 "popq [rsp + #%d]\n\t"
1142 "pushq [rsp + #%d]\n\t"
1143 "popq [rsp + #%d]",
1144 src_offset, dst_offset, src_offset+8, dst_offset+8);
1145 break;
1146 case Op_VecY:
1147 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1148 "vmovdqu xmm0, [rsp + #%d]\n\t"
1149 "vmovdqu [rsp + #%d], xmm0\n\t"
1150 "vmovdqu xmm0, [rsp - #32]",
1151 src_offset, dst_offset);
1152 break;
1153 case Op_VecZ:
1154 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1155 "vmovdqu xmm0, [rsp + #%d]\n\t"
1156 "vmovdqu [rsp + #%d], xmm0\n\t"
1157 "vmovdqu xmm0, [rsp - #64]",
1158 src_offset, dst_offset);
1159 break;
1160 default:
1161 ShouldNotReachHere();
1162 }
1163 #endif
1164 }
1165 }
1166
1167 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1168 PhaseRegAlloc* ra_,
1169 bool do_size,
1170 outputStream* st) const {
1171 assert(cbuf != NULL || st != NULL, "sanity");
1172 // Get registers to move
1173 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1174 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1175 OptoReg::Name dst_second = ra_->get_reg_second(this);
1176 OptoReg::Name dst_first = ra_->get_reg_first(this);
1177
1178 enum RC src_second_rc = rc_class(src_second);
1179 enum RC src_first_rc = rc_class(src_first);
1180 enum RC dst_second_rc = rc_class(dst_second);
1181 enum RC dst_first_rc = rc_class(dst_first);
1182
1183 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1184 "must move at least 1 register" );
1185
1186 if (src_first == dst_first && src_second == dst_second) {
1187 // Self copy, no move
1188 return 0;
1189 }
1190 if (bottom_type()->isa_vect() != NULL) {
1191 uint ireg = ideal_reg();
1192 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1193 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1194 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1195 // mem -> mem
1196 int src_offset = ra_->reg2offset(src_first);
1197 int dst_offset = ra_->reg2offset(dst_first);
1198 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1199 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1200 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1201 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1202 int stack_offset = ra_->reg2offset(dst_first);
1203 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1204 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1205 int stack_offset = ra_->reg2offset(src_first);
1206 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1207 } else {
1208 ShouldNotReachHere();
1209 }
1210 return 0;
1211 }
1212 if (src_first_rc == rc_stack) {
1213 // mem ->
1214 if (dst_first_rc == rc_stack) {
1215 // mem -> mem
1216 assert(src_second != dst_first, "overlap");
1217 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1218 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1219 // 64-bit
1220 int src_offset = ra_->reg2offset(src_first);
1221 int dst_offset = ra_->reg2offset(dst_first);
1222 if (cbuf) {
1223 MacroAssembler _masm(cbuf);
1224 __ pushq(Address(rsp, src_offset));
1225 __ popq (Address(rsp, dst_offset));
1226 #ifndef PRODUCT
1227 } else {
1228 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1229 "popq [rsp + #%d]",
1230 src_offset, dst_offset);
1231 #endif
1232 }
1233 } else {
1234 // 32-bit
1235 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1236 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1237 // No pushl/popl, so:
1238 int src_offset = ra_->reg2offset(src_first);
1239 int dst_offset = ra_->reg2offset(dst_first);
1240 if (cbuf) {
1241 MacroAssembler _masm(cbuf);
1242 __ movq(Address(rsp, -8), rax);
1243 __ movl(rax, Address(rsp, src_offset));
1244 __ movl(Address(rsp, dst_offset), rax);
1245 __ movq(rax, Address(rsp, -8));
1246 #ifndef PRODUCT
1247 } else {
1248 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1249 "movl rax, [rsp + #%d]\n\t"
1250 "movl [rsp + #%d], rax\n\t"
1251 "movq rax, [rsp - #8]",
1252 src_offset, dst_offset);
1253 #endif
1254 }
1255 }
1256 return 0;
1257 } else if (dst_first_rc == rc_int) {
1258 // mem -> gpr
1259 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1260 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1261 // 64-bit
1262 int offset = ra_->reg2offset(src_first);
1263 if (cbuf) {
1264 MacroAssembler _masm(cbuf);
1265 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1266 #ifndef PRODUCT
1267 } else {
1268 st->print("movq %s, [rsp + #%d]\t# spill",
1269 Matcher::regName[dst_first],
1270 offset);
1271 #endif
1272 }
1273 } else {
1274 // 32-bit
1275 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1276 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1277 int offset = ra_->reg2offset(src_first);
1278 if (cbuf) {
1279 MacroAssembler _masm(cbuf);
1280 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1281 #ifndef PRODUCT
1282 } else {
1283 st->print("movl %s, [rsp + #%d]\t# spill",
1284 Matcher::regName[dst_first],
1285 offset);
1286 #endif
1287 }
1288 }
1289 return 0;
1290 } else if (dst_first_rc == rc_float) {
1291 // mem-> xmm
1292 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1293 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1294 // 64-bit
1295 int offset = ra_->reg2offset(src_first);
1296 if (cbuf) {
1297 MacroAssembler _masm(cbuf);
1298 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1299 #ifndef PRODUCT
1300 } else {
1301 st->print("%s %s, [rsp + #%d]\t# spill",
1302 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1303 Matcher::regName[dst_first],
1304 offset);
1305 #endif
1306 }
1307 } else {
1308 // 32-bit
1309 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1310 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1311 int offset = ra_->reg2offset(src_first);
1312 if (cbuf) {
1313 MacroAssembler _masm(cbuf);
1314 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1315 #ifndef PRODUCT
1316 } else {
1317 st->print("movss %s, [rsp + #%d]\t# spill",
1318 Matcher::regName[dst_first],
1319 offset);
1320 #endif
1321 }
1322 }
1323 return 0;
1324 }
1325 } else if (src_first_rc == rc_int) {
1326 // gpr ->
1327 if (dst_first_rc == rc_stack) {
1328 // gpr -> mem
1329 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1330 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1331 // 64-bit
1332 int offset = ra_->reg2offset(dst_first);
1333 if (cbuf) {
1334 MacroAssembler _masm(cbuf);
1335 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1336 #ifndef PRODUCT
1337 } else {
1338 st->print("movq [rsp + #%d], %s\t# spill",
1339 offset,
1340 Matcher::regName[src_first]);
1341 #endif
1342 }
1343 } else {
1344 // 32-bit
1345 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1346 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1347 int offset = ra_->reg2offset(dst_first);
1348 if (cbuf) {
1349 MacroAssembler _masm(cbuf);
1350 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1351 #ifndef PRODUCT
1352 } else {
1353 st->print("movl [rsp + #%d], %s\t# spill",
1354 offset,
1355 Matcher::regName[src_first]);
1356 #endif
1357 }
1358 }
1359 return 0;
1360 } else if (dst_first_rc == rc_int) {
1361 // gpr -> gpr
1362 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1363 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1364 // 64-bit
1365 if (cbuf) {
1366 MacroAssembler _masm(cbuf);
1367 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1368 as_Register(Matcher::_regEncode[src_first]));
1369 #ifndef PRODUCT
1370 } else {
1371 st->print("movq %s, %s\t# spill",
1372 Matcher::regName[dst_first],
1373 Matcher::regName[src_first]);
1374 #endif
1375 }
1376 return 0;
1377 } else {
1378 // 32-bit
1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1384 as_Register(Matcher::_regEncode[src_first]));
1385 #ifndef PRODUCT
1386 } else {
1387 st->print("movl %s, %s\t# spill",
1388 Matcher::regName[dst_first],
1389 Matcher::regName[src_first]);
1390 #endif
1391 }
1392 return 0;
1393 }
1394 } else if (dst_first_rc == rc_float) {
1395 // gpr -> xmm
1396 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1397 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1398 // 64-bit
1399 if (cbuf) {
1400 MacroAssembler _masm(cbuf);
1401 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1402 #ifndef PRODUCT
1403 } else {
1404 st->print("movdq %s, %s\t# spill",
1405 Matcher::regName[dst_first],
1406 Matcher::regName[src_first]);
1407 #endif
1408 }
1409 } else {
1410 // 32-bit
1411 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1412 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 st->print("movdl %s, %s\t# spill",
1419 Matcher::regName[dst_first],
1420 Matcher::regName[src_first]);
1421 #endif
1422 }
1423 }
1424 return 0;
1425 }
1426 } else if (src_first_rc == rc_float) {
1427 // xmm ->
1428 if (dst_first_rc == rc_stack) {
1429 // xmm -> mem
1430 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1431 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1432 // 64-bit
1433 int offset = ra_->reg2offset(dst_first);
1434 if (cbuf) {
1435 MacroAssembler _masm(cbuf);
1436 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("movsd [rsp + #%d], %s\t# spill",
1440 offset,
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 } else {
1445 // 32-bit
1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448 int offset = ra_->reg2offset(dst_first);
1449 if (cbuf) {
1450 MacroAssembler _masm(cbuf);
1451 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1452 #ifndef PRODUCT
1453 } else {
1454 st->print("movss [rsp + #%d], %s\t# spill",
1455 offset,
1456 Matcher::regName[src_first]);
1457 #endif
1458 }
1459 }
1460 return 0;
1461 } else if (dst_first_rc == rc_int) {
1462 // xmm -> gpr
1463 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1464 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1465 // 64-bit
1466 if (cbuf) {
1467 MacroAssembler _masm(cbuf);
1468 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1469 #ifndef PRODUCT
1470 } else {
1471 st->print("movdq %s, %s\t# spill",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 } else {
1477 // 32-bit
1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480 if (cbuf) {
1481 MacroAssembler _masm(cbuf);
1482 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484 } else {
1485 st->print("movdl %s, %s\t# spill",
1486 Matcher::regName[dst_first],
1487 Matcher::regName[src_first]);
1488 #endif
1489 }
1490 }
1491 return 0;
1492 } else if (dst_first_rc == rc_float) {
1493 // xmm -> xmm
1494 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1495 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1496 // 64-bit
1497 if (cbuf) {
1498 MacroAssembler _masm(cbuf);
1499 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1500 #ifndef PRODUCT
1501 } else {
1502 st->print("%s %s, %s\t# spill",
1503 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1504 Matcher::regName[dst_first],
1505 Matcher::regName[src_first]);
1506 #endif
1507 }
1508 } else {
1509 // 32-bit
1510 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1511 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1512 if (cbuf) {
1513 MacroAssembler _masm(cbuf);
1514 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1515 #ifndef PRODUCT
1516 } else {
1517 st->print("%s %s, %s\t# spill",
1518 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1519 Matcher::regName[dst_first],
1520 Matcher::regName[src_first]);
1521 #endif
1522 }
1523 }
1524 return 0;
1525 }
1526 }
1527
1528 assert(0," foo ");
1529 Unimplemented();
1530 return 0;
1531 }
1532
1533 #ifndef PRODUCT
1534 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1535 implementation(NULL, ra_, false, st);
1536 }
1537 #endif
1538
1539 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1540 implementation(&cbuf, ra_, false, NULL);
1541 }
1542
1543 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1544 return MachNode::size(ra_);
1545 }
1546
1547 //=============================================================================
1548 #ifndef PRODUCT
1549 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1550 {
1551 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1552 int reg = ra_->get_reg_first(this);
1553 st->print("leaq %s, [rsp + #%d]\t# box lock",
1554 Matcher::regName[reg], offset);
1555 }
1556 #endif
1557
1558 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1559 {
1560 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1561 int reg = ra_->get_encode(this);
1562 if (offset >= 0x80) {
1563 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1564 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1565 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1566 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1567 emit_d32(cbuf, offset);
1568 } else {
1569 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1570 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1571 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1572 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1573 emit_d8(cbuf, offset);
1574 }
1575 }
1576
1577 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1578 {
1579 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1580 return (offset < 0x80) ? 5 : 8; // REX
1581 }
1582
1583 //=============================================================================
1584 #ifndef PRODUCT
1585 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1586 {
1587 if (UseCompressedClassPointers) {
1588 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1589 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1590 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1591 } else {
1592 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1593 "# Inline cache check");
1594 }
1595 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1596 st->print_cr("\tnop\t# nops to align entry point");
1597 }
1598 #endif
1599
1600 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1601 {
1602 MacroAssembler masm(&cbuf);
1603 uint insts_size = cbuf.insts_size();
1604 if (UseCompressedClassPointers) {
1605 masm.load_klass(rscratch1, j_rarg0);
1606 masm.cmpptr(rax, rscratch1);
1607 } else {
1608 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1609 }
1610
1611 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1612
1613 /* WARNING these NOPs are critical so that verified entry point is properly
1614 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1615 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1616 if (OptoBreakpoint) {
1617 // Leave space for int3
1618 nops_cnt -= 1;
1619 }
1620 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1621 if (nops_cnt > 0)
1622 masm.nop(nops_cnt);
1623 }
1624
1625 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1626 {
1627 return MachNode::size(ra_); // too many variables; just compute it
1628 // the hard way
1629 }
1630
1631
1632 //=============================================================================
1633
1634 int Matcher::regnum_to_fpu_offset(int regnum)
1635 {
1636 return regnum - 32; // The FP registers are in the second chunk
1637 }
1638
1639 // This is UltraSparc specific, true just means we have fast l2f conversion
1640 const bool Matcher::convL2FSupported(void) {
1641 return true;
1642 }
1643
1644 // Is this branch offset short enough that a short branch can be used?
1645 //
1646 // NOTE: If the platform does not provide any short branch variants, then
1647 // this method should return false for offset 0.
1648 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1649 // The passed offset is relative to address of the branch.
1650 // On 86 a branch displacement is calculated relative to address
1651 // of a next instruction.
1652 offset -= br_size;
1653
1654 // the short version of jmpConUCF2 contains multiple branches,
1655 // making the reach slightly less
1656 if (rule == jmpConUCF2_rule)
1657 return (-126 <= offset && offset <= 125);
1658 return (-128 <= offset && offset <= 127);
1659 }
1660
1661 const bool Matcher::isSimpleConstant64(jlong value) {
1662 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1663 //return value == (int) value; // Cf. storeImmL and immL32.
1664
1665 // Probably always true, even if a temp register is required.
1666 return true;
1667 }
1668
1669 // The ecx parameter to rep stosq for the ClearArray node is in words.
1670 const bool Matcher::init_array_count_is_in_bytes = false;
1671
1672 // No additional cost for CMOVL.
1673 const int Matcher::long_cmove_cost() { return 0; }
1674
1675 // No CMOVF/CMOVD with SSE2
1676 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1677
1678 // Does the CPU require late expand (see block.cpp for description of late expand)?
1679 const bool Matcher::require_postalloc_expand = false;
1680
1681 // Do we need to mask the count passed to shift instructions or does
1682 // the cpu only look at the lower 5/6 bits anyway?
1683 const bool Matcher::need_masked_shift_count = false;
1684
1685 bool Matcher::narrow_oop_use_complex_address() {
1686 assert(UseCompressedOops, "only for compressed oops code");
1687 return (LogMinObjAlignmentInBytes <= 3);
1688 }
1689
1690 bool Matcher::narrow_klass_use_complex_address() {
1691 assert(UseCompressedClassPointers, "only for compressed klass code");
1692 return (LogKlassAlignmentInBytes <= 3);
1693 }
1694
1695 bool Matcher::const_oop_prefer_decode() {
1696 // Prefer ConN+DecodeN over ConP.
1697 return true;
1698 }
1699
1700 bool Matcher::const_klass_prefer_decode() {
1701 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1702 // or condisider the following:
1703 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1704 //return Universe::narrow_klass_base() == NULL;
1705 return true;
1706 }
1707
1708 // Is it better to copy float constants, or load them directly from
1709 // memory? Intel can load a float constant from a direct address,
1710 // requiring no extra registers. Most RISCs will have to materialize
1711 // an address into a register first, so they would do better to copy
1712 // the constant from stack.
1713 const bool Matcher::rematerialize_float_constants = true; // XXX
1714
1715 // If CPU can load and store mis-aligned doubles directly then no
1716 // fixup is needed. Else we split the double into 2 integer pieces
1717 // and move it piece-by-piece. Only happens when passing doubles into
1718 // C code as the Java calling convention forces doubles to be aligned.
1719 const bool Matcher::misaligned_doubles_ok = true;
1720
1721 // No-op on amd64
1722 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1723
1724 // Advertise here if the CPU requires explicit rounding operations to
1725 // implement the UseStrictFP mode.
1726 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1727
1728 // Are floats conerted to double when stored to stack during deoptimization?
1729 // On x64 it is stored without convertion so we can use normal access.
1730 bool Matcher::float_in_double() { return false; }
1731
1732 // Do ints take an entire long register or just half?
1733 const bool Matcher::int_in_long = true;
1734
1735 // Return whether or not this register is ever used as an argument.
1736 // This function is used on startup to build the trampoline stubs in
1737 // generateOptoStub. Registers not mentioned will be killed by the VM
1738 // call in the trampoline, and arguments in those registers not be
1739 // available to the callee.
1740 bool Matcher::can_be_java_arg(int reg)
1741 {
1742 return
1743 reg == RDI_num || reg == RDI_H_num ||
1744 reg == RSI_num || reg == RSI_H_num ||
1745 reg == RDX_num || reg == RDX_H_num ||
1746 reg == RCX_num || reg == RCX_H_num ||
1747 reg == R8_num || reg == R8_H_num ||
1748 reg == R9_num || reg == R9_H_num ||
1749 reg == R12_num || reg == R12_H_num ||
1750 reg == XMM0_num || reg == XMM0b_num ||
1751 reg == XMM1_num || reg == XMM1b_num ||
1752 reg == XMM2_num || reg == XMM2b_num ||
1753 reg == XMM3_num || reg == XMM3b_num ||
1754 reg == XMM4_num || reg == XMM4b_num ||
1755 reg == XMM5_num || reg == XMM5b_num ||
1756 reg == XMM6_num || reg == XMM6b_num ||
1757 reg == XMM7_num || reg == XMM7b_num;
1758 }
1759
1760 bool Matcher::is_spillable_arg(int reg)
1761 {
1762 return can_be_java_arg(reg);
1763 }
1764
1765 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1766 // In 64 bit mode a code which use multiply when
1767 // devisor is constant is faster than hardware
1768 // DIV instruction (it uses MulHiL).
1769 return false;
1770 }
1771
1772 // Register for DIVI projection of divmodI
1773 RegMask Matcher::divI_proj_mask() {
1774 return INT_RAX_REG_mask();
1775 }
1776
1777 // Register for MODI projection of divmodI
1778 RegMask Matcher::modI_proj_mask() {
1779 return INT_RDX_REG_mask();
1780 }
1781
1782 // Register for DIVL projection of divmodL
1783 RegMask Matcher::divL_proj_mask() {
1784 return LONG_RAX_REG_mask();
1785 }
1786
1787 // Register for MODL projection of divmodL
1788 RegMask Matcher::modL_proj_mask() {
1789 return LONG_RDX_REG_mask();
1790 }
1791
1792 // Register for saving SP into on method handle invokes. Not used on x86_64.
1793 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1794 return NO_REG_mask();
1795 }
1796
1797 %}
1798
1799 //----------ENCODING BLOCK-----------------------------------------------------
1800 // This block specifies the encoding classes used by the compiler to
1801 // output byte streams. Encoding classes are parameterized macros
1802 // used by Machine Instruction Nodes in order to generate the bit
1803 // encoding of the instruction. Operands specify their base encoding
1804 // interface with the interface keyword. There are currently
1805 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1806 // COND_INTER. REG_INTER causes an operand to generate a function
1807 // which returns its register number when queried. CONST_INTER causes
1808 // an operand to generate a function which returns the value of the
1809 // constant when queried. MEMORY_INTER causes an operand to generate
1810 // four functions which return the Base Register, the Index Register,
1811 // the Scale Value, and the Offset Value of the operand when queried.
1812 // COND_INTER causes an operand to generate six functions which return
1813 // the encoding code (ie - encoding bits for the instruction)
1814 // associated with each basic boolean condition for a conditional
1815 // instruction.
1816 //
1817 // Instructions specify two basic values for encoding. Again, a
1818 // function is available to check if the constant displacement is an
1819 // oop. They use the ins_encode keyword to specify their encoding
1820 // classes (which must be a sequence of enc_class names, and their
1821 // parameters, specified in the encoding block), and they use the
1822 // opcode keyword to specify, in order, their primary, secondary, and
1823 // tertiary opcode. Only the opcode sections which a particular
1824 // instruction needs for encoding need to be specified.
1825 encode %{
1826 // Build emit functions for each basic byte or larger field in the
1827 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1828 // from C++ code in the enc_class source block. Emit functions will
1829 // live in the main source block for now. In future, we can
1830 // generalize this by adding a syntax that specifies the sizes of
1831 // fields in an order, so that the adlc can build the emit functions
1832 // automagically
1833
1834 // Emit primary opcode
1835 enc_class OpcP
1836 %{
1837 emit_opcode(cbuf, $primary);
1838 %}
1839
1840 // Emit secondary opcode
1841 enc_class OpcS
1842 %{
1843 emit_opcode(cbuf, $secondary);
1844 %}
1845
1846 // Emit tertiary opcode
1847 enc_class OpcT
1848 %{
1849 emit_opcode(cbuf, $tertiary);
1850 %}
1851
1852 // Emit opcode directly
1853 enc_class Opcode(immI d8)
1854 %{
1855 emit_opcode(cbuf, $d8$$constant);
1856 %}
1857
1858 // Emit size prefix
1859 enc_class SizePrefix
1860 %{
1861 emit_opcode(cbuf, 0x66);
1862 %}
1863
1864 enc_class reg(rRegI reg)
1865 %{
1866 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1867 %}
1868
1869 enc_class reg_reg(rRegI dst, rRegI src)
1870 %{
1871 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1872 %}
1873
1874 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1875 %{
1876 emit_opcode(cbuf, $opcode$$constant);
1877 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1878 %}
1879
1880 enc_class cdql_enc(no_rax_rdx_RegI div)
1881 %{
1882 // Full implementation of Java idiv and irem; checks for
1883 // special case as described in JVM spec., p.243 & p.271.
1884 //
1885 // normal case special case
1886 //
1887 // input : rax: dividend min_int
1888 // reg: divisor -1
1889 //
1890 // output: rax: quotient (= rax idiv reg) min_int
1891 // rdx: remainder (= rax irem reg) 0
1892 //
1893 // Code sequnce:
1894 //
1895 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1896 // 5: 75 07/08 jne e <normal>
1897 // 7: 33 d2 xor %edx,%edx
1898 // [div >= 8 -> offset + 1]
1899 // [REX_B]
1900 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1901 // c: 74 03/04 je 11 <done>
1902 // 000000000000000e <normal>:
1903 // e: 99 cltd
1904 // [div >= 8 -> offset + 1]
1905 // [REX_B]
1906 // f: f7 f9 idiv $div
1907 // 0000000000000011 <done>:
1908
1909 // cmp $0x80000000,%eax
1910 emit_opcode(cbuf, 0x3d);
1911 emit_d8(cbuf, 0x00);
1912 emit_d8(cbuf, 0x00);
1913 emit_d8(cbuf, 0x00);
1914 emit_d8(cbuf, 0x80);
1915
1916 // jne e <normal>
1917 emit_opcode(cbuf, 0x75);
1918 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1919
1920 // xor %edx,%edx
1921 emit_opcode(cbuf, 0x33);
1922 emit_d8(cbuf, 0xD2);
1923
1924 // cmp $0xffffffffffffffff,%ecx
1925 if ($div$$reg >= 8) {
1926 emit_opcode(cbuf, Assembler::REX_B);
1927 }
1928 emit_opcode(cbuf, 0x83);
1929 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1930 emit_d8(cbuf, 0xFF);
1931
1932 // je 11 <done>
1933 emit_opcode(cbuf, 0x74);
1934 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1935
1936 // <normal>
1937 // cltd
1938 emit_opcode(cbuf, 0x99);
1939
1940 // idivl (note: must be emitted by the user of this rule)
1941 // <done>
1942 %}
1943
1944 enc_class cdqq_enc(no_rax_rdx_RegL div)
1945 %{
1946 // Full implementation of Java ldiv and lrem; checks for
1947 // special case as described in JVM spec., p.243 & p.271.
1948 //
1949 // normal case special case
1950 //
1951 // input : rax: dividend min_long
1952 // reg: divisor -1
1953 //
1954 // output: rax: quotient (= rax idiv reg) min_long
1955 // rdx: remainder (= rax irem reg) 0
1956 //
1957 // Code sequnce:
1958 //
1959 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1960 // 7: 00 00 80
1961 // a: 48 39 d0 cmp %rdx,%rax
1962 // d: 75 08 jne 17 <normal>
1963 // f: 33 d2 xor %edx,%edx
1964 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1965 // 15: 74 05 je 1c <done>
1966 // 0000000000000017 <normal>:
1967 // 17: 48 99 cqto
1968 // 19: 48 f7 f9 idiv $div
1969 // 000000000000001c <done>:
1970
1971 // mov $0x8000000000000000,%rdx
1972 emit_opcode(cbuf, Assembler::REX_W);
1973 emit_opcode(cbuf, 0xBA);
1974 emit_d8(cbuf, 0x00);
1975 emit_d8(cbuf, 0x00);
1976 emit_d8(cbuf, 0x00);
1977 emit_d8(cbuf, 0x00);
1978 emit_d8(cbuf, 0x00);
1979 emit_d8(cbuf, 0x00);
1980 emit_d8(cbuf, 0x00);
1981 emit_d8(cbuf, 0x80);
1982
1983 // cmp %rdx,%rax
1984 emit_opcode(cbuf, Assembler::REX_W);
1985 emit_opcode(cbuf, 0x39);
1986 emit_d8(cbuf, 0xD0);
1987
1988 // jne 17 <normal>
1989 emit_opcode(cbuf, 0x75);
1990 emit_d8(cbuf, 0x08);
1991
1992 // xor %edx,%edx
1993 emit_opcode(cbuf, 0x33);
1994 emit_d8(cbuf, 0xD2);
1995
1996 // cmp $0xffffffffffffffff,$div
1997 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1998 emit_opcode(cbuf, 0x83);
1999 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2000 emit_d8(cbuf, 0xFF);
2001
2002 // je 1e <done>
2003 emit_opcode(cbuf, 0x74);
2004 emit_d8(cbuf, 0x05);
2005
2006 // <normal>
2007 // cqto
2008 emit_opcode(cbuf, Assembler::REX_W);
2009 emit_opcode(cbuf, 0x99);
2010
2011 // idivq (note: must be emitted by the user of this rule)
2012 // <done>
2013 %}
2014
2015 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2016 enc_class OpcSE(immI imm)
2017 %{
2018 // Emit primary opcode and set sign-extend bit
2019 // Check for 8-bit immediate, and set sign extend bit in opcode
2020 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2021 emit_opcode(cbuf, $primary | 0x02);
2022 } else {
2023 // 32-bit immediate
2024 emit_opcode(cbuf, $primary);
2025 }
2026 %}
2027
2028 enc_class OpcSErm(rRegI dst, immI imm)
2029 %{
2030 // OpcSEr/m
2031 int dstenc = $dst$$reg;
2032 if (dstenc >= 8) {
2033 emit_opcode(cbuf, Assembler::REX_B);
2034 dstenc -= 8;
2035 }
2036 // Emit primary opcode and set sign-extend bit
2037 // Check for 8-bit immediate, and set sign extend bit in opcode
2038 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2039 emit_opcode(cbuf, $primary | 0x02);
2040 } else {
2041 // 32-bit immediate
2042 emit_opcode(cbuf, $primary);
2043 }
2044 // Emit r/m byte with secondary opcode, after primary opcode.
2045 emit_rm(cbuf, 0x3, $secondary, dstenc);
2046 %}
2047
2048 enc_class OpcSErm_wide(rRegL dst, immI imm)
2049 %{
2050 // OpcSEr/m
2051 int dstenc = $dst$$reg;
2052 if (dstenc < 8) {
2053 emit_opcode(cbuf, Assembler::REX_W);
2054 } else {
2055 emit_opcode(cbuf, Assembler::REX_WB);
2056 dstenc -= 8;
2057 }
2058 // Emit primary opcode and set sign-extend bit
2059 // Check for 8-bit immediate, and set sign extend bit in opcode
2060 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2061 emit_opcode(cbuf, $primary | 0x02);
2062 } else {
2063 // 32-bit immediate
2064 emit_opcode(cbuf, $primary);
2065 }
2066 // Emit r/m byte with secondary opcode, after primary opcode.
2067 emit_rm(cbuf, 0x3, $secondary, dstenc);
2068 %}
2069
2070 enc_class Con8or32(immI imm)
2071 %{
2072 // Check for 8-bit immediate, and set sign extend bit in opcode
2073 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2074 $$$emit8$imm$$constant;
2075 } else {
2076 // 32-bit immediate
2077 $$$emit32$imm$$constant;
2078 }
2079 %}
2080
2081 enc_class opc2_reg(rRegI dst)
2082 %{
2083 // BSWAP
2084 emit_cc(cbuf, $secondary, $dst$$reg);
2085 %}
2086
2087 enc_class opc3_reg(rRegI dst)
2088 %{
2089 // BSWAP
2090 emit_cc(cbuf, $tertiary, $dst$$reg);
2091 %}
2092
2093 enc_class reg_opc(rRegI div)
2094 %{
2095 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2096 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2097 %}
2098
2099 enc_class enc_cmov(cmpOp cop)
2100 %{
2101 // CMOV
2102 $$$emit8$primary;
2103 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2104 %}
2105
2106 enc_class enc_PartialSubtypeCheck()
2107 %{
2108 Register Rrdi = as_Register(RDI_enc); // result register
2109 Register Rrax = as_Register(RAX_enc); // super class
2110 Register Rrcx = as_Register(RCX_enc); // killed
2111 Register Rrsi = as_Register(RSI_enc); // sub class
2112 Label miss;
2113 const bool set_cond_codes = true;
2114
2115 MacroAssembler _masm(&cbuf);
2116 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2117 NULL, &miss,
2118 /*set_cond_codes:*/ true);
2119 if ($primary) {
2120 __ xorptr(Rrdi, Rrdi);
2121 }
2122 __ bind(miss);
2123 %}
2124
2125 enc_class clear_avx %{
2126 debug_only(int off0 = cbuf.insts_size());
2127 if (generate_vzeroupper(Compile::current())) {
2128 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2129 // Clear upper bits of YMM registers when current compiled code uses
2130 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2131 MacroAssembler _masm(&cbuf);
2132 __ vzeroupper();
2133 }
2134 debug_only(int off1 = cbuf.insts_size());
2135 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2136 %}
2137
2138 enc_class Java_To_Runtime(method meth) %{
2139 // No relocation needed
2140 MacroAssembler _masm(&cbuf);
2141 __ mov64(r10, (int64_t) $meth$$method);
2142 __ call(r10);
2143 %}
2144
2145 enc_class Java_To_Interpreter(method meth)
2146 %{
2147 // CALL Java_To_Interpreter
2148 // This is the instruction starting address for relocation info.
2149 cbuf.set_insts_mark();
2150 $$$emit8$primary;
2151 // CALL directly to the runtime
2152 emit_d32_reloc(cbuf,
2153 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2154 runtime_call_Relocation::spec(),
2155 RELOC_DISP32);
2156 %}
2157
2158 enc_class Java_Static_Call(method meth)
2159 %{
2160 // JAVA STATIC CALL
2161 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2162 // determine who we intended to call.
2163 cbuf.set_insts_mark();
2164 $$$emit8$primary;
2165
2166 if (!_method) {
2167 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2168 runtime_call_Relocation::spec(),
2169 RELOC_DISP32);
2170 } else {
2171 int method_index = resolved_method_index(cbuf);
2172 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2173 : static_call_Relocation::spec(method_index);
2174 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2175 rspec, RELOC_DISP32);
2176 // Emit stubs for static call.
2177 address mark = cbuf.insts_mark();
2178 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2179 if (stub == NULL) {
2180 ciEnv::current()->record_failure("CodeCache is full");
2181 return;
2182 }
2183 #if INCLUDE_AOT
2184 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2185 #endif
2186 }
2187 %}
2188
2189 enc_class Java_Dynamic_Call(method meth) %{
2190 MacroAssembler _masm(&cbuf);
2191 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2192 %}
2193
2194 enc_class Java_Compiled_Call(method meth)
2195 %{
2196 // JAVA COMPILED CALL
2197 int disp = in_bytes(Method:: from_compiled_offset());
2198
2199 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2200 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2201
2202 // callq *disp(%rax)
2203 cbuf.set_insts_mark();
2204 $$$emit8$primary;
2205 if (disp < 0x80) {
2206 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2207 emit_d8(cbuf, disp); // Displacement
2208 } else {
2209 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2210 emit_d32(cbuf, disp); // Displacement
2211 }
2212 %}
2213
2214 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2215 %{
2216 // SAL, SAR, SHR
2217 int dstenc = $dst$$reg;
2218 if (dstenc >= 8) {
2219 emit_opcode(cbuf, Assembler::REX_B);
2220 dstenc -= 8;
2221 }
2222 $$$emit8$primary;
2223 emit_rm(cbuf, 0x3, $secondary, dstenc);
2224 $$$emit8$shift$$constant;
2225 %}
2226
2227 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2228 %{
2229 // SAL, SAR, SHR
2230 int dstenc = $dst$$reg;
2231 if (dstenc < 8) {
2232 emit_opcode(cbuf, Assembler::REX_W);
2233 } else {
2234 emit_opcode(cbuf, Assembler::REX_WB);
2235 dstenc -= 8;
2236 }
2237 $$$emit8$primary;
2238 emit_rm(cbuf, 0x3, $secondary, dstenc);
2239 $$$emit8$shift$$constant;
2240 %}
2241
2242 enc_class load_immI(rRegI dst, immI src)
2243 %{
2244 int dstenc = $dst$$reg;
2245 if (dstenc >= 8) {
2246 emit_opcode(cbuf, Assembler::REX_B);
2247 dstenc -= 8;
2248 }
2249 emit_opcode(cbuf, 0xB8 | dstenc);
2250 $$$emit32$src$$constant;
2251 %}
2252
2253 enc_class load_immL(rRegL dst, immL src)
2254 %{
2255 int dstenc = $dst$$reg;
2256 if (dstenc < 8) {
2257 emit_opcode(cbuf, Assembler::REX_W);
2258 } else {
2259 emit_opcode(cbuf, Assembler::REX_WB);
2260 dstenc -= 8;
2261 }
2262 emit_opcode(cbuf, 0xB8 | dstenc);
2263 emit_d64(cbuf, $src$$constant);
2264 %}
2265
2266 enc_class load_immUL32(rRegL dst, immUL32 src)
2267 %{
2268 // same as load_immI, but this time we care about zeroes in the high word
2269 int dstenc = $dst$$reg;
2270 if (dstenc >= 8) {
2271 emit_opcode(cbuf, Assembler::REX_B);
2272 dstenc -= 8;
2273 }
2274 emit_opcode(cbuf, 0xB8 | dstenc);
2275 $$$emit32$src$$constant;
2276 %}
2277
2278 enc_class load_immL32(rRegL dst, immL32 src)
2279 %{
2280 int dstenc = $dst$$reg;
2281 if (dstenc < 8) {
2282 emit_opcode(cbuf, Assembler::REX_W);
2283 } else {
2284 emit_opcode(cbuf, Assembler::REX_WB);
2285 dstenc -= 8;
2286 }
2287 emit_opcode(cbuf, 0xC7);
2288 emit_rm(cbuf, 0x03, 0x00, dstenc);
2289 $$$emit32$src$$constant;
2290 %}
2291
2292 enc_class load_immP31(rRegP dst, immP32 src)
2293 %{
2294 // same as load_immI, but this time we care about zeroes in the high word
2295 int dstenc = $dst$$reg;
2296 if (dstenc >= 8) {
2297 emit_opcode(cbuf, Assembler::REX_B);
2298 dstenc -= 8;
2299 }
2300 emit_opcode(cbuf, 0xB8 | dstenc);
2301 $$$emit32$src$$constant;
2302 %}
2303
2304 enc_class load_immP(rRegP dst, immP src)
2305 %{
2306 int dstenc = $dst$$reg;
2307 if (dstenc < 8) {
2308 emit_opcode(cbuf, Assembler::REX_W);
2309 } else {
2310 emit_opcode(cbuf, Assembler::REX_WB);
2311 dstenc -= 8;
2312 }
2313 emit_opcode(cbuf, 0xB8 | dstenc);
2314 // This next line should be generated from ADLC
2315 if ($src->constant_reloc() != relocInfo::none) {
2316 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2317 } else {
2318 emit_d64(cbuf, $src$$constant);
2319 }
2320 %}
2321
2322 enc_class Con32(immI src)
2323 %{
2324 // Output immediate
2325 $$$emit32$src$$constant;
2326 %}
2327
2328 enc_class Con32F_as_bits(immF src)
2329 %{
2330 // Output Float immediate bits
2331 jfloat jf = $src$$constant;
2332 jint jf_as_bits = jint_cast(jf);
2333 emit_d32(cbuf, jf_as_bits);
2334 %}
2335
2336 enc_class Con16(immI src)
2337 %{
2338 // Output immediate
2339 $$$emit16$src$$constant;
2340 %}
2341
2342 // How is this different from Con32??? XXX
2343 enc_class Con_d32(immI src)
2344 %{
2345 emit_d32(cbuf,$src$$constant);
2346 %}
2347
2348 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2349 // Output immediate memory reference
2350 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2351 emit_d32(cbuf, 0x00);
2352 %}
2353
2354 enc_class lock_prefix()
2355 %{
2356 emit_opcode(cbuf, 0xF0); // lock
2357 %}
2358
2359 enc_class REX_mem(memory mem)
2360 %{
2361 if ($mem$$base >= 8) {
2362 if ($mem$$index < 8) {
2363 emit_opcode(cbuf, Assembler::REX_B);
2364 } else {
2365 emit_opcode(cbuf, Assembler::REX_XB);
2366 }
2367 } else {
2368 if ($mem$$index >= 8) {
2369 emit_opcode(cbuf, Assembler::REX_X);
2370 }
2371 }
2372 %}
2373
2374 enc_class REX_mem_wide(memory mem)
2375 %{
2376 if ($mem$$base >= 8) {
2377 if ($mem$$index < 8) {
2378 emit_opcode(cbuf, Assembler::REX_WB);
2379 } else {
2380 emit_opcode(cbuf, Assembler::REX_WXB);
2381 }
2382 } else {
2383 if ($mem$$index < 8) {
2384 emit_opcode(cbuf, Assembler::REX_W);
2385 } else {
2386 emit_opcode(cbuf, Assembler::REX_WX);
2387 }
2388 }
2389 %}
2390
2391 // for byte regs
2392 enc_class REX_breg(rRegI reg)
2393 %{
2394 if ($reg$$reg >= 4) {
2395 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2396 }
2397 %}
2398
2399 // for byte regs
2400 enc_class REX_reg_breg(rRegI dst, rRegI src)
2401 %{
2402 if ($dst$$reg < 8) {
2403 if ($src$$reg >= 4) {
2404 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2405 }
2406 } else {
2407 if ($src$$reg < 8) {
2408 emit_opcode(cbuf, Assembler::REX_R);
2409 } else {
2410 emit_opcode(cbuf, Assembler::REX_RB);
2411 }
2412 }
2413 %}
2414
2415 // for byte regs
2416 enc_class REX_breg_mem(rRegI reg, memory mem)
2417 %{
2418 if ($reg$$reg < 8) {
2419 if ($mem$$base < 8) {
2420 if ($mem$$index >= 8) {
2421 emit_opcode(cbuf, Assembler::REX_X);
2422 } else if ($reg$$reg >= 4) {
2423 emit_opcode(cbuf, Assembler::REX);
2424 }
2425 } else {
2426 if ($mem$$index < 8) {
2427 emit_opcode(cbuf, Assembler::REX_B);
2428 } else {
2429 emit_opcode(cbuf, Assembler::REX_XB);
2430 }
2431 }
2432 } else {
2433 if ($mem$$base < 8) {
2434 if ($mem$$index < 8) {
2435 emit_opcode(cbuf, Assembler::REX_R);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_RX);
2438 }
2439 } else {
2440 if ($mem$$index < 8) {
2441 emit_opcode(cbuf, Assembler::REX_RB);
2442 } else {
2443 emit_opcode(cbuf, Assembler::REX_RXB);
2444 }
2445 }
2446 }
2447 %}
2448
2449 enc_class REX_reg(rRegI reg)
2450 %{
2451 if ($reg$$reg >= 8) {
2452 emit_opcode(cbuf, Assembler::REX_B);
2453 }
2454 %}
2455
2456 enc_class REX_reg_wide(rRegI reg)
2457 %{
2458 if ($reg$$reg < 8) {
2459 emit_opcode(cbuf, Assembler::REX_W);
2460 } else {
2461 emit_opcode(cbuf, Assembler::REX_WB);
2462 }
2463 %}
2464
2465 enc_class REX_reg_reg(rRegI dst, rRegI src)
2466 %{
2467 if ($dst$$reg < 8) {
2468 if ($src$$reg >= 8) {
2469 emit_opcode(cbuf, Assembler::REX_B);
2470 }
2471 } else {
2472 if ($src$$reg < 8) {
2473 emit_opcode(cbuf, Assembler::REX_R);
2474 } else {
2475 emit_opcode(cbuf, Assembler::REX_RB);
2476 }
2477 }
2478 %}
2479
2480 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2481 %{
2482 if ($dst$$reg < 8) {
2483 if ($src$$reg < 8) {
2484 emit_opcode(cbuf, Assembler::REX_W);
2485 } else {
2486 emit_opcode(cbuf, Assembler::REX_WB);
2487 }
2488 } else {
2489 if ($src$$reg < 8) {
2490 emit_opcode(cbuf, Assembler::REX_WR);
2491 } else {
2492 emit_opcode(cbuf, Assembler::REX_WRB);
2493 }
2494 }
2495 %}
2496
2497 enc_class REX_reg_mem(rRegI reg, memory mem)
2498 %{
2499 if ($reg$$reg < 8) {
2500 if ($mem$$base < 8) {
2501 if ($mem$$index >= 8) {
2502 emit_opcode(cbuf, Assembler::REX_X);
2503 }
2504 } else {
2505 if ($mem$$index < 8) {
2506 emit_opcode(cbuf, Assembler::REX_B);
2507 } else {
2508 emit_opcode(cbuf, Assembler::REX_XB);
2509 }
2510 }
2511 } else {
2512 if ($mem$$base < 8) {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_R);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_RX);
2517 }
2518 } else {
2519 if ($mem$$index < 8) {
2520 emit_opcode(cbuf, Assembler::REX_RB);
2521 } else {
2522 emit_opcode(cbuf, Assembler::REX_RXB);
2523 }
2524 }
2525 }
2526 %}
2527
2528 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2529 %{
2530 if ($reg$$reg < 8) {
2531 if ($mem$$base < 8) {
2532 if ($mem$$index < 8) {
2533 emit_opcode(cbuf, Assembler::REX_W);
2534 } else {
2535 emit_opcode(cbuf, Assembler::REX_WX);
2536 }
2537 } else {
2538 if ($mem$$index < 8) {
2539 emit_opcode(cbuf, Assembler::REX_WB);
2540 } else {
2541 emit_opcode(cbuf, Assembler::REX_WXB);
2542 }
2543 }
2544 } else {
2545 if ($mem$$base < 8) {
2546 if ($mem$$index < 8) {
2547 emit_opcode(cbuf, Assembler::REX_WR);
2548 } else {
2549 emit_opcode(cbuf, Assembler::REX_WRX);
2550 }
2551 } else {
2552 if ($mem$$index < 8) {
2553 emit_opcode(cbuf, Assembler::REX_WRB);
2554 } else {
2555 emit_opcode(cbuf, Assembler::REX_WRXB);
2556 }
2557 }
2558 }
2559 %}
2560
2561 enc_class reg_mem(rRegI ereg, memory mem)
2562 %{
2563 // High registers handle in encode_RegMem
2564 int reg = $ereg$$reg;
2565 int base = $mem$$base;
2566 int index = $mem$$index;
2567 int scale = $mem$$scale;
2568 int disp = $mem$$disp;
2569 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2570
2571 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2572 %}
2573
2574 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2575 %{
2576 int rm_byte_opcode = $rm_opcode$$constant;
2577
2578 // High registers handle in encode_RegMem
2579 int base = $mem$$base;
2580 int index = $mem$$index;
2581 int scale = $mem$$scale;
2582 int displace = $mem$$disp;
2583
2584 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2585 // working with static
2586 // globals
2587 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2588 disp_reloc);
2589 %}
2590
2591 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2592 %{
2593 int reg_encoding = $dst$$reg;
2594 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2595 int index = 0x04; // 0x04 indicates no index
2596 int scale = 0x00; // 0x00 indicates no scale
2597 int displace = $src1$$constant; // 0x00 indicates no displacement
2598 relocInfo::relocType disp_reloc = relocInfo::none;
2599 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2600 disp_reloc);
2601 %}
2602
2603 enc_class neg_reg(rRegI dst)
2604 %{
2605 int dstenc = $dst$$reg;
2606 if (dstenc >= 8) {
2607 emit_opcode(cbuf, Assembler::REX_B);
2608 dstenc -= 8;
2609 }
2610 // NEG $dst
2611 emit_opcode(cbuf, 0xF7);
2612 emit_rm(cbuf, 0x3, 0x03, dstenc);
2613 %}
2614
2615 enc_class neg_reg_wide(rRegI dst)
2616 %{
2617 int dstenc = $dst$$reg;
2618 if (dstenc < 8) {
2619 emit_opcode(cbuf, Assembler::REX_W);
2620 } else {
2621 emit_opcode(cbuf, Assembler::REX_WB);
2622 dstenc -= 8;
2623 }
2624 // NEG $dst
2625 emit_opcode(cbuf, 0xF7);
2626 emit_rm(cbuf, 0x3, 0x03, dstenc);
2627 %}
2628
2629 enc_class setLT_reg(rRegI dst)
2630 %{
2631 int dstenc = $dst$$reg;
2632 if (dstenc >= 8) {
2633 emit_opcode(cbuf, Assembler::REX_B);
2634 dstenc -= 8;
2635 } else if (dstenc >= 4) {
2636 emit_opcode(cbuf, Assembler::REX);
2637 }
2638 // SETLT $dst
2639 emit_opcode(cbuf, 0x0F);
2640 emit_opcode(cbuf, 0x9C);
2641 emit_rm(cbuf, 0x3, 0x0, dstenc);
2642 %}
2643
2644 enc_class setNZ_reg(rRegI dst)
2645 %{
2646 int dstenc = $dst$$reg;
2647 if (dstenc >= 8) {
2648 emit_opcode(cbuf, Assembler::REX_B);
2649 dstenc -= 8;
2650 } else if (dstenc >= 4) {
2651 emit_opcode(cbuf, Assembler::REX);
2652 }
2653 // SETNZ $dst
2654 emit_opcode(cbuf, 0x0F);
2655 emit_opcode(cbuf, 0x95);
2656 emit_rm(cbuf, 0x3, 0x0, dstenc);
2657 %}
2658
2659
2660 // Compare the lonogs and set -1, 0, or 1 into dst
2661 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2662 %{
2663 int src1enc = $src1$$reg;
2664 int src2enc = $src2$$reg;
2665 int dstenc = $dst$$reg;
2666
2667 // cmpq $src1, $src2
2668 if (src1enc < 8) {
2669 if (src2enc < 8) {
2670 emit_opcode(cbuf, Assembler::REX_W);
2671 } else {
2672 emit_opcode(cbuf, Assembler::REX_WB);
2673 }
2674 } else {
2675 if (src2enc < 8) {
2676 emit_opcode(cbuf, Assembler::REX_WR);
2677 } else {
2678 emit_opcode(cbuf, Assembler::REX_WRB);
2679 }
2680 }
2681 emit_opcode(cbuf, 0x3B);
2682 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2683
2684 // movl $dst, -1
2685 if (dstenc >= 8) {
2686 emit_opcode(cbuf, Assembler::REX_B);
2687 }
2688 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2689 emit_d32(cbuf, -1);
2690
2691 // jl,s done
2692 emit_opcode(cbuf, 0x7C);
2693 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2694
2695 // setne $dst
2696 if (dstenc >= 4) {
2697 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2698 }
2699 emit_opcode(cbuf, 0x0F);
2700 emit_opcode(cbuf, 0x95);
2701 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2702
2703 // movzbl $dst, $dst
2704 if (dstenc >= 4) {
2705 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2706 }
2707 emit_opcode(cbuf, 0x0F);
2708 emit_opcode(cbuf, 0xB6);
2709 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2710 %}
2711
2712 enc_class Push_ResultXD(regD dst) %{
2713 MacroAssembler _masm(&cbuf);
2714 __ fstp_d(Address(rsp, 0));
2715 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2716 __ addptr(rsp, 8);
2717 %}
2718
2719 enc_class Push_SrcXD(regD src) %{
2720 MacroAssembler _masm(&cbuf);
2721 __ subptr(rsp, 8);
2722 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2723 __ fld_d(Address(rsp, 0));
2724 %}
2725
2726
2727 enc_class enc_rethrow()
2728 %{
2729 cbuf.set_insts_mark();
2730 emit_opcode(cbuf, 0xE9); // jmp entry
2731 emit_d32_reloc(cbuf,
2732 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2733 runtime_call_Relocation::spec(),
2734 RELOC_DISP32);
2735 %}
2736
2737 %}
2738
2739
2740
2741 //----------FRAME--------------------------------------------------------------
2742 // Definition of frame structure and management information.
2743 //
2744 // S T A C K L A Y O U T Allocators stack-slot number
2745 // | (to get allocators register number
2746 // G Owned by | | v add OptoReg::stack0())
2747 // r CALLER | |
2748 // o | +--------+ pad to even-align allocators stack-slot
2749 // w V | pad0 | numbers; owned by CALLER
2750 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2751 // h ^ | in | 5
2752 // | | args | 4 Holes in incoming args owned by SELF
2753 // | | | | 3
2754 // | | +--------+
2755 // V | | old out| Empty on Intel, window on Sparc
2756 // | old |preserve| Must be even aligned.
2757 // | SP-+--------+----> Matcher::_old_SP, even aligned
2758 // | | in | 3 area for Intel ret address
2759 // Owned by |preserve| Empty on Sparc.
2760 // SELF +--------+
2761 // | | pad2 | 2 pad to align old SP
2762 // | +--------+ 1
2763 // | | locks | 0
2764 // | +--------+----> OptoReg::stack0(), even aligned
2765 // | | pad1 | 11 pad to align new SP
2766 // | +--------+
2767 // | | | 10
2768 // | | spills | 9 spills
2769 // V | | 8 (pad0 slot for callee)
2770 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2771 // ^ | out | 7
2772 // | | args | 6 Holes in outgoing args owned by CALLEE
2773 // Owned by +--------+
2774 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2775 // | new |preserve| Must be even-aligned.
2776 // | SP-+--------+----> Matcher::_new_SP, even aligned
2777 // | | |
2778 //
2779 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2780 // known from SELF's arguments and the Java calling convention.
2781 // Region 6-7 is determined per call site.
2782 // Note 2: If the calling convention leaves holes in the incoming argument
2783 // area, those holes are owned by SELF. Holes in the outgoing area
2784 // are owned by the CALLEE. Holes should not be nessecary in the
2785 // incoming area, as the Java calling convention is completely under
2786 // the control of the AD file. Doubles can be sorted and packed to
2787 // avoid holes. Holes in the outgoing arguments may be nessecary for
2788 // varargs C calling conventions.
2789 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2790 // even aligned with pad0 as needed.
2791 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2792 // region 6-11 is even aligned; it may be padded out more so that
2793 // the region from SP to FP meets the minimum stack alignment.
2794 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2795 // alignment. Region 11, pad1, may be dynamically extended so that
2796 // SP meets the minimum alignment.
2797
2798 frame
2799 %{
2800 // What direction does stack grow in (assumed to be same for C & Java)
2801 stack_direction(TOWARDS_LOW);
2802
2803 // These three registers define part of the calling convention
2804 // between compiled code and the interpreter.
2805 inline_cache_reg(RAX); // Inline Cache Register
2806 interpreter_method_oop_reg(RBX); // Method Oop Register when
2807 // calling interpreter
2808
2809 // Optional: name the operand used by cisc-spilling to access
2810 // [stack_pointer + offset]
2811 cisc_spilling_operand_name(indOffset32);
2812
2813 // Number of stack slots consumed by locking an object
2814 sync_stack_slots(2);
2815
2816 // Compiled code's Frame Pointer
2817 frame_pointer(RSP);
2818
2819 // Interpreter stores its frame pointer in a register which is
2820 // stored to the stack by I2CAdaptors.
2821 // I2CAdaptors convert from interpreted java to compiled java.
2822 interpreter_frame_pointer(RBP);
2823
2824 // Stack alignment requirement
2825 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2826
2827 // Number of stack slots between incoming argument block and the start of
2828 // a new frame. The PROLOG must add this many slots to the stack. The
2829 // EPILOG must remove this many slots. amd64 needs two slots for
2830 // return address.
2831 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2832
2833 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2834 // for calls to C. Supports the var-args backing area for register parms.
2835 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2836
2837 // The after-PROLOG location of the return address. Location of
2838 // return address specifies a type (REG or STACK) and a number
2839 // representing the register number (i.e. - use a register name) or
2840 // stack slot.
2841 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2842 // Otherwise, it is above the locks and verification slot and alignment word
2843 return_addr(STACK - 2 +
2844 align_up((Compile::current()->in_preserve_stack_slots() +
2845 Compile::current()->fixed_slots()),
2846 stack_alignment_in_slots()));
2847
2848 // Body of function which returns an integer array locating
2849 // arguments either in registers or in stack slots. Passed an array
2850 // of ideal registers called "sig" and a "length" count. Stack-slot
2851 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2852 // arguments for a CALLEE. Incoming stack arguments are
2853 // automatically biased by the preserve_stack_slots field above.
2854
2855 calling_convention
2856 %{
2857 // No difference between ingoing/outgoing just pass false
2858 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2859 %}
2860
2861 c_calling_convention
2862 %{
2863 // This is obviously always outgoing
2864 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2865 %}
2866
2867 // Location of compiled Java return values. Same as C for now.
2868 return_value
2869 %{
2870 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2871 "only return normal values");
2872
2873 static const int lo[Op_RegL + 1] = {
2874 0,
2875 0,
2876 RAX_num, // Op_RegN
2877 RAX_num, // Op_RegI
2878 RAX_num, // Op_RegP
2879 XMM0_num, // Op_RegF
2880 XMM0_num, // Op_RegD
2881 RAX_num // Op_RegL
2882 };
2883 static const int hi[Op_RegL + 1] = {
2884 0,
2885 0,
2886 OptoReg::Bad, // Op_RegN
2887 OptoReg::Bad, // Op_RegI
2888 RAX_H_num, // Op_RegP
2889 OptoReg::Bad, // Op_RegF
2890 XMM0b_num, // Op_RegD
2891 RAX_H_num // Op_RegL
2892 };
2893 // Excluded flags and vector registers.
2894 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2895 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2896 %}
2897 %}
2898
2899 //----------ATTRIBUTES---------------------------------------------------------
2900 //----------Operand Attributes-------------------------------------------------
2901 op_attrib op_cost(0); // Required cost attribute
2902
2903 //----------Instruction Attributes---------------------------------------------
2904 ins_attrib ins_cost(100); // Required cost attribute
2905 ins_attrib ins_size(8); // Required size attribute (in bits)
2906 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2907 // a non-matching short branch variant
2908 // of some long branch?
2909 ins_attrib ins_alignment(1); // Required alignment attribute (must
2910 // be a power of 2) specifies the
2911 // alignment that some part of the
2912 // instruction (not necessarily the
2913 // start) requires. If > 1, a
2914 // compute_padding() function must be
2915 // provided for the instruction
2916
2917 //----------OPERANDS-----------------------------------------------------------
2918 // Operand definitions must precede instruction definitions for correct parsing
2919 // in the ADLC because operands constitute user defined types which are used in
2920 // instruction definitions.
2921
2922 //----------Simple Operands----------------------------------------------------
2923 // Immediate Operands
2924 // Integer Immediate
2925 operand immI()
2926 %{
2927 match(ConI);
2928
2929 op_cost(10);
2930 format %{ %}
2931 interface(CONST_INTER);
2932 %}
2933
2934 // Constant for test vs zero
2935 operand immI0()
2936 %{
2937 predicate(n->get_int() == 0);
2938 match(ConI);
2939
2940 op_cost(0);
2941 format %{ %}
2942 interface(CONST_INTER);
2943 %}
2944
2945 // Constant for increment
2946 operand immI1()
2947 %{
2948 predicate(n->get_int() == 1);
2949 match(ConI);
2950
2951 op_cost(0);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // Constant for decrement
2957 operand immI_M1()
2958 %{
2959 predicate(n->get_int() == -1);
2960 match(ConI);
2961
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967 // Valid scale values for addressing modes
2968 operand immI2()
2969 %{
2970 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2971 match(ConI);
2972
2973 format %{ %}
2974 interface(CONST_INTER);
2975 %}
2976
2977 operand immI8()
2978 %{
2979 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2980 match(ConI);
2981
2982 op_cost(5);
2983 format %{ %}
2984 interface(CONST_INTER);
2985 %}
2986
2987 operand immU8()
2988 %{
2989 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2990 match(ConI);
2991
2992 op_cost(5);
2993 format %{ %}
2994 interface(CONST_INTER);
2995 %}
2996
2997 operand immI16()
2998 %{
2999 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3000 match(ConI);
3001
3002 op_cost(10);
3003 format %{ %}
3004 interface(CONST_INTER);
3005 %}
3006
3007 // Int Immediate non-negative
3008 operand immU31()
3009 %{
3010 predicate(n->get_int() >= 0);
3011 match(ConI);
3012
3013 op_cost(0);
3014 format %{ %}
3015 interface(CONST_INTER);
3016 %}
3017
3018 // Constant for long shifts
3019 operand immI_32()
3020 %{
3021 predicate( n->get_int() == 32 );
3022 match(ConI);
3023
3024 op_cost(0);
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 // Constant for long shifts
3030 operand immI_64()
3031 %{
3032 predicate( n->get_int() == 64 );
3033 match(ConI);
3034
3035 op_cost(0);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 // Pointer Immediate
3041 operand immP()
3042 %{
3043 match(ConP);
3044
3045 op_cost(10);
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050 // NULL Pointer Immediate
3051 operand immP0()
3052 %{
3053 predicate(n->get_ptr() == 0);
3054 match(ConP);
3055
3056 op_cost(5);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061 // Pointer Immediate
3062 operand immN() %{
3063 match(ConN);
3064
3065 op_cost(10);
3066 format %{ %}
3067 interface(CONST_INTER);
3068 %}
3069
3070 operand immNKlass() %{
3071 match(ConNKlass);
3072
3073 op_cost(10);
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3077
3078 // NULL Pointer Immediate
3079 operand immN0() %{
3080 predicate(n->get_narrowcon() == 0);
3081 match(ConN);
3082
3083 op_cost(5);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 operand immP31()
3089 %{
3090 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3091 && (n->get_ptr() >> 31) == 0);
3092 match(ConP);
3093
3094 op_cost(5);
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3098
3099
3100 // Long Immediate
3101 operand immL()
3102 %{
3103 match(ConL);
3104
3105 op_cost(20);
3106 format %{ %}
3107 interface(CONST_INTER);
3108 %}
3109
3110 // Long Immediate 8-bit
3111 operand immL8()
3112 %{
3113 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3114 match(ConL);
3115
3116 op_cost(5);
3117 format %{ %}
3118 interface(CONST_INTER);
3119 %}
3120
3121 // Long Immediate 32-bit unsigned
3122 operand immUL32()
3123 %{
3124 predicate(n->get_long() == (unsigned int) (n->get_long()));
3125 match(ConL);
3126
3127 op_cost(10);
3128 format %{ %}
3129 interface(CONST_INTER);
3130 %}
3131
3132 // Long Immediate 32-bit signed
3133 operand immL32()
3134 %{
3135 predicate(n->get_long() == (int) (n->get_long()));
3136 match(ConL);
3137
3138 op_cost(15);
3139 format %{ %}
3140 interface(CONST_INTER);
3141 %}
3142
3143 // Long Immediate zero
3144 operand immL0()
3145 %{
3146 predicate(n->get_long() == 0L);
3147 match(ConL);
3148
3149 op_cost(10);
3150 format %{ %}
3151 interface(CONST_INTER);
3152 %}
3153
3154 // Constant for increment
3155 operand immL1()
3156 %{
3157 predicate(n->get_long() == 1);
3158 match(ConL);
3159
3160 format %{ %}
3161 interface(CONST_INTER);
3162 %}
3163
3164 // Constant for decrement
3165 operand immL_M1()
3166 %{
3167 predicate(n->get_long() == -1);
3168 match(ConL);
3169
3170 format %{ %}
3171 interface(CONST_INTER);
3172 %}
3173
3174 // Long Immediate: the value 10
3175 operand immL10()
3176 %{
3177 predicate(n->get_long() == 10);
3178 match(ConL);
3179
3180 format %{ %}
3181 interface(CONST_INTER);
3182 %}
3183
3184 // Long immediate from 0 to 127.
3185 // Used for a shorter form of long mul by 10.
3186 operand immL_127()
3187 %{
3188 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3189 match(ConL);
3190
3191 op_cost(10);
3192 format %{ %}
3193 interface(CONST_INTER);
3194 %}
3195
3196 // Long Immediate: low 32-bit mask
3197 operand immL_32bits()
3198 %{
3199 predicate(n->get_long() == 0xFFFFFFFFL);
3200 match(ConL);
3201 op_cost(20);
3202
3203 format %{ %}
3204 interface(CONST_INTER);
3205 %}
3206
3207 // Float Immediate zero
3208 operand immF0()
3209 %{
3210 predicate(jint_cast(n->getf()) == 0);
3211 match(ConF);
3212
3213 op_cost(5);
3214 format %{ %}
3215 interface(CONST_INTER);
3216 %}
3217
3218 // Float Immediate
3219 operand immF()
3220 %{
3221 match(ConF);
3222
3223 op_cost(15);
3224 format %{ %}
3225 interface(CONST_INTER);
3226 %}
3227
3228 // Double Immediate zero
3229 operand immD0()
3230 %{
3231 predicate(jlong_cast(n->getd()) == 0);
3232 match(ConD);
3233
3234 op_cost(5);
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 // Double Immediate
3240 operand immD()
3241 %{
3242 match(ConD);
3243
3244 op_cost(15);
3245 format %{ %}
3246 interface(CONST_INTER);
3247 %}
3248
3249 // Immediates for special shifts (sign extend)
3250
3251 // Constants for increment
3252 operand immI_16()
3253 %{
3254 predicate(n->get_int() == 16);
3255 match(ConI);
3256
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 operand immI_24()
3262 %{
3263 predicate(n->get_int() == 24);
3264 match(ConI);
3265
3266 format %{ %}
3267 interface(CONST_INTER);
3268 %}
3269
3270 // Constant for byte-wide masking
3271 operand immI_255()
3272 %{
3273 predicate(n->get_int() == 255);
3274 match(ConI);
3275
3276 format %{ %}
3277 interface(CONST_INTER);
3278 %}
3279
3280 // Constant for short-wide masking
3281 operand immI_65535()
3282 %{
3283 predicate(n->get_int() == 65535);
3284 match(ConI);
3285
3286 format %{ %}
3287 interface(CONST_INTER);
3288 %}
3289
3290 // Constant for byte-wide masking
3291 operand immL_255()
3292 %{
3293 predicate(n->get_long() == 255);
3294 match(ConL);
3295
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Constant for short-wide masking
3301 operand immL_65535()
3302 %{
3303 predicate(n->get_long() == 65535);
3304 match(ConL);
3305
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3309
3310 // Register Operands
3311 // Integer Register
3312 operand rRegI()
3313 %{
3314 constraint(ALLOC_IN_RC(int_reg));
3315 match(RegI);
3316
3317 match(rax_RegI);
3318 match(rbx_RegI);
3319 match(rcx_RegI);
3320 match(rdx_RegI);
3321 match(rdi_RegI);
3322
3323 format %{ %}
3324 interface(REG_INTER);
3325 %}
3326
3327 // Special Registers
3328 operand rax_RegI()
3329 %{
3330 constraint(ALLOC_IN_RC(int_rax_reg));
3331 match(RegI);
3332 match(rRegI);
3333
3334 format %{ "RAX" %}
3335 interface(REG_INTER);
3336 %}
3337
3338 // Special Registers
3339 operand rbx_RegI()
3340 %{
3341 constraint(ALLOC_IN_RC(int_rbx_reg));
3342 match(RegI);
3343 match(rRegI);
3344
3345 format %{ "RBX" %}
3346 interface(REG_INTER);
3347 %}
3348
3349 operand rcx_RegI()
3350 %{
3351 constraint(ALLOC_IN_RC(int_rcx_reg));
3352 match(RegI);
3353 match(rRegI);
3354
3355 format %{ "RCX" %}
3356 interface(REG_INTER);
3357 %}
3358
3359 operand rdx_RegI()
3360 %{
3361 constraint(ALLOC_IN_RC(int_rdx_reg));
3362 match(RegI);
3363 match(rRegI);
3364
3365 format %{ "RDX" %}
3366 interface(REG_INTER);
3367 %}
3368
3369 operand rdi_RegI()
3370 %{
3371 constraint(ALLOC_IN_RC(int_rdi_reg));
3372 match(RegI);
3373 match(rRegI);
3374
3375 format %{ "RDI" %}
3376 interface(REG_INTER);
3377 %}
3378
3379 operand no_rcx_RegI()
3380 %{
3381 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3382 match(RegI);
3383 match(rax_RegI);
3384 match(rbx_RegI);
3385 match(rdx_RegI);
3386 match(rdi_RegI);
3387
3388 format %{ %}
3389 interface(REG_INTER);
3390 %}
3391
3392 operand no_rax_rdx_RegI()
3393 %{
3394 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3395 match(RegI);
3396 match(rbx_RegI);
3397 match(rcx_RegI);
3398 match(rdi_RegI);
3399
3400 format %{ %}
3401 interface(REG_INTER);
3402 %}
3403
3404 // Pointer Register
3405 operand any_RegP()
3406 %{
3407 constraint(ALLOC_IN_RC(any_reg));
3408 match(RegP);
3409 match(rax_RegP);
3410 match(rbx_RegP);
3411 match(rdi_RegP);
3412 match(rsi_RegP);
3413 match(rbp_RegP);
3414 match(r15_RegP);
3415 match(rRegP);
3416
3417 format %{ %}
3418 interface(REG_INTER);
3419 %}
3420
3421 operand rRegP()
3422 %{
3423 constraint(ALLOC_IN_RC(ptr_reg));
3424 match(RegP);
3425 match(rax_RegP);
3426 match(rbx_RegP);
3427 match(rdi_RegP);
3428 match(rsi_RegP);
3429 match(rbp_RegP); // See Q&A below about
3430 match(r15_RegP); // r15_RegP and rbp_RegP.
3431
3432 format %{ %}
3433 interface(REG_INTER);
3434 %}
3435
3436 operand rRegN() %{
3437 constraint(ALLOC_IN_RC(int_reg));
3438 match(RegN);
3439
3440 format %{ %}
3441 interface(REG_INTER);
3442 %}
3443
3444 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3445 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3446 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3447 // The output of an instruction is controlled by the allocator, which respects
3448 // register class masks, not match rules. Unless an instruction mentions
3449 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3450 // by the allocator as an input.
3451 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3452 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3453 // result, RBP is not included in the output of the instruction either.
3454
3455 operand no_rax_RegP()
3456 %{
3457 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3458 match(RegP);
3459 match(rbx_RegP);
3460 match(rsi_RegP);
3461 match(rdi_RegP);
3462
3463 format %{ %}
3464 interface(REG_INTER);
3465 %}
3466
3467 // This operand is not allowed to use RBP even if
3468 // RBP is not used to hold the frame pointer.
3469 operand no_rbp_RegP()
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3472 match(RegP);
3473 match(rbx_RegP);
3474 match(rsi_RegP);
3475 match(rdi_RegP);
3476
3477 format %{ %}
3478 interface(REG_INTER);
3479 %}
3480
3481 operand no_rax_rbx_RegP()
3482 %{
3483 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3484 match(RegP);
3485 match(rsi_RegP);
3486 match(rdi_RegP);
3487
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 // Special Registers
3493 // Return a pointer value
3494 operand rax_RegP()
3495 %{
3496 constraint(ALLOC_IN_RC(ptr_rax_reg));
3497 match(RegP);
3498 match(rRegP);
3499
3500 format %{ %}
3501 interface(REG_INTER);
3502 %}
3503
3504 // Special Registers
3505 // Return a compressed pointer value
3506 operand rax_RegN()
3507 %{
3508 constraint(ALLOC_IN_RC(int_rax_reg));
3509 match(RegN);
3510 match(rRegN);
3511
3512 format %{ %}
3513 interface(REG_INTER);
3514 %}
3515
3516 // Used in AtomicAdd
3517 operand rbx_RegP()
3518 %{
3519 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3520 match(RegP);
3521 match(rRegP);
3522
3523 format %{ %}
3524 interface(REG_INTER);
3525 %}
3526
3527 operand rsi_RegP()
3528 %{
3529 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3530 match(RegP);
3531 match(rRegP);
3532
3533 format %{ %}
3534 interface(REG_INTER);
3535 %}
3536
3537 // Used in rep stosq
3538 operand rdi_RegP()
3539 %{
3540 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3541 match(RegP);
3542 match(rRegP);
3543
3544 format %{ %}
3545 interface(REG_INTER);
3546 %}
3547
3548 operand r15_RegP()
3549 %{
3550 constraint(ALLOC_IN_RC(ptr_r15_reg));
3551 match(RegP);
3552 match(rRegP);
3553
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3557
3558 operand rRegL()
3559 %{
3560 constraint(ALLOC_IN_RC(long_reg));
3561 match(RegL);
3562 match(rax_RegL);
3563 match(rdx_RegL);
3564
3565 format %{ %}
3566 interface(REG_INTER);
3567 %}
3568
3569 // Special Registers
3570 operand no_rax_rdx_RegL()
3571 %{
3572 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3573 match(RegL);
3574 match(rRegL);
3575
3576 format %{ %}
3577 interface(REG_INTER);
3578 %}
3579
3580 operand no_rax_RegL()
3581 %{
3582 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3583 match(RegL);
3584 match(rRegL);
3585 match(rdx_RegL);
3586
3587 format %{ %}
3588 interface(REG_INTER);
3589 %}
3590
3591 operand no_rcx_RegL()
3592 %{
3593 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3594 match(RegL);
3595 match(rRegL);
3596
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 operand rax_RegL()
3602 %{
3603 constraint(ALLOC_IN_RC(long_rax_reg));
3604 match(RegL);
3605 match(rRegL);
3606
3607 format %{ "RAX" %}
3608 interface(REG_INTER);
3609 %}
3610
3611 operand rcx_RegL()
3612 %{
3613 constraint(ALLOC_IN_RC(long_rcx_reg));
3614 match(RegL);
3615 match(rRegL);
3616
3617 format %{ %}
3618 interface(REG_INTER);
3619 %}
3620
3621 operand rdx_RegL()
3622 %{
3623 constraint(ALLOC_IN_RC(long_rdx_reg));
3624 match(RegL);
3625 match(rRegL);
3626
3627 format %{ %}
3628 interface(REG_INTER);
3629 %}
3630
3631 // Flags register, used as output of compare instructions
3632 operand rFlagsReg()
3633 %{
3634 constraint(ALLOC_IN_RC(int_flags));
3635 match(RegFlags);
3636
3637 format %{ "RFLAGS" %}
3638 interface(REG_INTER);
3639 %}
3640
3641 // Flags register, used as output of FLOATING POINT compare instructions
3642 operand rFlagsRegU()
3643 %{
3644 constraint(ALLOC_IN_RC(int_flags));
3645 match(RegFlags);
3646
3647 format %{ "RFLAGS_U" %}
3648 interface(REG_INTER);
3649 %}
3650
3651 operand rFlagsRegUCF() %{
3652 constraint(ALLOC_IN_RC(int_flags));
3653 match(RegFlags);
3654 predicate(false);
3655
3656 format %{ "RFLAGS_U_CF" %}
3657 interface(REG_INTER);
3658 %}
3659
3660 // Float register operands
3661 operand regF() %{
3662 constraint(ALLOC_IN_RC(float_reg));
3663 match(RegF);
3664
3665 format %{ %}
3666 interface(REG_INTER);
3667 %}
3668
3669 // Float register operands
3670 operand vlRegF() %{
3671 constraint(ALLOC_IN_RC(float_reg_vl));
3672 match(RegF);
3673
3674 format %{ %}
3675 interface(REG_INTER);
3676 %}
3677
3678 // Double register operands
3679 operand regD() %{
3680 constraint(ALLOC_IN_RC(double_reg));
3681 match(RegD);
3682
3683 format %{ %}
3684 interface(REG_INTER);
3685 %}
3686
3687 // Double register operands
3688 operand vlRegD() %{
3689 constraint(ALLOC_IN_RC(double_reg_vl));
3690 match(RegD);
3691
3692 format %{ %}
3693 interface(REG_INTER);
3694 %}
3695
3696 // Vectors
3697 operand vecS() %{
3698 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3699 match(VecS);
3700
3701 format %{ %}
3702 interface(REG_INTER);
3703 %}
3704
3705 // Vectors
3706 operand legVecS() %{
3707 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3708 match(VecS);
3709
3710 format %{ %}
3711 interface(REG_INTER);
3712 %}
3713
3714 operand vecD() %{
3715 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3716 match(VecD);
3717
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3721
3722 operand legVecD() %{
3723 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3724 match(VecD);
3725
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3729
3730 operand vecX() %{
3731 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3732 match(VecX);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand legVecX() %{
3739 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3740 match(VecX);
3741
3742 format %{ %}
3743 interface(REG_INTER);
3744 %}
3745
3746 operand vecY() %{
3747 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3748 match(VecY);
3749
3750 format %{ %}
3751 interface(REG_INTER);
3752 %}
3753
3754 operand legVecY() %{
3755 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3756 match(VecY);
3757
3758 format %{ %}
3759 interface(REG_INTER);
3760 %}
3761
3762 //----------Memory Operands----------------------------------------------------
3763 // Direct Memory Operand
3764 // operand direct(immP addr)
3765 // %{
3766 // match(addr);
3767
3768 // format %{ "[$addr]" %}
3769 // interface(MEMORY_INTER) %{
3770 // base(0xFFFFFFFF);
3771 // index(0x4);
3772 // scale(0x0);
3773 // disp($addr);
3774 // %}
3775 // %}
3776
3777 // Indirect Memory Operand
3778 operand indirect(any_RegP reg)
3779 %{
3780 constraint(ALLOC_IN_RC(ptr_reg));
3781 match(reg);
3782
3783 format %{ "[$reg]" %}
3784 interface(MEMORY_INTER) %{
3785 base($reg);
3786 index(0x4);
3787 scale(0x0);
3788 disp(0x0);
3789 %}
3790 %}
3791
3792 // Indirect Memory Plus Short Offset Operand
3793 operand indOffset8(any_RegP reg, immL8 off)
3794 %{
3795 constraint(ALLOC_IN_RC(ptr_reg));
3796 match(AddP reg off);
3797
3798 format %{ "[$reg + $off (8-bit)]" %}
3799 interface(MEMORY_INTER) %{
3800 base($reg);
3801 index(0x4);
3802 scale(0x0);
3803 disp($off);
3804 %}
3805 %}
3806
3807 // Indirect Memory Plus Long Offset Operand
3808 operand indOffset32(any_RegP reg, immL32 off)
3809 %{
3810 constraint(ALLOC_IN_RC(ptr_reg));
3811 match(AddP reg off);
3812
3813 format %{ "[$reg + $off (32-bit)]" %}
3814 interface(MEMORY_INTER) %{
3815 base($reg);
3816 index(0x4);
3817 scale(0x0);
3818 disp($off);
3819 %}
3820 %}
3821
3822 // Indirect Memory Plus Index Register Plus Offset Operand
3823 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3824 %{
3825 constraint(ALLOC_IN_RC(ptr_reg));
3826 match(AddP (AddP reg lreg) off);
3827
3828 op_cost(10);
3829 format %{"[$reg + $off + $lreg]" %}
3830 interface(MEMORY_INTER) %{
3831 base($reg);
3832 index($lreg);
3833 scale(0x0);
3834 disp($off);
3835 %}
3836 %}
3837
3838 // Indirect Memory Plus Index Register Plus Offset Operand
3839 operand indIndex(any_RegP reg, rRegL lreg)
3840 %{
3841 constraint(ALLOC_IN_RC(ptr_reg));
3842 match(AddP reg lreg);
3843
3844 op_cost(10);
3845 format %{"[$reg + $lreg]" %}
3846 interface(MEMORY_INTER) %{
3847 base($reg);
3848 index($lreg);
3849 scale(0x0);
3850 disp(0x0);
3851 %}
3852 %}
3853
3854 // Indirect Memory Times Scale Plus Index Register
3855 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3856 %{
3857 constraint(ALLOC_IN_RC(ptr_reg));
3858 match(AddP reg (LShiftL lreg scale));
3859
3860 op_cost(10);
3861 format %{"[$reg + $lreg << $scale]" %}
3862 interface(MEMORY_INTER) %{
3863 base($reg);
3864 index($lreg);
3865 scale($scale);
3866 disp(0x0);
3867 %}
3868 %}
3869
3870 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3871 %{
3872 constraint(ALLOC_IN_RC(ptr_reg));
3873 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3874 match(AddP reg (LShiftL (ConvI2L idx) scale));
3875
3876 op_cost(10);
3877 format %{"[$reg + pos $idx << $scale]" %}
3878 interface(MEMORY_INTER) %{
3879 base($reg);
3880 index($idx);
3881 scale($scale);
3882 disp(0x0);
3883 %}
3884 %}
3885
3886 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3887 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3888 %{
3889 constraint(ALLOC_IN_RC(ptr_reg));
3890 match(AddP (AddP reg (LShiftL lreg scale)) off);
3891
3892 op_cost(10);
3893 format %{"[$reg + $off + $lreg << $scale]" %}
3894 interface(MEMORY_INTER) %{
3895 base($reg);
3896 index($lreg);
3897 scale($scale);
3898 disp($off);
3899 %}
3900 %}
3901
3902 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3903 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3904 %{
3905 constraint(ALLOC_IN_RC(ptr_reg));
3906 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3907 match(AddP (AddP reg (ConvI2L idx)) off);
3908
3909 op_cost(10);
3910 format %{"[$reg + $off + $idx]" %}
3911 interface(MEMORY_INTER) %{
3912 base($reg);
3913 index($idx);
3914 scale(0x0);
3915 disp($off);
3916 %}
3917 %}
3918
3919 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3920 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3921 %{
3922 constraint(ALLOC_IN_RC(ptr_reg));
3923 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3924 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3925
3926 op_cost(10);
3927 format %{"[$reg + $off + $idx << $scale]" %}
3928 interface(MEMORY_INTER) %{
3929 base($reg);
3930 index($idx);
3931 scale($scale);
3932 disp($off);
3933 %}
3934 %}
3935
3936 // Indirect Narrow Oop Plus Offset Operand
3937 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3938 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3939 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3940 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3941 constraint(ALLOC_IN_RC(ptr_reg));
3942 match(AddP (DecodeN reg) off);
3943
3944 op_cost(10);
3945 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3946 interface(MEMORY_INTER) %{
3947 base(0xc); // R12
3948 index($reg);
3949 scale(0x3);
3950 disp($off);
3951 %}
3952 %}
3953
3954 // Indirect Memory Operand
3955 operand indirectNarrow(rRegN reg)
3956 %{
3957 predicate(Universe::narrow_oop_shift() == 0);
3958 constraint(ALLOC_IN_RC(ptr_reg));
3959 match(DecodeN reg);
3960
3961 format %{ "[$reg]" %}
3962 interface(MEMORY_INTER) %{
3963 base($reg);
3964 index(0x4);
3965 scale(0x0);
3966 disp(0x0);
3967 %}
3968 %}
3969
3970 // Indirect Memory Plus Short Offset Operand
3971 operand indOffset8Narrow(rRegN reg, immL8 off)
3972 %{
3973 predicate(Universe::narrow_oop_shift() == 0);
3974 constraint(ALLOC_IN_RC(ptr_reg));
3975 match(AddP (DecodeN reg) off);
3976
3977 format %{ "[$reg + $off (8-bit)]" %}
3978 interface(MEMORY_INTER) %{
3979 base($reg);
3980 index(0x4);
3981 scale(0x0);
3982 disp($off);
3983 %}
3984 %}
3985
3986 // Indirect Memory Plus Long Offset Operand
3987 operand indOffset32Narrow(rRegN reg, immL32 off)
3988 %{
3989 predicate(Universe::narrow_oop_shift() == 0);
3990 constraint(ALLOC_IN_RC(ptr_reg));
3991 match(AddP (DecodeN reg) off);
3992
3993 format %{ "[$reg + $off (32-bit)]" %}
3994 interface(MEMORY_INTER) %{
3995 base($reg);
3996 index(0x4);
3997 scale(0x0);
3998 disp($off);
3999 %}
4000 %}
4001
4002 // Indirect Memory Plus Index Register Plus Offset Operand
4003 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4004 %{
4005 predicate(Universe::narrow_oop_shift() == 0);
4006 constraint(ALLOC_IN_RC(ptr_reg));
4007 match(AddP (AddP (DecodeN reg) lreg) off);
4008
4009 op_cost(10);
4010 format %{"[$reg + $off + $lreg]" %}
4011 interface(MEMORY_INTER) %{
4012 base($reg);
4013 index($lreg);
4014 scale(0x0);
4015 disp($off);
4016 %}
4017 %}
4018
4019 // Indirect Memory Plus Index Register Plus Offset Operand
4020 operand indIndexNarrow(rRegN reg, rRegL lreg)
4021 %{
4022 predicate(Universe::narrow_oop_shift() == 0);
4023 constraint(ALLOC_IN_RC(ptr_reg));
4024 match(AddP (DecodeN reg) lreg);
4025
4026 op_cost(10);
4027 format %{"[$reg + $lreg]" %}
4028 interface(MEMORY_INTER) %{
4029 base($reg);
4030 index($lreg);
4031 scale(0x0);
4032 disp(0x0);
4033 %}
4034 %}
4035
4036 // Indirect Memory Times Scale Plus Index Register
4037 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4038 %{
4039 predicate(Universe::narrow_oop_shift() == 0);
4040 constraint(ALLOC_IN_RC(ptr_reg));
4041 match(AddP (DecodeN reg) (LShiftL lreg scale));
4042
4043 op_cost(10);
4044 format %{"[$reg + $lreg << $scale]" %}
4045 interface(MEMORY_INTER) %{
4046 base($reg);
4047 index($lreg);
4048 scale($scale);
4049 disp(0x0);
4050 %}
4051 %}
4052
4053 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4054 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4055 %{
4056 predicate(Universe::narrow_oop_shift() == 0);
4057 constraint(ALLOC_IN_RC(ptr_reg));
4058 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4059
4060 op_cost(10);
4061 format %{"[$reg + $off + $lreg << $scale]" %}
4062 interface(MEMORY_INTER) %{
4063 base($reg);
4064 index($lreg);
4065 scale($scale);
4066 disp($off);
4067 %}
4068 %}
4069
4070 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4071 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4072 %{
4073 constraint(ALLOC_IN_RC(ptr_reg));
4074 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4075 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4076
4077 op_cost(10);
4078 format %{"[$reg + $off + $idx]" %}
4079 interface(MEMORY_INTER) %{
4080 base($reg);
4081 index($idx);
4082 scale(0x0);
4083 disp($off);
4084 %}
4085 %}
4086
4087 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4088 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4089 %{
4090 constraint(ALLOC_IN_RC(ptr_reg));
4091 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4092 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4093
4094 op_cost(10);
4095 format %{"[$reg + $off + $idx << $scale]" %}
4096 interface(MEMORY_INTER) %{
4097 base($reg);
4098 index($idx);
4099 scale($scale);
4100 disp($off);
4101 %}
4102 %}
4103
4104 //----------Special Memory Operands--------------------------------------------
4105 // Stack Slot Operand - This operand is used for loading and storing temporary
4106 // values on the stack where a match requires a value to
4107 // flow through memory.
4108 operand stackSlotP(sRegP reg)
4109 %{
4110 constraint(ALLOC_IN_RC(stack_slots));
4111 // No match rule because this operand is only generated in matching
4112
4113 format %{ "[$reg]" %}
4114 interface(MEMORY_INTER) %{
4115 base(0x4); // RSP
4116 index(0x4); // No Index
4117 scale(0x0); // No Scale
4118 disp($reg); // Stack Offset
4119 %}
4120 %}
4121
4122 operand stackSlotI(sRegI reg)
4123 %{
4124 constraint(ALLOC_IN_RC(stack_slots));
4125 // No match rule because this operand is only generated in matching
4126
4127 format %{ "[$reg]" %}
4128 interface(MEMORY_INTER) %{
4129 base(0x4); // RSP
4130 index(0x4); // No Index
4131 scale(0x0); // No Scale
4132 disp($reg); // Stack Offset
4133 %}
4134 %}
4135
4136 operand stackSlotF(sRegF reg)
4137 %{
4138 constraint(ALLOC_IN_RC(stack_slots));
4139 // No match rule because this operand is only generated in matching
4140
4141 format %{ "[$reg]" %}
4142 interface(MEMORY_INTER) %{
4143 base(0x4); // RSP
4144 index(0x4); // No Index
4145 scale(0x0); // No Scale
4146 disp($reg); // Stack Offset
4147 %}
4148 %}
4149
4150 operand stackSlotD(sRegD reg)
4151 %{
4152 constraint(ALLOC_IN_RC(stack_slots));
4153 // No match rule because this operand is only generated in matching
4154
4155 format %{ "[$reg]" %}
4156 interface(MEMORY_INTER) %{
4157 base(0x4); // RSP
4158 index(0x4); // No Index
4159 scale(0x0); // No Scale
4160 disp($reg); // Stack Offset
4161 %}
4162 %}
4163 operand stackSlotL(sRegL reg)
4164 %{
4165 constraint(ALLOC_IN_RC(stack_slots));
4166 // No match rule because this operand is only generated in matching
4167
4168 format %{ "[$reg]" %}
4169 interface(MEMORY_INTER) %{
4170 base(0x4); // RSP
4171 index(0x4); // No Index
4172 scale(0x0); // No Scale
4173 disp($reg); // Stack Offset
4174 %}
4175 %}
4176
4177 //----------Conditional Branch Operands----------------------------------------
4178 // Comparison Op - This is the operation of the comparison, and is limited to
4179 // the following set of codes:
4180 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4181 //
4182 // Other attributes of the comparison, such as unsignedness, are specified
4183 // by the comparison instruction that sets a condition code flags register.
4184 // That result is represented by a flags operand whose subtype is appropriate
4185 // to the unsignedness (etc.) of the comparison.
4186 //
4187 // Later, the instruction which matches both the Comparison Op (a Bool) and
4188 // the flags (produced by the Cmp) specifies the coding of the comparison op
4189 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4190
4191 // Comparision Code
4192 operand cmpOp()
4193 %{
4194 match(Bool);
4195
4196 format %{ "" %}
4197 interface(COND_INTER) %{
4198 equal(0x4, "e");
4199 not_equal(0x5, "ne");
4200 less(0xC, "l");
4201 greater_equal(0xD, "ge");
4202 less_equal(0xE, "le");
4203 greater(0xF, "g");
4204 overflow(0x0, "o");
4205 no_overflow(0x1, "no");
4206 %}
4207 %}
4208
4209 // Comparison Code, unsigned compare. Used by FP also, with
4210 // C2 (unordered) turned into GT or LT already. The other bits
4211 // C0 and C3 are turned into Carry & Zero flags.
4212 operand cmpOpU()
4213 %{
4214 match(Bool);
4215
4216 format %{ "" %}
4217 interface(COND_INTER) %{
4218 equal(0x4, "e");
4219 not_equal(0x5, "ne");
4220 less(0x2, "b");
4221 greater_equal(0x3, "nb");
4222 less_equal(0x6, "be");
4223 greater(0x7, "nbe");
4224 overflow(0x0, "o");
4225 no_overflow(0x1, "no");
4226 %}
4227 %}
4228
4229
4230 // Floating comparisons that don't require any fixup for the unordered case
4231 operand cmpOpUCF() %{
4232 match(Bool);
4233 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4234 n->as_Bool()->_test._test == BoolTest::ge ||
4235 n->as_Bool()->_test._test == BoolTest::le ||
4236 n->as_Bool()->_test._test == BoolTest::gt);
4237 format %{ "" %}
4238 interface(COND_INTER) %{
4239 equal(0x4, "e");
4240 not_equal(0x5, "ne");
4241 less(0x2, "b");
4242 greater_equal(0x3, "nb");
4243 less_equal(0x6, "be");
4244 greater(0x7, "nbe");
4245 overflow(0x0, "o");
4246 no_overflow(0x1, "no");
4247 %}
4248 %}
4249
4250
4251 // Floating comparisons that can be fixed up with extra conditional jumps
4252 operand cmpOpUCF2() %{
4253 match(Bool);
4254 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4255 n->as_Bool()->_test._test == BoolTest::eq);
4256 format %{ "" %}
4257 interface(COND_INTER) %{
4258 equal(0x4, "e");
4259 not_equal(0x5, "ne");
4260 less(0x2, "b");
4261 greater_equal(0x3, "nb");
4262 less_equal(0x6, "be");
4263 greater(0x7, "nbe");
4264 overflow(0x0, "o");
4265 no_overflow(0x1, "no");
4266 %}
4267 %}
4268
4269 // Operands for bound floating pointer register arguments
4270 operand rxmm0() %{
4271 constraint(ALLOC_IN_RC(xmm0_reg)); match(VecX);
4272 predicate((UseSSE > 0) && (UseAVX<= 2)); format%{%} interface(REG_INTER);
4273 %}
4274 operand rxmm1() %{
4275 constraint(ALLOC_IN_RC(xmm1_reg)); match(VecX);
4276 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4277 %}
4278 operand rxmm2() %{
4279 constraint(ALLOC_IN_RC(xmm2_reg)); match(VecX);
4280 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4281 %}
4282 operand rxmm3() %{
4283 constraint(ALLOC_IN_RC(xmm3_reg)); match(VecX);
4284 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4285 %}
4286 operand rxmm4() %{
4287 constraint(ALLOC_IN_RC(xmm4_reg)); match(VecX);
4288 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4289 %}
4290 operand rxmm5() %{
4291 constraint(ALLOC_IN_RC(xmm5_reg)); match(VecX);
4292 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4293 %}
4294 operand rxmm6() %{
4295 constraint(ALLOC_IN_RC(xmm6_reg)); match(VecX);
4296 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4297 %}
4298 operand rxmm7() %{
4299 constraint(ALLOC_IN_RC(xmm7_reg)); match(VecX);
4300 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4301 %}
4302 operand rxmm8() %{
4303 constraint(ALLOC_IN_RC(xmm8_reg)); match(VecX);
4304 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4305 %}
4306 operand rxmm9() %{
4307 constraint(ALLOC_IN_RC(xmm9_reg)); match(VecX);
4308 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4309 %}
4310 operand rxmm10() %{
4311 constraint(ALLOC_IN_RC(xmm10_reg)); match(VecX);
4312 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4313 %}
4314 operand rxmm11() %{
4315 constraint(ALLOC_IN_RC(xmm11_reg)); match(VecX);
4316 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4317 %}
4318 operand rxmm12() %{
4319 constraint(ALLOC_IN_RC(xmm12_reg)); match(VecX);
4320 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4321 %}
4322 operand rxmm13() %{
4323 constraint(ALLOC_IN_RC(xmm13_reg)); match(VecX);
4324 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4325 %}
4326 operand rxmm14() %{
4327 constraint(ALLOC_IN_RC(xmm14_reg)); match(VecX);
4328 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4329 %}
4330 operand rxmm15() %{
4331 constraint(ALLOC_IN_RC(xmm15_reg)); match(VecX);
4332 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4333 %}
4334 operand rxmm16() %{
4335 constraint(ALLOC_IN_RC(xmm16_reg)); match(VecX);
4336 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4337 %}
4338 operand rxmm17() %{
4339 constraint(ALLOC_IN_RC(xmm17_reg)); match(VecX);
4340 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4341 %}
4342 operand rxmm18() %{
4343 constraint(ALLOC_IN_RC(xmm18_reg)); match(VecX);
4344 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4345 %}
4346 operand rxmm19() %{
4347 constraint(ALLOC_IN_RC(xmm19_reg)); match(VecX);
4348 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4349 %}
4350 operand rxmm20() %{
4351 constraint(ALLOC_IN_RC(xmm20_reg)); match(VecX);
4352 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4353 %}
4354 operand rxmm21() %{
4355 constraint(ALLOC_IN_RC(xmm21_reg)); match(VecX);
4356 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4357 %}
4358 operand rxmm22() %{
4359 constraint(ALLOC_IN_RC(xmm22_reg)); match(VecX);
4360 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4361 %}
4362 operand rxmm23() %{
4363 constraint(ALLOC_IN_RC(xmm23_reg)); match(VecX);
4364 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4365 %}
4366 operand rxmm24() %{
4367 constraint(ALLOC_IN_RC(xmm24_reg)); match(VecX);
4368 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4369 %}
4370 operand rxmm25() %{
4371 constraint(ALLOC_IN_RC(xmm25_reg)); match(VecX);
4372 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4373 %}
4374 operand rxmm26() %{
4375 constraint(ALLOC_IN_RC(xmm26_reg)); match(VecX);
4376 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4377 %}
4378 operand rxmm27() %{
4379 constraint(ALLOC_IN_RC(xmm27_reg)); match(VecX);
4380 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4381 %}
4382 operand rxmm28() %{
4383 constraint(ALLOC_IN_RC(xmm28_reg)); match(VecX);
4384 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4385 %}
4386 operand rxmm29() %{
4387 constraint(ALLOC_IN_RC(xmm29_reg)); match(VecX);
4388 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4389 %}
4390 operand rxmm30() %{
4391 constraint(ALLOC_IN_RC(xmm30_reg)); match(VecX);
4392 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4393 %}
4394 operand rxmm31() %{
4395 constraint(ALLOC_IN_RC(xmm31_reg)); match(VecX);
4396 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4397 %}
4398
4399 //----------OPERAND CLASSES----------------------------------------------------
4400 // Operand Classes are groups of operands that are used as to simplify
4401 // instruction definitions by not requiring the AD writer to specify separate
4402 // instructions for every form of operand when the instruction accepts
4403 // multiple operand types with the same basic encoding and format. The classic
4404 // case of this is memory operands.
4405
4406 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4407 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4408 indCompressedOopOffset,
4409 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4410 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4411 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4412
4413 //----------PIPELINE-----------------------------------------------------------
4414 // Rules which define the behavior of the target architectures pipeline.
4415 pipeline %{
4416
4417 //----------ATTRIBUTES---------------------------------------------------------
4418 attributes %{
4419 variable_size_instructions; // Fixed size instructions
4420 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4421 instruction_unit_size = 1; // An instruction is 1 bytes long
4422 instruction_fetch_unit_size = 16; // The processor fetches one line
4423 instruction_fetch_units = 1; // of 16 bytes
4424
4425 // List of nop instructions
4426 nops( MachNop );
4427 %}
4428
4429 //----------RESOURCES----------------------------------------------------------
4430 // Resources are the functional units available to the machine
4431
4432 // Generic P2/P3 pipeline
4433 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4434 // 3 instructions decoded per cycle.
4435 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4436 // 3 ALU op, only ALU0 handles mul instructions.
4437 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4438 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4439 BR, FPU,
4440 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4441
4442 //----------PIPELINE DESCRIPTION-----------------------------------------------
4443 // Pipeline Description specifies the stages in the machine's pipeline
4444
4445 // Generic P2/P3 pipeline
4446 pipe_desc(S0, S1, S2, S3, S4, S5);
4447
4448 //----------PIPELINE CLASSES---------------------------------------------------
4449 // Pipeline Classes describe the stages in which input and output are
4450 // referenced by the hardware pipeline.
4451
4452 // Naming convention: ialu or fpu
4453 // Then: _reg
4454 // Then: _reg if there is a 2nd register
4455 // Then: _long if it's a pair of instructions implementing a long
4456 // Then: _fat if it requires the big decoder
4457 // Or: _mem if it requires the big decoder and a memory unit.
4458
4459 // Integer ALU reg operation
4460 pipe_class ialu_reg(rRegI dst)
4461 %{
4462 single_instruction;
4463 dst : S4(write);
4464 dst : S3(read);
4465 DECODE : S0; // any decoder
4466 ALU : S3; // any alu
4467 %}
4468
4469 // Long ALU reg operation
4470 pipe_class ialu_reg_long(rRegL dst)
4471 %{
4472 instruction_count(2);
4473 dst : S4(write);
4474 dst : S3(read);
4475 DECODE : S0(2); // any 2 decoders
4476 ALU : S3(2); // both alus
4477 %}
4478
4479 // Integer ALU reg operation using big decoder
4480 pipe_class ialu_reg_fat(rRegI dst)
4481 %{
4482 single_instruction;
4483 dst : S4(write);
4484 dst : S3(read);
4485 D0 : S0; // big decoder only
4486 ALU : S3; // any alu
4487 %}
4488
4489 // Long ALU reg operation using big decoder
4490 pipe_class ialu_reg_long_fat(rRegL dst)
4491 %{
4492 instruction_count(2);
4493 dst : S4(write);
4494 dst : S3(read);
4495 D0 : S0(2); // big decoder only; twice
4496 ALU : S3(2); // any 2 alus
4497 %}
4498
4499 // Integer ALU reg-reg operation
4500 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4501 %{
4502 single_instruction;
4503 dst : S4(write);
4504 src : S3(read);
4505 DECODE : S0; // any decoder
4506 ALU : S3; // any alu
4507 %}
4508
4509 // Long ALU reg-reg operation
4510 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4511 %{
4512 instruction_count(2);
4513 dst : S4(write);
4514 src : S3(read);
4515 DECODE : S0(2); // any 2 decoders
4516 ALU : S3(2); // both alus
4517 %}
4518
4519 // Integer ALU reg-reg operation
4520 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4521 %{
4522 single_instruction;
4523 dst : S4(write);
4524 src : S3(read);
4525 D0 : S0; // big decoder only
4526 ALU : S3; // any alu
4527 %}
4528
4529 // Long ALU reg-reg operation
4530 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4531 %{
4532 instruction_count(2);
4533 dst : S4(write);
4534 src : S3(read);
4535 D0 : S0(2); // big decoder only; twice
4536 ALU : S3(2); // both alus
4537 %}
4538
4539 // Integer ALU reg-mem operation
4540 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4541 %{
4542 single_instruction;
4543 dst : S5(write);
4544 mem : S3(read);
4545 D0 : S0; // big decoder only
4546 ALU : S4; // any alu
4547 MEM : S3; // any mem
4548 %}
4549
4550 // Integer mem operation (prefetch)
4551 pipe_class ialu_mem(memory mem)
4552 %{
4553 single_instruction;
4554 mem : S3(read);
4555 D0 : S0; // big decoder only
4556 MEM : S3; // any mem
4557 %}
4558
4559 // Integer Store to Memory
4560 pipe_class ialu_mem_reg(memory mem, rRegI src)
4561 %{
4562 single_instruction;
4563 mem : S3(read);
4564 src : S5(read);
4565 D0 : S0; // big decoder only
4566 ALU : S4; // any alu
4567 MEM : S3;
4568 %}
4569
4570 // // Long Store to Memory
4571 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4572 // %{
4573 // instruction_count(2);
4574 // mem : S3(read);
4575 // src : S5(read);
4576 // D0 : S0(2); // big decoder only; twice
4577 // ALU : S4(2); // any 2 alus
4578 // MEM : S3(2); // Both mems
4579 // %}
4580
4581 // Integer Store to Memory
4582 pipe_class ialu_mem_imm(memory mem)
4583 %{
4584 single_instruction;
4585 mem : S3(read);
4586 D0 : S0; // big decoder only
4587 ALU : S4; // any alu
4588 MEM : S3;
4589 %}
4590
4591 // Integer ALU0 reg-reg operation
4592 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4593 %{
4594 single_instruction;
4595 dst : S4(write);
4596 src : S3(read);
4597 D0 : S0; // Big decoder only
4598 ALU0 : S3; // only alu0
4599 %}
4600
4601 // Integer ALU0 reg-mem operation
4602 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4603 %{
4604 single_instruction;
4605 dst : S5(write);
4606 mem : S3(read);
4607 D0 : S0; // big decoder only
4608 ALU0 : S4; // ALU0 only
4609 MEM : S3; // any mem
4610 %}
4611
4612 // Integer ALU reg-reg operation
4613 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4614 %{
4615 single_instruction;
4616 cr : S4(write);
4617 src1 : S3(read);
4618 src2 : S3(read);
4619 DECODE : S0; // any decoder
4620 ALU : S3; // any alu
4621 %}
4622
4623 // Integer ALU reg-imm operation
4624 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4625 %{
4626 single_instruction;
4627 cr : S4(write);
4628 src1 : S3(read);
4629 DECODE : S0; // any decoder
4630 ALU : S3; // any alu
4631 %}
4632
4633 // Integer ALU reg-mem operation
4634 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4635 %{
4636 single_instruction;
4637 cr : S4(write);
4638 src1 : S3(read);
4639 src2 : S3(read);
4640 D0 : S0; // big decoder only
4641 ALU : S4; // any alu
4642 MEM : S3;
4643 %}
4644
4645 // Conditional move reg-reg
4646 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4647 %{
4648 instruction_count(4);
4649 y : S4(read);
4650 q : S3(read);
4651 p : S3(read);
4652 DECODE : S0(4); // any decoder
4653 %}
4654
4655 // Conditional move reg-reg
4656 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4657 %{
4658 single_instruction;
4659 dst : S4(write);
4660 src : S3(read);
4661 cr : S3(read);
4662 DECODE : S0; // any decoder
4663 %}
4664
4665 // Conditional move reg-mem
4666 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4667 %{
4668 single_instruction;
4669 dst : S4(write);
4670 src : S3(read);
4671 cr : S3(read);
4672 DECODE : S0; // any decoder
4673 MEM : S3;
4674 %}
4675
4676 // Conditional move reg-reg long
4677 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4678 %{
4679 single_instruction;
4680 dst : S4(write);
4681 src : S3(read);
4682 cr : S3(read);
4683 DECODE : S0(2); // any 2 decoders
4684 %}
4685
4686 // XXX
4687 // // Conditional move double reg-reg
4688 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4689 // %{
4690 // single_instruction;
4691 // dst : S4(write);
4692 // src : S3(read);
4693 // cr : S3(read);
4694 // DECODE : S0; // any decoder
4695 // %}
4696
4697 // Float reg-reg operation
4698 pipe_class fpu_reg(regD dst)
4699 %{
4700 instruction_count(2);
4701 dst : S3(read);
4702 DECODE : S0(2); // any 2 decoders
4703 FPU : S3;
4704 %}
4705
4706 // Float reg-reg operation
4707 pipe_class fpu_reg_reg(regD dst, regD src)
4708 %{
4709 instruction_count(2);
4710 dst : S4(write);
4711 src : S3(read);
4712 DECODE : S0(2); // any 2 decoders
4713 FPU : S3;
4714 %}
4715
4716 // Float reg-reg operation
4717 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4718 %{
4719 instruction_count(3);
4720 dst : S4(write);
4721 src1 : S3(read);
4722 src2 : S3(read);
4723 DECODE : S0(3); // any 3 decoders
4724 FPU : S3(2);
4725 %}
4726
4727 // Float reg-reg operation
4728 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4729 %{
4730 instruction_count(4);
4731 dst : S4(write);
4732 src1 : S3(read);
4733 src2 : S3(read);
4734 src3 : S3(read);
4735 DECODE : S0(4); // any 3 decoders
4736 FPU : S3(2);
4737 %}
4738
4739 // Float reg-reg operation
4740 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4741 %{
4742 instruction_count(4);
4743 dst : S4(write);
4744 src1 : S3(read);
4745 src2 : S3(read);
4746 src3 : S3(read);
4747 DECODE : S1(3); // any 3 decoders
4748 D0 : S0; // Big decoder only
4749 FPU : S3(2);
4750 MEM : S3;
4751 %}
4752
4753 // Float reg-mem operation
4754 pipe_class fpu_reg_mem(regD dst, memory mem)
4755 %{
4756 instruction_count(2);
4757 dst : S5(write);
4758 mem : S3(read);
4759 D0 : S0; // big decoder only
4760 DECODE : S1; // any decoder for FPU POP
4761 FPU : S4;
4762 MEM : S3; // any mem
4763 %}
4764
4765 // Float reg-mem operation
4766 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4767 %{
4768 instruction_count(3);
4769 dst : S5(write);
4770 src1 : S3(read);
4771 mem : S3(read);
4772 D0 : S0; // big decoder only
4773 DECODE : S1(2); // any decoder for FPU POP
4774 FPU : S4;
4775 MEM : S3; // any mem
4776 %}
4777
4778 // Float mem-reg operation
4779 pipe_class fpu_mem_reg(memory mem, regD src)
4780 %{
4781 instruction_count(2);
4782 src : S5(read);
4783 mem : S3(read);
4784 DECODE : S0; // any decoder for FPU PUSH
4785 D0 : S1; // big decoder only
4786 FPU : S4;
4787 MEM : S3; // any mem
4788 %}
4789
4790 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4791 %{
4792 instruction_count(3);
4793 src1 : S3(read);
4794 src2 : S3(read);
4795 mem : S3(read);
4796 DECODE : S0(2); // any decoder for FPU PUSH
4797 D0 : S1; // big decoder only
4798 FPU : S4;
4799 MEM : S3; // any mem
4800 %}
4801
4802 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4803 %{
4804 instruction_count(3);
4805 src1 : S3(read);
4806 src2 : S3(read);
4807 mem : S4(read);
4808 DECODE : S0; // any decoder for FPU PUSH
4809 D0 : S0(2); // big decoder only
4810 FPU : S4;
4811 MEM : S3(2); // any mem
4812 %}
4813
4814 pipe_class fpu_mem_mem(memory dst, memory src1)
4815 %{
4816 instruction_count(2);
4817 src1 : S3(read);
4818 dst : S4(read);
4819 D0 : S0(2); // big decoder only
4820 MEM : S3(2); // any mem
4821 %}
4822
4823 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4824 %{
4825 instruction_count(3);
4826 src1 : S3(read);
4827 src2 : S3(read);
4828 dst : S4(read);
4829 D0 : S0(3); // big decoder only
4830 FPU : S4;
4831 MEM : S3(3); // any mem
4832 %}
4833
4834 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4835 %{
4836 instruction_count(3);
4837 src1 : S4(read);
4838 mem : S4(read);
4839 DECODE : S0; // any decoder for FPU PUSH
4840 D0 : S0(2); // big decoder only
4841 FPU : S4;
4842 MEM : S3(2); // any mem
4843 %}
4844
4845 // Float load constant
4846 pipe_class fpu_reg_con(regD dst)
4847 %{
4848 instruction_count(2);
4849 dst : S5(write);
4850 D0 : S0; // big decoder only for the load
4851 DECODE : S1; // any decoder for FPU POP
4852 FPU : S4;
4853 MEM : S3; // any mem
4854 %}
4855
4856 // Float load constant
4857 pipe_class fpu_reg_reg_con(regD dst, regD src)
4858 %{
4859 instruction_count(3);
4860 dst : S5(write);
4861 src : S3(read);
4862 D0 : S0; // big decoder only for the load
4863 DECODE : S1(2); // any decoder for FPU POP
4864 FPU : S4;
4865 MEM : S3; // any mem
4866 %}
4867
4868 // UnConditional branch
4869 pipe_class pipe_jmp(label labl)
4870 %{
4871 single_instruction;
4872 BR : S3;
4873 %}
4874
4875 // Conditional branch
4876 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4877 %{
4878 single_instruction;
4879 cr : S1(read);
4880 BR : S3;
4881 %}
4882
4883 // Allocation idiom
4884 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4885 %{
4886 instruction_count(1); force_serialization;
4887 fixed_latency(6);
4888 heap_ptr : S3(read);
4889 DECODE : S0(3);
4890 D0 : S2;
4891 MEM : S3;
4892 ALU : S3(2);
4893 dst : S5(write);
4894 BR : S5;
4895 %}
4896
4897 // Generic big/slow expanded idiom
4898 pipe_class pipe_slow()
4899 %{
4900 instruction_count(10); multiple_bundles; force_serialization;
4901 fixed_latency(100);
4902 D0 : S0(2);
4903 MEM : S3(2);
4904 %}
4905
4906 // The real do-nothing guy
4907 pipe_class empty()
4908 %{
4909 instruction_count(0);
4910 %}
4911
4912 // Define the class for the Nop node
4913 define
4914 %{
4915 MachNop = empty;
4916 %}
4917
4918 %}
4919
4920 //----------INSTRUCTIONS-------------------------------------------------------
4921 //
4922 // match -- States which machine-independent subtree may be replaced
4923 // by this instruction.
4924 // ins_cost -- The estimated cost of this instruction is used by instruction
4925 // selection to identify a minimum cost tree of machine
4926 // instructions that matches a tree of machine-independent
4927 // instructions.
4928 // format -- A string providing the disassembly for this instruction.
4929 // The value of an instruction's operand may be inserted
4930 // by referring to it with a '$' prefix.
4931 // opcode -- Three instruction opcodes may be provided. These are referred
4932 // to within an encode class as $primary, $secondary, and $tertiary
4933 // rrspectively. The primary opcode is commonly used to
4934 // indicate the type of machine instruction, while secondary
4935 // and tertiary are often used for prefix options or addressing
4936 // modes.
4937 // ins_encode -- A list of encode classes with parameters. The encode class
4938 // name must have been defined in an 'enc_class' specification
4939 // in the encode section of the architecture description.
4940
4941
4942 //----------Load/Store/Move Instructions---------------------------------------
4943 //----------Load Instructions--------------------------------------------------
4944
4945 // Load Byte (8 bit signed)
4946 instruct loadB(rRegI dst, memory mem)
4947 %{
4948 match(Set dst (LoadB mem));
4949
4950 ins_cost(125);
4951 format %{ "movsbl $dst, $mem\t# byte" %}
4952
4953 ins_encode %{
4954 __ movsbl($dst$$Register, $mem$$Address);
4955 %}
4956
4957 ins_pipe(ialu_reg_mem);
4958 %}
4959
4960 // Load Byte (8 bit signed) into Long Register
4961 instruct loadB2L(rRegL dst, memory mem)
4962 %{
4963 match(Set dst (ConvI2L (LoadB mem)));
4964
4965 ins_cost(125);
4966 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4967
4968 ins_encode %{
4969 __ movsbq($dst$$Register, $mem$$Address);
4970 %}
4971
4972 ins_pipe(ialu_reg_mem);
4973 %}
4974
4975 // Load Unsigned Byte (8 bit UNsigned)
4976 instruct loadUB(rRegI dst, memory mem)
4977 %{
4978 match(Set dst (LoadUB mem));
4979
4980 ins_cost(125);
4981 format %{ "movzbl $dst, $mem\t# ubyte" %}
4982
4983 ins_encode %{
4984 __ movzbl($dst$$Register, $mem$$Address);
4985 %}
4986
4987 ins_pipe(ialu_reg_mem);
4988 %}
4989
4990 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4991 instruct loadUB2L(rRegL dst, memory mem)
4992 %{
4993 match(Set dst (ConvI2L (LoadUB mem)));
4994
4995 ins_cost(125);
4996 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4997
4998 ins_encode %{
4999 __ movzbq($dst$$Register, $mem$$Address);
5000 %}
5001
5002 ins_pipe(ialu_reg_mem);
5003 %}
5004
5005 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5006 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5007 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5008 effect(KILL cr);
5009
5010 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5011 "andl $dst, right_n_bits($mask, 8)" %}
5012 ins_encode %{
5013 Register Rdst = $dst$$Register;
5014 __ movzbq(Rdst, $mem$$Address);
5015 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5016 %}
5017 ins_pipe(ialu_reg_mem);
5018 %}
5019
5020 // Load Short (16 bit signed)
5021 instruct loadS(rRegI dst, memory mem)
5022 %{
5023 match(Set dst (LoadS mem));
5024
5025 ins_cost(125);
5026 format %{ "movswl $dst, $mem\t# short" %}
5027
5028 ins_encode %{
5029 __ movswl($dst$$Register, $mem$$Address);
5030 %}
5031
5032 ins_pipe(ialu_reg_mem);
5033 %}
5034
5035 // Load Short (16 bit signed) to Byte (8 bit signed)
5036 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5037 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5038
5039 ins_cost(125);
5040 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5041 ins_encode %{
5042 __ movsbl($dst$$Register, $mem$$Address);
5043 %}
5044 ins_pipe(ialu_reg_mem);
5045 %}
5046
5047 // Load Short (16 bit signed) into Long Register
5048 instruct loadS2L(rRegL dst, memory mem)
5049 %{
5050 match(Set dst (ConvI2L (LoadS mem)));
5051
5052 ins_cost(125);
5053 format %{ "movswq $dst, $mem\t# short -> long" %}
5054
5055 ins_encode %{
5056 __ movswq($dst$$Register, $mem$$Address);
5057 %}
5058
5059 ins_pipe(ialu_reg_mem);
5060 %}
5061
5062 // Load Unsigned Short/Char (16 bit UNsigned)
5063 instruct loadUS(rRegI dst, memory mem)
5064 %{
5065 match(Set dst (LoadUS mem));
5066
5067 ins_cost(125);
5068 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5069
5070 ins_encode %{
5071 __ movzwl($dst$$Register, $mem$$Address);
5072 %}
5073
5074 ins_pipe(ialu_reg_mem);
5075 %}
5076
5077 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5078 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5079 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5080
5081 ins_cost(125);
5082 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5083 ins_encode %{
5084 __ movsbl($dst$$Register, $mem$$Address);
5085 %}
5086 ins_pipe(ialu_reg_mem);
5087 %}
5088
5089 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5090 instruct loadUS2L(rRegL dst, memory mem)
5091 %{
5092 match(Set dst (ConvI2L (LoadUS mem)));
5093
5094 ins_cost(125);
5095 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5096
5097 ins_encode %{
5098 __ movzwq($dst$$Register, $mem$$Address);
5099 %}
5100
5101 ins_pipe(ialu_reg_mem);
5102 %}
5103
5104 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5105 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5106 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5107
5108 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5109 ins_encode %{
5110 __ movzbq($dst$$Register, $mem$$Address);
5111 %}
5112 ins_pipe(ialu_reg_mem);
5113 %}
5114
5115 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5116 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5117 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5118 effect(KILL cr);
5119
5120 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5121 "andl $dst, right_n_bits($mask, 16)" %}
5122 ins_encode %{
5123 Register Rdst = $dst$$Register;
5124 __ movzwq(Rdst, $mem$$Address);
5125 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5126 %}
5127 ins_pipe(ialu_reg_mem);
5128 %}
5129
5130 // Load Integer
5131 instruct loadI(rRegI dst, memory mem)
5132 %{
5133 match(Set dst (LoadI mem));
5134
5135 ins_cost(125);
5136 format %{ "movl $dst, $mem\t# int" %}
5137
5138 ins_encode %{
5139 __ movl($dst$$Register, $mem$$Address);
5140 %}
5141
5142 ins_pipe(ialu_reg_mem);
5143 %}
5144
5145 // Load Integer (32 bit signed) to Byte (8 bit signed)
5146 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5147 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5148
5149 ins_cost(125);
5150 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5151 ins_encode %{
5152 __ movsbl($dst$$Register, $mem$$Address);
5153 %}
5154 ins_pipe(ialu_reg_mem);
5155 %}
5156
5157 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5158 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5159 match(Set dst (AndI (LoadI mem) mask));
5160
5161 ins_cost(125);
5162 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5163 ins_encode %{
5164 __ movzbl($dst$$Register, $mem$$Address);
5165 %}
5166 ins_pipe(ialu_reg_mem);
5167 %}
5168
5169 // Load Integer (32 bit signed) to Short (16 bit signed)
5170 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5171 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5172
5173 ins_cost(125);
5174 format %{ "movswl $dst, $mem\t# int -> short" %}
5175 ins_encode %{
5176 __ movswl($dst$$Register, $mem$$Address);
5177 %}
5178 ins_pipe(ialu_reg_mem);
5179 %}
5180
5181 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5182 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5183 match(Set dst (AndI (LoadI mem) mask));
5184
5185 ins_cost(125);
5186 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5187 ins_encode %{
5188 __ movzwl($dst$$Register, $mem$$Address);
5189 %}
5190 ins_pipe(ialu_reg_mem);
5191 %}
5192
5193 // Load Integer into Long Register
5194 instruct loadI2L(rRegL dst, memory mem)
5195 %{
5196 match(Set dst (ConvI2L (LoadI mem)));
5197
5198 ins_cost(125);
5199 format %{ "movslq $dst, $mem\t# int -> long" %}
5200
5201 ins_encode %{
5202 __ movslq($dst$$Register, $mem$$Address);
5203 %}
5204
5205 ins_pipe(ialu_reg_mem);
5206 %}
5207
5208 // Load Integer with mask 0xFF into Long Register
5209 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5210 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5211
5212 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5213 ins_encode %{
5214 __ movzbq($dst$$Register, $mem$$Address);
5215 %}
5216 ins_pipe(ialu_reg_mem);
5217 %}
5218
5219 // Load Integer with mask 0xFFFF into Long Register
5220 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5221 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5222
5223 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5224 ins_encode %{
5225 __ movzwq($dst$$Register, $mem$$Address);
5226 %}
5227 ins_pipe(ialu_reg_mem);
5228 %}
5229
5230 // Load Integer with a 31-bit mask into Long Register
5231 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5232 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5233 effect(KILL cr);
5234
5235 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5236 "andl $dst, $mask" %}
5237 ins_encode %{
5238 Register Rdst = $dst$$Register;
5239 __ movl(Rdst, $mem$$Address);
5240 __ andl(Rdst, $mask$$constant);
5241 %}
5242 ins_pipe(ialu_reg_mem);
5243 %}
5244
5245 // Load Unsigned Integer into Long Register
5246 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5247 %{
5248 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5249
5250 ins_cost(125);
5251 format %{ "movl $dst, $mem\t# uint -> long" %}
5252
5253 ins_encode %{
5254 __ movl($dst$$Register, $mem$$Address);
5255 %}
5256
5257 ins_pipe(ialu_reg_mem);
5258 %}
5259
5260 // Load Long
5261 instruct loadL(rRegL dst, memory mem)
5262 %{
5263 match(Set dst (LoadL mem));
5264
5265 ins_cost(125);
5266 format %{ "movq $dst, $mem\t# long" %}
5267
5268 ins_encode %{
5269 __ movq($dst$$Register, $mem$$Address);
5270 %}
5271
5272 ins_pipe(ialu_reg_mem); // XXX
5273 %}
5274
5275 // Load Range
5276 instruct loadRange(rRegI dst, memory mem)
5277 %{
5278 match(Set dst (LoadRange mem));
5279
5280 ins_cost(125); // XXX
5281 format %{ "movl $dst, $mem\t# range" %}
5282 opcode(0x8B);
5283 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5284 ins_pipe(ialu_reg_mem);
5285 %}
5286
5287 // Load Pointer
5288 instruct loadP(rRegP dst, memory mem)
5289 %{
5290 match(Set dst (LoadP mem));
5291
5292 ins_cost(125); // XXX
5293 format %{ "movq $dst, $mem\t# ptr" %}
5294 opcode(0x8B);
5295 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5296 ins_pipe(ialu_reg_mem); // XXX
5297 %}
5298
5299 // Load Compressed Pointer
5300 instruct loadN(rRegN dst, memory mem)
5301 %{
5302 match(Set dst (LoadN mem));
5303
5304 ins_cost(125); // XXX
5305 format %{ "movl $dst, $mem\t# compressed ptr" %}
5306 ins_encode %{
5307 __ movl($dst$$Register, $mem$$Address);
5308 %}
5309 ins_pipe(ialu_reg_mem); // XXX
5310 %}
5311
5312
5313 // Load Klass Pointer
5314 instruct loadKlass(rRegP dst, memory mem)
5315 %{
5316 match(Set dst (LoadKlass mem));
5317
5318 ins_cost(125); // XXX
5319 format %{ "movq $dst, $mem\t# class" %}
5320 opcode(0x8B);
5321 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5322 ins_pipe(ialu_reg_mem); // XXX
5323 %}
5324
5325 // Load narrow Klass Pointer
5326 instruct loadNKlass(rRegN dst, memory mem)
5327 %{
5328 match(Set dst (LoadNKlass mem));
5329
5330 ins_cost(125); // XXX
5331 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5332 ins_encode %{
5333 __ movl($dst$$Register, $mem$$Address);
5334 %}
5335 ins_pipe(ialu_reg_mem); // XXX
5336 %}
5337
5338 // Load Float
5339 instruct loadF(regF dst, memory mem)
5340 %{
5341 match(Set dst (LoadF mem));
5342
5343 ins_cost(145); // XXX
5344 format %{ "movss $dst, $mem\t# float" %}
5345 ins_encode %{
5346 __ movflt($dst$$XMMRegister, $mem$$Address);
5347 %}
5348 ins_pipe(pipe_slow); // XXX
5349 %}
5350
5351 // Load Float
5352 instruct MoveF2VL(vlRegF dst, regF src) %{
5353 match(Set dst src);
5354 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5355 ins_encode %{
5356 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5357 %}
5358 ins_pipe( fpu_reg_reg );
5359 %}
5360
5361 // Load Float
5362 instruct MoveVL2F(regF dst, vlRegF src) %{
5363 match(Set dst src);
5364 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5365 ins_encode %{
5366 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5367 %}
5368 ins_pipe( fpu_reg_reg );
5369 %}
5370
5371 // Load Double
5372 instruct loadD_partial(regD dst, memory mem)
5373 %{
5374 predicate(!UseXmmLoadAndClearUpper);
5375 match(Set dst (LoadD mem));
5376
5377 ins_cost(145); // XXX
5378 format %{ "movlpd $dst, $mem\t# double" %}
5379 ins_encode %{
5380 __ movdbl($dst$$XMMRegister, $mem$$Address);
5381 %}
5382 ins_pipe(pipe_slow); // XXX
5383 %}
5384
5385 instruct loadD(regD dst, memory mem)
5386 %{
5387 predicate(UseXmmLoadAndClearUpper);
5388 match(Set dst (LoadD mem));
5389
5390 ins_cost(145); // XXX
5391 format %{ "movsd $dst, $mem\t# double" %}
5392 ins_encode %{
5393 __ movdbl($dst$$XMMRegister, $mem$$Address);
5394 %}
5395 ins_pipe(pipe_slow); // XXX
5396 %}
5397
5398 // Load Double
5399 instruct MoveD2VL(vlRegD dst, regD src) %{
5400 match(Set dst src);
5401 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5402 ins_encode %{
5403 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5404 %}
5405 ins_pipe( fpu_reg_reg );
5406 %}
5407
5408 // Load Double
5409 instruct MoveVL2D(regD dst, vlRegD src) %{
5410 match(Set dst src);
5411 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5412 ins_encode %{
5413 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5414 %}
5415 ins_pipe( fpu_reg_reg );
5416 %}
5417
5418 // Load Effective Address
5419 instruct leaP8(rRegP dst, indOffset8 mem)
5420 %{
5421 match(Set dst mem);
5422
5423 ins_cost(110); // XXX
5424 format %{ "leaq $dst, $mem\t# ptr 8" %}
5425 opcode(0x8D);
5426 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5427 ins_pipe(ialu_reg_reg_fat);
5428 %}
5429
5430 instruct leaP32(rRegP dst, indOffset32 mem)
5431 %{
5432 match(Set dst mem);
5433
5434 ins_cost(110);
5435 format %{ "leaq $dst, $mem\t# ptr 32" %}
5436 opcode(0x8D);
5437 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5438 ins_pipe(ialu_reg_reg_fat);
5439 %}
5440
5441 // instruct leaPIdx(rRegP dst, indIndex mem)
5442 // %{
5443 // match(Set dst mem);
5444
5445 // ins_cost(110);
5446 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5447 // opcode(0x8D);
5448 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5449 // ins_pipe(ialu_reg_reg_fat);
5450 // %}
5451
5452 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5453 %{
5454 match(Set dst mem);
5455
5456 ins_cost(110);
5457 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5458 opcode(0x8D);
5459 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5460 ins_pipe(ialu_reg_reg_fat);
5461 %}
5462
5463 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5464 %{
5465 match(Set dst mem);
5466
5467 ins_cost(110);
5468 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5469 opcode(0x8D);
5470 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5471 ins_pipe(ialu_reg_reg_fat);
5472 %}
5473
5474 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5475 %{
5476 match(Set dst mem);
5477
5478 ins_cost(110);
5479 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5480 opcode(0x8D);
5481 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5482 ins_pipe(ialu_reg_reg_fat);
5483 %}
5484
5485 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5486 %{
5487 match(Set dst mem);
5488
5489 ins_cost(110);
5490 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5491 opcode(0x8D);
5492 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5493 ins_pipe(ialu_reg_reg_fat);
5494 %}
5495
5496 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5497 %{
5498 match(Set dst mem);
5499
5500 ins_cost(110);
5501 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5502 opcode(0x8D);
5503 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5504 ins_pipe(ialu_reg_reg_fat);
5505 %}
5506
5507 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5508 %{
5509 match(Set dst mem);
5510
5511 ins_cost(110);
5512 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5513 opcode(0x8D);
5514 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5515 ins_pipe(ialu_reg_reg_fat);
5516 %}
5517
5518 // Load Effective Address which uses Narrow (32-bits) oop
5519 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5520 %{
5521 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5522 match(Set dst mem);
5523
5524 ins_cost(110);
5525 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5526 opcode(0x8D);
5527 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5528 ins_pipe(ialu_reg_reg_fat);
5529 %}
5530
5531 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5532 %{
5533 predicate(Universe::narrow_oop_shift() == 0);
5534 match(Set dst mem);
5535
5536 ins_cost(110); // XXX
5537 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5538 opcode(0x8D);
5539 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5540 ins_pipe(ialu_reg_reg_fat);
5541 %}
5542
5543 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5544 %{
5545 predicate(Universe::narrow_oop_shift() == 0);
5546 match(Set dst mem);
5547
5548 ins_cost(110);
5549 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5550 opcode(0x8D);
5551 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5552 ins_pipe(ialu_reg_reg_fat);
5553 %}
5554
5555 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5556 %{
5557 predicate(Universe::narrow_oop_shift() == 0);
5558 match(Set dst mem);
5559
5560 ins_cost(110);
5561 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5562 opcode(0x8D);
5563 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5564 ins_pipe(ialu_reg_reg_fat);
5565 %}
5566
5567 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5568 %{
5569 predicate(Universe::narrow_oop_shift() == 0);
5570 match(Set dst mem);
5571
5572 ins_cost(110);
5573 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5574 opcode(0x8D);
5575 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5576 ins_pipe(ialu_reg_reg_fat);
5577 %}
5578
5579 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5580 %{
5581 predicate(Universe::narrow_oop_shift() == 0);
5582 match(Set dst mem);
5583
5584 ins_cost(110);
5585 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5586 opcode(0x8D);
5587 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5588 ins_pipe(ialu_reg_reg_fat);
5589 %}
5590
5591 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5592 %{
5593 predicate(Universe::narrow_oop_shift() == 0);
5594 match(Set dst mem);
5595
5596 ins_cost(110);
5597 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5598 opcode(0x8D);
5599 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5600 ins_pipe(ialu_reg_reg_fat);
5601 %}
5602
5603 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5604 %{
5605 predicate(Universe::narrow_oop_shift() == 0);
5606 match(Set dst mem);
5607
5608 ins_cost(110);
5609 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5610 opcode(0x8D);
5611 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5612 ins_pipe(ialu_reg_reg_fat);
5613 %}
5614
5615 instruct loadConI(rRegI dst, immI src)
5616 %{
5617 match(Set dst src);
5618
5619 format %{ "movl $dst, $src\t# int" %}
5620 ins_encode(load_immI(dst, src));
5621 ins_pipe(ialu_reg_fat); // XXX
5622 %}
5623
5624 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5625 %{
5626 match(Set dst src);
5627 effect(KILL cr);
5628
5629 ins_cost(50);
5630 format %{ "xorl $dst, $dst\t# int" %}
5631 opcode(0x33); /* + rd */
5632 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5633 ins_pipe(ialu_reg);
5634 %}
5635
5636 instruct loadConL(rRegL dst, immL src)
5637 %{
5638 match(Set dst src);
5639
5640 ins_cost(150);
5641 format %{ "movq $dst, $src\t# long" %}
5642 ins_encode(load_immL(dst, src));
5643 ins_pipe(ialu_reg);
5644 %}
5645
5646 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5647 %{
5648 match(Set dst src);
5649 effect(KILL cr);
5650
5651 ins_cost(50);
5652 format %{ "xorl $dst, $dst\t# long" %}
5653 opcode(0x33); /* + rd */
5654 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5655 ins_pipe(ialu_reg); // XXX
5656 %}
5657
5658 instruct loadConUL32(rRegL dst, immUL32 src)
5659 %{
5660 match(Set dst src);
5661
5662 ins_cost(60);
5663 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5664 ins_encode(load_immUL32(dst, src));
5665 ins_pipe(ialu_reg);
5666 %}
5667
5668 instruct loadConL32(rRegL dst, immL32 src)
5669 %{
5670 match(Set dst src);
5671
5672 ins_cost(70);
5673 format %{ "movq $dst, $src\t# long (32-bit)" %}
5674 ins_encode(load_immL32(dst, src));
5675 ins_pipe(ialu_reg);
5676 %}
5677
5678 instruct loadConP(rRegP dst, immP con) %{
5679 match(Set dst con);
5680
5681 format %{ "movq $dst, $con\t# ptr" %}
5682 ins_encode(load_immP(dst, con));
5683 ins_pipe(ialu_reg_fat); // XXX
5684 %}
5685
5686 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5687 %{
5688 match(Set dst src);
5689 effect(KILL cr);
5690
5691 ins_cost(50);
5692 format %{ "xorl $dst, $dst\t# ptr" %}
5693 opcode(0x33); /* + rd */
5694 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5695 ins_pipe(ialu_reg);
5696 %}
5697
5698 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5699 %{
5700 match(Set dst src);
5701 effect(KILL cr);
5702
5703 ins_cost(60);
5704 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5705 ins_encode(load_immP31(dst, src));
5706 ins_pipe(ialu_reg);
5707 %}
5708
5709 instruct loadConF(regF dst, immF con) %{
5710 match(Set dst con);
5711 ins_cost(125);
5712 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5713 ins_encode %{
5714 __ movflt($dst$$XMMRegister, $constantaddress($con));
5715 %}
5716 ins_pipe(pipe_slow);
5717 %}
5718
5719 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5720 match(Set dst src);
5721 effect(KILL cr);
5722 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5723 ins_encode %{
5724 __ xorq($dst$$Register, $dst$$Register);
5725 %}
5726 ins_pipe(ialu_reg);
5727 %}
5728
5729 instruct loadConN(rRegN dst, immN src) %{
5730 match(Set dst src);
5731
5732 ins_cost(125);
5733 format %{ "movl $dst, $src\t# compressed ptr" %}
5734 ins_encode %{
5735 address con = (address)$src$$constant;
5736 if (con == NULL) {
5737 ShouldNotReachHere();
5738 } else {
5739 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5740 }
5741 %}
5742 ins_pipe(ialu_reg_fat); // XXX
5743 %}
5744
5745 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5746 match(Set dst src);
5747
5748 ins_cost(125);
5749 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5750 ins_encode %{
5751 address con = (address)$src$$constant;
5752 if (con == NULL) {
5753 ShouldNotReachHere();
5754 } else {
5755 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5756 }
5757 %}
5758 ins_pipe(ialu_reg_fat); // XXX
5759 %}
5760
5761 instruct loadConF0(regF dst, immF0 src)
5762 %{
5763 match(Set dst src);
5764 ins_cost(100);
5765
5766 format %{ "xorps $dst, $dst\t# float 0.0" %}
5767 ins_encode %{
5768 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5769 %}
5770 ins_pipe(pipe_slow);
5771 %}
5772
5773 // Use the same format since predicate() can not be used here.
5774 instruct loadConD(regD dst, immD con) %{
5775 match(Set dst con);
5776 ins_cost(125);
5777 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5778 ins_encode %{
5779 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5780 %}
5781 ins_pipe(pipe_slow);
5782 %}
5783
5784 instruct loadConD0(regD dst, immD0 src)
5785 %{
5786 match(Set dst src);
5787 ins_cost(100);
5788
5789 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5790 ins_encode %{
5791 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5792 %}
5793 ins_pipe(pipe_slow);
5794 %}
5795
5796 instruct loadSSI(rRegI dst, stackSlotI src)
5797 %{
5798 match(Set dst src);
5799
5800 ins_cost(125);
5801 format %{ "movl $dst, $src\t# int stk" %}
5802 opcode(0x8B);
5803 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5804 ins_pipe(ialu_reg_mem);
5805 %}
5806
5807 instruct loadSSL(rRegL dst, stackSlotL src)
5808 %{
5809 match(Set dst src);
5810
5811 ins_cost(125);
5812 format %{ "movq $dst, $src\t# long stk" %}
5813 opcode(0x8B);
5814 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5815 ins_pipe(ialu_reg_mem);
5816 %}
5817
5818 instruct loadSSP(rRegP dst, stackSlotP src)
5819 %{
5820 match(Set dst src);
5821
5822 ins_cost(125);
5823 format %{ "movq $dst, $src\t# ptr stk" %}
5824 opcode(0x8B);
5825 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5826 ins_pipe(ialu_reg_mem);
5827 %}
5828
5829 instruct loadSSF(regF dst, stackSlotF src)
5830 %{
5831 match(Set dst src);
5832
5833 ins_cost(125);
5834 format %{ "movss $dst, $src\t# float stk" %}
5835 ins_encode %{
5836 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5837 %}
5838 ins_pipe(pipe_slow); // XXX
5839 %}
5840
5841 // Use the same format since predicate() can not be used here.
5842 instruct loadSSD(regD dst, stackSlotD src)
5843 %{
5844 match(Set dst src);
5845
5846 ins_cost(125);
5847 format %{ "movsd $dst, $src\t# double stk" %}
5848 ins_encode %{
5849 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5850 %}
5851 ins_pipe(pipe_slow); // XXX
5852 %}
5853
5854 // Prefetch instructions for allocation.
5855 // Must be safe to execute with invalid address (cannot fault).
5856
5857 instruct prefetchAlloc( memory mem ) %{
5858 predicate(AllocatePrefetchInstr==3);
5859 match(PrefetchAllocation mem);
5860 ins_cost(125);
5861
5862 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5863 ins_encode %{
5864 __ prefetchw($mem$$Address);
5865 %}
5866 ins_pipe(ialu_mem);
5867 %}
5868
5869 instruct prefetchAllocNTA( memory mem ) %{
5870 predicate(AllocatePrefetchInstr==0);
5871 match(PrefetchAllocation mem);
5872 ins_cost(125);
5873
5874 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5875 ins_encode %{
5876 __ prefetchnta($mem$$Address);
5877 %}
5878 ins_pipe(ialu_mem);
5879 %}
5880
5881 instruct prefetchAllocT0( memory mem ) %{
5882 predicate(AllocatePrefetchInstr==1);
5883 match(PrefetchAllocation mem);
5884 ins_cost(125);
5885
5886 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5887 ins_encode %{
5888 __ prefetcht0($mem$$Address);
5889 %}
5890 ins_pipe(ialu_mem);
5891 %}
5892
5893 instruct prefetchAllocT2( memory mem ) %{
5894 predicate(AllocatePrefetchInstr==2);
5895 match(PrefetchAllocation mem);
5896 ins_cost(125);
5897
5898 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5899 ins_encode %{
5900 __ prefetcht2($mem$$Address);
5901 %}
5902 ins_pipe(ialu_mem);
5903 %}
5904
5905 //----------Store Instructions-------------------------------------------------
5906
5907 // Store Byte
5908 instruct storeB(memory mem, rRegI src)
5909 %{
5910 match(Set mem (StoreB mem src));
5911
5912 ins_cost(125); // XXX
5913 format %{ "movb $mem, $src\t# byte" %}
5914 opcode(0x88);
5915 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5916 ins_pipe(ialu_mem_reg);
5917 %}
5918
5919 // Store Char/Short
5920 instruct storeC(memory mem, rRegI src)
5921 %{
5922 match(Set mem (StoreC mem src));
5923
5924 ins_cost(125); // XXX
5925 format %{ "movw $mem, $src\t# char/short" %}
5926 opcode(0x89);
5927 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5928 ins_pipe(ialu_mem_reg);
5929 %}
5930
5931 // Store Integer
5932 instruct storeI(memory mem, rRegI src)
5933 %{
5934 match(Set mem (StoreI mem src));
5935
5936 ins_cost(125); // XXX
5937 format %{ "movl $mem, $src\t# int" %}
5938 opcode(0x89);
5939 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5940 ins_pipe(ialu_mem_reg);
5941 %}
5942
5943 // Store Long
5944 instruct storeL(memory mem, rRegL src)
5945 %{
5946 match(Set mem (StoreL mem src));
5947
5948 ins_cost(125); // XXX
5949 format %{ "movq $mem, $src\t# long" %}
5950 opcode(0x89);
5951 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5952 ins_pipe(ialu_mem_reg); // XXX
5953 %}
5954
5955 // Store Pointer
5956 instruct storeP(memory mem, any_RegP src)
5957 %{
5958 match(Set mem (StoreP mem src));
5959
5960 ins_cost(125); // XXX
5961 format %{ "movq $mem, $src\t# ptr" %}
5962 opcode(0x89);
5963 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5964 ins_pipe(ialu_mem_reg);
5965 %}
5966
5967 instruct storeImmP0(memory mem, immP0 zero)
5968 %{
5969 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5970 match(Set mem (StoreP mem zero));
5971
5972 ins_cost(125); // XXX
5973 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5974 ins_encode %{
5975 __ movq($mem$$Address, r12);
5976 %}
5977 ins_pipe(ialu_mem_reg);
5978 %}
5979
5980 // Store NULL Pointer, mark word, or other simple pointer constant.
5981 instruct storeImmP(memory mem, immP31 src)
5982 %{
5983 match(Set mem (StoreP mem src));
5984
5985 ins_cost(150); // XXX
5986 format %{ "movq $mem, $src\t# ptr" %}
5987 opcode(0xC7); /* C7 /0 */
5988 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5989 ins_pipe(ialu_mem_imm);
5990 %}
5991
5992 // Store Compressed Pointer
5993 instruct storeN(memory mem, rRegN src)
5994 %{
5995 match(Set mem (StoreN mem src));
5996
5997 ins_cost(125); // XXX
5998 format %{ "movl $mem, $src\t# compressed ptr" %}
5999 ins_encode %{
6000 __ movl($mem$$Address, $src$$Register);
6001 %}
6002 ins_pipe(ialu_mem_reg);
6003 %}
6004
6005 instruct storeNKlass(memory mem, rRegN src)
6006 %{
6007 match(Set mem (StoreNKlass mem src));
6008
6009 ins_cost(125); // XXX
6010 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6011 ins_encode %{
6012 __ movl($mem$$Address, $src$$Register);
6013 %}
6014 ins_pipe(ialu_mem_reg);
6015 %}
6016
6017 instruct storeImmN0(memory mem, immN0 zero)
6018 %{
6019 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6020 match(Set mem (StoreN mem zero));
6021
6022 ins_cost(125); // XXX
6023 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6024 ins_encode %{
6025 __ movl($mem$$Address, r12);
6026 %}
6027 ins_pipe(ialu_mem_reg);
6028 %}
6029
6030 instruct storeImmN(memory mem, immN src)
6031 %{
6032 match(Set mem (StoreN mem src));
6033
6034 ins_cost(150); // XXX
6035 format %{ "movl $mem, $src\t# compressed ptr" %}
6036 ins_encode %{
6037 address con = (address)$src$$constant;
6038 if (con == NULL) {
6039 __ movl($mem$$Address, (int32_t)0);
6040 } else {
6041 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6042 }
6043 %}
6044 ins_pipe(ialu_mem_imm);
6045 %}
6046
6047 instruct storeImmNKlass(memory mem, immNKlass src)
6048 %{
6049 match(Set mem (StoreNKlass mem src));
6050
6051 ins_cost(150); // XXX
6052 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6053 ins_encode %{
6054 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6055 %}
6056 ins_pipe(ialu_mem_imm);
6057 %}
6058
6059 // Store Integer Immediate
6060 instruct storeImmI0(memory mem, immI0 zero)
6061 %{
6062 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6063 match(Set mem (StoreI mem zero));
6064
6065 ins_cost(125); // XXX
6066 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6067 ins_encode %{
6068 __ movl($mem$$Address, r12);
6069 %}
6070 ins_pipe(ialu_mem_reg);
6071 %}
6072
6073 instruct storeImmI(memory mem, immI src)
6074 %{
6075 match(Set mem (StoreI mem src));
6076
6077 ins_cost(150);
6078 format %{ "movl $mem, $src\t# int" %}
6079 opcode(0xC7); /* C7 /0 */
6080 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6081 ins_pipe(ialu_mem_imm);
6082 %}
6083
6084 // Store Long Immediate
6085 instruct storeImmL0(memory mem, immL0 zero)
6086 %{
6087 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6088 match(Set mem (StoreL mem zero));
6089
6090 ins_cost(125); // XXX
6091 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6092 ins_encode %{
6093 __ movq($mem$$Address, r12);
6094 %}
6095 ins_pipe(ialu_mem_reg);
6096 %}
6097
6098 instruct storeImmL(memory mem, immL32 src)
6099 %{
6100 match(Set mem (StoreL mem src));
6101
6102 ins_cost(150);
6103 format %{ "movq $mem, $src\t# long" %}
6104 opcode(0xC7); /* C7 /0 */
6105 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6106 ins_pipe(ialu_mem_imm);
6107 %}
6108
6109 // Store Short/Char Immediate
6110 instruct storeImmC0(memory mem, immI0 zero)
6111 %{
6112 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6113 match(Set mem (StoreC mem zero));
6114
6115 ins_cost(125); // XXX
6116 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6117 ins_encode %{
6118 __ movw($mem$$Address, r12);
6119 %}
6120 ins_pipe(ialu_mem_reg);
6121 %}
6122
6123 instruct storeImmI16(memory mem, immI16 src)
6124 %{
6125 predicate(UseStoreImmI16);
6126 match(Set mem (StoreC mem src));
6127
6128 ins_cost(150);
6129 format %{ "movw $mem, $src\t# short/char" %}
6130 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6131 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6132 ins_pipe(ialu_mem_imm);
6133 %}
6134
6135 // Store Byte Immediate
6136 instruct storeImmB0(memory mem, immI0 zero)
6137 %{
6138 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6139 match(Set mem (StoreB mem zero));
6140
6141 ins_cost(125); // XXX
6142 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6143 ins_encode %{
6144 __ movb($mem$$Address, r12);
6145 %}
6146 ins_pipe(ialu_mem_reg);
6147 %}
6148
6149 instruct storeImmB(memory mem, immI8 src)
6150 %{
6151 match(Set mem (StoreB mem src));
6152
6153 ins_cost(150); // XXX
6154 format %{ "movb $mem, $src\t# byte" %}
6155 opcode(0xC6); /* C6 /0 */
6156 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6157 ins_pipe(ialu_mem_imm);
6158 %}
6159
6160 // Store CMS card-mark Immediate
6161 instruct storeImmCM0_reg(memory mem, immI0 zero)
6162 %{
6163 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6164 match(Set mem (StoreCM mem zero));
6165
6166 ins_cost(125); // XXX
6167 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6168 ins_encode %{
6169 __ movb($mem$$Address, r12);
6170 %}
6171 ins_pipe(ialu_mem_reg);
6172 %}
6173
6174 instruct storeImmCM0(memory mem, immI0 src)
6175 %{
6176 match(Set mem (StoreCM mem src));
6177
6178 ins_cost(150); // XXX
6179 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6180 opcode(0xC6); /* C6 /0 */
6181 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6182 ins_pipe(ialu_mem_imm);
6183 %}
6184
6185 // Store Float
6186 instruct storeF(memory mem, regF src)
6187 %{
6188 match(Set mem (StoreF mem src));
6189
6190 ins_cost(95); // XXX
6191 format %{ "movss $mem, $src\t# float" %}
6192 ins_encode %{
6193 __ movflt($mem$$Address, $src$$XMMRegister);
6194 %}
6195 ins_pipe(pipe_slow); // XXX
6196 %}
6197
6198 // Store immediate Float value (it is faster than store from XMM register)
6199 instruct storeF0(memory mem, immF0 zero)
6200 %{
6201 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6202 match(Set mem (StoreF mem zero));
6203
6204 ins_cost(25); // XXX
6205 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6206 ins_encode %{
6207 __ movl($mem$$Address, r12);
6208 %}
6209 ins_pipe(ialu_mem_reg);
6210 %}
6211
6212 instruct storeF_imm(memory mem, immF src)
6213 %{
6214 match(Set mem (StoreF mem src));
6215
6216 ins_cost(50);
6217 format %{ "movl $mem, $src\t# float" %}
6218 opcode(0xC7); /* C7 /0 */
6219 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6220 ins_pipe(ialu_mem_imm);
6221 %}
6222
6223 // Store Double
6224 instruct storeD(memory mem, regD src)
6225 %{
6226 match(Set mem (StoreD mem src));
6227
6228 ins_cost(95); // XXX
6229 format %{ "movsd $mem, $src\t# double" %}
6230 ins_encode %{
6231 __ movdbl($mem$$Address, $src$$XMMRegister);
6232 %}
6233 ins_pipe(pipe_slow); // XXX
6234 %}
6235
6236 // Store immediate double 0.0 (it is faster than store from XMM register)
6237 instruct storeD0_imm(memory mem, immD0 src)
6238 %{
6239 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6240 match(Set mem (StoreD mem src));
6241
6242 ins_cost(50);
6243 format %{ "movq $mem, $src\t# double 0." %}
6244 opcode(0xC7); /* C7 /0 */
6245 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6246 ins_pipe(ialu_mem_imm);
6247 %}
6248
6249 instruct storeD0(memory mem, immD0 zero)
6250 %{
6251 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6252 match(Set mem (StoreD mem zero));
6253
6254 ins_cost(25); // XXX
6255 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6256 ins_encode %{
6257 __ movq($mem$$Address, r12);
6258 %}
6259 ins_pipe(ialu_mem_reg);
6260 %}
6261
6262 instruct storeSSI(stackSlotI dst, rRegI src)
6263 %{
6264 match(Set dst src);
6265
6266 ins_cost(100);
6267 format %{ "movl $dst, $src\t# int stk" %}
6268 opcode(0x89);
6269 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6270 ins_pipe( ialu_mem_reg );
6271 %}
6272
6273 instruct storeSSL(stackSlotL dst, rRegL src)
6274 %{
6275 match(Set dst src);
6276
6277 ins_cost(100);
6278 format %{ "movq $dst, $src\t# long stk" %}
6279 opcode(0x89);
6280 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6281 ins_pipe(ialu_mem_reg);
6282 %}
6283
6284 instruct storeSSP(stackSlotP dst, rRegP src)
6285 %{
6286 match(Set dst src);
6287
6288 ins_cost(100);
6289 format %{ "movq $dst, $src\t# ptr stk" %}
6290 opcode(0x89);
6291 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6292 ins_pipe(ialu_mem_reg);
6293 %}
6294
6295 instruct storeSSF(stackSlotF dst, regF src)
6296 %{
6297 match(Set dst src);
6298
6299 ins_cost(95); // XXX
6300 format %{ "movss $dst, $src\t# float stk" %}
6301 ins_encode %{
6302 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6303 %}
6304 ins_pipe(pipe_slow); // XXX
6305 %}
6306
6307 instruct storeSSD(stackSlotD dst, regD src)
6308 %{
6309 match(Set dst src);
6310
6311 ins_cost(95); // XXX
6312 format %{ "movsd $dst, $src\t# double stk" %}
6313 ins_encode %{
6314 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6315 %}
6316 ins_pipe(pipe_slow); // XXX
6317 %}
6318
6319 //----------BSWAP Instructions-------------------------------------------------
6320 instruct bytes_reverse_int(rRegI dst) %{
6321 match(Set dst (ReverseBytesI dst));
6322
6323 format %{ "bswapl $dst" %}
6324 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6325 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6326 ins_pipe( ialu_reg );
6327 %}
6328
6329 instruct bytes_reverse_long(rRegL dst) %{
6330 match(Set dst (ReverseBytesL dst));
6331
6332 format %{ "bswapq $dst" %}
6333 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6334 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6335 ins_pipe( ialu_reg);
6336 %}
6337
6338 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6339 match(Set dst (ReverseBytesUS dst));
6340 effect(KILL cr);
6341
6342 format %{ "bswapl $dst\n\t"
6343 "shrl $dst,16\n\t" %}
6344 ins_encode %{
6345 __ bswapl($dst$$Register);
6346 __ shrl($dst$$Register, 16);
6347 %}
6348 ins_pipe( ialu_reg );
6349 %}
6350
6351 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6352 match(Set dst (ReverseBytesS dst));
6353 effect(KILL cr);
6354
6355 format %{ "bswapl $dst\n\t"
6356 "sar $dst,16\n\t" %}
6357 ins_encode %{
6358 __ bswapl($dst$$Register);
6359 __ sarl($dst$$Register, 16);
6360 %}
6361 ins_pipe( ialu_reg );
6362 %}
6363
6364 //---------- Zeros Count Instructions ------------------------------------------
6365
6366 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6367 predicate(UseCountLeadingZerosInstruction);
6368 match(Set dst (CountLeadingZerosI src));
6369 effect(KILL cr);
6370
6371 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6372 ins_encode %{
6373 __ lzcntl($dst$$Register, $src$$Register);
6374 %}
6375 ins_pipe(ialu_reg);
6376 %}
6377
6378 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6379 predicate(!UseCountLeadingZerosInstruction);
6380 match(Set dst (CountLeadingZerosI src));
6381 effect(KILL cr);
6382
6383 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6384 "jnz skip\n\t"
6385 "movl $dst, -1\n"
6386 "skip:\n\t"
6387 "negl $dst\n\t"
6388 "addl $dst, 31" %}
6389 ins_encode %{
6390 Register Rdst = $dst$$Register;
6391 Register Rsrc = $src$$Register;
6392 Label skip;
6393 __ bsrl(Rdst, Rsrc);
6394 __ jccb(Assembler::notZero, skip);
6395 __ movl(Rdst, -1);
6396 __ bind(skip);
6397 __ negl(Rdst);
6398 __ addl(Rdst, BitsPerInt - 1);
6399 %}
6400 ins_pipe(ialu_reg);
6401 %}
6402
6403 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6404 predicate(UseCountLeadingZerosInstruction);
6405 match(Set dst (CountLeadingZerosL src));
6406 effect(KILL cr);
6407
6408 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6409 ins_encode %{
6410 __ lzcntq($dst$$Register, $src$$Register);
6411 %}
6412 ins_pipe(ialu_reg);
6413 %}
6414
6415 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6416 predicate(!UseCountLeadingZerosInstruction);
6417 match(Set dst (CountLeadingZerosL src));
6418 effect(KILL cr);
6419
6420 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6421 "jnz skip\n\t"
6422 "movl $dst, -1\n"
6423 "skip:\n\t"
6424 "negl $dst\n\t"
6425 "addl $dst, 63" %}
6426 ins_encode %{
6427 Register Rdst = $dst$$Register;
6428 Register Rsrc = $src$$Register;
6429 Label skip;
6430 __ bsrq(Rdst, Rsrc);
6431 __ jccb(Assembler::notZero, skip);
6432 __ movl(Rdst, -1);
6433 __ bind(skip);
6434 __ negl(Rdst);
6435 __ addl(Rdst, BitsPerLong - 1);
6436 %}
6437 ins_pipe(ialu_reg);
6438 %}
6439
6440 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6441 predicate(UseCountTrailingZerosInstruction);
6442 match(Set dst (CountTrailingZerosI src));
6443 effect(KILL cr);
6444
6445 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6446 ins_encode %{
6447 __ tzcntl($dst$$Register, $src$$Register);
6448 %}
6449 ins_pipe(ialu_reg);
6450 %}
6451
6452 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6453 predicate(!UseCountTrailingZerosInstruction);
6454 match(Set dst (CountTrailingZerosI src));
6455 effect(KILL cr);
6456
6457 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6458 "jnz done\n\t"
6459 "movl $dst, 32\n"
6460 "done:" %}
6461 ins_encode %{
6462 Register Rdst = $dst$$Register;
6463 Label done;
6464 __ bsfl(Rdst, $src$$Register);
6465 __ jccb(Assembler::notZero, done);
6466 __ movl(Rdst, BitsPerInt);
6467 __ bind(done);
6468 %}
6469 ins_pipe(ialu_reg);
6470 %}
6471
6472 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6473 predicate(UseCountTrailingZerosInstruction);
6474 match(Set dst (CountTrailingZerosL src));
6475 effect(KILL cr);
6476
6477 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6478 ins_encode %{
6479 __ tzcntq($dst$$Register, $src$$Register);
6480 %}
6481 ins_pipe(ialu_reg);
6482 %}
6483
6484 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6485 predicate(!UseCountTrailingZerosInstruction);
6486 match(Set dst (CountTrailingZerosL src));
6487 effect(KILL cr);
6488
6489 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6490 "jnz done\n\t"
6491 "movl $dst, 64\n"
6492 "done:" %}
6493 ins_encode %{
6494 Register Rdst = $dst$$Register;
6495 Label done;
6496 __ bsfq(Rdst, $src$$Register);
6497 __ jccb(Assembler::notZero, done);
6498 __ movl(Rdst, BitsPerLong);
6499 __ bind(done);
6500 %}
6501 ins_pipe(ialu_reg);
6502 %}
6503
6504
6505 //---------- Population Count Instructions -------------------------------------
6506
6507 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6508 predicate(UsePopCountInstruction);
6509 match(Set dst (PopCountI src));
6510 effect(KILL cr);
6511
6512 format %{ "popcnt $dst, $src" %}
6513 ins_encode %{
6514 __ popcntl($dst$$Register, $src$$Register);
6515 %}
6516 ins_pipe(ialu_reg);
6517 %}
6518
6519 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6520 predicate(UsePopCountInstruction);
6521 match(Set dst (PopCountI (LoadI mem)));
6522 effect(KILL cr);
6523
6524 format %{ "popcnt $dst, $mem" %}
6525 ins_encode %{
6526 __ popcntl($dst$$Register, $mem$$Address);
6527 %}
6528 ins_pipe(ialu_reg);
6529 %}
6530
6531 // Note: Long.bitCount(long) returns an int.
6532 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6533 predicate(UsePopCountInstruction);
6534 match(Set dst (PopCountL src));
6535 effect(KILL cr);
6536
6537 format %{ "popcnt $dst, $src" %}
6538 ins_encode %{
6539 __ popcntq($dst$$Register, $src$$Register);
6540 %}
6541 ins_pipe(ialu_reg);
6542 %}
6543
6544 // Note: Long.bitCount(long) returns an int.
6545 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6546 predicate(UsePopCountInstruction);
6547 match(Set dst (PopCountL (LoadL mem)));
6548 effect(KILL cr);
6549
6550 format %{ "popcnt $dst, $mem" %}
6551 ins_encode %{
6552 __ popcntq($dst$$Register, $mem$$Address);
6553 %}
6554 ins_pipe(ialu_reg);
6555 %}
6556
6557
6558 //----------MemBar Instructions-----------------------------------------------
6559 // Memory barrier flavors
6560
6561 instruct membar_acquire()
6562 %{
6563 match(MemBarAcquire);
6564 match(LoadFence);
6565 ins_cost(0);
6566
6567 size(0);
6568 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6569 ins_encode();
6570 ins_pipe(empty);
6571 %}
6572
6573 instruct membar_acquire_lock()
6574 %{
6575 match(MemBarAcquireLock);
6576 ins_cost(0);
6577
6578 size(0);
6579 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6580 ins_encode();
6581 ins_pipe(empty);
6582 %}
6583
6584 instruct membar_release()
6585 %{
6586 match(MemBarRelease);
6587 match(StoreFence);
6588 ins_cost(0);
6589
6590 size(0);
6591 format %{ "MEMBAR-release ! (empty encoding)" %}
6592 ins_encode();
6593 ins_pipe(empty);
6594 %}
6595
6596 instruct membar_release_lock()
6597 %{
6598 match(MemBarReleaseLock);
6599 ins_cost(0);
6600
6601 size(0);
6602 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6603 ins_encode();
6604 ins_pipe(empty);
6605 %}
6606
6607 instruct membar_volatile(rFlagsReg cr) %{
6608 match(MemBarVolatile);
6609 effect(KILL cr);
6610 ins_cost(400);
6611
6612 format %{
6613 $$template
6614 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6615 %}
6616 ins_encode %{
6617 __ membar(Assembler::StoreLoad);
6618 %}
6619 ins_pipe(pipe_slow);
6620 %}
6621
6622 instruct unnecessary_membar_volatile()
6623 %{
6624 match(MemBarVolatile);
6625 predicate(Matcher::post_store_load_barrier(n));
6626 ins_cost(0);
6627
6628 size(0);
6629 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6630 ins_encode();
6631 ins_pipe(empty);
6632 %}
6633
6634 instruct membar_storestore() %{
6635 match(MemBarStoreStore);
6636 ins_cost(0);
6637
6638 size(0);
6639 format %{ "MEMBAR-storestore (empty encoding)" %}
6640 ins_encode( );
6641 ins_pipe(empty);
6642 %}
6643
6644 //----------Move Instructions--------------------------------------------------
6645
6646 instruct castX2P(rRegP dst, rRegL src)
6647 %{
6648 match(Set dst (CastX2P src));
6649
6650 format %{ "movq $dst, $src\t# long->ptr" %}
6651 ins_encode %{
6652 if ($dst$$reg != $src$$reg) {
6653 __ movptr($dst$$Register, $src$$Register);
6654 }
6655 %}
6656 ins_pipe(ialu_reg_reg); // XXX
6657 %}
6658
6659 instruct castP2X(rRegL dst, rRegP src)
6660 %{
6661 match(Set dst (CastP2X src));
6662
6663 format %{ "movq $dst, $src\t# ptr -> long" %}
6664 ins_encode %{
6665 if ($dst$$reg != $src$$reg) {
6666 __ movptr($dst$$Register, $src$$Register);
6667 }
6668 %}
6669 ins_pipe(ialu_reg_reg); // XXX
6670 %}
6671
6672 // Convert oop into int for vectors alignment masking
6673 instruct convP2I(rRegI dst, rRegP src)
6674 %{
6675 match(Set dst (ConvL2I (CastP2X src)));
6676
6677 format %{ "movl $dst, $src\t# ptr -> int" %}
6678 ins_encode %{
6679 __ movl($dst$$Register, $src$$Register);
6680 %}
6681 ins_pipe(ialu_reg_reg); // XXX
6682 %}
6683
6684 // Convert compressed oop into int for vectors alignment masking
6685 // in case of 32bit oops (heap < 4Gb).
6686 instruct convN2I(rRegI dst, rRegN src)
6687 %{
6688 predicate(Universe::narrow_oop_shift() == 0);
6689 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6690
6691 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6692 ins_encode %{
6693 __ movl($dst$$Register, $src$$Register);
6694 %}
6695 ins_pipe(ialu_reg_reg); // XXX
6696 %}
6697
6698 instruct shenandoahRB(rRegP dst, rRegP src, rFlagsReg cr) %{
6699 match(Set dst (ShenandoahReadBarrier src));
6700 effect(DEF dst, USE src);
6701 ins_cost(125); // XXX
6702 format %{ "shenandoah_rb $dst, $src" %}
6703 ins_encode %{
6704 #if INCLUDE_SHENANDOAHGC
6705 Register d = $dst$$Register;
6706 Register s = $src$$Register;
6707 __ movptr(d, Address(s, ShenandoahBrooksPointer::byte_offset()));
6708 #else
6709 ShouldNotReachHere();
6710 #endif
6711 %}
6712 ins_pipe(ialu_reg_mem);
6713 %}
6714
6715 instruct shenandoahRBNarrow(rRegP dst, rRegN src) %{
6716 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == 0));
6717 match(Set dst (ShenandoahReadBarrier (DecodeN src)));
6718 effect(DEF dst, USE src);
6719 ins_cost(125); // XXX
6720 format %{ "shenandoah_rb $dst, $src" %}
6721 ins_encode %{
6722 #if INCLUDE_SHENANDOAHGC
6723 Register d = $dst$$Register;
6724 Register s = $src$$Register;
6725 __ movptr(d, Address(r12, s, Address::times_1, ShenandoahBrooksPointer::byte_offset()));
6726 #else
6727 ShouldNotReachHere();
6728 #endif
6729 %}
6730 ins_pipe(ialu_reg_mem);
6731 %}
6732
6733 instruct shenandoahRBNarrowShift(rRegP dst, rRegN src) %{
6734 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
6735 match(Set dst (ShenandoahReadBarrier (DecodeN src)));
6736 effect(DEF dst, USE src);
6737 ins_cost(125); // XXX
6738 format %{ "shenandoah_rb $dst, $src" %}
6739 ins_encode %{
6740 #if INCLUDE_SHENANDOAHGC
6741 Register d = $dst$$Register;
6742 Register s = $src$$Register;
6743 __ movptr(d, Address(r12, s, Address::times_8, ShenandoahBrooksPointer::byte_offset()));
6744 #else
6745 ShouldNotReachHere();
6746 #endif
6747 %}
6748 ins_pipe(ialu_reg_mem);
6749 %}
6750
6751 // Convert oop pointer into compressed form
6752 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6753 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6754 match(Set dst (EncodeP src));
6755 effect(KILL cr);
6756 format %{ "encode_heap_oop $dst,$src" %}
6757 ins_encode %{
6758 Register s = $src$$Register;
6759 Register d = $dst$$Register;
6760 if (s != d) {
6761 __ movq(d, s);
6762 }
6763 __ encode_heap_oop(d);
6764 %}
6765 ins_pipe(ialu_reg_long);
6766 %}
6767
6768 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6769 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6770 match(Set dst (EncodeP src));
6771 effect(KILL cr);
6772 format %{ "encode_heap_oop_not_null $dst,$src" %}
6773 ins_encode %{
6774 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6775 %}
6776 ins_pipe(ialu_reg_long);
6777 %}
6778
6779 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6780 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6781 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6782 match(Set dst (DecodeN src));
6783 effect(KILL cr);
6784 format %{ "decode_heap_oop $dst,$src" %}
6785 ins_encode %{
6786 Register s = $src$$Register;
6787 Register d = $dst$$Register;
6788 if (s != d) {
6789 __ movq(d, s);
6790 }
6791 __ decode_heap_oop(d);
6792 %}
6793 ins_pipe(ialu_reg_long);
6794 %}
6795
6796 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6797 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6798 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6799 match(Set dst (DecodeN src));
6800 effect(KILL cr);
6801 format %{ "decode_heap_oop_not_null $dst,$src" %}
6802 ins_encode %{
6803 Register s = $src$$Register;
6804 Register d = $dst$$Register;
6805 if (s != d) {
6806 __ decode_heap_oop_not_null(d, s);
6807 } else {
6808 __ decode_heap_oop_not_null(d);
6809 }
6810 %}
6811 ins_pipe(ialu_reg_long);
6812 %}
6813
6814 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6815 match(Set dst (EncodePKlass src));
6816 effect(KILL cr);
6817 format %{ "encode_klass_not_null $dst,$src" %}
6818 ins_encode %{
6819 __ encode_klass_not_null($dst$$Register, $src$$Register);
6820 %}
6821 ins_pipe(ialu_reg_long);
6822 %}
6823
6824 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6825 match(Set dst (DecodeNKlass src));
6826 effect(KILL cr);
6827 format %{ "decode_klass_not_null $dst,$src" %}
6828 ins_encode %{
6829 Register s = $src$$Register;
6830 Register d = $dst$$Register;
6831 if (s != d) {
6832 __ decode_klass_not_null(d, s);
6833 } else {
6834 __ decode_klass_not_null(d);
6835 }
6836 %}
6837 ins_pipe(ialu_reg_long);
6838 %}
6839
6840
6841 //----------Conditional Move---------------------------------------------------
6842 // Jump
6843 // dummy instruction for generating temp registers
6844 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6845 match(Jump (LShiftL switch_val shift));
6846 ins_cost(350);
6847 predicate(false);
6848 effect(TEMP dest);
6849
6850 format %{ "leaq $dest, [$constantaddress]\n\t"
6851 "jmp [$dest + $switch_val << $shift]\n\t" %}
6852 ins_encode %{
6853 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6854 // to do that and the compiler is using that register as one it can allocate.
6855 // So we build it all by hand.
6856 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6857 // ArrayAddress dispatch(table, index);
6858 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6859 __ lea($dest$$Register, $constantaddress);
6860 __ jmp(dispatch);
6861 %}
6862 ins_pipe(pipe_jmp);
6863 %}
6864
6865 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6866 match(Jump (AddL (LShiftL switch_val shift) offset));
6867 ins_cost(350);
6868 effect(TEMP dest);
6869
6870 format %{ "leaq $dest, [$constantaddress]\n\t"
6871 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6872 ins_encode %{
6873 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6874 // to do that and the compiler is using that register as one it can allocate.
6875 // So we build it all by hand.
6876 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6877 // ArrayAddress dispatch(table, index);
6878 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6879 __ lea($dest$$Register, $constantaddress);
6880 __ jmp(dispatch);
6881 %}
6882 ins_pipe(pipe_jmp);
6883 %}
6884
6885 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6886 match(Jump switch_val);
6887 ins_cost(350);
6888 effect(TEMP dest);
6889
6890 format %{ "leaq $dest, [$constantaddress]\n\t"
6891 "jmp [$dest + $switch_val]\n\t" %}
6892 ins_encode %{
6893 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6894 // to do that and the compiler is using that register as one it can allocate.
6895 // So we build it all by hand.
6896 // Address index(noreg, switch_reg, Address::times_1);
6897 // ArrayAddress dispatch(table, index);
6898 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6899 __ lea($dest$$Register, $constantaddress);
6900 __ jmp(dispatch);
6901 %}
6902 ins_pipe(pipe_jmp);
6903 %}
6904
6905 // Conditional move
6906 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6907 %{
6908 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6909
6910 ins_cost(200); // XXX
6911 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6912 opcode(0x0F, 0x40);
6913 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6914 ins_pipe(pipe_cmov_reg);
6915 %}
6916
6917 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6918 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6919
6920 ins_cost(200); // XXX
6921 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6922 opcode(0x0F, 0x40);
6923 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6924 ins_pipe(pipe_cmov_reg);
6925 %}
6926
6927 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6928 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6929 ins_cost(200);
6930 expand %{
6931 cmovI_regU(cop, cr, dst, src);
6932 %}
6933 %}
6934
6935 // Conditional move
6936 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6937 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6938
6939 ins_cost(250); // XXX
6940 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6941 opcode(0x0F, 0x40);
6942 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6943 ins_pipe(pipe_cmov_mem);
6944 %}
6945
6946 // Conditional move
6947 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6948 %{
6949 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6950
6951 ins_cost(250); // XXX
6952 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6953 opcode(0x0F, 0x40);
6954 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6955 ins_pipe(pipe_cmov_mem);
6956 %}
6957
6958 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6959 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6960 ins_cost(250);
6961 expand %{
6962 cmovI_memU(cop, cr, dst, src);
6963 %}
6964 %}
6965
6966 // Conditional move
6967 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6968 %{
6969 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6970
6971 ins_cost(200); // XXX
6972 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6973 opcode(0x0F, 0x40);
6974 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6975 ins_pipe(pipe_cmov_reg);
6976 %}
6977
6978 // Conditional move
6979 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6980 %{
6981 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6982
6983 ins_cost(200); // XXX
6984 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6985 opcode(0x0F, 0x40);
6986 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6987 ins_pipe(pipe_cmov_reg);
6988 %}
6989
6990 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6991 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6992 ins_cost(200);
6993 expand %{
6994 cmovN_regU(cop, cr, dst, src);
6995 %}
6996 %}
6997
6998 // Conditional move
6999 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7000 %{
7001 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7002
7003 ins_cost(200); // XXX
7004 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7005 opcode(0x0F, 0x40);
7006 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7007 ins_pipe(pipe_cmov_reg); // XXX
7008 %}
7009
7010 // Conditional move
7011 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7012 %{
7013 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7014
7015 ins_cost(200); // XXX
7016 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7017 opcode(0x0F, 0x40);
7018 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7019 ins_pipe(pipe_cmov_reg); // XXX
7020 %}
7021
7022 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7023 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7024 ins_cost(200);
7025 expand %{
7026 cmovP_regU(cop, cr, dst, src);
7027 %}
7028 %}
7029
7030 // DISABLED: Requires the ADLC to emit a bottom_type call that
7031 // correctly meets the two pointer arguments; one is an incoming
7032 // register but the other is a memory operand. ALSO appears to
7033 // be buggy with implicit null checks.
7034 //
7035 //// Conditional move
7036 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7037 //%{
7038 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7039 // ins_cost(250);
7040 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7041 // opcode(0x0F,0x40);
7042 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7043 // ins_pipe( pipe_cmov_mem );
7044 //%}
7045 //
7046 //// Conditional move
7047 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7048 //%{
7049 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7050 // ins_cost(250);
7051 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7052 // opcode(0x0F,0x40);
7053 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7054 // ins_pipe( pipe_cmov_mem );
7055 //%}
7056
7057 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7058 %{
7059 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7060
7061 ins_cost(200); // XXX
7062 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7063 opcode(0x0F, 0x40);
7064 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7065 ins_pipe(pipe_cmov_reg); // XXX
7066 %}
7067
7068 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7069 %{
7070 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7071
7072 ins_cost(200); // XXX
7073 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7074 opcode(0x0F, 0x40);
7075 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7076 ins_pipe(pipe_cmov_mem); // XXX
7077 %}
7078
7079 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7080 %{
7081 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7082
7083 ins_cost(200); // XXX
7084 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7085 opcode(0x0F, 0x40);
7086 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7087 ins_pipe(pipe_cmov_reg); // XXX
7088 %}
7089
7090 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7091 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7092 ins_cost(200);
7093 expand %{
7094 cmovL_regU(cop, cr, dst, src);
7095 %}
7096 %}
7097
7098 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7099 %{
7100 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7101
7102 ins_cost(200); // XXX
7103 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7104 opcode(0x0F, 0x40);
7105 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7106 ins_pipe(pipe_cmov_mem); // XXX
7107 %}
7108
7109 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7110 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7111 ins_cost(200);
7112 expand %{
7113 cmovL_memU(cop, cr, dst, src);
7114 %}
7115 %}
7116
7117 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7118 %{
7119 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7120
7121 ins_cost(200); // XXX
7122 format %{ "jn$cop skip\t# signed cmove float\n\t"
7123 "movss $dst, $src\n"
7124 "skip:" %}
7125 ins_encode %{
7126 Label Lskip;
7127 // Invert sense of branch from sense of CMOV
7128 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7129 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7130 __ bind(Lskip);
7131 %}
7132 ins_pipe(pipe_slow);
7133 %}
7134
7135 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7136 // %{
7137 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7138
7139 // ins_cost(200); // XXX
7140 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7141 // "movss $dst, $src\n"
7142 // "skip:" %}
7143 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7144 // ins_pipe(pipe_slow);
7145 // %}
7146
7147 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7148 %{
7149 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7150
7151 ins_cost(200); // XXX
7152 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7153 "movss $dst, $src\n"
7154 "skip:" %}
7155 ins_encode %{
7156 Label Lskip;
7157 // Invert sense of branch from sense of CMOV
7158 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7159 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7160 __ bind(Lskip);
7161 %}
7162 ins_pipe(pipe_slow);
7163 %}
7164
7165 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7166 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7167 ins_cost(200);
7168 expand %{
7169 cmovF_regU(cop, cr, dst, src);
7170 %}
7171 %}
7172
7173 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7174 %{
7175 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7176
7177 ins_cost(200); // XXX
7178 format %{ "jn$cop skip\t# signed cmove double\n\t"
7179 "movsd $dst, $src\n"
7180 "skip:" %}
7181 ins_encode %{
7182 Label Lskip;
7183 // Invert sense of branch from sense of CMOV
7184 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7185 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7186 __ bind(Lskip);
7187 %}
7188 ins_pipe(pipe_slow);
7189 %}
7190
7191 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7192 %{
7193 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7194
7195 ins_cost(200); // XXX
7196 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7197 "movsd $dst, $src\n"
7198 "skip:" %}
7199 ins_encode %{
7200 Label Lskip;
7201 // Invert sense of branch from sense of CMOV
7202 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7203 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7204 __ bind(Lskip);
7205 %}
7206 ins_pipe(pipe_slow);
7207 %}
7208
7209 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7210 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7211 ins_cost(200);
7212 expand %{
7213 cmovD_regU(cop, cr, dst, src);
7214 %}
7215 %}
7216
7217 //----------Arithmetic Instructions--------------------------------------------
7218 //----------Addition Instructions----------------------------------------------
7219
7220 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7221 %{
7222 match(Set dst (AddI dst src));
7223 effect(KILL cr);
7224
7225 format %{ "addl $dst, $src\t# int" %}
7226 opcode(0x03);
7227 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7228 ins_pipe(ialu_reg_reg);
7229 %}
7230
7231 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7232 %{
7233 match(Set dst (AddI dst src));
7234 effect(KILL cr);
7235
7236 format %{ "addl $dst, $src\t# int" %}
7237 opcode(0x81, 0x00); /* /0 id */
7238 ins_encode(OpcSErm(dst, src), Con8or32(src));
7239 ins_pipe( ialu_reg );
7240 %}
7241
7242 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7243 %{
7244 match(Set dst (AddI dst (LoadI src)));
7245 effect(KILL cr);
7246
7247 ins_cost(125); // XXX
7248 format %{ "addl $dst, $src\t# int" %}
7249 opcode(0x03);
7250 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7251 ins_pipe(ialu_reg_mem);
7252 %}
7253
7254 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7255 %{
7256 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7257 effect(KILL cr);
7258
7259 ins_cost(150); // XXX
7260 format %{ "addl $dst, $src\t# int" %}
7261 opcode(0x01); /* Opcode 01 /r */
7262 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7263 ins_pipe(ialu_mem_reg);
7264 %}
7265
7266 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7267 %{
7268 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7269 effect(KILL cr);
7270
7271 ins_cost(125); // XXX
7272 format %{ "addl $dst, $src\t# int" %}
7273 opcode(0x81); /* Opcode 81 /0 id */
7274 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7275 ins_pipe(ialu_mem_imm);
7276 %}
7277
7278 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7279 %{
7280 predicate(UseIncDec);
7281 match(Set dst (AddI dst src));
7282 effect(KILL cr);
7283
7284 format %{ "incl $dst\t# int" %}
7285 opcode(0xFF, 0x00); // FF /0
7286 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7287 ins_pipe(ialu_reg);
7288 %}
7289
7290 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7291 %{
7292 predicate(UseIncDec);
7293 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7294 effect(KILL cr);
7295
7296 ins_cost(125); // XXX
7297 format %{ "incl $dst\t# int" %}
7298 opcode(0xFF); /* Opcode FF /0 */
7299 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7300 ins_pipe(ialu_mem_imm);
7301 %}
7302
7303 // XXX why does that use AddI
7304 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7305 %{
7306 predicate(UseIncDec);
7307 match(Set dst (AddI dst src));
7308 effect(KILL cr);
7309
7310 format %{ "decl $dst\t# int" %}
7311 opcode(0xFF, 0x01); // FF /1
7312 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7313 ins_pipe(ialu_reg);
7314 %}
7315
7316 // XXX why does that use AddI
7317 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7318 %{
7319 predicate(UseIncDec);
7320 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7321 effect(KILL cr);
7322
7323 ins_cost(125); // XXX
7324 format %{ "decl $dst\t# int" %}
7325 opcode(0xFF); /* Opcode FF /1 */
7326 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7327 ins_pipe(ialu_mem_imm);
7328 %}
7329
7330 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7331 %{
7332 match(Set dst (AddI src0 src1));
7333
7334 ins_cost(110);
7335 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7336 opcode(0x8D); /* 0x8D /r */
7337 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7338 ins_pipe(ialu_reg_reg);
7339 %}
7340
7341 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7342 %{
7343 match(Set dst (AddL dst src));
7344 effect(KILL cr);
7345
7346 format %{ "addq $dst, $src\t# long" %}
7347 opcode(0x03);
7348 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7349 ins_pipe(ialu_reg_reg);
7350 %}
7351
7352 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7353 %{
7354 match(Set dst (AddL dst src));
7355 effect(KILL cr);
7356
7357 format %{ "addq $dst, $src\t# long" %}
7358 opcode(0x81, 0x00); /* /0 id */
7359 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7360 ins_pipe( ialu_reg );
7361 %}
7362
7363 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7364 %{
7365 match(Set dst (AddL dst (LoadL src)));
7366 effect(KILL cr);
7367
7368 ins_cost(125); // XXX
7369 format %{ "addq $dst, $src\t# long" %}
7370 opcode(0x03);
7371 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7372 ins_pipe(ialu_reg_mem);
7373 %}
7374
7375 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7376 %{
7377 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7378 effect(KILL cr);
7379
7380 ins_cost(150); // XXX
7381 format %{ "addq $dst, $src\t# long" %}
7382 opcode(0x01); /* Opcode 01 /r */
7383 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7384 ins_pipe(ialu_mem_reg);
7385 %}
7386
7387 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7388 %{
7389 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7390 effect(KILL cr);
7391
7392 ins_cost(125); // XXX
7393 format %{ "addq $dst, $src\t# long" %}
7394 opcode(0x81); /* Opcode 81 /0 id */
7395 ins_encode(REX_mem_wide(dst),
7396 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7397 ins_pipe(ialu_mem_imm);
7398 %}
7399
7400 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7401 %{
7402 predicate(UseIncDec);
7403 match(Set dst (AddL dst src));
7404 effect(KILL cr);
7405
7406 format %{ "incq $dst\t# long" %}
7407 opcode(0xFF, 0x00); // FF /0
7408 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7409 ins_pipe(ialu_reg);
7410 %}
7411
7412 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7413 %{
7414 predicate(UseIncDec);
7415 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7416 effect(KILL cr);
7417
7418 ins_cost(125); // XXX
7419 format %{ "incq $dst\t# long" %}
7420 opcode(0xFF); /* Opcode FF /0 */
7421 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7422 ins_pipe(ialu_mem_imm);
7423 %}
7424
7425 // XXX why does that use AddL
7426 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7427 %{
7428 predicate(UseIncDec);
7429 match(Set dst (AddL dst src));
7430 effect(KILL cr);
7431
7432 format %{ "decq $dst\t# long" %}
7433 opcode(0xFF, 0x01); // FF /1
7434 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7435 ins_pipe(ialu_reg);
7436 %}
7437
7438 // XXX why does that use AddL
7439 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7440 %{
7441 predicate(UseIncDec);
7442 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7443 effect(KILL cr);
7444
7445 ins_cost(125); // XXX
7446 format %{ "decq $dst\t# long" %}
7447 opcode(0xFF); /* Opcode FF /1 */
7448 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7449 ins_pipe(ialu_mem_imm);
7450 %}
7451
7452 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7453 %{
7454 match(Set dst (AddL src0 src1));
7455
7456 ins_cost(110);
7457 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7458 opcode(0x8D); /* 0x8D /r */
7459 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7460 ins_pipe(ialu_reg_reg);
7461 %}
7462
7463 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7464 %{
7465 match(Set dst (AddP dst src));
7466 effect(KILL cr);
7467
7468 format %{ "addq $dst, $src\t# ptr" %}
7469 opcode(0x03);
7470 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7471 ins_pipe(ialu_reg_reg);
7472 %}
7473
7474 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7475 %{
7476 match(Set dst (AddP dst src));
7477 effect(KILL cr);
7478
7479 format %{ "addq $dst, $src\t# ptr" %}
7480 opcode(0x81, 0x00); /* /0 id */
7481 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7482 ins_pipe( ialu_reg );
7483 %}
7484
7485 // XXX addP mem ops ????
7486
7487 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7488 %{
7489 match(Set dst (AddP src0 src1));
7490
7491 ins_cost(110);
7492 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7493 opcode(0x8D); /* 0x8D /r */
7494 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7495 ins_pipe(ialu_reg_reg);
7496 %}
7497
7498 instruct checkCastPP(rRegP dst)
7499 %{
7500 match(Set dst (CheckCastPP dst));
7501
7502 size(0);
7503 format %{ "# checkcastPP of $dst" %}
7504 ins_encode(/* empty encoding */);
7505 ins_pipe(empty);
7506 %}
7507
7508 instruct castPP(rRegP dst)
7509 %{
7510 match(Set dst (CastPP dst));
7511
7512 size(0);
7513 format %{ "# castPP of $dst" %}
7514 ins_encode(/* empty encoding */);
7515 ins_pipe(empty);
7516 %}
7517
7518 instruct castII(rRegI dst)
7519 %{
7520 match(Set dst (CastII dst));
7521
7522 size(0);
7523 format %{ "# castII of $dst" %}
7524 ins_encode(/* empty encoding */);
7525 ins_cost(0);
7526 ins_pipe(empty);
7527 %}
7528
7529 // LoadP-locked same as a regular LoadP when used with compare-swap
7530 instruct loadPLocked(rRegP dst, memory mem)
7531 %{
7532 match(Set dst (LoadPLocked mem));
7533
7534 ins_cost(125); // XXX
7535 format %{ "movq $dst, $mem\t# ptr locked" %}
7536 opcode(0x8B);
7537 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7538 ins_pipe(ialu_reg_mem); // XXX
7539 %}
7540
7541 // Conditional-store of the updated heap-top.
7542 // Used during allocation of the shared heap.
7543 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7544
7545 instruct storePConditional(memory heap_top_ptr,
7546 rax_RegP oldval, rRegP newval,
7547 rFlagsReg cr)
7548 %{
7549 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7550
7551 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7552 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7553 opcode(0x0F, 0xB1);
7554 ins_encode(lock_prefix,
7555 REX_reg_mem_wide(newval, heap_top_ptr),
7556 OpcP, OpcS,
7557 reg_mem(newval, heap_top_ptr));
7558 ins_pipe(pipe_cmpxchg);
7559 %}
7560
7561 // Conditional-store of an int value.
7562 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7563 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7564 %{
7565 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7566 effect(KILL oldval);
7567
7568 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7569 opcode(0x0F, 0xB1);
7570 ins_encode(lock_prefix,
7571 REX_reg_mem(newval, mem),
7572 OpcP, OpcS,
7573 reg_mem(newval, mem));
7574 ins_pipe(pipe_cmpxchg);
7575 %}
7576
7577 // Conditional-store of a long value.
7578 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7579 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7580 %{
7581 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7582 effect(KILL oldval);
7583
7584 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7585 opcode(0x0F, 0xB1);
7586 ins_encode(lock_prefix,
7587 REX_reg_mem_wide(newval, mem),
7588 OpcP, OpcS,
7589 reg_mem(newval, mem));
7590 ins_pipe(pipe_cmpxchg);
7591 %}
7592
7593
7594 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7595 instruct compareAndSwapP(rRegI res,
7596 memory mem_ptr,
7597 rax_RegP oldval, rRegP newval,
7598 rFlagsReg cr)
7599 %{
7600 predicate(VM_Version::supports_cx8());
7601 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7602 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7603 effect(KILL cr, KILL oldval);
7604
7605 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7606 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7607 "sete $res\n\t"
7608 "movzbl $res, $res" %}
7609 opcode(0x0F, 0xB1);
7610 ins_encode(lock_prefix,
7611 REX_reg_mem_wide(newval, mem_ptr),
7612 OpcP, OpcS,
7613 reg_mem(newval, mem_ptr),
7614 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7615 REX_reg_breg(res, res), // movzbl
7616 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7617 ins_pipe( pipe_cmpxchg );
7618 %}
7619
7620 instruct compareAndSwapP_shenandoah(rRegI res,
7621 memory mem_ptr,
7622 rRegP tmp1, rRegP tmp2,
7623 rax_RegP oldval, rRegP newval,
7624 rFlagsReg cr)
7625 %{
7626 predicate(VM_Version::supports_cx8());
7627 match(Set res (ShenandoahCompareAndSwapP mem_ptr (Binary oldval newval)));
7628 match(Set res (ShenandoahWeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7629 effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval);
7630
7631 format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7632
7633 ins_encode %{
7634 #if INCLUDE_SHENANDOAHGC
7635 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
7636 $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7637 false, // swap
7638 false, $tmp1$$Register, $tmp2$$Register
7639 );
7640 #else
7641 ShouldNotReachHere();
7642 #endif
7643 %}
7644 ins_pipe( pipe_cmpxchg );
7645 %}
7646
7647 instruct compareAndSwapL(rRegI res,
7648 memory mem_ptr,
7649 rax_RegL oldval, rRegL newval,
7650 rFlagsReg cr)
7651 %{
7652 predicate(VM_Version::supports_cx8());
7653 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7654 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7655 effect(KILL cr, KILL oldval);
7656
7657 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7658 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7659 "sete $res\n\t"
7660 "movzbl $res, $res" %}
7661 opcode(0x0F, 0xB1);
7662 ins_encode(lock_prefix,
7663 REX_reg_mem_wide(newval, mem_ptr),
7664 OpcP, OpcS,
7665 reg_mem(newval, mem_ptr),
7666 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7667 REX_reg_breg(res, res), // movzbl
7668 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7669 ins_pipe( pipe_cmpxchg );
7670 %}
7671
7672 instruct compareAndSwapI(rRegI res,
7673 memory mem_ptr,
7674 rax_RegI oldval, rRegI newval,
7675 rFlagsReg cr)
7676 %{
7677 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7678 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7679 effect(KILL cr, KILL oldval);
7680
7681 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7682 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7683 "sete $res\n\t"
7684 "movzbl $res, $res" %}
7685 opcode(0x0F, 0xB1);
7686 ins_encode(lock_prefix,
7687 REX_reg_mem(newval, mem_ptr),
7688 OpcP, OpcS,
7689 reg_mem(newval, mem_ptr),
7690 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7691 REX_reg_breg(res, res), // movzbl
7692 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7693 ins_pipe( pipe_cmpxchg );
7694 %}
7695
7696 instruct compareAndSwapB(rRegI res,
7697 memory mem_ptr,
7698 rax_RegI oldval, rRegI newval,
7699 rFlagsReg cr)
7700 %{
7701 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7702 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7703 effect(KILL cr, KILL oldval);
7704
7705 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7706 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7707 "sete $res\n\t"
7708 "movzbl $res, $res" %}
7709 opcode(0x0F, 0xB0);
7710 ins_encode(lock_prefix,
7711 REX_breg_mem(newval, mem_ptr),
7712 OpcP, OpcS,
7713 reg_mem(newval, mem_ptr),
7714 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7715 REX_reg_breg(res, res), // movzbl
7716 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7717 ins_pipe( pipe_cmpxchg );
7718 %}
7719
7720 instruct compareAndSwapS(rRegI res,
7721 memory mem_ptr,
7722 rax_RegI oldval, rRegI newval,
7723 rFlagsReg cr)
7724 %{
7725 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7726 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7727 effect(KILL cr, KILL oldval);
7728
7729 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7730 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7731 "sete $res\n\t"
7732 "movzbl $res, $res" %}
7733 opcode(0x0F, 0xB1);
7734 ins_encode(lock_prefix,
7735 SizePrefix,
7736 REX_reg_mem(newval, mem_ptr),
7737 OpcP, OpcS,
7738 reg_mem(newval, mem_ptr),
7739 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7740 REX_reg_breg(res, res), // movzbl
7741 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7742 ins_pipe( pipe_cmpxchg );
7743 %}
7744
7745 instruct compareAndSwapN(rRegI res,
7746 memory mem_ptr,
7747 rax_RegN oldval, rRegN newval,
7748 rFlagsReg cr) %{
7749 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7750 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7751 effect(KILL cr, KILL oldval);
7752
7753 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7754 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7755 "sete $res\n\t"
7756 "movzbl $res, $res" %}
7757 opcode(0x0F, 0xB1);
7758 ins_encode(lock_prefix,
7759 REX_reg_mem(newval, mem_ptr),
7760 OpcP, OpcS,
7761 reg_mem(newval, mem_ptr),
7762 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7763 REX_reg_breg(res, res), // movzbl
7764 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7765 ins_pipe( pipe_cmpxchg );
7766 %}
7767
7768 instruct compareAndSwapN_shenandoah(rRegI res,
7769 memory mem_ptr,
7770 rRegP tmp1, rRegP tmp2,
7771 rax_RegN oldval, rRegN newval,
7772 rFlagsReg cr) %{
7773 match(Set res (ShenandoahCompareAndSwapN mem_ptr (Binary oldval newval)));
7774 match(Set res (ShenandoahWeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7775 effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval);
7776
7777 format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7778
7779 ins_encode %{
7780 #if INCLUDE_SHENANDOAHGC
7781 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
7782 $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7783 false, // swap
7784 false, $tmp1$$Register, $tmp2$$Register
7785 );
7786 #else
7787 ShouldNotReachHere();
7788 #endif
7789 %}
7790 ins_pipe( pipe_cmpxchg );
7791 %}
7792
7793 instruct compareAndExchangeB(
7794 memory mem_ptr,
7795 rax_RegI oldval, rRegI newval,
7796 rFlagsReg cr)
7797 %{
7798 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7799 effect(KILL cr);
7800
7801 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7802 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7803 opcode(0x0F, 0xB0);
7804 ins_encode(lock_prefix,
7805 REX_breg_mem(newval, mem_ptr),
7806 OpcP, OpcS,
7807 reg_mem(newval, mem_ptr) // lock cmpxchg
7808 );
7809 ins_pipe( pipe_cmpxchg );
7810 %}
7811
7812 instruct compareAndExchangeS(
7813 memory mem_ptr,
7814 rax_RegI oldval, rRegI newval,
7815 rFlagsReg cr)
7816 %{
7817 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7818 effect(KILL cr);
7819
7820 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7821 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7822 opcode(0x0F, 0xB1);
7823 ins_encode(lock_prefix,
7824 SizePrefix,
7825 REX_reg_mem(newval, mem_ptr),
7826 OpcP, OpcS,
7827 reg_mem(newval, mem_ptr) // lock cmpxchg
7828 );
7829 ins_pipe( pipe_cmpxchg );
7830 %}
7831
7832 instruct compareAndExchangeI(
7833 memory mem_ptr,
7834 rax_RegI oldval, rRegI newval,
7835 rFlagsReg cr)
7836 %{
7837 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7838 effect(KILL cr);
7839
7840 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7841 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7842 opcode(0x0F, 0xB1);
7843 ins_encode(lock_prefix,
7844 REX_reg_mem(newval, mem_ptr),
7845 OpcP, OpcS,
7846 reg_mem(newval, mem_ptr) // lock cmpxchg
7847 );
7848 ins_pipe( pipe_cmpxchg );
7849 %}
7850
7851 instruct compareAndExchangeL(
7852 memory mem_ptr,
7853 rax_RegL oldval, rRegL newval,
7854 rFlagsReg cr)
7855 %{
7856 predicate(VM_Version::supports_cx8());
7857 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7858 effect(KILL cr);
7859
7860 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7861 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7862 opcode(0x0F, 0xB1);
7863 ins_encode(lock_prefix,
7864 REX_reg_mem_wide(newval, mem_ptr),
7865 OpcP, OpcS,
7866 reg_mem(newval, mem_ptr) // lock cmpxchg
7867 );
7868 ins_pipe( pipe_cmpxchg );
7869 %}
7870
7871 instruct compareAndExchangeN(
7872 memory mem_ptr,
7873 rax_RegN oldval, rRegN newval,
7874 rFlagsReg cr) %{
7875 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7876 effect(KILL cr);
7877
7878 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7879 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7880 opcode(0x0F, 0xB1);
7881 ins_encode(lock_prefix,
7882 REX_reg_mem(newval, mem_ptr),
7883 OpcP, OpcS,
7884 reg_mem(newval, mem_ptr) // lock cmpxchg
7885 );
7886 ins_pipe( pipe_cmpxchg );
7887 %}
7888
7889 instruct compareAndExchangeN_shenandoah(memory mem_ptr,
7890 rax_RegN oldval, rRegN newval,
7891 rRegP tmp1, rRegP tmp2,
7892 rFlagsReg cr) %{
7893 match(Set oldval (ShenandoahCompareAndExchangeN mem_ptr (Binary oldval newval)));
7894 effect(TEMP tmp1, TEMP tmp2, KILL cr);
7895
7896 format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7897
7898 ins_encode %{
7899 #if INCLUDE_SHENANDOAHGC
7900 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
7901 NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7902 true, // exchange
7903 false, $tmp1$$Register, $tmp2$$Register
7904 );
7905 #else
7906 ShouldNotReachHere();
7907 #endif
7908 %}
7909 ins_pipe( pipe_cmpxchg );
7910 %}
7911
7912 instruct compareAndExchangeP(
7913 memory mem_ptr,
7914 rax_RegP oldval, rRegP newval,
7915 rFlagsReg cr)
7916 %{
7917 predicate(VM_Version::supports_cx8());
7918 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7919 effect(KILL cr);
7920
7921 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7922 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7923 opcode(0x0F, 0xB1);
7924 ins_encode(lock_prefix,
7925 REX_reg_mem_wide(newval, mem_ptr),
7926 OpcP, OpcS,
7927 reg_mem(newval, mem_ptr) // lock cmpxchg
7928 );
7929 ins_pipe( pipe_cmpxchg );
7930 %}
7931
7932 instruct compareAndExchangeP_shenandoah(memory mem_ptr,
7933 rax_RegP oldval, rRegP newval,
7934 rRegP tmp1, rRegP tmp2,
7935 rFlagsReg cr)
7936 %{
7937 predicate(VM_Version::supports_cx8());
7938 match(Set oldval (ShenandoahCompareAndExchangeP mem_ptr (Binary oldval newval)));
7939 effect(KILL cr, TEMP tmp1, TEMP tmp2);
7940 ins_cost(1000);
7941
7942 format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7943
7944 ins_encode %{
7945 #if INCLUDE_SHENANDOAHGC
7946 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
7947 NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7948 true, // exchange
7949 false, $tmp1$$Register, $tmp2$$Register
7950 );
7951 #else
7952 ShouldNotReachHere();
7953 #endif
7954 %}
7955 ins_pipe( pipe_cmpxchg );
7956 %}
7957
7958 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7959 predicate(n->as_LoadStore()->result_not_used());
7960 match(Set dummy (GetAndAddB mem add));
7961 effect(KILL cr);
7962 format %{ "ADDB [$mem],$add" %}
7963 ins_encode %{
7964 __ lock();
7965 __ addb($mem$$Address, $add$$constant);
7966 %}
7967 ins_pipe( pipe_cmpxchg );
7968 %}
7969
7970 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7971 match(Set newval (GetAndAddB mem newval));
7972 effect(KILL cr);
7973 format %{ "XADDB [$mem],$newval" %}
7974 ins_encode %{
7975 __ lock();
7976 __ xaddb($mem$$Address, $newval$$Register);
7977 %}
7978 ins_pipe( pipe_cmpxchg );
7979 %}
7980
7981 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7982 predicate(n->as_LoadStore()->result_not_used());
7983 match(Set dummy (GetAndAddS mem add));
7984 effect(KILL cr);
7985 format %{ "ADDW [$mem],$add" %}
7986 ins_encode %{
7987 __ lock();
7988 __ addw($mem$$Address, $add$$constant);
7989 %}
7990 ins_pipe( pipe_cmpxchg );
7991 %}
7992
7993 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7994 match(Set newval (GetAndAddS mem newval));
7995 effect(KILL cr);
7996 format %{ "XADDW [$mem],$newval" %}
7997 ins_encode %{
7998 __ lock();
7999 __ xaddw($mem$$Address, $newval$$Register);
8000 %}
8001 ins_pipe( pipe_cmpxchg );
8002 %}
8003
8004 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8005 predicate(n->as_LoadStore()->result_not_used());
8006 match(Set dummy (GetAndAddI mem add));
8007 effect(KILL cr);
8008 format %{ "ADDL [$mem],$add" %}
8009 ins_encode %{
8010 __ lock();
8011 __ addl($mem$$Address, $add$$constant);
8012 %}
8013 ins_pipe( pipe_cmpxchg );
8014 %}
8015
8016 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8017 match(Set newval (GetAndAddI mem newval));
8018 effect(KILL cr);
8019 format %{ "XADDL [$mem],$newval" %}
8020 ins_encode %{
8021 __ lock();
8022 __ xaddl($mem$$Address, $newval$$Register);
8023 %}
8024 ins_pipe( pipe_cmpxchg );
8025 %}
8026
8027 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8028 predicate(n->as_LoadStore()->result_not_used());
8029 match(Set dummy (GetAndAddL mem add));
8030 effect(KILL cr);
8031 format %{ "ADDQ [$mem],$add" %}
8032 ins_encode %{
8033 __ lock();
8034 __ addq($mem$$Address, $add$$constant);
8035 %}
8036 ins_pipe( pipe_cmpxchg );
8037 %}
8038
8039 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8040 match(Set newval (GetAndAddL mem newval));
8041 effect(KILL cr);
8042 format %{ "XADDQ [$mem],$newval" %}
8043 ins_encode %{
8044 __ lock();
8045 __ xaddq($mem$$Address, $newval$$Register);
8046 %}
8047 ins_pipe( pipe_cmpxchg );
8048 %}
8049
8050 instruct xchgB( memory mem, rRegI newval) %{
8051 match(Set newval (GetAndSetB mem newval));
8052 format %{ "XCHGB $newval,[$mem]" %}
8053 ins_encode %{
8054 __ xchgb($newval$$Register, $mem$$Address);
8055 %}
8056 ins_pipe( pipe_cmpxchg );
8057 %}
8058
8059 instruct xchgS( memory mem, rRegI newval) %{
8060 match(Set newval (GetAndSetS mem newval));
8061 format %{ "XCHGW $newval,[$mem]" %}
8062 ins_encode %{
8063 __ xchgw($newval$$Register, $mem$$Address);
8064 %}
8065 ins_pipe( pipe_cmpxchg );
8066 %}
8067
8068 instruct xchgI( memory mem, rRegI newval) %{
8069 match(Set newval (GetAndSetI mem newval));
8070 format %{ "XCHGL $newval,[$mem]" %}
8071 ins_encode %{
8072 __ xchgl($newval$$Register, $mem$$Address);
8073 %}
8074 ins_pipe( pipe_cmpxchg );
8075 %}
8076
8077 instruct xchgL( memory mem, rRegL newval) %{
8078 match(Set newval (GetAndSetL mem newval));
8079 format %{ "XCHGL $newval,[$mem]" %}
8080 ins_encode %{
8081 __ xchgq($newval$$Register, $mem$$Address);
8082 %}
8083 ins_pipe( pipe_cmpxchg );
8084 %}
8085
8086 instruct xchgP( memory mem, rRegP newval) %{
8087 match(Set newval (GetAndSetP mem newval));
8088 format %{ "XCHGQ $newval,[$mem]" %}
8089 ins_encode %{
8090 __ xchgq($newval$$Register, $mem$$Address);
8091 %}
8092 ins_pipe( pipe_cmpxchg );
8093 %}
8094
8095 instruct xchgN( memory mem, rRegN newval) %{
8096 match(Set newval (GetAndSetN mem newval));
8097 format %{ "XCHGL $newval,$mem]" %}
8098 ins_encode %{
8099 __ xchgl($newval$$Register, $mem$$Address);
8100 %}
8101 ins_pipe( pipe_cmpxchg );
8102 %}
8103
8104 //----------Subtraction Instructions-------------------------------------------
8105
8106 // Integer Subtraction Instructions
8107 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8108 %{
8109 match(Set dst (SubI dst src));
8110 effect(KILL cr);
8111
8112 format %{ "subl $dst, $src\t# int" %}
8113 opcode(0x2B);
8114 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8115 ins_pipe(ialu_reg_reg);
8116 %}
8117
8118 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8119 %{
8120 match(Set dst (SubI dst src));
8121 effect(KILL cr);
8122
8123 format %{ "subl $dst, $src\t# int" %}
8124 opcode(0x81, 0x05); /* Opcode 81 /5 */
8125 ins_encode(OpcSErm(dst, src), Con8or32(src));
8126 ins_pipe(ialu_reg);
8127 %}
8128
8129 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8130 %{
8131 match(Set dst (SubI dst (LoadI src)));
8132 effect(KILL cr);
8133
8134 ins_cost(125);
8135 format %{ "subl $dst, $src\t# int" %}
8136 opcode(0x2B);
8137 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8138 ins_pipe(ialu_reg_mem);
8139 %}
8140
8141 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8142 %{
8143 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8144 effect(KILL cr);
8145
8146 ins_cost(150);
8147 format %{ "subl $dst, $src\t# int" %}
8148 opcode(0x29); /* Opcode 29 /r */
8149 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8150 ins_pipe(ialu_mem_reg);
8151 %}
8152
8153 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8154 %{
8155 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8156 effect(KILL cr);
8157
8158 ins_cost(125); // XXX
8159 format %{ "subl $dst, $src\t# int" %}
8160 opcode(0x81); /* Opcode 81 /5 id */
8161 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8162 ins_pipe(ialu_mem_imm);
8163 %}
8164
8165 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8166 %{
8167 match(Set dst (SubL dst src));
8168 effect(KILL cr);
8169
8170 format %{ "subq $dst, $src\t# long" %}
8171 opcode(0x2B);
8172 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8173 ins_pipe(ialu_reg_reg);
8174 %}
8175
8176 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8177 %{
8178 match(Set dst (SubL dst src));
8179 effect(KILL cr);
8180
8181 format %{ "subq $dst, $src\t# long" %}
8182 opcode(0x81, 0x05); /* Opcode 81 /5 */
8183 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8184 ins_pipe(ialu_reg);
8185 %}
8186
8187 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8188 %{
8189 match(Set dst (SubL dst (LoadL src)));
8190 effect(KILL cr);
8191
8192 ins_cost(125);
8193 format %{ "subq $dst, $src\t# long" %}
8194 opcode(0x2B);
8195 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8196 ins_pipe(ialu_reg_mem);
8197 %}
8198
8199 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8200 %{
8201 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8202 effect(KILL cr);
8203
8204 ins_cost(150);
8205 format %{ "subq $dst, $src\t# long" %}
8206 opcode(0x29); /* Opcode 29 /r */
8207 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8208 ins_pipe(ialu_mem_reg);
8209 %}
8210
8211 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8212 %{
8213 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8214 effect(KILL cr);
8215
8216 ins_cost(125); // XXX
8217 format %{ "subq $dst, $src\t# long" %}
8218 opcode(0x81); /* Opcode 81 /5 id */
8219 ins_encode(REX_mem_wide(dst),
8220 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8221 ins_pipe(ialu_mem_imm);
8222 %}
8223
8224 // Subtract from a pointer
8225 // XXX hmpf???
8226 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8227 %{
8228 match(Set dst (AddP dst (SubI zero src)));
8229 effect(KILL cr);
8230
8231 format %{ "subq $dst, $src\t# ptr - int" %}
8232 opcode(0x2B);
8233 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8234 ins_pipe(ialu_reg_reg);
8235 %}
8236
8237 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8238 %{
8239 match(Set dst (SubI zero dst));
8240 effect(KILL cr);
8241
8242 format %{ "negl $dst\t# int" %}
8243 opcode(0xF7, 0x03); // Opcode F7 /3
8244 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8245 ins_pipe(ialu_reg);
8246 %}
8247
8248 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8249 %{
8250 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8251 effect(KILL cr);
8252
8253 format %{ "negl $dst\t# int" %}
8254 opcode(0xF7, 0x03); // Opcode F7 /3
8255 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8256 ins_pipe(ialu_reg);
8257 %}
8258
8259 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8260 %{
8261 match(Set dst (SubL zero dst));
8262 effect(KILL cr);
8263
8264 format %{ "negq $dst\t# long" %}
8265 opcode(0xF7, 0x03); // Opcode F7 /3
8266 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8267 ins_pipe(ialu_reg);
8268 %}
8269
8270 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8271 %{
8272 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8273 effect(KILL cr);
8274
8275 format %{ "negq $dst\t# long" %}
8276 opcode(0xF7, 0x03); // Opcode F7 /3
8277 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8278 ins_pipe(ialu_reg);
8279 %}
8280
8281 //----------Multiplication/Division Instructions-------------------------------
8282 // Integer Multiplication Instructions
8283 // Multiply Register
8284
8285 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8286 %{
8287 match(Set dst (MulI dst src));
8288 effect(KILL cr);
8289
8290 ins_cost(300);
8291 format %{ "imull $dst, $src\t# int" %}
8292 opcode(0x0F, 0xAF);
8293 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8294 ins_pipe(ialu_reg_reg_alu0);
8295 %}
8296
8297 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8298 %{
8299 match(Set dst (MulI src imm));
8300 effect(KILL cr);
8301
8302 ins_cost(300);
8303 format %{ "imull $dst, $src, $imm\t# int" %}
8304 opcode(0x69); /* 69 /r id */
8305 ins_encode(REX_reg_reg(dst, src),
8306 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8307 ins_pipe(ialu_reg_reg_alu0);
8308 %}
8309
8310 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8311 %{
8312 match(Set dst (MulI dst (LoadI src)));
8313 effect(KILL cr);
8314
8315 ins_cost(350);
8316 format %{ "imull $dst, $src\t# int" %}
8317 opcode(0x0F, 0xAF);
8318 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8319 ins_pipe(ialu_reg_mem_alu0);
8320 %}
8321
8322 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8323 %{
8324 match(Set dst (MulI (LoadI src) imm));
8325 effect(KILL cr);
8326
8327 ins_cost(300);
8328 format %{ "imull $dst, $src, $imm\t# int" %}
8329 opcode(0x69); /* 69 /r id */
8330 ins_encode(REX_reg_mem(dst, src),
8331 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8332 ins_pipe(ialu_reg_mem_alu0);
8333 %}
8334
8335 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8336 %{
8337 match(Set dst (MulL dst src));
8338 effect(KILL cr);
8339
8340 ins_cost(300);
8341 format %{ "imulq $dst, $src\t# long" %}
8342 opcode(0x0F, 0xAF);
8343 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8344 ins_pipe(ialu_reg_reg_alu0);
8345 %}
8346
8347 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8348 %{
8349 match(Set dst (MulL src imm));
8350 effect(KILL cr);
8351
8352 ins_cost(300);
8353 format %{ "imulq $dst, $src, $imm\t# long" %}
8354 opcode(0x69); /* 69 /r id */
8355 ins_encode(REX_reg_reg_wide(dst, src),
8356 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8357 ins_pipe(ialu_reg_reg_alu0);
8358 %}
8359
8360 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8361 %{
8362 match(Set dst (MulL dst (LoadL src)));
8363 effect(KILL cr);
8364
8365 ins_cost(350);
8366 format %{ "imulq $dst, $src\t# long" %}
8367 opcode(0x0F, 0xAF);
8368 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8369 ins_pipe(ialu_reg_mem_alu0);
8370 %}
8371
8372 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8373 %{
8374 match(Set dst (MulL (LoadL src) imm));
8375 effect(KILL cr);
8376
8377 ins_cost(300);
8378 format %{ "imulq $dst, $src, $imm\t# long" %}
8379 opcode(0x69); /* 69 /r id */
8380 ins_encode(REX_reg_mem_wide(dst, src),
8381 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8382 ins_pipe(ialu_reg_mem_alu0);
8383 %}
8384
8385 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8386 %{
8387 match(Set dst (MulHiL src rax));
8388 effect(USE_KILL rax, KILL cr);
8389
8390 ins_cost(300);
8391 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8392 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8393 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8394 ins_pipe(ialu_reg_reg_alu0);
8395 %}
8396
8397 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8398 rFlagsReg cr)
8399 %{
8400 match(Set rax (DivI rax div));
8401 effect(KILL rdx, KILL cr);
8402
8403 ins_cost(30*100+10*100); // XXX
8404 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8405 "jne,s normal\n\t"
8406 "xorl rdx, rdx\n\t"
8407 "cmpl $div, -1\n\t"
8408 "je,s done\n"
8409 "normal: cdql\n\t"
8410 "idivl $div\n"
8411 "done:" %}
8412 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8413 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8414 ins_pipe(ialu_reg_reg_alu0);
8415 %}
8416
8417 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8418 rFlagsReg cr)
8419 %{
8420 match(Set rax (DivL rax div));
8421 effect(KILL rdx, KILL cr);
8422
8423 ins_cost(30*100+10*100); // XXX
8424 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8425 "cmpq rax, rdx\n\t"
8426 "jne,s normal\n\t"
8427 "xorl rdx, rdx\n\t"
8428 "cmpq $div, -1\n\t"
8429 "je,s done\n"
8430 "normal: cdqq\n\t"
8431 "idivq $div\n"
8432 "done:" %}
8433 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8434 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8435 ins_pipe(ialu_reg_reg_alu0);
8436 %}
8437
8438 // Integer DIVMOD with Register, both quotient and mod results
8439 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8440 rFlagsReg cr)
8441 %{
8442 match(DivModI rax div);
8443 effect(KILL cr);
8444
8445 ins_cost(30*100+10*100); // XXX
8446 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8447 "jne,s normal\n\t"
8448 "xorl rdx, rdx\n\t"
8449 "cmpl $div, -1\n\t"
8450 "je,s done\n"
8451 "normal: cdql\n\t"
8452 "idivl $div\n"
8453 "done:" %}
8454 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8455 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8456 ins_pipe(pipe_slow);
8457 %}
8458
8459 // Long DIVMOD with Register, both quotient and mod results
8460 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8461 rFlagsReg cr)
8462 %{
8463 match(DivModL rax div);
8464 effect(KILL cr);
8465
8466 ins_cost(30*100+10*100); // XXX
8467 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8468 "cmpq rax, rdx\n\t"
8469 "jne,s normal\n\t"
8470 "xorl rdx, rdx\n\t"
8471 "cmpq $div, -1\n\t"
8472 "je,s done\n"
8473 "normal: cdqq\n\t"
8474 "idivq $div\n"
8475 "done:" %}
8476 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8477 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8478 ins_pipe(pipe_slow);
8479 %}
8480
8481 //----------- DivL-By-Constant-Expansions--------------------------------------
8482 // DivI cases are handled by the compiler
8483
8484 // Magic constant, reciprocal of 10
8485 instruct loadConL_0x6666666666666667(rRegL dst)
8486 %{
8487 effect(DEF dst);
8488
8489 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8490 ins_encode(load_immL(dst, 0x6666666666666667));
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8495 %{
8496 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8497
8498 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8499 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8500 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8501 ins_pipe(ialu_reg_reg_alu0);
8502 %}
8503
8504 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8505 %{
8506 effect(USE_DEF dst, KILL cr);
8507
8508 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8509 opcode(0xC1, 0x7); /* C1 /7 ib */
8510 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8511 ins_pipe(ialu_reg);
8512 %}
8513
8514 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8515 %{
8516 effect(USE_DEF dst, KILL cr);
8517
8518 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8519 opcode(0xC1, 0x7); /* C1 /7 ib */
8520 ins_encode(reg_opc_imm_wide(dst, 0x2));
8521 ins_pipe(ialu_reg);
8522 %}
8523
8524 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8525 %{
8526 match(Set dst (DivL src div));
8527
8528 ins_cost((5+8)*100);
8529 expand %{
8530 rax_RegL rax; // Killed temp
8531 rFlagsReg cr; // Killed
8532 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8533 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8534 sarL_rReg_63(src, cr); // sarq src, 63
8535 sarL_rReg_2(dst, cr); // sarq rdx, 2
8536 subL_rReg(dst, src, cr); // subl rdx, src
8537 %}
8538 %}
8539
8540 //-----------------------------------------------------------------------------
8541
8542 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8543 rFlagsReg cr)
8544 %{
8545 match(Set rdx (ModI rax div));
8546 effect(KILL rax, KILL cr);
8547
8548 ins_cost(300); // XXX
8549 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8550 "jne,s normal\n\t"
8551 "xorl rdx, rdx\n\t"
8552 "cmpl $div, -1\n\t"
8553 "je,s done\n"
8554 "normal: cdql\n\t"
8555 "idivl $div\n"
8556 "done:" %}
8557 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8558 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8559 ins_pipe(ialu_reg_reg_alu0);
8560 %}
8561
8562 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8563 rFlagsReg cr)
8564 %{
8565 match(Set rdx (ModL rax div));
8566 effect(KILL rax, KILL cr);
8567
8568 ins_cost(300); // XXX
8569 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8570 "cmpq rax, rdx\n\t"
8571 "jne,s normal\n\t"
8572 "xorl rdx, rdx\n\t"
8573 "cmpq $div, -1\n\t"
8574 "je,s done\n"
8575 "normal: cdqq\n\t"
8576 "idivq $div\n"
8577 "done:" %}
8578 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8579 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8580 ins_pipe(ialu_reg_reg_alu0);
8581 %}
8582
8583 // Integer Shift Instructions
8584 // Shift Left by one
8585 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8586 %{
8587 match(Set dst (LShiftI dst shift));
8588 effect(KILL cr);
8589
8590 format %{ "sall $dst, $shift" %}
8591 opcode(0xD1, 0x4); /* D1 /4 */
8592 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8593 ins_pipe(ialu_reg);
8594 %}
8595
8596 // Shift Left by one
8597 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8598 %{
8599 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8600 effect(KILL cr);
8601
8602 format %{ "sall $dst, $shift\t" %}
8603 opcode(0xD1, 0x4); /* D1 /4 */
8604 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8605 ins_pipe(ialu_mem_imm);
8606 %}
8607
8608 // Shift Left by 8-bit immediate
8609 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8610 %{
8611 match(Set dst (LShiftI dst shift));
8612 effect(KILL cr);
8613
8614 format %{ "sall $dst, $shift" %}
8615 opcode(0xC1, 0x4); /* C1 /4 ib */
8616 ins_encode(reg_opc_imm(dst, shift));
8617 ins_pipe(ialu_reg);
8618 %}
8619
8620 // Shift Left by 8-bit immediate
8621 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8622 %{
8623 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8624 effect(KILL cr);
8625
8626 format %{ "sall $dst, $shift" %}
8627 opcode(0xC1, 0x4); /* C1 /4 ib */
8628 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8629 ins_pipe(ialu_mem_imm);
8630 %}
8631
8632 // Shift Left by variable
8633 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8634 %{
8635 match(Set dst (LShiftI dst shift));
8636 effect(KILL cr);
8637
8638 format %{ "sall $dst, $shift" %}
8639 opcode(0xD3, 0x4); /* D3 /4 */
8640 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8641 ins_pipe(ialu_reg_reg);
8642 %}
8643
8644 // Shift Left by variable
8645 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8646 %{
8647 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8648 effect(KILL cr);
8649
8650 format %{ "sall $dst, $shift" %}
8651 opcode(0xD3, 0x4); /* D3 /4 */
8652 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8653 ins_pipe(ialu_mem_reg);
8654 %}
8655
8656 // Arithmetic shift right by one
8657 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8658 %{
8659 match(Set dst (RShiftI dst shift));
8660 effect(KILL cr);
8661
8662 format %{ "sarl $dst, $shift" %}
8663 opcode(0xD1, 0x7); /* D1 /7 */
8664 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8665 ins_pipe(ialu_reg);
8666 %}
8667
8668 // Arithmetic shift right by one
8669 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8670 %{
8671 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8672 effect(KILL cr);
8673
8674 format %{ "sarl $dst, $shift" %}
8675 opcode(0xD1, 0x7); /* D1 /7 */
8676 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8677 ins_pipe(ialu_mem_imm);
8678 %}
8679
8680 // Arithmetic Shift Right by 8-bit immediate
8681 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8682 %{
8683 match(Set dst (RShiftI dst shift));
8684 effect(KILL cr);
8685
8686 format %{ "sarl $dst, $shift" %}
8687 opcode(0xC1, 0x7); /* C1 /7 ib */
8688 ins_encode(reg_opc_imm(dst, shift));
8689 ins_pipe(ialu_mem_imm);
8690 %}
8691
8692 // Arithmetic Shift Right by 8-bit immediate
8693 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8694 %{
8695 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8696 effect(KILL cr);
8697
8698 format %{ "sarl $dst, $shift" %}
8699 opcode(0xC1, 0x7); /* C1 /7 ib */
8700 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8701 ins_pipe(ialu_mem_imm);
8702 %}
8703
8704 // Arithmetic Shift Right by variable
8705 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8706 %{
8707 match(Set dst (RShiftI dst shift));
8708 effect(KILL cr);
8709
8710 format %{ "sarl $dst, $shift" %}
8711 opcode(0xD3, 0x7); /* D3 /7 */
8712 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8713 ins_pipe(ialu_reg_reg);
8714 %}
8715
8716 // Arithmetic Shift Right by variable
8717 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8718 %{
8719 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8720 effect(KILL cr);
8721
8722 format %{ "sarl $dst, $shift" %}
8723 opcode(0xD3, 0x7); /* D3 /7 */
8724 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8725 ins_pipe(ialu_mem_reg);
8726 %}
8727
8728 // Logical shift right by one
8729 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8730 %{
8731 match(Set dst (URShiftI dst shift));
8732 effect(KILL cr);
8733
8734 format %{ "shrl $dst, $shift" %}
8735 opcode(0xD1, 0x5); /* D1 /5 */
8736 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8737 ins_pipe(ialu_reg);
8738 %}
8739
8740 // Logical shift right by one
8741 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8742 %{
8743 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8744 effect(KILL cr);
8745
8746 format %{ "shrl $dst, $shift" %}
8747 opcode(0xD1, 0x5); /* D1 /5 */
8748 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8749 ins_pipe(ialu_mem_imm);
8750 %}
8751
8752 // Logical Shift Right by 8-bit immediate
8753 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8754 %{
8755 match(Set dst (URShiftI dst shift));
8756 effect(KILL cr);
8757
8758 format %{ "shrl $dst, $shift" %}
8759 opcode(0xC1, 0x5); /* C1 /5 ib */
8760 ins_encode(reg_opc_imm(dst, shift));
8761 ins_pipe(ialu_reg);
8762 %}
8763
8764 // Logical Shift Right by 8-bit immediate
8765 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8766 %{
8767 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8768 effect(KILL cr);
8769
8770 format %{ "shrl $dst, $shift" %}
8771 opcode(0xC1, 0x5); /* C1 /5 ib */
8772 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8773 ins_pipe(ialu_mem_imm);
8774 %}
8775
8776 // Logical Shift Right by variable
8777 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8778 %{
8779 match(Set dst (URShiftI dst shift));
8780 effect(KILL cr);
8781
8782 format %{ "shrl $dst, $shift" %}
8783 opcode(0xD3, 0x5); /* D3 /5 */
8784 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8785 ins_pipe(ialu_reg_reg);
8786 %}
8787
8788 // Logical Shift Right by variable
8789 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8790 %{
8791 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8792 effect(KILL cr);
8793
8794 format %{ "shrl $dst, $shift" %}
8795 opcode(0xD3, 0x5); /* D3 /5 */
8796 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8797 ins_pipe(ialu_mem_reg);
8798 %}
8799
8800 // Long Shift Instructions
8801 // Shift Left by one
8802 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8803 %{
8804 match(Set dst (LShiftL dst shift));
8805 effect(KILL cr);
8806
8807 format %{ "salq $dst, $shift" %}
8808 opcode(0xD1, 0x4); /* D1 /4 */
8809 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8810 ins_pipe(ialu_reg);
8811 %}
8812
8813 // Shift Left by one
8814 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8815 %{
8816 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8817 effect(KILL cr);
8818
8819 format %{ "salq $dst, $shift" %}
8820 opcode(0xD1, 0x4); /* D1 /4 */
8821 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8822 ins_pipe(ialu_mem_imm);
8823 %}
8824
8825 // Shift Left by 8-bit immediate
8826 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8827 %{
8828 match(Set dst (LShiftL dst shift));
8829 effect(KILL cr);
8830
8831 format %{ "salq $dst, $shift" %}
8832 opcode(0xC1, 0x4); /* C1 /4 ib */
8833 ins_encode(reg_opc_imm_wide(dst, shift));
8834 ins_pipe(ialu_reg);
8835 %}
8836
8837 // Shift Left by 8-bit immediate
8838 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8839 %{
8840 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8841 effect(KILL cr);
8842
8843 format %{ "salq $dst, $shift" %}
8844 opcode(0xC1, 0x4); /* C1 /4 ib */
8845 ins_encode(REX_mem_wide(dst), OpcP,
8846 RM_opc_mem(secondary, dst), Con8or32(shift));
8847 ins_pipe(ialu_mem_imm);
8848 %}
8849
8850 // Shift Left by variable
8851 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8852 %{
8853 match(Set dst (LShiftL dst shift));
8854 effect(KILL cr);
8855
8856 format %{ "salq $dst, $shift" %}
8857 opcode(0xD3, 0x4); /* D3 /4 */
8858 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8859 ins_pipe(ialu_reg_reg);
8860 %}
8861
8862 // Shift Left by variable
8863 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8864 %{
8865 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8866 effect(KILL cr);
8867
8868 format %{ "salq $dst, $shift" %}
8869 opcode(0xD3, 0x4); /* D3 /4 */
8870 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8871 ins_pipe(ialu_mem_reg);
8872 %}
8873
8874 // Arithmetic shift right by one
8875 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8876 %{
8877 match(Set dst (RShiftL dst shift));
8878 effect(KILL cr);
8879
8880 format %{ "sarq $dst, $shift" %}
8881 opcode(0xD1, 0x7); /* D1 /7 */
8882 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8883 ins_pipe(ialu_reg);
8884 %}
8885
8886 // Arithmetic shift right by one
8887 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8888 %{
8889 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8890 effect(KILL cr);
8891
8892 format %{ "sarq $dst, $shift" %}
8893 opcode(0xD1, 0x7); /* D1 /7 */
8894 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8895 ins_pipe(ialu_mem_imm);
8896 %}
8897
8898 // Arithmetic Shift Right by 8-bit immediate
8899 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8900 %{
8901 match(Set dst (RShiftL dst shift));
8902 effect(KILL cr);
8903
8904 format %{ "sarq $dst, $shift" %}
8905 opcode(0xC1, 0x7); /* C1 /7 ib */
8906 ins_encode(reg_opc_imm_wide(dst, shift));
8907 ins_pipe(ialu_mem_imm);
8908 %}
8909
8910 // Arithmetic Shift Right by 8-bit immediate
8911 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8912 %{
8913 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8914 effect(KILL cr);
8915
8916 format %{ "sarq $dst, $shift" %}
8917 opcode(0xC1, 0x7); /* C1 /7 ib */
8918 ins_encode(REX_mem_wide(dst), OpcP,
8919 RM_opc_mem(secondary, dst), Con8or32(shift));
8920 ins_pipe(ialu_mem_imm);
8921 %}
8922
8923 // Arithmetic Shift Right by variable
8924 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8925 %{
8926 match(Set dst (RShiftL dst shift));
8927 effect(KILL cr);
8928
8929 format %{ "sarq $dst, $shift" %}
8930 opcode(0xD3, 0x7); /* D3 /7 */
8931 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8932 ins_pipe(ialu_reg_reg);
8933 %}
8934
8935 // Arithmetic Shift Right by variable
8936 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8937 %{
8938 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8939 effect(KILL cr);
8940
8941 format %{ "sarq $dst, $shift" %}
8942 opcode(0xD3, 0x7); /* D3 /7 */
8943 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8944 ins_pipe(ialu_mem_reg);
8945 %}
8946
8947 // Logical shift right by one
8948 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8949 %{
8950 match(Set dst (URShiftL dst shift));
8951 effect(KILL cr);
8952
8953 format %{ "shrq $dst, $shift" %}
8954 opcode(0xD1, 0x5); /* D1 /5 */
8955 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8956 ins_pipe(ialu_reg);
8957 %}
8958
8959 // Logical shift right by one
8960 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8961 %{
8962 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8963 effect(KILL cr);
8964
8965 format %{ "shrq $dst, $shift" %}
8966 opcode(0xD1, 0x5); /* D1 /5 */
8967 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8968 ins_pipe(ialu_mem_imm);
8969 %}
8970
8971 // Logical Shift Right by 8-bit immediate
8972 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8973 %{
8974 match(Set dst (URShiftL dst shift));
8975 effect(KILL cr);
8976
8977 format %{ "shrq $dst, $shift" %}
8978 opcode(0xC1, 0x5); /* C1 /5 ib */
8979 ins_encode(reg_opc_imm_wide(dst, shift));
8980 ins_pipe(ialu_reg);
8981 %}
8982
8983
8984 // Logical Shift Right by 8-bit immediate
8985 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8986 %{
8987 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8988 effect(KILL cr);
8989
8990 format %{ "shrq $dst, $shift" %}
8991 opcode(0xC1, 0x5); /* C1 /5 ib */
8992 ins_encode(REX_mem_wide(dst), OpcP,
8993 RM_opc_mem(secondary, dst), Con8or32(shift));
8994 ins_pipe(ialu_mem_imm);
8995 %}
8996
8997 // Logical Shift Right by variable
8998 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8999 %{
9000 match(Set dst (URShiftL dst shift));
9001 effect(KILL cr);
9002
9003 format %{ "shrq $dst, $shift" %}
9004 opcode(0xD3, 0x5); /* D3 /5 */
9005 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9006 ins_pipe(ialu_reg_reg);
9007 %}
9008
9009 // Logical Shift Right by variable
9010 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9011 %{
9012 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9013 effect(KILL cr);
9014
9015 format %{ "shrq $dst, $shift" %}
9016 opcode(0xD3, 0x5); /* D3 /5 */
9017 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9018 ins_pipe(ialu_mem_reg);
9019 %}
9020
9021 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9022 // This idiom is used by the compiler for the i2b bytecode.
9023 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9024 %{
9025 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9026
9027 format %{ "movsbl $dst, $src\t# i2b" %}
9028 opcode(0x0F, 0xBE);
9029 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9030 ins_pipe(ialu_reg_reg);
9031 %}
9032
9033 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9034 // This idiom is used by the compiler the i2s bytecode.
9035 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9036 %{
9037 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9038
9039 format %{ "movswl $dst, $src\t# i2s" %}
9040 opcode(0x0F, 0xBF);
9041 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9042 ins_pipe(ialu_reg_reg);
9043 %}
9044
9045 // ROL/ROR instructions
9046
9047 // ROL expand
9048 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9049 effect(KILL cr, USE_DEF dst);
9050
9051 format %{ "roll $dst" %}
9052 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9053 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9054 ins_pipe(ialu_reg);
9055 %}
9056
9057 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9058 effect(USE_DEF dst, USE shift, KILL cr);
9059
9060 format %{ "roll $dst, $shift" %}
9061 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9062 ins_encode( reg_opc_imm(dst, shift) );
9063 ins_pipe(ialu_reg);
9064 %}
9065
9066 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9067 %{
9068 effect(USE_DEF dst, USE shift, KILL cr);
9069
9070 format %{ "roll $dst, $shift" %}
9071 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9072 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9073 ins_pipe(ialu_reg_reg);
9074 %}
9075 // end of ROL expand
9076
9077 // Rotate Left by one
9078 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9079 %{
9080 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9081
9082 expand %{
9083 rolI_rReg_imm1(dst, cr);
9084 %}
9085 %}
9086
9087 // Rotate Left by 8-bit immediate
9088 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9089 %{
9090 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9091 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9092
9093 expand %{
9094 rolI_rReg_imm8(dst, lshift, cr);
9095 %}
9096 %}
9097
9098 // Rotate Left by variable
9099 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9100 %{
9101 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9102
9103 expand %{
9104 rolI_rReg_CL(dst, shift, cr);
9105 %}
9106 %}
9107
9108 // Rotate Left by variable
9109 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9110 %{
9111 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9112
9113 expand %{
9114 rolI_rReg_CL(dst, shift, cr);
9115 %}
9116 %}
9117
9118 // ROR expand
9119 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9120 %{
9121 effect(USE_DEF dst, KILL cr);
9122
9123 format %{ "rorl $dst" %}
9124 opcode(0xD1, 0x1); /* D1 /1 */
9125 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9126 ins_pipe(ialu_reg);
9127 %}
9128
9129 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9130 %{
9131 effect(USE_DEF dst, USE shift, KILL cr);
9132
9133 format %{ "rorl $dst, $shift" %}
9134 opcode(0xC1, 0x1); /* C1 /1 ib */
9135 ins_encode(reg_opc_imm(dst, shift));
9136 ins_pipe(ialu_reg);
9137 %}
9138
9139 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9140 %{
9141 effect(USE_DEF dst, USE shift, KILL cr);
9142
9143 format %{ "rorl $dst, $shift" %}
9144 opcode(0xD3, 0x1); /* D3 /1 */
9145 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9146 ins_pipe(ialu_reg_reg);
9147 %}
9148 // end of ROR expand
9149
9150 // Rotate Right by one
9151 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9152 %{
9153 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9154
9155 expand %{
9156 rorI_rReg_imm1(dst, cr);
9157 %}
9158 %}
9159
9160 // Rotate Right by 8-bit immediate
9161 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9162 %{
9163 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9164 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9165
9166 expand %{
9167 rorI_rReg_imm8(dst, rshift, cr);
9168 %}
9169 %}
9170
9171 // Rotate Right by variable
9172 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9173 %{
9174 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9175
9176 expand %{
9177 rorI_rReg_CL(dst, shift, cr);
9178 %}
9179 %}
9180
9181 // Rotate Right by variable
9182 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9183 %{
9184 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9185
9186 expand %{
9187 rorI_rReg_CL(dst, shift, cr);
9188 %}
9189 %}
9190
9191 // for long rotate
9192 // ROL expand
9193 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9194 effect(USE_DEF dst, KILL cr);
9195
9196 format %{ "rolq $dst" %}
9197 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9198 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9199 ins_pipe(ialu_reg);
9200 %}
9201
9202 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9203 effect(USE_DEF dst, USE shift, KILL cr);
9204
9205 format %{ "rolq $dst, $shift" %}
9206 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9207 ins_encode( reg_opc_imm_wide(dst, shift) );
9208 ins_pipe(ialu_reg);
9209 %}
9210
9211 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9212 %{
9213 effect(USE_DEF dst, USE shift, KILL cr);
9214
9215 format %{ "rolq $dst, $shift" %}
9216 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9217 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9218 ins_pipe(ialu_reg_reg);
9219 %}
9220 // end of ROL expand
9221
9222 // Rotate Left by one
9223 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9224 %{
9225 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9226
9227 expand %{
9228 rolL_rReg_imm1(dst, cr);
9229 %}
9230 %}
9231
9232 // Rotate Left by 8-bit immediate
9233 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9234 %{
9235 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9236 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9237
9238 expand %{
9239 rolL_rReg_imm8(dst, lshift, cr);
9240 %}
9241 %}
9242
9243 // Rotate Left by variable
9244 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9245 %{
9246 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9247
9248 expand %{
9249 rolL_rReg_CL(dst, shift, cr);
9250 %}
9251 %}
9252
9253 // Rotate Left by variable
9254 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9255 %{
9256 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9257
9258 expand %{
9259 rolL_rReg_CL(dst, shift, cr);
9260 %}
9261 %}
9262
9263 // ROR expand
9264 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9265 %{
9266 effect(USE_DEF dst, KILL cr);
9267
9268 format %{ "rorq $dst" %}
9269 opcode(0xD1, 0x1); /* D1 /1 */
9270 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9271 ins_pipe(ialu_reg);
9272 %}
9273
9274 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9275 %{
9276 effect(USE_DEF dst, USE shift, KILL cr);
9277
9278 format %{ "rorq $dst, $shift" %}
9279 opcode(0xC1, 0x1); /* C1 /1 ib */
9280 ins_encode(reg_opc_imm_wide(dst, shift));
9281 ins_pipe(ialu_reg);
9282 %}
9283
9284 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9285 %{
9286 effect(USE_DEF dst, USE shift, KILL cr);
9287
9288 format %{ "rorq $dst, $shift" %}
9289 opcode(0xD3, 0x1); /* D3 /1 */
9290 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9291 ins_pipe(ialu_reg_reg);
9292 %}
9293 // end of ROR expand
9294
9295 // Rotate Right by one
9296 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9297 %{
9298 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9299
9300 expand %{
9301 rorL_rReg_imm1(dst, cr);
9302 %}
9303 %}
9304
9305 // Rotate Right by 8-bit immediate
9306 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9307 %{
9308 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9309 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9310
9311 expand %{
9312 rorL_rReg_imm8(dst, rshift, cr);
9313 %}
9314 %}
9315
9316 // Rotate Right by variable
9317 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9318 %{
9319 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9320
9321 expand %{
9322 rorL_rReg_CL(dst, shift, cr);
9323 %}
9324 %}
9325
9326 // Rotate Right by variable
9327 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9328 %{
9329 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9330
9331 expand %{
9332 rorL_rReg_CL(dst, shift, cr);
9333 %}
9334 %}
9335
9336 // Logical Instructions
9337
9338 // Integer Logical Instructions
9339
9340 // And Instructions
9341 // And Register with Register
9342 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9343 %{
9344 match(Set dst (AndI dst src));
9345 effect(KILL cr);
9346
9347 format %{ "andl $dst, $src\t# int" %}
9348 opcode(0x23);
9349 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9350 ins_pipe(ialu_reg_reg);
9351 %}
9352
9353 // And Register with Immediate 255
9354 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9355 %{
9356 match(Set dst (AndI dst src));
9357
9358 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9359 opcode(0x0F, 0xB6);
9360 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9361 ins_pipe(ialu_reg);
9362 %}
9363
9364 // And Register with Immediate 255 and promote to long
9365 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9366 %{
9367 match(Set dst (ConvI2L (AndI src mask)));
9368
9369 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9370 opcode(0x0F, 0xB6);
9371 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9372 ins_pipe(ialu_reg);
9373 %}
9374
9375 // And Register with Immediate 65535
9376 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9377 %{
9378 match(Set dst (AndI dst src));
9379
9380 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9381 opcode(0x0F, 0xB7);
9382 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9383 ins_pipe(ialu_reg);
9384 %}
9385
9386 // And Register with Immediate 65535 and promote to long
9387 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9388 %{
9389 match(Set dst (ConvI2L (AndI src mask)));
9390
9391 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9392 opcode(0x0F, 0xB7);
9393 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9394 ins_pipe(ialu_reg);
9395 %}
9396
9397 // And Register with Immediate
9398 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9399 %{
9400 match(Set dst (AndI dst src));
9401 effect(KILL cr);
9402
9403 format %{ "andl $dst, $src\t# int" %}
9404 opcode(0x81, 0x04); /* Opcode 81 /4 */
9405 ins_encode(OpcSErm(dst, src), Con8or32(src));
9406 ins_pipe(ialu_reg);
9407 %}
9408
9409 // And Register with Memory
9410 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9411 %{
9412 match(Set dst (AndI dst (LoadI src)));
9413 effect(KILL cr);
9414
9415 ins_cost(125);
9416 format %{ "andl $dst, $src\t# int" %}
9417 opcode(0x23);
9418 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9419 ins_pipe(ialu_reg_mem);
9420 %}
9421
9422 // And Memory with Register
9423 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9424 %{
9425 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9426 effect(KILL cr);
9427
9428 ins_cost(150);
9429 format %{ "andl $dst, $src\t# int" %}
9430 opcode(0x21); /* Opcode 21 /r */
9431 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9432 ins_pipe(ialu_mem_reg);
9433 %}
9434
9435 // And Memory with Immediate
9436 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9437 %{
9438 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9439 effect(KILL cr);
9440
9441 ins_cost(125);
9442 format %{ "andl $dst, $src\t# int" %}
9443 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9444 ins_encode(REX_mem(dst), OpcSE(src),
9445 RM_opc_mem(secondary, dst), Con8or32(src));
9446 ins_pipe(ialu_mem_imm);
9447 %}
9448
9449 // BMI1 instructions
9450 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9451 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9452 predicate(UseBMI1Instructions);
9453 effect(KILL cr);
9454
9455 ins_cost(125);
9456 format %{ "andnl $dst, $src1, $src2" %}
9457
9458 ins_encode %{
9459 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9460 %}
9461 ins_pipe(ialu_reg_mem);
9462 %}
9463
9464 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9465 match(Set dst (AndI (XorI src1 minus_1) src2));
9466 predicate(UseBMI1Instructions);
9467 effect(KILL cr);
9468
9469 format %{ "andnl $dst, $src1, $src2" %}
9470
9471 ins_encode %{
9472 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9473 %}
9474 ins_pipe(ialu_reg);
9475 %}
9476
9477 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9478 match(Set dst (AndI (SubI imm_zero src) src));
9479 predicate(UseBMI1Instructions);
9480 effect(KILL cr);
9481
9482 format %{ "blsil $dst, $src" %}
9483
9484 ins_encode %{
9485 __ blsil($dst$$Register, $src$$Register);
9486 %}
9487 ins_pipe(ialu_reg);
9488 %}
9489
9490 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9491 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9492 predicate(UseBMI1Instructions);
9493 effect(KILL cr);
9494
9495 ins_cost(125);
9496 format %{ "blsil $dst, $src" %}
9497
9498 ins_encode %{
9499 __ blsil($dst$$Register, $src$$Address);
9500 %}
9501 ins_pipe(ialu_reg_mem);
9502 %}
9503
9504 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9505 %{
9506 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9507 predicate(UseBMI1Instructions);
9508 effect(KILL cr);
9509
9510 ins_cost(125);
9511 format %{ "blsmskl $dst, $src" %}
9512
9513 ins_encode %{
9514 __ blsmskl($dst$$Register, $src$$Address);
9515 %}
9516 ins_pipe(ialu_reg_mem);
9517 %}
9518
9519 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9520 %{
9521 match(Set dst (XorI (AddI src minus_1) src));
9522 predicate(UseBMI1Instructions);
9523 effect(KILL cr);
9524
9525 format %{ "blsmskl $dst, $src" %}
9526
9527 ins_encode %{
9528 __ blsmskl($dst$$Register, $src$$Register);
9529 %}
9530
9531 ins_pipe(ialu_reg);
9532 %}
9533
9534 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9535 %{
9536 match(Set dst (AndI (AddI src minus_1) src) );
9537 predicate(UseBMI1Instructions);
9538 effect(KILL cr);
9539
9540 format %{ "blsrl $dst, $src" %}
9541
9542 ins_encode %{
9543 __ blsrl($dst$$Register, $src$$Register);
9544 %}
9545
9546 ins_pipe(ialu_reg_mem);
9547 %}
9548
9549 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9550 %{
9551 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9552 predicate(UseBMI1Instructions);
9553 effect(KILL cr);
9554
9555 ins_cost(125);
9556 format %{ "blsrl $dst, $src" %}
9557
9558 ins_encode %{
9559 __ blsrl($dst$$Register, $src$$Address);
9560 %}
9561
9562 ins_pipe(ialu_reg);
9563 %}
9564
9565 // Or Instructions
9566 // Or Register with Register
9567 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9568 %{
9569 match(Set dst (OrI dst src));
9570 effect(KILL cr);
9571
9572 format %{ "orl $dst, $src\t# int" %}
9573 opcode(0x0B);
9574 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9575 ins_pipe(ialu_reg_reg);
9576 %}
9577
9578 // Or Register with Immediate
9579 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9580 %{
9581 match(Set dst (OrI dst src));
9582 effect(KILL cr);
9583
9584 format %{ "orl $dst, $src\t# int" %}
9585 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9586 ins_encode(OpcSErm(dst, src), Con8or32(src));
9587 ins_pipe(ialu_reg);
9588 %}
9589
9590 // Or Register with Memory
9591 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9592 %{
9593 match(Set dst (OrI dst (LoadI src)));
9594 effect(KILL cr);
9595
9596 ins_cost(125);
9597 format %{ "orl $dst, $src\t# int" %}
9598 opcode(0x0B);
9599 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9600 ins_pipe(ialu_reg_mem);
9601 %}
9602
9603 // Or Memory with Register
9604 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9605 %{
9606 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9607 effect(KILL cr);
9608
9609 ins_cost(150);
9610 format %{ "orl $dst, $src\t# int" %}
9611 opcode(0x09); /* Opcode 09 /r */
9612 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9613 ins_pipe(ialu_mem_reg);
9614 %}
9615
9616 // Or Memory with Immediate
9617 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9618 %{
9619 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9620 effect(KILL cr);
9621
9622 ins_cost(125);
9623 format %{ "orl $dst, $src\t# int" %}
9624 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9625 ins_encode(REX_mem(dst), OpcSE(src),
9626 RM_opc_mem(secondary, dst), Con8or32(src));
9627 ins_pipe(ialu_mem_imm);
9628 %}
9629
9630 // Xor Instructions
9631 // Xor Register with Register
9632 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9633 %{
9634 match(Set dst (XorI dst src));
9635 effect(KILL cr);
9636
9637 format %{ "xorl $dst, $src\t# int" %}
9638 opcode(0x33);
9639 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9640 ins_pipe(ialu_reg_reg);
9641 %}
9642
9643 // Xor Register with Immediate -1
9644 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9645 match(Set dst (XorI dst imm));
9646
9647 format %{ "not $dst" %}
9648 ins_encode %{
9649 __ notl($dst$$Register);
9650 %}
9651 ins_pipe(ialu_reg);
9652 %}
9653
9654 // Xor Register with Immediate
9655 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9656 %{
9657 match(Set dst (XorI dst src));
9658 effect(KILL cr);
9659
9660 format %{ "xorl $dst, $src\t# int" %}
9661 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9662 ins_encode(OpcSErm(dst, src), Con8or32(src));
9663 ins_pipe(ialu_reg);
9664 %}
9665
9666 // Xor Register with Memory
9667 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9668 %{
9669 match(Set dst (XorI dst (LoadI src)));
9670 effect(KILL cr);
9671
9672 ins_cost(125);
9673 format %{ "xorl $dst, $src\t# int" %}
9674 opcode(0x33);
9675 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9676 ins_pipe(ialu_reg_mem);
9677 %}
9678
9679 // Xor Memory with Register
9680 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9681 %{
9682 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9683 effect(KILL cr);
9684
9685 ins_cost(150);
9686 format %{ "xorl $dst, $src\t# int" %}
9687 opcode(0x31); /* Opcode 31 /r */
9688 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9689 ins_pipe(ialu_mem_reg);
9690 %}
9691
9692 // Xor Memory with Immediate
9693 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9694 %{
9695 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9696 effect(KILL cr);
9697
9698 ins_cost(125);
9699 format %{ "xorl $dst, $src\t# int" %}
9700 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9701 ins_encode(REX_mem(dst), OpcSE(src),
9702 RM_opc_mem(secondary, dst), Con8or32(src));
9703 ins_pipe(ialu_mem_imm);
9704 %}
9705
9706
9707 // Long Logical Instructions
9708
9709 // And Instructions
9710 // And Register with Register
9711 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9712 %{
9713 match(Set dst (AndL dst src));
9714 effect(KILL cr);
9715
9716 format %{ "andq $dst, $src\t# long" %}
9717 opcode(0x23);
9718 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9719 ins_pipe(ialu_reg_reg);
9720 %}
9721
9722 // And Register with Immediate 255
9723 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9724 %{
9725 match(Set dst (AndL dst src));
9726
9727 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9728 opcode(0x0F, 0xB6);
9729 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9730 ins_pipe(ialu_reg);
9731 %}
9732
9733 // And Register with Immediate 65535
9734 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9735 %{
9736 match(Set dst (AndL dst src));
9737
9738 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9739 opcode(0x0F, 0xB7);
9740 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9741 ins_pipe(ialu_reg);
9742 %}
9743
9744 // And Register with Immediate
9745 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9746 %{
9747 match(Set dst (AndL dst src));
9748 effect(KILL cr);
9749
9750 format %{ "andq $dst, $src\t# long" %}
9751 opcode(0x81, 0x04); /* Opcode 81 /4 */
9752 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9753 ins_pipe(ialu_reg);
9754 %}
9755
9756 // And Register with Memory
9757 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9758 %{
9759 match(Set dst (AndL dst (LoadL src)));
9760 effect(KILL cr);
9761
9762 ins_cost(125);
9763 format %{ "andq $dst, $src\t# long" %}
9764 opcode(0x23);
9765 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9766 ins_pipe(ialu_reg_mem);
9767 %}
9768
9769 // And Memory with Register
9770 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9771 %{
9772 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9773 effect(KILL cr);
9774
9775 ins_cost(150);
9776 format %{ "andq $dst, $src\t# long" %}
9777 opcode(0x21); /* Opcode 21 /r */
9778 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9779 ins_pipe(ialu_mem_reg);
9780 %}
9781
9782 // And Memory with Immediate
9783 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9784 %{
9785 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9786 effect(KILL cr);
9787
9788 ins_cost(125);
9789 format %{ "andq $dst, $src\t# long" %}
9790 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9791 ins_encode(REX_mem_wide(dst), OpcSE(src),
9792 RM_opc_mem(secondary, dst), Con8or32(src));
9793 ins_pipe(ialu_mem_imm);
9794 %}
9795
9796 // BMI1 instructions
9797 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9798 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9799 predicate(UseBMI1Instructions);
9800 effect(KILL cr);
9801
9802 ins_cost(125);
9803 format %{ "andnq $dst, $src1, $src2" %}
9804
9805 ins_encode %{
9806 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9807 %}
9808 ins_pipe(ialu_reg_mem);
9809 %}
9810
9811 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9812 match(Set dst (AndL (XorL src1 minus_1) src2));
9813 predicate(UseBMI1Instructions);
9814 effect(KILL cr);
9815
9816 format %{ "andnq $dst, $src1, $src2" %}
9817
9818 ins_encode %{
9819 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9820 %}
9821 ins_pipe(ialu_reg_mem);
9822 %}
9823
9824 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9825 match(Set dst (AndL (SubL imm_zero src) src));
9826 predicate(UseBMI1Instructions);
9827 effect(KILL cr);
9828
9829 format %{ "blsiq $dst, $src" %}
9830
9831 ins_encode %{
9832 __ blsiq($dst$$Register, $src$$Register);
9833 %}
9834 ins_pipe(ialu_reg);
9835 %}
9836
9837 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9838 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9839 predicate(UseBMI1Instructions);
9840 effect(KILL cr);
9841
9842 ins_cost(125);
9843 format %{ "blsiq $dst, $src" %}
9844
9845 ins_encode %{
9846 __ blsiq($dst$$Register, $src$$Address);
9847 %}
9848 ins_pipe(ialu_reg_mem);
9849 %}
9850
9851 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9852 %{
9853 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9854 predicate(UseBMI1Instructions);
9855 effect(KILL cr);
9856
9857 ins_cost(125);
9858 format %{ "blsmskq $dst, $src" %}
9859
9860 ins_encode %{
9861 __ blsmskq($dst$$Register, $src$$Address);
9862 %}
9863 ins_pipe(ialu_reg_mem);
9864 %}
9865
9866 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9867 %{
9868 match(Set dst (XorL (AddL src minus_1) src));
9869 predicate(UseBMI1Instructions);
9870 effect(KILL cr);
9871
9872 format %{ "blsmskq $dst, $src" %}
9873
9874 ins_encode %{
9875 __ blsmskq($dst$$Register, $src$$Register);
9876 %}
9877
9878 ins_pipe(ialu_reg);
9879 %}
9880
9881 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9882 %{
9883 match(Set dst (AndL (AddL src minus_1) src) );
9884 predicate(UseBMI1Instructions);
9885 effect(KILL cr);
9886
9887 format %{ "blsrq $dst, $src" %}
9888
9889 ins_encode %{
9890 __ blsrq($dst$$Register, $src$$Register);
9891 %}
9892
9893 ins_pipe(ialu_reg);
9894 %}
9895
9896 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9897 %{
9898 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9899 predicate(UseBMI1Instructions);
9900 effect(KILL cr);
9901
9902 ins_cost(125);
9903 format %{ "blsrq $dst, $src" %}
9904
9905 ins_encode %{
9906 __ blsrq($dst$$Register, $src$$Address);
9907 %}
9908
9909 ins_pipe(ialu_reg);
9910 %}
9911
9912 // Or Instructions
9913 // Or Register with Register
9914 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9915 %{
9916 match(Set dst (OrL dst src));
9917 effect(KILL cr);
9918
9919 format %{ "orq $dst, $src\t# long" %}
9920 opcode(0x0B);
9921 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9922 ins_pipe(ialu_reg_reg);
9923 %}
9924
9925 // Use any_RegP to match R15 (TLS register) without spilling.
9926 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9927 match(Set dst (OrL dst (CastP2X src)));
9928 effect(KILL cr);
9929
9930 format %{ "orq $dst, $src\t# long" %}
9931 opcode(0x0B);
9932 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9933 ins_pipe(ialu_reg_reg);
9934 %}
9935
9936
9937 // Or Register with Immediate
9938 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9939 %{
9940 match(Set dst (OrL dst src));
9941 effect(KILL cr);
9942
9943 format %{ "orq $dst, $src\t# long" %}
9944 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9945 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9946 ins_pipe(ialu_reg);
9947 %}
9948
9949 // Or Register with Memory
9950 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9951 %{
9952 match(Set dst (OrL dst (LoadL src)));
9953 effect(KILL cr);
9954
9955 ins_cost(125);
9956 format %{ "orq $dst, $src\t# long" %}
9957 opcode(0x0B);
9958 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9959 ins_pipe(ialu_reg_mem);
9960 %}
9961
9962 // Or Memory with Register
9963 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9964 %{
9965 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9966 effect(KILL cr);
9967
9968 ins_cost(150);
9969 format %{ "orq $dst, $src\t# long" %}
9970 opcode(0x09); /* Opcode 09 /r */
9971 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9972 ins_pipe(ialu_mem_reg);
9973 %}
9974
9975 // Or Memory with Immediate
9976 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9977 %{
9978 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9979 effect(KILL cr);
9980
9981 ins_cost(125);
9982 format %{ "orq $dst, $src\t# long" %}
9983 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9984 ins_encode(REX_mem_wide(dst), OpcSE(src),
9985 RM_opc_mem(secondary, dst), Con8or32(src));
9986 ins_pipe(ialu_mem_imm);
9987 %}
9988
9989 // Xor Instructions
9990 // Xor Register with Register
9991 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9992 %{
9993 match(Set dst (XorL dst src));
9994 effect(KILL cr);
9995
9996 format %{ "xorq $dst, $src\t# long" %}
9997 opcode(0x33);
9998 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9999 ins_pipe(ialu_reg_reg);
10000 %}
10001
10002 // Xor Register with Immediate -1
10003 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10004 match(Set dst (XorL dst imm));
10005
10006 format %{ "notq $dst" %}
10007 ins_encode %{
10008 __ notq($dst$$Register);
10009 %}
10010 ins_pipe(ialu_reg);
10011 %}
10012
10013 // Xor Register with Immediate
10014 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10015 %{
10016 match(Set dst (XorL dst src));
10017 effect(KILL cr);
10018
10019 format %{ "xorq $dst, $src\t# long" %}
10020 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10021 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10022 ins_pipe(ialu_reg);
10023 %}
10024
10025 // Xor Register with Memory
10026 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10027 %{
10028 match(Set dst (XorL dst (LoadL src)));
10029 effect(KILL cr);
10030
10031 ins_cost(125);
10032 format %{ "xorq $dst, $src\t# long" %}
10033 opcode(0x33);
10034 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10035 ins_pipe(ialu_reg_mem);
10036 %}
10037
10038 // Xor Memory with Register
10039 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10040 %{
10041 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10042 effect(KILL cr);
10043
10044 ins_cost(150);
10045 format %{ "xorq $dst, $src\t# long" %}
10046 opcode(0x31); /* Opcode 31 /r */
10047 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10048 ins_pipe(ialu_mem_reg);
10049 %}
10050
10051 // Xor Memory with Immediate
10052 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10053 %{
10054 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10055 effect(KILL cr);
10056
10057 ins_cost(125);
10058 format %{ "xorq $dst, $src\t# long" %}
10059 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10060 ins_encode(REX_mem_wide(dst), OpcSE(src),
10061 RM_opc_mem(secondary, dst), Con8or32(src));
10062 ins_pipe(ialu_mem_imm);
10063 %}
10064
10065 // Convert Int to Boolean
10066 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10067 %{
10068 match(Set dst (Conv2B src));
10069 effect(KILL cr);
10070
10071 format %{ "testl $src, $src\t# ci2b\n\t"
10072 "setnz $dst\n\t"
10073 "movzbl $dst, $dst" %}
10074 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10075 setNZ_reg(dst),
10076 REX_reg_breg(dst, dst), // movzbl
10077 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10078 ins_pipe(pipe_slow); // XXX
10079 %}
10080
10081 // Convert Pointer to Boolean
10082 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10083 %{
10084 match(Set dst (Conv2B src));
10085 effect(KILL cr);
10086
10087 format %{ "testq $src, $src\t# cp2b\n\t"
10088 "setnz $dst\n\t"
10089 "movzbl $dst, $dst" %}
10090 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10091 setNZ_reg(dst),
10092 REX_reg_breg(dst, dst), // movzbl
10093 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10094 ins_pipe(pipe_slow); // XXX
10095 %}
10096
10097 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10098 %{
10099 match(Set dst (CmpLTMask p q));
10100 effect(KILL cr);
10101
10102 ins_cost(400);
10103 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10104 "setlt $dst\n\t"
10105 "movzbl $dst, $dst\n\t"
10106 "negl $dst" %}
10107 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10108 setLT_reg(dst),
10109 REX_reg_breg(dst, dst), // movzbl
10110 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10111 neg_reg(dst));
10112 ins_pipe(pipe_slow);
10113 %}
10114
10115 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10116 %{
10117 match(Set dst (CmpLTMask dst zero));
10118 effect(KILL cr);
10119
10120 ins_cost(100);
10121 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10122 ins_encode %{
10123 __ sarl($dst$$Register, 31);
10124 %}
10125 ins_pipe(ialu_reg);
10126 %}
10127
10128 /* Better to save a register than avoid a branch */
10129 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10130 %{
10131 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10132 effect(KILL cr);
10133 ins_cost(300);
10134 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10135 "jge done\n\t"
10136 "addl $p,$y\n"
10137 "done: " %}
10138 ins_encode %{
10139 Register Rp = $p$$Register;
10140 Register Rq = $q$$Register;
10141 Register Ry = $y$$Register;
10142 Label done;
10143 __ subl(Rp, Rq);
10144 __ jccb(Assembler::greaterEqual, done);
10145 __ addl(Rp, Ry);
10146 __ bind(done);
10147 %}
10148 ins_pipe(pipe_cmplt);
10149 %}
10150
10151 /* Better to save a register than avoid a branch */
10152 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10153 %{
10154 match(Set y (AndI (CmpLTMask p q) y));
10155 effect(KILL cr);
10156
10157 ins_cost(300);
10158
10159 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10160 "jlt done\n\t"
10161 "xorl $y, $y\n"
10162 "done: " %}
10163 ins_encode %{
10164 Register Rp = $p$$Register;
10165 Register Rq = $q$$Register;
10166 Register Ry = $y$$Register;
10167 Label done;
10168 __ cmpl(Rp, Rq);
10169 __ jccb(Assembler::less, done);
10170 __ xorl(Ry, Ry);
10171 __ bind(done);
10172 %}
10173 ins_pipe(pipe_cmplt);
10174 %}
10175
10176
10177 //---------- FP Instructions------------------------------------------------
10178
10179 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10180 %{
10181 match(Set cr (CmpF src1 src2));
10182
10183 ins_cost(145);
10184 format %{ "ucomiss $src1, $src2\n\t"
10185 "jnp,s exit\n\t"
10186 "pushfq\t# saw NaN, set CF\n\t"
10187 "andq [rsp], #0xffffff2b\n\t"
10188 "popfq\n"
10189 "exit:" %}
10190 ins_encode %{
10191 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10192 emit_cmpfp_fixup(_masm);
10193 %}
10194 ins_pipe(pipe_slow);
10195 %}
10196
10197 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10198 match(Set cr (CmpF src1 src2));
10199
10200 ins_cost(100);
10201 format %{ "ucomiss $src1, $src2" %}
10202 ins_encode %{
10203 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10204 %}
10205 ins_pipe(pipe_slow);
10206 %}
10207
10208 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10209 %{
10210 match(Set cr (CmpF src1 (LoadF src2)));
10211
10212 ins_cost(145);
10213 format %{ "ucomiss $src1, $src2\n\t"
10214 "jnp,s exit\n\t"
10215 "pushfq\t# saw NaN, set CF\n\t"
10216 "andq [rsp], #0xffffff2b\n\t"
10217 "popfq\n"
10218 "exit:" %}
10219 ins_encode %{
10220 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10221 emit_cmpfp_fixup(_masm);
10222 %}
10223 ins_pipe(pipe_slow);
10224 %}
10225
10226 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10227 match(Set cr (CmpF src1 (LoadF src2)));
10228
10229 ins_cost(100);
10230 format %{ "ucomiss $src1, $src2" %}
10231 ins_encode %{
10232 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10233 %}
10234 ins_pipe(pipe_slow);
10235 %}
10236
10237 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10238 match(Set cr (CmpF src con));
10239
10240 ins_cost(145);
10241 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10242 "jnp,s exit\n\t"
10243 "pushfq\t# saw NaN, set CF\n\t"
10244 "andq [rsp], #0xffffff2b\n\t"
10245 "popfq\n"
10246 "exit:" %}
10247 ins_encode %{
10248 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10249 emit_cmpfp_fixup(_masm);
10250 %}
10251 ins_pipe(pipe_slow);
10252 %}
10253
10254 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10255 match(Set cr (CmpF src con));
10256 ins_cost(100);
10257 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10258 ins_encode %{
10259 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10260 %}
10261 ins_pipe(pipe_slow);
10262 %}
10263
10264 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10265 %{
10266 match(Set cr (CmpD src1 src2));
10267
10268 ins_cost(145);
10269 format %{ "ucomisd $src1, $src2\n\t"
10270 "jnp,s exit\n\t"
10271 "pushfq\t# saw NaN, set CF\n\t"
10272 "andq [rsp], #0xffffff2b\n\t"
10273 "popfq\n"
10274 "exit:" %}
10275 ins_encode %{
10276 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10277 emit_cmpfp_fixup(_masm);
10278 %}
10279 ins_pipe(pipe_slow);
10280 %}
10281
10282 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10283 match(Set cr (CmpD src1 src2));
10284
10285 ins_cost(100);
10286 format %{ "ucomisd $src1, $src2 test" %}
10287 ins_encode %{
10288 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10289 %}
10290 ins_pipe(pipe_slow);
10291 %}
10292
10293 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10294 %{
10295 match(Set cr (CmpD src1 (LoadD src2)));
10296
10297 ins_cost(145);
10298 format %{ "ucomisd $src1, $src2\n\t"
10299 "jnp,s exit\n\t"
10300 "pushfq\t# saw NaN, set CF\n\t"
10301 "andq [rsp], #0xffffff2b\n\t"
10302 "popfq\n"
10303 "exit:" %}
10304 ins_encode %{
10305 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10306 emit_cmpfp_fixup(_masm);
10307 %}
10308 ins_pipe(pipe_slow);
10309 %}
10310
10311 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10312 match(Set cr (CmpD src1 (LoadD src2)));
10313
10314 ins_cost(100);
10315 format %{ "ucomisd $src1, $src2" %}
10316 ins_encode %{
10317 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10318 %}
10319 ins_pipe(pipe_slow);
10320 %}
10321
10322 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10323 match(Set cr (CmpD src con));
10324
10325 ins_cost(145);
10326 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10327 "jnp,s exit\n\t"
10328 "pushfq\t# saw NaN, set CF\n\t"
10329 "andq [rsp], #0xffffff2b\n\t"
10330 "popfq\n"
10331 "exit:" %}
10332 ins_encode %{
10333 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10334 emit_cmpfp_fixup(_masm);
10335 %}
10336 ins_pipe(pipe_slow);
10337 %}
10338
10339 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10340 match(Set cr (CmpD src con));
10341 ins_cost(100);
10342 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10343 ins_encode %{
10344 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10345 %}
10346 ins_pipe(pipe_slow);
10347 %}
10348
10349 // Compare into -1,0,1
10350 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10351 %{
10352 match(Set dst (CmpF3 src1 src2));
10353 effect(KILL cr);
10354
10355 ins_cost(275);
10356 format %{ "ucomiss $src1, $src2\n\t"
10357 "movl $dst, #-1\n\t"
10358 "jp,s done\n\t"
10359 "jb,s done\n\t"
10360 "setne $dst\n\t"
10361 "movzbl $dst, $dst\n"
10362 "done:" %}
10363 ins_encode %{
10364 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10365 emit_cmpfp3(_masm, $dst$$Register);
10366 %}
10367 ins_pipe(pipe_slow);
10368 %}
10369
10370 // Compare into -1,0,1
10371 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10372 %{
10373 match(Set dst (CmpF3 src1 (LoadF src2)));
10374 effect(KILL cr);
10375
10376 ins_cost(275);
10377 format %{ "ucomiss $src1, $src2\n\t"
10378 "movl $dst, #-1\n\t"
10379 "jp,s done\n\t"
10380 "jb,s done\n\t"
10381 "setne $dst\n\t"
10382 "movzbl $dst, $dst\n"
10383 "done:" %}
10384 ins_encode %{
10385 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10386 emit_cmpfp3(_masm, $dst$$Register);
10387 %}
10388 ins_pipe(pipe_slow);
10389 %}
10390
10391 // Compare into -1,0,1
10392 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10393 match(Set dst (CmpF3 src con));
10394 effect(KILL cr);
10395
10396 ins_cost(275);
10397 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10398 "movl $dst, #-1\n\t"
10399 "jp,s done\n\t"
10400 "jb,s done\n\t"
10401 "setne $dst\n\t"
10402 "movzbl $dst, $dst\n"
10403 "done:" %}
10404 ins_encode %{
10405 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10406 emit_cmpfp3(_masm, $dst$$Register);
10407 %}
10408 ins_pipe(pipe_slow);
10409 %}
10410
10411 // Compare into -1,0,1
10412 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10413 %{
10414 match(Set dst (CmpD3 src1 src2));
10415 effect(KILL cr);
10416
10417 ins_cost(275);
10418 format %{ "ucomisd $src1, $src2\n\t"
10419 "movl $dst, #-1\n\t"
10420 "jp,s done\n\t"
10421 "jb,s done\n\t"
10422 "setne $dst\n\t"
10423 "movzbl $dst, $dst\n"
10424 "done:" %}
10425 ins_encode %{
10426 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10427 emit_cmpfp3(_masm, $dst$$Register);
10428 %}
10429 ins_pipe(pipe_slow);
10430 %}
10431
10432 // Compare into -1,0,1
10433 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10434 %{
10435 match(Set dst (CmpD3 src1 (LoadD src2)));
10436 effect(KILL cr);
10437
10438 ins_cost(275);
10439 format %{ "ucomisd $src1, $src2\n\t"
10440 "movl $dst, #-1\n\t"
10441 "jp,s done\n\t"
10442 "jb,s done\n\t"
10443 "setne $dst\n\t"
10444 "movzbl $dst, $dst\n"
10445 "done:" %}
10446 ins_encode %{
10447 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10448 emit_cmpfp3(_masm, $dst$$Register);
10449 %}
10450 ins_pipe(pipe_slow);
10451 %}
10452
10453 // Compare into -1,0,1
10454 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10455 match(Set dst (CmpD3 src con));
10456 effect(KILL cr);
10457
10458 ins_cost(275);
10459 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10460 "movl $dst, #-1\n\t"
10461 "jp,s done\n\t"
10462 "jb,s done\n\t"
10463 "setne $dst\n\t"
10464 "movzbl $dst, $dst\n"
10465 "done:" %}
10466 ins_encode %{
10467 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10468 emit_cmpfp3(_masm, $dst$$Register);
10469 %}
10470 ins_pipe(pipe_slow);
10471 %}
10472
10473 //----------Arithmetic Conversion Instructions---------------------------------
10474
10475 instruct roundFloat_nop(regF dst)
10476 %{
10477 match(Set dst (RoundFloat dst));
10478
10479 ins_cost(0);
10480 ins_encode();
10481 ins_pipe(empty);
10482 %}
10483
10484 instruct roundDouble_nop(regD dst)
10485 %{
10486 match(Set dst (RoundDouble dst));
10487
10488 ins_cost(0);
10489 ins_encode();
10490 ins_pipe(empty);
10491 %}
10492
10493 instruct convF2D_reg_reg(regD dst, regF src)
10494 %{
10495 match(Set dst (ConvF2D src));
10496
10497 format %{ "cvtss2sd $dst, $src" %}
10498 ins_encode %{
10499 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10500 %}
10501 ins_pipe(pipe_slow); // XXX
10502 %}
10503
10504 instruct convF2D_reg_mem(regD dst, memory src)
10505 %{
10506 match(Set dst (ConvF2D (LoadF src)));
10507
10508 format %{ "cvtss2sd $dst, $src" %}
10509 ins_encode %{
10510 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10511 %}
10512 ins_pipe(pipe_slow); // XXX
10513 %}
10514
10515 instruct convD2F_reg_reg(regF dst, regD src)
10516 %{
10517 match(Set dst (ConvD2F src));
10518
10519 format %{ "cvtsd2ss $dst, $src" %}
10520 ins_encode %{
10521 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10522 %}
10523 ins_pipe(pipe_slow); // XXX
10524 %}
10525
10526 instruct convD2F_reg_mem(regF dst, memory src)
10527 %{
10528 match(Set dst (ConvD2F (LoadD src)));
10529
10530 format %{ "cvtsd2ss $dst, $src" %}
10531 ins_encode %{
10532 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10533 %}
10534 ins_pipe(pipe_slow); // XXX
10535 %}
10536
10537 // XXX do mem variants
10538 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10539 %{
10540 match(Set dst (ConvF2I src));
10541 effect(KILL cr);
10542
10543 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10544 "cmpl $dst, #0x80000000\n\t"
10545 "jne,s done\n\t"
10546 "subq rsp, #8\n\t"
10547 "movss [rsp], $src\n\t"
10548 "call f2i_fixup\n\t"
10549 "popq $dst\n"
10550 "done: "%}
10551 ins_encode %{
10552 Label done;
10553 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10554 __ cmpl($dst$$Register, 0x80000000);
10555 __ jccb(Assembler::notEqual, done);
10556 __ subptr(rsp, 8);
10557 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10558 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10559 __ pop($dst$$Register);
10560 __ bind(done);
10561 %}
10562 ins_pipe(pipe_slow);
10563 %}
10564
10565 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10566 %{
10567 match(Set dst (ConvF2L src));
10568 effect(KILL cr);
10569
10570 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10571 "cmpq $dst, [0x8000000000000000]\n\t"
10572 "jne,s done\n\t"
10573 "subq rsp, #8\n\t"
10574 "movss [rsp], $src\n\t"
10575 "call f2l_fixup\n\t"
10576 "popq $dst\n"
10577 "done: "%}
10578 ins_encode %{
10579 Label done;
10580 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10581 __ cmp64($dst$$Register,
10582 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10583 __ jccb(Assembler::notEqual, done);
10584 __ subptr(rsp, 8);
10585 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10586 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10587 __ pop($dst$$Register);
10588 __ bind(done);
10589 %}
10590 ins_pipe(pipe_slow);
10591 %}
10592
10593 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10594 %{
10595 match(Set dst (ConvD2I src));
10596 effect(KILL cr);
10597
10598 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10599 "cmpl $dst, #0x80000000\n\t"
10600 "jne,s done\n\t"
10601 "subq rsp, #8\n\t"
10602 "movsd [rsp], $src\n\t"
10603 "call d2i_fixup\n\t"
10604 "popq $dst\n"
10605 "done: "%}
10606 ins_encode %{
10607 Label done;
10608 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10609 __ cmpl($dst$$Register, 0x80000000);
10610 __ jccb(Assembler::notEqual, done);
10611 __ subptr(rsp, 8);
10612 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10613 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10614 __ pop($dst$$Register);
10615 __ bind(done);
10616 %}
10617 ins_pipe(pipe_slow);
10618 %}
10619
10620 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10621 %{
10622 match(Set dst (ConvD2L src));
10623 effect(KILL cr);
10624
10625 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10626 "cmpq $dst, [0x8000000000000000]\n\t"
10627 "jne,s done\n\t"
10628 "subq rsp, #8\n\t"
10629 "movsd [rsp], $src\n\t"
10630 "call d2l_fixup\n\t"
10631 "popq $dst\n"
10632 "done: "%}
10633 ins_encode %{
10634 Label done;
10635 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10636 __ cmp64($dst$$Register,
10637 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10638 __ jccb(Assembler::notEqual, done);
10639 __ subptr(rsp, 8);
10640 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10641 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10642 __ pop($dst$$Register);
10643 __ bind(done);
10644 %}
10645 ins_pipe(pipe_slow);
10646 %}
10647
10648 instruct convI2F_reg_reg(regF dst, rRegI src)
10649 %{
10650 predicate(!UseXmmI2F);
10651 match(Set dst (ConvI2F src));
10652
10653 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10654 ins_encode %{
10655 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10656 %}
10657 ins_pipe(pipe_slow); // XXX
10658 %}
10659
10660 instruct convI2F_reg_mem(regF dst, memory src)
10661 %{
10662 match(Set dst (ConvI2F (LoadI src)));
10663
10664 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10665 ins_encode %{
10666 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10667 %}
10668 ins_pipe(pipe_slow); // XXX
10669 %}
10670
10671 instruct convI2D_reg_reg(regD dst, rRegI src)
10672 %{
10673 predicate(!UseXmmI2D);
10674 match(Set dst (ConvI2D src));
10675
10676 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10677 ins_encode %{
10678 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10679 %}
10680 ins_pipe(pipe_slow); // XXX
10681 %}
10682
10683 instruct convI2D_reg_mem(regD dst, memory src)
10684 %{
10685 match(Set dst (ConvI2D (LoadI src)));
10686
10687 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10688 ins_encode %{
10689 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10690 %}
10691 ins_pipe(pipe_slow); // XXX
10692 %}
10693
10694 instruct convXI2F_reg(regF dst, rRegI src)
10695 %{
10696 predicate(UseXmmI2F);
10697 match(Set dst (ConvI2F src));
10698
10699 format %{ "movdl $dst, $src\n\t"
10700 "cvtdq2psl $dst, $dst\t# i2f" %}
10701 ins_encode %{
10702 __ movdl($dst$$XMMRegister, $src$$Register);
10703 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10704 %}
10705 ins_pipe(pipe_slow); // XXX
10706 %}
10707
10708 instruct convXI2D_reg(regD dst, rRegI src)
10709 %{
10710 predicate(UseXmmI2D);
10711 match(Set dst (ConvI2D src));
10712
10713 format %{ "movdl $dst, $src\n\t"
10714 "cvtdq2pdl $dst, $dst\t# i2d" %}
10715 ins_encode %{
10716 __ movdl($dst$$XMMRegister, $src$$Register);
10717 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10718 %}
10719 ins_pipe(pipe_slow); // XXX
10720 %}
10721
10722 instruct convL2F_reg_reg(regF dst, rRegL src)
10723 %{
10724 match(Set dst (ConvL2F src));
10725
10726 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10727 ins_encode %{
10728 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10729 %}
10730 ins_pipe(pipe_slow); // XXX
10731 %}
10732
10733 instruct convL2F_reg_mem(regF dst, memory src)
10734 %{
10735 match(Set dst (ConvL2F (LoadL src)));
10736
10737 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10738 ins_encode %{
10739 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10740 %}
10741 ins_pipe(pipe_slow); // XXX
10742 %}
10743
10744 instruct convL2D_reg_reg(regD dst, rRegL src)
10745 %{
10746 match(Set dst (ConvL2D src));
10747
10748 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10749 ins_encode %{
10750 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10751 %}
10752 ins_pipe(pipe_slow); // XXX
10753 %}
10754
10755 instruct convL2D_reg_mem(regD dst, memory src)
10756 %{
10757 match(Set dst (ConvL2D (LoadL src)));
10758
10759 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10760 ins_encode %{
10761 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10762 %}
10763 ins_pipe(pipe_slow); // XXX
10764 %}
10765
10766 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10767 %{
10768 match(Set dst (ConvI2L src));
10769
10770 ins_cost(125);
10771 format %{ "movslq $dst, $src\t# i2l" %}
10772 ins_encode %{
10773 __ movslq($dst$$Register, $src$$Register);
10774 %}
10775 ins_pipe(ialu_reg_reg);
10776 %}
10777
10778 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10779 // %{
10780 // match(Set dst (ConvI2L src));
10781 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10782 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10783 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10784 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10785 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10786 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10787
10788 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10789 // ins_encode(enc_copy(dst, src));
10790 // // opcode(0x63); // needs REX.W
10791 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10792 // ins_pipe(ialu_reg_reg);
10793 // %}
10794
10795 // Zero-extend convert int to long
10796 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10797 %{
10798 match(Set dst (AndL (ConvI2L src) mask));
10799
10800 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10801 ins_encode %{
10802 if ($dst$$reg != $src$$reg) {
10803 __ movl($dst$$Register, $src$$Register);
10804 }
10805 %}
10806 ins_pipe(ialu_reg_reg);
10807 %}
10808
10809 // Zero-extend convert int to long
10810 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10811 %{
10812 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10813
10814 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10815 ins_encode %{
10816 __ movl($dst$$Register, $src$$Address);
10817 %}
10818 ins_pipe(ialu_reg_mem);
10819 %}
10820
10821 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10822 %{
10823 match(Set dst (AndL src mask));
10824
10825 format %{ "movl $dst, $src\t# zero-extend long" %}
10826 ins_encode %{
10827 __ movl($dst$$Register, $src$$Register);
10828 %}
10829 ins_pipe(ialu_reg_reg);
10830 %}
10831
10832 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10833 %{
10834 match(Set dst (ConvL2I src));
10835
10836 format %{ "movl $dst, $src\t# l2i" %}
10837 ins_encode %{
10838 __ movl($dst$$Register, $src$$Register);
10839 %}
10840 ins_pipe(ialu_reg_reg);
10841 %}
10842
10843
10844 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10845 match(Set dst (MoveF2I src));
10846 effect(DEF dst, USE src);
10847
10848 ins_cost(125);
10849 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10850 ins_encode %{
10851 __ movl($dst$$Register, Address(rsp, $src$$disp));
10852 %}
10853 ins_pipe(ialu_reg_mem);
10854 %}
10855
10856 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10857 match(Set dst (MoveI2F src));
10858 effect(DEF dst, USE src);
10859
10860 ins_cost(125);
10861 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10862 ins_encode %{
10863 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10864 %}
10865 ins_pipe(pipe_slow);
10866 %}
10867
10868 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10869 match(Set dst (MoveD2L src));
10870 effect(DEF dst, USE src);
10871
10872 ins_cost(125);
10873 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10874 ins_encode %{
10875 __ movq($dst$$Register, Address(rsp, $src$$disp));
10876 %}
10877 ins_pipe(ialu_reg_mem);
10878 %}
10879
10880 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10881 predicate(!UseXmmLoadAndClearUpper);
10882 match(Set dst (MoveL2D src));
10883 effect(DEF dst, USE src);
10884
10885 ins_cost(125);
10886 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10887 ins_encode %{
10888 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10889 %}
10890 ins_pipe(pipe_slow);
10891 %}
10892
10893 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10894 predicate(UseXmmLoadAndClearUpper);
10895 match(Set dst (MoveL2D src));
10896 effect(DEF dst, USE src);
10897
10898 ins_cost(125);
10899 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10900 ins_encode %{
10901 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10902 %}
10903 ins_pipe(pipe_slow);
10904 %}
10905
10906
10907 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10908 match(Set dst (MoveF2I src));
10909 effect(DEF dst, USE src);
10910
10911 ins_cost(95); // XXX
10912 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10913 ins_encode %{
10914 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10915 %}
10916 ins_pipe(pipe_slow);
10917 %}
10918
10919 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10920 match(Set dst (MoveI2F src));
10921 effect(DEF dst, USE src);
10922
10923 ins_cost(100);
10924 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10925 ins_encode %{
10926 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10927 %}
10928 ins_pipe( ialu_mem_reg );
10929 %}
10930
10931 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10932 match(Set dst (MoveD2L src));
10933 effect(DEF dst, USE src);
10934
10935 ins_cost(95); // XXX
10936 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10937 ins_encode %{
10938 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10939 %}
10940 ins_pipe(pipe_slow);
10941 %}
10942
10943 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10944 match(Set dst (MoveL2D src));
10945 effect(DEF dst, USE src);
10946
10947 ins_cost(100);
10948 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10949 ins_encode %{
10950 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10951 %}
10952 ins_pipe(ialu_mem_reg);
10953 %}
10954
10955 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10956 match(Set dst (MoveF2I src));
10957 effect(DEF dst, USE src);
10958 ins_cost(85);
10959 format %{ "movd $dst,$src\t# MoveF2I" %}
10960 ins_encode %{
10961 __ movdl($dst$$Register, $src$$XMMRegister);
10962 %}
10963 ins_pipe( pipe_slow );
10964 %}
10965
10966 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10967 match(Set dst (MoveD2L src));
10968 effect(DEF dst, USE src);
10969 ins_cost(85);
10970 format %{ "movd $dst,$src\t# MoveD2L" %}
10971 ins_encode %{
10972 __ movdq($dst$$Register, $src$$XMMRegister);
10973 %}
10974 ins_pipe( pipe_slow );
10975 %}
10976
10977 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10978 match(Set dst (MoveI2F src));
10979 effect(DEF dst, USE src);
10980 ins_cost(100);
10981 format %{ "movd $dst,$src\t# MoveI2F" %}
10982 ins_encode %{
10983 __ movdl($dst$$XMMRegister, $src$$Register);
10984 %}
10985 ins_pipe( pipe_slow );
10986 %}
10987
10988 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10989 match(Set dst (MoveL2D src));
10990 effect(DEF dst, USE src);
10991 ins_cost(100);
10992 format %{ "movd $dst,$src\t# MoveL2D" %}
10993 ins_encode %{
10994 __ movdq($dst$$XMMRegister, $src$$Register);
10995 %}
10996 ins_pipe( pipe_slow );
10997 %}
10998
10999
11000 // =======================================================================
11001 // fast clearing of an array
11002 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11003 Universe dummy, rFlagsReg cr)
11004 %{
11005 predicate(!((ClearArrayNode*)n)->is_large());
11006 match(Set dummy (ClearArray cnt base));
11007 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11008
11009 format %{ $$template
11010 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11011 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11012 $$emit$$"jg LARGE\n\t"
11013 $$emit$$"dec rcx\n\t"
11014 $$emit$$"js DONE\t# Zero length\n\t"
11015 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11016 $$emit$$"dec rcx\n\t"
11017 $$emit$$"jge LOOP\n\t"
11018 $$emit$$"jmp DONE\n\t"
11019 $$emit$$"# LARGE:\n\t"
11020 if (UseFastStosb) {
11021 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11022 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11023 } else if (UseXMMForObjInit) {
11024 $$emit$$"mov rdi,rax\n\t"
11025 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11026 $$emit$$"jmpq L_zero_64_bytes\n\t"
11027 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11028 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11029 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11030 $$emit$$"add 0x40,rax\n\t"
11031 $$emit$$"# L_zero_64_bytes:\n\t"
11032 $$emit$$"sub 0x8,rcx\n\t"
11033 $$emit$$"jge L_loop\n\t"
11034 $$emit$$"add 0x4,rcx\n\t"
11035 $$emit$$"jl L_tail\n\t"
11036 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11037 $$emit$$"add 0x20,rax\n\t"
11038 $$emit$$"sub 0x4,rcx\n\t"
11039 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11040 $$emit$$"add 0x4,rcx\n\t"
11041 $$emit$$"jle L_end\n\t"
11042 $$emit$$"dec rcx\n\t"
11043 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11044 $$emit$$"vmovq xmm0,(rax)\n\t"
11045 $$emit$$"add 0x8,rax\n\t"
11046 $$emit$$"dec rcx\n\t"
11047 $$emit$$"jge L_sloop\n\t"
11048 $$emit$$"# L_end:\n\t"
11049 } else {
11050 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11051 }
11052 $$emit$$"# DONE"
11053 %}
11054 ins_encode %{
11055 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11056 $tmp$$XMMRegister, false);
11057 %}
11058 ins_pipe(pipe_slow);
11059 %}
11060
11061 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11062 Universe dummy, rFlagsReg cr)
11063 %{
11064 predicate(((ClearArrayNode*)n)->is_large());
11065 match(Set dummy (ClearArray cnt base));
11066 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11067
11068 format %{ $$template
11069 if (UseFastStosb) {
11070 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11071 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11072 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11073 } else if (UseXMMForObjInit) {
11074 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11075 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11076 $$emit$$"jmpq L_zero_64_bytes\n\t"
11077 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11078 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11079 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11080 $$emit$$"add 0x40,rax\n\t"
11081 $$emit$$"# L_zero_64_bytes:\n\t"
11082 $$emit$$"sub 0x8,rcx\n\t"
11083 $$emit$$"jge L_loop\n\t"
11084 $$emit$$"add 0x4,rcx\n\t"
11085 $$emit$$"jl L_tail\n\t"
11086 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11087 $$emit$$"add 0x20,rax\n\t"
11088 $$emit$$"sub 0x4,rcx\n\t"
11089 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11090 $$emit$$"add 0x4,rcx\n\t"
11091 $$emit$$"jle L_end\n\t"
11092 $$emit$$"dec rcx\n\t"
11093 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11094 $$emit$$"vmovq xmm0,(rax)\n\t"
11095 $$emit$$"add 0x8,rax\n\t"
11096 $$emit$$"dec rcx\n\t"
11097 $$emit$$"jge L_sloop\n\t"
11098 $$emit$$"# L_end:\n\t"
11099 } else {
11100 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11101 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11102 }
11103 %}
11104 ins_encode %{
11105 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11106 $tmp$$XMMRegister, true);
11107 %}
11108 ins_pipe(pipe_slow);
11109 %}
11110
11111 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11112 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11113 %{
11114 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11115 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11116 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11117
11118 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11119 ins_encode %{
11120 __ string_compare($str1$$Register, $str2$$Register,
11121 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11122 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11123 %}
11124 ins_pipe( pipe_slow );
11125 %}
11126
11127 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11128 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11129 %{
11130 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11131 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11132 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11133
11134 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11135 ins_encode %{
11136 __ string_compare($str1$$Register, $str2$$Register,
11137 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11138 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11139 %}
11140 ins_pipe( pipe_slow );
11141 %}
11142
11143 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11144 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11145 %{
11146 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11147 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11148 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11149
11150 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11151 ins_encode %{
11152 __ string_compare($str1$$Register, $str2$$Register,
11153 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11154 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11155 %}
11156 ins_pipe( pipe_slow );
11157 %}
11158
11159 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11160 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11161 %{
11162 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11163 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11164 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11165
11166 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11167 ins_encode %{
11168 __ string_compare($str2$$Register, $str1$$Register,
11169 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11170 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11171 %}
11172 ins_pipe( pipe_slow );
11173 %}
11174
11175 // fast search of substring with known size.
11176 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11177 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11178 %{
11179 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11180 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11181 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11182
11183 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11184 ins_encode %{
11185 int icnt2 = (int)$int_cnt2$$constant;
11186 if (icnt2 >= 16) {
11187 // IndexOf for constant substrings with size >= 16 elements
11188 // which don't need to be loaded through stack.
11189 __ string_indexofC8($str1$$Register, $str2$$Register,
11190 $cnt1$$Register, $cnt2$$Register,
11191 icnt2, $result$$Register,
11192 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11193 } else {
11194 // Small strings are loaded through stack if they cross page boundary.
11195 __ string_indexof($str1$$Register, $str2$$Register,
11196 $cnt1$$Register, $cnt2$$Register,
11197 icnt2, $result$$Register,
11198 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11199 }
11200 %}
11201 ins_pipe( pipe_slow );
11202 %}
11203
11204 // fast search of substring with known size.
11205 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11206 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11207 %{
11208 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11209 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11210 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11211
11212 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11213 ins_encode %{
11214 int icnt2 = (int)$int_cnt2$$constant;
11215 if (icnt2 >= 8) {
11216 // IndexOf for constant substrings with size >= 8 elements
11217 // which don't need to be loaded through stack.
11218 __ string_indexofC8($str1$$Register, $str2$$Register,
11219 $cnt1$$Register, $cnt2$$Register,
11220 icnt2, $result$$Register,
11221 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11222 } else {
11223 // Small strings are loaded through stack if they cross page boundary.
11224 __ string_indexof($str1$$Register, $str2$$Register,
11225 $cnt1$$Register, $cnt2$$Register,
11226 icnt2, $result$$Register,
11227 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11228 }
11229 %}
11230 ins_pipe( pipe_slow );
11231 %}
11232
11233 // fast search of substring with known size.
11234 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11235 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11236 %{
11237 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11238 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11239 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11240
11241 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11242 ins_encode %{
11243 int icnt2 = (int)$int_cnt2$$constant;
11244 if (icnt2 >= 8) {
11245 // IndexOf for constant substrings with size >= 8 elements
11246 // which don't need to be loaded through stack.
11247 __ string_indexofC8($str1$$Register, $str2$$Register,
11248 $cnt1$$Register, $cnt2$$Register,
11249 icnt2, $result$$Register,
11250 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11251 } else {
11252 // Small strings are loaded through stack if they cross page boundary.
11253 __ string_indexof($str1$$Register, $str2$$Register,
11254 $cnt1$$Register, $cnt2$$Register,
11255 icnt2, $result$$Register,
11256 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11257 }
11258 %}
11259 ins_pipe( pipe_slow );
11260 %}
11261
11262 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11263 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11264 %{
11265 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11266 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11267 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11268
11269 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11270 ins_encode %{
11271 __ string_indexof($str1$$Register, $str2$$Register,
11272 $cnt1$$Register, $cnt2$$Register,
11273 (-1), $result$$Register,
11274 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11275 %}
11276 ins_pipe( pipe_slow );
11277 %}
11278
11279 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11280 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11281 %{
11282 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11283 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11284 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11285
11286 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11287 ins_encode %{
11288 __ string_indexof($str1$$Register, $str2$$Register,
11289 $cnt1$$Register, $cnt2$$Register,
11290 (-1), $result$$Register,
11291 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11292 %}
11293 ins_pipe( pipe_slow );
11294 %}
11295
11296 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11297 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11298 %{
11299 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11300 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11301 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11302
11303 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11304 ins_encode %{
11305 __ string_indexof($str1$$Register, $str2$$Register,
11306 $cnt1$$Register, $cnt2$$Register,
11307 (-1), $result$$Register,
11308 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11309 %}
11310 ins_pipe( pipe_slow );
11311 %}
11312
11313 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11314 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11315 %{
11316 predicate(UseSSE42Intrinsics);
11317 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11318 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11319 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11320 ins_encode %{
11321 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11322 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11323 %}
11324 ins_pipe( pipe_slow );
11325 %}
11326
11327 // fast string equals
11328 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11329 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11330 %{
11331 match(Set result (StrEquals (Binary str1 str2) cnt));
11332 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11333
11334 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11335 ins_encode %{
11336 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11337 $cnt$$Register, $result$$Register, $tmp3$$Register,
11338 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11339 %}
11340 ins_pipe( pipe_slow );
11341 %}
11342
11343 // fast array equals
11344 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11345 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11346 %{
11347 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11348 match(Set result (AryEq ary1 ary2));
11349 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11350
11351 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11352 ins_encode %{
11353 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11354 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11355 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11356 %}
11357 ins_pipe( pipe_slow );
11358 %}
11359
11360 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11361 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11362 %{
11363 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11364 match(Set result (AryEq ary1 ary2));
11365 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11366
11367 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11368 ins_encode %{
11369 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11370 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11371 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11372 %}
11373 ins_pipe( pipe_slow );
11374 %}
11375
11376 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11377 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11378 %{
11379 match(Set result (HasNegatives ary1 len));
11380 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11381
11382 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11383 ins_encode %{
11384 __ has_negatives($ary1$$Register, $len$$Register,
11385 $result$$Register, $tmp3$$Register,
11386 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11387 %}
11388 ins_pipe( pipe_slow );
11389 %}
11390
11391 // fast char[] to byte[] compression
11392 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11393 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11394 match(Set result (StrCompressedCopy src (Binary dst len)));
11395 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11396
11397 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11398 ins_encode %{
11399 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11400 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11401 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11402 %}
11403 ins_pipe( pipe_slow );
11404 %}
11405
11406 // fast byte[] to char[] inflation
11407 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11408 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11409 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11410 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11411
11412 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11413 ins_encode %{
11414 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11415 $tmp1$$XMMRegister, $tmp2$$Register);
11416 %}
11417 ins_pipe( pipe_slow );
11418 %}
11419
11420 // encode char[] to byte[] in ISO_8859_1
11421 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11422 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11423 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11424 match(Set result (EncodeISOArray src (Binary dst len)));
11425 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11426
11427 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11428 ins_encode %{
11429 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11430 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11431 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11432 %}
11433 ins_pipe( pipe_slow );
11434 %}
11435
11436 //----------Overflow Math Instructions-----------------------------------------
11437
11438 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11439 %{
11440 match(Set cr (OverflowAddI op1 op2));
11441 effect(DEF cr, USE_KILL op1, USE op2);
11442
11443 format %{ "addl $op1, $op2\t# overflow check int" %}
11444
11445 ins_encode %{
11446 __ addl($op1$$Register, $op2$$Register);
11447 %}
11448 ins_pipe(ialu_reg_reg);
11449 %}
11450
11451 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11452 %{
11453 match(Set cr (OverflowAddI op1 op2));
11454 effect(DEF cr, USE_KILL op1, USE op2);
11455
11456 format %{ "addl $op1, $op2\t# overflow check int" %}
11457
11458 ins_encode %{
11459 __ addl($op1$$Register, $op2$$constant);
11460 %}
11461 ins_pipe(ialu_reg_reg);
11462 %}
11463
11464 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11465 %{
11466 match(Set cr (OverflowAddL op1 op2));
11467 effect(DEF cr, USE_KILL op1, USE op2);
11468
11469 format %{ "addq $op1, $op2\t# overflow check long" %}
11470 ins_encode %{
11471 __ addq($op1$$Register, $op2$$Register);
11472 %}
11473 ins_pipe(ialu_reg_reg);
11474 %}
11475
11476 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11477 %{
11478 match(Set cr (OverflowAddL op1 op2));
11479 effect(DEF cr, USE_KILL op1, USE op2);
11480
11481 format %{ "addq $op1, $op2\t# overflow check long" %}
11482 ins_encode %{
11483 __ addq($op1$$Register, $op2$$constant);
11484 %}
11485 ins_pipe(ialu_reg_reg);
11486 %}
11487
11488 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11489 %{
11490 match(Set cr (OverflowSubI op1 op2));
11491
11492 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11493 ins_encode %{
11494 __ cmpl($op1$$Register, $op2$$Register);
11495 %}
11496 ins_pipe(ialu_reg_reg);
11497 %}
11498
11499 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11500 %{
11501 match(Set cr (OverflowSubI op1 op2));
11502
11503 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11504 ins_encode %{
11505 __ cmpl($op1$$Register, $op2$$constant);
11506 %}
11507 ins_pipe(ialu_reg_reg);
11508 %}
11509
11510 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11511 %{
11512 match(Set cr (OverflowSubL op1 op2));
11513
11514 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11515 ins_encode %{
11516 __ cmpq($op1$$Register, $op2$$Register);
11517 %}
11518 ins_pipe(ialu_reg_reg);
11519 %}
11520
11521 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11522 %{
11523 match(Set cr (OverflowSubL op1 op2));
11524
11525 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11526 ins_encode %{
11527 __ cmpq($op1$$Register, $op2$$constant);
11528 %}
11529 ins_pipe(ialu_reg_reg);
11530 %}
11531
11532 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11533 %{
11534 match(Set cr (OverflowSubI zero op2));
11535 effect(DEF cr, USE_KILL op2);
11536
11537 format %{ "negl $op2\t# overflow check int" %}
11538 ins_encode %{
11539 __ negl($op2$$Register);
11540 %}
11541 ins_pipe(ialu_reg_reg);
11542 %}
11543
11544 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11545 %{
11546 match(Set cr (OverflowSubL zero op2));
11547 effect(DEF cr, USE_KILL op2);
11548
11549 format %{ "negq $op2\t# overflow check long" %}
11550 ins_encode %{
11551 __ negq($op2$$Register);
11552 %}
11553 ins_pipe(ialu_reg_reg);
11554 %}
11555
11556 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11557 %{
11558 match(Set cr (OverflowMulI op1 op2));
11559 effect(DEF cr, USE_KILL op1, USE op2);
11560
11561 format %{ "imull $op1, $op2\t# overflow check int" %}
11562 ins_encode %{
11563 __ imull($op1$$Register, $op2$$Register);
11564 %}
11565 ins_pipe(ialu_reg_reg_alu0);
11566 %}
11567
11568 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11569 %{
11570 match(Set cr (OverflowMulI op1 op2));
11571 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11572
11573 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11574 ins_encode %{
11575 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11576 %}
11577 ins_pipe(ialu_reg_reg_alu0);
11578 %}
11579
11580 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11581 %{
11582 match(Set cr (OverflowMulL op1 op2));
11583 effect(DEF cr, USE_KILL op1, USE op2);
11584
11585 format %{ "imulq $op1, $op2\t# overflow check long" %}
11586 ins_encode %{
11587 __ imulq($op1$$Register, $op2$$Register);
11588 %}
11589 ins_pipe(ialu_reg_reg_alu0);
11590 %}
11591
11592 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11593 %{
11594 match(Set cr (OverflowMulL op1 op2));
11595 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11596
11597 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11598 ins_encode %{
11599 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11600 %}
11601 ins_pipe(ialu_reg_reg_alu0);
11602 %}
11603
11604
11605 //----------Control Flow Instructions------------------------------------------
11606 // Signed compare Instructions
11607
11608 // XXX more variants!!
11609 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11610 %{
11611 match(Set cr (CmpI op1 op2));
11612 effect(DEF cr, USE op1, USE op2);
11613
11614 format %{ "cmpl $op1, $op2" %}
11615 opcode(0x3B); /* Opcode 3B /r */
11616 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11617 ins_pipe(ialu_cr_reg_reg);
11618 %}
11619
11620 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11621 %{
11622 match(Set cr (CmpI op1 op2));
11623
11624 format %{ "cmpl $op1, $op2" %}
11625 opcode(0x81, 0x07); /* Opcode 81 /7 */
11626 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11627 ins_pipe(ialu_cr_reg_imm);
11628 %}
11629
11630 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11631 %{
11632 match(Set cr (CmpI op1 (LoadI op2)));
11633
11634 ins_cost(500); // XXX
11635 format %{ "cmpl $op1, $op2" %}
11636 opcode(0x3B); /* Opcode 3B /r */
11637 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11638 ins_pipe(ialu_cr_reg_mem);
11639 %}
11640
11641 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11642 %{
11643 match(Set cr (CmpI src zero));
11644
11645 format %{ "testl $src, $src" %}
11646 opcode(0x85);
11647 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11648 ins_pipe(ialu_cr_reg_imm);
11649 %}
11650
11651 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11652 %{
11653 match(Set cr (CmpI (AndI src con) zero));
11654
11655 format %{ "testl $src, $con" %}
11656 opcode(0xF7, 0x00);
11657 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11658 ins_pipe(ialu_cr_reg_imm);
11659 %}
11660
11661 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11662 %{
11663 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11664
11665 format %{ "testl $src, $mem" %}
11666 opcode(0x85);
11667 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11668 ins_pipe(ialu_cr_reg_mem);
11669 %}
11670
11671 // Unsigned compare Instructions; really, same as signed except they
11672 // produce an rFlagsRegU instead of rFlagsReg.
11673 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11674 %{
11675 match(Set cr (CmpU op1 op2));
11676
11677 format %{ "cmpl $op1, $op2\t# unsigned" %}
11678 opcode(0x3B); /* Opcode 3B /r */
11679 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11680 ins_pipe(ialu_cr_reg_reg);
11681 %}
11682
11683 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11684 %{
11685 match(Set cr (CmpU op1 op2));
11686
11687 format %{ "cmpl $op1, $op2\t# unsigned" %}
11688 opcode(0x81,0x07); /* Opcode 81 /7 */
11689 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11690 ins_pipe(ialu_cr_reg_imm);
11691 %}
11692
11693 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11694 %{
11695 match(Set cr (CmpU op1 (LoadI op2)));
11696
11697 ins_cost(500); // XXX
11698 format %{ "cmpl $op1, $op2\t# unsigned" %}
11699 opcode(0x3B); /* Opcode 3B /r */
11700 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11701 ins_pipe(ialu_cr_reg_mem);
11702 %}
11703
11704 // // // Cisc-spilled version of cmpU_rReg
11705 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11706 // //%{
11707 // // match(Set cr (CmpU (LoadI op1) op2));
11708 // //
11709 // // format %{ "CMPu $op1,$op2" %}
11710 // // ins_cost(500);
11711 // // opcode(0x39); /* Opcode 39 /r */
11712 // // ins_encode( OpcP, reg_mem( op1, op2) );
11713 // //%}
11714
11715 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11716 %{
11717 match(Set cr (CmpU src zero));
11718
11719 format %{ "testl $src, $src\t# unsigned" %}
11720 opcode(0x85);
11721 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11722 ins_pipe(ialu_cr_reg_imm);
11723 %}
11724
11725 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11726 %{
11727 match(Set cr (CmpP op1 op2));
11728
11729 format %{ "cmpq $op1, $op2\t# ptr" %}
11730 opcode(0x3B); /* Opcode 3B /r */
11731 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11732 ins_pipe(ialu_cr_reg_reg);
11733 %}
11734
11735 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11736 %{
11737 match(Set cr (CmpP op1 (LoadP op2)));
11738
11739 ins_cost(500); // XXX
11740 format %{ "cmpq $op1, $op2\t# ptr" %}
11741 opcode(0x3B); /* Opcode 3B /r */
11742 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11743 ins_pipe(ialu_cr_reg_mem);
11744 %}
11745
11746 // // // Cisc-spilled version of cmpP_rReg
11747 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11748 // //%{
11749 // // match(Set cr (CmpP (LoadP op1) op2));
11750 // //
11751 // // format %{ "CMPu $op1,$op2" %}
11752 // // ins_cost(500);
11753 // // opcode(0x39); /* Opcode 39 /r */
11754 // // ins_encode( OpcP, reg_mem( op1, op2) );
11755 // //%}
11756
11757 // XXX this is generalized by compP_rReg_mem???
11758 // Compare raw pointer (used in out-of-heap check).
11759 // Only works because non-oop pointers must be raw pointers
11760 // and raw pointers have no anti-dependencies.
11761 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11762 %{
11763 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11764 match(Set cr (CmpP op1 (LoadP op2)));
11765
11766 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11767 opcode(0x3B); /* Opcode 3B /r */
11768 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11769 ins_pipe(ialu_cr_reg_mem);
11770 %}
11771
11772 // This will generate a signed flags result. This should be OK since
11773 // any compare to a zero should be eq/neq.
11774 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11775 %{
11776 match(Set cr (CmpP src zero));
11777
11778 format %{ "testq $src, $src\t# ptr" %}
11779 opcode(0x85);
11780 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11781 ins_pipe(ialu_cr_reg_imm);
11782 %}
11783
11784 // This will generate a signed flags result. This should be OK since
11785 // any compare to a zero should be eq/neq.
11786 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11787 %{
11788 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11789 match(Set cr (CmpP (LoadP op) zero));
11790
11791 ins_cost(500); // XXX
11792 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11793 opcode(0xF7); /* Opcode F7 /0 */
11794 ins_encode(REX_mem_wide(op),
11795 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11796 ins_pipe(ialu_cr_reg_imm);
11797 %}
11798
11799 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11800 %{
11801 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11802 match(Set cr (CmpP (LoadP mem) zero));
11803
11804 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11805 ins_encode %{
11806 __ cmpq(r12, $mem$$Address);
11807 %}
11808 ins_pipe(ialu_cr_reg_mem);
11809 %}
11810
11811 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11812 %{
11813 match(Set cr (CmpN op1 op2));
11814
11815 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11816 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11817 ins_pipe(ialu_cr_reg_reg);
11818 %}
11819
11820 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11821 %{
11822 match(Set cr (CmpN src (LoadN mem)));
11823
11824 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11825 ins_encode %{
11826 __ cmpl($src$$Register, $mem$$Address);
11827 %}
11828 ins_pipe(ialu_cr_reg_mem);
11829 %}
11830
11831 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11832 match(Set cr (CmpN op1 op2));
11833
11834 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11835 ins_encode %{
11836 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11837 %}
11838 ins_pipe(ialu_cr_reg_imm);
11839 %}
11840
11841 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11842 %{
11843 match(Set cr (CmpN src (LoadN mem)));
11844
11845 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11846 ins_encode %{
11847 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11848 %}
11849 ins_pipe(ialu_cr_reg_mem);
11850 %}
11851
11852 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11853 match(Set cr (CmpN op1 op2));
11854
11855 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11856 ins_encode %{
11857 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11858 %}
11859 ins_pipe(ialu_cr_reg_imm);
11860 %}
11861
11862 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11863 %{
11864 match(Set cr (CmpN src (LoadNKlass mem)));
11865
11866 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11867 ins_encode %{
11868 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11869 %}
11870 ins_pipe(ialu_cr_reg_mem);
11871 %}
11872
11873 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11874 match(Set cr (CmpN src zero));
11875
11876 format %{ "testl $src, $src\t# compressed ptr" %}
11877 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11878 ins_pipe(ialu_cr_reg_imm);
11879 %}
11880
11881 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11882 %{
11883 predicate(Universe::narrow_oop_base() != NULL);
11884 match(Set cr (CmpN (LoadN mem) zero));
11885
11886 ins_cost(500); // XXX
11887 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11888 ins_encode %{
11889 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11890 %}
11891 ins_pipe(ialu_cr_reg_mem);
11892 %}
11893
11894 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11895 %{
11896 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11897 match(Set cr (CmpN (LoadN mem) zero));
11898
11899 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11900 ins_encode %{
11901 __ cmpl(r12, $mem$$Address);
11902 %}
11903 ins_pipe(ialu_cr_reg_mem);
11904 %}
11905
11906 // Yanked all unsigned pointer compare operations.
11907 // Pointer compares are done with CmpP which is already unsigned.
11908
11909 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11910 %{
11911 match(Set cr (CmpL op1 op2));
11912
11913 format %{ "cmpq $op1, $op2" %}
11914 opcode(0x3B); /* Opcode 3B /r */
11915 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11916 ins_pipe(ialu_cr_reg_reg);
11917 %}
11918
11919 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11920 %{
11921 match(Set cr (CmpL op1 op2));
11922
11923 format %{ "cmpq $op1, $op2" %}
11924 opcode(0x81, 0x07); /* Opcode 81 /7 */
11925 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11926 ins_pipe(ialu_cr_reg_imm);
11927 %}
11928
11929 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11930 %{
11931 match(Set cr (CmpL op1 (LoadL op2)));
11932
11933 format %{ "cmpq $op1, $op2" %}
11934 opcode(0x3B); /* Opcode 3B /r */
11935 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11936 ins_pipe(ialu_cr_reg_mem);
11937 %}
11938
11939 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11940 %{
11941 match(Set cr (CmpL src zero));
11942
11943 format %{ "testq $src, $src" %}
11944 opcode(0x85);
11945 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11946 ins_pipe(ialu_cr_reg_imm);
11947 %}
11948
11949 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11950 %{
11951 match(Set cr (CmpL (AndL src con) zero));
11952
11953 format %{ "testq $src, $con\t# long" %}
11954 opcode(0xF7, 0x00);
11955 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11956 ins_pipe(ialu_cr_reg_imm);
11957 %}
11958
11959 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11960 %{
11961 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11962
11963 format %{ "testq $src, $mem" %}
11964 opcode(0x85);
11965 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11966 ins_pipe(ialu_cr_reg_mem);
11967 %}
11968
11969 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11970 %{
11971 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11972
11973 format %{ "testq $src, $mem" %}
11974 opcode(0x85);
11975 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11976 ins_pipe(ialu_cr_reg_mem);
11977 %}
11978
11979 // Manifest a CmpL result in an integer register. Very painful.
11980 // This is the test to avoid.
11981 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11982 %{
11983 match(Set dst (CmpL3 src1 src2));
11984 effect(KILL flags);
11985
11986 ins_cost(275); // XXX
11987 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11988 "movl $dst, -1\n\t"
11989 "jl,s done\n\t"
11990 "setne $dst\n\t"
11991 "movzbl $dst, $dst\n\t"
11992 "done:" %}
11993 ins_encode(cmpl3_flag(src1, src2, dst));
11994 ins_pipe(pipe_slow);
11995 %}
11996
11997 // Unsigned long compare Instructions; really, same as signed long except they
11998 // produce an rFlagsRegU instead of rFlagsReg.
11999 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12000 %{
12001 match(Set cr (CmpUL op1 op2));
12002
12003 format %{ "cmpq $op1, $op2\t# unsigned" %}
12004 opcode(0x3B); /* Opcode 3B /r */
12005 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12006 ins_pipe(ialu_cr_reg_reg);
12007 %}
12008
12009 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12010 %{
12011 match(Set cr (CmpUL op1 op2));
12012
12013 format %{ "cmpq $op1, $op2\t# unsigned" %}
12014 opcode(0x81, 0x07); /* Opcode 81 /7 */
12015 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12016 ins_pipe(ialu_cr_reg_imm);
12017 %}
12018
12019 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12020 %{
12021 match(Set cr (CmpUL op1 (LoadL op2)));
12022
12023 format %{ "cmpq $op1, $op2\t# unsigned" %}
12024 opcode(0x3B); /* Opcode 3B /r */
12025 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12026 ins_pipe(ialu_cr_reg_mem);
12027 %}
12028
12029 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12030 %{
12031 match(Set cr (CmpUL src zero));
12032
12033 format %{ "testq $src, $src\t# unsigned" %}
12034 opcode(0x85);
12035 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12036 ins_pipe(ialu_cr_reg_imm);
12037 %}
12038
12039 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12040 %{
12041 match(Set cr (CmpI (LoadB mem) imm));
12042
12043 ins_cost(125);
12044 format %{ "cmpb $mem, $imm" %}
12045 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12046 ins_pipe(ialu_cr_reg_mem);
12047 %}
12048
12049 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12050 %{
12051 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12052
12053 ins_cost(125);
12054 format %{ "testb $mem, $imm" %}
12055 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12056 ins_pipe(ialu_cr_reg_mem);
12057 %}
12058
12059 //----------Max and Min--------------------------------------------------------
12060 // Min Instructions
12061
12062 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12063 %{
12064 effect(USE_DEF dst, USE src, USE cr);
12065
12066 format %{ "cmovlgt $dst, $src\t# min" %}
12067 opcode(0x0F, 0x4F);
12068 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12069 ins_pipe(pipe_cmov_reg);
12070 %}
12071
12072
12073 instruct minI_rReg(rRegI dst, rRegI src)
12074 %{
12075 match(Set dst (MinI dst src));
12076
12077 ins_cost(200);
12078 expand %{
12079 rFlagsReg cr;
12080 compI_rReg(cr, dst, src);
12081 cmovI_reg_g(dst, src, cr);
12082 %}
12083 %}
12084
12085 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12086 %{
12087 effect(USE_DEF dst, USE src, USE cr);
12088
12089 format %{ "cmovllt $dst, $src\t# max" %}
12090 opcode(0x0F, 0x4C);
12091 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12092 ins_pipe(pipe_cmov_reg);
12093 %}
12094
12095
12096 instruct maxI_rReg(rRegI dst, rRegI src)
12097 %{
12098 match(Set dst (MaxI dst src));
12099
12100 ins_cost(200);
12101 expand %{
12102 rFlagsReg cr;
12103 compI_rReg(cr, dst, src);
12104 cmovI_reg_l(dst, src, cr);
12105 %}
12106 %}
12107
12108 // ============================================================================
12109 // Branch Instructions
12110
12111 // Jump Direct - Label defines a relative address from JMP+1
12112 instruct jmpDir(label labl)
12113 %{
12114 match(Goto);
12115 effect(USE labl);
12116
12117 ins_cost(300);
12118 format %{ "jmp $labl" %}
12119 size(5);
12120 ins_encode %{
12121 Label* L = $labl$$label;
12122 __ jmp(*L, false); // Always long jump
12123 %}
12124 ins_pipe(pipe_jmp);
12125 %}
12126
12127 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12128 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12129 %{
12130 match(If cop cr);
12131 effect(USE labl);
12132
12133 ins_cost(300);
12134 format %{ "j$cop $labl" %}
12135 size(6);
12136 ins_encode %{
12137 Label* L = $labl$$label;
12138 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12139 %}
12140 ins_pipe(pipe_jcc);
12141 %}
12142
12143 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12144 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12145 %{
12146 predicate(!n->has_vector_mask_set());
12147 match(CountedLoopEnd cop cr);
12148 effect(USE labl);
12149
12150 ins_cost(300);
12151 format %{ "j$cop $labl\t# loop end" %}
12152 size(6);
12153 ins_encode %{
12154 Label* L = $labl$$label;
12155 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12156 %}
12157 ins_pipe(pipe_jcc);
12158 %}
12159
12160 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12161 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12162 predicate(!n->has_vector_mask_set());
12163 match(CountedLoopEnd cop cmp);
12164 effect(USE labl);
12165
12166 ins_cost(300);
12167 format %{ "j$cop,u $labl\t# loop end" %}
12168 size(6);
12169 ins_encode %{
12170 Label* L = $labl$$label;
12171 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12172 %}
12173 ins_pipe(pipe_jcc);
12174 %}
12175
12176 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12177 predicate(!n->has_vector_mask_set());
12178 match(CountedLoopEnd cop cmp);
12179 effect(USE labl);
12180
12181 ins_cost(200);
12182 format %{ "j$cop,u $labl\t# loop end" %}
12183 size(6);
12184 ins_encode %{
12185 Label* L = $labl$$label;
12186 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12187 %}
12188 ins_pipe(pipe_jcc);
12189 %}
12190
12191 // mask version
12192 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12193 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12194 %{
12195 predicate(n->has_vector_mask_set());
12196 match(CountedLoopEnd cop cr);
12197 effect(USE labl);
12198
12199 ins_cost(400);
12200 format %{ "j$cop $labl\t# loop end\n\t"
12201 "restorevectmask \t# vector mask restore for loops" %}
12202 size(10);
12203 ins_encode %{
12204 Label* L = $labl$$label;
12205 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12206 __ restorevectmask();
12207 %}
12208 ins_pipe(pipe_jcc);
12209 %}
12210
12211 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12212 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12213 predicate(n->has_vector_mask_set());
12214 match(CountedLoopEnd cop cmp);
12215 effect(USE labl);
12216
12217 ins_cost(400);
12218 format %{ "j$cop,u $labl\t# loop end\n\t"
12219 "restorevectmask \t# vector mask restore for loops" %}
12220 size(10);
12221 ins_encode %{
12222 Label* L = $labl$$label;
12223 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12224 __ restorevectmask();
12225 %}
12226 ins_pipe(pipe_jcc);
12227 %}
12228
12229 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12230 predicate(n->has_vector_mask_set());
12231 match(CountedLoopEnd cop cmp);
12232 effect(USE labl);
12233
12234 ins_cost(300);
12235 format %{ "j$cop,u $labl\t# loop end\n\t"
12236 "restorevectmask \t# vector mask restore for loops" %}
12237 size(10);
12238 ins_encode %{
12239 Label* L = $labl$$label;
12240 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12241 __ restorevectmask();
12242 %}
12243 ins_pipe(pipe_jcc);
12244 %}
12245
12246 // Jump Direct Conditional - using unsigned comparison
12247 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12248 match(If cop cmp);
12249 effect(USE labl);
12250
12251 ins_cost(300);
12252 format %{ "j$cop,u $labl" %}
12253 size(6);
12254 ins_encode %{
12255 Label* L = $labl$$label;
12256 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12257 %}
12258 ins_pipe(pipe_jcc);
12259 %}
12260
12261 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12262 match(If cop cmp);
12263 effect(USE labl);
12264
12265 ins_cost(200);
12266 format %{ "j$cop,u $labl" %}
12267 size(6);
12268 ins_encode %{
12269 Label* L = $labl$$label;
12270 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12271 %}
12272 ins_pipe(pipe_jcc);
12273 %}
12274
12275 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12276 match(If cop cmp);
12277 effect(USE labl);
12278
12279 ins_cost(200);
12280 format %{ $$template
12281 if ($cop$$cmpcode == Assembler::notEqual) {
12282 $$emit$$"jp,u $labl\n\t"
12283 $$emit$$"j$cop,u $labl"
12284 } else {
12285 $$emit$$"jp,u done\n\t"
12286 $$emit$$"j$cop,u $labl\n\t"
12287 $$emit$$"done:"
12288 }
12289 %}
12290 ins_encode %{
12291 Label* l = $labl$$label;
12292 if ($cop$$cmpcode == Assembler::notEqual) {
12293 __ jcc(Assembler::parity, *l, false);
12294 __ jcc(Assembler::notEqual, *l, false);
12295 } else if ($cop$$cmpcode == Assembler::equal) {
12296 Label done;
12297 __ jccb(Assembler::parity, done);
12298 __ jcc(Assembler::equal, *l, false);
12299 __ bind(done);
12300 } else {
12301 ShouldNotReachHere();
12302 }
12303 %}
12304 ins_pipe(pipe_jcc);
12305 %}
12306
12307 // ============================================================================
12308 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12309 // superklass array for an instance of the superklass. Set a hidden
12310 // internal cache on a hit (cache is checked with exposed code in
12311 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12312 // encoding ALSO sets flags.
12313
12314 instruct partialSubtypeCheck(rdi_RegP result,
12315 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12316 rFlagsReg cr)
12317 %{
12318 match(Set result (PartialSubtypeCheck sub super));
12319 effect(KILL rcx, KILL cr);
12320
12321 ins_cost(1100); // slightly larger than the next version
12322 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12323 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12324 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12325 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12326 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12327 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12328 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12329 "miss:\t" %}
12330
12331 opcode(0x1); // Force a XOR of RDI
12332 ins_encode(enc_PartialSubtypeCheck());
12333 ins_pipe(pipe_slow);
12334 %}
12335
12336 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12337 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12338 immP0 zero,
12339 rdi_RegP result)
12340 %{
12341 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12342 effect(KILL rcx, KILL result);
12343
12344 ins_cost(1000);
12345 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12346 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12347 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12348 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12349 "jne,s miss\t\t# Missed: flags nz\n\t"
12350 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12351 "miss:\t" %}
12352
12353 opcode(0x0); // No need to XOR RDI
12354 ins_encode(enc_PartialSubtypeCheck());
12355 ins_pipe(pipe_slow);
12356 %}
12357
12358 // ============================================================================
12359 // Branch Instructions -- short offset versions
12360 //
12361 // These instructions are used to replace jumps of a long offset (the default
12362 // match) with jumps of a shorter offset. These instructions are all tagged
12363 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12364 // match rules in general matching. Instead, the ADLC generates a conversion
12365 // method in the MachNode which can be used to do in-place replacement of the
12366 // long variant with the shorter variant. The compiler will determine if a
12367 // branch can be taken by the is_short_branch_offset() predicate in the machine
12368 // specific code section of the file.
12369
12370 // Jump Direct - Label defines a relative address from JMP+1
12371 instruct jmpDir_short(label labl) %{
12372 match(Goto);
12373 effect(USE labl);
12374
12375 ins_cost(300);
12376 format %{ "jmp,s $labl" %}
12377 size(2);
12378 ins_encode %{
12379 Label* L = $labl$$label;
12380 __ jmpb(*L);
12381 %}
12382 ins_pipe(pipe_jmp);
12383 ins_short_branch(1);
12384 %}
12385
12386 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12387 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12388 match(If cop cr);
12389 effect(USE labl);
12390
12391 ins_cost(300);
12392 format %{ "j$cop,s $labl" %}
12393 size(2);
12394 ins_encode %{
12395 Label* L = $labl$$label;
12396 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12397 %}
12398 ins_pipe(pipe_jcc);
12399 ins_short_branch(1);
12400 %}
12401
12402 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12403 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12404 match(CountedLoopEnd cop cr);
12405 effect(USE labl);
12406
12407 ins_cost(300);
12408 format %{ "j$cop,s $labl\t# loop end" %}
12409 size(2);
12410 ins_encode %{
12411 Label* L = $labl$$label;
12412 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12413 %}
12414 ins_pipe(pipe_jcc);
12415 ins_short_branch(1);
12416 %}
12417
12418 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12419 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12420 match(CountedLoopEnd cop cmp);
12421 effect(USE labl);
12422
12423 ins_cost(300);
12424 format %{ "j$cop,us $labl\t# loop end" %}
12425 size(2);
12426 ins_encode %{
12427 Label* L = $labl$$label;
12428 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12429 %}
12430 ins_pipe(pipe_jcc);
12431 ins_short_branch(1);
12432 %}
12433
12434 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12435 match(CountedLoopEnd cop cmp);
12436 effect(USE labl);
12437
12438 ins_cost(300);
12439 format %{ "j$cop,us $labl\t# loop end" %}
12440 size(2);
12441 ins_encode %{
12442 Label* L = $labl$$label;
12443 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12444 %}
12445 ins_pipe(pipe_jcc);
12446 ins_short_branch(1);
12447 %}
12448
12449 // Jump Direct Conditional - using unsigned comparison
12450 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12451 match(If cop cmp);
12452 effect(USE labl);
12453
12454 ins_cost(300);
12455 format %{ "j$cop,us $labl" %}
12456 size(2);
12457 ins_encode %{
12458 Label* L = $labl$$label;
12459 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12460 %}
12461 ins_pipe(pipe_jcc);
12462 ins_short_branch(1);
12463 %}
12464
12465 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12466 match(If cop cmp);
12467 effect(USE labl);
12468
12469 ins_cost(300);
12470 format %{ "j$cop,us $labl" %}
12471 size(2);
12472 ins_encode %{
12473 Label* L = $labl$$label;
12474 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12475 %}
12476 ins_pipe(pipe_jcc);
12477 ins_short_branch(1);
12478 %}
12479
12480 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12481 match(If cop cmp);
12482 effect(USE labl);
12483
12484 ins_cost(300);
12485 format %{ $$template
12486 if ($cop$$cmpcode == Assembler::notEqual) {
12487 $$emit$$"jp,u,s $labl\n\t"
12488 $$emit$$"j$cop,u,s $labl"
12489 } else {
12490 $$emit$$"jp,u,s done\n\t"
12491 $$emit$$"j$cop,u,s $labl\n\t"
12492 $$emit$$"done:"
12493 }
12494 %}
12495 size(4);
12496 ins_encode %{
12497 Label* l = $labl$$label;
12498 if ($cop$$cmpcode == Assembler::notEqual) {
12499 __ jccb(Assembler::parity, *l);
12500 __ jccb(Assembler::notEqual, *l);
12501 } else if ($cop$$cmpcode == Assembler::equal) {
12502 Label done;
12503 __ jccb(Assembler::parity, done);
12504 __ jccb(Assembler::equal, *l);
12505 __ bind(done);
12506 } else {
12507 ShouldNotReachHere();
12508 }
12509 %}
12510 ins_pipe(pipe_jcc);
12511 ins_short_branch(1);
12512 %}
12513
12514 // ============================================================================
12515 // inlined locking and unlocking
12516
12517 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12518 predicate(Compile::current()->use_rtm());
12519 match(Set cr (FastLock object box));
12520 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12521 ins_cost(300);
12522 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12523 ins_encode %{
12524 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12525 $scr$$Register, $cx1$$Register, $cx2$$Register,
12526 _counters, _rtm_counters, _stack_rtm_counters,
12527 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12528 true, ra_->C->profile_rtm());
12529 %}
12530 ins_pipe(pipe_slow);
12531 %}
12532
12533 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12534 predicate(!Compile::current()->use_rtm());
12535 match(Set cr (FastLock object box));
12536 effect(TEMP tmp, TEMP scr, USE_KILL box);
12537 ins_cost(300);
12538 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12539 ins_encode %{
12540 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12541 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12542 %}
12543 ins_pipe(pipe_slow);
12544 %}
12545
12546 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12547 match(Set cr (FastUnlock object box));
12548 effect(TEMP tmp, USE_KILL box);
12549 ins_cost(300);
12550 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12551 ins_encode %{
12552 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12553 %}
12554 ins_pipe(pipe_slow);
12555 %}
12556
12557
12558 // ============================================================================
12559 // Safepoint Instructions
12560 instruct safePoint_poll(rFlagsReg cr)
12561 %{
12562 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12563 match(SafePoint);
12564 effect(KILL cr);
12565
12566 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12567 "# Safepoint: poll for GC" %}
12568 ins_cost(125);
12569 ins_encode %{
12570 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12571 __ testl(rax, addr);
12572 %}
12573 ins_pipe(ialu_reg_mem);
12574 %}
12575
12576 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12577 %{
12578 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12579 match(SafePoint poll);
12580 effect(KILL cr, USE poll);
12581
12582 format %{ "testl rax, [$poll]\t"
12583 "# Safepoint: poll for GC" %}
12584 ins_cost(125);
12585 ins_encode %{
12586 __ relocate(relocInfo::poll_type);
12587 __ testl(rax, Address($poll$$Register, 0));
12588 %}
12589 ins_pipe(ialu_reg_mem);
12590 %}
12591
12592 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12593 %{
12594 predicate(SafepointMechanism::uses_thread_local_poll());
12595 match(SafePoint poll);
12596 effect(KILL cr, USE poll);
12597
12598 format %{ "testl rax, [$poll]\t"
12599 "# Safepoint: poll for GC" %}
12600 ins_cost(125);
12601 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12602 ins_encode %{
12603 __ relocate(relocInfo::poll_type);
12604 address pre_pc = __ pc();
12605 __ testl(rax, Address($poll$$Register, 0));
12606 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12607 %}
12608 ins_pipe(ialu_reg_mem);
12609 %}
12610
12611 // ============================================================================
12612 // Procedure Call/Return Instructions
12613 // Call Java Static Instruction
12614 // Note: If this code changes, the corresponding ret_addr_offset() and
12615 // compute_padding() functions will have to be adjusted.
12616 instruct CallStaticJavaDirect(method meth) %{
12617 match(CallStaticJava);
12618 effect(USE meth);
12619
12620 ins_cost(300);
12621 format %{ "call,static " %}
12622 opcode(0xE8); /* E8 cd */
12623 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12624 ins_pipe(pipe_slow);
12625 ins_alignment(4);
12626 %}
12627
12628 // Call Java Dynamic Instruction
12629 // Note: If this code changes, the corresponding ret_addr_offset() and
12630 // compute_padding() functions will have to be adjusted.
12631 instruct CallDynamicJavaDirect(method meth)
12632 %{
12633 match(CallDynamicJava);
12634 effect(USE meth);
12635
12636 ins_cost(300);
12637 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12638 "call,dynamic " %}
12639 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12640 ins_pipe(pipe_slow);
12641 ins_alignment(4);
12642 %}
12643
12644 // Call Runtime Instruction
12645 instruct CallRuntimeDirect(method meth)
12646 %{
12647 match(CallRuntime);
12648 effect(USE meth);
12649
12650 ins_cost(300);
12651 format %{ "call,runtime " %}
12652 ins_encode(clear_avx, Java_To_Runtime(meth));
12653 ins_pipe(pipe_slow);
12654 %}
12655
12656 // Call runtime without safepoint
12657 instruct CallLeafDirect(method meth)
12658 %{
12659 match(CallLeaf);
12660 effect(USE meth);
12661
12662 ins_cost(300);
12663 format %{ "call_leaf,runtime " %}
12664 ins_encode(clear_avx, Java_To_Runtime(meth));
12665 ins_pipe(pipe_slow);
12666 %}
12667
12668 // Call runtime without safepoint
12669 instruct CallLeafNoFPDirect(method meth)
12670 %{
12671 match(CallLeafNoFP);
12672 effect(USE meth);
12673
12674 ins_cost(300);
12675 format %{ "call_leaf_nofp,runtime " %}
12676 ins_encode(clear_avx, Java_To_Runtime(meth));
12677 ins_pipe(pipe_slow);
12678 %}
12679
12680 // Return Instruction
12681 // Remove the return address & jump to it.
12682 // Notice: We always emit a nop after a ret to make sure there is room
12683 // for safepoint patching
12684 instruct Ret()
12685 %{
12686 match(Return);
12687
12688 format %{ "ret" %}
12689 opcode(0xC3);
12690 ins_encode(OpcP);
12691 ins_pipe(pipe_jmp);
12692 %}
12693
12694 // Tail Call; Jump from runtime stub to Java code.
12695 // Also known as an 'interprocedural jump'.
12696 // Target of jump will eventually return to caller.
12697 // TailJump below removes the return address.
12698 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12699 %{
12700 match(TailCall jump_target method_oop);
12701
12702 ins_cost(300);
12703 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12704 opcode(0xFF, 0x4); /* Opcode FF /4 */
12705 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12706 ins_pipe(pipe_jmp);
12707 %}
12708
12709 // Tail Jump; remove the return address; jump to target.
12710 // TailCall above leaves the return address around.
12711 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12712 %{
12713 match(TailJump jump_target ex_oop);
12714
12715 ins_cost(300);
12716 format %{ "popq rdx\t# pop return address\n\t"
12717 "jmp $jump_target" %}
12718 opcode(0xFF, 0x4); /* Opcode FF /4 */
12719 ins_encode(Opcode(0x5a), // popq rdx
12720 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12721 ins_pipe(pipe_jmp);
12722 %}
12723
12724 // Create exception oop: created by stack-crawling runtime code.
12725 // Created exception is now available to this handler, and is setup
12726 // just prior to jumping to this handler. No code emitted.
12727 instruct CreateException(rax_RegP ex_oop)
12728 %{
12729 match(Set ex_oop (CreateEx));
12730
12731 size(0);
12732 // use the following format syntax
12733 format %{ "# exception oop is in rax; no code emitted" %}
12734 ins_encode();
12735 ins_pipe(empty);
12736 %}
12737
12738 // Rethrow exception:
12739 // The exception oop will come in the first argument position.
12740 // Then JUMP (not call) to the rethrow stub code.
12741 instruct RethrowException()
12742 %{
12743 match(Rethrow);
12744
12745 // use the following format syntax
12746 format %{ "jmp rethrow_stub" %}
12747 ins_encode(enc_rethrow);
12748 ins_pipe(pipe_jmp);
12749 %}
12750
12751 //
12752 // Execute ZGC load barrier (strong) slow path
12753 //
12754
12755 // When running without XMM regs
12756 instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12757
12758 match(Set dst (LoadBarrierSlowReg mem));
12759 predicate(MaxVectorSize < 16);
12760
12761 effect(DEF dst, KILL cr);
12762
12763 format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12764 ins_encode %{
12765 #if INCLUDE_ZGC
12766 Register d = $dst$$Register;
12767 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12768
12769 assert(d != r12, "Can't be R12!");
12770 assert(d != r15, "Can't be R15!");
12771 assert(d != rsp, "Can't be RSP!");
12772
12773 __ lea(d, $mem$$Address);
12774 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12775 #else
12776 ShouldNotReachHere();
12777 #endif
12778 %}
12779 ins_pipe(pipe_slow);
12780 %}
12781
12782 // For XMM and YMM enabled processors
12783 instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12784 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12785 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12786 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12787 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12788
12789 match(Set dst (LoadBarrierSlowReg mem));
12790 predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12791
12792 effect(DEF dst, KILL cr,
12793 KILL x0, KILL x1, KILL x2, KILL x3,
12794 KILL x4, KILL x5, KILL x6, KILL x7,
12795 KILL x8, KILL x9, KILL x10, KILL x11,
12796 KILL x12, KILL x13, KILL x14, KILL x15);
12797
12798 format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
12799 ins_encode %{
12800 #if INCLUDE_ZGC
12801 Register d = $dst$$Register;
12802 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12803
12804 assert(d != r12, "Can't be R12!");
12805 assert(d != r15, "Can't be R15!");
12806 assert(d != rsp, "Can't be RSP!");
12807
12808 __ lea(d, $mem$$Address);
12809 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12810 #else
12811 ShouldNotReachHere();
12812 #endif
12813 %}
12814 ins_pipe(pipe_slow);
12815 %}
12816
12817 // For ZMM enabled processors
12818 instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12819 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12820 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12821 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12822 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12823 rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12824 rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12825 rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12826 rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12827
12828 match(Set dst (LoadBarrierSlowReg mem));
12829 predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12830
12831 effect(DEF dst, KILL cr,
12832 KILL x0, KILL x1, KILL x2, KILL x3,
12833 KILL x4, KILL x5, KILL x6, KILL x7,
12834 KILL x8, KILL x9, KILL x10, KILL x11,
12835 KILL x12, KILL x13, KILL x14, KILL x15,
12836 KILL x16, KILL x17, KILL x18, KILL x19,
12837 KILL x20, KILL x21, KILL x22, KILL x23,
12838 KILL x24, KILL x25, KILL x26, KILL x27,
12839 KILL x28, KILL x29, KILL x30, KILL x31);
12840
12841 format %{"LoadBarrierSlowRegZmm $dst, $mem" %}
12842 ins_encode %{
12843 #if INCLUDE_ZGC
12844 Register d = $dst$$Register;
12845 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12846
12847 assert(d != r12, "Can't be R12!");
12848 assert(d != r15, "Can't be R15!");
12849 assert(d != rsp, "Can't be RSP!");
12850
12851 __ lea(d, $mem$$Address);
12852 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12853 #else
12854 ShouldNotReachHere();
12855 #endif
12856 %}
12857 ins_pipe(pipe_slow);
12858 %}
12859
12860 //
12861 // Execute ZGC load barrier (weak) slow path
12862 //
12863
12864 // When running without XMM regs
12865 instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12866
12867 match(Set dst (LoadBarrierSlowReg mem));
12868 predicate(MaxVectorSize < 16);
12869
12870 effect(DEF dst, KILL cr);
12871
12872 format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12873 ins_encode %{
12874 #if INCLUDE_ZGC
12875 Register d = $dst$$Register;
12876 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12877
12878 assert(d != r12, "Can't be R12!");
12879 assert(d != r15, "Can't be R15!");
12880 assert(d != rsp, "Can't be RSP!");
12881
12882 __ lea(d, $mem$$Address);
12883 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12884 #else
12885 ShouldNotReachHere();
12886 #endif
12887 %}
12888 ins_pipe(pipe_slow);
12889 %}
12890
12891 // For XMM and YMM enabled processors
12892 instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12893 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12894 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12895 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12896 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12897
12898 match(Set dst (LoadBarrierWeakSlowReg mem));
12899 predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12900
12901 effect(DEF dst, KILL cr,
12902 KILL x0, KILL x1, KILL x2, KILL x3,
12903 KILL x4, KILL x5, KILL x6, KILL x7,
12904 KILL x8, KILL x9, KILL x10, KILL x11,
12905 KILL x12, KILL x13, KILL x14, KILL x15);
12906
12907 format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
12908 ins_encode %{
12909 #if INCLUDE_ZGC
12910 Register d = $dst$$Register;
12911 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12912
12913 assert(d != r12, "Can't be R12!");
12914 assert(d != r15, "Can't be R15!");
12915 assert(d != rsp, "Can't be RSP!");
12916
12917 __ lea(d,$mem$$Address);
12918 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12919 #else
12920 ShouldNotReachHere();
12921 #endif
12922 %}
12923 ins_pipe(pipe_slow);
12924 %}
12925
12926 // For ZMM enabled processors
12927 instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12928 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12929 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12930 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12931 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12932 rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12933 rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12934 rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12935 rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12936
12937 match(Set dst (LoadBarrierWeakSlowReg mem));
12938 predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12939
12940 effect(DEF dst, KILL cr,
12941 KILL x0, KILL x1, KILL x2, KILL x3,
12942 KILL x4, KILL x5, KILL x6, KILL x7,
12943 KILL x8, KILL x9, KILL x10, KILL x11,
12944 KILL x12, KILL x13, KILL x14, KILL x15,
12945 KILL x16, KILL x17, KILL x18, KILL x19,
12946 KILL x20, KILL x21, KILL x22, KILL x23,
12947 KILL x24, KILL x25, KILL x26, KILL x27,
12948 KILL x28, KILL x29, KILL x30, KILL x31);
12949
12950 format %{"LoadBarrierWeakSlowRegZmm $dst, $mem" %}
12951 ins_encode %{
12952 #if INCLUDE_ZGC
12953 Register d = $dst$$Register;
12954 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12955
12956 assert(d != r12, "Can't be R12!");
12957 assert(d != r15, "Can't be R15!");
12958 assert(d != rsp, "Can't be RSP!");
12959
12960 __ lea(d,$mem$$Address);
12961 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12962 #else
12963 ShouldNotReachHere();
12964 #endif
12965 %}
12966 ins_pipe(pipe_slow);
12967 %}
12968
12969 // ============================================================================
12970 // This name is KNOWN by the ADLC and cannot be changed.
12971 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12972 // for this guy.
12973 instruct tlsLoadP(r15_RegP dst) %{
12974 match(Set dst (ThreadLocal));
12975 effect(DEF dst);
12976
12977 size(0);
12978 format %{ "# TLS is in R15" %}
12979 ins_encode( /*empty encoding*/ );
12980 ins_pipe(ialu_reg_reg);
12981 %}
12982
12983
12984 //----------PEEPHOLE RULES-----------------------------------------------------
12985 // These must follow all instruction definitions as they use the names
12986 // defined in the instructions definitions.
12987 //
12988 // peepmatch ( root_instr_name [preceding_instruction]* );
12989 //
12990 // peepconstraint %{
12991 // (instruction_number.operand_name relational_op instruction_number.operand_name
12992 // [, ...] );
12993 // // instruction numbers are zero-based using left to right order in peepmatch
12994 //
12995 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12996 // // provide an instruction_number.operand_name for each operand that appears
12997 // // in the replacement instruction's match rule
12998 //
12999 // ---------VM FLAGS---------------------------------------------------------
13000 //
13001 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13002 //
13003 // Each peephole rule is given an identifying number starting with zero and
13004 // increasing by one in the order seen by the parser. An individual peephole
13005 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13006 // on the command-line.
13007 //
13008 // ---------CURRENT LIMITATIONS----------------------------------------------
13009 //
13010 // Only match adjacent instructions in same basic block
13011 // Only equality constraints
13012 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13013 // Only one replacement instruction
13014 //
13015 // ---------EXAMPLE----------------------------------------------------------
13016 //
13017 // // pertinent parts of existing instructions in architecture description
13018 // instruct movI(rRegI dst, rRegI src)
13019 // %{
13020 // match(Set dst (CopyI src));
13021 // %}
13022 //
13023 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
13024 // %{
13025 // match(Set dst (AddI dst src));
13026 // effect(KILL cr);
13027 // %}
13028 //
13029 // // Change (inc mov) to lea
13030 // peephole %{
13031 // // increment preceeded by register-register move
13032 // peepmatch ( incI_rReg movI );
13033 // // require that the destination register of the increment
13034 // // match the destination register of the move
13035 // peepconstraint ( 0.dst == 1.dst );
13036 // // construct a replacement instruction that sets
13037 // // the destination to ( move's source register + one )
13038 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13039 // %}
13040 //
13041
13042 // Implementation no longer uses movX instructions since
13043 // machine-independent system no longer uses CopyX nodes.
13044 //
13045 // peephole
13046 // %{
13047 // peepmatch (incI_rReg movI);
13048 // peepconstraint (0.dst == 1.dst);
13049 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13050 // %}
13051
13052 // peephole
13053 // %{
13054 // peepmatch (decI_rReg movI);
13055 // peepconstraint (0.dst == 1.dst);
13056 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13057 // %}
13058
13059 // peephole
13060 // %{
13061 // peepmatch (addI_rReg_imm movI);
13062 // peepconstraint (0.dst == 1.dst);
13063 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13064 // %}
13065
13066 // peephole
13067 // %{
13068 // peepmatch (incL_rReg movL);
13069 // peepconstraint (0.dst == 1.dst);
13070 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13071 // %}
13072
13073 // peephole
13074 // %{
13075 // peepmatch (decL_rReg movL);
13076 // peepconstraint (0.dst == 1.dst);
13077 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13078 // %}
13079
13080 // peephole
13081 // %{
13082 // peepmatch (addL_rReg_imm movL);
13083 // peepconstraint (0.dst == 1.dst);
13084 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13085 // %}
13086
13087 // peephole
13088 // %{
13089 // peepmatch (addP_rReg_imm movP);
13090 // peepconstraint (0.dst == 1.dst);
13091 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13092 // %}
13093
13094 // // Change load of spilled value to only a spill
13095 // instruct storeI(memory mem, rRegI src)
13096 // %{
13097 // match(Set mem (StoreI mem src));
13098 // %}
13099 //
13100 // instruct loadI(rRegI dst, memory mem)
13101 // %{
13102 // match(Set dst (LoadI mem));
13103 // %}
13104 //
13105
13106 peephole
13107 %{
13108 peepmatch (loadI storeI);
13109 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13110 peepreplace (storeI(1.mem 1.mem 1.src));
13111 %}
13112
13113 peephole
13114 %{
13115 peepmatch (loadL storeL);
13116 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13117 peepreplace (storeL(1.mem 1.mem 1.src));
13118 %}
13119
13120 //----------SMARTSPILL RULES---------------------------------------------------
13121 // These must follow all instruction definitions as they use the names
13122 // defined in the instructions definitions.