1 /*
2 * Copyright (c) 2005, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_Instruction.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_LIRGenerator.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArray.hpp"
34 #include "ci/ciObjArrayKlass.hpp"
35 #include "ci/ciTypeArrayKlass.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "vmreg_x86.inline.hpp"
39
40 #ifdef ASSERT
41 #define __ gen()->lir(__FILE__, __LINE__)->
42 #else
43 #define __ gen()->lir()->
44 #endif
45
46 #if INCLUDE_ALL_GCS
47 #include "gc_implementation/shenandoah/shenandoahBarrierSetC1.hpp"
48 #endif
49
50 // Item will be loaded into a byte register; Intel only
51 void LIRItem::load_byte_item() {
52 load_item();
53 LIR_Opr res = result();
54
55 if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {
56 // make sure that it is a byte register
57 assert(!value()->type()->is_float() && !value()->type()->is_double(),
58 "can't load floats in byte register");
59 LIR_Opr reg = _gen->rlock_byte(T_BYTE);
60 __ move(res, reg);
61
62 _result = reg;
63 }
64 }
65
66
67 void LIRItem::load_nonconstant() {
68 LIR_Opr r = value()->operand();
69 if (r->is_constant()) {
70 _result = r;
71 } else {
72 load_item();
73 }
74 }
75
76 //--------------------------------------------------------------
77 // LIRGenerator
78 //--------------------------------------------------------------
79
80
81 LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::rax_oop_opr; }
82 LIR_Opr LIRGenerator::exceptionPcOpr() { return FrameMap::rdx_opr; }
83 LIR_Opr LIRGenerator::divInOpr() { return FrameMap::rax_opr; }
84 LIR_Opr LIRGenerator::divOutOpr() { return FrameMap::rax_opr; }
85 LIR_Opr LIRGenerator::remOutOpr() { return FrameMap::rdx_opr; }
86 LIR_Opr LIRGenerator::shiftCountOpr() { return FrameMap::rcx_opr; }
87 LIR_Opr LIRGenerator::syncTempOpr() { return FrameMap::rax_opr; }
88 LIR_Opr LIRGenerator::getThreadTemp() { return LIR_OprFact::illegalOpr; }
89
90
91 LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {
92 LIR_Opr opr;
93 switch (type->tag()) {
94 case intTag: opr = FrameMap::rax_opr; break;
95 case objectTag: opr = FrameMap::rax_oop_opr; break;
96 case longTag: opr = FrameMap::long0_opr; break;
97 case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break;
98 case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break;
99
100 case addressTag:
101 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
102 }
103
104 assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");
105 return opr;
106 }
107
108
109 LIR_Opr LIRGenerator::rlock_byte(BasicType type) {
110 LIR_Opr reg = new_register(T_INT);
111 set_vreg_flag(reg, LIRGenerator::byte_reg);
112 return reg;
113 }
114
115
116 //--------- loading items into registers --------------------------------
117
118
119 // i486 instructions can inline constants
120 bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {
121 if (type == T_SHORT || type == T_CHAR) {
122 // there is no immediate move of word values in asembler_i486.?pp
123 return false;
124 }
125 Constant* c = v->as_Constant();
126 if (c && c->state_before() == NULL) {
127 // constants of any type can be stored directly, except for
128 // unloaded object constants.
129 return true;
130 }
131 return false;
132 }
133
134
135 bool LIRGenerator::can_inline_as_constant(Value v) const {
136 if (v->type()->tag() == longTag) return false;
137 return v->type()->tag() != objectTag ||
138 (v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
139 }
140
141
142 bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
143 if (c->type() == T_LONG) return false;
144 return c->type() != T_OBJECT || c->as_jobject() == NULL;
145 }
146
147
148 LIR_Opr LIRGenerator::safepoint_poll_register() {
149 return LIR_OprFact::illegalOpr;
150 }
151
152
153 LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,
154 int shift, int disp, BasicType type) {
155 assert(base->is_register(), "must be");
156 if (index->is_constant()) {
157 return new LIR_Address(base,
158 (index->as_constant_ptr()->as_jint() << shift) + disp,
159 type);
160 } else {
161 return new LIR_Address(base, index, (LIR_Address::Scale)shift, disp, type);
162 }
163 }
164
165
166 LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,
167 BasicType type, bool needs_card_mark) {
168 int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);
169
170 LIR_Address* addr;
171 if (index_opr->is_constant()) {
172 int elem_size = type2aelembytes(type);
173 addr = new LIR_Address(array_opr,
174 offset_in_bytes + index_opr->as_jint() * elem_size, type);
175 } else {
176 #ifdef _LP64
177 if (index_opr->type() == T_INT) {
178 LIR_Opr tmp = new_register(T_LONG);
179 __ convert(Bytecodes::_i2l, index_opr, tmp);
180 index_opr = tmp;
181 }
182 #endif // _LP64
183 addr = new LIR_Address(array_opr,
184 index_opr,
185 LIR_Address::scale(type),
186 offset_in_bytes, type);
187 }
188 if (needs_card_mark) {
189 // This store will need a precise card mark, so go ahead and
190 // compute the full adddres instead of computing once for the
191 // store and again for the card mark.
192 LIR_Opr tmp = new_pointer_register();
193 __ leal(LIR_OprFact::address(addr), tmp);
194 return new LIR_Address(tmp, type);
195 } else {
196 return addr;
197 }
198 }
199
200
201 LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {
202 LIR_Opr r = NULL;
203 if (type == T_LONG) {
204 r = LIR_OprFact::longConst(x);
205 } else if (type == T_INT) {
206 r = LIR_OprFact::intConst(x);
207 } else {
208 ShouldNotReachHere();
209 }
210 return r;
211 }
212
213 void LIRGenerator::increment_counter(address counter, BasicType type, int step) {
214 LIR_Opr pointer = new_pointer_register();
215 __ move(LIR_OprFact::intptrConst(counter), pointer);
216 LIR_Address* addr = new LIR_Address(pointer, type);
217 increment_counter(addr, step);
218 }
219
220
221 void LIRGenerator::increment_counter(LIR_Address* addr, int step) {
222 __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr);
223 }
224
225 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
226 __ cmp_mem_int(condition, base, disp, c, info);
227 }
228
229
230 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {
231 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
232 }
233
234
235 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {
236 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
237 }
238
239
240 bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
241 if (tmp->is_valid()) {
242 if (is_power_of_2(c + 1)) {
243 __ move(left, tmp);
244 __ shift_left(left, log2_jint(c + 1), left);
245 __ sub(left, tmp, result);
246 return true;
247 } else if (is_power_of_2(c - 1)) {
248 __ move(left, tmp);
249 __ shift_left(left, log2_jint(c - 1), left);
250 __ add(left, tmp, result);
251 return true;
252 }
253 }
254 return false;
255 }
256
257
258 void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {
259 BasicType type = item->type();
260 __ store(item, new LIR_Address(FrameMap::rsp_opr, in_bytes(offset_from_sp), type));
261 }
262
263 //----------------------------------------------------------------------
264 // visitor functions
265 //----------------------------------------------------------------------
266
267
268 void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {
269 assert(x->is_pinned(),"");
270 bool needs_range_check = x->compute_needs_range_check();
271 bool use_length = x->length() != NULL;
272 bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;
273 bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||
274 !get_jobject_constant(x->value())->is_null_object() ||
275 x->should_profile());
276
277 LIRItem array(x->array(), this);
278 LIRItem index(x->index(), this);
279 LIRItem value(x->value(), this);
280 LIRItem length(this);
281
282 array.load_item();
283 index.load_nonconstant();
284
285 if (use_length && needs_range_check) {
286 length.set_instruction(x->length());
287 length.load_item();
288
289 }
290 if (needs_store_check || x->check_boolean()) {
291 value.load_item();
292 } else {
293 value.load_for_store(x->elt_type());
294 }
295
296 set_no_result(x);
297
298 // the CodeEmitInfo must be duplicated for each different
299 // LIR-instruction because spilling can occur anywhere between two
300 // instructions and so the debug information must be different
301 CodeEmitInfo* range_check_info = state_for(x);
302 CodeEmitInfo* null_check_info = NULL;
303 if (x->needs_null_check()) {
304 null_check_info = new CodeEmitInfo(range_check_info);
305 }
306
307 // emit array address setup early so it schedules better
308 LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);
309
310 if (GenerateRangeChecks && needs_range_check) {
311 if (use_length) {
312 __ cmp(lir_cond_belowEqual, length.result(), index.result());
313 __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));
314 } else {
315 array_range_check(array.result(), index.result(), null_check_info, range_check_info);
316 // range_check also does the null check
317 null_check_info = NULL;
318 }
319 }
320
321 if (GenerateArrayStoreCheck && needs_store_check) {
322 LIR_Opr tmp1 = new_register(objectType);
323 LIR_Opr tmp2 = new_register(objectType);
324 LIR_Opr tmp3 = new_register(objectType);
325
326 CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);
327 __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info, x->profiled_method(), x->profiled_bci());
328 }
329
330 if (obj_store) {
331 // Needs GC write barriers.
332 pre_barrier(LIR_OprFact::address(array_addr), LIR_OprFact::illegalOpr /* pre_val */,
333 true /* do_load */, false /* patch */, NULL);
334 __ move(value.result(), array_addr, null_check_info);
335 // Seems to be a precise
336 post_barrier(LIR_OprFact::address(array_addr), value.result());
337 } else {
338 LIR_Opr result = maybe_mask_boolean(x, array.result(), value.result(), null_check_info);
339 __ move(result, array_addr, null_check_info);
340 }
341 }
342
343
344 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {
345 assert(x->is_pinned(),"");
346 LIRItem obj(x->obj(), this);
347 obj.load_item();
348
349 set_no_result(x);
350
351 // "lock" stores the address of the monitor stack slot, so this is not an oop
352 LIR_Opr lock = new_register(T_INT);
353 // Need a scratch register for biased locking on x86
354 LIR_Opr scratch = LIR_OprFact::illegalOpr;
355 if (UseBiasedLocking) {
356 scratch = new_register(T_INT);
357 }
358
359 CodeEmitInfo* info_for_exception = NULL;
360 if (x->needs_null_check()) {
361 info_for_exception = state_for(x);
362 }
363 // this CodeEmitInfo must not have the xhandlers because here the
364 // object is already locked (xhandlers expect object to be unlocked)
365 CodeEmitInfo* info = state_for(x, x->state(), true);
366 monitor_enter(obj.result(), lock, syncTempOpr(), scratch,
367 x->monitor_no(), info_for_exception, info);
368 }
369
370
371 void LIRGenerator::do_MonitorExit(MonitorExit* x) {
372 assert(x->is_pinned(),"");
373
374 LIRItem obj(x->obj(), this);
375 obj.dont_load_item();
376
377 LIR_Opr lock = new_register(T_INT);
378 LIR_Opr obj_temp = new_register(T_INT);
379 set_no_result(x);
380 monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no());
381 }
382
383
384 // _ineg, _lneg, _fneg, _dneg
385 void LIRGenerator::do_NegateOp(NegateOp* x) {
386 LIRItem value(x->x(), this);
387 value.set_destroys_register();
388 value.load_item();
389 LIR_Opr reg = rlock(x);
390 __ negate(value.result(), reg);
391
392 set_result(x, round_item(reg));
393 }
394
395
396 // for _fadd, _fmul, _fsub, _fdiv, _frem
397 // _dadd, _dmul, _dsub, _ddiv, _drem
398 void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {
399 LIRItem left(x->x(), this);
400 LIRItem right(x->y(), this);
401 LIRItem* left_arg = &left;
402 LIRItem* right_arg = &right;
403 assert(!left.is_stack() || !right.is_stack(), "can't both be memory operands");
404 bool must_load_both = (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem);
405 if (left.is_register() || x->x()->type()->is_constant() || must_load_both) {
406 left.load_item();
407 } else {
408 left.dont_load_item();
409 }
410
411 // do not load right operand if it is a constant. only 0 and 1 are
412 // loaded because there are special instructions for loading them
413 // without memory access (not needed for SSE2 instructions)
414 bool must_load_right = false;
415 if (right.is_constant()) {
416 LIR_Const* c = right.result()->as_constant_ptr();
417 assert(c != NULL, "invalid constant");
418 assert(c->type() == T_FLOAT || c->type() == T_DOUBLE, "invalid type");
419
420 if (c->type() == T_FLOAT) {
421 must_load_right = UseSSE < 1 && (c->is_one_float() || c->is_zero_float());
422 } else {
423 must_load_right = UseSSE < 2 && (c->is_one_double() || c->is_zero_double());
424 }
425 }
426
427 if (must_load_both) {
428 // frem and drem destroy also right operand, so move it to a new register
429 right.set_destroys_register();
430 right.load_item();
431 } else if (right.is_register() || must_load_right) {
432 right.load_item();
433 } else {
434 right.dont_load_item();
435 }
436 LIR_Opr reg = rlock(x);
437 LIR_Opr tmp = LIR_OprFact::illegalOpr;
438 if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) {
439 tmp = new_register(T_DOUBLE);
440 }
441
442 if ((UseSSE >= 1 && x->op() == Bytecodes::_frem) || (UseSSE >= 2 && x->op() == Bytecodes::_drem)) {
443 // special handling for frem and drem: no SSE instruction, so must use FPU with temporary fpu stack slots
444 LIR_Opr fpu0, fpu1;
445 if (x->op() == Bytecodes::_frem) {
446 fpu0 = LIR_OprFact::single_fpu(0);
447 fpu1 = LIR_OprFact::single_fpu(1);
448 } else {
449 fpu0 = LIR_OprFact::double_fpu(0);
450 fpu1 = LIR_OprFact::double_fpu(1);
451 }
452 __ move(right.result(), fpu1); // order of left and right operand is important!
453 __ move(left.result(), fpu0);
454 __ rem (fpu0, fpu1, fpu0);
455 __ move(fpu0, reg);
456
457 } else {
458 arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp);
459 }
460
461 set_result(x, round_item(reg));
462 }
463
464
465 // for _ladd, _lmul, _lsub, _ldiv, _lrem
466 void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
467 if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem ) {
468 // long division is implemented as a direct call into the runtime
469 LIRItem left(x->x(), this);
470 LIRItem right(x->y(), this);
471
472 // the check for division by zero destroys the right operand
473 right.set_destroys_register();
474
475 BasicTypeList signature(2);
476 signature.append(T_LONG);
477 signature.append(T_LONG);
478 CallingConvention* cc = frame_map()->c_calling_convention(&signature);
479
480 // check for division by zero (destroys registers of right operand!)
481 CodeEmitInfo* info = state_for(x);
482
483 const LIR_Opr result_reg = result_register_for(x->type());
484 left.load_item_force(cc->at(1));
485 right.load_item();
486
487 __ move(right.result(), cc->at(0));
488
489 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));
490 __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));
491
492 address entry = NULL;
493 switch (x->op()) {
494 case Bytecodes::_lrem:
495 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem);
496 break; // check if dividend is 0 is done elsewhere
497 case Bytecodes::_ldiv:
498 entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv);
499 break; // check if dividend is 0 is done elsewhere
500 case Bytecodes::_lmul:
501 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul);
502 break;
503 default:
504 ShouldNotReachHere();
505 }
506
507 LIR_Opr result = rlock_result(x);
508 __ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args());
509 __ move(result_reg, result);
510 } else if (x->op() == Bytecodes::_lmul) {
511 // missing test if instr is commutative and if we should swap
512 LIRItem left(x->x(), this);
513 LIRItem right(x->y(), this);
514
515 // right register is destroyed by the long mul, so it must be
516 // copied to a new register.
517 right.set_destroys_register();
518
519 left.load_item();
520 right.load_item();
521
522 LIR_Opr reg = FrameMap::long0_opr;
523 arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
524 LIR_Opr result = rlock_result(x);
525 __ move(reg, result);
526 } else {
527 // missing test if instr is commutative and if we should swap
528 LIRItem left(x->x(), this);
529 LIRItem right(x->y(), this);
530
531 left.load_item();
532 // don't load constants to save register
533 right.load_nonconstant();
534 rlock_result(x);
535 arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);
536 }
537 }
538
539
540
541 // for: _iadd, _imul, _isub, _idiv, _irem
542 void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {
543 if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {
544 // The requirements for division and modulo
545 // input : rax,: dividend min_int
546 // reg: divisor (may not be rax,/rdx) -1
547 //
548 // output: rax,: quotient (= rax, idiv reg) min_int
549 // rdx: remainder (= rax, irem reg) 0
550
551 // rax, and rdx will be destroyed
552
553 // Note: does this invalidate the spec ???
554 LIRItem right(x->y(), this);
555 LIRItem left(x->x() , this); // visit left second, so that the is_register test is valid
556
557 // call state_for before load_item_force because state_for may
558 // force the evaluation of other instructions that are needed for
559 // correct debug info. Otherwise the live range of the fix
560 // register might be too long.
561 CodeEmitInfo* info = state_for(x);
562
563 left.load_item_force(divInOpr());
564
565 right.load_item();
566
567 LIR_Opr result = rlock_result(x);
568 LIR_Opr result_reg;
569 if (x->op() == Bytecodes::_idiv) {
570 result_reg = divOutOpr();
571 } else {
572 result_reg = remOutOpr();
573 }
574
575 if (!ImplicitDiv0Checks) {
576 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::intConst(0));
577 __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info));
578 }
579 LIR_Opr tmp = FrameMap::rdx_opr; // idiv and irem use rdx in their implementation
580 if (x->op() == Bytecodes::_irem) {
581 __ irem(left.result(), right.result(), result_reg, tmp, info);
582 } else if (x->op() == Bytecodes::_idiv) {
583 __ idiv(left.result(), right.result(), result_reg, tmp, info);
584 } else {
585 ShouldNotReachHere();
586 }
587
588 __ move(result_reg, result);
589 } else {
590 // missing test if instr is commutative and if we should swap
591 LIRItem left(x->x(), this);
592 LIRItem right(x->y(), this);
593 LIRItem* left_arg = &left;
594 LIRItem* right_arg = &right;
595 if (x->is_commutative() && left.is_stack() && right.is_register()) {
596 // swap them if left is real stack (or cached) and right is real register(not cached)
597 left_arg = &right;
598 right_arg = &left;
599 }
600
601 left_arg->load_item();
602
603 // do not need to load right, as we can handle stack and constants
604 if (x->op() == Bytecodes::_imul ) {
605 // check if we can use shift instead
606 bool use_constant = false;
607 bool use_tmp = false;
608 if (right_arg->is_constant()) {
609 int iconst = right_arg->get_jint_constant();
610 if (iconst > 0) {
611 if (is_power_of_2(iconst)) {
612 use_constant = true;
613 } else if (is_power_of_2(iconst - 1) || is_power_of_2(iconst + 1)) {
614 use_constant = true;
615 use_tmp = true;
616 }
617 }
618 }
619 if (use_constant) {
620 right_arg->dont_load_item();
621 } else {
622 right_arg->load_item();
623 }
624 LIR_Opr tmp = LIR_OprFact::illegalOpr;
625 if (use_tmp) {
626 tmp = new_register(T_INT);
627 }
628 rlock_result(x);
629
630 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
631 } else {
632 right_arg->dont_load_item();
633 rlock_result(x);
634 LIR_Opr tmp = LIR_OprFact::illegalOpr;
635 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
636 }
637 }
638 }
639
640
641 void LIRGenerator::do_ArithmeticOp(ArithmeticOp* x) {
642 // when an operand with use count 1 is the left operand, then it is
643 // likely that no move for 2-operand-LIR-form is necessary
644 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
645 x->swap_operands();
646 }
647
648 ValueTag tag = x->type()->tag();
649 assert(x->x()->type()->tag() == tag && x->y()->type()->tag() == tag, "wrong parameters");
650 switch (tag) {
651 case floatTag:
652 case doubleTag: do_ArithmeticOp_FPU(x); return;
653 case longTag: do_ArithmeticOp_Long(x); return;
654 case intTag: do_ArithmeticOp_Int(x); return;
655 }
656 ShouldNotReachHere();
657 }
658
659
660 // _ishl, _lshl, _ishr, _lshr, _iushr, _lushr
661 void LIRGenerator::do_ShiftOp(ShiftOp* x) {
662 // count must always be in rcx
663 LIRItem value(x->x(), this);
664 LIRItem count(x->y(), this);
665
666 ValueTag elemType = x->type()->tag();
667 bool must_load_count = !count.is_constant() || elemType == longTag;
668 if (must_load_count) {
669 // count for long must be in register
670 count.load_item_force(shiftCountOpr());
671 } else {
672 count.dont_load_item();
673 }
674 value.load_item();
675 LIR_Opr reg = rlock_result(x);
676
677 shift_op(x->op(), reg, value.result(), count.result(), LIR_OprFact::illegalOpr);
678 }
679
680
681 // _iand, _land, _ior, _lor, _ixor, _lxor
682 void LIRGenerator::do_LogicOp(LogicOp* x) {
683 // when an operand with use count 1 is the left operand, then it is
684 // likely that no move for 2-operand-LIR-form is necessary
685 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
686 x->swap_operands();
687 }
688
689 LIRItem left(x->x(), this);
690 LIRItem right(x->y(), this);
691
692 left.load_item();
693 right.load_nonconstant();
694 LIR_Opr reg = rlock_result(x);
695
696 logic_op(x->op(), reg, left.result(), right.result());
697 }
698
699
700
701 // _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg
702 void LIRGenerator::do_CompareOp(CompareOp* x) {
703 LIRItem left(x->x(), this);
704 LIRItem right(x->y(), this);
705 ValueTag tag = x->x()->type()->tag();
706 if (tag == longTag) {
707 left.set_destroys_register();
708 }
709 left.load_item();
710 right.load_item();
711 LIR_Opr reg = rlock_result(x);
712
713 if (x->x()->type()->is_float_kind()) {
714 Bytecodes::Code code = x->op();
715 __ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl));
716 } else if (x->x()->type()->tag() == longTag) {
717 __ lcmp2int(left.result(), right.result(), reg);
718 } else {
719 Unimplemented();
720 }
721 }
722
723
724 void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) {
725 assert(x->number_of_arguments() == 4, "wrong type");
726 LIRItem obj (x->argument_at(0), this); // object
727 LIRItem offset(x->argument_at(1), this); // offset of field
728 LIRItem cmp (x->argument_at(2), this); // value to compare with field
729 LIRItem val (x->argument_at(3), this); // replace field with val if matches cmp
730
731 assert(obj.type()->tag() == objectTag, "invalid type");
732
733 // In 64bit the type can be long, sparc doesn't have this assert
734 // assert(offset.type()->tag() == intTag, "invalid type");
735
736 assert(cmp.type()->tag() == type->tag(), "invalid type");
737 assert(val.type()->tag() == type->tag(), "invalid type");
738
739 // get address of field
740 obj.load_item();
741 offset.load_nonconstant();
742
743 if (type == objectType) {
744 cmp.load_item_force(FrameMap::rax_oop_opr);
745 val.load_item();
746 } else if (type == intType) {
747 cmp.load_item_force(FrameMap::rax_opr);
748 val.load_item();
749 } else if (type == longType) {
750 cmp.load_item_force(FrameMap::long0_opr);
751 val.load_item_force(FrameMap::long1_opr);
752 } else {
753 ShouldNotReachHere();
754 }
755
756 LIR_Opr addr = new_pointer_register();
757 LIR_Address* a;
758 if(offset.result()->is_constant()) {
759 #ifdef _LP64
760 jlong c = offset.result()->as_jlong();
761 if ((jlong)((jint)c) == c) {
762 a = new LIR_Address(obj.result(),
763 (jint)c,
764 as_BasicType(type));
765 } else {
766 LIR_Opr tmp = new_register(T_LONG);
767 __ move(offset.result(), tmp);
768 a = new LIR_Address(obj.result(),
769 tmp,
770 as_BasicType(type));
771 }
772 #else
773 a = new LIR_Address(obj.result(),
774 offset.result()->as_jint(),
775 as_BasicType(type));
776 #endif
777 } else {
778 a = new LIR_Address(obj.result(),
779 offset.result(),
780 LIR_Address::times_1,
781 0,
782 as_BasicType(type));
783 }
784 __ leal(LIR_OprFact::address(a), addr);
785
786 if (type == objectType) { // Write-barrier needed for Object fields.
787 // Do the pre-write barrier, if any.
788 pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
789 true /* do_load */, false /* patch */, NULL);
790 }
791
792 LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience
793 if (type == objectType) {
794 #if INCLUDE_ALL_GCS
795 if (UseShenandoahGC) {
796 __ cas_obj(addr, cmp.result(), val.result(), new_register(T_OBJECT), new_register(T_OBJECT));
797 } else
798 #endif
799 {
800 __ cas_obj(addr, cmp.result(), val.result(), ill, ill);
801 }
802 }
803 else if (type == intType)
804 __ cas_int(addr, cmp.result(), val.result(), ill, ill);
805 else if (type == longType)
806 __ cas_long(addr, cmp.result(), val.result(), ill, ill);
807 else {
808 ShouldNotReachHere();
809 }
810
811 // generate conditional move of boolean result
812 LIR_Opr result = rlock_result(x);
813 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
814 result, as_BasicType(type));
815 if (type == objectType) { // Write-barrier needed for Object fields.
816 // Seems to be precise
817 post_barrier(addr, val.result());
818 }
819 }
820
821
822 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
823 assert(x->number_of_arguments() == 1 || (x->number_of_arguments() == 2 && x->id() == vmIntrinsics::_dpow), "wrong type");
824 LIRItem value(x->argument_at(0), this);
825
826 bool use_fpu = false;
827 if (UseSSE >= 2) {
828 switch(x->id()) {
829 case vmIntrinsics::_dsin:
830 case vmIntrinsics::_dcos:
831 case vmIntrinsics::_dtan:
832 case vmIntrinsics::_dlog:
833 case vmIntrinsics::_dlog10:
834 case vmIntrinsics::_dexp:
835 case vmIntrinsics::_dpow:
836 use_fpu = true;
837 }
838 } else {
839 value.set_destroys_register();
840 }
841
842 value.load_item();
843
844 LIR_Opr calc_input = value.result();
845 LIR_Opr calc_input2 = NULL;
846 if (x->id() == vmIntrinsics::_dpow) {
847 LIRItem extra_arg(x->argument_at(1), this);
848 if (UseSSE < 2) {
849 extra_arg.set_destroys_register();
850 }
851 extra_arg.load_item();
852 calc_input2 = extra_arg.result();
853 }
854 LIR_Opr calc_result = rlock_result(x);
855
856 // sin, cos, pow and exp need two free fpu stack slots, so register
857 // two temporary operands
858 LIR_Opr tmp1 = FrameMap::caller_save_fpu_reg_at(0);
859 LIR_Opr tmp2 = FrameMap::caller_save_fpu_reg_at(1);
860
861 if (use_fpu) {
862 LIR_Opr tmp = FrameMap::fpu0_double_opr;
863 int tmp_start = 1;
864 if (calc_input2 != NULL) {
865 __ move(calc_input2, tmp);
866 tmp_start = 2;
867 calc_input2 = tmp;
868 }
869 __ move(calc_input, tmp);
870
871 calc_input = tmp;
872 calc_result = tmp;
873
874 tmp1 = FrameMap::caller_save_fpu_reg_at(tmp_start);
875 tmp2 = FrameMap::caller_save_fpu_reg_at(tmp_start + 1);
876 }
877
878 switch(x->id()) {
879 case vmIntrinsics::_dabs: __ abs (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
880 case vmIntrinsics::_dsqrt: __ sqrt (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
881 case vmIntrinsics::_dsin: __ sin (calc_input, calc_result, tmp1, tmp2); break;
882 case vmIntrinsics::_dcos: __ cos (calc_input, calc_result, tmp1, tmp2); break;
883 case vmIntrinsics::_dtan: __ tan (calc_input, calc_result, tmp1, tmp2); break;
884 case vmIntrinsics::_dlog: __ log (calc_input, calc_result, tmp1); break;
885 case vmIntrinsics::_dlog10: __ log10(calc_input, calc_result, tmp1); break;
886 case vmIntrinsics::_dexp: __ exp (calc_input, calc_result, tmp1, tmp2, FrameMap::rax_opr, FrameMap::rcx_opr, FrameMap::rdx_opr); break;
887 case vmIntrinsics::_dpow: __ pow (calc_input, calc_input2, calc_result, tmp1, tmp2, FrameMap::rax_opr, FrameMap::rcx_opr, FrameMap::rdx_opr); break;
888 default: ShouldNotReachHere();
889 }
890
891 if (use_fpu) {
892 __ move(calc_result, x->operand());
893 }
894 }
895
896
897 void LIRGenerator::do_ArrayCopy(Intrinsic* x) {
898 assert(x->number_of_arguments() == 5, "wrong type");
899
900 // Make all state_for calls early since they can emit code
901 CodeEmitInfo* info = state_for(x, x->state());
902
903 LIRItem src(x->argument_at(0), this);
904 LIRItem src_pos(x->argument_at(1), this);
905 LIRItem dst(x->argument_at(2), this);
906 LIRItem dst_pos(x->argument_at(3), this);
907 LIRItem length(x->argument_at(4), this);
908
909 // operands for arraycopy must use fixed registers, otherwise
910 // LinearScan will fail allocation (because arraycopy always needs a
911 // call)
912
913 #ifndef _LP64
914 src.load_item_force (FrameMap::rcx_oop_opr);
915 src_pos.load_item_force (FrameMap::rdx_opr);
916 dst.load_item_force (FrameMap::rax_oop_opr);
917 dst_pos.load_item_force (FrameMap::rbx_opr);
918 length.load_item_force (FrameMap::rdi_opr);
919 LIR_Opr tmp = (FrameMap::rsi_opr);
920 #else
921
922 // The java calling convention will give us enough registers
923 // so that on the stub side the args will be perfect already.
924 // On the other slow/special case side we call C and the arg
925 // positions are not similar enough to pick one as the best.
926 // Also because the java calling convention is a "shifted" version
927 // of the C convention we can process the java args trivially into C
928 // args without worry of overwriting during the xfer
929
930 src.load_item_force (FrameMap::as_oop_opr(j_rarg0));
931 src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
932 dst.load_item_force (FrameMap::as_oop_opr(j_rarg2));
933 dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
934 length.load_item_force (FrameMap::as_opr(j_rarg4));
935
936 LIR_Opr tmp = FrameMap::as_opr(j_rarg5);
937 #endif // LP64
938
939 set_no_result(x);
940
941 int flags;
942 ciArrayKlass* expected_type;
943 arraycopy_helper(x, &flags, &expected_type);
944
945 __ arraycopy(src.result(), src_pos.result(), dst.result(), dst_pos.result(), length.result(), tmp, expected_type, flags, info); // does add_safepoint
946 }
947
948 void LIRGenerator::do_update_CRC32(Intrinsic* x) {
949 assert(UseCRC32Intrinsics, "need AVX and LCMUL instructions support");
950 // Make all state_for calls early since they can emit code
951 LIR_Opr result = rlock_result(x);
952 int flags = 0;
953 switch (x->id()) {
954 case vmIntrinsics::_updateCRC32: {
955 LIRItem crc(x->argument_at(0), this);
956 LIRItem val(x->argument_at(1), this);
957 // val is destroyed by update_crc32
958 val.set_destroys_register();
959 crc.load_item();
960 val.load_item();
961 __ update_crc32(crc.result(), val.result(), result);
962 break;
963 }
964 case vmIntrinsics::_updateBytesCRC32:
965 case vmIntrinsics::_updateByteBufferCRC32: {
966 bool is_updateBytes = (x->id() == vmIntrinsics::_updateBytesCRC32);
967
968 LIRItem crc(x->argument_at(0), this);
969 LIRItem buf(x->argument_at(1), this);
970 LIRItem off(x->argument_at(2), this);
971 LIRItem len(x->argument_at(3), this);
972 buf.load_item();
973 off.load_nonconstant();
974
975 LIR_Opr index = off.result();
976 int offset = is_updateBytes ? arrayOopDesc::base_offset_in_bytes(T_BYTE) : 0;
977 if(off.result()->is_constant()) {
978 index = LIR_OprFact::illegalOpr;
979 offset += off.result()->as_jint();
980 }
981 LIR_Opr base_op = buf.result();
982
983 #ifndef _LP64
984 if (!is_updateBytes) { // long b raw address
985 base_op = new_register(T_INT);
986 __ convert(Bytecodes::_l2i, buf.result(), base_op);
987 }
988 #else
989 if (index->is_valid()) {
990 LIR_Opr tmp = new_register(T_LONG);
991 __ convert(Bytecodes::_i2l, index, tmp);
992 index = tmp;
993 }
994 #endif
995
996 LIR_Address* a = new LIR_Address(base_op,
997 index,
998 LIR_Address::times_1,
999 offset,
1000 T_BYTE);
1001 BasicTypeList signature(3);
1002 signature.append(T_INT);
1003 signature.append(T_ADDRESS);
1004 signature.append(T_INT);
1005 CallingConvention* cc = frame_map()->c_calling_convention(&signature);
1006 const LIR_Opr result_reg = result_register_for(x->type());
1007
1008 LIR_Opr addr = new_pointer_register();
1009 __ leal(LIR_OprFact::address(a), addr);
1010
1011 crc.load_item_force(cc->at(0));
1012 __ move(addr, cc->at(1));
1013 len.load_item_force(cc->at(2));
1014
1015 __ call_runtime_leaf(StubRoutines::updateBytesCRC32(), getThreadTemp(), result_reg, cc->args());
1016 __ move(result_reg, result);
1017
1018 break;
1019 }
1020 default: {
1021 ShouldNotReachHere();
1022 }
1023 }
1024 }
1025
1026 // _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
1027 // _i2b, _i2c, _i2s
1028 LIR_Opr fixed_register_for(BasicType type) {
1029 switch (type) {
1030 case T_FLOAT: return FrameMap::fpu0_float_opr;
1031 case T_DOUBLE: return FrameMap::fpu0_double_opr;
1032 case T_INT: return FrameMap::rax_opr;
1033 case T_LONG: return FrameMap::long0_opr;
1034 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
1035 }
1036 }
1037
1038 void LIRGenerator::do_Convert(Convert* x) {
1039 // flags that vary for the different operations and different SSE-settings
1040 bool fixed_input = false, fixed_result = false, round_result = false, needs_stub = false;
1041
1042 switch (x->op()) {
1043 case Bytecodes::_i2l: // fall through
1044 case Bytecodes::_l2i: // fall through
1045 case Bytecodes::_i2b: // fall through
1046 case Bytecodes::_i2c: // fall through
1047 case Bytecodes::_i2s: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
1048
1049 case Bytecodes::_f2d: fixed_input = UseSSE == 1; fixed_result = false; round_result = false; needs_stub = false; break;
1050 case Bytecodes::_d2f: fixed_input = false; fixed_result = UseSSE == 1; round_result = UseSSE < 1; needs_stub = false; break;
1051 case Bytecodes::_i2f: fixed_input = false; fixed_result = false; round_result = UseSSE < 1; needs_stub = false; break;
1052 case Bytecodes::_i2d: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
1053 case Bytecodes::_f2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
1054 case Bytecodes::_d2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
1055 case Bytecodes::_l2f: fixed_input = false; fixed_result = UseSSE >= 1; round_result = UseSSE < 1; needs_stub = false; break;
1056 case Bytecodes::_l2d: fixed_input = false; fixed_result = UseSSE >= 2; round_result = UseSSE < 2; needs_stub = false; break;
1057 case Bytecodes::_f2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
1058 case Bytecodes::_d2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
1059 default: ShouldNotReachHere();
1060 }
1061
1062 LIRItem value(x->value(), this);
1063 value.load_item();
1064 LIR_Opr input = value.result();
1065 LIR_Opr result = rlock(x);
1066
1067 // arguments of lir_convert
1068 LIR_Opr conv_input = input;
1069 LIR_Opr conv_result = result;
1070 ConversionStub* stub = NULL;
1071
1072 if (fixed_input) {
1073 conv_input = fixed_register_for(input->type());
1074 __ move(input, conv_input);
1075 }
1076
1077 assert(fixed_result == false || round_result == false, "cannot set both");
1078 if (fixed_result) {
1079 conv_result = fixed_register_for(result->type());
1080 } else if (round_result) {
1081 result = new_register(result->type());
1082 set_vreg_flag(result, must_start_in_memory);
1083 }
1084
1085 if (needs_stub) {
1086 stub = new ConversionStub(x->op(), conv_input, conv_result);
1087 }
1088
1089 __ convert(x->op(), conv_input, conv_result, stub);
1090
1091 if (result != conv_result) {
1092 __ move(conv_result, result);
1093 }
1094
1095 assert(result->is_virtual(), "result must be virtual register");
1096 set_result(x, result);
1097 }
1098
1099
1100 void LIRGenerator::do_NewInstance(NewInstance* x) {
1101 print_if_not_loaded(x);
1102
1103 CodeEmitInfo* info = state_for(x, x->state());
1104 LIR_Opr reg = result_register_for(x->type());
1105 new_instance(reg, x->klass(), x->is_unresolved(),
1106 FrameMap::rcx_oop_opr,
1107 FrameMap::rdi_oop_opr,
1108 FrameMap::rsi_oop_opr,
1109 LIR_OprFact::illegalOpr,
1110 FrameMap::rdx_metadata_opr, info);
1111 LIR_Opr result = rlock_result(x);
1112 __ move(reg, result);
1113 }
1114
1115
1116 void LIRGenerator::do_NewTypeArray(NewTypeArray* x) {
1117 CodeEmitInfo* info = state_for(x, x->state());
1118
1119 LIRItem length(x->length(), this);
1120 length.load_item_force(FrameMap::rbx_opr);
1121
1122 LIR_Opr reg = result_register_for(x->type());
1123 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1124 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1125 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1126 LIR_Opr tmp4 = reg;
1127 LIR_Opr klass_reg = FrameMap::rdx_metadata_opr;
1128 LIR_Opr len = length.result();
1129 BasicType elem_type = x->elt_type();
1130
1131 __ metadata2reg(ciTypeArrayKlass::make(elem_type)->constant_encoding(), klass_reg);
1132
1133 CodeStub* slow_path = new NewTypeArrayStub(klass_reg, len, reg, info);
1134 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, elem_type, klass_reg, slow_path);
1135
1136 LIR_Opr result = rlock_result(x);
1137 __ move(reg, result);
1138 }
1139
1140
1141 void LIRGenerator::do_NewObjectArray(NewObjectArray* x) {
1142 LIRItem length(x->length(), this);
1143 // in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction
1144 // and therefore provide the state before the parameters have been consumed
1145 CodeEmitInfo* patching_info = NULL;
1146 if (!x->klass()->is_loaded() || PatchALot) {
1147 patching_info = state_for(x, x->state_before());
1148 }
1149
1150 CodeEmitInfo* info = state_for(x, x->state());
1151
1152 const LIR_Opr reg = result_register_for(x->type());
1153 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1154 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1155 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1156 LIR_Opr tmp4 = reg;
1157 LIR_Opr klass_reg = FrameMap::rdx_metadata_opr;
1158
1159 length.load_item_force(FrameMap::rbx_opr);
1160 LIR_Opr len = length.result();
1161
1162 CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info);
1163 ciKlass* obj = (ciKlass*) ciObjArrayKlass::make(x->klass());
1164 if (obj == ciEnv::unloaded_ciobjarrayklass()) {
1165 BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
1166 }
1167 klass2reg_with_patching(klass_reg, obj, patching_info);
1168 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, T_OBJECT, klass_reg, slow_path);
1169
1170 LIR_Opr result = rlock_result(x);
1171 __ move(reg, result);
1172 }
1173
1174
1175 void LIRGenerator::do_NewMultiArray(NewMultiArray* x) {
1176 Values* dims = x->dims();
1177 int i = dims->length();
1178 LIRItemList* items = new LIRItemList(dims->length(), NULL);
1179 while (i-- > 0) {
1180 LIRItem* size = new LIRItem(dims->at(i), this);
1181 items->at_put(i, size);
1182 }
1183
1184 // Evaluate state_for early since it may emit code.
1185 CodeEmitInfo* patching_info = NULL;
1186 if (!x->klass()->is_loaded() || PatchALot) {
1187 patching_info = state_for(x, x->state_before());
1188
1189 // Cannot re-use same xhandlers for multiple CodeEmitInfos, so
1190 // clone all handlers (NOTE: Usually this is handled transparently
1191 // by the CodeEmitInfo cloning logic in CodeStub constructors but
1192 // is done explicitly here because a stub isn't being used).
1193 x->set_exception_handlers(new XHandlers(x->exception_handlers()));
1194 }
1195 CodeEmitInfo* info = state_for(x, x->state());
1196
1197 i = dims->length();
1198 while (i-- > 0) {
1199 LIRItem* size = items->at(i);
1200 size->load_nonconstant();
1201
1202 store_stack_parameter(size->result(), in_ByteSize(i*4));
1203 }
1204
1205 LIR_Opr klass_reg = FrameMap::rax_metadata_opr;
1206 klass2reg_with_patching(klass_reg, x->klass(), patching_info);
1207
1208 LIR_Opr rank = FrameMap::rbx_opr;
1209 __ move(LIR_OprFact::intConst(x->rank()), rank);
1210 LIR_Opr varargs = FrameMap::rcx_opr;
1211 __ move(FrameMap::rsp_opr, varargs);
1212 LIR_OprList* args = new LIR_OprList(3);
1213 args->append(klass_reg);
1214 args->append(rank);
1215 args->append(varargs);
1216 LIR_Opr reg = result_register_for(x->type());
1217 __ call_runtime(Runtime1::entry_for(Runtime1::new_multi_array_id),
1218 LIR_OprFact::illegalOpr,
1219 reg, args, info);
1220
1221 LIR_Opr result = rlock_result(x);
1222 __ move(reg, result);
1223 }
1224
1225
1226 void LIRGenerator::do_BlockBegin(BlockBegin* x) {
1227 // nothing to do for now
1228 }
1229
1230
1231 void LIRGenerator::do_CheckCast(CheckCast* x) {
1232 LIRItem obj(x->obj(), this);
1233
1234 CodeEmitInfo* patching_info = NULL;
1235 if (!x->klass()->is_loaded() || (PatchALot && !x->is_incompatible_class_change_check())) {
1236 // must do this before locking the destination register as an oop register,
1237 // and before the obj is loaded (the latter is for deoptimization)
1238 patching_info = state_for(x, x->state_before());
1239 }
1240 obj.load_item();
1241
1242 // info for exceptions
1243 CodeEmitInfo* info_for_exception =
1244 (x->needs_exception_state() ? state_for(x) :
1245 state_for(x, x->state_before(), true /*ignore_xhandler*/));
1246
1247 CodeStub* stub;
1248 if (x->is_incompatible_class_change_check()) {
1249 assert(patching_info == NULL, "can't patch this");
1250 stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception);
1251 } else if (x->is_invokespecial_receiver_check()) {
1252 assert(patching_info == NULL, "can't patch this");
1253 stub = new DeoptimizeStub(info_for_exception);
1254 } else {
1255 stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception);
1256 }
1257 LIR_Opr reg = rlock_result(x);
1258 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1259 if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
1260 tmp3 = new_register(objectType);
1261 }
1262 __ checkcast(reg, obj.result(), x->klass(),
1263 new_register(objectType), new_register(objectType), tmp3,
1264 x->direct_compare(), info_for_exception, patching_info, stub,
1265 x->profiled_method(), x->profiled_bci());
1266 }
1267
1268
1269 void LIRGenerator::do_InstanceOf(InstanceOf* x) {
1270 LIRItem obj(x->obj(), this);
1271
1272 // result and test object may not be in same register
1273 LIR_Opr reg = rlock_result(x);
1274 CodeEmitInfo* patching_info = NULL;
1275 if ((!x->klass()->is_loaded() || PatchALot)) {
1276 // must do this before locking the destination register as an oop register
1277 patching_info = state_for(x, x->state_before());
1278 }
1279 obj.load_item();
1280 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1281 if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
1282 tmp3 = new_register(objectType);
1283 }
1284 __ instanceof(reg, obj.result(), x->klass(),
1285 new_register(objectType), new_register(objectType), tmp3,
1286 x->direct_compare(), patching_info, x->profiled_method(), x->profiled_bci());
1287 }
1288
1289
1290 void LIRGenerator::do_If(If* x) {
1291 assert(x->number_of_sux() == 2, "inconsistency");
1292 ValueTag tag = x->x()->type()->tag();
1293 bool is_safepoint = x->is_safepoint();
1294
1295 If::Condition cond = x->cond();
1296
1297 LIRItem xitem(x->x(), this);
1298 LIRItem yitem(x->y(), this);
1299 LIRItem* xin = &xitem;
1300 LIRItem* yin = &yitem;
1301
1302 if (tag == longTag) {
1303 // for longs, only conditions "eql", "neq", "lss", "geq" are valid;
1304 // mirror for other conditions
1305 if (cond == If::gtr || cond == If::leq) {
1306 cond = Instruction::mirror(cond);
1307 xin = &yitem;
1308 yin = &xitem;
1309 }
1310 xin->set_destroys_register();
1311 }
1312 xin->load_item();
1313 if (tag == longTag && yin->is_constant() && yin->get_jlong_constant() == 0 && (cond == If::eql || cond == If::neq)) {
1314 // inline long zero
1315 yin->dont_load_item();
1316 } else if (tag == longTag || tag == floatTag || tag == doubleTag) {
1317 // longs cannot handle constants at right side
1318 yin->load_item();
1319 } else {
1320 yin->dont_load_item();
1321 }
1322
1323 // add safepoint before generating condition code so it can be recomputed
1324 if (x->is_safepoint()) {
1325 // increment backedge counter if needed
1326 increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci());
1327 __ safepoint(LIR_OprFact::illegalOpr, state_for(x, x->state_before()));
1328 }
1329 set_no_result(x);
1330
1331 LIR_Opr left = xin->result();
1332 LIR_Opr right = yin->result();
1333 __ cmp(lir_cond(cond), left, right);
1334 // Generate branch profiling. Profiling code doesn't kill flags.
1335 profile_branch(x, cond);
1336 move_to_phi(x->state());
1337 if (x->x()->type()->is_float_kind()) {
1338 __ branch(lir_cond(cond), right->type(), x->tsux(), x->usux());
1339 } else {
1340 __ branch(lir_cond(cond), right->type(), x->tsux());
1341 }
1342 assert(x->default_sux() == x->fsux(), "wrong destination above");
1343 __ jump(x->default_sux());
1344 }
1345
1346
1347 LIR_Opr LIRGenerator::getThreadPointer() {
1348 #ifdef _LP64
1349 return FrameMap::as_pointer_opr(r15_thread);
1350 #else
1351 LIR_Opr result = new_register(T_INT);
1352 __ get_thread(result);
1353 return result;
1354 #endif //
1355 }
1356
1357 void LIRGenerator::trace_block_entry(BlockBegin* block) {
1358 store_stack_parameter(LIR_OprFact::intConst(block->block_id()), in_ByteSize(0));
1359 LIR_OprList* args = new LIR_OprList();
1360 address func = CAST_FROM_FN_PTR(address, Runtime1::trace_block_entry);
1361 __ call_runtime_leaf(func, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, args);
1362 }
1363
1364
1365 void LIRGenerator::volatile_field_store(LIR_Opr value, LIR_Address* address,
1366 CodeEmitInfo* info) {
1367 if (address->type() == T_LONG) {
1368 address = new LIR_Address(address->base(),
1369 address->index(), address->scale(),
1370 address->disp(), T_DOUBLE);
1371 // Transfer the value atomically by using FP moves. This means
1372 // the value has to be moved between CPU and FPU registers. It
1373 // always has to be moved through spill slot since there's no
1374 // quick way to pack the value into an SSE register.
1375 LIR_Opr temp_double = new_register(T_DOUBLE);
1376 LIR_Opr spill = new_register(T_LONG);
1377 set_vreg_flag(spill, must_start_in_memory);
1378 __ move(value, spill);
1379 __ volatile_move(spill, temp_double, T_LONG);
1380 __ volatile_move(temp_double, LIR_OprFact::address(address), T_LONG, info);
1381 } else {
1382 __ store(value, address, info);
1383 }
1384 }
1385
1386
1387
1388 void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
1389 CodeEmitInfo* info) {
1390 if (address->type() == T_LONG) {
1391 address = new LIR_Address(address->base(),
1392 address->index(), address->scale(),
1393 address->disp(), T_DOUBLE);
1394 // Transfer the value atomically by using FP moves. This means
1395 // the value has to be moved between CPU and FPU registers. In
1396 // SSE0 and SSE1 mode it has to be moved through spill slot but in
1397 // SSE2+ mode it can be moved directly.
1398 LIR_Opr temp_double = new_register(T_DOUBLE);
1399 __ volatile_move(LIR_OprFact::address(address), temp_double, T_LONG, info);
1400 __ volatile_move(temp_double, result, T_LONG);
1401 if (UseSSE < 2) {
1402 // no spill slot needed in SSE2 mode because xmm->cpu register move is possible
1403 set_vreg_flag(result, must_start_in_memory);
1404 }
1405 } else {
1406 __ load(address, result, info);
1407 }
1408 }
1409
1410 void LIRGenerator::get_Object_unsafe(LIR_Opr dst, LIR_Opr src, LIR_Opr offset,
1411 BasicType type, bool is_volatile) {
1412 if (is_volatile && type == T_LONG) {
1413 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1414 LIR_Opr tmp = new_register(T_DOUBLE);
1415 __ load(addr, tmp);
1416 LIR_Opr spill = new_register(T_LONG);
1417 set_vreg_flag(spill, must_start_in_memory);
1418 __ move(tmp, spill);
1419 __ move(spill, dst);
1420 } else {
1421 LIR_Address* addr = new LIR_Address(src, offset, type);
1422 __ load(addr, dst);
1423 }
1424 }
1425
1426
1427 void LIRGenerator::put_Object_unsafe(LIR_Opr src, LIR_Opr offset, LIR_Opr data,
1428 BasicType type, bool is_volatile) {
1429 if (is_volatile && type == T_LONG) {
1430 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1431 LIR_Opr tmp = new_register(T_DOUBLE);
1432 LIR_Opr spill = new_register(T_DOUBLE);
1433 set_vreg_flag(spill, must_start_in_memory);
1434 __ move(data, spill);
1435 __ move(spill, tmp);
1436 __ move(tmp, addr);
1437 } else {
1438 LIR_Address* addr = new LIR_Address(src, offset, type);
1439 bool is_obj = (type == T_ARRAY || type == T_OBJECT);
1440 if (is_obj) {
1441 // Do the pre-write barrier, if any.
1442 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1443 true /* do_load */, false /* patch */, NULL);
1444 __ move(data, addr);
1445 assert(src->is_register(), "must be register");
1446 // Seems to be a precise address
1447 post_barrier(LIR_OprFact::address(addr), data);
1448 } else {
1449 __ move(data, addr);
1450 }
1451 }
1452 }
1453
1454 void LIRGenerator::do_UnsafeGetAndSetObject(UnsafeGetAndSetObject* x) {
1455 BasicType type = x->basic_type();
1456 LIRItem src(x->object(), this);
1457 LIRItem off(x->offset(), this);
1458 LIRItem value(x->value(), this);
1459
1460 src.load_item();
1461 value.load_item();
1462 off.load_nonconstant();
1463
1464 LIR_Opr dst = rlock_result(x, type);
1465 LIR_Opr data = value.result();
1466 bool is_obj = (type == T_ARRAY || type == T_OBJECT);
1467 LIR_Opr offset = off.result();
1468
1469 assert (type == T_INT || (!x->is_add() && is_obj) LP64_ONLY( || type == T_LONG ), "unexpected type");
1470 LIR_Address* addr;
1471 if (offset->is_constant()) {
1472 #ifdef _LP64
1473 jlong c = offset->as_jlong();
1474 if ((jlong)((jint)c) == c) {
1475 addr = new LIR_Address(src.result(), (jint)c, type);
1476 } else {
1477 LIR_Opr tmp = new_register(T_LONG);
1478 __ move(offset, tmp);
1479 addr = new LIR_Address(src.result(), tmp, type);
1480 }
1481 #else
1482 addr = new LIR_Address(src.result(), offset->as_jint(), type);
1483 #endif
1484 } else {
1485 addr = new LIR_Address(src.result(), offset, type);
1486 }
1487
1488 // Because we want a 2-arg form of xchg and xadd
1489 __ move(data, dst);
1490
1491 if (x->is_add()) {
1492 __ xadd(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1493 } else {
1494 if (is_obj) {
1495 // Do the pre-write barrier, if any.
1496 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1497 true /* do_load */, false /* patch */, NULL);
1498 }
1499 __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1500
1501 #if INCLUDE_ALL_GCS
1502 if (UseShenandoahGC && is_obj) {
1503 dst = ShenandoahBarrierSet::barrier_set()->bsc1()->load_reference_barrier(this, dst, NULL, true);
1504 LIR_Opr tmp = new_register(type);
1505 __ move(dst, tmp);
1506 dst = tmp;
1507 }
1508 #endif
1509
1510 if (is_obj) {
1511 // Seems to be a precise address
1512 post_barrier(LIR_OprFact::address(addr), data);
1513 }
1514 }
1515 }