1 /* 2 * Copyright (c) 2018, 2019, Red Hat, Inc. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_LIRAssembler.hpp" 27 #include "c1/c1_MacroAssembler.hpp" 28 #include "gc/shenandoah/shenandoahBarrierSet.hpp" 29 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" 30 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" 31 32 #define __ masm->masm()-> 33 34 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { 35 NOT_LP64(assert(_addr->is_single_cpu(), "must be single");) 36 Register addr = _addr->is_single_cpu() ? _addr->as_register() : _addr->as_register_lo(); 37 Register newval = _new_value->as_register(); 38 Register cmpval = _cmp_value->as_register(); 39 Register tmp1 = _tmp1->as_register(); 40 Register tmp2 = _tmp2->as_register(); 41 Register result = result_opr()->as_register(); 42 assert(cmpval == rax, "wrong register"); 43 assert(newval != NULL, "new val must be register"); 44 assert(cmpval != newval, "cmp and new values must be in different registers"); 45 assert(cmpval != addr, "cmp and addr must be in different registers"); 46 assert(newval != addr, "new value and addr must be in different registers"); 47 48 // Apply storeval barrier to newval. 49 ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, tmp1); 50 51 #ifdef _LP64 52 if (UseCompressedOops) { 53 __ encode_heap_oop(cmpval); 54 __ mov(rscratch1, newval); 55 __ encode_heap_oop(rscratch1); 56 newval = rscratch1; 57 } 58 #endif 59 60 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), result, Address(addr, 0), cmpval, newval, false, tmp1, tmp2); 61 } 62 63 #undef __ 64 65 #ifdef ASSERT 66 #define __ gen->lir(__FILE__, __LINE__)-> 67 #else 68 #define __ gen->lir()-> 69 #endif 70 71 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) { 72 73 if (access.is_oop()) { 74 LIRGenerator* gen = access.gen(); 75 if (ShenandoahSATBBarrier) { 76 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(), 77 LIR_OprFact::illegalOpr /* pre_val */); 78 } 79 if (ShenandoahCASBarrier) { 80 cmp_value.load_item_force(FrameMap::rax_oop_opr); 81 new_value.load_item(); 82 83 LIR_Opr t1 = gen->new_register(T_OBJECT); 84 LIR_Opr t2 = gen->new_register(T_OBJECT); 85 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); 86 LIR_Opr result = gen->new_register(T_INT); 87 88 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result)); 89 return result; 90 } 91 } 92 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); 93 } 94 95 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) { 96 LIRGenerator* gen = access.gen(); 97 BasicType type = access.type(); 98 99 LIR_Opr result = gen->new_register(type); 100 value.load_item(); 101 LIR_Opr value_opr = value.result(); 102 103 if (access.is_oop()) { 104 value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators()); 105 } 106 107 // Because we want a 2-arg form of xchg and xadd 108 __ move(value_opr, result); 109 110 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type"); 111 __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr); 112 113 if (access.is_oop()) { 114 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0)); 115 LIR_Opr tmp = gen->new_register(type); 116 __ move(result, tmp); 117 result = tmp; 118 if (ShenandoahSATBBarrier) { 119 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, 120 result /* pre_val */); 121 } 122 } 123 124 return result; 125 }