1 // Sundry CAS operations. Note that release is always true, 2 // regardless of the memory ordering of the CAS. This is because we 3 // need the volatile case to be sequentially consistent but there is 4 // no trailing StoreLoad barrier emitted by C2. Unfortunately we 5 // can't check the type of memory ordering here, so we always emit a 6 // STLXR. 7 8 define(`CAS_INSN', 9 ` 10 instruct compareAndExchange$1$5(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{ 11 match(Set res (CompareAndExchange$1 mem (Binary oldval newval))); 12 ifelse($5,Acq,' predicate(needs_acquiring_load_exclusive(n)); 13 ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`) 14 effect(KILL cr); 15 format %{ 16 "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval" 17 %} 18 ins_encode %{ 19 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, 20 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 21 /*weak*/ false, $res$$Register); 22 %} 23 ins_pipe(pipe_slow); 24 %}')dnl 25 define(`CAS_INSN4', 26 ` 27 instruct compareAndExchange$1$7(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{ 28 match(Set res (CompareAndExchange$1 mem (Binary oldval newval))); 29 ifelse($7,Acq,' predicate(needs_acquiring_load_exclusive(n)); 30 ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`) 31 effect(KILL cr); 32 format %{ 33 "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval" 34 %} 35 ins_encode %{ 36 __ $5(rscratch2, $oldval$$Register); 37 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register, 38 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 39 /*weak*/ false, $res$$Register); 40 __ $6($res$$Register, $res$$Register); 41 %} 42 ins_pipe(pipe_slow); 43 %}')dnl 44 CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw) 45 CAS_INSN4(S,I,short,halfword,uxthw,sxthw) 46 CAS_INSN(I,I,int,word) 47 CAS_INSN(L,L,long,xword) 48 CAS_INSN(N,N,narrow oop,word) 49 CAS_INSN(P,P,ptr,xword) 50 dnl 51 dnl CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw,Acq) 90 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, 91 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 92 /*weak*/ true, noreg); 93 __ csetw($res$$Register, Assembler::EQ); 94 %} 95 ins_pipe(pipe_slow); 96 %}')dnl 97 CAS_INSN2(B,I,byte,byte,bw) 98 CAS_INSN2(S,I,short,halfword,hw) 99 CAS_INSN3(I,I,int,word) 100 CAS_INSN3(L,L,long,xword) 101 CAS_INSN3(N,N,narrow oop,word) 102 CAS_INSN3(P,P,ptr,xword) 103 dnl CAS_INSN2(B,I,byte,byte,bw,Acq) 104 dnl CAS_INSN2(S,I,short,halfword,hw,Acq) 105 dnl CAS_INSN3(I,I,int,word,Acq) 106 dnl CAS_INSN3(L,L,long,xword,Acq) 107 dnl CAS_INSN3(N,N,narrow oop,word,Acq) 108 dnl CAS_INSN3(P,P,ptr,xword,Acq) 109 dnl | 1 dnl Copyright (c) 2014, Red Hat Inc. All rights reserved. 2 dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 dnl 4 dnl This code is free software; you can redistribute it and/or modify it 5 dnl under the terms of the GNU General Public License version 2 only, as 6 dnl published by the Free Software Foundation. 7 dnl 8 dnl This code is distributed in the hope that it will be useful, but WITHOUT 9 dnl ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 dnl FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 dnl version 2 for more details (a copy is included in the LICENSE file that 12 dnl accompanied this code). 13 dnl 14 dnl You should have received a copy of the GNU General Public License version 15 dnl 2 along with this work; if not, write to the Free Software Foundation, 16 dnl Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 17 dnl 18 dnl Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 19 dnl or visit www.oracle.com if you need additional information or have any 20 dnl questions. 21 dnl 22 dnl 23 dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic 24 dnl and shift patterns patterns used in aarch64.ad. 25 dnl 26 27 // BEGIN This section of the file is automatically generated. Do not edit -------------- 28 29 // Sundry CAS operations. Note that release is always true, 30 // regardless of the memory ordering of the CAS. This is because we 31 // need the volatile case to be sequentially consistent but there is 32 // no trailing StoreLoad barrier emitted by C2. Unfortunately we 33 // can't check the type of memory ordering here, so we always emit a 34 // STLXR. 35 36 // This section is generated from aarch64_ad_cas.m4 37 38 39 define(`CAS_INSN', 40 ` 41 instruct compareAndExchange$1$5(iReg$2NoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{ 42 match(Set res (CompareAndExchange$1 mem (Binary oldval newval))); 43 ifelse($5,Acq,' predicate(needs_acquiring_load_exclusive(n)); 44 ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`) 45 effect(TEMP_DEF res, KILL cr); 46 format %{ 47 "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval" 48 %} 49 ins_encode %{ 50 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, 51 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 52 /*weak*/ false, $res$$Register); 53 %} 54 ins_pipe(pipe_slow); 55 %}')dnl 56 define(`CAS_INSN4', 57 ` 58 instruct compareAndExchange$1$7(iReg$2NoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{ 59 match(Set res (CompareAndExchange$1 mem (Binary oldval newval))); 60 ifelse($7,Acq,' predicate(needs_acquiring_load_exclusive(n)); 61 ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`) 62 effect(TEMP_DEF res, KILL cr); 63 format %{ 64 "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval" 65 %} 66 ins_encode %{ 67 __ $5(rscratch2, $oldval$$Register); 68 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register, 69 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 70 /*weak*/ false, $res$$Register); 71 __ $6($res$$Register, $res$$Register); 72 %} 73 ins_pipe(pipe_slow); 74 %}')dnl 75 CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw) 76 CAS_INSN4(S,I,short,halfword,uxthw,sxthw) 77 CAS_INSN(I,I,int,word) 78 CAS_INSN(L,L,long,xword) 79 CAS_INSN(N,N,narrow oop,word) 80 CAS_INSN(P,P,ptr,xword) 81 dnl 82 dnl CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw,Acq) 121 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, 122 Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true, 123 /*weak*/ true, noreg); 124 __ csetw($res$$Register, Assembler::EQ); 125 %} 126 ins_pipe(pipe_slow); 127 %}')dnl 128 CAS_INSN2(B,I,byte,byte,bw) 129 CAS_INSN2(S,I,short,halfword,hw) 130 CAS_INSN3(I,I,int,word) 131 CAS_INSN3(L,L,long,xword) 132 CAS_INSN3(N,N,narrow oop,word) 133 CAS_INSN3(P,P,ptr,xword) 134 dnl CAS_INSN2(B,I,byte,byte,bw,Acq) 135 dnl CAS_INSN2(S,I,short,halfword,hw,Acq) 136 dnl CAS_INSN3(I,I,int,word,Acq) 137 dnl CAS_INSN3(L,L,long,xword,Acq) 138 dnl CAS_INSN3(N,N,narrow oop,word,Acq) 139 dnl CAS_INSN3(P,P,ptr,xword,Acq) 140 dnl 141 142 // END This section of the file is automatically generated. Do not edit -------------- |