1 //
2 // Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 // AArch64 Architecture Description File
27
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
32
33 register %{
34 //----------Architecture Description Register Definitions----------------------
35 // General Registers
36 // "reg_def" name ( register save type, C convention save type,
37 // ideal register type, encoding );
38 // Register Save Types:
39 //
40 // NS = No-Save: The register allocator assumes that these registers
41 // can be used without saving upon entry to the method, &
42 // that they do not need to be saved at call sites.
43 //
44 // SOC = Save-On-Call: The register allocator assumes that these registers
45 // can be used without saving upon entry to the method,
46 // but that they must be saved at call sites.
47 //
48 // SOE = Save-On-Entry: The register allocator assumes that these registers
49 // must be saved before using them upon entry to the
50 // method, but they do not need to be saved at call
51 // sites.
52 //
53 // AS = Always-Save: The register allocator assumes that these registers
54 // must be saved before using them upon entry to the
55 // method, & that they must be saved at call sites.
56 //
57 // Ideal Register Type is used to determine how to save & restore a
58 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
59 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
60 //
61 // The encoding number is the actual bit-pattern placed into the opcodes.
62
63 // We must define the 64 bit int registers in two 32 bit halves, the
64 // real lower register and a virtual upper half register. upper halves
65 // are used by the register allocator but are not actually supplied as
66 // operands to memory ops.
67 //
68 // follow the C1 compiler in making registers
69 //
70 // r0-r7,r10-r26 volatile (caller save)
71 // r27-r32 system (no save, no allocate)
72 // r8-r9 invisible to the allocator (so we can use them as scratch regs)
73 //
74 // as regards Java usage. we don't use any callee save registers
75 // because this makes it difficult to de-optimise a frame (see comment
76 // in x86 implementation of Deoptimization::unwind_callee_save_values)
77 //
78
79 // General Registers
80
81 reg_def R0 ( SOC, SOC, Op_RegI, 0, r0->as_VMReg() );
82 reg_def R0_H ( SOC, SOC, Op_RegI, 0, r0->as_VMReg()->next() );
83 reg_def R1 ( SOC, SOC, Op_RegI, 1, r1->as_VMReg() );
84 reg_def R1_H ( SOC, SOC, Op_RegI, 1, r1->as_VMReg()->next() );
85 reg_def R2 ( SOC, SOC, Op_RegI, 2, r2->as_VMReg() );
86 reg_def R2_H ( SOC, SOC, Op_RegI, 2, r2->as_VMReg()->next() );
87 reg_def R3 ( SOC, SOC, Op_RegI, 3, r3->as_VMReg() );
88 reg_def R3_H ( SOC, SOC, Op_RegI, 3, r3->as_VMReg()->next() );
89 reg_def R4 ( SOC, SOC, Op_RegI, 4, r4->as_VMReg() );
90 reg_def R4_H ( SOC, SOC, Op_RegI, 4, r4->as_VMReg()->next() );
91 reg_def R5 ( SOC, SOC, Op_RegI, 5, r5->as_VMReg() );
92 reg_def R5_H ( SOC, SOC, Op_RegI, 5, r5->as_VMReg()->next() );
93 reg_def R6 ( SOC, SOC, Op_RegI, 6, r6->as_VMReg() );
94 reg_def R6_H ( SOC, SOC, Op_RegI, 6, r6->as_VMReg()->next() );
95 reg_def R7 ( SOC, SOC, Op_RegI, 7, r7->as_VMReg() );
96 reg_def R7_H ( SOC, SOC, Op_RegI, 7, r7->as_VMReg()->next() );
97 reg_def R10 ( SOC, SOC, Op_RegI, 10, r10->as_VMReg() );
98 reg_def R10_H ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
99 reg_def R11 ( SOC, SOC, Op_RegI, 11, r11->as_VMReg() );
100 reg_def R11_H ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
101 reg_def R12 ( SOC, SOC, Op_RegI, 12, r12->as_VMReg() );
102 reg_def R12_H ( SOC, SOC, Op_RegI, 12, r12->as_VMReg()->next());
103 reg_def R13 ( SOC, SOC, Op_RegI, 13, r13->as_VMReg() );
104 reg_def R13_H ( SOC, SOC, Op_RegI, 13, r13->as_VMReg()->next());
105 reg_def R14 ( SOC, SOC, Op_RegI, 14, r14->as_VMReg() );
106 reg_def R14_H ( SOC, SOC, Op_RegI, 14, r14->as_VMReg()->next());
107 reg_def R15 ( SOC, SOC, Op_RegI, 15, r15->as_VMReg() );
108 reg_def R15_H ( SOC, SOC, Op_RegI, 15, r15->as_VMReg()->next());
109 reg_def R16 ( SOC, SOC, Op_RegI, 16, r16->as_VMReg() );
110 reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
111 reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() );
112 reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
113 reg_def R18 ( SOC, SOC, Op_RegI, 18, r18->as_VMReg() );
114 reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
115 reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() );
116 reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next());
117 reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp
118 reg_def R20_H ( SOC, SOE, Op_RegI, 20, r20->as_VMReg()->next());
119 reg_def R21 ( SOC, SOE, Op_RegI, 21, r21->as_VMReg() );
120 reg_def R21_H ( SOC, SOE, Op_RegI, 21, r21->as_VMReg()->next());
121 reg_def R22 ( SOC, SOE, Op_RegI, 22, r22->as_VMReg() );
122 reg_def R22_H ( SOC, SOE, Op_RegI, 22, r22->as_VMReg()->next());
123 reg_def R23 ( SOC, SOE, Op_RegI, 23, r23->as_VMReg() );
124 reg_def R23_H ( SOC, SOE, Op_RegI, 23, r23->as_VMReg()->next());
125 reg_def R24 ( SOC, SOE, Op_RegI, 24, r24->as_VMReg() );
126 reg_def R24_H ( SOC, SOE, Op_RegI, 24, r24->as_VMReg()->next());
127 reg_def R25 ( SOC, SOE, Op_RegI, 25, r25->as_VMReg() );
128 reg_def R25_H ( SOC, SOE, Op_RegI, 25, r25->as_VMReg()->next());
129 reg_def R26 ( SOC, SOE, Op_RegI, 26, r26->as_VMReg() );
130 reg_def R26_H ( SOC, SOE, Op_RegI, 26, r26->as_VMReg()->next());
131 reg_def R27 ( NS, SOE, Op_RegI, 27, r27->as_VMReg() ); // heapbase
132 reg_def R27_H ( NS, SOE, Op_RegI, 27, r27->as_VMReg()->next());
133 reg_def R28 ( NS, SOE, Op_RegI, 28, r28->as_VMReg() ); // thread
134 reg_def R28_H ( NS, SOE, Op_RegI, 28, r28->as_VMReg()->next());
135 reg_def R29 ( NS, NS, Op_RegI, 29, r29->as_VMReg() ); // fp
136 reg_def R29_H ( NS, NS, Op_RegI, 29, r29->as_VMReg()->next());
137 reg_def R30 ( NS, NS, Op_RegI, 30, r30->as_VMReg() ); // lr
138 reg_def R30_H ( NS, NS, Op_RegI, 30, r30->as_VMReg()->next());
139 reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp
140 reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Double Registers
147
148 // The rules of ADL require that double registers be defined in pairs.
149 // Each pair must be two 32-bit values, but not necessarily a pair of
150 // single float registers. In each pair, ADLC-assigned register numbers
151 // must be adjacent, with the lower number even. Finally, when the
152 // CPU stores such a register pair to memory, the word associated with
153 // the lower ADLC-assigned number must be stored to the lower address.
154
155 // AArch64 has 32 floating-point registers. Each can store a vector of
156 // single or double precision floating-point values up to 8 * 32
157 // floats, 4 * 64 bit floats or 2 * 128 bit floats. We currently only
158 // use the first float or double element of the vector.
159
160 // for Java use float registers v0-v15 are always save on call whereas
161 // the platform ABI treats v8-v15 as callee save). float registers
162 // v16-v31 are SOC as per the platform spec
163
164 reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() );
165 reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() );
166 reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) );
167 reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) );
168
169 reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() );
170 reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() );
171 reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) );
172 reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) );
173
174 reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() );
175 reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() );
176 reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) );
177 reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) );
178
179 reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() );
180 reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() );
181 reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) );
182 reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) );
183
184 reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() );
185 reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() );
186 reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) );
187 reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) );
188
189 reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() );
190 reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() );
191 reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) );
192 reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) );
193
194 reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() );
195 reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() );
196 reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) );
197 reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) );
198
199 reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() );
200 reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() );
201 reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) );
202 reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) );
203
204 reg_def V8 ( SOC, SOC, Op_RegF, 8, v8->as_VMReg() );
205 reg_def V8_H ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next() );
206 reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) );
207 reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) );
208
209 reg_def V9 ( SOC, SOC, Op_RegF, 9, v9->as_VMReg() );
210 reg_def V9_H ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next() );
211 reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) );
212 reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) );
213
214 reg_def V10 ( SOC, SOC, Op_RegF, 10, v10->as_VMReg() );
215 reg_def V10_H( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next() );
216 reg_def V10_J( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2));
217 reg_def V10_K( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3));
218
219 reg_def V11 ( SOC, SOC, Op_RegF, 11, v11->as_VMReg() );
220 reg_def V11_H( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next() );
221 reg_def V11_J( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2));
222 reg_def V11_K( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3));
223
224 reg_def V12 ( SOC, SOC, Op_RegF, 12, v12->as_VMReg() );
225 reg_def V12_H( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next() );
226 reg_def V12_J( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2));
227 reg_def V12_K( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3));
228
229 reg_def V13 ( SOC, SOC, Op_RegF, 13, v13->as_VMReg() );
230 reg_def V13_H( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next() );
231 reg_def V13_J( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2));
232 reg_def V13_K( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3));
233
234 reg_def V14 ( SOC, SOC, Op_RegF, 14, v14->as_VMReg() );
235 reg_def V14_H( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next() );
236 reg_def V14_J( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2));
237 reg_def V14_K( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3));
238
239 reg_def V15 ( SOC, SOC, Op_RegF, 15, v15->as_VMReg() );
240 reg_def V15_H( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next() );
241 reg_def V15_J( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2));
242 reg_def V15_K( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3));
243
244 reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() );
245 reg_def V16_H( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() );
246 reg_def V16_J( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2));
247 reg_def V16_K( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3));
248
249 reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() );
250 reg_def V17_H( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() );
251 reg_def V17_J( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2));
252 reg_def V17_K( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3));
253
254 reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() );
255 reg_def V18_H( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() );
256 reg_def V18_J( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2));
257 reg_def V18_K( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3));
258
259 reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() );
260 reg_def V19_H( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() );
261 reg_def V19_J( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2));
262 reg_def V19_K( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3));
263
264 reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() );
265 reg_def V20_H( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() );
266 reg_def V20_J( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2));
267 reg_def V20_K( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3));
268
269 reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() );
270 reg_def V21_H( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() );
271 reg_def V21_J( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2));
272 reg_def V21_K( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3));
273
274 reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() );
275 reg_def V22_H( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() );
276 reg_def V22_J( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2));
277 reg_def V22_K( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3));
278
279 reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() );
280 reg_def V23_H( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() );
281 reg_def V23_J( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2));
282 reg_def V23_K( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3));
283
284 reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() );
285 reg_def V24_H( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() );
286 reg_def V24_J( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2));
287 reg_def V24_K( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3));
288
289 reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() );
290 reg_def V25_H( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() );
291 reg_def V25_J( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2));
292 reg_def V25_K( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3));
293
294 reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() );
295 reg_def V26_H( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() );
296 reg_def V26_J( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2));
297 reg_def V26_K( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3));
298
299 reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() );
300 reg_def V27_H( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() );
301 reg_def V27_J( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2));
302 reg_def V27_K( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3));
303
304 reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() );
305 reg_def V28_H( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() );
306 reg_def V28_J( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2));
307 reg_def V28_K( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3));
308
309 reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() );
310 reg_def V29_H( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() );
311 reg_def V29_J( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2));
312 reg_def V29_K( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3));
313
314 reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() );
315 reg_def V30_H( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() );
316 reg_def V30_J( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2));
317 reg_def V30_K( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3));
318
319 reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() );
320 reg_def V31_H( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() );
321 reg_def V31_J( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2));
322 reg_def V31_K( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3));
323
324 // ----------------------------
325 // Special Registers
326 // ----------------------------
327
328 // the AArch64 CSPR status flag register is not directly acessible as
329 // instruction operand. the FPSR status flag register is a system
330 // register which can be written/read using MSR/MRS but again does not
331 // appear as an operand (a code identifying the FSPR occurs as an
332 // immediate value in the instruction).
333
334 reg_def RFLAGS(SOC, SOC, 0, 32, VMRegImpl::Bad());
335
336
337 // Specify priority of register selection within phases of register
338 // allocation. Highest priority is first. A useful heuristic is to
339 // give registers a low priority when they are required by machine
340 // instructions, like EAX and EDX on I486, and choose no-save registers
341 // before save-on-call, & save-on-call before save-on-entry. Registers
342 // which participate in fixed calling sequences should come last.
343 // Registers which are used as pairs must fall on an even boundary.
344
345 alloc_class chunk0(
346 // volatiles
347 R10, R10_H,
348 R11, R11_H,
349 R12, R12_H,
350 R13, R13_H,
351 R14, R14_H,
352 R15, R15_H,
353 R16, R16_H,
354 R17, R17_H,
355 R18, R18_H,
356
357 // arg registers
358 R0, R0_H,
359 R1, R1_H,
360 R2, R2_H,
361 R3, R3_H,
362 R4, R4_H,
363 R5, R5_H,
364 R6, R6_H,
365 R7, R7_H,
366
367 // non-volatiles
368 R19, R19_H,
369 R20, R20_H,
370 R21, R21_H,
371 R22, R22_H,
372 R23, R23_H,
373 R24, R24_H,
374 R25, R25_H,
375 R26, R26_H,
376
377 // non-allocatable registers
378
379 R27, R27_H, // heapbase
380 R28, R28_H, // thread
381 R29, R29_H, // fp
382 R30, R30_H, // lr
383 R31, R31_H, // sp
384 );
385
386 alloc_class chunk1(
387
388 // no save
389 V16, V16_H, V16_J, V16_K,
390 V17, V17_H, V17_J, V17_K,
391 V18, V18_H, V18_J, V18_K,
392 V19, V19_H, V19_J, V19_K,
393 V20, V20_H, V20_J, V20_K,
394 V21, V21_H, V21_J, V21_K,
395 V22, V22_H, V22_J, V22_K,
396 V23, V23_H, V23_J, V23_K,
397 V24, V24_H, V24_J, V24_K,
398 V25, V25_H, V25_J, V25_K,
399 V26, V26_H, V26_J, V26_K,
400 V27, V27_H, V27_J, V27_K,
401 V28, V28_H, V28_J, V28_K,
402 V29, V29_H, V29_J, V29_K,
403 V30, V30_H, V30_J, V30_K,
404 V31, V31_H, V31_J, V31_K,
405
406 // arg registers
407 V0, V0_H, V0_J, V0_K,
408 V1, V1_H, V1_J, V1_K,
409 V2, V2_H, V2_J, V2_K,
410 V3, V3_H, V3_J, V3_K,
411 V4, V4_H, V4_J, V4_K,
412 V5, V5_H, V5_J, V5_K,
413 V6, V6_H, V6_J, V6_K,
414 V7, V7_H, V7_J, V7_K,
415
416 // non-volatiles
417 V8, V8_H, V8_J, V8_K,
418 V9, V9_H, V9_J, V9_K,
419 V10, V10_H, V10_J, V10_K,
420 V11, V11_H, V11_J, V11_K,
421 V12, V12_H, V12_J, V12_K,
422 V13, V13_H, V13_J, V13_K,
423 V14, V14_H, V14_J, V14_K,
424 V15, V15_H, V15_J, V15_K,
425 );
426
427 alloc_class chunk2(RFLAGS);
428
429 //----------Architecture Description Register Classes--------------------------
430 // Several register classes are automatically defined based upon information in
431 // this architecture description.
432 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
433 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
434 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
435 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
436 //
437
438 // Class for all 32 bit integer registers -- excludes SP which will
439 // never be used as an integer register
440 reg_class any_reg32(
441 R0,
442 R1,
443 R2,
444 R3,
445 R4,
446 R5,
447 R6,
448 R7,
449 R10,
450 R11,
451 R12,
452 R13,
453 R14,
454 R15,
455 R16,
456 R17,
457 R18,
458 R19,
459 R20,
460 R21,
461 R22,
462 R23,
463 R24,
464 R25,
465 R26,
466 R27,
467 R28,
468 R29,
469 R30
470 );
471
472 // Singleton class for R0 int register
473 reg_class int_r0_reg(R0);
474
475 // Singleton class for R2 int register
476 reg_class int_r2_reg(R2);
477
478 // Singleton class for R3 int register
479 reg_class int_r3_reg(R3);
480
481 // Singleton class for R4 int register
482 reg_class int_r4_reg(R4);
483
484 // Class for all long integer registers (including RSP)
485 reg_class any_reg(
486 R0, R0_H,
487 R1, R1_H,
488 R2, R2_H,
489 R3, R3_H,
490 R4, R4_H,
491 R5, R5_H,
492 R6, R6_H,
493 R7, R7_H,
494 R10, R10_H,
495 R11, R11_H,
496 R12, R12_H,
497 R13, R13_H,
498 R14, R14_H,
499 R15, R15_H,
500 R16, R16_H,
501 R17, R17_H,
502 R18, R18_H,
503 R19, R19_H,
504 R20, R20_H,
505 R21, R21_H,
506 R22, R22_H,
507 R23, R23_H,
508 R24, R24_H,
509 R25, R25_H,
510 R26, R26_H,
511 R27, R27_H,
512 R28, R28_H,
513 R29, R29_H,
514 R30, R30_H,
515 R31, R31_H
516 );
517
518 // Class for all non-special integer registers
519 reg_class no_special_reg32_no_fp(
520 R0,
521 R1,
522 R2,
523 R3,
524 R4,
525 R5,
526 R6,
527 R7,
528 R10,
529 R11,
530 R12, // rmethod
531 R13,
532 R14,
533 R15,
534 R16,
535 R17,
536 R18,
537 R19,
538 R20,
539 R21,
540 R22,
541 R23,
542 R24,
543 R25,
544 R26
545 /* R27, */ // heapbase
546 /* R28, */ // thread
547 /* R29, */ // fp
548 /* R30, */ // lr
549 /* R31 */ // sp
550 );
551
552 reg_class no_special_reg32_with_fp(
553 R0,
554 R1,
555 R2,
556 R3,
557 R4,
558 R5,
559 R6,
560 R7,
561 R10,
562 R11,
563 R12, // rmethod
564 R13,
565 R14,
566 R15,
567 R16,
568 R17,
569 R18,
570 R19,
571 R20,
572 R21,
573 R22,
574 R23,
575 R24,
576 R25,
577 R26
578 /* R27, */ // heapbase
579 /* R28, */ // thread
580 /* R29, */ // fp
581 /* R30, */ // lr
582 /* R31 */ // sp
583 );
584
585 reg_class_dynamic no_special_reg32(no_special_reg32_no_fp, no_special_reg32_with_fp, %{ PreserveFramePointer %});
586
587 // Class for all non-special long integer registers
588 reg_class no_special_reg_no_fp(
589 R0, R0_H,
590 R1, R1_H,
591 R2, R2_H,
592 R3, R3_H,
593 R4, R4_H,
594 R5, R5_H,
595 R6, R6_H,
596 R7, R7_H,
597 R10, R10_H,
598 R11, R11_H,
599 R12, R12_H, // rmethod
600 R13, R13_H,
601 R14, R14_H,
602 R15, R15_H,
603 R16, R16_H,
604 R17, R17_H,
605 R18, R18_H,
606 R19, R19_H,
607 R20, R20_H,
608 R21, R21_H,
609 R22, R22_H,
610 R23, R23_H,
611 R24, R24_H,
612 R25, R25_H,
613 R26, R26_H,
614 /* R27, R27_H, */ // heapbase
615 /* R28, R28_H, */ // thread
616 /* R29, R29_H, */ // fp
617 /* R30, R30_H, */ // lr
618 /* R31, R31_H */ // sp
619 );
620
621 reg_class no_special_reg_with_fp(
622 R0, R0_H,
623 R1, R1_H,
624 R2, R2_H,
625 R3, R3_H,
626 R4, R4_H,
627 R5, R5_H,
628 R6, R6_H,
629 R7, R7_H,
630 R10, R10_H,
631 R11, R11_H,
632 R12, R12_H, // rmethod
633 R13, R13_H,
634 R14, R14_H,
635 R15, R15_H,
636 R16, R16_H,
637 R17, R17_H,
638 R18, R18_H,
639 R19, R19_H,
640 R20, R20_H,
641 R21, R21_H,
642 R22, R22_H,
643 R23, R23_H,
644 R24, R24_H,
645 R25, R25_H,
646 R26, R26_H,
647 /* R27, R27_H, */ // heapbase
648 /* R28, R28_H, */ // thread
649 /* R29, R29_H, */ // fp
650 /* R30, R30_H, */ // lr
651 /* R31, R31_H */ // sp
652 );
653
654 reg_class_dynamic no_special_reg(no_special_reg_no_fp, no_special_reg_with_fp, %{ PreserveFramePointer %});
655
656 // Class for 64 bit register r0
657 reg_class r0_reg(
658 R0, R0_H
659 );
660
661 // Class for 64 bit register r1
662 reg_class r1_reg(
663 R1, R1_H
664 );
665
666 // Class for 64 bit register r2
667 reg_class r2_reg(
668 R2, R2_H
669 );
670
671 // Class for 64 bit register r3
672 reg_class r3_reg(
673 R3, R3_H
674 );
675
676 // Class for 64 bit register r4
677 reg_class r4_reg(
678 R4, R4_H
679 );
680
681 // Class for 64 bit register r5
682 reg_class r5_reg(
683 R5, R5_H
684 );
685
686 // Class for 64 bit register r10
687 reg_class r10_reg(
688 R10, R10_H
689 );
690
691 // Class for 64 bit register r11
692 reg_class r11_reg(
693 R11, R11_H
694 );
695
696 // Class for method register
697 reg_class method_reg(
698 R12, R12_H
699 );
700
701 // Class for heapbase register
702 reg_class heapbase_reg(
703 R27, R27_H
704 );
705
706 // Class for thread register
707 reg_class thread_reg(
708 R28, R28_H
709 );
710
711 // Class for frame pointer register
712 reg_class fp_reg(
713 R29, R29_H
714 );
715
716 // Class for link register
717 reg_class lr_reg(
718 R30, R30_H
719 );
720
721 // Class for long sp register
722 reg_class sp_reg(
723 R31, R31_H
724 );
725
726 // Class for all pointer registers
727 reg_class ptr_reg(
728 R0, R0_H,
729 R1, R1_H,
730 R2, R2_H,
731 R3, R3_H,
732 R4, R4_H,
733 R5, R5_H,
734 R6, R6_H,
735 R7, R7_H,
736 R10, R10_H,
737 R11, R11_H,
738 R12, R12_H,
739 R13, R13_H,
740 R14, R14_H,
741 R15, R15_H,
742 R16, R16_H,
743 R17, R17_H,
744 R18, R18_H,
745 R19, R19_H,
746 R20, R20_H,
747 R21, R21_H,
748 R22, R22_H,
749 R23, R23_H,
750 R24, R24_H,
751 R25, R25_H,
752 R26, R26_H,
753 R27, R27_H,
754 R28, R28_H,
755 R29, R29_H,
756 R30, R30_H,
757 R31, R31_H
758 );
759
760 // Class for all non_special pointer registers
761 reg_class no_special_ptr_reg(
762 R0, R0_H,
763 R1, R1_H,
764 R2, R2_H,
765 R3, R3_H,
766 R4, R4_H,
767 R5, R5_H,
768 R6, R6_H,
769 R7, R7_H,
770 R10, R10_H,
771 R11, R11_H,
772 R12, R12_H,
773 R13, R13_H,
774 R14, R14_H,
775 R15, R15_H,
776 R16, R16_H,
777 R17, R17_H,
778 R18, R18_H,
779 R19, R19_H,
780 R20, R20_H,
781 R21, R21_H,
782 R22, R22_H,
783 R23, R23_H,
784 R24, R24_H,
785 R25, R25_H,
786 R26, R26_H,
787 /* R27, R27_H, */ // heapbase
788 /* R28, R28_H, */ // thread
789 /* R29, R29_H, */ // fp
790 /* R30, R30_H, */ // lr
791 /* R31, R31_H */ // sp
792 );
793
794 // Class for all float registers
795 reg_class float_reg(
796 V0,
797 V1,
798 V2,
799 V3,
800 V4,
801 V5,
802 V6,
803 V7,
804 V8,
805 V9,
806 V10,
807 V11,
808 V12,
809 V13,
810 V14,
811 V15,
812 V16,
813 V17,
814 V18,
815 V19,
816 V20,
817 V21,
818 V22,
819 V23,
820 V24,
821 V25,
822 V26,
823 V27,
824 V28,
825 V29,
826 V30,
827 V31
828 );
829
830 // Double precision float registers have virtual `high halves' that
831 // are needed by the allocator.
832 // Class for all double registers
833 reg_class double_reg(
834 V0, V0_H,
835 V1, V1_H,
836 V2, V2_H,
837 V3, V3_H,
838 V4, V4_H,
839 V5, V5_H,
840 V6, V6_H,
841 V7, V7_H,
842 V8, V8_H,
843 V9, V9_H,
844 V10, V10_H,
845 V11, V11_H,
846 V12, V12_H,
847 V13, V13_H,
848 V14, V14_H,
849 V15, V15_H,
850 V16, V16_H,
851 V17, V17_H,
852 V18, V18_H,
853 V19, V19_H,
854 V20, V20_H,
855 V21, V21_H,
856 V22, V22_H,
857 V23, V23_H,
858 V24, V24_H,
859 V25, V25_H,
860 V26, V26_H,
861 V27, V27_H,
862 V28, V28_H,
863 V29, V29_H,
864 V30, V30_H,
865 V31, V31_H
866 );
867
868 // Class for all 64bit vector registers
869 reg_class vectord_reg(
870 V0, V0_H,
871 V1, V1_H,
872 V2, V2_H,
873 V3, V3_H,
874 V4, V4_H,
875 V5, V5_H,
876 V6, V6_H,
877 V7, V7_H,
878 V8, V8_H,
879 V9, V9_H,
880 V10, V10_H,
881 V11, V11_H,
882 V12, V12_H,
883 V13, V13_H,
884 V14, V14_H,
885 V15, V15_H,
886 V16, V16_H,
887 V17, V17_H,
888 V18, V18_H,
889 V19, V19_H,
890 V20, V20_H,
891 V21, V21_H,
892 V22, V22_H,
893 V23, V23_H,
894 V24, V24_H,
895 V25, V25_H,
896 V26, V26_H,
897 V27, V27_H,
898 V28, V28_H,
899 V29, V29_H,
900 V30, V30_H,
901 V31, V31_H
902 );
903
904 // Class for all 128bit vector registers
905 reg_class vectorx_reg(
906 V0, V0_H, V0_J, V0_K,
907 V1, V1_H, V1_J, V1_K,
908 V2, V2_H, V2_J, V2_K,
909 V3, V3_H, V3_J, V3_K,
910 V4, V4_H, V4_J, V4_K,
911 V5, V5_H, V5_J, V5_K,
912 V6, V6_H, V6_J, V6_K,
913 V7, V7_H, V7_J, V7_K,
914 V8, V8_H, V8_J, V8_K,
915 V9, V9_H, V9_J, V9_K,
916 V10, V10_H, V10_J, V10_K,
917 V11, V11_H, V11_J, V11_K,
918 V12, V12_H, V12_J, V12_K,
919 V13, V13_H, V13_J, V13_K,
920 V14, V14_H, V14_J, V14_K,
921 V15, V15_H, V15_J, V15_K,
922 V16, V16_H, V16_J, V16_K,
923 V17, V17_H, V17_J, V17_K,
924 V18, V18_H, V18_J, V18_K,
925 V19, V19_H, V19_J, V19_K,
926 V20, V20_H, V20_J, V20_K,
927 V21, V21_H, V21_J, V21_K,
928 V22, V22_H, V22_J, V22_K,
929 V23, V23_H, V23_J, V23_K,
930 V24, V24_H, V24_J, V24_K,
931 V25, V25_H, V25_J, V25_K,
932 V26, V26_H, V26_J, V26_K,
933 V27, V27_H, V27_J, V27_K,
934 V28, V28_H, V28_J, V28_K,
935 V29, V29_H, V29_J, V29_K,
936 V30, V30_H, V30_J, V30_K,
937 V31, V31_H, V31_J, V31_K
938 );
939
940 // Class for 128 bit register v0
941 reg_class v0_reg(
942 V0, V0_H
943 );
944
945 // Class for 128 bit register v1
946 reg_class v1_reg(
947 V1, V1_H
948 );
949
950 // Class for 128 bit register v2
951 reg_class v2_reg(
952 V2, V2_H
953 );
954
955 // Class for 128 bit register v3
956 reg_class v3_reg(
957 V3, V3_H
958 );
959
960 // Singleton class for condition codes
961 reg_class int_flags(RFLAGS);
962
963 %}
964
965 //----------DEFINITION BLOCK---------------------------------------------------
966 // Define name --> value mappings to inform the ADLC of an integer valued name
967 // Current support includes integer values in the range [0, 0x7FFFFFFF]
968 // Format:
969 // int_def <name> ( <int_value>, <expression>);
970 // Generated Code in ad_<arch>.hpp
971 // #define <name> (<expression>)
972 // // value == <int_value>
973 // Generated code in ad_<arch>.cpp adlc_verification()
974 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
975 //
976
977 // we follow the ppc-aix port in using a simple cost model which ranks
978 // register operations as cheap, memory ops as more expensive and
979 // branches as most expensive. the first two have a low as well as a
980 // normal cost. huge cost appears to be a way of saying don't do
981 // something
982
983 definitions %{
984 // The default cost (of a register move instruction).
985 int_def INSN_COST ( 100, 100);
986 int_def BRANCH_COST ( 200, 2 * INSN_COST);
987 int_def CALL_COST ( 200, 2 * INSN_COST);
988 int_def VOLATILE_REF_COST ( 1000, 10 * INSN_COST);
989 %}
990
991
992 //----------SOURCE BLOCK-------------------------------------------------------
993 // This is a block of C++ code which provides values, functions, and
994 // definitions necessary in the rest of the architecture description
995
996 source_hpp %{
997
998 #include "gc/shared/cardTableModRefBS.hpp"
999 #include "opto/addnode.hpp"
1000
1001 class CallStubImpl {
1002
1003 //--------------------------------------------------------------
1004 //---< Used for optimization in Compile::shorten_branches >---
1005 //--------------------------------------------------------------
1006
1007 public:
1008 // Size of call trampoline stub.
1009 static uint size_call_trampoline() {
1010 return 0; // no call trampolines on this platform
1011 }
1012
1013 // number of relocations needed by a call trampoline stub
1014 static uint reloc_call_trampoline() {
1015 return 0; // no call trampolines on this platform
1016 }
1017 };
1018
1019 class HandlerImpl {
1020
1021 public:
1022
1023 static int emit_exception_handler(CodeBuffer &cbuf);
1024 static int emit_deopt_handler(CodeBuffer& cbuf);
1025
1026 static uint size_exception_handler() {
1027 return MacroAssembler::far_branch_size();
1028 }
1029
1030 static uint size_deopt_handler() {
1031 // count one adr and one far branch instruction
1032 return 4 * NativeInstruction::instruction_size;
1033 }
1034 };
1035
1036 // graph traversal helpers
1037
1038 MemBarNode *parent_membar(const Node *n);
1039 MemBarNode *child_membar(const MemBarNode *n);
1040 bool leading_membar(const MemBarNode *barrier);
1041
1042 bool is_card_mark_membar(const MemBarNode *barrier);
1043 bool is_CAS(int opcode);
1044
1045 MemBarNode *leading_to_trailing(MemBarNode *leading);
1046 MemBarNode *card_mark_to_leading(const MemBarNode *barrier);
1047 MemBarNode *trailing_to_leading(const MemBarNode *trailing);
1048
1049 // predicates controlling emit of ldr<x>/ldar<x> and associated dmb
1050
1051 bool unnecessary_acquire(const Node *barrier);
1052 bool needs_acquiring_load(const Node *load);
1053
1054 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
1055
1056 bool unnecessary_release(const Node *barrier);
1057 bool unnecessary_volatile(const Node *barrier);
1058 bool needs_releasing_store(const Node *store);
1059
1060 // predicate controlling translation of CompareAndSwapX
1061 bool needs_acquiring_load_exclusive(const Node *load);
1062
1063 // predicate controlling translation of StoreCM
1064 bool unnecessary_storestore(const Node *storecm);
1065
1066 // predicate controlling addressing modes
1067 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1068 %}
1069
1070 source %{
1071
1072 // Optimizaton of volatile gets and puts
1073 // -------------------------------------
1074 //
1075 // AArch64 has ldar<x> and stlr<x> instructions which we can safely
1076 // use to implement volatile reads and writes. For a volatile read
1077 // we simply need
1078 //
1079 // ldar<x>
1080 //
1081 // and for a volatile write we need
1082 //
1083 // stlr<x>
1084 //
1085 // Alternatively, we can implement them by pairing a normal
1086 // load/store with a memory barrier. For a volatile read we need
1087 //
1088 // ldr<x>
1089 // dmb ishld
1090 //
1091 // for a volatile write
1092 //
1093 // dmb ish
1094 // str<x>
1095 // dmb ish
1096 //
1097 // We can also use ldaxr and stlxr to implement compare and swap CAS
1098 // sequences. These are normally translated to an instruction
1099 // sequence like the following
1100 //
1101 // dmb ish
1102 // retry:
1103 // ldxr<x> rval raddr
1104 // cmp rval rold
1105 // b.ne done
1106 // stlxr<x> rval, rnew, rold
1107 // cbnz rval retry
1108 // done:
1109 // cset r0, eq
1110 // dmb ishld
1111 //
1112 // Note that the exclusive store is already using an stlxr
1113 // instruction. That is required to ensure visibility to other
1114 // threads of the exclusive write (assuming it succeeds) before that
1115 // of any subsequent writes.
1116 //
1117 // The following instruction sequence is an improvement on the above
1118 //
1119 // retry:
1120 // ldaxr<x> rval raddr
1121 // cmp rval rold
1122 // b.ne done
1123 // stlxr<x> rval, rnew, rold
1124 // cbnz rval retry
1125 // done:
1126 // cset r0, eq
1127 //
1128 // We don't need the leading dmb ish since the stlxr guarantees
1129 // visibility of prior writes in the case that the swap is
1130 // successful. Crucially we don't have to worry about the case where
1131 // the swap is not successful since no valid program should be
1132 // relying on visibility of prior changes by the attempting thread
1133 // in the case where the CAS fails.
1134 //
1135 // Similarly, we don't need the trailing dmb ishld if we substitute
1136 // an ldaxr instruction since that will provide all the guarantees we
1137 // require regarding observation of changes made by other threads
1138 // before any change to the CAS address observed by the load.
1139 //
1140 // In order to generate the desired instruction sequence we need to
1141 // be able to identify specific 'signature' ideal graph node
1142 // sequences which i) occur as a translation of a volatile reads or
1143 // writes or CAS operations and ii) do not occur through any other
1144 // translation or graph transformation. We can then provide
1145 // alternative aldc matching rules which translate these node
1146 // sequences to the desired machine code sequences. Selection of the
1147 // alternative rules can be implemented by predicates which identify
1148 // the relevant node sequences.
1149 //
1150 // The ideal graph generator translates a volatile read to the node
1151 // sequence
1152 //
1153 // LoadX[mo_acquire]
1154 // MemBarAcquire
1155 //
1156 // As a special case when using the compressed oops optimization we
1157 // may also see this variant
1158 //
1159 // LoadN[mo_acquire]
1160 // DecodeN
1161 // MemBarAcquire
1162 //
1163 // A volatile write is translated to the node sequence
1164 //
1165 // MemBarRelease
1166 // StoreX[mo_release] {CardMark}-optional
1167 // MemBarVolatile
1168 //
1169 // n.b. the above node patterns are generated with a strict
1170 // 'signature' configuration of input and output dependencies (see
1171 // the predicates below for exact details). The card mark may be as
1172 // simple as a few extra nodes or, in a few GC configurations, may
1173 // include more complex control flow between the leading and
1174 // trailing memory barriers. However, whatever the card mark
1175 // configuration these signatures are unique to translated volatile
1176 // reads/stores -- they will not appear as a result of any other
1177 // bytecode translation or inlining nor as a consequence of
1178 // optimizing transforms.
1179 //
1180 // We also want to catch inlined unsafe volatile gets and puts and
1181 // be able to implement them using either ldar<x>/stlr<x> or some
1182 // combination of ldr<x>/stlr<x> and dmb instructions.
1183 //
1184 // Inlined unsafe volatiles puts manifest as a minor variant of the
1185 // normal volatile put node sequence containing an extra cpuorder
1186 // membar
1187 //
1188 // MemBarRelease
1189 // MemBarCPUOrder
1190 // StoreX[mo_release] {CardMark}-optional
1191 // MemBarVolatile
1192 //
1193 // n.b. as an aside, the cpuorder membar is not itself subject to
1194 // matching and translation by adlc rules. However, the rule
1195 // predicates need to detect its presence in order to correctly
1196 // select the desired adlc rules.
1197 //
1198 // Inlined unsafe volatile gets manifest as a somewhat different
1199 // node sequence to a normal volatile get
1200 //
1201 // MemBarCPUOrder
1202 // || \\
1203 // MemBarAcquire LoadX[mo_acquire]
1204 // ||
1205 // MemBarCPUOrder
1206 //
1207 // In this case the acquire membar does not directly depend on the
1208 // load. However, we can be sure that the load is generated from an
1209 // inlined unsafe volatile get if we see it dependent on this unique
1210 // sequence of membar nodes. Similarly, given an acquire membar we
1211 // can know that it was added because of an inlined unsafe volatile
1212 // get if it is fed and feeds a cpuorder membar and if its feed
1213 // membar also feeds an acquiring load.
1214 //
1215 // Finally an inlined (Unsafe) CAS operation is translated to the
1216 // following ideal graph
1217 //
1218 // MemBarRelease
1219 // MemBarCPUOrder
1220 // CompareAndSwapX {CardMark}-optional
1221 // MemBarCPUOrder
1222 // MemBarAcquire
1223 //
1224 // So, where we can identify these volatile read and write
1225 // signatures we can choose to plant either of the above two code
1226 // sequences. For a volatile read we can simply plant a normal
1227 // ldr<x> and translate the MemBarAcquire to a dmb. However, we can
1228 // also choose to inhibit translation of the MemBarAcquire and
1229 // inhibit planting of the ldr<x>, instead planting an ldar<x>.
1230 //
1231 // When we recognise a volatile store signature we can choose to
1232 // plant at a dmb ish as a translation for the MemBarRelease, a
1233 // normal str<x> and then a dmb ish for the MemBarVolatile.
1234 // Alternatively, we can inhibit translation of the MemBarRelease
1235 // and MemBarVolatile and instead plant a simple stlr<x>
1236 // instruction.
1237 //
1238 // when we recognise a CAS signature we can choose to plant a dmb
1239 // ish as a translation for the MemBarRelease, the conventional
1240 // macro-instruction sequence for the CompareAndSwap node (which
1241 // uses ldxr<x>) and then a dmb ishld for the MemBarAcquire.
1242 // Alternatively, we can elide generation of the dmb instructions
1243 // and plant the alternative CompareAndSwap macro-instruction
1244 // sequence (which uses ldaxr<x>).
1245 //
1246 // Of course, the above only applies when we see these signature
1247 // configurations. We still want to plant dmb instructions in any
1248 // other cases where we may see a MemBarAcquire, MemBarRelease or
1249 // MemBarVolatile. For example, at the end of a constructor which
1250 // writes final/volatile fields we will see a MemBarRelease
1251 // instruction and this needs a 'dmb ish' lest we risk the
1252 // constructed object being visible without making the
1253 // final/volatile field writes visible.
1254 //
1255 // n.b. the translation rules below which rely on detection of the
1256 // volatile signatures and insert ldar<x> or stlr<x> are failsafe.
1257 // If we see anything other than the signature configurations we
1258 // always just translate the loads and stores to ldr<x> and str<x>
1259 // and translate acquire, release and volatile membars to the
1260 // relevant dmb instructions.
1261 //
1262
1263 // graph traversal helpers used for volatile put/get and CAS
1264 // optimization
1265
1266 // 1) general purpose helpers
1267
1268 // if node n is linked to a parent MemBarNode by an intervening
1269 // Control and Memory ProjNode return the MemBarNode otherwise return
1270 // NULL.
1271 //
1272 // n may only be a Load or a MemBar.
1273
1274 MemBarNode *parent_membar(const Node *n)
1275 {
1276 Node *ctl = NULL;
1277 Node *mem = NULL;
1278 Node *membar = NULL;
1279
1280 if (n->is_Load()) {
1281 ctl = n->lookup(LoadNode::Control);
1282 mem = n->lookup(LoadNode::Memory);
1283 } else if (n->is_MemBar()) {
1284 ctl = n->lookup(TypeFunc::Control);
1285 mem = n->lookup(TypeFunc::Memory);
1286 } else {
1287 return NULL;
1288 }
1289
1290 if (!ctl || !mem || !ctl->is_Proj() || !mem->is_Proj()) {
1291 return NULL;
1292 }
1293
1294 membar = ctl->lookup(0);
1295
1296 if (!membar || !membar->is_MemBar()) {
1297 return NULL;
1298 }
1299
1300 if (mem->lookup(0) != membar) {
1301 return NULL;
1302 }
1303
1304 return membar->as_MemBar();
1305 }
1306
1307 // if n is linked to a child MemBarNode by intervening Control and
1308 // Memory ProjNodes return the MemBarNode otherwise return NULL.
1309
1310 MemBarNode *child_membar(const MemBarNode *n)
1311 {
1312 ProjNode *ctl = n->proj_out(TypeFunc::Control);
1313 ProjNode *mem = n->proj_out(TypeFunc::Memory);
1314
1315 // MemBar needs to have both a Ctl and Mem projection
1316 if (! ctl || ! mem)
1317 return NULL;
1318
1319 MemBarNode *child = NULL;
1320 Node *x;
1321
1322 for (DUIterator_Fast imax, i = ctl->fast_outs(imax); i < imax; i++) {
1323 x = ctl->fast_out(i);
1324 // if we see a membar we keep hold of it. we may also see a new
1325 // arena copy of the original but it will appear later
1326 if (x->is_MemBar()) {
1327 child = x->as_MemBar();
1328 break;
1329 }
1330 }
1331
1332 if (child == NULL) {
1333 return NULL;
1334 }
1335
1336 for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) {
1337 x = mem->fast_out(i);
1338 // if we see a membar we keep hold of it. we may also see a new
1339 // arena copy of the original but it will appear later
1340 if (x == child) {
1341 return child;
1342 }
1343 }
1344 return NULL;
1345 }
1346
1347 // helper predicate use to filter candidates for a leading memory
1348 // barrier
1349 //
1350 // returns true if barrier is a MemBarRelease or a MemBarCPUOrder
1351 // whose Ctl and Mem feeds come from a MemBarRelease otherwise false
1352
1353 bool leading_membar(const MemBarNode *barrier)
1354 {
1355 int opcode = barrier->Opcode();
1356 // if this is a release membar we are ok
1357 if (opcode == Op_MemBarRelease) {
1358 return true;
1359 }
1360 // if its a cpuorder membar . . .
1361 if (opcode != Op_MemBarCPUOrder) {
1362 return false;
1363 }
1364 // then the parent has to be a release membar
1365 MemBarNode *parent = parent_membar(barrier);
1366 if (!parent) {
1367 return false;
1368 }
1369 opcode = parent->Opcode();
1370 return opcode == Op_MemBarRelease;
1371 }
1372
1373 // 2) card mark detection helper
1374
1375 // helper predicate which can be used to detect a volatile membar
1376 // introduced as part of a conditional card mark sequence either by
1377 // G1 or by CMS when UseCondCardMark is true.
1378 //
1379 // membar can be definitively determined to be part of a card mark
1380 // sequence if and only if all the following hold
1381 //
1382 // i) it is a MemBarVolatile
1383 //
1384 // ii) either UseG1GC or (UseConcMarkSweepGC && UseCondCardMark) is
1385 // true
1386 //
1387 // iii) the node's Mem projection feeds a StoreCM node.
1388
1389 bool is_card_mark_membar(const MemBarNode *barrier)
1390 {
1391 if (!UseG1GC && !(UseConcMarkSweepGC && UseCondCardMark)) {
1392 return false;
1393 }
1394
1395 if (barrier->Opcode() != Op_MemBarVolatile) {
1396 return false;
1397 }
1398
1399 ProjNode *mem = barrier->proj_out(TypeFunc::Memory);
1400
1401 for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax ; i++) {
1402 Node *y = mem->fast_out(i);
1403 if (y->Opcode() == Op_StoreCM) {
1404 return true;
1405 }
1406 }
1407
1408 return false;
1409 }
1410
1411
1412 // 3) helper predicates to traverse volatile put or CAS graphs which
1413 // may contain GC barrier subgraphs
1414
1415 // Preamble
1416 // --------
1417 //
1418 // for volatile writes we can omit generating barriers and employ a
1419 // releasing store when we see a node sequence sequence with a
1420 // leading MemBarRelease and a trailing MemBarVolatile as follows
1421 //
1422 // MemBarRelease
1423 // { || } -- optional
1424 // {MemBarCPUOrder}
1425 // || \\
1426 // || StoreX[mo_release]
1427 // | \ Bot / ???
1428 // | MergeMem
1429 // | /
1430 // MemBarVolatile
1431 //
1432 // where
1433 // || and \\ represent Ctl and Mem feeds via Proj nodes
1434 // | \ and / indicate further routing of the Ctl and Mem feeds
1435 //
1436 // Note that the memory feed from the CPUOrder membar to the
1437 // MergeMem node is an AliasIdxBot slice while the feed from the
1438 // StoreX is for a slice determined by the type of value being
1439 // written.
1440 //
1441 // the diagram above shows the graph we see for non-object stores.
1442 // for a volatile Object store (StoreN/P) we may see other nodes
1443 // below the leading membar because of the need for a GC pre- or
1444 // post-write barrier.
1445 //
1446 // with most GC configurations we with see this simple variant which
1447 // includes a post-write barrier card mark.
1448 //
1449 // MemBarRelease______________________________
1450 // || \\ Ctl \ \\
1451 // || StoreN/P[mo_release] CastP2X StoreB/CM
1452 // | \ Bot / oop . . . /
1453 // | MergeMem
1454 // | /
1455 // || /
1456 // MemBarVolatile
1457 //
1458 // i.e. the leading membar feeds Ctl to a CastP2X (which converts
1459 // the object address to an int used to compute the card offset) and
1460 // Ctl+Mem to a StoreB node (which does the actual card mark).
1461 //
1462 // n.b. a StoreCM node is only ever used when CMS (with or without
1463 // CondCardMark) or G1 is configured. This abstract instruction
1464 // differs from a normal card mark write (StoreB) because it implies
1465 // a requirement to order visibility of the card mark (StoreCM)
1466 // after that of the object put (StoreP/N) using a StoreStore memory
1467 // barrier. Note that this is /not/ a requirement to order the
1468 // instructions in the generated code (that is already guaranteed by
1469 // the order of memory dependencies). Rather it is a requirement to
1470 // ensure visibility order which only applies on architectures like
1471 // AArch64 which do not implement TSO. This ordering is required for
1472 // both non-volatile and volatile puts.
1473 //
1474 // That implies that we need to translate a StoreCM using the
1475 // sequence
1476 //
1477 // dmb ishst
1478 // stlrb
1479 //
1480 // This dmb cannot be omitted even when the associated StoreX or
1481 // CompareAndSwapX is implemented using stlr. However, as described
1482 // below there are circumstances where a specific GC configuration
1483 // requires a stronger barrier in which case it can be omitted.
1484 //
1485 // With the Serial or Parallel GC using +CondCardMark the card mark
1486 // is performed conditionally on it currently being unmarked in
1487 // which case the volatile put graph looks slightly different
1488 //
1489 // MemBarRelease____________________________________________
1490 // || \\ Ctl \ Ctl \ \\ Mem \
1491 // || StoreN/P[mo_release] CastP2X If LoadB |
1492 // | \ Bot / oop \ |
1493 // | MergeMem . . . StoreB
1494 // | / /
1495 // || /
1496 // MemBarVolatile
1497 //
1498 // It is worth noting at this stage that all the above
1499 // configurations can be uniquely identified by checking that the
1500 // memory flow includes the following subgraph:
1501 //
1502 // MemBarRelease
1503 // {MemBarCPUOrder}
1504 // | \ . . .
1505 // | StoreX[mo_release] . . .
1506 // Bot | / oop
1507 // MergeMem
1508 // |
1509 // MemBarVolatile
1510 //
1511 // This is referred to as a *normal* volatile store subgraph. It can
1512 // easily be detected starting from any candidate MemBarRelease,
1513 // StoreX[mo_release] or MemBarVolatile node.
1514 //
1515 // A small variation on this normal case occurs for an unsafe CAS
1516 // operation. The basic memory flow subgraph for a non-object CAS is
1517 // as follows
1518 //
1519 // MemBarRelease
1520 // ||
1521 // MemBarCPUOrder
1522 // | \\ . . .
1523 // | CompareAndSwapX
1524 // | |
1525 // Bot | SCMemProj
1526 // \ / Bot
1527 // MergeMem
1528 // /
1529 // MemBarCPUOrder
1530 // ||
1531 // MemBarAcquire
1532 //
1533 // The same basic variations on this arrangement (mutatis mutandis)
1534 // occur when a card mark is introduced. i.e. the CPUOrder MemBar
1535 // feeds the extra CastP2X, LoadB etc nodes but the above memory
1536 // flow subgraph is still present.
1537 //
1538 // This is referred to as a *normal* CAS subgraph. It can easily be
1539 // detected starting from any candidate MemBarRelease,
1540 // StoreX[mo_release] or MemBarAcquire node.
1541 //
1542 // The code below uses two helper predicates, leading_to_trailing
1543 // and trailing_to_leading to identify these normal graphs, one
1544 // validating the layout starting from the top membar and searching
1545 // down and the other validating the layout starting from the lower
1546 // membar and searching up.
1547 //
1548 // There are two special case GC configurations when the simple
1549 // normal graphs above may not be generated: when using G1 (which
1550 // always employs a conditional card mark); and when using CMS with
1551 // conditional card marking (+CondCardMark) configured. These GCs
1552 // are both concurrent rather than stop-the world GCs. So they
1553 // introduce extra Ctl+Mem flow into the graph between the leading
1554 // and trailing membar nodes, in particular enforcing stronger
1555 // memory serialisation beween the object put and the corresponding
1556 // conditional card mark. CMS employs a post-write GC barrier while
1557 // G1 employs both a pre- and post-write GC barrier.
1558 //
1559 // The post-write barrier subgraph for these configurations includes
1560 // a MemBarVolatile node -- referred to as a card mark membar --
1561 // which is needed to order the card write (StoreCM) operation in
1562 // the barrier, the preceding StoreX (or CompareAndSwapX) and Store
1563 // operations performed by GC threads i.e. a card mark membar
1564 // constitutes a StoreLoad barrier hence must be translated to a dmb
1565 // ish (whether or not it sits inside a volatile store sequence).
1566 //
1567 // Of course, the use of the dmb ish for the card mark membar also
1568 // implies theat the StoreCM which follows can omit the dmb ishst
1569 // instruction. The necessary visibility ordering will already be
1570 // guaranteed by the dmb ish. In sum, the dmb ishst instruction only
1571 // needs to be generated for as part of the StoreCM sequence with GC
1572 // configuration +CMS -CondCardMark.
1573 //
1574 // Of course all these extra barrier nodes may well be absent --
1575 // they are only inserted for object puts. Their potential presence
1576 // significantly complicates the task of identifying whether a
1577 // MemBarRelease, StoreX[mo_release], MemBarVolatile or
1578 // MemBarAcquire forms part of a volatile put or CAS when using
1579 // these GC configurations (see below) and also complicates the
1580 // decision as to how to translate a MemBarVolatile and StoreCM.
1581 //
1582 // So, thjis means that a card mark MemBarVolatile occurring in the
1583 // post-barrier graph it needs to be distinguished from a normal
1584 // trailing MemBarVolatile. Resolving this is straightforward: a
1585 // card mark MemBarVolatile always projects a Mem feed to a StoreCM
1586 // node and that is a unique marker
1587 //
1588 // MemBarVolatile (card mark)
1589 // C | \ . . .
1590 // | StoreCM . . .
1591 // . . .
1592 //
1593 // Returning to the task of translating the object put and the
1594 // leading/trailing membar nodes: what do the node graphs look like
1595 // for these 2 special cases? and how can we determine the status of
1596 // a MemBarRelease, StoreX[mo_release] or MemBarVolatile in both
1597 // normal and non-normal cases?
1598 //
1599 // A CMS GC post-barrier wraps its card write (StoreCM) inside an If
1600 // which selects conditonal execution based on the value loaded
1601 // (LoadB) from the card. Ctl and Mem are fed to the If via an
1602 // intervening StoreLoad barrier (MemBarVolatile).
1603 //
1604 // So, with CMS we may see a node graph for a volatile object store
1605 // which looks like this
1606 //
1607 // MemBarRelease
1608 // MemBarCPUOrder_(leading)____________________
1609 // C | | M \ \\ M | C \
1610 // | | \ StoreN/P[mo_release] | CastP2X
1611 // | | Bot \ / oop \ |
1612 // | | MergeMem \ /
1613 // | | / | /
1614 // MemBarVolatile (card mark) | /
1615 // C | || M | | /
1616 // | LoadB | Bot oop | / Bot
1617 // | | | / /
1618 // | Cmp |\ / /
1619 // | / | \ / /
1620 // If | \ / /
1621 // | \ | \ / /
1622 // IfFalse IfTrue | \ / /
1623 // \ / \ | | / /
1624 // \ / StoreCM | / /
1625 // \ / \ / / /
1626 // Region Phi / /
1627 // | \ Raw | / /
1628 // | . . . | / /
1629 // | MergeMem
1630 // | |
1631 // MemBarVolatile (trailing)
1632 //
1633 // Notice that there are two MergeMem nodes below the leading
1634 // membar. The first MergeMem merges the AliasIdxBot Mem slice from
1635 // the leading membar and the oopptr Mem slice from the Store into
1636 // the card mark membar. The trailing MergeMem merges the
1637 // AliasIdxBot Mem slice from the leading membar, the AliasIdxRaw
1638 // slice from the StoreCM and an oop slice from the StoreN/P node
1639 // into the trailing membar (n.b. the raw slice proceeds via a Phi
1640 // associated with the If region).
1641 //
1642 // So, in the case of CMS + CondCardMark the volatile object store
1643 // graph still includes a normal volatile store subgraph from the
1644 // leading membar to the trailing membar. However, it also contains
1645 // the same shape memory flow to the card mark membar. The two flows
1646 // can be distinguished by testing whether or not the downstream
1647 // membar is a card mark membar.
1648 //
1649 // The graph for a CAS also varies with CMS + CondCardMark, in
1650 // particular employing a control feed from the CompareAndSwapX node
1651 // through a CmpI and If to the card mark membar and StoreCM which
1652 // updates the associated card. This avoids executing the card mark
1653 // if the CAS fails. However, it can be seen from the diagram below
1654 // that the presence of the barrier does not alter the normal CAS
1655 // memory subgraph where the leading membar feeds a CompareAndSwapX,
1656 // an SCMemProj, a MergeMem then a final trailing MemBarCPUOrder and
1657 // MemBarAcquire pair.
1658 //
1659 // MemBarRelease
1660 // MemBarCPUOrder__(leading)_______________________
1661 // C / M | \\ C \
1662 // . . . | Bot CompareAndSwapN/P CastP2X
1663 // | C / M |
1664 // | CmpI |
1665 // | / |
1666 // | . . . |
1667 // | IfTrue |
1668 // | / |
1669 // MemBarVolatile (card mark) |
1670 // C | || M | |
1671 // | LoadB | Bot ______/|
1672 // | | | / |
1673 // | Cmp | / SCMemProj
1674 // | / | / |
1675 // If | / /
1676 // | \ | / / Bot
1677 // IfFalse IfTrue | / /
1678 // | / \ / / prec /
1679 // . . . | / StoreCM /
1680 // \ | / | raw /
1681 // Region . . . /
1682 // | \ /
1683 // | . . . \ / Bot
1684 // | MergeMem
1685 // | /
1686 // MemBarCPUOrder
1687 // MemBarAcquire (trailing)
1688 //
1689 // This has a slightly different memory subgraph to the one seen
1690 // previously but the core of it has a similar memory flow to the
1691 // CAS normal subgraph:
1692 //
1693 // MemBarRelease
1694 // MemBarCPUOrder____
1695 // | \ . . .
1696 // | CompareAndSwapX . . .
1697 // | C / M |
1698 // | CmpI |
1699 // | / |
1700 // | . . /
1701 // Bot | IfTrue /
1702 // | / /
1703 // MemBarVolatile /
1704 // | ... /
1705 // StoreCM ... /
1706 // | /
1707 // . . . SCMemProj
1708 // Raw \ / Bot
1709 // MergeMem
1710 // |
1711 // MemBarCPUOrder
1712 // MemBarAcquire
1713 //
1714 // The G1 graph for a volatile object put is a lot more complicated.
1715 // Nodes inserted on behalf of G1 may comprise: a pre-write graph
1716 // which adds the old value to the SATB queue; the releasing store
1717 // itself; and, finally, a post-write graph which performs a card
1718 // mark.
1719 //
1720 // The pre-write graph may be omitted, but only when the put is
1721 // writing to a newly allocated (young gen) object and then only if
1722 // there is a direct memory chain to the Initialize node for the
1723 // object allocation. This will not happen for a volatile put since
1724 // any memory chain passes through the leading membar.
1725 //
1726 // The pre-write graph includes a series of 3 If tests. The outermost
1727 // If tests whether SATB is enabled (no else case). The next If tests
1728 // whether the old value is non-NULL (no else case). The third tests
1729 // whether the SATB queue index is > 0, if so updating the queue. The
1730 // else case for this third If calls out to the runtime to allocate a
1731 // new queue buffer.
1732 //
1733 // So with G1 the pre-write and releasing store subgraph looks like
1734 // this (the nested Ifs are omitted).
1735 //
1736 // MemBarRelease (leading)____________
1737 // C | || M \ M \ M \ M \ . . .
1738 // | LoadB \ LoadL LoadN \
1739 // | / \ \
1740 // If |\ \
1741 // | \ | \ \
1742 // IfFalse IfTrue | \ \
1743 // | | | \ |
1744 // | If | /\ |
1745 // | | \ |
1746 // | \ |
1747 // | . . . \ |
1748 // | / | / | |
1749 // Region Phi[M] | |
1750 // | \ | | |
1751 // | \_____ | ___ | |
1752 // C | C \ | C \ M | |
1753 // | CastP2X | StoreN/P[mo_release] |
1754 // | | | |
1755 // C | M | M | M |
1756 // \ | Raw | oop / Bot
1757 // . . .
1758 // (post write subtree elided)
1759 // . . .
1760 // C \ M /
1761 // MemBarVolatile (trailing)
1762 //
1763 // Note that the three memory feeds into the post-write tree are an
1764 // AliasRawIdx slice associated with the writes in the pre-write
1765 // tree, an oop type slice from the StoreX specific to the type of
1766 // the volatile field and the AliasBotIdx slice emanating from the
1767 // leading membar.
1768 //
1769 // n.b. the LoadB in this subgraph is not the card read -- it's a
1770 // read of the SATB queue active flag.
1771 //
1772 // The CAS graph is once again a variant of the above with a
1773 // CompareAndSwapX node and SCMemProj in place of the StoreX. The
1774 // value from the CompareAndSwapX node is fed into the post-write
1775 // graph aling with the AliasIdxRaw feed from the pre-barrier and
1776 // the AliasIdxBot feeds from the leading membar and the ScMemProj.
1777 //
1778 // MemBarRelease (leading)____________
1779 // C | || M \ M \ M \ M \ . . .
1780 // | LoadB \ LoadL LoadN \
1781 // | / \ \
1782 // If |\ \
1783 // | \ | \ \
1784 // IfFalse IfTrue | \ \
1785 // | | | \ \
1786 // | If | \ |
1787 // | | \ |
1788 // | \ |
1789 // | . . . \ |
1790 // | / | / \ |
1791 // Region Phi[M] \ |
1792 // | \ | \ |
1793 // | \_____ | | |
1794 // C | C \ | | |
1795 // | CastP2X | CompareAndSwapX |
1796 // | | res | | |
1797 // C | M | | SCMemProj M |
1798 // \ | Raw | | Bot / Bot
1799 // . . .
1800 // (post write subtree elided)
1801 // . . .
1802 // C \ M /
1803 // MemBarVolatile (trailing)
1804 //
1805 // The G1 post-write subtree is also optional, this time when the
1806 // new value being written is either null or can be identified as a
1807 // newly allocated (young gen) object with no intervening control
1808 // flow. The latter cannot happen but the former may, in which case
1809 // the card mark membar is omitted and the memory feeds from the
1810 // leading membar and the SToreN/P are merged direct into the
1811 // trailing membar as per the normal subgraph. So, the only special
1812 // case which arises is when the post-write subgraph is generated.
1813 //
1814 // The kernel of the post-write G1 subgraph is the card mark itself
1815 // which includes a card mark memory barrier (MemBarVolatile), a
1816 // card test (LoadB), and a conditional update (If feeding a
1817 // StoreCM). These nodes are surrounded by a series of nested Ifs
1818 // which try to avoid doing the card mark. The top level If skips if
1819 // the object reference does not cross regions (i.e. it tests if
1820 // (adr ^ val) >> log2(regsize) != 0) -- intra-region references
1821 // need not be recorded. The next If, which skips on a NULL value,
1822 // may be absent (it is not generated if the type of value is >=
1823 // OopPtr::NotNull). The 3rd If skips writes to young regions (by
1824 // checking if card_val != young). n.b. although this test requires
1825 // a pre-read of the card it can safely be done before the StoreLoad
1826 // barrier. However that does not bypass the need to reread the card
1827 // after the barrier.
1828 //
1829 // (pre-write subtree elided)
1830 // . . . . . . . . . . . .
1831 // C | M | M | M |
1832 // Region Phi[M] StoreN |
1833 // | Raw | oop | Bot |
1834 // / \_______ |\ |\ |\
1835 // C / C \ . . . | \ | \ | \
1836 // If CastP2X . . . | \ | \ | \
1837 // / \ | \ | \ | \
1838 // / \ | \ | \ | \
1839 // IfFalse IfTrue | | | \
1840 // | | \ | / |
1841 // | If \ | \ / \ |
1842 // | / \ \ | / \ |
1843 // | / \ \ | / \ | |
1844 // | IfFalse IfTrue MergeMem \ | |
1845 // | . . . / \ | \ | |
1846 // | / \ | | | |
1847 // | IfFalse IfTrue | | | |
1848 // | . . . | | | | |
1849 // | If / | | |
1850 // | / \ / | | |
1851 // | / \ / | | |
1852 // | IfFalse IfTrue / | | |
1853 // | . . . | / | | |
1854 // | \ / | | |
1855 // | \ / | | |
1856 // | MemBarVolatile__(card mark ) | | |
1857 // | || C | \ | | |
1858 // | LoadB If | / | |
1859 // | / \ Raw | / / /
1860 // | . . . | / / /
1861 // | \ | / / /
1862 // | StoreCM / / /
1863 // | | / / /
1864 // | . . . / /
1865 // | / /
1866 // | . . . / /
1867 // | | | / / /
1868 // | | Phi[M] / / /
1869 // | | | / / /
1870 // | | | / / /
1871 // | Region . . . Phi[M] / /
1872 // | | | / /
1873 // \ | | / /
1874 // \ | . . . | / /
1875 // \ | | / /
1876 // Region Phi[M] / /
1877 // | \ / /
1878 // \ MergeMem
1879 // \ /
1880 // MemBarVolatile
1881 //
1882 // As with CMS + CondCardMark the first MergeMem merges the
1883 // AliasIdxBot Mem slice from the leading membar and the oopptr Mem
1884 // slice from the Store into the card mark membar. However, in this
1885 // case it may also merge an AliasRawIdx mem slice from the pre
1886 // barrier write.
1887 //
1888 // The trailing MergeMem merges an AliasIdxBot Mem slice from the
1889 // leading membar with an oop slice from the StoreN and an
1890 // AliasRawIdx slice from the post barrier writes. In this case the
1891 // AliasIdxRaw Mem slice is merged through a series of Phi nodes
1892 // which combine feeds from the If regions in the post barrier
1893 // subgraph.
1894 //
1895 // So, for G1 the same characteristic subgraph arises as for CMS +
1896 // CondCardMark. There is a normal subgraph feeding the card mark
1897 // membar and a normal subgraph feeding the trailing membar.
1898 //
1899 // The CAS graph when using G1GC also includes an optional
1900 // post-write subgraph. It is very similar to the above graph except
1901 // for a few details.
1902 //
1903 // - The control flow is gated by an additonal If which tests the
1904 // result from the CompareAndSwapX node
1905 //
1906 // - The MergeMem which feeds the card mark membar only merges the
1907 // AliasIdxBot slice from the leading membar and the AliasIdxRaw
1908 // slice from the pre-barrier. It does not merge the SCMemProj
1909 // AliasIdxBot slice. So, this subgraph does not look like the
1910 // normal CAS subgraph.
1911 //
1912 // - The MergeMem which feeds the trailing membar merges the
1913 // AliasIdxBot slice from the leading membar, the AliasIdxRaw slice
1914 // from the post-barrier and the SCMemProj AliasIdxBot slice i.e. it
1915 // has two AliasIdxBot input slices. However, this subgraph does
1916 // still look like the normal CAS subgraph.
1917 //
1918 // So, the upshot is:
1919 //
1920 // In all cases a volatile put graph will include a *normal*
1921 // volatile store subgraph betwen the leading membar and the
1922 // trailing membar. It may also include a normal volatile store
1923 // subgraph betwen the leading membar and the card mark membar.
1924 //
1925 // In all cases a CAS graph will contain a unique normal CAS graph
1926 // feeding the trailing membar.
1927 //
1928 // In all cases where there is a card mark membar (either as part of
1929 // a volatile object put or CAS) it will be fed by a MergeMem whose
1930 // AliasIdxBot slice feed will be a leading membar.
1931 //
1932 // The predicates controlling generation of instructions for store
1933 // and barrier nodes employ a few simple helper functions (described
1934 // below) which identify the presence or absence of all these
1935 // subgraph configurations and provide a means of traversing from
1936 // one node in the subgraph to another.
1937
1938 // is_CAS(int opcode)
1939 //
1940 // return true if opcode is one of the possible CompareAndSwapX
1941 // values otherwise false.
1942
1943 bool is_CAS(int opcode)
1944 {
1945 switch(opcode) {
1946 // We handle these
1947 case Op_CompareAndSwapI:
1948 case Op_CompareAndSwapL:
1949 case Op_CompareAndSwapP:
1950 case Op_CompareAndSwapN:
1951 // case Op_CompareAndSwapB:
1952 // case Op_CompareAndSwapS:
1953 return true;
1954 // These are TBD
1955 case Op_WeakCompareAndSwapB:
1956 case Op_WeakCompareAndSwapS:
1957 case Op_WeakCompareAndSwapI:
1958 case Op_WeakCompareAndSwapL:
1959 case Op_WeakCompareAndSwapP:
1960 case Op_WeakCompareAndSwapN:
1961 case Op_CompareAndExchangeB:
1962 case Op_CompareAndExchangeS:
1963 case Op_CompareAndExchangeI:
1964 case Op_CompareAndExchangeL:
1965 case Op_CompareAndExchangeP:
1966 case Op_CompareAndExchangeN:
1967 return false;
1968 default:
1969 return false;
1970 }
1971 }
1972
1973
1974 // leading_to_trailing
1975 //
1976 //graph traversal helper which detects the normal case Mem feed from
1977 // a release membar (or, optionally, its cpuorder child) to a
1978 // dependent volatile membar i.e. it ensures that one or other of
1979 // the following Mem flow subgraph is present.
1980 //
1981 // MemBarRelease {leading}
1982 // {MemBarCPUOrder} {optional}
1983 // Bot | \ . . .
1984 // | StoreN/P[mo_release] . . .
1985 // | /
1986 // MergeMem
1987 // |
1988 // MemBarVolatile {not card mark}
1989 //
1990 // MemBarRelease {leading}
1991 // {MemBarCPUOrder} {optional}
1992 // | \ . . .
1993 // | CompareAndSwapX . . .
1994 // |
1995 // . . . SCMemProj
1996 // \ |
1997 // | MergeMem
1998 // | /
1999 // MemBarCPUOrder
2000 // MemBarAcquire {trailing}
2001 //
2002 // the predicate needs to be capable of distinguishing the following
2003 // volatile put graph which may arises when a GC post barrier
2004 // inserts a card mark membar
2005 //
2006 // MemBarRelease {leading}
2007 // {MemBarCPUOrder}__
2008 // Bot | \ \
2009 // | StoreN/P \
2010 // | / \ |
2011 // MergeMem \ |
2012 // | \ |
2013 // MemBarVolatile \ |
2014 // {card mark} \ |
2015 // MergeMem
2016 // |
2017 // {not card mark} MemBarVolatile
2018 //
2019 // if the correct configuration is present returns the trailing
2020 // membar otherwise NULL.
2021 //
2022 // the input membar is expected to be either a cpuorder membar or a
2023 // release membar. in the latter case it should not have a cpu membar
2024 // child.
2025 //
2026 // the returned value may be a card mark or trailing membar
2027 //
2028
2029 MemBarNode *leading_to_trailing(MemBarNode *leading)
2030 {
2031 assert((leading->Opcode() == Op_MemBarRelease ||
2032 leading->Opcode() == Op_MemBarCPUOrder),
2033 "expecting a volatile or cpuroder membar!");
2034
2035 // check the mem flow
2036 ProjNode *mem = leading->proj_out(TypeFunc::Memory);
2037
2038 if (!mem) {
2039 return NULL;
2040 }
2041
2042 Node *x = NULL;
2043 StoreNode * st = NULL;
2044 LoadStoreNode *cas = NULL;
2045 MergeMemNode *mm = NULL;
2046 MergeMemNode *mm2 = NULL;
2047
2048 for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) {
2049 x = mem->fast_out(i);
2050 if (x->is_MergeMem()) {
2051 if (mm != NULL) {
2052 if (mm2 != NULL) {
2053 // should not see more than 2 merge mems
2054 return NULL;
2055 } else {
2056 mm2 = x->as_MergeMem();
2057 }
2058 } else {
2059 mm = x->as_MergeMem();
2060 }
2061 } else if (x->is_Store() && x->as_Store()->is_release() && x->Opcode() != Op_StoreCM) {
2062 // two releasing stores/CAS nodes is one too many
2063 if (st != NULL || cas != NULL) {
2064 return NULL;
2065 }
2066 st = x->as_Store();
2067 } else if (is_CAS(x->Opcode())) {
2068 if (st != NULL || cas != NULL) {
2069 return NULL;
2070 }
2071 cas = x->as_LoadStore();
2072 }
2073 }
2074
2075 // must have a store or a cas
2076 if (!st && !cas) {
2077 return NULL;
2078 }
2079
2080 // must have at least one merge if we also have st
2081 if (st && !mm) {
2082 return NULL;
2083 }
2084
2085 if (cas) {
2086 Node *y = NULL;
2087 // look for an SCMemProj
2088 for (DUIterator_Fast imax, i = cas->fast_outs(imax); i < imax; i++) {
2089 x = cas->fast_out(i);
2090 if (x->is_Proj()) {
2091 y = x;
2092 break;
2093 }
2094 }
2095 if (y == NULL) {
2096 return NULL;
2097 }
2098 // the proj must feed a MergeMem
2099 for (DUIterator_Fast imax, i = y->fast_outs(imax); i < imax; i++) {
2100 x = y->fast_out(i);
2101 if (x->is_MergeMem()) {
2102 mm = x->as_MergeMem();
2103 break;
2104 }
2105 }
2106 if (mm == NULL) {
2107 return NULL;
2108 }
2109 MemBarNode *mbar = NULL;
2110 // ensure the merge feeds a trailing membar cpuorder + acquire pair
2111 for (DUIterator_Fast imax, i = mm->fast_outs(imax); i < imax; i++) {
2112 x = mm->fast_out(i);
2113 if (x->is_MemBar()) {
2114 int opcode = x->Opcode();
2115 if (opcode == Op_MemBarCPUOrder) {
2116 MemBarNode *z = x->as_MemBar();
2117 z = child_membar(z);
2118 if (z != NULL && z->Opcode() == Op_MemBarAcquire) {
2119 mbar = z;
2120 }
2121 }
2122 break;
2123 }
2124 }
2125 return mbar;
2126 } else {
2127 Node *y = NULL;
2128 // ensure the store feeds the first mergemem;
2129 for (DUIterator_Fast imax, i = st->fast_outs(imax); i < imax; i++) {
2130 if (st->fast_out(i) == mm) {
2131 y = st;
2132 break;
2133 }
2134 }
2135 if (y == NULL) {
2136 return NULL;
2137 }
2138 if (mm2 != NULL) {
2139 // ensure the store feeds the second mergemem;
2140 y = NULL;
2141 for (DUIterator_Fast imax, i = st->fast_outs(imax); i < imax; i++) {
2142 if (st->fast_out(i) == mm2) {
2143 y = st;
2144 }
2145 }
2146 if (y == NULL) {
2147 return NULL;
2148 }
2149 }
2150
2151 MemBarNode *mbar = NULL;
2152 // ensure the first mergemem feeds a volatile membar
2153 for (DUIterator_Fast imax, i = mm->fast_outs(imax); i < imax; i++) {
2154 x = mm->fast_out(i);
2155 if (x->is_MemBar()) {
2156 int opcode = x->Opcode();
2157 if (opcode == Op_MemBarVolatile) {
2158 mbar = x->as_MemBar();
2159 }
2160 break;
2161 }
2162 }
2163 if (mm2 == NULL) {
2164 // this is our only option for a trailing membar
2165 return mbar;
2166 }
2167 // ensure the second mergemem feeds a volatile membar
2168 MemBarNode *mbar2 = NULL;
2169 for (DUIterator_Fast imax, i = mm2->fast_outs(imax); i < imax; i++) {
2170 x = mm2->fast_out(i);
2171 if (x->is_MemBar()) {
2172 int opcode = x->Opcode();
2173 if (opcode == Op_MemBarVolatile) {
2174 mbar2 = x->as_MemBar();
2175 }
2176 break;
2177 }
2178 }
2179 // if we have two merge mems we must have two volatile membars
2180 if (mbar == NULL || mbar2 == NULL) {
2181 return NULL;
2182 }
2183 // return the trailing membar
2184 if (is_card_mark_membar(mbar2)) {
2185 return mbar;
2186 } else {
2187 if (is_card_mark_membar(mbar)) {
2188 return mbar2;
2189 } else {
2190 return NULL;
2191 }
2192 }
2193 }
2194 }
2195
2196 // trailing_to_leading
2197 //
2198 // graph traversal helper which detects the normal case Mem feed
2199 // from a trailing membar to a preceding release membar (optionally
2200 // its cpuorder child) i.e. it ensures that one or other of the
2201 // following Mem flow subgraphs is present.
2202 //
2203 // MemBarRelease {leading}
2204 // MemBarCPUOrder {optional}
2205 // | Bot | \ . . .
2206 // | | StoreN/P[mo_release] . . .
2207 // | | /
2208 // | MergeMem
2209 // | |
2210 // MemBarVolatile {not card mark}
2211 //
2212 // MemBarRelease {leading}
2213 // MemBarCPUOrder {optional}
2214 // | \ . . .
2215 // | CompareAndSwapX . . .
2216 // |
2217 // . . . SCMemProj
2218 // \ |
2219 // | MergeMem
2220 // | |
2221 // MemBarCPUOrder
2222 // MemBarAcquire {trailing}
2223 //
2224 // this predicate checks for the same flow as the previous predicate
2225 // but starting from the bottom rather than the top.
2226 //
2227 // if the configuration is present returns the cpuorder member for
2228 // preference or when absent the release membar otherwise NULL.
2229 //
2230 // n.b. the input membar is expected to be a MemBarVolatile or
2231 // MemBarAcquire. if it is a MemBarVolatile it must *not* be a card
2232 // mark membar.
2233
2234 MemBarNode *trailing_to_leading(const MemBarNode *barrier)
2235 {
2236 // input must be a volatile membar
2237 assert((barrier->Opcode() == Op_MemBarVolatile ||
2238 barrier->Opcode() == Op_MemBarAcquire),
2239 "expecting a volatile or an acquire membar");
2240
2241 assert((barrier->Opcode() != Op_MemBarVolatile) ||
2242 !is_card_mark_membar(barrier),
2243 "not expecting a card mark membar");
2244 Node *x;
2245 bool is_cas = barrier->Opcode() == Op_MemBarAcquire;
2246
2247 // if we have an acquire membar then it must be fed via a CPUOrder
2248 // membar
2249
2250 if (is_cas) {
2251 // skip to parent barrier which must be a cpuorder
2252 x = parent_membar(barrier);
2253 if (x->Opcode() != Op_MemBarCPUOrder)
2254 return NULL;
2255 } else {
2256 // start from the supplied barrier
2257 x = (Node *)barrier;
2258 }
2259
2260 // the Mem feed to the membar should be a merge
2261 x = x ->in(TypeFunc::Memory);
2262 if (!x->is_MergeMem())
2263 return NULL;
2264
2265 MergeMemNode *mm = x->as_MergeMem();
2266
2267 if (is_cas) {
2268 // the merge should be fed from the CAS via an SCMemProj node
2269 x = NULL;
2270 for (uint idx = 1; idx < mm->req(); idx++) {
2271 if (mm->in(idx)->Opcode() == Op_SCMemProj) {
2272 x = mm->in(idx);
2273 break;
2274 }
2275 }
2276 if (x == NULL) {
2277 return NULL;
2278 }
2279 // check for a CAS feeding this proj
2280 x = x->in(0);
2281 int opcode = x->Opcode();
2282 if (!is_CAS(opcode)) {
2283 return NULL;
2284 }
2285 // the CAS should get its mem feed from the leading membar
2286 x = x->in(MemNode::Memory);
2287 } else {
2288 // the merge should get its Bottom mem feed from the leading membar
2289 x = mm->in(Compile::AliasIdxBot);
2290 }
2291
2292 // ensure this is a non control projection
2293 if (!x->is_Proj() || x->is_CFG()) {
2294 return NULL;
2295 }
2296 // if it is fed by a membar that's the one we want
2297 x = x->in(0);
2298
2299 if (!x->is_MemBar()) {
2300 return NULL;
2301 }
2302
2303 MemBarNode *leading = x->as_MemBar();
2304 // reject invalid candidates
2305 if (!leading_membar(leading)) {
2306 return NULL;
2307 }
2308
2309 // ok, we have a leading membar, now for the sanity clauses
2310
2311 // the leading membar must feed Mem to a releasing store or CAS
2312 ProjNode *mem = leading->proj_out(TypeFunc::Memory);
2313 StoreNode *st = NULL;
2314 LoadStoreNode *cas = NULL;
2315 for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) {
2316 x = mem->fast_out(i);
2317 if (x->is_Store() && x->as_Store()->is_release() && x->Opcode() != Op_StoreCM) {
2318 // two stores or CASes is one too many
2319 if (st != NULL || cas != NULL) {
2320 return NULL;
2321 }
2322 st = x->as_Store();
2323 } else if (is_CAS(x->Opcode())) {
2324 if (st != NULL || cas != NULL) {
2325 return NULL;
2326 }
2327 cas = x->as_LoadStore();
2328 }
2329 }
2330
2331 // we should not have both a store and a cas
2332 if (st == NULL & cas == NULL) {
2333 return NULL;
2334 }
2335
2336 if (st == NULL) {
2337 // nothing more to check
2338 return leading;
2339 } else {
2340 // we should not have a store if we started from an acquire
2341 if (is_cas) {
2342 return NULL;
2343 }
2344
2345 // the store should feed the merge we used to get here
2346 for (DUIterator_Fast imax, i = st->fast_outs(imax); i < imax; i++) {
2347 if (st->fast_out(i) == mm) {
2348 return leading;
2349 }
2350 }
2351 }
2352
2353 return NULL;
2354 }
2355
2356 // card_mark_to_leading
2357 //
2358 // graph traversal helper which traverses from a card mark volatile
2359 // membar to a leading membar i.e. it ensures that the following Mem
2360 // flow subgraph is present.
2361 //
2362 // MemBarRelease {leading}
2363 // {MemBarCPUOrder} {optional}
2364 // | . . .
2365 // Bot | /
2366 // MergeMem
2367 // |
2368 // MemBarVolatile (card mark)
2369 // | \
2370 // . . . StoreCM
2371 //
2372 // if the configuration is present returns the cpuorder member for
2373 // preference or when absent the release membar otherwise NULL.
2374 //
2375 // n.b. the input membar is expected to be a MemBarVolatile amd must
2376 // be a card mark membar.
2377
2378 MemBarNode *card_mark_to_leading(const MemBarNode *barrier)
2379 {
2380 // input must be a card mark volatile membar
2381 assert(is_card_mark_membar(barrier), "expecting a card mark membar");
2382
2383 // the Mem feed to the membar should be a merge
2384 Node *x = barrier->in(TypeFunc::Memory);
2385 if (!x->is_MergeMem()) {
2386 return NULL;
2387 }
2388
2389 MergeMemNode *mm = x->as_MergeMem();
2390
2391 x = mm->in(Compile::AliasIdxBot);
2392
2393 if (!x->is_MemBar()) {
2394 return NULL;
2395 }
2396
2397 MemBarNode *leading = x->as_MemBar();
2398
2399 if (leading_membar(leading)) {
2400 return leading;
2401 }
2402
2403 return NULL;
2404 }
2405
2406 bool unnecessary_acquire(const Node *barrier)
2407 {
2408 assert(barrier->is_MemBar(), "expecting a membar");
2409
2410 if (UseBarriersForVolatile) {
2411 // we need to plant a dmb
2412 return false;
2413 }
2414
2415 // a volatile read derived from bytecode (or also from an inlined
2416 // SHA field read via LibraryCallKit::load_field_from_object)
2417 // manifests as a LoadX[mo_acquire] followed by an acquire membar
2418 // with a bogus read dependency on it's preceding load. so in those
2419 // cases we will find the load node at the PARMS offset of the
2420 // acquire membar. n.b. there may be an intervening DecodeN node.
2421 //
2422 // a volatile load derived from an inlined unsafe field access
2423 // manifests as a cpuorder membar with Ctl and Mem projections
2424 // feeding both an acquire membar and a LoadX[mo_acquire]. The
2425 // acquire then feeds another cpuorder membar via Ctl and Mem
2426 // projections. The load has no output dependency on these trailing
2427 // membars because subsequent nodes inserted into the graph take
2428 // their control feed from the final membar cpuorder meaning they
2429 // are all ordered after the load.
2430
2431 Node *x = barrier->lookup(TypeFunc::Parms);
2432 if (x) {
2433 // we are starting from an acquire and it has a fake dependency
2434 //
2435 // need to check for
2436 //
2437 // LoadX[mo_acquire]
2438 // { |1 }
2439 // {DecodeN}
2440 // |Parms
2441 // MemBarAcquire*
2442 //
2443 // where * tags node we were passed
2444 // and |k means input k
2445 if (x->is_DecodeNarrowPtr()) {
2446 x = x->in(1);
2447 }
2448
2449 return (x->is_Load() && x->as_Load()->is_acquire());
2450 }
2451
2452 // now check for an unsafe volatile get
2453
2454 // need to check for
2455 //
2456 // MemBarCPUOrder
2457 // || \\
2458 // MemBarAcquire* LoadX[mo_acquire]
2459 // ||
2460 // MemBarCPUOrder
2461 //
2462 // where * tags node we were passed
2463 // and || or \\ are Ctl+Mem feeds via intermediate Proj Nodes
2464
2465 // check for a parent MemBarCPUOrder
2466 ProjNode *ctl;
2467 ProjNode *mem;
2468 MemBarNode *parent = parent_membar(barrier);
2469 if (!parent || parent->Opcode() != Op_MemBarCPUOrder)
2470 return false;
2471 ctl = parent->proj_out(TypeFunc::Control);
2472 mem = parent->proj_out(TypeFunc::Memory);
2473 if (!ctl || !mem) {
2474 return false;
2475 }
2476 // ensure the proj nodes both feed a LoadX[mo_acquire]
2477 LoadNode *ld = NULL;
2478 for (DUIterator_Fast imax, i = ctl->fast_outs(imax); i < imax; i++) {
2479 x = ctl->fast_out(i);
2480 // if we see a load we keep hold of it and stop searching
2481 if (x->is_Load()) {
2482 ld = x->as_Load();
2483 break;
2484 }
2485 }
2486 // it must be an acquiring load
2487 if (ld && ld->is_acquire()) {
2488
2489 for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) {
2490 x = mem->fast_out(i);
2491 // if we see the same load we drop it and stop searching
2492 if (x == ld) {
2493 ld = NULL;
2494 break;
2495 }
2496 }
2497 // we must have dropped the load
2498 if (ld == NULL) {
2499 // check for a child cpuorder membar
2500 MemBarNode *child = child_membar(barrier->as_MemBar());
2501 if (child && child->Opcode() == Op_MemBarCPUOrder)
2502 return true;
2503 }
2504 }
2505
2506 // final option for unnecessary mebar is that it is a trailing node
2507 // belonging to a CAS
2508
2509 MemBarNode *leading = trailing_to_leading(barrier->as_MemBar());
2510
2511 return leading != NULL;
2512 }
2513
2514 bool needs_acquiring_load(const Node *n)
2515 {
2516 assert(n->is_Load(), "expecting a load");
2517 if (UseBarriersForVolatile) {
2518 // we use a normal load and a dmb
2519 return false;
2520 }
2521
2522 LoadNode *ld = n->as_Load();
2523
2524 if (!ld->is_acquire()) {
2525 return false;
2526 }
2527
2528 // check if this load is feeding an acquire membar
2529 //
2530 // LoadX[mo_acquire]
2531 // { |1 }
2532 // {DecodeN}
2533 // |Parms
2534 // MemBarAcquire*
2535 //
2536 // where * tags node we were passed
2537 // and |k means input k
2538
2539 Node *start = ld;
2540 Node *mbacq = NULL;
2541
2542 // if we hit a DecodeNarrowPtr we reset the start node and restart
2543 // the search through the outputs
2544 restart:
2545
2546 for (DUIterator_Fast imax, i = start->fast_outs(imax); i < imax; i++) {
2547 Node *x = start->fast_out(i);
2548 if (x->is_MemBar() && x->Opcode() == Op_MemBarAcquire) {
2549 mbacq = x;
2550 } else if (!mbacq &&
2551 (x->is_DecodeNarrowPtr() ||
2552 (x->is_Mach() && x->Opcode() == Op_DecodeN))) {
2553 start = x;
2554 goto restart;
2555 }
2556 }
2557
2558 if (mbacq) {
2559 return true;
2560 }
2561
2562 // now check for an unsafe volatile get
2563
2564 // check if Ctl and Proj feed comes from a MemBarCPUOrder
2565 //
2566 // MemBarCPUOrder
2567 // || \\
2568 // MemBarAcquire* LoadX[mo_acquire]
2569 // ||
2570 // MemBarCPUOrder
2571
2572 MemBarNode *membar;
2573
2574 membar = parent_membar(ld);
2575
2576 if (!membar || !membar->Opcode() == Op_MemBarCPUOrder) {
2577 return false;
2578 }
2579
2580 // ensure that there is a CPUOrder->Acquire->CPUOrder membar chain
2581
2582 membar = child_membar(membar);
2583
2584 if (!membar || !membar->Opcode() == Op_MemBarAcquire) {
2585 return false;
2586 }
2587
2588 membar = child_membar(membar);
2589
2590 if (!membar || !membar->Opcode() == Op_MemBarCPUOrder) {
2591 return false;
2592 }
2593
2594 return true;
2595 }
2596
2597 bool unnecessary_release(const Node *n)
2598 {
2599 assert((n->is_MemBar() &&
2600 n->Opcode() == Op_MemBarRelease),
2601 "expecting a release membar");
2602
2603 if (UseBarriersForVolatile) {
2604 // we need to plant a dmb
2605 return false;
2606 }
2607
2608 // if there is a dependent CPUOrder barrier then use that as the
2609 // leading
2610
2611 MemBarNode *barrier = n->as_MemBar();
2612 // check for an intervening cpuorder membar
2613 MemBarNode *b = child_membar(barrier);
2614 if (b && b->Opcode() == Op_MemBarCPUOrder) {
2615 // ok, so start the check from the dependent cpuorder barrier
2616 barrier = b;
2617 }
2618
2619 // must start with a normal feed
2620 MemBarNode *trailing = leading_to_trailing(barrier);
2621
2622 return (trailing != NULL);
2623 }
2624
2625 bool unnecessary_volatile(const Node *n)
2626 {
2627 // assert n->is_MemBar();
2628 if (UseBarriersForVolatile) {
2629 // we need to plant a dmb
2630 return false;
2631 }
2632
2633 MemBarNode *mbvol = n->as_MemBar();
2634
2635 // first we check if this is part of a card mark. if so then we have
2636 // to generate a StoreLoad barrier
2637
2638 if (is_card_mark_membar(mbvol)) {
2639 return false;
2640 }
2641
2642 // ok, if it's not a card mark then we still need to check if it is
2643 // a trailing membar of a volatile put graph.
2644
2645 return (trailing_to_leading(mbvol) != NULL);
2646 }
2647
2648 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
2649
2650 bool needs_releasing_store(const Node *n)
2651 {
2652 // assert n->is_Store();
2653 if (UseBarriersForVolatile) {
2654 // we use a normal store and dmb combination
2655 return false;
2656 }
2657
2658 StoreNode *st = n->as_Store();
2659
2660 // the store must be marked as releasing
2661 if (!st->is_release()) {
2662 return false;
2663 }
2664
2665 // the store must be fed by a membar
2666
2667 Node *x = st->lookup(StoreNode::Memory);
2668
2669 if (! x || !x->is_Proj()) {
2670 return false;
2671 }
2672
2673 ProjNode *proj = x->as_Proj();
2674
2675 x = proj->lookup(0);
2676
2677 if (!x || !x->is_MemBar()) {
2678 return false;
2679 }
2680
2681 MemBarNode *barrier = x->as_MemBar();
2682
2683 // if the barrier is a release membar or a cpuorder mmebar fed by a
2684 // release membar then we need to check whether that forms part of a
2685 // volatile put graph.
2686
2687 // reject invalid candidates
2688 if (!leading_membar(barrier)) {
2689 return false;
2690 }
2691
2692 // does this lead a normal subgraph?
2693 MemBarNode *trailing = leading_to_trailing(barrier);
2694
2695 return (trailing != NULL);
2696 }
2697
2698 // predicate controlling translation of CAS
2699 //
2700 // returns true if CAS needs to use an acquiring load otherwise false
2701
2702 bool needs_acquiring_load_exclusive(const Node *n)
2703 {
2704 assert(is_CAS(n->Opcode()), "expecting a compare and swap");
2705 if (UseBarriersForVolatile) {
2706 return false;
2707 }
2708
2709 // CAS nodes only ought to turn up in inlined unsafe CAS operations
2710 #ifdef ASSERT
2711 LoadStoreNode *st = n->as_LoadStore();
2712
2713 // the store must be fed by a membar
2714
2715 Node *x = st->lookup(StoreNode::Memory);
2716
2717 assert (x && x->is_Proj(), "CAS not fed by memory proj!");
2718
2719 ProjNode *proj = x->as_Proj();
2720
2721 x = proj->lookup(0);
2722
2723 assert (x && x->is_MemBar(), "CAS not fed by membar!");
2724
2725 MemBarNode *barrier = x->as_MemBar();
2726
2727 // the barrier must be a cpuorder mmebar fed by a release membar
2728
2729 assert(barrier->Opcode() == Op_MemBarCPUOrder,
2730 "CAS not fed by cpuorder membar!");
2731
2732 MemBarNode *b = parent_membar(barrier);
2733 assert ((b != NULL && b->Opcode() == Op_MemBarRelease),
2734 "CAS not fed by cpuorder+release membar pair!");
2735
2736 // does this lead a normal subgraph?
2737 MemBarNode *mbar = leading_to_trailing(barrier);
2738
2739 assert(mbar != NULL, "CAS not embedded in normal graph!");
2740
2741 assert(mbar->Opcode() == Op_MemBarAcquire, "trailing membar should be an acquire");
2742 #endif // ASSERT
2743 // so we can just return true here
2744 return true;
2745 }
2746
2747 // predicate controlling translation of StoreCM
2748 //
2749 // returns true if a StoreStore must precede the card write otherwise
2750 // false
2751
2752 bool unnecessary_storestore(const Node *storecm)
2753 {
2754 assert(storecm->Opcode() == Op_StoreCM, "expecting a StoreCM");
2755
2756 // we only ever need to generate a dmb ishst between an object put
2757 // and the associated card mark when we are using CMS without
2758 // conditional card marking. Any other occurence will happen when
2759 // performing a card mark using CMS with conditional card marking or
2760 // G1. In those cases the preceding MamBarVolatile will be
2761 // translated to a dmb ish which guarantes visibility of the
2762 // preceding StoreN/P before this StoreCM
2763
2764 if (!UseConcMarkSweepGC || UseCondCardMark) {
2765 return true;
2766 }
2767
2768 // if we are implementing volatile puts using barriers then we must
2769 // insert the dmb ishst
2770
2771 if (UseBarriersForVolatile) {
2772 return false;
2773 }
2774
2775 // we must be using CMS with conditional card marking so we ahve to
2776 // generate the StoreStore
2777
2778 return false;
2779 }
2780
2781
2782 #define __ _masm.
2783
2784 // advance declarations for helper functions to convert register
2785 // indices to register objects
2786
2787 // the ad file has to provide implementations of certain methods
2788 // expected by the generic code
2789 //
2790 // REQUIRED FUNCTIONALITY
2791
2792 //=============================================================================
2793
2794 // !!!!! Special hack to get all types of calls to specify the byte offset
2795 // from the start of the call to the point where the return address
2796 // will point.
2797
2798 int MachCallStaticJavaNode::ret_addr_offset()
2799 {
2800 // call should be a simple bl
2801 int off = 4;
2802 return off;
2803 }
2804
2805 int MachCallDynamicJavaNode::ret_addr_offset()
2806 {
2807 return 16; // movz, movk, movk, bl
2808 }
2809
2810 int MachCallRuntimeNode::ret_addr_offset() {
2811 // for generated stubs the call will be
2812 // far_call(addr)
2813 // for real runtime callouts it will be six instructions
2814 // see aarch64_enc_java_to_runtime
2815 // adr(rscratch2, retaddr)
2816 // lea(rscratch1, RuntimeAddress(addr)
2817 // stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)))
2818 // blrt rscratch1
2819 CodeBlob *cb = CodeCache::find_blob(_entry_point);
2820 if (cb) {
2821 return MacroAssembler::far_branch_size();
2822 } else {
2823 return 6 * NativeInstruction::instruction_size;
2824 }
2825 }
2826
2827 // Indicate if the safepoint node needs the polling page as an input
2828
2829 // the shared code plants the oop data at the start of the generated
2830 // code for the safepoint node and that needs ot be at the load
2831 // instruction itself. so we cannot plant a mov of the safepoint poll
2832 // address followed by a load. setting this to true means the mov is
2833 // scheduled as a prior instruction. that's better for scheduling
2834 // anyway.
2835
2836 bool SafePointNode::needs_polling_address_input()
2837 {
2838 return true;
2839 }
2840
2841 //=============================================================================
2842
2843 #ifndef PRODUCT
2844 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2845 st->print("BREAKPOINT");
2846 }
2847 #endif
2848
2849 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2850 MacroAssembler _masm(&cbuf);
2851 __ brk(0);
2852 }
2853
2854 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
2855 return MachNode::size(ra_);
2856 }
2857
2858 //=============================================================================
2859
2860 #ifndef PRODUCT
2861 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
2862 st->print("nop \t# %d bytes pad for loops and calls", _count);
2863 }
2864 #endif
2865
2866 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
2867 MacroAssembler _masm(&cbuf);
2868 for (int i = 0; i < _count; i++) {
2869 __ nop();
2870 }
2871 }
2872
2873 uint MachNopNode::size(PhaseRegAlloc*) const {
2874 return _count * NativeInstruction::instruction_size;
2875 }
2876
2877 //=============================================================================
2878 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
2879
2880 int Compile::ConstantTable::calculate_table_base_offset() const {
2881 return 0; // absolute addressing, no offset
2882 }
2883
2884 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
2885 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
2886 ShouldNotReachHere();
2887 }
2888
2889 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
2890 // Empty encoding
2891 }
2892
2893 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
2894 return 0;
2895 }
2896
2897 #ifndef PRODUCT
2898 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
2899 st->print("-- \t// MachConstantBaseNode (empty encoding)");
2900 }
2901 #endif
2902
2903 #ifndef PRODUCT
2904 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2905 Compile* C = ra_->C;
2906
2907 int framesize = C->frame_slots() << LogBytesPerInt;
2908
2909 if (C->need_stack_bang(framesize))
2910 st->print("# stack bang size=%d\n\t", framesize);
2911
2912 if (framesize < ((1 << 9) + 2 * wordSize)) {
2913 st->print("sub sp, sp, #%d\n\t", framesize);
2914 st->print("stp rfp, lr, [sp, #%d]", framesize - 2 * wordSize);
2915 if (PreserveFramePointer) st->print("\n\tadd rfp, sp, #%d", framesize - 2 * wordSize);
2916 } else {
2917 st->print("stp lr, rfp, [sp, #%d]!\n\t", -(2 * wordSize));
2918 if (PreserveFramePointer) st->print("mov rfp, sp\n\t");
2919 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
2920 st->print("sub sp, sp, rscratch1");
2921 }
2922 }
2923 #endif
2924
2925 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2926 Compile* C = ra_->C;
2927 MacroAssembler _masm(&cbuf);
2928
2929 // n.b. frame size includes space for return pc and rfp
2930 const long framesize = C->frame_size_in_bytes();
2931 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
2932
2933 // insert a nop at the start of the prolog so we can patch in a
2934 // branch if we need to invalidate the method later
2935 __ nop();
2936
2937 int bangsize = C->bang_size_in_bytes();
2938 if (C->need_stack_bang(bangsize) && UseStackBanging)
2939 __ generate_stack_overflow_check(bangsize);
2940
2941 __ build_frame(framesize);
2942
2943 if (NotifySimulator) {
2944 __ notify(Assembler::method_entry);
2945 }
2946
2947 if (VerifyStackAtCalls) {
2948 Unimplemented();
2949 }
2950
2951 C->set_frame_complete(cbuf.insts_size());
2952
2953 if (C->has_mach_constant_base_node()) {
2954 // NOTE: We set the table base offset here because users might be
2955 // emitted before MachConstantBaseNode.
2956 Compile::ConstantTable& constant_table = C->constant_table();
2957 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
2958 }
2959 }
2960
2961 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
2962 {
2963 return MachNode::size(ra_); // too many variables; just compute it
2964 // the hard way
2965 }
2966
2967 int MachPrologNode::reloc() const
2968 {
2969 return 0;
2970 }
2971
2972 //=============================================================================
2973
2974 #ifndef PRODUCT
2975 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2976 Compile* C = ra_->C;
2977 int framesize = C->frame_slots() << LogBytesPerInt;
2978
2979 st->print("# pop frame %d\n\t",framesize);
2980
2981 if (framesize == 0) {
2982 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
2983 } else if (framesize < ((1 << 9) + 2 * wordSize)) {
2984 st->print("ldp lr, rfp, [sp,#%d]\n\t", framesize - 2 * wordSize);
2985 st->print("add sp, sp, #%d\n\t", framesize);
2986 } else {
2987 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
2988 st->print("add sp, sp, rscratch1\n\t");
2989 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
2990 }
2991
2992 if (do_polling() && C->is_method_compilation()) {
2993 st->print("# touch polling page\n\t");
2994 st->print("mov rscratch1, #0x%lx\n\t", p2i(os::get_polling_page()));
2995 st->print("ldr zr, [rscratch1]");
2996 }
2997 }
2998 #endif
2999
3000 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
3001 Compile* C = ra_->C;
3002 MacroAssembler _masm(&cbuf);
3003 int framesize = C->frame_slots() << LogBytesPerInt;
3004
3005 __ remove_frame(framesize);
3006
3007 if (NotifySimulator) {
3008 __ notify(Assembler::method_reentry);
3009 }
3010
3011 if (do_polling() && C->is_method_compilation()) {
3012 __ read_polling_page(rscratch1, os::get_polling_page(), relocInfo::poll_return_type);
3013 }
3014 }
3015
3016 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
3017 // Variable size. Determine dynamically.
3018 return MachNode::size(ra_);
3019 }
3020
3021 int MachEpilogNode::reloc() const {
3022 // Return number of relocatable values contained in this instruction.
3023 return 1; // 1 for polling page.
3024 }
3025
3026 const Pipeline * MachEpilogNode::pipeline() const {
3027 return MachNode::pipeline_class();
3028 }
3029
3030 // This method seems to be obsolete. It is declared in machnode.hpp
3031 // and defined in all *.ad files, but it is never called. Should we
3032 // get rid of it?
3033 int MachEpilogNode::safepoint_offset() const {
3034 assert(do_polling(), "no return for this epilog node");
3035 return 4;
3036 }
3037
3038 //=============================================================================
3039
3040 // Figure out which register class each belongs in: rc_int, rc_float or
3041 // rc_stack.
3042 enum RC { rc_bad, rc_int, rc_float, rc_stack };
3043
3044 static enum RC rc_class(OptoReg::Name reg) {
3045
3046 if (reg == OptoReg::Bad) {
3047 return rc_bad;
3048 }
3049
3050 // we have 30 int registers * 2 halves
3051 // (rscratch1 and rscratch2 are omitted)
3052
3053 if (reg < 60) {
3054 return rc_int;
3055 }
3056
3057 // we have 32 float register * 2 halves
3058 if (reg < 60 + 128) {
3059 return rc_float;
3060 }
3061
3062 // Between float regs & stack is the flags regs.
3063 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
3064
3065 return rc_stack;
3066 }
3067
3068 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
3069 Compile* C = ra_->C;
3070
3071 // Get registers to move.
3072 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
3073 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
3074 OptoReg::Name dst_hi = ra_->get_reg_second(this);
3075 OptoReg::Name dst_lo = ra_->get_reg_first(this);
3076
3077 enum RC src_hi_rc = rc_class(src_hi);
3078 enum RC src_lo_rc = rc_class(src_lo);
3079 enum RC dst_hi_rc = rc_class(dst_hi);
3080 enum RC dst_lo_rc = rc_class(dst_lo);
3081
3082 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
3083
3084 if (src_hi != OptoReg::Bad) {
3085 assert((src_lo&1)==0 && src_lo+1==src_hi &&
3086 (dst_lo&1)==0 && dst_lo+1==dst_hi,
3087 "expected aligned-adjacent pairs");
3088 }
3089
3090 if (src_lo == dst_lo && src_hi == dst_hi) {
3091 return 0; // Self copy, no move.
3092 }
3093
3094 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
3095 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
3096 int src_offset = ra_->reg2offset(src_lo);
3097 int dst_offset = ra_->reg2offset(dst_lo);
3098
3099 if (bottom_type()->isa_vect() != NULL) {
3100 uint ireg = ideal_reg();
3101 assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
3102 if (cbuf) {
3103 MacroAssembler _masm(cbuf);
3104 assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
3105 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
3106 // stack->stack
3107 assert((src_offset & 7) == 0 && (dst_offset & 7) == 0, "unaligned stack offset");
3108 if (ireg == Op_VecD) {
3109 __ unspill(rscratch1, true, src_offset);
3110 __ spill(rscratch1, true, dst_offset);
3111 } else {
3112 __ spill_copy128(src_offset, dst_offset);
3113 }
3114 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
3115 __ mov(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3116 ireg == Op_VecD ? __ T8B : __ T16B,
3117 as_FloatRegister(Matcher::_regEncode[src_lo]));
3118 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
3119 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
3120 ireg == Op_VecD ? __ D : __ Q,
3121 ra_->reg2offset(dst_lo));
3122 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
3123 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3124 ireg == Op_VecD ? __ D : __ Q,
3125 ra_->reg2offset(src_lo));
3126 } else {
3127 ShouldNotReachHere();
3128 }
3129 }
3130 } else if (cbuf) {
3131 MacroAssembler _masm(cbuf);
3132 switch (src_lo_rc) {
3133 case rc_int:
3134 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
3135 if (is64) {
3136 __ mov(as_Register(Matcher::_regEncode[dst_lo]),
3137 as_Register(Matcher::_regEncode[src_lo]));
3138 } else {
3139 MacroAssembler _masm(cbuf);
3140 __ movw(as_Register(Matcher::_regEncode[dst_lo]),
3141 as_Register(Matcher::_regEncode[src_lo]));
3142 }
3143 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
3144 if (is64) {
3145 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3146 as_Register(Matcher::_regEncode[src_lo]));
3147 } else {
3148 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3149 as_Register(Matcher::_regEncode[src_lo]));
3150 }
3151 } else { // gpr --> stack spill
3152 assert(dst_lo_rc == rc_stack, "spill to bad register class");
3153 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
3154 }
3155 break;
3156 case rc_float:
3157 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
3158 if (is64) {
3159 __ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
3160 as_FloatRegister(Matcher::_regEncode[src_lo]));
3161 } else {
3162 __ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
3163 as_FloatRegister(Matcher::_regEncode[src_lo]));
3164 }
3165 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
3166 if (cbuf) {
3167 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3168 as_FloatRegister(Matcher::_regEncode[src_lo]));
3169 } else {
3170 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3171 as_FloatRegister(Matcher::_regEncode[src_lo]));
3172 }
3173 } else { // fpr --> stack spill
3174 assert(dst_lo_rc == rc_stack, "spill to bad register class");
3175 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
3176 is64 ? __ D : __ S, dst_offset);
3177 }
3178 break;
3179 case rc_stack:
3180 if (dst_lo_rc == rc_int) { // stack --> gpr load
3181 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
3182 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
3183 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
3184 is64 ? __ D : __ S, src_offset);
3185 } else { // stack --> stack copy
3186 assert(dst_lo_rc == rc_stack, "spill to bad register class");
3187 __ unspill(rscratch1, is64, src_offset);
3188 __ spill(rscratch1, is64, dst_offset);
3189 }
3190 break;
3191 default:
3192 assert(false, "bad rc_class for spill");
3193 ShouldNotReachHere();
3194 }
3195 }
3196
3197 if (st) {
3198 st->print("spill ");
3199 if (src_lo_rc == rc_stack) {
3200 st->print("[sp, #%d] -> ", ra_->reg2offset(src_lo));
3201 } else {
3202 st->print("%s -> ", Matcher::regName[src_lo]);
3203 }
3204 if (dst_lo_rc == rc_stack) {
3205 st->print("[sp, #%d]", ra_->reg2offset(dst_lo));
3206 } else {
3207 st->print("%s", Matcher::regName[dst_lo]);
3208 }
3209 if (bottom_type()->isa_vect() != NULL) {
3210 st->print("\t# vector spill size = %d", ideal_reg()==Op_VecD ? 64:128);
3211 } else {
3212 st->print("\t# spill size = %d", is64 ? 64:32);
3213 }
3214 }
3215
3216 return 0;
3217
3218 }
3219
3220 #ifndef PRODUCT
3221 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
3222 if (!ra_)
3223 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
3224 else
3225 implementation(NULL, ra_, false, st);
3226 }
3227 #endif
3228
3229 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
3230 implementation(&cbuf, ra_, false, NULL);
3231 }
3232
3233 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
3234 return MachNode::size(ra_);
3235 }
3236
3237 //=============================================================================
3238
3239 #ifndef PRODUCT
3240 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
3241 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
3242 int reg = ra_->get_reg_first(this);
3243 st->print("add %s, rsp, #%d]\t# box lock",
3244 Matcher::regName[reg], offset);
3245 }
3246 #endif
3247
3248 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
3249 MacroAssembler _masm(&cbuf);
3250
3251 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
3252 int reg = ra_->get_encode(this);
3253
3254 if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
3255 __ add(as_Register(reg), sp, offset);
3256 } else {
3257 ShouldNotReachHere();
3258 }
3259 }
3260
3261 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
3262 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
3263 return 4;
3264 }
3265
3266 //=============================================================================
3267
3268 #ifndef PRODUCT
3269 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
3270 {
3271 st->print_cr("# MachUEPNode");
3272 if (UseCompressedClassPointers) {
3273 st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
3274 if (Universe::narrow_klass_shift() != 0) {
3275 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
3276 }
3277 } else {
3278 st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
3279 }
3280 st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
3281 st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
3282 }
3283 #endif
3284
3285 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
3286 {
3287 // This is the unverified entry point.
3288 MacroAssembler _masm(&cbuf);
3289
3290 __ cmp_klass(j_rarg0, rscratch2, rscratch1);
3291 Label skip;
3292 // TODO
3293 // can we avoid this skip and still use a reloc?
3294 __ br(Assembler::EQ, skip);
3295 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
3296 __ bind(skip);
3297 }
3298
3299 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
3300 {
3301 return MachNode::size(ra_);
3302 }
3303
3304 // REQUIRED EMIT CODE
3305
3306 //=============================================================================
3307
3308 // Emit exception handler code.
3309 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
3310 {
3311 // mov rscratch1 #exception_blob_entry_point
3312 // br rscratch1
3313 // Note that the code buffer's insts_mark is always relative to insts.
3314 // That's why we must use the macroassembler to generate a handler.
3315 MacroAssembler _masm(&cbuf);
3316 address base = __ start_a_stub(size_exception_handler());
3317 if (base == NULL) {
3318 ciEnv::current()->record_failure("CodeCache is full");
3319 return 0; // CodeBuffer::expand failed
3320 }
3321 int offset = __ offset();
3322 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
3323 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
3324 __ end_a_stub();
3325 return offset;
3326 }
3327
3328 // Emit deopt handler code.
3329 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
3330 {
3331 // Note that the code buffer's insts_mark is always relative to insts.
3332 // That's why we must use the macroassembler to generate a handler.
3333 MacroAssembler _masm(&cbuf);
3334 address base = __ start_a_stub(size_deopt_handler());
3335 if (base == NULL) {
3336 ciEnv::current()->record_failure("CodeCache is full");
3337 return 0; // CodeBuffer::expand failed
3338 }
3339 int offset = __ offset();
3340
3341 __ adr(lr, __ pc());
3342 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
3343
3344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
3345 __ end_a_stub();
3346 return offset;
3347 }
3348
3349 // REQUIRED MATCHER CODE
3350
3351 //=============================================================================
3352
3353 const bool Matcher::match_rule_supported(int opcode) {
3354
3355 switch (opcode) {
3356 default:
3357 break;
3358 }
3359
3360 if (!has_match_rule(opcode)) {
3361 return false;
3362 }
3363
3364 return true; // Per default match rules are supported.
3365 }
3366
3367 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
3368
3369 // TODO
3370 // identify extra cases that we might want to provide match rules for
3371 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
3372 bool ret_value = match_rule_supported(opcode);
3373 // Add rules here.
3374
3375 return ret_value; // Per default match rules are supported.
3376 }
3377
3378 const bool Matcher::has_predicated_vectors(void) {
3379 return false;
3380 }
3381
3382 const int Matcher::float_pressure(int default_pressure_threshold) {
3383 return default_pressure_threshold;
3384 }
3385
3386 int Matcher::regnum_to_fpu_offset(int regnum)
3387 {
3388 Unimplemented();
3389 return 0;
3390 }
3391
3392 // Is this branch offset short enough that a short branch can be used?
3393 //
3394 // NOTE: If the platform does not provide any short branch variants, then
3395 // this method should return false for offset 0.
3396 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
3397 // The passed offset is relative to address of the branch.
3398
3399 return (-32768 <= offset && offset < 32768);
3400 }
3401
3402 const bool Matcher::isSimpleConstant64(jlong value) {
3403 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
3404 // Probably always true, even if a temp register is required.
3405 return true;
3406 }
3407
3408 // true just means we have fast l2f conversion
3409 const bool Matcher::convL2FSupported(void) {
3410 return true;
3411 }
3412
3413 // Vector width in bytes.
3414 const int Matcher::vector_width_in_bytes(BasicType bt) {
3415 int size = MIN2(16,(int)MaxVectorSize);
3416 // Minimum 2 values in vector
3417 if (size < 2*type2aelembytes(bt)) size = 0;
3418 // But never < 4
3419 if (size < 4) size = 0;
3420 return size;
3421 }
3422
3423 // Limits on vector size (number of elements) loaded into vector.
3424 const int Matcher::max_vector_size(const BasicType bt) {
3425 return vector_width_in_bytes(bt)/type2aelembytes(bt);
3426 }
3427 const int Matcher::min_vector_size(const BasicType bt) {
3428 // For the moment limit the vector size to 8 bytes
3429 int size = 8 / type2aelembytes(bt);
3430 if (size < 2) size = 2;
3431 return size;
3432 }
3433
3434 // Vector ideal reg.
3435 const int Matcher::vector_ideal_reg(int len) {
3436 switch(len) {
3437 case 8: return Op_VecD;
3438 case 16: return Op_VecX;
3439 }
3440 ShouldNotReachHere();
3441 return 0;
3442 }
3443
3444 const int Matcher::vector_shift_count_ideal_reg(int size) {
3445 return Op_VecX;
3446 }
3447
3448 // AES support not yet implemented
3449 const bool Matcher::pass_original_key_for_aes() {
3450 return false;
3451 }
3452
3453 // x86 supports misaligned vectors store/load.
3454 const bool Matcher::misaligned_vectors_ok() {
3455 return !AlignVector; // can be changed by flag
3456 }
3457
3458 // false => size gets scaled to BytesPerLong, ok.
3459 const bool Matcher::init_array_count_is_in_bytes = false;
3460
3461 // Use conditional move (CMOVL)
3462 const int Matcher::long_cmove_cost() {
3463 // long cmoves are no more expensive than int cmoves
3464 return 0;
3465 }
3466
3467 const int Matcher::float_cmove_cost() {
3468 // float cmoves are no more expensive than int cmoves
3469 return 0;
3470 }
3471
3472 // Does the CPU require late expand (see block.cpp for description of late expand)?
3473 const bool Matcher::require_postalloc_expand = false;
3474
3475 // Do we need to mask the count passed to shift instructions or does
3476 // the cpu only look at the lower 5/6 bits anyway?
3477 const bool Matcher::need_masked_shift_count = false;
3478
3479 // This affects two different things:
3480 // - how Decode nodes are matched
3481 // - how ImplicitNullCheck opportunities are recognized
3482 // If true, the matcher will try to remove all Decodes and match them
3483 // (as operands) into nodes. NullChecks are not prepared to deal with
3484 // Decodes by final_graph_reshaping().
3485 // If false, final_graph_reshaping() forces the decode behind the Cmp
3486 // for a NullCheck. The matcher matches the Decode node into a register.
3487 // Implicit_null_check optimization moves the Decode along with the
3488 // memory operation back up before the NullCheck.
3489 bool Matcher::narrow_oop_use_complex_address() {
3490 return Universe::narrow_oop_shift() == 0;
3491 }
3492
3493 bool Matcher::narrow_klass_use_complex_address() {
3494 // TODO
3495 // decide whether we need to set this to true
3496 return false;
3497 }
3498
3499 bool Matcher::const_oop_prefer_decode() {
3500 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
3501 return Universe::narrow_oop_base() == NULL;
3502 }
3503
3504 bool Matcher::const_klass_prefer_decode() {
3505 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
3506 return Universe::narrow_klass_base() == NULL;
3507 }
3508
3509 // Is it better to copy float constants, or load them directly from
3510 // memory? Intel can load a float constant from a direct address,
3511 // requiring no extra registers. Most RISCs will have to materialize
3512 // an address into a register first, so they would do better to copy
3513 // the constant from stack.
3514 const bool Matcher::rematerialize_float_constants = false;
3515
3516 // If CPU can load and store mis-aligned doubles directly then no
3517 // fixup is needed. Else we split the double into 2 integer pieces
3518 // and move it piece-by-piece. Only happens when passing doubles into
3519 // C code as the Java calling convention forces doubles to be aligned.
3520 const bool Matcher::misaligned_doubles_ok = true;
3521
3522 // No-op on amd64
3523 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
3524 Unimplemented();
3525 }
3526
3527 // Advertise here if the CPU requires explicit rounding operations to
3528 // implement the UseStrictFP mode.
3529 const bool Matcher::strict_fp_requires_explicit_rounding = false;
3530
3531 // Are floats converted to double when stored to stack during
3532 // deoptimization?
3533 bool Matcher::float_in_double() { return true; }
3534
3535 // Do ints take an entire long register or just half?
3536 // The relevant question is how the int is callee-saved:
3537 // the whole long is written but de-opt'ing will have to extract
3538 // the relevant 32 bits.
3539 const bool Matcher::int_in_long = true;
3540
3541 // Return whether or not this register is ever used as an argument.
3542 // This function is used on startup to build the trampoline stubs in
3543 // generateOptoStub. Registers not mentioned will be killed by the VM
3544 // call in the trampoline, and arguments in those registers not be
3545 // available to the callee.
3546 bool Matcher::can_be_java_arg(int reg)
3547 {
3548 return
3549 reg == R0_num || reg == R0_H_num ||
3550 reg == R1_num || reg == R1_H_num ||
3551 reg == R2_num || reg == R2_H_num ||
3552 reg == R3_num || reg == R3_H_num ||
3553 reg == R4_num || reg == R4_H_num ||
3554 reg == R5_num || reg == R5_H_num ||
3555 reg == R6_num || reg == R6_H_num ||
3556 reg == R7_num || reg == R7_H_num ||
3557 reg == V0_num || reg == V0_H_num ||
3558 reg == V1_num || reg == V1_H_num ||
3559 reg == V2_num || reg == V2_H_num ||
3560 reg == V3_num || reg == V3_H_num ||
3561 reg == V4_num || reg == V4_H_num ||
3562 reg == V5_num || reg == V5_H_num ||
3563 reg == V6_num || reg == V6_H_num ||
3564 reg == V7_num || reg == V7_H_num;
3565 }
3566
3567 bool Matcher::is_spillable_arg(int reg)
3568 {
3569 return can_be_java_arg(reg);
3570 }
3571
3572 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
3573 return false;
3574 }
3575
3576 RegMask Matcher::divI_proj_mask() {
3577 ShouldNotReachHere();
3578 return RegMask();
3579 }
3580
3581 // Register for MODI projection of divmodI.
3582 RegMask Matcher::modI_proj_mask() {
3583 ShouldNotReachHere();
3584 return RegMask();
3585 }
3586
3587 // Register for DIVL projection of divmodL.
3588 RegMask Matcher::divL_proj_mask() {
3589 ShouldNotReachHere();
3590 return RegMask();
3591 }
3592
3593 // Register for MODL projection of divmodL.
3594 RegMask Matcher::modL_proj_mask() {
3595 ShouldNotReachHere();
3596 return RegMask();
3597 }
3598
3599 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
3600 return FP_REG_mask();
3601 }
3602
3603 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
3604 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
3605 Node* u = addp->fast_out(i);
3606 if (u->is_Mem()) {
3607 int opsize = u->as_Mem()->memory_size();
3608 assert(opsize > 0, "unexpected memory operand size");
3609 if (u->as_Mem()->memory_size() != (1<<shift)) {
3610 return false;
3611 }
3612 }
3613 }
3614 return true;
3615 }
3616
3617 const bool Matcher::convi2l_type_required = false;
3618
3619 // Should the Matcher clone shifts on addressing modes, expecting them
3620 // to be subsumed into complex addressing expressions or compute them
3621 // into registers?
3622 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
3623 if (clone_base_plus_offset_address(m, mstack, address_visited)) {
3624 return true;
3625 }
3626
3627 Node *off = m->in(AddPNode::Offset);
3628 if (off->Opcode() == Op_LShiftL && off->in(2)->is_Con() &&
3629 size_fits_all_mem_uses(m, off->in(2)->get_int()) &&
3630 // Are there other uses besides address expressions?
3631 !is_visited(off)) {
3632 address_visited.set(off->_idx); // Flag as address_visited
3633 mstack.push(off->in(2), Visit);
3634 Node *conv = off->in(1);
3635 if (conv->Opcode() == Op_ConvI2L &&
3636 // Are there other uses besides address expressions?
3637 !is_visited(conv)) {
3638 address_visited.set(conv->_idx); // Flag as address_visited
3639 mstack.push(conv->in(1), Pre_Visit);
3640 } else {
3641 mstack.push(conv, Pre_Visit);
3642 }
3643 address_visited.test_set(m->_idx); // Flag as address_visited
3644 mstack.push(m->in(AddPNode::Address), Pre_Visit);
3645 mstack.push(m->in(AddPNode::Base), Pre_Visit);
3646 return true;
3647 } else if (off->Opcode() == Op_ConvI2L &&
3648 // Are there other uses besides address expressions?
3649 !is_visited(off)) {
3650 address_visited.test_set(m->_idx); // Flag as address_visited
3651 address_visited.set(off->_idx); // Flag as address_visited
3652 mstack.push(off->in(1), Pre_Visit);
3653 mstack.push(m->in(AddPNode::Address), Pre_Visit);
3654 mstack.push(m->in(AddPNode::Base), Pre_Visit);
3655 return true;
3656 }
3657 return false;
3658 }
3659
3660 // Transform:
3661 // (AddP base (AddP base address (LShiftL index con)) offset)
3662 // into:
3663 // (AddP base (AddP base offset) (LShiftL index con))
3664 // to take full advantage of ARM's addressing modes
3665 void Compile::reshape_address(AddPNode* addp) {
3666 Node *addr = addp->in(AddPNode::Address);
3667 if (addr->is_AddP() && addr->in(AddPNode::Base) == addp->in(AddPNode::Base)) {
3668 const AddPNode *addp2 = addr->as_AddP();
3669 if ((addp2->in(AddPNode::Offset)->Opcode() == Op_LShiftL &&
3670 addp2->in(AddPNode::Offset)->in(2)->is_Con() &&
3671 size_fits_all_mem_uses(addp, addp2->in(AddPNode::Offset)->in(2)->get_int())) ||
3672 addp2->in(AddPNode::Offset)->Opcode() == Op_ConvI2L) {
3673
3674 // Any use that can't embed the address computation?
3675 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
3676 Node* u = addp->fast_out(i);
3677 if (!u->is_Mem() || u->is_LoadVector() || u->is_StoreVector() || u->Opcode() == Op_StoreCM) {
3678 return;
3679 }
3680 }
3681
3682 Node* off = addp->in(AddPNode::Offset);
3683 Node* addr2 = addp2->in(AddPNode::Address);
3684 Node* base = addp->in(AddPNode::Base);
3685
3686 Node* new_addr = NULL;
3687 // Check whether the graph already has the new AddP we need
3688 // before we create one (no GVN available here).
3689 for (DUIterator_Fast imax, i = addr2->fast_outs(imax); i < imax; i++) {
3690 Node* u = addr2->fast_out(i);
3691 if (u->is_AddP() &&
3692 u->in(AddPNode::Base) == base &&
3693 u->in(AddPNode::Address) == addr2 &&
3694 u->in(AddPNode::Offset) == off) {
3695 new_addr = u;
3696 break;
3697 }
3698 }
3699
3700 if (new_addr == NULL) {
3701 new_addr = new AddPNode(base, addr2, off);
3702 }
3703 Node* new_off = addp2->in(AddPNode::Offset);
3704 addp->set_req(AddPNode::Address, new_addr);
3705 if (addr->outcnt() == 0) {
3706 addr->disconnect_inputs(NULL, this);
3707 }
3708 addp->set_req(AddPNode::Offset, new_off);
3709 if (off->outcnt() == 0) {
3710 off->disconnect_inputs(NULL, this);
3711 }
3712 }
3713 }
3714 }
3715
3716 // helper for encoding java_to_runtime calls on sim
3717 //
3718 // this is needed to compute the extra arguments required when
3719 // planting a call to the simulator blrt instruction. the TypeFunc
3720 // can be queried to identify the counts for integral, and floating
3721 // arguments and the return type
3722
3723 static void getCallInfo(const TypeFunc *tf, int &gpcnt, int &fpcnt, int &rtype)
3724 {
3725 int gps = 0;
3726 int fps = 0;
3727 const TypeTuple *domain = tf->domain();
3728 int max = domain->cnt();
3729 for (int i = TypeFunc::Parms; i < max; i++) {
3730 const Type *t = domain->field_at(i);
3731 switch(t->basic_type()) {
3732 case T_FLOAT:
3733 case T_DOUBLE:
3734 fps++;
3735 default:
3736 gps++;
3737 }
3738 }
3739 gpcnt = gps;
3740 fpcnt = fps;
3741 BasicType rt = tf->return_type();
3742 switch (rt) {
3743 case T_VOID:
3744 rtype = MacroAssembler::ret_type_void;
3745 break;
3746 default:
3747 rtype = MacroAssembler::ret_type_integral;
3748 break;
3749 case T_FLOAT:
3750 rtype = MacroAssembler::ret_type_float;
3751 break;
3752 case T_DOUBLE:
3753 rtype = MacroAssembler::ret_type_double;
3754 break;
3755 }
3756 }
3757
3758 #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
3759 MacroAssembler _masm(&cbuf); \
3760 { \
3761 guarantee(INDEX == -1, "mode not permitted for volatile"); \
3762 guarantee(DISP == 0, "mode not permitted for volatile"); \
3763 guarantee(SCALE == 0, "mode not permitted for volatile"); \
3764 __ INSN(REG, as_Register(BASE)); \
3765 }
3766
3767 typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
3768 typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
3769 typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt,
3770 MacroAssembler::SIMD_RegVariant T, const Address &adr);
3771
3772 // Used for all non-volatile memory accesses. The use of
3773 // $mem->opcode() to discover whether this pattern uses sign-extended
3774 // offsets is something of a kludge.
3775 static void loadStore(MacroAssembler masm, mem_insn insn,
3776 Register reg, int opcode,
3777 Register base, int index, int size, int disp)
3778 {
3779 Address::extend scale;
3780
3781 // Hooboy, this is fugly. We need a way to communicate to the
3782 // encoder that the index needs to be sign extended, so we have to
3783 // enumerate all the cases.
3784 switch (opcode) {
3785 case INDINDEXSCALEDI2L:
3786 case INDINDEXSCALEDI2LN:
3787 case INDINDEXI2L:
3788 case INDINDEXI2LN:
3789 scale = Address::sxtw(size);
3790 break;
3791 default:
3792 scale = Address::lsl(size);
3793 }
3794
3795 if (index == -1) {
3796 (masm.*insn)(reg, Address(base, disp));
3797 } else {
3798 assert(disp == 0, "unsupported address mode: disp = %d", disp);
3799 (masm.*insn)(reg, Address(base, as_Register(index), scale));
3800 }
3801 }
3802
3803 static void loadStore(MacroAssembler masm, mem_float_insn insn,
3804 FloatRegister reg, int opcode,
3805 Register base, int index, int size, int disp)
3806 {
3807 Address::extend scale;
3808
3809 switch (opcode) {
3810 case INDINDEXSCALEDI2L:
3811 case INDINDEXSCALEDI2LN:
3812 scale = Address::sxtw(size);
3813 break;
3814 default:
3815 scale = Address::lsl(size);
3816 }
3817
3818 if (index == -1) {
3819 (masm.*insn)(reg, Address(base, disp));
3820 } else {
3821 assert(disp == 0, "unsupported address mode: disp = %d", disp);
3822 (masm.*insn)(reg, Address(base, as_Register(index), scale));
3823 }
3824 }
3825
3826 static void loadStore(MacroAssembler masm, mem_vector_insn insn,
3827 FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
3828 int opcode, Register base, int index, int size, int disp)
3829 {
3830 if (index == -1) {
3831 (masm.*insn)(reg, T, Address(base, disp));
3832 } else {
3833 assert(disp == 0, "unsupported address mode");
3834 (masm.*insn)(reg, T, Address(base, as_Register(index), Address::lsl(size)));
3835 }
3836 }
3837
3838 %}
3839
3840
3841
3842 //----------ENCODING BLOCK-----------------------------------------------------
3843 // This block specifies the encoding classes used by the compiler to
3844 // output byte streams. Encoding classes are parameterized macros
3845 // used by Machine Instruction Nodes in order to generate the bit
3846 // encoding of the instruction. Operands specify their base encoding
3847 // interface with the interface keyword. There are currently
3848 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
3849 // COND_INTER. REG_INTER causes an operand to generate a function
3850 // which returns its register number when queried. CONST_INTER causes
3851 // an operand to generate a function which returns the value of the
3852 // constant when queried. MEMORY_INTER causes an operand to generate
3853 // four functions which return the Base Register, the Index Register,
3854 // the Scale Value, and the Offset Value of the operand when queried.
3855 // COND_INTER causes an operand to generate six functions which return
3856 // the encoding code (ie - encoding bits for the instruction)
3857 // associated with each basic boolean condition for a conditional
3858 // instruction.
3859 //
3860 // Instructions specify two basic values for encoding. Again, a
3861 // function is available to check if the constant displacement is an
3862 // oop. They use the ins_encode keyword to specify their encoding
3863 // classes (which must be a sequence of enc_class names, and their
3864 // parameters, specified in the encoding block), and they use the
3865 // opcode keyword to specify, in order, their primary, secondary, and
3866 // tertiary opcode. Only the opcode sections which a particular
3867 // instruction needs for encoding need to be specified.
3868 encode %{
3869 // Build emit functions for each basic byte or larger field in the
3870 // intel encoding scheme (opcode, rm, sib, immediate), and call them
3871 // from C++ code in the enc_class source block. Emit functions will
3872 // live in the main source block for now. In future, we can
3873 // generalize this by adding a syntax that specifies the sizes of
3874 // fields in an order, so that the adlc can build the emit functions
3875 // automagically
3876
3877 // catch all for unimplemented encodings
3878 enc_class enc_unimplemented %{
3879 MacroAssembler _masm(&cbuf);
3880 __ unimplemented("C2 catch all");
3881 %}
3882
3883 // BEGIN Non-volatile memory access
3884
3885 enc_class aarch64_enc_ldrsbw(iRegI dst, memory mem) %{
3886 Register dst_reg = as_Register($dst$$reg);
3887 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsbw, dst_reg, $mem->opcode(),
3888 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3889 %}
3890
3891 enc_class aarch64_enc_ldrsb(iRegI dst, memory mem) %{
3892 Register dst_reg = as_Register($dst$$reg);
3893 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsb, dst_reg, $mem->opcode(),
3894 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3895 %}
3896
3897 enc_class aarch64_enc_ldrb(iRegI dst, memory mem) %{
3898 Register dst_reg = as_Register($dst$$reg);
3899 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
3900 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3901 %}
3902
3903 enc_class aarch64_enc_ldrb(iRegL dst, memory mem) %{
3904 Register dst_reg = as_Register($dst$$reg);
3905 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
3906 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3907 %}
3908
3909 enc_class aarch64_enc_ldrshw(iRegI dst, memory mem) %{
3910 Register dst_reg = as_Register($dst$$reg);
3911 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrshw, dst_reg, $mem->opcode(),
3912 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3913 %}
3914
3915 enc_class aarch64_enc_ldrsh(iRegI dst, memory mem) %{
3916 Register dst_reg = as_Register($dst$$reg);
3917 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsh, dst_reg, $mem->opcode(),
3918 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3919 %}
3920
3921 enc_class aarch64_enc_ldrh(iRegI dst, memory mem) %{
3922 Register dst_reg = as_Register($dst$$reg);
3923 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
3924 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3925 %}
3926
3927 enc_class aarch64_enc_ldrh(iRegL dst, memory mem) %{
3928 Register dst_reg = as_Register($dst$$reg);
3929 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
3930 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3931 %}
3932
3933 enc_class aarch64_enc_ldrw(iRegI dst, memory mem) %{
3934 Register dst_reg = as_Register($dst$$reg);
3935 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
3936 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3937 %}
3938
3939 enc_class aarch64_enc_ldrw(iRegL dst, memory mem) %{
3940 Register dst_reg = as_Register($dst$$reg);
3941 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
3942 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3943 %}
3944
3945 enc_class aarch64_enc_ldrsw(iRegL dst, memory mem) %{
3946 Register dst_reg = as_Register($dst$$reg);
3947 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsw, dst_reg, $mem->opcode(),
3948 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3949 %}
3950
3951 enc_class aarch64_enc_ldr(iRegL dst, memory mem) %{
3952 Register dst_reg = as_Register($dst$$reg);
3953 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, $mem->opcode(),
3954 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3955 %}
3956
3957 enc_class aarch64_enc_ldrs(vRegF dst, memory mem) %{
3958 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3959 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, dst_reg, $mem->opcode(),
3960 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3961 %}
3962
3963 enc_class aarch64_enc_ldrd(vRegD dst, memory mem) %{
3964 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3965 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, dst_reg, $mem->opcode(),
3966 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3967 %}
3968
3969 enc_class aarch64_enc_ldrvS(vecD dst, memory mem) %{
3970 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3971 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
3972 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3973 %}
3974
3975 enc_class aarch64_enc_ldrvD(vecD dst, memory mem) %{
3976 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3977 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
3978 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3979 %}
3980
3981 enc_class aarch64_enc_ldrvQ(vecX dst, memory mem) %{
3982 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3983 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
3984 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3985 %}
3986
3987 enc_class aarch64_enc_strb(iRegI src, memory mem) %{
3988 Register src_reg = as_Register($src$$reg);
3989 loadStore(MacroAssembler(&cbuf), &MacroAssembler::strb, src_reg, $mem->opcode(),
3990 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3991 %}
3992
3993 enc_class aarch64_enc_strb0(memory mem) %{
3994 MacroAssembler _masm(&cbuf);
3995 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
3996 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3997 %}
3998
3999 enc_class aarch64_enc_strb0_ordered(memory mem) %{
4000 MacroAssembler _masm(&cbuf);
4001 __ membar(Assembler::StoreStore);
4002 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
4003 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4004 %}
4005
4006 enc_class aarch64_enc_strh(iRegI src, memory mem) %{
4007 Register src_reg = as_Register($src$$reg);
4008 loadStore(MacroAssembler(&cbuf), &MacroAssembler::strh, src_reg, $mem->opcode(),
4009 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4010 %}
4011
4012 enc_class aarch64_enc_strh0(memory mem) %{
4013 MacroAssembler _masm(&cbuf);
4014 loadStore(_masm, &MacroAssembler::strh, zr, $mem->opcode(),
4015 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4016 %}
4017
4018 enc_class aarch64_enc_strw(iRegI src, memory mem) %{
4019 Register src_reg = as_Register($src$$reg);
4020 loadStore(MacroAssembler(&cbuf), &MacroAssembler::strw, src_reg, $mem->opcode(),
4021 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4022 %}
4023
4024 enc_class aarch64_enc_strw0(memory mem) %{
4025 MacroAssembler _masm(&cbuf);
4026 loadStore(_masm, &MacroAssembler::strw, zr, $mem->opcode(),
4027 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4028 %}
4029
4030 enc_class aarch64_enc_str(iRegL src, memory mem) %{
4031 Register src_reg = as_Register($src$$reg);
4032 // we sometimes get asked to store the stack pointer into the
4033 // current thread -- we cannot do that directly on AArch64
4034 if (src_reg == r31_sp) {
4035 MacroAssembler _masm(&cbuf);
4036 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
4037 __ mov(rscratch2, sp);
4038 src_reg = rscratch2;
4039 }
4040 loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, $mem->opcode(),
4041 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4042 %}
4043
4044 enc_class aarch64_enc_str0(memory mem) %{
4045 MacroAssembler _masm(&cbuf);
4046 loadStore(_masm, &MacroAssembler::str, zr, $mem->opcode(),
4047 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4048 %}
4049
4050 enc_class aarch64_enc_strs(vRegF src, memory mem) %{
4051 FloatRegister src_reg = as_FloatRegister($src$$reg);
4052 loadStore(MacroAssembler(&cbuf), &MacroAssembler::strs, src_reg, $mem->opcode(),
4053 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4054 %}
4055
4056 enc_class aarch64_enc_strd(vRegD src, memory mem) %{
4057 FloatRegister src_reg = as_FloatRegister($src$$reg);
4058 loadStore(MacroAssembler(&cbuf), &MacroAssembler::strd, src_reg, $mem->opcode(),
4059 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4060 %}
4061
4062 enc_class aarch64_enc_strvS(vecD src, memory mem) %{
4063 FloatRegister src_reg = as_FloatRegister($src$$reg);
4064 loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::S,
4065 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4066 %}
4067
4068 enc_class aarch64_enc_strvD(vecD src, memory mem) %{
4069 FloatRegister src_reg = as_FloatRegister($src$$reg);
4070 loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::D,
4071 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4072 %}
4073
4074 enc_class aarch64_enc_strvQ(vecX src, memory mem) %{
4075 FloatRegister src_reg = as_FloatRegister($src$$reg);
4076 loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::Q,
4077 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
4078 %}
4079
4080 // END Non-volatile memory access
4081
4082 // volatile loads and stores
4083
4084 enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
4085 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4086 rscratch1, stlrb);
4087 %}
4088
4089 enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
4090 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4091 rscratch1, stlrh);
4092 %}
4093
4094 enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
4095 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4096 rscratch1, stlrw);
4097 %}
4098
4099
4100 enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
4101 Register dst_reg = as_Register($dst$$reg);
4102 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4103 rscratch1, ldarb);
4104 __ sxtbw(dst_reg, dst_reg);
4105 %}
4106
4107 enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
4108 Register dst_reg = as_Register($dst$$reg);
4109 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4110 rscratch1, ldarb);
4111 __ sxtb(dst_reg, dst_reg);
4112 %}
4113
4114 enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
4115 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4116 rscratch1, ldarb);
4117 %}
4118
4119 enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
4120 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4121 rscratch1, ldarb);
4122 %}
4123
4124 enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
4125 Register dst_reg = as_Register($dst$$reg);
4126 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4127 rscratch1, ldarh);
4128 __ sxthw(dst_reg, dst_reg);
4129 %}
4130
4131 enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
4132 Register dst_reg = as_Register($dst$$reg);
4133 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4134 rscratch1, ldarh);
4135 __ sxth(dst_reg, dst_reg);
4136 %}
4137
4138 enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
4139 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4140 rscratch1, ldarh);
4141 %}
4142
4143 enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
4144 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4145 rscratch1, ldarh);
4146 %}
4147
4148 enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
4149 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4150 rscratch1, ldarw);
4151 %}
4152
4153 enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
4154 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4155 rscratch1, ldarw);
4156 %}
4157
4158 enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
4159 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4160 rscratch1, ldar);
4161 %}
4162
4163 enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
4164 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4165 rscratch1, ldarw);
4166 __ fmovs(as_FloatRegister($dst$$reg), rscratch1);
4167 %}
4168
4169 enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
4170 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4171 rscratch1, ldar);
4172 __ fmovd(as_FloatRegister($dst$$reg), rscratch1);
4173 %}
4174
4175 enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
4176 Register src_reg = as_Register($src$$reg);
4177 // we sometimes get asked to store the stack pointer into the
4178 // current thread -- we cannot do that directly on AArch64
4179 if (src_reg == r31_sp) {
4180 MacroAssembler _masm(&cbuf);
4181 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
4182 __ mov(rscratch2, sp);
4183 src_reg = rscratch2;
4184 }
4185 MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4186 rscratch1, stlr);
4187 %}
4188
4189 enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
4190 {
4191 MacroAssembler _masm(&cbuf);
4192 FloatRegister src_reg = as_FloatRegister($src$$reg);
4193 __ fmovs(rscratch2, src_reg);
4194 }
4195 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4196 rscratch1, stlrw);
4197 %}
4198
4199 enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
4200 {
4201 MacroAssembler _masm(&cbuf);
4202 FloatRegister src_reg = as_FloatRegister($src$$reg);
4203 __ fmovd(rscratch2, src_reg);
4204 }
4205 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
4206 rscratch1, stlr);
4207 %}
4208
4209 // synchronized read/update encodings
4210
4211 enc_class aarch64_enc_ldaxr(iRegL dst, memory mem) %{
4212 MacroAssembler _masm(&cbuf);
4213 Register dst_reg = as_Register($dst$$reg);
4214 Register base = as_Register($mem$$base);
4215 int index = $mem$$index;
4216 int scale = $mem$$scale;
4217 int disp = $mem$$disp;
4218 if (index == -1) {
4219 if (disp != 0) {
4220 __ lea(rscratch1, Address(base, disp));
4221 __ ldaxr(dst_reg, rscratch1);
4222 } else {
4223 // TODO
4224 // should we ever get anything other than this case?
4225 __ ldaxr(dst_reg, base);
4226 }
4227 } else {
4228 Register index_reg = as_Register(index);
4229 if (disp == 0) {
4230 __ lea(rscratch1, Address(base, index_reg, Address::lsl(scale)));
4231 __ ldaxr(dst_reg, rscratch1);
4232 } else {
4233 __ lea(rscratch1, Address(base, disp));
4234 __ lea(rscratch1, Address(rscratch1, index_reg, Address::lsl(scale)));
4235 __ ldaxr(dst_reg, rscratch1);
4236 }
4237 }
4238 %}
4239
4240 enc_class aarch64_enc_stlxr(iRegLNoSp src, memory mem) %{
4241 MacroAssembler _masm(&cbuf);
4242 Register src_reg = as_Register($src$$reg);
4243 Register base = as_Register($mem$$base);
4244 int index = $mem$$index;
4245 int scale = $mem$$scale;
4246 int disp = $mem$$disp;
4247 if (index == -1) {
4248 if (disp != 0) {
4249 __ lea(rscratch2, Address(base, disp));
4250 __ stlxr(rscratch1, src_reg, rscratch2);
4251 } else {
4252 // TODO
4253 // should we ever get anything other than this case?
4254 __ stlxr(rscratch1, src_reg, base);
4255 }
4256 } else {
4257 Register index_reg = as_Register(index);
4258 if (disp == 0) {
4259 __ lea(rscratch2, Address(base, index_reg, Address::lsl(scale)));
4260 __ stlxr(rscratch1, src_reg, rscratch2);
4261 } else {
4262 __ lea(rscratch2, Address(base, disp));
4263 __ lea(rscratch2, Address(rscratch2, index_reg, Address::lsl(scale)));
4264 __ stlxr(rscratch1, src_reg, rscratch2);
4265 }
4266 }
4267 __ cmpw(rscratch1, zr);
4268 %}
4269
4270 enc_class aarch64_enc_cmpxchg(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
4271 MacroAssembler _masm(&cbuf);
4272 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
4273 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
4274 Assembler::xword, /*acquire*/ false, /*release*/ true,
4275 /*weak*/ false, noreg);
4276 %}
4277
4278 enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
4279 MacroAssembler _masm(&cbuf);
4280 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
4281 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
4282 Assembler::word, /*acquire*/ false, /*release*/ true,
4283 /*weak*/ false, noreg);
4284 %}
4285
4286
4287 // The only difference between aarch64_enc_cmpxchg and
4288 // aarch64_enc_cmpxchg_acq is that we use load-acquire in the
4289 // CompareAndSwap sequence to serve as a barrier on acquiring a
4290 // lock.
4291 enc_class aarch64_enc_cmpxchg_acq(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
4292 MacroAssembler _masm(&cbuf);
4293 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
4294 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
4295 Assembler::xword, /*acquire*/ true, /*release*/ true,
4296 /*weak*/ false, noreg);
4297 %}
4298
4299 enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
4300 MacroAssembler _masm(&cbuf);
4301 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
4302 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
4303 Assembler::word, /*acquire*/ true, /*release*/ true,
4304 /*weak*/ false, noreg);
4305 %}
4306
4307
4308 // auxiliary used for CompareAndSwapX to set result register
4309 enc_class aarch64_enc_cset_eq(iRegINoSp res) %{
4310 MacroAssembler _masm(&cbuf);
4311 Register res_reg = as_Register($res$$reg);
4312 __ cset(res_reg, Assembler::EQ);
4313 %}
4314
4315 // prefetch encodings
4316
4317 enc_class aarch64_enc_prefetchw(memory mem) %{
4318 MacroAssembler _masm(&cbuf);
4319 Register base = as_Register($mem$$base);
4320 int index = $mem$$index;
4321 int scale = $mem$$scale;
4322 int disp = $mem$$disp;
4323 if (index == -1) {
4324 __ prfm(Address(base, disp), PSTL1KEEP);
4325 } else {
4326 Register index_reg = as_Register(index);
4327 if (disp == 0) {
4328 __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
4329 } else {
4330 __ lea(rscratch1, Address(base, disp));
4331 __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
4332 }
4333 }
4334 %}
4335
4336 /// mov envcodings
4337
4338 enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
4339 MacroAssembler _masm(&cbuf);
4340 u_int32_t con = (u_int32_t)$src$$constant;
4341 Register dst_reg = as_Register($dst$$reg);
4342 if (con == 0) {
4343 __ movw(dst_reg, zr);
4344 } else {
4345 __ movw(dst_reg, con);
4346 }
4347 %}
4348
4349 enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
4350 MacroAssembler _masm(&cbuf);
4351 Register dst_reg = as_Register($dst$$reg);
4352 u_int64_t con = (u_int64_t)$src$$constant;
4353 if (con == 0) {
4354 __ mov(dst_reg, zr);
4355 } else {
4356 __ mov(dst_reg, con);
4357 }
4358 %}
4359
4360 enc_class aarch64_enc_mov_p(iRegP dst, immP src) %{
4361 MacroAssembler _masm(&cbuf);
4362 Register dst_reg = as_Register($dst$$reg);
4363 address con = (address)$src$$constant;
4364 if (con == NULL || con == (address)1) {
4365 ShouldNotReachHere();
4366 } else {
4367 relocInfo::relocType rtype = $src->constant_reloc();
4368 if (rtype == relocInfo::oop_type) {
4369 __ movoop(dst_reg, (jobject)con, /*immediate*/true);
4370 } else if (rtype == relocInfo::metadata_type) {
4371 __ mov_metadata(dst_reg, (Metadata*)con);
4372 } else {
4373 assert(rtype == relocInfo::none, "unexpected reloc type");
4374 if (con < (address)(uintptr_t)os::vm_page_size()) {
4375 __ mov(dst_reg, con);
4376 } else {
4377 unsigned long offset;
4378 __ adrp(dst_reg, con, offset);
4379 __ add(dst_reg, dst_reg, offset);
4380 }
4381 }
4382 }
4383 %}
4384
4385 enc_class aarch64_enc_mov_p0(iRegP dst, immP0 src) %{
4386 MacroAssembler _masm(&cbuf);
4387 Register dst_reg = as_Register($dst$$reg);
4388 __ mov(dst_reg, zr);
4389 %}
4390
4391 enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
4392 MacroAssembler _masm(&cbuf);
4393 Register dst_reg = as_Register($dst$$reg);
4394 __ mov(dst_reg, (u_int64_t)1);
4395 %}
4396
4397 enc_class aarch64_enc_mov_poll_page(iRegP dst, immPollPage src) %{
4398 MacroAssembler _masm(&cbuf);
4399 address page = (address)$src$$constant;
4400 Register dst_reg = as_Register($dst$$reg);
4401 unsigned long off;
4402 __ adrp(dst_reg, Address(page, relocInfo::poll_type), off);
4403 assert(off == 0, "assumed offset == 0");
4404 %}
4405
4406 enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
4407 MacroAssembler _masm(&cbuf);
4408 __ load_byte_map_base($dst$$Register);
4409 %}
4410
4411 enc_class aarch64_enc_mov_n(iRegN dst, immN src) %{
4412 MacroAssembler _masm(&cbuf);
4413 Register dst_reg = as_Register($dst$$reg);
4414 address con = (address)$src$$constant;
4415 if (con == NULL) {
4416 ShouldNotReachHere();
4417 } else {
4418 relocInfo::relocType rtype = $src->constant_reloc();
4419 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
4420 __ set_narrow_oop(dst_reg, (jobject)con);
4421 }
4422 %}
4423
4424 enc_class aarch64_enc_mov_n0(iRegN dst, immN0 src) %{
4425 MacroAssembler _masm(&cbuf);
4426 Register dst_reg = as_Register($dst$$reg);
4427 __ mov(dst_reg, zr);
4428 %}
4429
4430 enc_class aarch64_enc_mov_nk(iRegN dst, immNKlass src) %{
4431 MacroAssembler _masm(&cbuf);
4432 Register dst_reg = as_Register($dst$$reg);
4433 address con = (address)$src$$constant;
4434 if (con == NULL) {
4435 ShouldNotReachHere();
4436 } else {
4437 relocInfo::relocType rtype = $src->constant_reloc();
4438 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
4439 __ set_narrow_klass(dst_reg, (Klass *)con);
4440 }
4441 %}
4442
4443 // arithmetic encodings
4444
4445 enc_class aarch64_enc_addsubw_imm(iRegI dst, iRegI src1, immIAddSub src2) %{
4446 MacroAssembler _masm(&cbuf);
4447 Register dst_reg = as_Register($dst$$reg);
4448 Register src_reg = as_Register($src1$$reg);
4449 int32_t con = (int32_t)$src2$$constant;
4450 // add has primary == 0, subtract has primary == 1
4451 if ($primary) { con = -con; }
4452 if (con < 0) {
4453 __ subw(dst_reg, src_reg, -con);
4454 } else {
4455 __ addw(dst_reg, src_reg, con);
4456 }
4457 %}
4458
4459 enc_class aarch64_enc_addsub_imm(iRegL dst, iRegL src1, immLAddSub src2) %{
4460 MacroAssembler _masm(&cbuf);
4461 Register dst_reg = as_Register($dst$$reg);
4462 Register src_reg = as_Register($src1$$reg);
4463 int32_t con = (int32_t)$src2$$constant;
4464 // add has primary == 0, subtract has primary == 1
4465 if ($primary) { con = -con; }
4466 if (con < 0) {
4467 __ sub(dst_reg, src_reg, -con);
4468 } else {
4469 __ add(dst_reg, src_reg, con);
4470 }
4471 %}
4472
4473 enc_class aarch64_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
4474 MacroAssembler _masm(&cbuf);
4475 Register dst_reg = as_Register($dst$$reg);
4476 Register src1_reg = as_Register($src1$$reg);
4477 Register src2_reg = as_Register($src2$$reg);
4478 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false, rscratch1);
4479 %}
4480
4481 enc_class aarch64_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
4482 MacroAssembler _masm(&cbuf);
4483 Register dst_reg = as_Register($dst$$reg);
4484 Register src1_reg = as_Register($src1$$reg);
4485 Register src2_reg = as_Register($src2$$reg);
4486 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false, rscratch1);
4487 %}
4488
4489 enc_class aarch64_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
4490 MacroAssembler _masm(&cbuf);
4491 Register dst_reg = as_Register($dst$$reg);
4492 Register src1_reg = as_Register($src1$$reg);
4493 Register src2_reg = as_Register($src2$$reg);
4494 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true, rscratch1);
4495 %}
4496
4497 enc_class aarch64_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
4498 MacroAssembler _masm(&cbuf);
4499 Register dst_reg = as_Register($dst$$reg);
4500 Register src1_reg = as_Register($src1$$reg);
4501 Register src2_reg = as_Register($src2$$reg);
4502 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true, rscratch1);
4503 %}
4504
4505 // compare instruction encodings
4506
4507 enc_class aarch64_enc_cmpw(iRegI src1, iRegI src2) %{
4508 MacroAssembler _masm(&cbuf);
4509 Register reg1 = as_Register($src1$$reg);
4510 Register reg2 = as_Register($src2$$reg);
4511 __ cmpw(reg1, reg2);
4512 %}
4513
4514 enc_class aarch64_enc_cmpw_imm_addsub(iRegI src1, immIAddSub src2) %{
4515 MacroAssembler _masm(&cbuf);
4516 Register reg = as_Register($src1$$reg);
4517 int32_t val = $src2$$constant;
4518 if (val >= 0) {
4519 __ subsw(zr, reg, val);
4520 } else {
4521 __ addsw(zr, reg, -val);
4522 }
4523 %}
4524
4525 enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
4526 MacroAssembler _masm(&cbuf);
4527 Register reg1 = as_Register($src1$$reg);
4528 u_int32_t val = (u_int32_t)$src2$$constant;
4529 __ movw(rscratch1, val);
4530 __ cmpw(reg1, rscratch1);
4531 %}
4532
4533 enc_class aarch64_enc_cmp(iRegL src1, iRegL src2) %{
4534 MacroAssembler _masm(&cbuf);
4535 Register reg1 = as_Register($src1$$reg);
4536 Register reg2 = as_Register($src2$$reg);
4537 __ cmp(reg1, reg2);
4538 %}
4539
4540 enc_class aarch64_enc_cmp_imm_addsub(iRegL src1, immL12 src2) %{
4541 MacroAssembler _masm(&cbuf);
4542 Register reg = as_Register($src1$$reg);
4543 int64_t val = $src2$$constant;
4544 if (val >= 0) {
4545 __ subs(zr, reg, val);
4546 } else if (val != -val) {
4547 __ adds(zr, reg, -val);
4548 } else {
4549 // aargh, Long.MIN_VALUE is a special case
4550 __ orr(rscratch1, zr, (u_int64_t)val);
4551 __ subs(zr, reg, rscratch1);
4552 }
4553 %}
4554
4555 enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
4556 MacroAssembler _masm(&cbuf);
4557 Register reg1 = as_Register($src1$$reg);
4558 u_int64_t val = (u_int64_t)$src2$$constant;
4559 __ mov(rscratch1, val);
4560 __ cmp(reg1, rscratch1);
4561 %}
4562
4563 enc_class aarch64_enc_cmpp(iRegP src1, iRegP src2) %{
4564 MacroAssembler _masm(&cbuf);
4565 Register reg1 = as_Register($src1$$reg);
4566 Register reg2 = as_Register($src2$$reg);
4567 __ cmp(reg1, reg2);
4568 %}
4569
4570 enc_class aarch64_enc_cmpn(iRegN src1, iRegN src2) %{
4571 MacroAssembler _masm(&cbuf);
4572 Register reg1 = as_Register($src1$$reg);
4573 Register reg2 = as_Register($src2$$reg);
4574 __ cmpw(reg1, reg2);
4575 %}
4576
4577 enc_class aarch64_enc_testp(iRegP src) %{
4578 MacroAssembler _masm(&cbuf);
4579 Register reg = as_Register($src$$reg);
4580 __ cmp(reg, zr);
4581 %}
4582
4583 enc_class aarch64_enc_testn(iRegN src) %{
4584 MacroAssembler _masm(&cbuf);
4585 Register reg = as_Register($src$$reg);
4586 __ cmpw(reg, zr);
4587 %}
4588
4589 enc_class aarch64_enc_b(label lbl) %{
4590 MacroAssembler _masm(&cbuf);
4591 Label *L = $lbl$$label;
4592 __ b(*L);
4593 %}
4594
4595 enc_class aarch64_enc_br_con(cmpOp cmp, label lbl) %{
4596 MacroAssembler _masm(&cbuf);
4597 Label *L = $lbl$$label;
4598 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
4599 %}
4600
4601 enc_class aarch64_enc_br_conU(cmpOpU cmp, label lbl) %{
4602 MacroAssembler _masm(&cbuf);
4603 Label *L = $lbl$$label;
4604 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
4605 %}
4606
4607 enc_class aarch64_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result)
4608 %{
4609 Register sub_reg = as_Register($sub$$reg);
4610 Register super_reg = as_Register($super$$reg);
4611 Register temp_reg = as_Register($temp$$reg);
4612 Register result_reg = as_Register($result$$reg);
4613
4614 Label miss;
4615 MacroAssembler _masm(&cbuf);
4616 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
4617 NULL, &miss,
4618 /*set_cond_codes:*/ true);
4619 if ($primary) {
4620 __ mov(result_reg, zr);
4621 }
4622 __ bind(miss);
4623 %}
4624
4625 enc_class aarch64_enc_java_static_call(method meth) %{
4626 MacroAssembler _masm(&cbuf);
4627
4628 address addr = (address)$meth$$method;
4629 address call;
4630 if (!_method) {
4631 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
4632 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
4633 } else {
4634 int method_index = resolved_method_index(cbuf);
4635 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
4636 : static_call_Relocation::spec(method_index);
4637 call = __ trampoline_call(Address(addr, rspec), &cbuf);
4638
4639 // Emit stub for static call
4640 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
4641 if (stub == NULL) {
4642 ciEnv::current()->record_failure("CodeCache is full");
4643 return;
4644 }
4645 }
4646 if (call == NULL) {
4647 ciEnv::current()->record_failure("CodeCache is full");
4648 return;
4649 }
4650 %}
4651
4652 enc_class aarch64_enc_java_dynamic_call(method meth) %{
4653 MacroAssembler _masm(&cbuf);
4654 int method_index = resolved_method_index(cbuf);
4655 address call = __ ic_call((address)$meth$$method, method_index);
4656 if (call == NULL) {
4657 ciEnv::current()->record_failure("CodeCache is full");
4658 return;
4659 }
4660 %}
4661
4662 enc_class aarch64_enc_call_epilog() %{
4663 MacroAssembler _masm(&cbuf);
4664 if (VerifyStackAtCalls) {
4665 // Check that stack depth is unchanged: find majik cookie on stack
4666 __ call_Unimplemented();
4667 }
4668 %}
4669
4670 enc_class aarch64_enc_java_to_runtime(method meth) %{
4671 MacroAssembler _masm(&cbuf);
4672
4673 // some calls to generated routines (arraycopy code) are scheduled
4674 // by C2 as runtime calls. if so we can call them using a br (they
4675 // will be in a reachable segment) otherwise we have to use a blrt
4676 // which loads the absolute address into a register.
4677 address entry = (address)$meth$$method;
4678 CodeBlob *cb = CodeCache::find_blob(entry);
4679 if (cb) {
4680 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
4681 if (call == NULL) {
4682 ciEnv::current()->record_failure("CodeCache is full");
4683 return;
4684 }
4685 } else {
4686 int gpcnt;
4687 int fpcnt;
4688 int rtype;
4689 getCallInfo(tf(), gpcnt, fpcnt, rtype);
4690 Label retaddr;
4691 __ adr(rscratch2, retaddr);
4692 __ lea(rscratch1, RuntimeAddress(entry));
4693 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
4694 __ stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)));
4695 __ blrt(rscratch1, gpcnt, fpcnt, rtype);
4696 __ bind(retaddr);
4697 __ add(sp, sp, 2 * wordSize);
4698 }
4699 %}
4700
4701 enc_class aarch64_enc_rethrow() %{
4702 MacroAssembler _masm(&cbuf);
4703 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
4704 %}
4705
4706 enc_class aarch64_enc_ret() %{
4707 MacroAssembler _masm(&cbuf);
4708 __ ret(lr);
4709 %}
4710
4711 enc_class aarch64_enc_tail_call(iRegP jump_target) %{
4712 MacroAssembler _masm(&cbuf);
4713 Register target_reg = as_Register($jump_target$$reg);
4714 __ br(target_reg);
4715 %}
4716
4717 enc_class aarch64_enc_tail_jmp(iRegP jump_target) %{
4718 MacroAssembler _masm(&cbuf);
4719 Register target_reg = as_Register($jump_target$$reg);
4720 // exception oop should be in r0
4721 // ret addr has been popped into lr
4722 // callee expects it in r3
4723 __ mov(r3, lr);
4724 __ br(target_reg);
4725 %}
4726
4727 enc_class aarch64_enc_fast_lock(iRegP object, iRegP box, iRegP tmp, iRegP tmp2) %{
4728 MacroAssembler _masm(&cbuf);
4729 Register oop = as_Register($object$$reg);
4730 Register box = as_Register($box$$reg);
4731 Register disp_hdr = as_Register($tmp$$reg);
4732 Register tmp = as_Register($tmp2$$reg);
4733 Label cont;
4734 Label object_has_monitor;
4735 Label cas_failed;
4736
4737 assert_different_registers(oop, box, tmp, disp_hdr);
4738
4739 // Load markOop from object into displaced_header.
4740 __ ldr(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
4741
4742 // Always do locking in runtime.
4743 if (EmitSync & 0x01) {
4744 __ cmp(oop, zr);
4745 return;
4746 }
4747
4748 if (UseBiasedLocking && !UseOptoBiasInlining) {
4749 __ biased_locking_enter(box, oop, disp_hdr, tmp, true, cont);
4750 }
4751
4752 // Handle existing monitor
4753 if ((EmitSync & 0x02) == 0) {
4754 // we can use AArch64's bit test and branch here but
4755 // markoopDesc does not define a bit index just the bit value
4756 // so assert in case the bit pos changes
4757 # define __monitor_value_log2 1
4758 assert(markOopDesc::monitor_value == (1 << __monitor_value_log2), "incorrect bit position");
4759 __ tbnz(disp_hdr, __monitor_value_log2, object_has_monitor);
4760 # undef __monitor_value_log2
4761 }
4762
4763 // Set displaced_header to be (markOop of object | UNLOCK_VALUE).
4764 __ orr(disp_hdr, disp_hdr, markOopDesc::unlocked_value);
4765
4766 // Load Compare Value application register.
4767
4768 // Initialize the box. (Must happen before we update the object mark!)
4769 __ str(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
4770
4771 // Compare object markOop with mark and if equal exchange scratch1
4772 // with object markOop.
4773 if (UseLSE) {
4774 __ mov(tmp, disp_hdr);
4775 __ casal(Assembler::xword, tmp, box, oop);
4776 __ cmp(tmp, disp_hdr);
4777 __ br(Assembler::EQ, cont);
4778 } else {
4779 Label retry_load;
4780 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
4781 __ prfm(Address(oop), PSTL1STRM);
4782 __ bind(retry_load);
4783 __ ldaxr(tmp, oop);
4784 __ cmp(tmp, disp_hdr);
4785 __ br(Assembler::NE, cas_failed);
4786 // use stlxr to ensure update is immediately visible
4787 __ stlxr(tmp, box, oop);
4788 __ cbzw(tmp, cont);
4789 __ b(retry_load);
4790 }
4791
4792 // Formerly:
4793 // __ cmpxchgptr(/*oldv=*/disp_hdr,
4794 // /*newv=*/box,
4795 // /*addr=*/oop,
4796 // /*tmp=*/tmp,
4797 // cont,
4798 // /*fail*/NULL);
4799
4800 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
4801
4802 // If the compare-and-exchange succeeded, then we found an unlocked
4803 // object, will have now locked it will continue at label cont
4804
4805 __ bind(cas_failed);
4806 // We did not see an unlocked object so try the fast recursive case.
4807
4808 // Check if the owner is self by comparing the value in the
4809 // markOop of object (disp_hdr) with the stack pointer.
4810 __ mov(rscratch1, sp);
4811 __ sub(disp_hdr, disp_hdr, rscratch1);
4812 __ mov(tmp, (address) (~(os::vm_page_size()-1) | markOopDesc::lock_mask_in_place));
4813 // If condition is true we are cont and hence we can store 0 as the
4814 // displaced header in the box, which indicates that it is a recursive lock.
4815 __ ands(tmp/*==0?*/, disp_hdr, tmp);
4816 __ str(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
4817
4818 // Handle existing monitor.
4819 if ((EmitSync & 0x02) == 0) {
4820 __ b(cont);
4821
4822 __ bind(object_has_monitor);
4823 // The object's monitor m is unlocked iff m->owner == NULL,
4824 // otherwise m->owner may contain a thread or a stack address.
4825 //
4826 // Try to CAS m->owner from NULL to current thread.
4827 __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value));
4828 __ mov(disp_hdr, zr);
4829
4830 if (UseLSE) {
4831 __ mov(rscratch1, disp_hdr);
4832 __ casal(Assembler::xword, rscratch1, rthread, tmp);
4833 __ cmp(rscratch1, disp_hdr);
4834 } else {
4835 Label retry_load, fail;
4836 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
4837 __ prfm(Address(tmp), PSTL1STRM);
4838 __ bind(retry_load);
4839 __ ldaxr(rscratch1, tmp);
4840 __ cmp(disp_hdr, rscratch1);
4841 __ br(Assembler::NE, fail);
4842 // use stlxr to ensure update is immediately visible
4843 __ stlxr(rscratch1, rthread, tmp);
4844 __ cbnzw(rscratch1, retry_load);
4845 __ bind(fail);
4846 }
4847
4848 // Label next;
4849 // __ cmpxchgptr(/*oldv=*/disp_hdr,
4850 // /*newv=*/rthread,
4851 // /*addr=*/tmp,
4852 // /*tmp=*/rscratch1,
4853 // /*succeed*/next,
4854 // /*fail*/NULL);
4855 // __ bind(next);
4856
4857 // store a non-null value into the box.
4858 __ str(box, Address(box, BasicLock::displaced_header_offset_in_bytes()));
4859
4860 // PPC port checks the following invariants
4861 // #ifdef ASSERT
4862 // bne(flag, cont);
4863 // We have acquired the monitor, check some invariants.
4864 // addw(/*monitor=*/tmp, tmp, -ObjectMonitor::owner_offset_in_bytes());
4865 // Invariant 1: _recursions should be 0.
4866 // assert(ObjectMonitor::recursions_size_in_bytes() == 8, "unexpected size");
4867 // assert_mem8_is_zero(ObjectMonitor::recursions_offset_in_bytes(), tmp,
4868 // "monitor->_recursions should be 0", -1);
4869 // Invariant 2: OwnerIsThread shouldn't be 0.
4870 // assert(ObjectMonitor::OwnerIsThread_size_in_bytes() == 4, "unexpected size");
4871 //assert_mem4_isnot_zero(ObjectMonitor::OwnerIsThread_offset_in_bytes(), tmp,
4872 // "monitor->OwnerIsThread shouldn't be 0", -1);
4873 // #endif
4874 }
4875
4876 __ bind(cont);
4877 // flag == EQ indicates success
4878 // flag == NE indicates failure
4879
4880 %}
4881
4882 // TODO
4883 // reimplement this with custom cmpxchgptr code
4884 // which avoids some of the unnecessary branching
4885 enc_class aarch64_enc_fast_unlock(iRegP object, iRegP box, iRegP tmp, iRegP tmp2) %{
4886 MacroAssembler _masm(&cbuf);
4887 Register oop = as_Register($object$$reg);
4888 Register box = as_Register($box$$reg);
4889 Register disp_hdr = as_Register($tmp$$reg);
4890 Register tmp = as_Register($tmp2$$reg);
4891 Label cont;
4892 Label object_has_monitor;
4893 Label cas_failed;
4894
4895 assert_different_registers(oop, box, tmp, disp_hdr);
4896
4897 // Always do locking in runtime.
4898 if (EmitSync & 0x01) {
4899 __ cmp(oop, zr); // Oop can't be 0 here => always false.
4900 return;
4901 }
4902
4903 if (UseBiasedLocking && !UseOptoBiasInlining) {
4904 __ biased_locking_exit(oop, tmp, cont);
4905 }
4906
4907 // Find the lock address and load the displaced header from the stack.
4908 __ ldr(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
4909
4910 // If the displaced header is 0, we have a recursive unlock.
4911 __ cmp(disp_hdr, zr);
4912 __ br(Assembler::EQ, cont);
4913
4914
4915 // Handle existing monitor.
4916 if ((EmitSync & 0x02) == 0) {
4917 __ ldr(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
4918 __ tbnz(disp_hdr, exact_log2(markOopDesc::monitor_value), object_has_monitor);
4919 }
4920
4921 // Check if it is still a light weight lock, this is is true if we
4922 // see the stack address of the basicLock in the markOop of the
4923 // object.
4924
4925 if (UseLSE) {
4926 __ mov(tmp, box);
4927 __ casl(Assembler::xword, tmp, disp_hdr, oop);
4928 __ cmp(tmp, box);
4929 } else {
4930 Label retry_load;
4931 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
4932 __ prfm(Address(oop), PSTL1STRM);
4933 __ bind(retry_load);
4934 __ ldxr(tmp, oop);
4935 __ cmp(box, tmp);
4936 __ br(Assembler::NE, cas_failed);
4937 // use stlxr to ensure update is immediately visible
4938 __ stlxr(tmp, disp_hdr, oop);
4939 __ cbzw(tmp, cont);
4940 __ b(retry_load);
4941 }
4942
4943 // __ cmpxchgptr(/*compare_value=*/box,
4944 // /*exchange_value=*/disp_hdr,
4945 // /*where=*/oop,
4946 // /*result=*/tmp,
4947 // cont,
4948 // /*cas_failed*/NULL);
4949 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
4950
4951 __ bind(cas_failed);
4952
4953 // Handle existing monitor.
4954 if ((EmitSync & 0x02) == 0) {
4955 __ b(cont);
4956
4957 __ bind(object_has_monitor);
4958 __ add(tmp, tmp, -markOopDesc::monitor_value); // monitor
4959 __ ldr(rscratch1, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
4960 __ ldr(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
4961 __ eor(rscratch1, rscratch1, rthread); // Will be 0 if we are the owner.
4962 __ orr(rscratch1, rscratch1, disp_hdr); // Will be 0 if there are 0 recursions
4963 __ cmp(rscratch1, zr);
4964 __ br(Assembler::NE, cont);
4965
4966 __ ldr(rscratch1, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
4967 __ ldr(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
4968 __ orr(rscratch1, rscratch1, disp_hdr); // Will be 0 if both are 0.
4969 __ cmp(rscratch1, zr);
4970 __ cbnz(rscratch1, cont);
4971 // need a release store here
4972 __ lea(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
4973 __ stlr(rscratch1, tmp); // rscratch1 is zero
4974 }
4975
4976 __ bind(cont);
4977 // flag == EQ indicates success
4978 // flag == NE indicates failure
4979 %}
4980
4981 %}
4982
4983 //----------FRAME--------------------------------------------------------------
4984 // Definition of frame structure and management information.
4985 //
4986 // S T A C K L A Y O U T Allocators stack-slot number
4987 // | (to get allocators register number
4988 // G Owned by | | v add OptoReg::stack0())
4989 // r CALLER | |
4990 // o | +--------+ pad to even-align allocators stack-slot
4991 // w V | pad0 | numbers; owned by CALLER
4992 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4993 // h ^ | in | 5
4994 // | | args | 4 Holes in incoming args owned by SELF
4995 // | | | | 3
4996 // | | +--------+
4997 // V | | old out| Empty on Intel, window on Sparc
4998 // | old |preserve| Must be even aligned.
4999 // | SP-+--------+----> Matcher::_old_SP, even aligned
5000 // | | in | 3 area for Intel ret address
5001 // Owned by |preserve| Empty on Sparc.
5002 // SELF +--------+
5003 // | | pad2 | 2 pad to align old SP
5004 // | +--------+ 1
5005 // | | locks | 0
5006 // | +--------+----> OptoReg::stack0(), even aligned
5007 // | | pad1 | 11 pad to align new SP
5008 // | +--------+
5009 // | | | 10
5010 // | | spills | 9 spills
5011 // V | | 8 (pad0 slot for callee)
5012 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
5013 // ^ | out | 7
5014 // | | args | 6 Holes in outgoing args owned by CALLEE
5015 // Owned by +--------+
5016 // CALLEE | new out| 6 Empty on Intel, window on Sparc
5017 // | new |preserve| Must be even-aligned.
5018 // | SP-+--------+----> Matcher::_new_SP, even aligned
5019 // | | |
5020 //
5021 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
5022 // known from SELF's arguments and the Java calling convention.
5023 // Region 6-7 is determined per call site.
5024 // Note 2: If the calling convention leaves holes in the incoming argument
5025 // area, those holes are owned by SELF. Holes in the outgoing area
5026 // are owned by the CALLEE. Holes should not be nessecary in the
5027 // incoming area, as the Java calling convention is completely under
5028 // the control of the AD file. Doubles can be sorted and packed to
5029 // avoid holes. Holes in the outgoing arguments may be nessecary for
5030 // varargs C calling conventions.
5031 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
5032 // even aligned with pad0 as needed.
5033 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
5034 // (the latter is true on Intel but is it false on AArch64?)
5035 // region 6-11 is even aligned; it may be padded out more so that
5036 // the region from SP to FP meets the minimum stack alignment.
5037 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
5038 // alignment. Region 11, pad1, may be dynamically extended so that
5039 // SP meets the minimum alignment.
5040
5041 frame %{
5042 // What direction does stack grow in (assumed to be same for C & Java)
5043 stack_direction(TOWARDS_LOW);
5044
5045 // These three registers define part of the calling convention
5046 // between compiled code and the interpreter.
5047
5048 // Inline Cache Register or methodOop for I2C.
5049 inline_cache_reg(R12);
5050
5051 // Method Oop Register when calling interpreter.
5052 interpreter_method_oop_reg(R12);
5053
5054 // Number of stack slots consumed by locking an object
5055 sync_stack_slots(2);
5056
5057 // Compiled code's Frame Pointer
5058 frame_pointer(R31);
5059
5060 // Interpreter stores its frame pointer in a register which is
5061 // stored to the stack by I2CAdaptors.
5062 // I2CAdaptors convert from interpreted java to compiled java.
5063 interpreter_frame_pointer(R29);
5064
5065 // Stack alignment requirement
5066 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
5067
5068 // Number of stack slots between incoming argument block and the start of
5069 // a new frame. The PROLOG must add this many slots to the stack. The
5070 // EPILOG must remove this many slots. aarch64 needs two slots for
5071 // return address and fp.
5072 // TODO think this is correct but check
5073 in_preserve_stack_slots(4);
5074
5075 // Number of outgoing stack slots killed above the out_preserve_stack_slots
5076 // for calls to C. Supports the var-args backing area for register parms.
5077 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
5078
5079 // The after-PROLOG location of the return address. Location of
5080 // return address specifies a type (REG or STACK) and a number
5081 // representing the register number (i.e. - use a register name) or
5082 // stack slot.
5083 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
5084 // Otherwise, it is above the locks and verification slot and alignment word
5085 // TODO this may well be correct but need to check why that - 2 is there
5086 // ppc port uses 0 but we definitely need to allow for fixed_slots
5087 // which folds in the space used for monitors
5088 return_addr(STACK - 2 +
5089 round_to((Compile::current()->in_preserve_stack_slots() +
5090 Compile::current()->fixed_slots()),
5091 stack_alignment_in_slots()));
5092
5093 // Body of function which returns an integer array locating
5094 // arguments either in registers or in stack slots. Passed an array
5095 // of ideal registers called "sig" and a "length" count. Stack-slot
5096 // offsets are based on outgoing arguments, i.e. a CALLER setting up
5097 // arguments for a CALLEE. Incoming stack arguments are
5098 // automatically biased by the preserve_stack_slots field above.
5099
5100 calling_convention
5101 %{
5102 // No difference between ingoing/outgoing just pass false
5103 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
5104 %}
5105
5106 c_calling_convention
5107 %{
5108 // This is obviously always outgoing
5109 (void) SharedRuntime::c_calling_convention(sig_bt, regs, NULL, length);
5110 %}
5111
5112 // Location of compiled Java return values. Same as C for now.
5113 return_value
5114 %{
5115 // TODO do we allow ideal_reg == Op_RegN???
5116 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
5117 "only return normal values");
5118
5119 static const int lo[Op_RegL + 1] = { // enum name
5120 0, // Op_Node
5121 0, // Op_Set
5122 R0_num, // Op_RegN
5123 R0_num, // Op_RegI
5124 R0_num, // Op_RegP
5125 V0_num, // Op_RegF
5126 V0_num, // Op_RegD
5127 R0_num // Op_RegL
5128 };
5129
5130 static const int hi[Op_RegL + 1] = { // enum name
5131 0, // Op_Node
5132 0, // Op_Set
5133 OptoReg::Bad, // Op_RegN
5134 OptoReg::Bad, // Op_RegI
5135 R0_H_num, // Op_RegP
5136 OptoReg::Bad, // Op_RegF
5137 V0_H_num, // Op_RegD
5138 R0_H_num // Op_RegL
5139 };
5140
5141 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
5142 %}
5143 %}
5144
5145 //----------ATTRIBUTES---------------------------------------------------------
5146 //----------Operand Attributes-------------------------------------------------
5147 op_attrib op_cost(1); // Required cost attribute
5148
5149 //----------Instruction Attributes---------------------------------------------
5150 ins_attrib ins_cost(INSN_COST); // Required cost attribute
5151 ins_attrib ins_size(32); // Required size attribute (in bits)
5152 ins_attrib ins_short_branch(0); // Required flag: is this instruction
5153 // a non-matching short branch variant
5154 // of some long branch?
5155 ins_attrib ins_alignment(4); // Required alignment attribute (must
5156 // be a power of 2) specifies the
5157 // alignment that some part of the
5158 // instruction (not necessarily the
5159 // start) requires. If > 1, a
5160 // compute_padding() function must be
5161 // provided for the instruction
5162
5163 //----------OPERANDS-----------------------------------------------------------
5164 // Operand definitions must precede instruction definitions for correct parsing
5165 // in the ADLC because operands constitute user defined types which are used in
5166 // instruction definitions.
5167
5168 //----------Simple Operands----------------------------------------------------
5169
5170 // Integer operands 32 bit
5171 // 32 bit immediate
5172 operand immI()
5173 %{
5174 match(ConI);
5175
5176 op_cost(0);
5177 format %{ %}
5178 interface(CONST_INTER);
5179 %}
5180
5181 // 32 bit zero
5182 operand immI0()
5183 %{
5184 predicate(n->get_int() == 0);
5185 match(ConI);
5186
5187 op_cost(0);
5188 format %{ %}
5189 interface(CONST_INTER);
5190 %}
5191
5192 // 32 bit unit increment
5193 operand immI_1()
5194 %{
5195 predicate(n->get_int() == 1);
5196 match(ConI);
5197
5198 op_cost(0);
5199 format %{ %}
5200 interface(CONST_INTER);
5201 %}
5202
5203 // 32 bit unit decrement
5204 operand immI_M1()
5205 %{
5206 predicate(n->get_int() == -1);
5207 match(ConI);
5208
5209 op_cost(0);
5210 format %{ %}
5211 interface(CONST_INTER);
5212 %}
5213
5214 operand immI_le_4()
5215 %{
5216 predicate(n->get_int() <= 4);
5217 match(ConI);
5218
5219 op_cost(0);
5220 format %{ %}
5221 interface(CONST_INTER);
5222 %}
5223
5224 operand immI_31()
5225 %{
5226 predicate(n->get_int() == 31);
5227 match(ConI);
5228
5229 op_cost(0);
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5233
5234 operand immI_8()
5235 %{
5236 predicate(n->get_int() == 8);
5237 match(ConI);
5238
5239 op_cost(0);
5240 format %{ %}
5241 interface(CONST_INTER);
5242 %}
5243
5244 operand immI_16()
5245 %{
5246 predicate(n->get_int() == 16);
5247 match(ConI);
5248
5249 op_cost(0);
5250 format %{ %}
5251 interface(CONST_INTER);
5252 %}
5253
5254 operand immI_24()
5255 %{
5256 predicate(n->get_int() == 24);
5257 match(ConI);
5258
5259 op_cost(0);
5260 format %{ %}
5261 interface(CONST_INTER);
5262 %}
5263
5264 operand immI_32()
5265 %{
5266 predicate(n->get_int() == 32);
5267 match(ConI);
5268
5269 op_cost(0);
5270 format %{ %}
5271 interface(CONST_INTER);
5272 %}
5273
5274 operand immI_48()
5275 %{
5276 predicate(n->get_int() == 48);
5277 match(ConI);
5278
5279 op_cost(0);
5280 format %{ %}
5281 interface(CONST_INTER);
5282 %}
5283
5284 operand immI_56()
5285 %{
5286 predicate(n->get_int() == 56);
5287 match(ConI);
5288
5289 op_cost(0);
5290 format %{ %}
5291 interface(CONST_INTER);
5292 %}
5293
5294 operand immI_64()
5295 %{
5296 predicate(n->get_int() == 64);
5297 match(ConI);
5298
5299 op_cost(0);
5300 format %{ %}
5301 interface(CONST_INTER);
5302 %}
5303
5304 operand immI_255()
5305 %{
5306 predicate(n->get_int() == 255);
5307 match(ConI);
5308
5309 op_cost(0);
5310 format %{ %}
5311 interface(CONST_INTER);
5312 %}
5313
5314 operand immI_65535()
5315 %{
5316 predicate(n->get_int() == 65535);
5317 match(ConI);
5318
5319 op_cost(0);
5320 format %{ %}
5321 interface(CONST_INTER);
5322 %}
5323
5324 operand immL_63()
5325 %{
5326 predicate(n->get_int() == 63);
5327 match(ConI);
5328
5329 op_cost(0);
5330 format %{ %}
5331 interface(CONST_INTER);
5332 %}
5333
5334 operand immL_255()
5335 %{
5336 predicate(n->get_int() == 255);
5337 match(ConI);
5338
5339 op_cost(0);
5340 format %{ %}
5341 interface(CONST_INTER);
5342 %}
5343
5344 operand immL_65535()
5345 %{
5346 predicate(n->get_long() == 65535L);
5347 match(ConL);
5348
5349 op_cost(0);
5350 format %{ %}
5351 interface(CONST_INTER);
5352 %}
5353
5354 operand immL_4294967295()
5355 %{
5356 predicate(n->get_long() == 4294967295L);
5357 match(ConL);
5358
5359 op_cost(0);
5360 format %{ %}
5361 interface(CONST_INTER);
5362 %}
5363
5364 operand immL_bitmask()
5365 %{
5366 predicate(((n->get_long() & 0xc000000000000000l) == 0)
5367 && is_power_of_2(n->get_long() + 1));
5368 match(ConL);
5369
5370 op_cost(0);
5371 format %{ %}
5372 interface(CONST_INTER);
5373 %}
5374
5375 operand immI_bitmask()
5376 %{
5377 predicate(((n->get_int() & 0xc0000000) == 0)
5378 && is_power_of_2(n->get_int() + 1));
5379 match(ConI);
5380
5381 op_cost(0);
5382 format %{ %}
5383 interface(CONST_INTER);
5384 %}
5385
5386 // Scale values for scaled offset addressing modes (up to long but not quad)
5387 operand immIScale()
5388 %{
5389 predicate(0 <= n->get_int() && (n->get_int() <= 3));
5390 match(ConI);
5391
5392 op_cost(0);
5393 format %{ %}
5394 interface(CONST_INTER);
5395 %}
5396
5397 // 26 bit signed offset -- for pc-relative branches
5398 operand immI26()
5399 %{
5400 predicate(((-(1 << 25)) <= n->get_int()) && (n->get_int() < (1 << 25)));
5401 match(ConI);
5402
5403 op_cost(0);
5404 format %{ %}
5405 interface(CONST_INTER);
5406 %}
5407
5408 // 19 bit signed offset -- for pc-relative loads
5409 operand immI19()
5410 %{
5411 predicate(((-(1 << 18)) <= n->get_int()) && (n->get_int() < (1 << 18)));
5412 match(ConI);
5413
5414 op_cost(0);
5415 format %{ %}
5416 interface(CONST_INTER);
5417 %}
5418
5419 // 12 bit unsigned offset -- for base plus immediate loads
5420 operand immIU12()
5421 %{
5422 predicate((0 <= n->get_int()) && (n->get_int() < (1 << 12)));
5423 match(ConI);
5424
5425 op_cost(0);
5426 format %{ %}
5427 interface(CONST_INTER);
5428 %}
5429
5430 operand immLU12()
5431 %{
5432 predicate((0 <= n->get_long()) && (n->get_long() < (1 << 12)));
5433 match(ConL);
5434
5435 op_cost(0);
5436 format %{ %}
5437 interface(CONST_INTER);
5438 %}
5439
5440 // Offset for scaled or unscaled immediate loads and stores
5441 operand immIOffset()
5442 %{
5443 predicate(Address::offset_ok_for_immed(n->get_int()));
5444 match(ConI);
5445
5446 op_cost(0);
5447 format %{ %}
5448 interface(CONST_INTER);
5449 %}
5450
5451 operand immIOffset4()
5452 %{
5453 predicate(Address::offset_ok_for_immed(n->get_int(), 2));
5454 match(ConI);
5455
5456 op_cost(0);
5457 format %{ %}
5458 interface(CONST_INTER);
5459 %}
5460
5461 operand immIOffset8()
5462 %{
5463 predicate(Address::offset_ok_for_immed(n->get_int(), 3));
5464 match(ConI);
5465
5466 op_cost(0);
5467 format %{ %}
5468 interface(CONST_INTER);
5469 %}
5470
5471 operand immIOffset16()
5472 %{
5473 predicate(Address::offset_ok_for_immed(n->get_int(), 4));
5474 match(ConI);
5475
5476 op_cost(0);
5477 format %{ %}
5478 interface(CONST_INTER);
5479 %}
5480
5481 operand immLoffset()
5482 %{
5483 predicate(Address::offset_ok_for_immed(n->get_long()));
5484 match(ConL);
5485
5486 op_cost(0);
5487 format %{ %}
5488 interface(CONST_INTER);
5489 %}
5490
5491 operand immLoffset4()
5492 %{
5493 predicate(Address::offset_ok_for_immed(n->get_long(), 2));
5494 match(ConL);
5495
5496 op_cost(0);
5497 format %{ %}
5498 interface(CONST_INTER);
5499 %}
5500
5501 operand immLoffset8()
5502 %{
5503 predicate(Address::offset_ok_for_immed(n->get_long(), 3));
5504 match(ConL);
5505
5506 op_cost(0);
5507 format %{ %}
5508 interface(CONST_INTER);
5509 %}
5510
5511 operand immLoffset16()
5512 %{
5513 predicate(Address::offset_ok_for_immed(n->get_long(), 4));
5514 match(ConL);
5515
5516 op_cost(0);
5517 format %{ %}
5518 interface(CONST_INTER);
5519 %}
5520
5521 // 32 bit integer valid for add sub immediate
5522 operand immIAddSub()
5523 %{
5524 predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int()));
5525 match(ConI);
5526 op_cost(0);
5527 format %{ %}
5528 interface(CONST_INTER);
5529 %}
5530
5531 // 32 bit unsigned integer valid for logical immediate
5532 // TODO -- check this is right when e.g the mask is 0x80000000
5533 operand immILog()
5534 %{
5535 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (unsigned long)n->get_int()));
5536 match(ConI);
5537
5538 op_cost(0);
5539 format %{ %}
5540 interface(CONST_INTER);
5541 %}
5542
5543 // Integer operands 64 bit
5544 // 64 bit immediate
5545 operand immL()
5546 %{
5547 match(ConL);
5548
5549 op_cost(0);
5550 format %{ %}
5551 interface(CONST_INTER);
5552 %}
5553
5554 // 64 bit zero
5555 operand immL0()
5556 %{
5557 predicate(n->get_long() == 0);
5558 match(ConL);
5559
5560 op_cost(0);
5561 format %{ %}
5562 interface(CONST_INTER);
5563 %}
5564
5565 // 64 bit unit increment
5566 operand immL_1()
5567 %{
5568 predicate(n->get_long() == 1);
5569 match(ConL);
5570
5571 op_cost(0);
5572 format %{ %}
5573 interface(CONST_INTER);
5574 %}
5575
5576 // 64 bit unit decrement
5577 operand immL_M1()
5578 %{
5579 predicate(n->get_long() == -1);
5580 match(ConL);
5581
5582 op_cost(0);
5583 format %{ %}
5584 interface(CONST_INTER);
5585 %}
5586
5587 // 32 bit offset of pc in thread anchor
5588
5589 operand immL_pc_off()
5590 %{
5591 predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
5592 in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
5593 match(ConL);
5594
5595 op_cost(0);
5596 format %{ %}
5597 interface(CONST_INTER);
5598 %}
5599
5600 // 64 bit integer valid for add sub immediate
5601 operand immLAddSub()
5602 %{
5603 predicate(Assembler::operand_valid_for_add_sub_immediate(n->get_long()));
5604 match(ConL);
5605 op_cost(0);
5606 format %{ %}
5607 interface(CONST_INTER);
5608 %}
5609
5610 // 64 bit integer valid for logical immediate
5611 operand immLLog()
5612 %{
5613 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (unsigned long)n->get_long()));
5614 match(ConL);
5615 op_cost(0);
5616 format %{ %}
5617 interface(CONST_INTER);
5618 %}
5619
5620 // Long Immediate: low 32-bit mask
5621 operand immL_32bits()
5622 %{
5623 predicate(n->get_long() == 0xFFFFFFFFL);
5624 match(ConL);
5625 op_cost(0);
5626 format %{ %}
5627 interface(CONST_INTER);
5628 %}
5629
5630 // Pointer operands
5631 // Pointer Immediate
5632 operand immP()
5633 %{
5634 match(ConP);
5635
5636 op_cost(0);
5637 format %{ %}
5638 interface(CONST_INTER);
5639 %}
5640
5641 // NULL Pointer Immediate
5642 operand immP0()
5643 %{
5644 predicate(n->get_ptr() == 0);
5645 match(ConP);
5646
5647 op_cost(0);
5648 format %{ %}
5649 interface(CONST_INTER);
5650 %}
5651
5652 // Pointer Immediate One
5653 // this is used in object initialization (initial object header)
5654 operand immP_1()
5655 %{
5656 predicate(n->get_ptr() == 1);
5657 match(ConP);
5658
5659 op_cost(0);
5660 format %{ %}
5661 interface(CONST_INTER);
5662 %}
5663
5664 // Polling Page Pointer Immediate
5665 operand immPollPage()
5666 %{
5667 predicate((address)n->get_ptr() == os::get_polling_page());
5668 match(ConP);
5669
5670 op_cost(0);
5671 format %{ %}
5672 interface(CONST_INTER);
5673 %}
5674
5675 // Card Table Byte Map Base
5676 operand immByteMapBase()
5677 %{
5678 // Get base of card map
5679 predicate((jbyte*)n->get_ptr() ==
5680 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base);
5681 match(ConP);
5682
5683 op_cost(0);
5684 format %{ %}
5685 interface(CONST_INTER);
5686 %}
5687
5688 // Pointer Immediate Minus One
5689 // this is used when we want to write the current PC to the thread anchor
5690 operand immP_M1()
5691 %{
5692 predicate(n->get_ptr() == -1);
5693 match(ConP);
5694
5695 op_cost(0);
5696 format %{ %}
5697 interface(CONST_INTER);
5698 %}
5699
5700 // Pointer Immediate Minus Two
5701 // this is used when we want to write the current PC to the thread anchor
5702 operand immP_M2()
5703 %{
5704 predicate(n->get_ptr() == -2);
5705 match(ConP);
5706
5707 op_cost(0);
5708 format %{ %}
5709 interface(CONST_INTER);
5710 %}
5711
5712 // Float and Double operands
5713 // Double Immediate
5714 operand immD()
5715 %{
5716 match(ConD);
5717 op_cost(0);
5718 format %{ %}
5719 interface(CONST_INTER);
5720 %}
5721
5722 // Double Immediate: +0.0d
5723 operand immD0()
5724 %{
5725 predicate(jlong_cast(n->getd()) == 0);
5726 match(ConD);
5727
5728 op_cost(0);
5729 format %{ %}
5730 interface(CONST_INTER);
5731 %}
5732
5733 // constant 'double +0.0'.
5734 operand immDPacked()
5735 %{
5736 predicate(Assembler::operand_valid_for_float_immediate(n->getd()));
5737 match(ConD);
5738 op_cost(0);
5739 format %{ %}
5740 interface(CONST_INTER);
5741 %}
5742
5743 // Float Immediate
5744 operand immF()
5745 %{
5746 match(ConF);
5747 op_cost(0);
5748 format %{ %}
5749 interface(CONST_INTER);
5750 %}
5751
5752 // Float Immediate: +0.0f.
5753 operand immF0()
5754 %{
5755 predicate(jint_cast(n->getf()) == 0);
5756 match(ConF);
5757
5758 op_cost(0);
5759 format %{ %}
5760 interface(CONST_INTER);
5761 %}
5762
5763 //
5764 operand immFPacked()
5765 %{
5766 predicate(Assembler::operand_valid_for_float_immediate((double)n->getf()));
5767 match(ConF);
5768 op_cost(0);
5769 format %{ %}
5770 interface(CONST_INTER);
5771 %}
5772
5773 // Narrow pointer operands
5774 // Narrow Pointer Immediate
5775 operand immN()
5776 %{
5777 match(ConN);
5778
5779 op_cost(0);
5780 format %{ %}
5781 interface(CONST_INTER);
5782 %}
5783
5784 // Narrow NULL Pointer Immediate
5785 operand immN0()
5786 %{
5787 predicate(n->get_narrowcon() == 0);
5788 match(ConN);
5789
5790 op_cost(0);
5791 format %{ %}
5792 interface(CONST_INTER);
5793 %}
5794
5795 operand immNKlass()
5796 %{
5797 match(ConNKlass);
5798
5799 op_cost(0);
5800 format %{ %}
5801 interface(CONST_INTER);
5802 %}
5803
5804 // Integer 32 bit Register Operands
5805 // Integer 32 bitRegister (excludes SP)
5806 operand iRegI()
5807 %{
5808 constraint(ALLOC_IN_RC(any_reg32));
5809 match(RegI);
5810 match(iRegINoSp);
5811 op_cost(0);
5812 format %{ %}
5813 interface(REG_INTER);
5814 %}
5815
5816 // Integer 32 bit Register not Special
5817 operand iRegINoSp()
5818 %{
5819 constraint(ALLOC_IN_RC(no_special_reg32));
5820 match(RegI);
5821 op_cost(0);
5822 format %{ %}
5823 interface(REG_INTER);
5824 %}
5825
5826 // Integer 64 bit Register Operands
5827 // Integer 64 bit Register (includes SP)
5828 operand iRegL()
5829 %{
5830 constraint(ALLOC_IN_RC(any_reg));
5831 match(RegL);
5832 match(iRegLNoSp);
5833 op_cost(0);
5834 format %{ %}
5835 interface(REG_INTER);
5836 %}
5837
5838 // Integer 64 bit Register not Special
5839 operand iRegLNoSp()
5840 %{
5841 constraint(ALLOC_IN_RC(no_special_reg));
5842 match(RegL);
5843 match(iRegL_R0);
5844 format %{ %}
5845 interface(REG_INTER);
5846 %}
5847
5848 // Pointer Register Operands
5849 // Pointer Register
5850 operand iRegP()
5851 %{
5852 constraint(ALLOC_IN_RC(ptr_reg));
5853 match(RegP);
5854 match(iRegPNoSp);
5855 match(iRegP_R0);
5856 //match(iRegP_R2);
5857 //match(iRegP_R4);
5858 //match(iRegP_R5);
5859 match(thread_RegP);
5860 op_cost(0);
5861 format %{ %}
5862 interface(REG_INTER);
5863 %}
5864
5865 // Pointer 64 bit Register not Special
5866 operand iRegPNoSp()
5867 %{
5868 constraint(ALLOC_IN_RC(no_special_ptr_reg));
5869 match(RegP);
5870 // match(iRegP);
5871 // match(iRegP_R0);
5872 // match(iRegP_R2);
5873 // match(iRegP_R4);
5874 // match(iRegP_R5);
5875 // match(thread_RegP);
5876 op_cost(0);
5877 format %{ %}
5878 interface(REG_INTER);
5879 %}
5880
5881 // Pointer 64 bit Register R0 only
5882 operand iRegP_R0()
5883 %{
5884 constraint(ALLOC_IN_RC(r0_reg));
5885 match(RegP);
5886 // match(iRegP);
5887 match(iRegPNoSp);
5888 op_cost(0);
5889 format %{ %}
5890 interface(REG_INTER);
5891 %}
5892
5893 // Pointer 64 bit Register R1 only
5894 operand iRegP_R1()
5895 %{
5896 constraint(ALLOC_IN_RC(r1_reg));
5897 match(RegP);
5898 // match(iRegP);
5899 match(iRegPNoSp);
5900 op_cost(0);
5901 format %{ %}
5902 interface(REG_INTER);
5903 %}
5904
5905 // Pointer 64 bit Register R2 only
5906 operand iRegP_R2()
5907 %{
5908 constraint(ALLOC_IN_RC(r2_reg));
5909 match(RegP);
5910 // match(iRegP);
5911 match(iRegPNoSp);
5912 op_cost(0);
5913 format %{ %}
5914 interface(REG_INTER);
5915 %}
5916
5917 // Pointer 64 bit Register R3 only
5918 operand iRegP_R3()
5919 %{
5920 constraint(ALLOC_IN_RC(r3_reg));
5921 match(RegP);
5922 // match(iRegP);
5923 match(iRegPNoSp);
5924 op_cost(0);
5925 format %{ %}
5926 interface(REG_INTER);
5927 %}
5928
5929 // Pointer 64 bit Register R4 only
5930 operand iRegP_R4()
5931 %{
5932 constraint(ALLOC_IN_RC(r4_reg));
5933 match(RegP);
5934 // match(iRegP);
5935 match(iRegPNoSp);
5936 op_cost(0);
5937 format %{ %}
5938 interface(REG_INTER);
5939 %}
5940
5941 // Pointer 64 bit Register R5 only
5942 operand iRegP_R5()
5943 %{
5944 constraint(ALLOC_IN_RC(r5_reg));
5945 match(RegP);
5946 // match(iRegP);
5947 match(iRegPNoSp);
5948 op_cost(0);
5949 format %{ %}
5950 interface(REG_INTER);
5951 %}
5952
5953 // Pointer 64 bit Register R10 only
5954 operand iRegP_R10()
5955 %{
5956 constraint(ALLOC_IN_RC(r10_reg));
5957 match(RegP);
5958 // match(iRegP);
5959 match(iRegPNoSp);
5960 op_cost(0);
5961 format %{ %}
5962 interface(REG_INTER);
5963 %}
5964
5965 // Long 64 bit Register R0 only
5966 operand iRegL_R0()
5967 %{
5968 constraint(ALLOC_IN_RC(r0_reg));
5969 match(RegL);
5970 match(iRegLNoSp);
5971 op_cost(0);
5972 format %{ %}
5973 interface(REG_INTER);
5974 %}
5975
5976 // Long 64 bit Register R2 only
5977 operand iRegL_R2()
5978 %{
5979 constraint(ALLOC_IN_RC(r2_reg));
5980 match(RegL);
5981 match(iRegLNoSp);
5982 op_cost(0);
5983 format %{ %}
5984 interface(REG_INTER);
5985 %}
5986
5987 // Long 64 bit Register R3 only
5988 operand iRegL_R3()
5989 %{
5990 constraint(ALLOC_IN_RC(r3_reg));
5991 match(RegL);
5992 match(iRegLNoSp);
5993 op_cost(0);
5994 format %{ %}
5995 interface(REG_INTER);
5996 %}
5997
5998 // Long 64 bit Register R11 only
5999 operand iRegL_R11()
6000 %{
6001 constraint(ALLOC_IN_RC(r11_reg));
6002 match(RegL);
6003 match(iRegLNoSp);
6004 op_cost(0);
6005 format %{ %}
6006 interface(REG_INTER);
6007 %}
6008
6009 // Pointer 64 bit Register FP only
6010 operand iRegP_FP()
6011 %{
6012 constraint(ALLOC_IN_RC(fp_reg));
6013 match(RegP);
6014 // match(iRegP);
6015 op_cost(0);
6016 format %{ %}
6017 interface(REG_INTER);
6018 %}
6019
6020 // Register R0 only
6021 operand iRegI_R0()
6022 %{
6023 constraint(ALLOC_IN_RC(int_r0_reg));
6024 match(RegI);
6025 match(iRegINoSp);
6026 op_cost(0);
6027 format %{ %}
6028 interface(REG_INTER);
6029 %}
6030
6031 // Register R2 only
6032 operand iRegI_R2()
6033 %{
6034 constraint(ALLOC_IN_RC(int_r2_reg));
6035 match(RegI);
6036 match(iRegINoSp);
6037 op_cost(0);
6038 format %{ %}
6039 interface(REG_INTER);
6040 %}
6041
6042 // Register R3 only
6043 operand iRegI_R3()
6044 %{
6045 constraint(ALLOC_IN_RC(int_r3_reg));
6046 match(RegI);
6047 match(iRegINoSp);
6048 op_cost(0);
6049 format %{ %}
6050 interface(REG_INTER);
6051 %}
6052
6053
6054 // Register R4 only
6055 operand iRegI_R4()
6056 %{
6057 constraint(ALLOC_IN_RC(int_r4_reg));
6058 match(RegI);
6059 match(iRegINoSp);
6060 op_cost(0);
6061 format %{ %}
6062 interface(REG_INTER);
6063 %}
6064
6065
6066 // Pointer Register Operands
6067 // Narrow Pointer Register
6068 operand iRegN()
6069 %{
6070 constraint(ALLOC_IN_RC(any_reg32));
6071 match(RegN);
6072 match(iRegNNoSp);
6073 op_cost(0);
6074 format %{ %}
6075 interface(REG_INTER);
6076 %}
6077
6078 operand iRegN_R0()
6079 %{
6080 constraint(ALLOC_IN_RC(r0_reg));
6081 match(iRegN);
6082 op_cost(0);
6083 format %{ %}
6084 interface(REG_INTER);
6085 %}
6086
6087 operand iRegN_R2()
6088 %{
6089 constraint(ALLOC_IN_RC(r2_reg));
6090 match(iRegN);
6091 op_cost(0);
6092 format %{ %}
6093 interface(REG_INTER);
6094 %}
6095
6096 operand iRegN_R3()
6097 %{
6098 constraint(ALLOC_IN_RC(r3_reg));
6099 match(iRegN);
6100 op_cost(0);
6101 format %{ %}
6102 interface(REG_INTER);
6103 %}
6104
6105 // Integer 64 bit Register not Special
6106 operand iRegNNoSp()
6107 %{
6108 constraint(ALLOC_IN_RC(no_special_reg32));
6109 match(RegN);
6110 op_cost(0);
6111 format %{ %}
6112 interface(REG_INTER);
6113 %}
6114
6115 // heap base register -- used for encoding immN0
6116
6117 operand iRegIHeapbase()
6118 %{
6119 constraint(ALLOC_IN_RC(heapbase_reg));
6120 match(RegI);
6121 op_cost(0);
6122 format %{ %}
6123 interface(REG_INTER);
6124 %}
6125
6126 // Float Register
6127 // Float register operands
6128 operand vRegF()
6129 %{
6130 constraint(ALLOC_IN_RC(float_reg));
6131 match(RegF);
6132
6133 op_cost(0);
6134 format %{ %}
6135 interface(REG_INTER);
6136 %}
6137
6138 // Double Register
6139 // Double register operands
6140 operand vRegD()
6141 %{
6142 constraint(ALLOC_IN_RC(double_reg));
6143 match(RegD);
6144
6145 op_cost(0);
6146 format %{ %}
6147 interface(REG_INTER);
6148 %}
6149
6150 operand vecD()
6151 %{
6152 constraint(ALLOC_IN_RC(vectord_reg));
6153 match(VecD);
6154
6155 op_cost(0);
6156 format %{ %}
6157 interface(REG_INTER);
6158 %}
6159
6160 operand vecX()
6161 %{
6162 constraint(ALLOC_IN_RC(vectorx_reg));
6163 match(VecX);
6164
6165 op_cost(0);
6166 format %{ %}
6167 interface(REG_INTER);
6168 %}
6169
6170 operand vRegD_V0()
6171 %{
6172 constraint(ALLOC_IN_RC(v0_reg));
6173 match(RegD);
6174 op_cost(0);
6175 format %{ %}
6176 interface(REG_INTER);
6177 %}
6178
6179 operand vRegD_V1()
6180 %{
6181 constraint(ALLOC_IN_RC(v1_reg));
6182 match(RegD);
6183 op_cost(0);
6184 format %{ %}
6185 interface(REG_INTER);
6186 %}
6187
6188 operand vRegD_V2()
6189 %{
6190 constraint(ALLOC_IN_RC(v2_reg));
6191 match(RegD);
6192 op_cost(0);
6193 format %{ %}
6194 interface(REG_INTER);
6195 %}
6196
6197 operand vRegD_V3()
6198 %{
6199 constraint(ALLOC_IN_RC(v3_reg));
6200 match(RegD);
6201 op_cost(0);
6202 format %{ %}
6203 interface(REG_INTER);
6204 %}
6205
6206 // Flags register, used as output of signed compare instructions
6207
6208 // note that on AArch64 we also use this register as the output for
6209 // for floating point compare instructions (CmpF CmpD). this ensures
6210 // that ordered inequality tests use GT, GE, LT or LE none of which
6211 // pass through cases where the result is unordered i.e. one or both
6212 // inputs to the compare is a NaN. this means that the ideal code can
6213 // replace e.g. a GT with an LE and not end up capturing the NaN case
6214 // (where the comparison should always fail). EQ and NE tests are
6215 // always generated in ideal code so that unordered folds into the NE
6216 // case, matching the behaviour of AArch64 NE.
6217 //
6218 // This differs from x86 where the outputs of FP compares use a
6219 // special FP flags registers and where compares based on this
6220 // register are distinguished into ordered inequalities (cmpOpUCF) and
6221 // EQ/NEQ tests (cmpOpUCF2). x86 has to special case the latter tests
6222 // to explicitly handle the unordered case in branches. x86 also has
6223 // to include extra CMoveX rules to accept a cmpOpUCF input.
6224
6225 operand rFlagsReg()
6226 %{
6227 constraint(ALLOC_IN_RC(int_flags));
6228 match(RegFlags);
6229
6230 op_cost(0);
6231 format %{ "RFLAGS" %}
6232 interface(REG_INTER);
6233 %}
6234
6235 // Flags register, used as output of unsigned compare instructions
6236 operand rFlagsRegU()
6237 %{
6238 constraint(ALLOC_IN_RC(int_flags));
6239 match(RegFlags);
6240
6241 op_cost(0);
6242 format %{ "RFLAGSU" %}
6243 interface(REG_INTER);
6244 %}
6245
6246 // Special Registers
6247
6248 // Method Register
6249 operand inline_cache_RegP(iRegP reg)
6250 %{
6251 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
6252 match(reg);
6253 match(iRegPNoSp);
6254 op_cost(0);
6255 format %{ %}
6256 interface(REG_INTER);
6257 %}
6258
6259 operand interpreter_method_oop_RegP(iRegP reg)
6260 %{
6261 constraint(ALLOC_IN_RC(method_reg)); // interpreter_method_oop_reg
6262 match(reg);
6263 match(iRegPNoSp);
6264 op_cost(0);
6265 format %{ %}
6266 interface(REG_INTER);
6267 %}
6268
6269 // Thread Register
6270 operand thread_RegP(iRegP reg)
6271 %{
6272 constraint(ALLOC_IN_RC(thread_reg)); // link_reg
6273 match(reg);
6274 op_cost(0);
6275 format %{ %}
6276 interface(REG_INTER);
6277 %}
6278
6279 operand lr_RegP(iRegP reg)
6280 %{
6281 constraint(ALLOC_IN_RC(lr_reg)); // link_reg
6282 match(reg);
6283 op_cost(0);
6284 format %{ %}
6285 interface(REG_INTER);
6286 %}
6287
6288 //----------Memory Operands----------------------------------------------------
6289
6290 operand indirect(iRegP reg)
6291 %{
6292 constraint(ALLOC_IN_RC(ptr_reg));
6293 match(reg);
6294 op_cost(0);
6295 format %{ "[$reg]" %}
6296 interface(MEMORY_INTER) %{
6297 base($reg);
6298 index(0xffffffff);
6299 scale(0x0);
6300 disp(0x0);
6301 %}
6302 %}
6303
6304 operand indIndexScaledI2L(iRegP reg, iRegI ireg, immIScale scale)
6305 %{
6306 constraint(ALLOC_IN_RC(ptr_reg));
6307 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
6308 match(AddP reg (LShiftL (ConvI2L ireg) scale));
6309 op_cost(0);
6310 format %{ "$reg, $ireg sxtw($scale), 0, I2L" %}
6311 interface(MEMORY_INTER) %{
6312 base($reg);
6313 index($ireg);
6314 scale($scale);
6315 disp(0x0);
6316 %}
6317 %}
6318
6319 operand indIndexScaled(iRegP reg, iRegL lreg, immIScale scale)
6320 %{
6321 constraint(ALLOC_IN_RC(ptr_reg));
6322 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
6323 match(AddP reg (LShiftL lreg scale));
6324 op_cost(0);
6325 format %{ "$reg, $lreg lsl($scale)" %}
6326 interface(MEMORY_INTER) %{
6327 base($reg);
6328 index($lreg);
6329 scale($scale);
6330 disp(0x0);
6331 %}
6332 %}
6333
6334 operand indIndexI2L(iRegP reg, iRegI ireg)
6335 %{
6336 constraint(ALLOC_IN_RC(ptr_reg));
6337 match(AddP reg (ConvI2L ireg));
6338 op_cost(0);
6339 format %{ "$reg, $ireg, 0, I2L" %}
6340 interface(MEMORY_INTER) %{
6341 base($reg);
6342 index($ireg);
6343 scale(0x0);
6344 disp(0x0);
6345 %}
6346 %}
6347
6348 operand indIndex(iRegP reg, iRegL lreg)
6349 %{
6350 constraint(ALLOC_IN_RC(ptr_reg));
6351 match(AddP reg lreg);
6352 op_cost(0);
6353 format %{ "$reg, $lreg" %}
6354 interface(MEMORY_INTER) %{
6355 base($reg);
6356 index($lreg);
6357 scale(0x0);
6358 disp(0x0);
6359 %}
6360 %}
6361
6362 operand indOffI(iRegP reg, immIOffset off)
6363 %{
6364 constraint(ALLOC_IN_RC(ptr_reg));
6365 match(AddP reg off);
6366 op_cost(0);
6367 format %{ "[$reg, $off]" %}
6368 interface(MEMORY_INTER) %{
6369 base($reg);
6370 index(0xffffffff);
6371 scale(0x0);
6372 disp($off);
6373 %}
6374 %}
6375
6376 operand indOffI4(iRegP reg, immIOffset4 off)
6377 %{
6378 constraint(ALLOC_IN_RC(ptr_reg));
6379 match(AddP reg off);
6380 op_cost(0);
6381 format %{ "[$reg, $off]" %}
6382 interface(MEMORY_INTER) %{
6383 base($reg);
6384 index(0xffffffff);
6385 scale(0x0);
6386 disp($off);
6387 %}
6388 %}
6389
6390 operand indOffI8(iRegP reg, immIOffset8 off)
6391 %{
6392 constraint(ALLOC_IN_RC(ptr_reg));
6393 match(AddP reg off);
6394 op_cost(0);
6395 format %{ "[$reg, $off]" %}
6396 interface(MEMORY_INTER) %{
6397 base($reg);
6398 index(0xffffffff);
6399 scale(0x0);
6400 disp($off);
6401 %}
6402 %}
6403
6404 operand indOffI16(iRegP reg, immIOffset16 off)
6405 %{
6406 constraint(ALLOC_IN_RC(ptr_reg));
6407 match(AddP reg off);
6408 op_cost(0);
6409 format %{ "[$reg, $off]" %}
6410 interface(MEMORY_INTER) %{
6411 base($reg);
6412 index(0xffffffff);
6413 scale(0x0);
6414 disp($off);
6415 %}
6416 %}
6417
6418 operand indOffL(iRegP reg, immLoffset off)
6419 %{
6420 constraint(ALLOC_IN_RC(ptr_reg));
6421 match(AddP reg off);
6422 op_cost(0);
6423 format %{ "[$reg, $off]" %}
6424 interface(MEMORY_INTER) %{
6425 base($reg);
6426 index(0xffffffff);
6427 scale(0x0);
6428 disp($off);
6429 %}
6430 %}
6431
6432 operand indOffL4(iRegP reg, immLoffset4 off)
6433 %{
6434 constraint(ALLOC_IN_RC(ptr_reg));
6435 match(AddP reg off);
6436 op_cost(0);
6437 format %{ "[$reg, $off]" %}
6438 interface(MEMORY_INTER) %{
6439 base($reg);
6440 index(0xffffffff);
6441 scale(0x0);
6442 disp($off);
6443 %}
6444 %}
6445
6446 operand indOffL8(iRegP reg, immLoffset8 off)
6447 %{
6448 constraint(ALLOC_IN_RC(ptr_reg));
6449 match(AddP reg off);
6450 op_cost(0);
6451 format %{ "[$reg, $off]" %}
6452 interface(MEMORY_INTER) %{
6453 base($reg);
6454 index(0xffffffff);
6455 scale(0x0);
6456 disp($off);
6457 %}
6458 %}
6459
6460 operand indOffL16(iRegP reg, immLoffset16 off)
6461 %{
6462 constraint(ALLOC_IN_RC(ptr_reg));
6463 match(AddP reg off);
6464 op_cost(0);
6465 format %{ "[$reg, $off]" %}
6466 interface(MEMORY_INTER) %{
6467 base($reg);
6468 index(0xffffffff);
6469 scale(0x0);
6470 disp($off);
6471 %}
6472 %}
6473
6474 operand indirectN(iRegN reg)
6475 %{
6476 predicate(Universe::narrow_oop_shift() == 0);
6477 constraint(ALLOC_IN_RC(ptr_reg));
6478 match(DecodeN reg);
6479 op_cost(0);
6480 format %{ "[$reg]\t# narrow" %}
6481 interface(MEMORY_INTER) %{
6482 base($reg);
6483 index(0xffffffff);
6484 scale(0x0);
6485 disp(0x0);
6486 %}
6487 %}
6488
6489 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
6490 %{
6491 predicate(Universe::narrow_oop_shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
6492 constraint(ALLOC_IN_RC(ptr_reg));
6493 match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
6494 op_cost(0);
6495 format %{ "$reg, $ireg sxtw($scale), 0, I2L\t# narrow" %}
6496 interface(MEMORY_INTER) %{
6497 base($reg);
6498 index($ireg);
6499 scale($scale);
6500 disp(0x0);
6501 %}
6502 %}
6503
6504 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
6505 %{
6506 predicate(Universe::narrow_oop_shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
6507 constraint(ALLOC_IN_RC(ptr_reg));
6508 match(AddP (DecodeN reg) (LShiftL lreg scale));
6509 op_cost(0);
6510 format %{ "$reg, $lreg lsl($scale)\t# narrow" %}
6511 interface(MEMORY_INTER) %{
6512 base($reg);
6513 index($lreg);
6514 scale($scale);
6515 disp(0x0);
6516 %}
6517 %}
6518
6519 operand indIndexI2LN(iRegN reg, iRegI ireg)
6520 %{
6521 predicate(Universe::narrow_oop_shift() == 0);
6522 constraint(ALLOC_IN_RC(ptr_reg));
6523 match(AddP (DecodeN reg) (ConvI2L ireg));
6524 op_cost(0);
6525 format %{ "$reg, $ireg, 0, I2L\t# narrow" %}
6526 interface(MEMORY_INTER) %{
6527 base($reg);
6528 index($ireg);
6529 scale(0x0);
6530 disp(0x0);
6531 %}
6532 %}
6533
6534 operand indIndexN(iRegN reg, iRegL lreg)
6535 %{
6536 predicate(Universe::narrow_oop_shift() == 0);
6537 constraint(ALLOC_IN_RC(ptr_reg));
6538 match(AddP (DecodeN reg) lreg);
6539 op_cost(0);
6540 format %{ "$reg, $lreg\t# narrow" %}
6541 interface(MEMORY_INTER) %{
6542 base($reg);
6543 index($lreg);
6544 scale(0x0);
6545 disp(0x0);
6546 %}
6547 %}
6548
6549 operand indOffIN(iRegN reg, immIOffset off)
6550 %{
6551 predicate(Universe::narrow_oop_shift() == 0);
6552 constraint(ALLOC_IN_RC(ptr_reg));
6553 match(AddP (DecodeN reg) off);
6554 op_cost(0);
6555 format %{ "[$reg, $off]\t# narrow" %}
6556 interface(MEMORY_INTER) %{
6557 base($reg);
6558 index(0xffffffff);
6559 scale(0x0);
6560 disp($off);
6561 %}
6562 %}
6563
6564 operand indOffLN(iRegN reg, immLoffset off)
6565 %{
6566 predicate(Universe::narrow_oop_shift() == 0);
6567 constraint(ALLOC_IN_RC(ptr_reg));
6568 match(AddP (DecodeN reg) off);
6569 op_cost(0);
6570 format %{ "[$reg, $off]\t# narrow" %}
6571 interface(MEMORY_INTER) %{
6572 base($reg);
6573 index(0xffffffff);
6574 scale(0x0);
6575 disp($off);
6576 %}
6577 %}
6578
6579
6580
6581 // AArch64 opto stubs need to write to the pc slot in the thread anchor
6582 operand thread_anchor_pc(thread_RegP reg, immL_pc_off off)
6583 %{
6584 constraint(ALLOC_IN_RC(ptr_reg));
6585 match(AddP reg off);
6586 op_cost(0);
6587 format %{ "[$reg, $off]" %}
6588 interface(MEMORY_INTER) %{
6589 base($reg);
6590 index(0xffffffff);
6591 scale(0x0);
6592 disp($off);
6593 %}
6594 %}
6595
6596 //----------Special Memory Operands--------------------------------------------
6597 // Stack Slot Operand - This operand is used for loading and storing temporary
6598 // values on the stack where a match requires a value to
6599 // flow through memory.
6600 operand stackSlotP(sRegP reg)
6601 %{
6602 constraint(ALLOC_IN_RC(stack_slots));
6603 op_cost(100);
6604 // No match rule because this operand is only generated in matching
6605 // match(RegP);
6606 format %{ "[$reg]" %}
6607 interface(MEMORY_INTER) %{
6608 base(0x1e); // RSP
6609 index(0x0); // No Index
6610 scale(0x0); // No Scale
6611 disp($reg); // Stack Offset
6612 %}
6613 %}
6614
6615 operand stackSlotI(sRegI reg)
6616 %{
6617 constraint(ALLOC_IN_RC(stack_slots));
6618 // No match rule because this operand is only generated in matching
6619 // match(RegI);
6620 format %{ "[$reg]" %}
6621 interface(MEMORY_INTER) %{
6622 base(0x1e); // RSP
6623 index(0x0); // No Index
6624 scale(0x0); // No Scale
6625 disp($reg); // Stack Offset
6626 %}
6627 %}
6628
6629 operand stackSlotF(sRegF reg)
6630 %{
6631 constraint(ALLOC_IN_RC(stack_slots));
6632 // No match rule because this operand is only generated in matching
6633 // match(RegF);
6634 format %{ "[$reg]" %}
6635 interface(MEMORY_INTER) %{
6636 base(0x1e); // RSP
6637 index(0x0); // No Index
6638 scale(0x0); // No Scale
6639 disp($reg); // Stack Offset
6640 %}
6641 %}
6642
6643 operand stackSlotD(sRegD reg)
6644 %{
6645 constraint(ALLOC_IN_RC(stack_slots));
6646 // No match rule because this operand is only generated in matching
6647 // match(RegD);
6648 format %{ "[$reg]" %}
6649 interface(MEMORY_INTER) %{
6650 base(0x1e); // RSP
6651 index(0x0); // No Index
6652 scale(0x0); // No Scale
6653 disp($reg); // Stack Offset
6654 %}
6655 %}
6656
6657 operand stackSlotL(sRegL reg)
6658 %{
6659 constraint(ALLOC_IN_RC(stack_slots));
6660 // No match rule because this operand is only generated in matching
6661 // match(RegL);
6662 format %{ "[$reg]" %}
6663 interface(MEMORY_INTER) %{
6664 base(0x1e); // RSP
6665 index(0x0); // No Index
6666 scale(0x0); // No Scale
6667 disp($reg); // Stack Offset
6668 %}
6669 %}
6670
6671 // Operands for expressing Control Flow
6672 // NOTE: Label is a predefined operand which should not be redefined in
6673 // the AD file. It is generically handled within the ADLC.
6674
6675 //----------Conditional Branch Operands----------------------------------------
6676 // Comparison Op - This is the operation of the comparison, and is limited to
6677 // the following set of codes:
6678 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6679 //
6680 // Other attributes of the comparison, such as unsignedness, are specified
6681 // by the comparison instruction that sets a condition code flags register.
6682 // That result is represented by a flags operand whose subtype is appropriate
6683 // to the unsignedness (etc.) of the comparison.
6684 //
6685 // Later, the instruction which matches both the Comparison Op (a Bool) and
6686 // the flags (produced by the Cmp) specifies the coding of the comparison op
6687 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6688
6689 // used for signed integral comparisons and fp comparisons
6690
6691 operand cmpOp()
6692 %{
6693 match(Bool);
6694
6695 format %{ "" %}
6696 interface(COND_INTER) %{
6697 equal(0x0, "eq");
6698 not_equal(0x1, "ne");
6699 less(0xb, "lt");
6700 greater_equal(0xa, "ge");
6701 less_equal(0xd, "le");
6702 greater(0xc, "gt");
6703 overflow(0x6, "vs");
6704 no_overflow(0x7, "vc");
6705 %}
6706 %}
6707
6708 // used for unsigned integral comparisons
6709
6710 operand cmpOpU()
6711 %{
6712 match(Bool);
6713
6714 format %{ "" %}
6715 interface(COND_INTER) %{
6716 equal(0x0, "eq");
6717 not_equal(0x1, "ne");
6718 less(0x3, "lo");
6719 greater_equal(0x2, "hs");
6720 less_equal(0x9, "ls");
6721 greater(0x8, "hi");
6722 overflow(0x6, "vs");
6723 no_overflow(0x7, "vc");
6724 %}
6725 %}
6726
6727 // used for certain integral comparisons which can be
6728 // converted to cbxx or tbxx instructions
6729
6730 operand cmpOpEqNe()
6731 %{
6732 match(Bool);
6733 match(CmpOp);
6734 op_cost(0);
6735 predicate(n->as_Bool()->_test._test == BoolTest::ne
6736 || n->as_Bool()->_test._test == BoolTest::eq);
6737
6738 format %{ "" %}
6739 interface(COND_INTER) %{
6740 equal(0x0, "eq");
6741 not_equal(0x1, "ne");
6742 less(0xb, "lt");
6743 greater_equal(0xa, "ge");
6744 less_equal(0xd, "le");
6745 greater(0xc, "gt");
6746 overflow(0x6, "vs");
6747 no_overflow(0x7, "vc");
6748 %}
6749 %}
6750
6751 // used for certain integral comparisons which can be
6752 // converted to cbxx or tbxx instructions
6753
6754 operand cmpOpLtGe()
6755 %{
6756 match(Bool);
6757 match(CmpOp);
6758 op_cost(0);
6759
6760 predicate(n->as_Bool()->_test._test == BoolTest::lt
6761 || n->as_Bool()->_test._test == BoolTest::ge);
6762
6763 format %{ "" %}
6764 interface(COND_INTER) %{
6765 equal(0x0, "eq");
6766 not_equal(0x1, "ne");
6767 less(0xb, "lt");
6768 greater_equal(0xa, "ge");
6769 less_equal(0xd, "le");
6770 greater(0xc, "gt");
6771 overflow(0x6, "vs");
6772 no_overflow(0x7, "vc");
6773 %}
6774 %}
6775
6776 // used for certain unsigned integral comparisons which can be
6777 // converted to cbxx or tbxx instructions
6778
6779 operand cmpOpUEqNeLtGe()
6780 %{
6781 match(Bool);
6782 match(CmpOp);
6783 op_cost(0);
6784
6785 predicate(n->as_Bool()->_test._test == BoolTest::eq
6786 || n->as_Bool()->_test._test == BoolTest::ne
6787 || n->as_Bool()->_test._test == BoolTest::lt
6788 || n->as_Bool()->_test._test == BoolTest::ge);
6789
6790 format %{ "" %}
6791 interface(COND_INTER) %{
6792 equal(0x0, "eq");
6793 not_equal(0x1, "ne");
6794 less(0xb, "lt");
6795 greater_equal(0xa, "ge");
6796 less_equal(0xd, "le");
6797 greater(0xc, "gt");
6798 overflow(0x6, "vs");
6799 no_overflow(0x7, "vc");
6800 %}
6801 %}
6802
6803 // Special operand allowing long args to int ops to be truncated for free
6804
6805 operand iRegL2I(iRegL reg) %{
6806
6807 op_cost(0);
6808
6809 match(ConvL2I reg);
6810
6811 format %{ "l2i($reg)" %}
6812
6813 interface(REG_INTER)
6814 %}
6815
6816 opclass vmem4(indirect, indIndex, indOffI4, indOffL4);
6817 opclass vmem8(indirect, indIndex, indOffI8, indOffL8);
6818 opclass vmem16(indirect, indIndex, indOffI16, indOffL16);
6819
6820 //----------OPERAND CLASSES----------------------------------------------------
6821 // Operand Classes are groups of operands that are used as to simplify
6822 // instruction definitions by not requiring the AD writer to specify
6823 // separate instructions for every form of operand when the
6824 // instruction accepts multiple operand types with the same basic
6825 // encoding and format. The classic case of this is memory operands.
6826
6827 // memory is used to define read/write location for load/store
6828 // instruction defs. we can turn a memory op into an Address
6829
6830 opclass memory(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI, indOffL,
6831 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
6832
6833 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
6834 // operations. it allows the src to be either an iRegI or a (ConvL2I
6835 // iRegL). in the latter case the l2i normally planted for a ConvL2I
6836 // can be elided because the 32-bit instruction will just employ the
6837 // lower 32 bits anyway.
6838 //
6839 // n.b. this does not elide all L2I conversions. if the truncated
6840 // value is consumed by more than one operation then the ConvL2I
6841 // cannot be bundled into the consuming nodes so an l2i gets planted
6842 // (actually a movw $dst $src) and the downstream instructions consume
6843 // the result of the l2i as an iRegI input. That's a shame since the
6844 // movw is actually redundant but its not too costly.
6845
6846 opclass iRegIorL2I(iRegI, iRegL2I);
6847
6848 //----------PIPELINE-----------------------------------------------------------
6849 // Rules which define the behavior of the target architectures pipeline.
6850
6851 // For specific pipelines, eg A53, define the stages of that pipeline
6852 //pipe_desc(ISS, EX1, EX2, WR);
6853 #define ISS S0
6854 #define EX1 S1
6855 #define EX2 S2
6856 #define WR S3
6857
6858 // Integer ALU reg operation
6859 pipeline %{
6860
6861 attributes %{
6862 // ARM instructions are of fixed length
6863 fixed_size_instructions; // Fixed size instructions TODO does
6864 max_instructions_per_bundle = 2; // A53 = 2, A57 = 4
6865 // ARM instructions come in 32-bit word units
6866 instruction_unit_size = 4; // An instruction is 4 bytes long
6867 instruction_fetch_unit_size = 64; // The processor fetches one line
6868 instruction_fetch_units = 1; // of 64 bytes
6869
6870 // List of nop instructions
6871 nops( MachNop );
6872 %}
6873
6874 // We don't use an actual pipeline model so don't care about resources
6875 // or description. we do use pipeline classes to introduce fixed
6876 // latencies
6877
6878 //----------RESOURCES----------------------------------------------------------
6879 // Resources are the functional units available to the machine
6880
6881 resources( INS0, INS1, INS01 = INS0 | INS1,
6882 ALU0, ALU1, ALU = ALU0 | ALU1,
6883 MAC,
6884 DIV,
6885 BRANCH,
6886 LDST,
6887 NEON_FP);
6888
6889 //----------PIPELINE DESCRIPTION-----------------------------------------------
6890 // Pipeline Description specifies the stages in the machine's pipeline
6891
6892 // Define the pipeline as a generic 6 stage pipeline
6893 pipe_desc(S0, S1, S2, S3, S4, S5);
6894
6895 //----------PIPELINE CLASSES---------------------------------------------------
6896 // Pipeline Classes describe the stages in which input and output are
6897 // referenced by the hardware pipeline.
6898
6899 pipe_class fp_dop_reg_reg_s(vRegF dst, vRegF src1, vRegF src2)
6900 %{
6901 single_instruction;
6902 src1 : S1(read);
6903 src2 : S2(read);
6904 dst : S5(write);
6905 INS01 : ISS;
6906 NEON_FP : S5;
6907 %}
6908
6909 pipe_class fp_dop_reg_reg_d(vRegD dst, vRegD src1, vRegD src2)
6910 %{
6911 single_instruction;
6912 src1 : S1(read);
6913 src2 : S2(read);
6914 dst : S5(write);
6915 INS01 : ISS;
6916 NEON_FP : S5;
6917 %}
6918
6919 pipe_class fp_uop_s(vRegF dst, vRegF src)
6920 %{
6921 single_instruction;
6922 src : S1(read);
6923 dst : S5(write);
6924 INS01 : ISS;
6925 NEON_FP : S5;
6926 %}
6927
6928 pipe_class fp_uop_d(vRegD dst, vRegD src)
6929 %{
6930 single_instruction;
6931 src : S1(read);
6932 dst : S5(write);
6933 INS01 : ISS;
6934 NEON_FP : S5;
6935 %}
6936
6937 pipe_class fp_d2f(vRegF dst, vRegD src)
6938 %{
6939 single_instruction;
6940 src : S1(read);
6941 dst : S5(write);
6942 INS01 : ISS;
6943 NEON_FP : S5;
6944 %}
6945
6946 pipe_class fp_f2d(vRegD dst, vRegF src)
6947 %{
6948 single_instruction;
6949 src : S1(read);
6950 dst : S5(write);
6951 INS01 : ISS;
6952 NEON_FP : S5;
6953 %}
6954
6955 pipe_class fp_f2i(iRegINoSp dst, vRegF src)
6956 %{
6957 single_instruction;
6958 src : S1(read);
6959 dst : S5(write);
6960 INS01 : ISS;
6961 NEON_FP : S5;
6962 %}
6963
6964 pipe_class fp_f2l(iRegLNoSp dst, vRegF src)
6965 %{
6966 single_instruction;
6967 src : S1(read);
6968 dst : S5(write);
6969 INS01 : ISS;
6970 NEON_FP : S5;
6971 %}
6972
6973 pipe_class fp_i2f(vRegF dst, iRegIorL2I src)
6974 %{
6975 single_instruction;
6976 src : S1(read);
6977 dst : S5(write);
6978 INS01 : ISS;
6979 NEON_FP : S5;
6980 %}
6981
6982 pipe_class fp_l2f(vRegF dst, iRegL src)
6983 %{
6984 single_instruction;
6985 src : S1(read);
6986 dst : S5(write);
6987 INS01 : ISS;
6988 NEON_FP : S5;
6989 %}
6990
6991 pipe_class fp_d2i(iRegINoSp dst, vRegD src)
6992 %{
6993 single_instruction;
6994 src : S1(read);
6995 dst : S5(write);
6996 INS01 : ISS;
6997 NEON_FP : S5;
6998 %}
6999
7000 pipe_class fp_d2l(iRegLNoSp dst, vRegD src)
7001 %{
7002 single_instruction;
7003 src : S1(read);
7004 dst : S5(write);
7005 INS01 : ISS;
7006 NEON_FP : S5;
7007 %}
7008
7009 pipe_class fp_i2d(vRegD dst, iRegIorL2I src)
7010 %{
7011 single_instruction;
7012 src : S1(read);
7013 dst : S5(write);
7014 INS01 : ISS;
7015 NEON_FP : S5;
7016 %}
7017
7018 pipe_class fp_l2d(vRegD dst, iRegIorL2I src)
7019 %{
7020 single_instruction;
7021 src : S1(read);
7022 dst : S5(write);
7023 INS01 : ISS;
7024 NEON_FP : S5;
7025 %}
7026
7027 pipe_class fp_div_s(vRegF dst, vRegF src1, vRegF src2)
7028 %{
7029 single_instruction;
7030 src1 : S1(read);
7031 src2 : S2(read);
7032 dst : S5(write);
7033 INS0 : ISS;
7034 NEON_FP : S5;
7035 %}
7036
7037 pipe_class fp_div_d(vRegD dst, vRegD src1, vRegD src2)
7038 %{
7039 single_instruction;
7040 src1 : S1(read);
7041 src2 : S2(read);
7042 dst : S5(write);
7043 INS0 : ISS;
7044 NEON_FP : S5;
7045 %}
7046
7047 pipe_class fp_cond_reg_reg_s(vRegF dst, vRegF src1, vRegF src2, rFlagsReg cr)
7048 %{
7049 single_instruction;
7050 cr : S1(read);
7051 src1 : S1(read);
7052 src2 : S1(read);
7053 dst : S3(write);
7054 INS01 : ISS;
7055 NEON_FP : S3;
7056 %}
7057
7058 pipe_class fp_cond_reg_reg_d(vRegD dst, vRegD src1, vRegD src2, rFlagsReg cr)
7059 %{
7060 single_instruction;
7061 cr : S1(read);
7062 src1 : S1(read);
7063 src2 : S1(read);
7064 dst : S3(write);
7065 INS01 : ISS;
7066 NEON_FP : S3;
7067 %}
7068
7069 pipe_class fp_imm_s(vRegF dst)
7070 %{
7071 single_instruction;
7072 dst : S3(write);
7073 INS01 : ISS;
7074 NEON_FP : S3;
7075 %}
7076
7077 pipe_class fp_imm_d(vRegD dst)
7078 %{
7079 single_instruction;
7080 dst : S3(write);
7081 INS01 : ISS;
7082 NEON_FP : S3;
7083 %}
7084
7085 pipe_class fp_load_constant_s(vRegF dst)
7086 %{
7087 single_instruction;
7088 dst : S4(write);
7089 INS01 : ISS;
7090 NEON_FP : S4;
7091 %}
7092
7093 pipe_class fp_load_constant_d(vRegD dst)
7094 %{
7095 single_instruction;
7096 dst : S4(write);
7097 INS01 : ISS;
7098 NEON_FP : S4;
7099 %}
7100
7101 pipe_class vmul64(vecD dst, vecD src1, vecD src2)
7102 %{
7103 single_instruction;
7104 dst : S5(write);
7105 src1 : S1(read);
7106 src2 : S1(read);
7107 INS01 : ISS;
7108 NEON_FP : S5;
7109 %}
7110
7111 pipe_class vmul128(vecX dst, vecX src1, vecX src2)
7112 %{
7113 single_instruction;
7114 dst : S5(write);
7115 src1 : S1(read);
7116 src2 : S1(read);
7117 INS0 : ISS;
7118 NEON_FP : S5;
7119 %}
7120
7121 pipe_class vmla64(vecD dst, vecD src1, vecD src2)
7122 %{
7123 single_instruction;
7124 dst : S5(write);
7125 src1 : S1(read);
7126 src2 : S1(read);
7127 dst : S1(read);
7128 INS01 : ISS;
7129 NEON_FP : S5;
7130 %}
7131
7132 pipe_class vmla128(vecX dst, vecX src1, vecX src2)
7133 %{
7134 single_instruction;
7135 dst : S5(write);
7136 src1 : S1(read);
7137 src2 : S1(read);
7138 dst : S1(read);
7139 INS0 : ISS;
7140 NEON_FP : S5;
7141 %}
7142
7143 pipe_class vdop64(vecD dst, vecD src1, vecD src2)
7144 %{
7145 single_instruction;
7146 dst : S4(write);
7147 src1 : S2(read);
7148 src2 : S2(read);
7149 INS01 : ISS;
7150 NEON_FP : S4;
7151 %}
7152
7153 pipe_class vdop128(vecX dst, vecX src1, vecX src2)
7154 %{
7155 single_instruction;
7156 dst : S4(write);
7157 src1 : S2(read);
7158 src2 : S2(read);
7159 INS0 : ISS;
7160 NEON_FP : S4;
7161 %}
7162
7163 pipe_class vlogical64(vecD dst, vecD src1, vecD src2)
7164 %{
7165 single_instruction;
7166 dst : S3(write);
7167 src1 : S2(read);
7168 src2 : S2(read);
7169 INS01 : ISS;
7170 NEON_FP : S3;
7171 %}
7172
7173 pipe_class vlogical128(vecX dst, vecX src1, vecX src2)
7174 %{
7175 single_instruction;
7176 dst : S3(write);
7177 src1 : S2(read);
7178 src2 : S2(read);
7179 INS0 : ISS;
7180 NEON_FP : S3;
7181 %}
7182
7183 pipe_class vshift64(vecD dst, vecD src, vecX shift)
7184 %{
7185 single_instruction;
7186 dst : S3(write);
7187 src : S1(read);
7188 shift : S1(read);
7189 INS01 : ISS;
7190 NEON_FP : S3;
7191 %}
7192
7193 pipe_class vshift128(vecX dst, vecX src, vecX shift)
7194 %{
7195 single_instruction;
7196 dst : S3(write);
7197 src : S1(read);
7198 shift : S1(read);
7199 INS0 : ISS;
7200 NEON_FP : S3;
7201 %}
7202
7203 pipe_class vshift64_imm(vecD dst, vecD src, immI shift)
7204 %{
7205 single_instruction;
7206 dst : S3(write);
7207 src : S1(read);
7208 INS01 : ISS;
7209 NEON_FP : S3;
7210 %}
7211
7212 pipe_class vshift128_imm(vecX dst, vecX src, immI shift)
7213 %{
7214 single_instruction;
7215 dst : S3(write);
7216 src : S1(read);
7217 INS0 : ISS;
7218 NEON_FP : S3;
7219 %}
7220
7221 pipe_class vdop_fp64(vecD dst, vecD src1, vecD src2)
7222 %{
7223 single_instruction;
7224 dst : S5(write);
7225 src1 : S1(read);
7226 src2 : S1(read);
7227 INS01 : ISS;
7228 NEON_FP : S5;
7229 %}
7230
7231 pipe_class vdop_fp128(vecX dst, vecX src1, vecX src2)
7232 %{
7233 single_instruction;
7234 dst : S5(write);
7235 src1 : S1(read);
7236 src2 : S1(read);
7237 INS0 : ISS;
7238 NEON_FP : S5;
7239 %}
7240
7241 pipe_class vmuldiv_fp64(vecD dst, vecD src1, vecD src2)
7242 %{
7243 single_instruction;
7244 dst : S5(write);
7245 src1 : S1(read);
7246 src2 : S1(read);
7247 INS0 : ISS;
7248 NEON_FP : S5;
7249 %}
7250
7251 pipe_class vmuldiv_fp128(vecX dst, vecX src1, vecX src2)
7252 %{
7253 single_instruction;
7254 dst : S5(write);
7255 src1 : S1(read);
7256 src2 : S1(read);
7257 INS0 : ISS;
7258 NEON_FP : S5;
7259 %}
7260
7261 pipe_class vsqrt_fp128(vecX dst, vecX src)
7262 %{
7263 single_instruction;
7264 dst : S5(write);
7265 src : S1(read);
7266 INS0 : ISS;
7267 NEON_FP : S5;
7268 %}
7269
7270 pipe_class vunop_fp64(vecD dst, vecD src)
7271 %{
7272 single_instruction;
7273 dst : S5(write);
7274 src : S1(read);
7275 INS01 : ISS;
7276 NEON_FP : S5;
7277 %}
7278
7279 pipe_class vunop_fp128(vecX dst, vecX src)
7280 %{
7281 single_instruction;
7282 dst : S5(write);
7283 src : S1(read);
7284 INS0 : ISS;
7285 NEON_FP : S5;
7286 %}
7287
7288 pipe_class vdup_reg_reg64(vecD dst, iRegI src)
7289 %{
7290 single_instruction;
7291 dst : S3(write);
7292 src : S1(read);
7293 INS01 : ISS;
7294 NEON_FP : S3;
7295 %}
7296
7297 pipe_class vdup_reg_reg128(vecX dst, iRegI src)
7298 %{
7299 single_instruction;
7300 dst : S3(write);
7301 src : S1(read);
7302 INS01 : ISS;
7303 NEON_FP : S3;
7304 %}
7305
7306 pipe_class vdup_reg_freg64(vecD dst, vRegF src)
7307 %{
7308 single_instruction;
7309 dst : S3(write);
7310 src : S1(read);
7311 INS01 : ISS;
7312 NEON_FP : S3;
7313 %}
7314
7315 pipe_class vdup_reg_freg128(vecX dst, vRegF src)
7316 %{
7317 single_instruction;
7318 dst : S3(write);
7319 src : S1(read);
7320 INS01 : ISS;
7321 NEON_FP : S3;
7322 %}
7323
7324 pipe_class vdup_reg_dreg128(vecX dst, vRegD src)
7325 %{
7326 single_instruction;
7327 dst : S3(write);
7328 src : S1(read);
7329 INS01 : ISS;
7330 NEON_FP : S3;
7331 %}
7332
7333 pipe_class vmovi_reg_imm64(vecD dst)
7334 %{
7335 single_instruction;
7336 dst : S3(write);
7337 INS01 : ISS;
7338 NEON_FP : S3;
7339 %}
7340
7341 pipe_class vmovi_reg_imm128(vecX dst)
7342 %{
7343 single_instruction;
7344 dst : S3(write);
7345 INS0 : ISS;
7346 NEON_FP : S3;
7347 %}
7348
7349 pipe_class vload_reg_mem64(vecD dst, vmem8 mem)
7350 %{
7351 single_instruction;
7352 dst : S5(write);
7353 mem : ISS(read);
7354 INS01 : ISS;
7355 NEON_FP : S3;
7356 %}
7357
7358 pipe_class vload_reg_mem128(vecX dst, vmem16 mem)
7359 %{
7360 single_instruction;
7361 dst : S5(write);
7362 mem : ISS(read);
7363 INS01 : ISS;
7364 NEON_FP : S3;
7365 %}
7366
7367 pipe_class vstore_reg_mem64(vecD src, vmem8 mem)
7368 %{
7369 single_instruction;
7370 mem : ISS(read);
7371 src : S2(read);
7372 INS01 : ISS;
7373 NEON_FP : S3;
7374 %}
7375
7376 pipe_class vstore_reg_mem128(vecD src, vmem16 mem)
7377 %{
7378 single_instruction;
7379 mem : ISS(read);
7380 src : S2(read);
7381 INS01 : ISS;
7382 NEON_FP : S3;
7383 %}
7384
7385 //------- Integer ALU operations --------------------------
7386
7387 // Integer ALU reg-reg operation
7388 // Operands needed in EX1, result generated in EX2
7389 // Eg. ADD x0, x1, x2
7390 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
7391 %{
7392 single_instruction;
7393 dst : EX2(write);
7394 src1 : EX1(read);
7395 src2 : EX1(read);
7396 INS01 : ISS; // Dual issue as instruction 0 or 1
7397 ALU : EX2;
7398 %}
7399
7400 // Integer ALU reg-reg operation with constant shift
7401 // Shifted register must be available in LATE_ISS instead of EX1
7402 // Eg. ADD x0, x1, x2, LSL #2
7403 pipe_class ialu_reg_reg_shift(iRegI dst, iRegI src1, iRegI src2, immI shift)
7404 %{
7405 single_instruction;
7406 dst : EX2(write);
7407 src1 : EX1(read);
7408 src2 : ISS(read);
7409 INS01 : ISS;
7410 ALU : EX2;
7411 %}
7412
7413 // Integer ALU reg operation with constant shift
7414 // Eg. LSL x0, x1, #shift
7415 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
7416 %{
7417 single_instruction;
7418 dst : EX2(write);
7419 src1 : ISS(read);
7420 INS01 : ISS;
7421 ALU : EX2;
7422 %}
7423
7424 // Integer ALU reg-reg operation with variable shift
7425 // Both operands must be available in LATE_ISS instead of EX1
7426 // Result is available in EX1 instead of EX2
7427 // Eg. LSLV x0, x1, x2
7428 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
7429 %{
7430 single_instruction;
7431 dst : EX1(write);
7432 src1 : ISS(read);
7433 src2 : ISS(read);
7434 INS01 : ISS;
7435 ALU : EX1;
7436 %}
7437
7438 // Integer ALU reg-reg operation with extract
7439 // As for _vshift above, but result generated in EX2
7440 // Eg. EXTR x0, x1, x2, #N
7441 pipe_class ialu_reg_reg_extr(iRegI dst, iRegI src1, iRegI src2)
7442 %{
7443 single_instruction;
7444 dst : EX2(write);
7445 src1 : ISS(read);
7446 src2 : ISS(read);
7447 INS1 : ISS; // Can only dual issue as Instruction 1
7448 ALU : EX1;
7449 %}
7450
7451 // Integer ALU reg operation
7452 // Eg. NEG x0, x1
7453 pipe_class ialu_reg(iRegI dst, iRegI src)
7454 %{
7455 single_instruction;
7456 dst : EX2(write);
7457 src : EX1(read);
7458 INS01 : ISS;
7459 ALU : EX2;
7460 %}
7461
7462 // Integer ALU reg mmediate operation
7463 // Eg. ADD x0, x1, #N
7464 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
7465 %{
7466 single_instruction;
7467 dst : EX2(write);
7468 src1 : EX1(read);
7469 INS01 : ISS;
7470 ALU : EX2;
7471 %}
7472
7473 // Integer ALU immediate operation (no source operands)
7474 // Eg. MOV x0, #N
7475 pipe_class ialu_imm(iRegI dst)
7476 %{
7477 single_instruction;
7478 dst : EX1(write);
7479 INS01 : ISS;
7480 ALU : EX1;
7481 %}
7482
7483 //------- Compare operation -------------------------------
7484
7485 // Compare reg-reg
7486 // Eg. CMP x0, x1
7487 pipe_class icmp_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
7488 %{
7489 single_instruction;
7490 // fixed_latency(16);
7491 cr : EX2(write);
7492 op1 : EX1(read);
7493 op2 : EX1(read);
7494 INS01 : ISS;
7495 ALU : EX2;
7496 %}
7497
7498 // Compare reg-reg
7499 // Eg. CMP x0, #N
7500 pipe_class icmp_reg_imm(rFlagsReg cr, iRegI op1)
7501 %{
7502 single_instruction;
7503 // fixed_latency(16);
7504 cr : EX2(write);
7505 op1 : EX1(read);
7506 INS01 : ISS;
7507 ALU : EX2;
7508 %}
7509
7510 //------- Conditional instructions ------------------------
7511
7512 // Conditional no operands
7513 // Eg. CSINC x0, zr, zr, <cond>
7514 pipe_class icond_none(iRegI dst, rFlagsReg cr)
7515 %{
7516 single_instruction;
7517 cr : EX1(read);
7518 dst : EX2(write);
7519 INS01 : ISS;
7520 ALU : EX2;
7521 %}
7522
7523 // Conditional 2 operand
7524 // EG. CSEL X0, X1, X2, <cond>
7525 pipe_class icond_reg_reg(iRegI dst, iRegI src1, iRegI src2, rFlagsReg cr)
7526 %{
7527 single_instruction;
7528 cr : EX1(read);
7529 src1 : EX1(read);
7530 src2 : EX1(read);
7531 dst : EX2(write);
7532 INS01 : ISS;
7533 ALU : EX2;
7534 %}
7535
7536 // Conditional 2 operand
7537 // EG. CSEL X0, X1, X2, <cond>
7538 pipe_class icond_reg(iRegI dst, iRegI src, rFlagsReg cr)
7539 %{
7540 single_instruction;
7541 cr : EX1(read);
7542 src : EX1(read);
7543 dst : EX2(write);
7544 INS01 : ISS;
7545 ALU : EX2;
7546 %}
7547
7548 //------- Multiply pipeline operations --------------------
7549
7550 // Multiply reg-reg
7551 // Eg. MUL w0, w1, w2
7552 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
7553 %{
7554 single_instruction;
7555 dst : WR(write);
7556 src1 : ISS(read);
7557 src2 : ISS(read);
7558 INS01 : ISS;
7559 MAC : WR;
7560 %}
7561
7562 // Multiply accumulate
7563 // Eg. MADD w0, w1, w2, w3
7564 pipe_class imac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
7565 %{
7566 single_instruction;
7567 dst : WR(write);
7568 src1 : ISS(read);
7569 src2 : ISS(read);
7570 src3 : ISS(read);
7571 INS01 : ISS;
7572 MAC : WR;
7573 %}
7574
7575 // Eg. MUL w0, w1, w2
7576 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
7577 %{
7578 single_instruction;
7579 fixed_latency(3); // Maximum latency for 64 bit mul
7580 dst : WR(write);
7581 src1 : ISS(read);
7582 src2 : ISS(read);
7583 INS01 : ISS;
7584 MAC : WR;
7585 %}
7586
7587 // Multiply accumulate
7588 // Eg. MADD w0, w1, w2, w3
7589 pipe_class lmac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
7590 %{
7591 single_instruction;
7592 fixed_latency(3); // Maximum latency for 64 bit mul
7593 dst : WR(write);
7594 src1 : ISS(read);
7595 src2 : ISS(read);
7596 src3 : ISS(read);
7597 INS01 : ISS;
7598 MAC : WR;
7599 %}
7600
7601 //------- Divide pipeline operations --------------------
7602
7603 // Eg. SDIV w0, w1, w2
7604 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
7605 %{
7606 single_instruction;
7607 fixed_latency(8); // Maximum latency for 32 bit divide
7608 dst : WR(write);
7609 src1 : ISS(read);
7610 src2 : ISS(read);
7611 INS0 : ISS; // Can only dual issue as instruction 0
7612 DIV : WR;
7613 %}
7614
7615 // Eg. SDIV x0, x1, x2
7616 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
7617 %{
7618 single_instruction;
7619 fixed_latency(16); // Maximum latency for 64 bit divide
7620 dst : WR(write);
7621 src1 : ISS(read);
7622 src2 : ISS(read);
7623 INS0 : ISS; // Can only dual issue as instruction 0
7624 DIV : WR;
7625 %}
7626
7627 //------- Load pipeline operations ------------------------
7628
7629 // Load - prefetch
7630 // Eg. PFRM <mem>
7631 pipe_class iload_prefetch(memory mem)
7632 %{
7633 single_instruction;
7634 mem : ISS(read);
7635 INS01 : ISS;
7636 LDST : WR;
7637 %}
7638
7639 // Load - reg, mem
7640 // Eg. LDR x0, <mem>
7641 pipe_class iload_reg_mem(iRegI dst, memory mem)
7642 %{
7643 single_instruction;
7644 dst : WR(write);
7645 mem : ISS(read);
7646 INS01 : ISS;
7647 LDST : WR;
7648 %}
7649
7650 // Load - reg, reg
7651 // Eg. LDR x0, [sp, x1]
7652 pipe_class iload_reg_reg(iRegI dst, iRegI src)
7653 %{
7654 single_instruction;
7655 dst : WR(write);
7656 src : ISS(read);
7657 INS01 : ISS;
7658 LDST : WR;
7659 %}
7660
7661 //------- Store pipeline operations -----------------------
7662
7663 // Store - zr, mem
7664 // Eg. STR zr, <mem>
7665 pipe_class istore_mem(memory mem)
7666 %{
7667 single_instruction;
7668 mem : ISS(read);
7669 INS01 : ISS;
7670 LDST : WR;
7671 %}
7672
7673 // Store - reg, mem
7674 // Eg. STR x0, <mem>
7675 pipe_class istore_reg_mem(iRegI src, memory mem)
7676 %{
7677 single_instruction;
7678 mem : ISS(read);
7679 src : EX2(read);
7680 INS01 : ISS;
7681 LDST : WR;
7682 %}
7683
7684 // Store - reg, reg
7685 // Eg. STR x0, [sp, x1]
7686 pipe_class istore_reg_reg(iRegI dst, iRegI src)
7687 %{
7688 single_instruction;
7689 dst : ISS(read);
7690 src : EX2(read);
7691 INS01 : ISS;
7692 LDST : WR;
7693 %}
7694
7695 //------- Store pipeline operations -----------------------
7696
7697 // Branch
7698 pipe_class pipe_branch()
7699 %{
7700 single_instruction;
7701 INS01 : ISS;
7702 BRANCH : EX1;
7703 %}
7704
7705 // Conditional branch
7706 pipe_class pipe_branch_cond(rFlagsReg cr)
7707 %{
7708 single_instruction;
7709 cr : EX1(read);
7710 INS01 : ISS;
7711 BRANCH : EX1;
7712 %}
7713
7714 // Compare & Branch
7715 // EG. CBZ/CBNZ
7716 pipe_class pipe_cmp_branch(iRegI op1)
7717 %{
7718 single_instruction;
7719 op1 : EX1(read);
7720 INS01 : ISS;
7721 BRANCH : EX1;
7722 %}
7723
7724 //------- Synchronisation operations ----------------------
7725
7726 // Any operation requiring serialization.
7727 // EG. DMB/Atomic Ops/Load Acquire/Str Release
7728 pipe_class pipe_serial()
7729 %{
7730 single_instruction;
7731 force_serialization;
7732 fixed_latency(16);
7733 INS01 : ISS(2); // Cannot dual issue with any other instruction
7734 LDST : WR;
7735 %}
7736
7737 // Generic big/slow expanded idiom - also serialized
7738 pipe_class pipe_slow()
7739 %{
7740 instruction_count(10);
7741 multiple_bundles;
7742 force_serialization;
7743 fixed_latency(16);
7744 INS01 : ISS(2); // Cannot dual issue with any other instruction
7745 LDST : WR;
7746 %}
7747
7748 // Empty pipeline class
7749 pipe_class pipe_class_empty()
7750 %{
7751 single_instruction;
7752 fixed_latency(0);
7753 %}
7754
7755 // Default pipeline class.
7756 pipe_class pipe_class_default()
7757 %{
7758 single_instruction;
7759 fixed_latency(2);
7760 %}
7761
7762 // Pipeline class for compares.
7763 pipe_class pipe_class_compare()
7764 %{
7765 single_instruction;
7766 fixed_latency(16);
7767 %}
7768
7769 // Pipeline class for memory operations.
7770 pipe_class pipe_class_memory()
7771 %{
7772 single_instruction;
7773 fixed_latency(16);
7774 %}
7775
7776 // Pipeline class for call.
7777 pipe_class pipe_class_call()
7778 %{
7779 single_instruction;
7780 fixed_latency(100);
7781 %}
7782
7783 // Define the class for the Nop node.
7784 define %{
7785 MachNop = pipe_class_empty;
7786 %}
7787
7788 %}
7789 //----------INSTRUCTIONS-------------------------------------------------------
7790 //
7791 // match -- States which machine-independent subtree may be replaced
7792 // by this instruction.
7793 // ins_cost -- The estimated cost of this instruction is used by instruction
7794 // selection to identify a minimum cost tree of machine
7795 // instructions that matches a tree of machine-independent
7796 // instructions.
7797 // format -- A string providing the disassembly for this instruction.
7798 // The value of an instruction's operand may be inserted
7799 // by referring to it with a '$' prefix.
7800 // opcode -- Three instruction opcodes may be provided. These are referred
7801 // to within an encode class as $primary, $secondary, and $tertiary
7802 // rrspectively. The primary opcode is commonly used to
7803 // indicate the type of machine instruction, while secondary
7804 // and tertiary are often used for prefix options or addressing
7805 // modes.
7806 // ins_encode -- A list of encode classes with parameters. The encode class
7807 // name must have been defined in an 'enc_class' specification
7808 // in the encode section of the architecture description.
7809
7810 // ============================================================================
7811 // Memory (Load/Store) Instructions
7812
7813 // Load Instructions
7814
7815 // Load Byte (8 bit signed)
7816 instruct loadB(iRegINoSp dst, memory mem)
7817 %{
7818 match(Set dst (LoadB mem));
7819 predicate(!needs_acquiring_load(n));
7820
7821 ins_cost(4 * INSN_COST);
7822 format %{ "ldrsbw $dst, $mem\t# byte" %}
7823
7824 ins_encode(aarch64_enc_ldrsbw(dst, mem));
7825
7826 ins_pipe(iload_reg_mem);
7827 %}
7828
7829 // Load Byte (8 bit signed) into long
7830 instruct loadB2L(iRegLNoSp dst, memory mem)
7831 %{
7832 match(Set dst (ConvI2L (LoadB mem)));
7833 predicate(!needs_acquiring_load(n->in(1)));
7834
7835 ins_cost(4 * INSN_COST);
7836 format %{ "ldrsb $dst, $mem\t# byte" %}
7837
7838 ins_encode(aarch64_enc_ldrsb(dst, mem));
7839
7840 ins_pipe(iload_reg_mem);
7841 %}
7842
7843 // Load Byte (8 bit unsigned)
7844 instruct loadUB(iRegINoSp dst, memory mem)
7845 %{
7846 match(Set dst (LoadUB mem));
7847 predicate(!needs_acquiring_load(n));
7848
7849 ins_cost(4 * INSN_COST);
7850 format %{ "ldrbw $dst, $mem\t# byte" %}
7851
7852 ins_encode(aarch64_enc_ldrb(dst, mem));
7853
7854 ins_pipe(iload_reg_mem);
7855 %}
7856
7857 // Load Byte (8 bit unsigned) into long
7858 instruct loadUB2L(iRegLNoSp dst, memory mem)
7859 %{
7860 match(Set dst (ConvI2L (LoadUB mem)));
7861 predicate(!needs_acquiring_load(n->in(1)));
7862
7863 ins_cost(4 * INSN_COST);
7864 format %{ "ldrb $dst, $mem\t# byte" %}
7865
7866 ins_encode(aarch64_enc_ldrb(dst, mem));
7867
7868 ins_pipe(iload_reg_mem);
7869 %}
7870
7871 // Load Short (16 bit signed)
7872 instruct loadS(iRegINoSp dst, memory mem)
7873 %{
7874 match(Set dst (LoadS mem));
7875 predicate(!needs_acquiring_load(n));
7876
7877 ins_cost(4 * INSN_COST);
7878 format %{ "ldrshw $dst, $mem\t# short" %}
7879
7880 ins_encode(aarch64_enc_ldrshw(dst, mem));
7881
7882 ins_pipe(iload_reg_mem);
7883 %}
7884
7885 // Load Short (16 bit signed) into long
7886 instruct loadS2L(iRegLNoSp dst, memory mem)
7887 %{
7888 match(Set dst (ConvI2L (LoadS mem)));
7889 predicate(!needs_acquiring_load(n->in(1)));
7890
7891 ins_cost(4 * INSN_COST);
7892 format %{ "ldrsh $dst, $mem\t# short" %}
7893
7894 ins_encode(aarch64_enc_ldrsh(dst, mem));
7895
7896 ins_pipe(iload_reg_mem);
7897 %}
7898
7899 // Load Char (16 bit unsigned)
7900 instruct loadUS(iRegINoSp dst, memory mem)
7901 %{
7902 match(Set dst (LoadUS mem));
7903 predicate(!needs_acquiring_load(n));
7904
7905 ins_cost(4 * INSN_COST);
7906 format %{ "ldrh $dst, $mem\t# short" %}
7907
7908 ins_encode(aarch64_enc_ldrh(dst, mem));
7909
7910 ins_pipe(iload_reg_mem);
7911 %}
7912
7913 // Load Short/Char (16 bit unsigned) into long
7914 instruct loadUS2L(iRegLNoSp dst, memory mem)
7915 %{
7916 match(Set dst (ConvI2L (LoadUS mem)));
7917 predicate(!needs_acquiring_load(n->in(1)));
7918
7919 ins_cost(4 * INSN_COST);
7920 format %{ "ldrh $dst, $mem\t# short" %}
7921
7922 ins_encode(aarch64_enc_ldrh(dst, mem));
7923
7924 ins_pipe(iload_reg_mem);
7925 %}
7926
7927 // Load Integer (32 bit signed)
7928 instruct loadI(iRegINoSp dst, memory mem)
7929 %{
7930 match(Set dst (LoadI mem));
7931 predicate(!needs_acquiring_load(n));
7932
7933 ins_cost(4 * INSN_COST);
7934 format %{ "ldrw $dst, $mem\t# int" %}
7935
7936 ins_encode(aarch64_enc_ldrw(dst, mem));
7937
7938 ins_pipe(iload_reg_mem);
7939 %}
7940
7941 // Load Integer (32 bit signed) into long
7942 instruct loadI2L(iRegLNoSp dst, memory mem)
7943 %{
7944 match(Set dst (ConvI2L (LoadI mem)));
7945 predicate(!needs_acquiring_load(n->in(1)));
7946
7947 ins_cost(4 * INSN_COST);
7948 format %{ "ldrsw $dst, $mem\t# int" %}
7949
7950 ins_encode(aarch64_enc_ldrsw(dst, mem));
7951
7952 ins_pipe(iload_reg_mem);
7953 %}
7954
7955 // Load Integer (32 bit unsigned) into long
7956 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
7957 %{
7958 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
7959 predicate(!needs_acquiring_load(n->in(1)->in(1)->as_Load()));
7960
7961 ins_cost(4 * INSN_COST);
7962 format %{ "ldrw $dst, $mem\t# int" %}
7963
7964 ins_encode(aarch64_enc_ldrw(dst, mem));
7965
7966 ins_pipe(iload_reg_mem);
7967 %}
7968
7969 // Load Long (64 bit signed)
7970 instruct loadL(iRegLNoSp dst, memory mem)
7971 %{
7972 match(Set dst (LoadL mem));
7973 predicate(!needs_acquiring_load(n));
7974
7975 ins_cost(4 * INSN_COST);
7976 format %{ "ldr $dst, $mem\t# int" %}
7977
7978 ins_encode(aarch64_enc_ldr(dst, mem));
7979
7980 ins_pipe(iload_reg_mem);
7981 %}
7982
7983 // Load Range
7984 instruct loadRange(iRegINoSp dst, memory mem)
7985 %{
7986 match(Set dst (LoadRange mem));
7987
7988 ins_cost(4 * INSN_COST);
7989 format %{ "ldrw $dst, $mem\t# range" %}
7990
7991 ins_encode(aarch64_enc_ldrw(dst, mem));
7992
7993 ins_pipe(iload_reg_mem);
7994 %}
7995
7996 // Load Pointer
7997 instruct loadP(iRegPNoSp dst, memory mem)
7998 %{
7999 match(Set dst (LoadP mem));
8000 predicate(!needs_acquiring_load(n));
8001
8002 ins_cost(4 * INSN_COST);
8003 format %{ "ldr $dst, $mem\t# ptr" %}
8004
8005 ins_encode(aarch64_enc_ldr(dst, mem));
8006
8007 ins_pipe(iload_reg_mem);
8008 %}
8009
8010 // Load Compressed Pointer
8011 instruct loadN(iRegNNoSp dst, memory mem)
8012 %{
8013 match(Set dst (LoadN mem));
8014 predicate(!needs_acquiring_load(n));
8015
8016 ins_cost(4 * INSN_COST);
8017 format %{ "ldrw $dst, $mem\t# compressed ptr" %}
8018
8019 ins_encode(aarch64_enc_ldrw(dst, mem));
8020
8021 ins_pipe(iload_reg_mem);
8022 %}
8023
8024 // Load Klass Pointer
8025 instruct loadKlass(iRegPNoSp dst, memory mem)
8026 %{
8027 match(Set dst (LoadKlass mem));
8028 predicate(!needs_acquiring_load(n));
8029
8030 ins_cost(4 * INSN_COST);
8031 format %{ "ldr $dst, $mem\t# class" %}
8032
8033 ins_encode(aarch64_enc_ldr(dst, mem));
8034
8035 ins_pipe(iload_reg_mem);
8036 %}
8037
8038 // Load Narrow Klass Pointer
8039 instruct loadNKlass(iRegNNoSp dst, memory mem)
8040 %{
8041 match(Set dst (LoadNKlass mem));
8042 predicate(!needs_acquiring_load(n));
8043
8044 ins_cost(4 * INSN_COST);
8045 format %{ "ldrw $dst, $mem\t# compressed class ptr" %}
8046
8047 ins_encode(aarch64_enc_ldrw(dst, mem));
8048
8049 ins_pipe(iload_reg_mem);
8050 %}
8051
8052 // Load Float
8053 instruct loadF(vRegF dst, memory mem)
8054 %{
8055 match(Set dst (LoadF mem));
8056 predicate(!needs_acquiring_load(n));
8057
8058 ins_cost(4 * INSN_COST);
8059 format %{ "ldrs $dst, $mem\t# float" %}
8060
8061 ins_encode( aarch64_enc_ldrs(dst, mem) );
8062
8063 ins_pipe(pipe_class_memory);
8064 %}
8065
8066 // Load Double
8067 instruct loadD(vRegD dst, memory mem)
8068 %{
8069 match(Set dst (LoadD mem));
8070 predicate(!needs_acquiring_load(n));
8071
8072 ins_cost(4 * INSN_COST);
8073 format %{ "ldrd $dst, $mem\t# double" %}
8074
8075 ins_encode( aarch64_enc_ldrd(dst, mem) );
8076
8077 ins_pipe(pipe_class_memory);
8078 %}
8079
8080
8081 // Load Int Constant
8082 instruct loadConI(iRegINoSp dst, immI src)
8083 %{
8084 match(Set dst src);
8085
8086 ins_cost(INSN_COST);
8087 format %{ "mov $dst, $src\t# int" %}
8088
8089 ins_encode( aarch64_enc_movw_imm(dst, src) );
8090
8091 ins_pipe(ialu_imm);
8092 %}
8093
8094 // Load Long Constant
8095 instruct loadConL(iRegLNoSp dst, immL src)
8096 %{
8097 match(Set dst src);
8098
8099 ins_cost(INSN_COST);
8100 format %{ "mov $dst, $src\t# long" %}
8101
8102 ins_encode( aarch64_enc_mov_imm(dst, src) );
8103
8104 ins_pipe(ialu_imm);
8105 %}
8106
8107 // Load Pointer Constant
8108
8109 instruct loadConP(iRegPNoSp dst, immP con)
8110 %{
8111 match(Set dst con);
8112
8113 ins_cost(INSN_COST * 4);
8114 format %{
8115 "mov $dst, $con\t# ptr\n\t"
8116 %}
8117
8118 ins_encode(aarch64_enc_mov_p(dst, con));
8119
8120 ins_pipe(ialu_imm);
8121 %}
8122
8123 // Load Null Pointer Constant
8124
8125 instruct loadConP0(iRegPNoSp dst, immP0 con)
8126 %{
8127 match(Set dst con);
8128
8129 ins_cost(INSN_COST);
8130 format %{ "mov $dst, $con\t# NULL ptr" %}
8131
8132 ins_encode(aarch64_enc_mov_p0(dst, con));
8133
8134 ins_pipe(ialu_imm);
8135 %}
8136
8137 // Load Pointer Constant One
8138
8139 instruct loadConP1(iRegPNoSp dst, immP_1 con)
8140 %{
8141 match(Set dst con);
8142
8143 ins_cost(INSN_COST);
8144 format %{ "mov $dst, $con\t# NULL ptr" %}
8145
8146 ins_encode(aarch64_enc_mov_p1(dst, con));
8147
8148 ins_pipe(ialu_imm);
8149 %}
8150
8151 // Load Poll Page Constant
8152
8153 instruct loadConPollPage(iRegPNoSp dst, immPollPage con)
8154 %{
8155 match(Set dst con);
8156
8157 ins_cost(INSN_COST);
8158 format %{ "adr $dst, $con\t# Poll Page Ptr" %}
8159
8160 ins_encode(aarch64_enc_mov_poll_page(dst, con));
8161
8162 ins_pipe(ialu_imm);
8163 %}
8164
8165 // Load Byte Map Base Constant
8166
8167 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
8168 %{
8169 match(Set dst con);
8170
8171 ins_cost(INSN_COST);
8172 format %{ "adr $dst, $con\t# Byte Map Base" %}
8173
8174 ins_encode(aarch64_enc_mov_byte_map_base(dst, con));
8175
8176 ins_pipe(ialu_imm);
8177 %}
8178
8179 // Load Narrow Pointer Constant
8180
8181 instruct loadConN(iRegNNoSp dst, immN con)
8182 %{
8183 match(Set dst con);
8184
8185 ins_cost(INSN_COST * 4);
8186 format %{ "mov $dst, $con\t# compressed ptr" %}
8187
8188 ins_encode(aarch64_enc_mov_n(dst, con));
8189
8190 ins_pipe(ialu_imm);
8191 %}
8192
8193 // Load Narrow Null Pointer Constant
8194
8195 instruct loadConN0(iRegNNoSp dst, immN0 con)
8196 %{
8197 match(Set dst con);
8198
8199 ins_cost(INSN_COST);
8200 format %{ "mov $dst, $con\t# compressed NULL ptr" %}
8201
8202 ins_encode(aarch64_enc_mov_n0(dst, con));
8203
8204 ins_pipe(ialu_imm);
8205 %}
8206
8207 // Load Narrow Klass Constant
8208
8209 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
8210 %{
8211 match(Set dst con);
8212
8213 ins_cost(INSN_COST);
8214 format %{ "mov $dst, $con\t# compressed klass ptr" %}
8215
8216 ins_encode(aarch64_enc_mov_nk(dst, con));
8217
8218 ins_pipe(ialu_imm);
8219 %}
8220
8221 // Load Packed Float Constant
8222
8223 instruct loadConF_packed(vRegF dst, immFPacked con) %{
8224 match(Set dst con);
8225 ins_cost(INSN_COST * 4);
8226 format %{ "fmovs $dst, $con"%}
8227 ins_encode %{
8228 __ fmovs(as_FloatRegister($dst$$reg), (double)$con$$constant);
8229 %}
8230
8231 ins_pipe(fp_imm_s);
8232 %}
8233
8234 // Load Float Constant
8235
8236 instruct loadConF(vRegF dst, immF con) %{
8237 match(Set dst con);
8238
8239 ins_cost(INSN_COST * 4);
8240
8241 format %{
8242 "ldrs $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
8243 %}
8244
8245 ins_encode %{
8246 __ ldrs(as_FloatRegister($dst$$reg), $constantaddress($con));
8247 %}
8248
8249 ins_pipe(fp_load_constant_s);
8250 %}
8251
8252 // Load Packed Double Constant
8253
8254 instruct loadConD_packed(vRegD dst, immDPacked con) %{
8255 match(Set dst con);
8256 ins_cost(INSN_COST);
8257 format %{ "fmovd $dst, $con"%}
8258 ins_encode %{
8259 __ fmovd(as_FloatRegister($dst$$reg), $con$$constant);
8260 %}
8261
8262 ins_pipe(fp_imm_d);
8263 %}
8264
8265 // Load Double Constant
8266
8267 instruct loadConD(vRegD dst, immD con) %{
8268 match(Set dst con);
8269
8270 ins_cost(INSN_COST * 5);
8271 format %{
8272 "ldrd $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
8273 %}
8274
8275 ins_encode %{
8276 __ ldrd(as_FloatRegister($dst$$reg), $constantaddress($con));
8277 %}
8278
8279 ins_pipe(fp_load_constant_d);
8280 %}
8281
8282 // Store Instructions
8283
8284 // Store CMS card-mark Immediate
8285 instruct storeimmCM0(immI0 zero, memory mem)
8286 %{
8287 match(Set mem (StoreCM mem zero));
8288 predicate(unnecessary_storestore(n));
8289
8290 ins_cost(INSN_COST);
8291 format %{ "strb zr, $mem\t# byte" %}
8292
8293 ins_encode(aarch64_enc_strb0(mem));
8294
8295 ins_pipe(istore_mem);
8296 %}
8297
8298 // Store CMS card-mark Immediate with intervening StoreStore
8299 // needed when using CMS with no conditional card marking
8300 instruct storeimmCM0_ordered(immI0 zero, memory mem)
8301 %{
8302 match(Set mem (StoreCM mem zero));
8303
8304 ins_cost(INSN_COST * 2);
8305 format %{ "dmb ishst"
8306 "\n\tstrb zr, $mem\t# byte" %}
8307
8308 ins_encode(aarch64_enc_strb0_ordered(mem));
8309
8310 ins_pipe(istore_mem);
8311 %}
8312
8313 // Store Byte
8314 instruct storeB(iRegIorL2I src, memory mem)
8315 %{
8316 match(Set mem (StoreB mem src));
8317 predicate(!needs_releasing_store(n));
8318
8319 ins_cost(INSN_COST);
8320 format %{ "strb $src, $mem\t# byte" %}
8321
8322 ins_encode(aarch64_enc_strb(src, mem));
8323
8324 ins_pipe(istore_reg_mem);
8325 %}
8326
8327
8328 instruct storeimmB0(immI0 zero, memory mem)
8329 %{
8330 match(Set mem (StoreB mem zero));
8331 predicate(!needs_releasing_store(n));
8332
8333 ins_cost(INSN_COST);
8334 format %{ "strb rscractch2, $mem\t# byte" %}
8335
8336 ins_encode(aarch64_enc_strb0(mem));
8337
8338 ins_pipe(istore_mem);
8339 %}
8340
8341 // Store Char/Short
8342 instruct storeC(iRegIorL2I src, memory mem)
8343 %{
8344 match(Set mem (StoreC mem src));
8345 predicate(!needs_releasing_store(n));
8346
8347 ins_cost(INSN_COST);
8348 format %{ "strh $src, $mem\t# short" %}
8349
8350 ins_encode(aarch64_enc_strh(src, mem));
8351
8352 ins_pipe(istore_reg_mem);
8353 %}
8354
8355 instruct storeimmC0(immI0 zero, memory mem)
8356 %{
8357 match(Set mem (StoreC mem zero));
8358 predicate(!needs_releasing_store(n));
8359
8360 ins_cost(INSN_COST);
8361 format %{ "strh zr, $mem\t# short" %}
8362
8363 ins_encode(aarch64_enc_strh0(mem));
8364
8365 ins_pipe(istore_mem);
8366 %}
8367
8368 // Store Integer
8369
8370 instruct storeI(iRegIorL2I src, memory mem)
8371 %{
8372 match(Set mem(StoreI mem src));
8373 predicate(!needs_releasing_store(n));
8374
8375 ins_cost(INSN_COST);
8376 format %{ "strw $src, $mem\t# int" %}
8377
8378 ins_encode(aarch64_enc_strw(src, mem));
8379
8380 ins_pipe(istore_reg_mem);
8381 %}
8382
8383 instruct storeimmI0(immI0 zero, memory mem)
8384 %{
8385 match(Set mem(StoreI mem zero));
8386 predicate(!needs_releasing_store(n));
8387
8388 ins_cost(INSN_COST);
8389 format %{ "strw zr, $mem\t# int" %}
8390
8391 ins_encode(aarch64_enc_strw0(mem));
8392
8393 ins_pipe(istore_mem);
8394 %}
8395
8396 // Store Long (64 bit signed)
8397 instruct storeL(iRegL src, memory mem)
8398 %{
8399 match(Set mem (StoreL mem src));
8400 predicate(!needs_releasing_store(n));
8401
8402 ins_cost(INSN_COST);
8403 format %{ "str $src, $mem\t# int" %}
8404
8405 ins_encode(aarch64_enc_str(src, mem));
8406
8407 ins_pipe(istore_reg_mem);
8408 %}
8409
8410 // Store Long (64 bit signed)
8411 instruct storeimmL0(immL0 zero, memory mem)
8412 %{
8413 match(Set mem (StoreL mem zero));
8414 predicate(!needs_releasing_store(n));
8415
8416 ins_cost(INSN_COST);
8417 format %{ "str zr, $mem\t# int" %}
8418
8419 ins_encode(aarch64_enc_str0(mem));
8420
8421 ins_pipe(istore_mem);
8422 %}
8423
8424 // Store Pointer
8425 instruct storeP(iRegP src, memory mem)
8426 %{
8427 match(Set mem (StoreP mem src));
8428 predicate(!needs_releasing_store(n));
8429
8430 ins_cost(INSN_COST);
8431 format %{ "str $src, $mem\t# ptr" %}
8432
8433 ins_encode(aarch64_enc_str(src, mem));
8434
8435 ins_pipe(istore_reg_mem);
8436 %}
8437
8438 // Store Pointer
8439 instruct storeimmP0(immP0 zero, memory mem)
8440 %{
8441 match(Set mem (StoreP mem zero));
8442 predicate(!needs_releasing_store(n));
8443
8444 ins_cost(INSN_COST);
8445 format %{ "str zr, $mem\t# ptr" %}
8446
8447 ins_encode(aarch64_enc_str0(mem));
8448
8449 ins_pipe(istore_mem);
8450 %}
8451
8452 // Store Compressed Pointer
8453 instruct storeN(iRegN src, memory mem)
8454 %{
8455 match(Set mem (StoreN mem src));
8456 predicate(!needs_releasing_store(n));
8457
8458 ins_cost(INSN_COST);
8459 format %{ "strw $src, $mem\t# compressed ptr" %}
8460
8461 ins_encode(aarch64_enc_strw(src, mem));
8462
8463 ins_pipe(istore_reg_mem);
8464 %}
8465
8466 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
8467 %{
8468 match(Set mem (StoreN mem zero));
8469 predicate(Universe::narrow_oop_base() == NULL &&
8470 Universe::narrow_klass_base() == NULL &&
8471 (!needs_releasing_store(n)));
8472
8473 ins_cost(INSN_COST);
8474 format %{ "strw rheapbase, $mem\t# compressed ptr (rheapbase==0)" %}
8475
8476 ins_encode(aarch64_enc_strw(heapbase, mem));
8477
8478 ins_pipe(istore_reg_mem);
8479 %}
8480
8481 // Store Float
8482 instruct storeF(vRegF src, memory mem)
8483 %{
8484 match(Set mem (StoreF mem src));
8485 predicate(!needs_releasing_store(n));
8486
8487 ins_cost(INSN_COST);
8488 format %{ "strs $src, $mem\t# float" %}
8489
8490 ins_encode( aarch64_enc_strs(src, mem) );
8491
8492 ins_pipe(pipe_class_memory);
8493 %}
8494
8495 // TODO
8496 // implement storeImmF0 and storeFImmPacked
8497
8498 // Store Double
8499 instruct storeD(vRegD src, memory mem)
8500 %{
8501 match(Set mem (StoreD mem src));
8502 predicate(!needs_releasing_store(n));
8503
8504 ins_cost(INSN_COST);
8505 format %{ "strd $src, $mem\t# double" %}
8506
8507 ins_encode( aarch64_enc_strd(src, mem) );
8508
8509 ins_pipe(pipe_class_memory);
8510 %}
8511
8512 // Store Compressed Klass Pointer
8513 instruct storeNKlass(iRegN src, memory mem)
8514 %{
8515 predicate(!needs_releasing_store(n));
8516 match(Set mem (StoreNKlass mem src));
8517
8518 ins_cost(INSN_COST);
8519 format %{ "strw $src, $mem\t# compressed klass ptr" %}
8520
8521 ins_encode(aarch64_enc_strw(src, mem));
8522
8523 ins_pipe(istore_reg_mem);
8524 %}
8525
8526 // TODO
8527 // implement storeImmD0 and storeDImmPacked
8528
8529 // prefetch instructions
8530 // Must be safe to execute with invalid address (cannot fault).
8531
8532 instruct prefetchalloc( memory mem ) %{
8533 match(PrefetchAllocation mem);
8534
8535 ins_cost(INSN_COST);
8536 format %{ "prfm $mem, PSTL1KEEP\t# Prefetch into level 1 cache write keep" %}
8537
8538 ins_encode( aarch64_enc_prefetchw(mem) );
8539
8540 ins_pipe(iload_prefetch);
8541 %}
8542
8543 // ---------------- volatile loads and stores ----------------
8544
8545 // Load Byte (8 bit signed)
8546 instruct loadB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
8547 %{
8548 match(Set dst (LoadB mem));
8549
8550 ins_cost(VOLATILE_REF_COST);
8551 format %{ "ldarsb $dst, $mem\t# byte" %}
8552
8553 ins_encode(aarch64_enc_ldarsb(dst, mem));
8554
8555 ins_pipe(pipe_serial);
8556 %}
8557
8558 // Load Byte (8 bit signed) into long
8559 instruct loadB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
8560 %{
8561 match(Set dst (ConvI2L (LoadB mem)));
8562
8563 ins_cost(VOLATILE_REF_COST);
8564 format %{ "ldarsb $dst, $mem\t# byte" %}
8565
8566 ins_encode(aarch64_enc_ldarsb(dst, mem));
8567
8568 ins_pipe(pipe_serial);
8569 %}
8570
8571 // Load Byte (8 bit unsigned)
8572 instruct loadUB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
8573 %{
8574 match(Set dst (LoadUB mem));
8575
8576 ins_cost(VOLATILE_REF_COST);
8577 format %{ "ldarb $dst, $mem\t# byte" %}
8578
8579 ins_encode(aarch64_enc_ldarb(dst, mem));
8580
8581 ins_pipe(pipe_serial);
8582 %}
8583
8584 // Load Byte (8 bit unsigned) into long
8585 instruct loadUB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
8586 %{
8587 match(Set dst (ConvI2L (LoadUB mem)));
8588
8589 ins_cost(VOLATILE_REF_COST);
8590 format %{ "ldarb $dst, $mem\t# byte" %}
8591
8592 ins_encode(aarch64_enc_ldarb(dst, mem));
8593
8594 ins_pipe(pipe_serial);
8595 %}
8596
8597 // Load Short (16 bit signed)
8598 instruct loadS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
8599 %{
8600 match(Set dst (LoadS mem));
8601
8602 ins_cost(VOLATILE_REF_COST);
8603 format %{ "ldarshw $dst, $mem\t# short" %}
8604
8605 ins_encode(aarch64_enc_ldarshw(dst, mem));
8606
8607 ins_pipe(pipe_serial);
8608 %}
8609
8610 instruct loadUS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
8611 %{
8612 match(Set dst (LoadUS mem));
8613
8614 ins_cost(VOLATILE_REF_COST);
8615 format %{ "ldarhw $dst, $mem\t# short" %}
8616
8617 ins_encode(aarch64_enc_ldarhw(dst, mem));
8618
8619 ins_pipe(pipe_serial);
8620 %}
8621
8622 // Load Short/Char (16 bit unsigned) into long
8623 instruct loadUS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
8624 %{
8625 match(Set dst (ConvI2L (LoadUS mem)));
8626
8627 ins_cost(VOLATILE_REF_COST);
8628 format %{ "ldarh $dst, $mem\t# short" %}
8629
8630 ins_encode(aarch64_enc_ldarh(dst, mem));
8631
8632 ins_pipe(pipe_serial);
8633 %}
8634
8635 // Load Short/Char (16 bit signed) into long
8636 instruct loadS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
8637 %{
8638 match(Set dst (ConvI2L (LoadS mem)));
8639
8640 ins_cost(VOLATILE_REF_COST);
8641 format %{ "ldarh $dst, $mem\t# short" %}
8642
8643 ins_encode(aarch64_enc_ldarsh(dst, mem));
8644
8645 ins_pipe(pipe_serial);
8646 %}
8647
8648 // Load Integer (32 bit signed)
8649 instruct loadI_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
8650 %{
8651 match(Set dst (LoadI mem));
8652
8653 ins_cost(VOLATILE_REF_COST);
8654 format %{ "ldarw $dst, $mem\t# int" %}
8655
8656 ins_encode(aarch64_enc_ldarw(dst, mem));
8657
8658 ins_pipe(pipe_serial);
8659 %}
8660
8661 // Load Integer (32 bit unsigned) into long
8662 instruct loadUI2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem, immL_32bits mask)
8663 %{
8664 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
8665
8666 ins_cost(VOLATILE_REF_COST);
8667 format %{ "ldarw $dst, $mem\t# int" %}
8668
8669 ins_encode(aarch64_enc_ldarw(dst, mem));
8670
8671 ins_pipe(pipe_serial);
8672 %}
8673
8674 // Load Long (64 bit signed)
8675 instruct loadL_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
8676 %{
8677 match(Set dst (LoadL mem));
8678
8679 ins_cost(VOLATILE_REF_COST);
8680 format %{ "ldar $dst, $mem\t# int" %}
8681
8682 ins_encode(aarch64_enc_ldar(dst, mem));
8683
8684 ins_pipe(pipe_serial);
8685 %}
8686
8687 // Load Pointer
8688 instruct loadP_volatile(iRegPNoSp dst, /* sync_memory*/indirect mem)
8689 %{
8690 match(Set dst (LoadP mem));
8691
8692 ins_cost(VOLATILE_REF_COST);
8693 format %{ "ldar $dst, $mem\t# ptr" %}
8694
8695 ins_encode(aarch64_enc_ldar(dst, mem));
8696
8697 ins_pipe(pipe_serial);
8698 %}
8699
8700 // Load Compressed Pointer
8701 instruct loadN_volatile(iRegNNoSp dst, /* sync_memory*/indirect mem)
8702 %{
8703 match(Set dst (LoadN mem));
8704
8705 ins_cost(VOLATILE_REF_COST);
8706 format %{ "ldarw $dst, $mem\t# compressed ptr" %}
8707
8708 ins_encode(aarch64_enc_ldarw(dst, mem));
8709
8710 ins_pipe(pipe_serial);
8711 %}
8712
8713 // Load Float
8714 instruct loadF_volatile(vRegF dst, /* sync_memory*/indirect mem)
8715 %{
8716 match(Set dst (LoadF mem));
8717
8718 ins_cost(VOLATILE_REF_COST);
8719 format %{ "ldars $dst, $mem\t# float" %}
8720
8721 ins_encode( aarch64_enc_fldars(dst, mem) );
8722
8723 ins_pipe(pipe_serial);
8724 %}
8725
8726 // Load Double
8727 instruct loadD_volatile(vRegD dst, /* sync_memory*/indirect mem)
8728 %{
8729 match(Set dst (LoadD mem));
8730
8731 ins_cost(VOLATILE_REF_COST);
8732 format %{ "ldard $dst, $mem\t# double" %}
8733
8734 ins_encode( aarch64_enc_fldard(dst, mem) );
8735
8736 ins_pipe(pipe_serial);
8737 %}
8738
8739 // Store Byte
8740 instruct storeB_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
8741 %{
8742 match(Set mem (StoreB mem src));
8743
8744 ins_cost(VOLATILE_REF_COST);
8745 format %{ "stlrb $src, $mem\t# byte" %}
8746
8747 ins_encode(aarch64_enc_stlrb(src, mem));
8748
8749 ins_pipe(pipe_class_memory);
8750 %}
8751
8752 // Store Char/Short
8753 instruct storeC_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
8754 %{
8755 match(Set mem (StoreC mem src));
8756
8757 ins_cost(VOLATILE_REF_COST);
8758 format %{ "stlrh $src, $mem\t# short" %}
8759
8760 ins_encode(aarch64_enc_stlrh(src, mem));
8761
8762 ins_pipe(pipe_class_memory);
8763 %}
8764
8765 // Store Integer
8766
8767 instruct storeI_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
8768 %{
8769 match(Set mem(StoreI mem src));
8770
8771 ins_cost(VOLATILE_REF_COST);
8772 format %{ "stlrw $src, $mem\t# int" %}
8773
8774 ins_encode(aarch64_enc_stlrw(src, mem));
8775
8776 ins_pipe(pipe_class_memory);
8777 %}
8778
8779 // Store Long (64 bit signed)
8780 instruct storeL_volatile(iRegL src, /* sync_memory*/indirect mem)
8781 %{
8782 match(Set mem (StoreL mem src));
8783
8784 ins_cost(VOLATILE_REF_COST);
8785 format %{ "stlr $src, $mem\t# int" %}
8786
8787 ins_encode(aarch64_enc_stlr(src, mem));
8788
8789 ins_pipe(pipe_class_memory);
8790 %}
8791
8792 // Store Pointer
8793 instruct storeP_volatile(iRegP src, /* sync_memory*/indirect mem)
8794 %{
8795 match(Set mem (StoreP mem src));
8796
8797 ins_cost(VOLATILE_REF_COST);
8798 format %{ "stlr $src, $mem\t# ptr" %}
8799
8800 ins_encode(aarch64_enc_stlr(src, mem));
8801
8802 ins_pipe(pipe_class_memory);
8803 %}
8804
8805 // Store Compressed Pointer
8806 instruct storeN_volatile(iRegN src, /* sync_memory*/indirect mem)
8807 %{
8808 match(Set mem (StoreN mem src));
8809
8810 ins_cost(VOLATILE_REF_COST);
8811 format %{ "stlrw $src, $mem\t# compressed ptr" %}
8812
8813 ins_encode(aarch64_enc_stlrw(src, mem));
8814
8815 ins_pipe(pipe_class_memory);
8816 %}
8817
8818 // Store Float
8819 instruct storeF_volatile(vRegF src, /* sync_memory*/indirect mem)
8820 %{
8821 match(Set mem (StoreF mem src));
8822
8823 ins_cost(VOLATILE_REF_COST);
8824 format %{ "stlrs $src, $mem\t# float" %}
8825
8826 ins_encode( aarch64_enc_fstlrs(src, mem) );
8827
8828 ins_pipe(pipe_class_memory);
8829 %}
8830
8831 // TODO
8832 // implement storeImmF0 and storeFImmPacked
8833
8834 // Store Double
8835 instruct storeD_volatile(vRegD src, /* sync_memory*/indirect mem)
8836 %{
8837 match(Set mem (StoreD mem src));
8838
8839 ins_cost(VOLATILE_REF_COST);
8840 format %{ "stlrd $src, $mem\t# double" %}
8841
8842 ins_encode( aarch64_enc_fstlrd(src, mem) );
8843
8844 ins_pipe(pipe_class_memory);
8845 %}
8846
8847 // ---------------- end of volatile loads and stores ----------------
8848
8849 // ============================================================================
8850 // BSWAP Instructions
8851
8852 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
8853 match(Set dst (ReverseBytesI src));
8854
8855 ins_cost(INSN_COST);
8856 format %{ "revw $dst, $src" %}
8857
8858 ins_encode %{
8859 __ revw(as_Register($dst$$reg), as_Register($src$$reg));
8860 %}
8861
8862 ins_pipe(ialu_reg);
8863 %}
8864
8865 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
8866 match(Set dst (ReverseBytesL src));
8867
8868 ins_cost(INSN_COST);
8869 format %{ "rev $dst, $src" %}
8870
8871 ins_encode %{
8872 __ rev(as_Register($dst$$reg), as_Register($src$$reg));
8873 %}
8874
8875 ins_pipe(ialu_reg);
8876 %}
8877
8878 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
8879 match(Set dst (ReverseBytesUS src));
8880
8881 ins_cost(INSN_COST);
8882 format %{ "rev16w $dst, $src" %}
8883
8884 ins_encode %{
8885 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
8886 %}
8887
8888 ins_pipe(ialu_reg);
8889 %}
8890
8891 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
8892 match(Set dst (ReverseBytesS src));
8893
8894 ins_cost(INSN_COST);
8895 format %{ "rev16w $dst, $src\n\t"
8896 "sbfmw $dst, $dst, #0, #15" %}
8897
8898 ins_encode %{
8899 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
8900 __ sbfmw(as_Register($dst$$reg), as_Register($dst$$reg), 0U, 15U);
8901 %}
8902
8903 ins_pipe(ialu_reg);
8904 %}
8905
8906 // ============================================================================
8907 // Zero Count Instructions
8908
8909 instruct countLeadingZerosI(iRegINoSp dst, iRegIorL2I src) %{
8910 match(Set dst (CountLeadingZerosI src));
8911
8912 ins_cost(INSN_COST);
8913 format %{ "clzw $dst, $src" %}
8914 ins_encode %{
8915 __ clzw(as_Register($dst$$reg), as_Register($src$$reg));
8916 %}
8917
8918 ins_pipe(ialu_reg);
8919 %}
8920
8921 instruct countLeadingZerosL(iRegINoSp dst, iRegL src) %{
8922 match(Set dst (CountLeadingZerosL src));
8923
8924 ins_cost(INSN_COST);
8925 format %{ "clz $dst, $src" %}
8926 ins_encode %{
8927 __ clz(as_Register($dst$$reg), as_Register($src$$reg));
8928 %}
8929
8930 ins_pipe(ialu_reg);
8931 %}
8932
8933 instruct countTrailingZerosI(iRegINoSp dst, iRegIorL2I src) %{
8934 match(Set dst (CountTrailingZerosI src));
8935
8936 ins_cost(INSN_COST * 2);
8937 format %{ "rbitw $dst, $src\n\t"
8938 "clzw $dst, $dst" %}
8939 ins_encode %{
8940 __ rbitw(as_Register($dst$$reg), as_Register($src$$reg));
8941 __ clzw(as_Register($dst$$reg), as_Register($dst$$reg));
8942 %}
8943
8944 ins_pipe(ialu_reg);
8945 %}
8946
8947 instruct countTrailingZerosL(iRegINoSp dst, iRegL src) %{
8948 match(Set dst (CountTrailingZerosL src));
8949
8950 ins_cost(INSN_COST * 2);
8951 format %{ "rbit $dst, $src\n\t"
8952 "clz $dst, $dst" %}
8953 ins_encode %{
8954 __ rbit(as_Register($dst$$reg), as_Register($src$$reg));
8955 __ clz(as_Register($dst$$reg), as_Register($dst$$reg));
8956 %}
8957
8958 ins_pipe(ialu_reg);
8959 %}
8960
8961 //---------- Population Count Instructions -------------------------------------
8962 //
8963
8964 instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
8965 predicate(UsePopCountInstruction);
8966 match(Set dst (PopCountI src));
8967 effect(TEMP tmp);
8968 ins_cost(INSN_COST * 13);
8969
8970 format %{ "movw $src, $src\n\t"
8971 "mov $tmp, $src\t# vector (1D)\n\t"
8972 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8973 "addv $tmp, $tmp\t# vector (8B)\n\t"
8974 "mov $dst, $tmp\t# vector (1D)" %}
8975 ins_encode %{
8976 __ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
8977 __ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
8978 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8979 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8980 __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
8981 %}
8982
8983 ins_pipe(pipe_class_default);
8984 %}
8985
8986 instruct popCountI_mem(iRegINoSp dst, memory mem, vRegF tmp) %{
8987 predicate(UsePopCountInstruction);
8988 match(Set dst (PopCountI (LoadI mem)));
8989 effect(TEMP tmp);
8990 ins_cost(INSN_COST * 13);
8991
8992 format %{ "ldrs $tmp, $mem\n\t"
8993 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8994 "addv $tmp, $tmp\t# vector (8B)\n\t"
8995 "mov $dst, $tmp\t# vector (1D)" %}
8996 ins_encode %{
8997 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
8998 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, tmp_reg, $mem->opcode(),
8999 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
9000 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9001 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9002 __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
9003 %}
9004
9005 ins_pipe(pipe_class_default);
9006 %}
9007
9008 // Note: Long.bitCount(long) returns an int.
9009 instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
9010 predicate(UsePopCountInstruction);
9011 match(Set dst (PopCountL src));
9012 effect(TEMP tmp);
9013 ins_cost(INSN_COST * 13);
9014
9015 format %{ "mov $tmp, $src\t# vector (1D)\n\t"
9016 "cnt $tmp, $tmp\t# vector (8B)\n\t"
9017 "addv $tmp, $tmp\t# vector (8B)\n\t"
9018 "mov $dst, $tmp\t# vector (1D)" %}
9019 ins_encode %{
9020 __ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
9021 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9022 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9023 __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
9024 %}
9025
9026 ins_pipe(pipe_class_default);
9027 %}
9028
9029 instruct popCountL_mem(iRegINoSp dst, memory mem, vRegD tmp) %{
9030 predicate(UsePopCountInstruction);
9031 match(Set dst (PopCountL (LoadL mem)));
9032 effect(TEMP tmp);
9033 ins_cost(INSN_COST * 13);
9034
9035 format %{ "ldrd $tmp, $mem\n\t"
9036 "cnt $tmp, $tmp\t# vector (8B)\n\t"
9037 "addv $tmp, $tmp\t# vector (8B)\n\t"
9038 "mov $dst, $tmp\t# vector (1D)" %}
9039 ins_encode %{
9040 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
9041 loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, tmp_reg, $mem->opcode(),
9042 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
9043 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9044 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
9045 __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
9046 %}
9047
9048 ins_pipe(pipe_class_default);
9049 %}
9050
9051 // ============================================================================
9052 // MemBar Instruction
9053
9054 instruct load_fence() %{
9055 match(LoadFence);
9056 ins_cost(VOLATILE_REF_COST);
9057
9058 format %{ "load_fence" %}
9059
9060 ins_encode %{
9061 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
9062 %}
9063 ins_pipe(pipe_serial);
9064 %}
9065
9066 instruct unnecessary_membar_acquire() %{
9067 predicate(unnecessary_acquire(n));
9068 match(MemBarAcquire);
9069 ins_cost(0);
9070
9071 format %{ "membar_acquire (elided)" %}
9072
9073 ins_encode %{
9074 __ block_comment("membar_acquire (elided)");
9075 %}
9076
9077 ins_pipe(pipe_class_empty);
9078 %}
9079
9080 instruct membar_acquire() %{
9081 match(MemBarAcquire);
9082 ins_cost(VOLATILE_REF_COST);
9083
9084 format %{ "membar_acquire" %}
9085
9086 ins_encode %{
9087 __ block_comment("membar_acquire");
9088 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
9089 %}
9090
9091 ins_pipe(pipe_serial);
9092 %}
9093
9094
9095 instruct membar_acquire_lock() %{
9096 match(MemBarAcquireLock);
9097 ins_cost(VOLATILE_REF_COST);
9098
9099 format %{ "membar_acquire_lock (elided)" %}
9100
9101 ins_encode %{
9102 __ block_comment("membar_acquire_lock (elided)");
9103 %}
9104
9105 ins_pipe(pipe_serial);
9106 %}
9107
9108 instruct store_fence() %{
9109 match(StoreFence);
9110 ins_cost(VOLATILE_REF_COST);
9111
9112 format %{ "store_fence" %}
9113
9114 ins_encode %{
9115 __ membar(Assembler::LoadStore|Assembler::StoreStore);
9116 %}
9117 ins_pipe(pipe_serial);
9118 %}
9119
9120 instruct unnecessary_membar_release() %{
9121 predicate(unnecessary_release(n));
9122 match(MemBarRelease);
9123 ins_cost(0);
9124
9125 format %{ "membar_release (elided)" %}
9126
9127 ins_encode %{
9128 __ block_comment("membar_release (elided)");
9129 %}
9130 ins_pipe(pipe_serial);
9131 %}
9132
9133 instruct membar_release() %{
9134 match(MemBarRelease);
9135 ins_cost(VOLATILE_REF_COST);
9136
9137 format %{ "membar_release" %}
9138
9139 ins_encode %{
9140 __ block_comment("membar_release");
9141 __ membar(Assembler::LoadStore|Assembler::StoreStore);
9142 %}
9143 ins_pipe(pipe_serial);
9144 %}
9145
9146 instruct membar_storestore() %{
9147 match(MemBarStoreStore);
9148 ins_cost(VOLATILE_REF_COST);
9149
9150 format %{ "MEMBAR-store-store" %}
9151
9152 ins_encode %{
9153 __ membar(Assembler::StoreStore);
9154 %}
9155 ins_pipe(pipe_serial);
9156 %}
9157
9158 instruct membar_release_lock() %{
9159 match(MemBarReleaseLock);
9160 ins_cost(VOLATILE_REF_COST);
9161
9162 format %{ "membar_release_lock (elided)" %}
9163
9164 ins_encode %{
9165 __ block_comment("membar_release_lock (elided)");
9166 %}
9167
9168 ins_pipe(pipe_serial);
9169 %}
9170
9171 instruct unnecessary_membar_volatile() %{
9172 predicate(unnecessary_volatile(n));
9173 match(MemBarVolatile);
9174 ins_cost(0);
9175
9176 format %{ "membar_volatile (elided)" %}
9177
9178 ins_encode %{
9179 __ block_comment("membar_volatile (elided)");
9180 %}
9181
9182 ins_pipe(pipe_serial);
9183 %}
9184
9185 instruct membar_volatile() %{
9186 match(MemBarVolatile);
9187 ins_cost(VOLATILE_REF_COST*100);
9188
9189 format %{ "membar_volatile" %}
9190
9191 ins_encode %{
9192 __ block_comment("membar_volatile");
9193 __ membar(Assembler::StoreLoad);
9194 %}
9195
9196 ins_pipe(pipe_serial);
9197 %}
9198
9199 // ============================================================================
9200 // Cast/Convert Instructions
9201
9202 instruct castX2P(iRegPNoSp dst, iRegL src) %{
9203 match(Set dst (CastX2P src));
9204
9205 ins_cost(INSN_COST);
9206 format %{ "mov $dst, $src\t# long -> ptr" %}
9207
9208 ins_encode %{
9209 if ($dst$$reg != $src$$reg) {
9210 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
9211 }
9212 %}
9213
9214 ins_pipe(ialu_reg);
9215 %}
9216
9217 instruct castP2X(iRegLNoSp dst, iRegP src) %{
9218 match(Set dst (CastP2X src));
9219
9220 ins_cost(INSN_COST);
9221 format %{ "mov $dst, $src\t# ptr -> long" %}
9222
9223 ins_encode %{
9224 if ($dst$$reg != $src$$reg) {
9225 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
9226 }
9227 %}
9228
9229 ins_pipe(ialu_reg);
9230 %}
9231
9232 // Convert oop into int for vectors alignment masking
9233 instruct convP2I(iRegINoSp dst, iRegP src) %{
9234 match(Set dst (ConvL2I (CastP2X src)));
9235
9236 ins_cost(INSN_COST);
9237 format %{ "movw $dst, $src\t# ptr -> int" %}
9238 ins_encode %{
9239 __ movw($dst$$Register, $src$$Register);
9240 %}
9241
9242 ins_pipe(ialu_reg);
9243 %}
9244
9245 // Convert compressed oop into int for vectors alignment masking
9246 // in case of 32bit oops (heap < 4Gb).
9247 instruct convN2I(iRegINoSp dst, iRegN src)
9248 %{
9249 predicate(Universe::narrow_oop_shift() == 0);
9250 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
9251
9252 ins_cost(INSN_COST);
9253 format %{ "mov dst, $src\t# compressed ptr -> int" %}
9254 ins_encode %{
9255 __ movw($dst$$Register, $src$$Register);
9256 %}
9257
9258 ins_pipe(ialu_reg);
9259 %}
9260
9261
9262 // Convert oop pointer into compressed form
9263 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
9264 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
9265 match(Set dst (EncodeP src));
9266 effect(KILL cr);
9267 ins_cost(INSN_COST * 3);
9268 format %{ "encode_heap_oop $dst, $src" %}
9269 ins_encode %{
9270 Register s = $src$$Register;
9271 Register d = $dst$$Register;
9272 __ encode_heap_oop(d, s);
9273 %}
9274 ins_pipe(ialu_reg);
9275 %}
9276
9277 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
9278 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
9279 match(Set dst (EncodeP src));
9280 ins_cost(INSN_COST * 3);
9281 format %{ "encode_heap_oop_not_null $dst, $src" %}
9282 ins_encode %{
9283 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
9284 %}
9285 ins_pipe(ialu_reg);
9286 %}
9287
9288 instruct decodeHeapOop(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
9289 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
9290 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
9291 match(Set dst (DecodeN src));
9292 ins_cost(INSN_COST * 3);
9293 format %{ "decode_heap_oop $dst, $src" %}
9294 ins_encode %{
9295 Register s = $src$$Register;
9296 Register d = $dst$$Register;
9297 __ decode_heap_oop(d, s);
9298 %}
9299 ins_pipe(ialu_reg);
9300 %}
9301
9302 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
9303 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
9304 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
9305 match(Set dst (DecodeN src));
9306 ins_cost(INSN_COST * 3);
9307 format %{ "decode_heap_oop_not_null $dst, $src" %}
9308 ins_encode %{
9309 Register s = $src$$Register;
9310 Register d = $dst$$Register;
9311 __ decode_heap_oop_not_null(d, s);
9312 %}
9313 ins_pipe(ialu_reg);
9314 %}
9315
9316 // n.b. AArch64 implementations of encode_klass_not_null and
9317 // decode_klass_not_null do not modify the flags register so, unlike
9318 // Intel, we don't kill CR as a side effect here
9319
9320 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
9321 match(Set dst (EncodePKlass src));
9322
9323 ins_cost(INSN_COST * 3);
9324 format %{ "encode_klass_not_null $dst,$src" %}
9325
9326 ins_encode %{
9327 Register src_reg = as_Register($src$$reg);
9328 Register dst_reg = as_Register($dst$$reg);
9329 __ encode_klass_not_null(dst_reg, src_reg);
9330 %}
9331
9332 ins_pipe(ialu_reg);
9333 %}
9334
9335 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src) %{
9336 match(Set dst (DecodeNKlass src));
9337
9338 ins_cost(INSN_COST * 3);
9339 format %{ "decode_klass_not_null $dst,$src" %}
9340
9341 ins_encode %{
9342 Register src_reg = as_Register($src$$reg);
9343 Register dst_reg = as_Register($dst$$reg);
9344 if (dst_reg != src_reg) {
9345 __ decode_klass_not_null(dst_reg, src_reg);
9346 } else {
9347 __ decode_klass_not_null(dst_reg);
9348 }
9349 %}
9350
9351 ins_pipe(ialu_reg);
9352 %}
9353
9354 instruct checkCastPP(iRegPNoSp dst)
9355 %{
9356 match(Set dst (CheckCastPP dst));
9357
9358 size(0);
9359 format %{ "# checkcastPP of $dst" %}
9360 ins_encode(/* empty encoding */);
9361 ins_pipe(pipe_class_empty);
9362 %}
9363
9364 instruct castPP(iRegPNoSp dst)
9365 %{
9366 match(Set dst (CastPP dst));
9367
9368 size(0);
9369 format %{ "# castPP of $dst" %}
9370 ins_encode(/* empty encoding */);
9371 ins_pipe(pipe_class_empty);
9372 %}
9373
9374 instruct castII(iRegI dst)
9375 %{
9376 match(Set dst (CastII dst));
9377
9378 size(0);
9379 format %{ "# castII of $dst" %}
9380 ins_encode(/* empty encoding */);
9381 ins_cost(0);
9382 ins_pipe(pipe_class_empty);
9383 %}
9384
9385 // ============================================================================
9386 // Atomic operation instructions
9387 //
9388 // Intel and SPARC both implement Ideal Node LoadPLocked and
9389 // Store{PIL}Conditional instructions using a normal load for the
9390 // LoadPLocked and a CAS for the Store{PIL}Conditional.
9391 //
9392 // The ideal code appears only to use LoadPLocked/StorePLocked as a
9393 // pair to lock object allocations from Eden space when not using
9394 // TLABs.
9395 //
9396 // There does not appear to be a Load{IL}Locked Ideal Node and the
9397 // Ideal code appears to use Store{IL}Conditional as an alias for CAS
9398 // and to use StoreIConditional only for 32-bit and StoreLConditional
9399 // only for 64-bit.
9400 //
9401 // We implement LoadPLocked and StorePLocked instructions using,
9402 // respectively the AArch64 hw load-exclusive and store-conditional
9403 // instructions. Whereas we must implement each of
9404 // Store{IL}Conditional using a CAS which employs a pair of
9405 // instructions comprising a load-exclusive followed by a
9406 // store-conditional.
9407
9408
9409 // Locked-load (linked load) of the current heap-top
9410 // used when updating the eden heap top
9411 // implemented using ldaxr on AArch64
9412
9413 instruct loadPLocked(iRegPNoSp dst, indirect mem)
9414 %{
9415 match(Set dst (LoadPLocked mem));
9416
9417 ins_cost(VOLATILE_REF_COST);
9418
9419 format %{ "ldaxr $dst, $mem\t# ptr linked acquire" %}
9420
9421 ins_encode(aarch64_enc_ldaxr(dst, mem));
9422
9423 ins_pipe(pipe_serial);
9424 %}
9425
9426 // Conditional-store of the updated heap-top.
9427 // Used during allocation of the shared heap.
9428 // Sets flag (EQ) on success.
9429 // implemented using stlxr on AArch64.
9430
9431 instruct storePConditional(memory heap_top_ptr, iRegP oldval, iRegP newval, rFlagsReg cr)
9432 %{
9433 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
9434
9435 ins_cost(VOLATILE_REF_COST);
9436
9437 // TODO
9438 // do we need to do a store-conditional release or can we just use a
9439 // plain store-conditional?
9440
9441 format %{
9442 "stlxr rscratch1, $newval, $heap_top_ptr\t# ptr cond release"
9443 "cmpw rscratch1, zr\t# EQ on successful write"
9444 %}
9445
9446 ins_encode(aarch64_enc_stlxr(newval, heap_top_ptr));
9447
9448 ins_pipe(pipe_serial);
9449 %}
9450
9451
9452 // storeLConditional is used by PhaseMacroExpand::expand_lock_node
9453 // when attempting to rebias a lock towards the current thread. We
9454 // must use the acquire form of cmpxchg in order to guarantee acquire
9455 // semantics in this case.
9456 instruct storeLConditional(indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr)
9457 %{
9458 match(Set cr (StoreLConditional mem (Binary oldval newval)));
9459
9460 ins_cost(VOLATILE_REF_COST);
9461
9462 format %{
9463 "cmpxchg rscratch1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
9464 "cmpw rscratch1, zr\t# EQ on successful write"
9465 %}
9466
9467 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval));
9468
9469 ins_pipe(pipe_slow);
9470 %}
9471
9472 // storeIConditional also has acquire semantics, for no better reason
9473 // than matching storeLConditional. At the time of writing this
9474 // comment storeIConditional was not used anywhere by AArch64.
9475 instruct storeIConditional(indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr)
9476 %{
9477 match(Set cr (StoreIConditional mem (Binary oldval newval)));
9478
9479 ins_cost(VOLATILE_REF_COST);
9480
9481 format %{
9482 "cmpxchgw rscratch1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
9483 "cmpw rscratch1, zr\t# EQ on successful write"
9484 %}
9485
9486 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval));
9487
9488 ins_pipe(pipe_slow);
9489 %}
9490
9491 // standard CompareAndSwapX when we are using barriers
9492 // these have higher priority than the rules selected by a predicate
9493
9494 // XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
9495 // can't match them
9496
9497 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
9498
9499 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
9500 ins_cost(2 * VOLATILE_REF_COST);
9501
9502 effect(KILL cr);
9503
9504 format %{
9505 "cmpxchgw $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
9506 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9507 %}
9508
9509 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
9510 aarch64_enc_cset_eq(res));
9511
9512 ins_pipe(pipe_slow);
9513 %}
9514
9515 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
9516
9517 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
9518 ins_cost(2 * VOLATILE_REF_COST);
9519
9520 effect(KILL cr);
9521
9522 format %{
9523 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
9524 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9525 %}
9526
9527 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
9528 aarch64_enc_cset_eq(res));
9529
9530 ins_pipe(pipe_slow);
9531 %}
9532
9533 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9534
9535 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
9536 ins_cost(2 * VOLATILE_REF_COST);
9537
9538 effect(KILL cr);
9539
9540 format %{
9541 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
9542 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9543 %}
9544
9545 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
9546 aarch64_enc_cset_eq(res));
9547
9548 ins_pipe(pipe_slow);
9549 %}
9550
9551 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
9552
9553 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
9554 ins_cost(2 * VOLATILE_REF_COST);
9555
9556 effect(KILL cr);
9557
9558 format %{
9559 "cmpxchgw $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
9560 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9561 %}
9562
9563 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
9564 aarch64_enc_cset_eq(res));
9565
9566 ins_pipe(pipe_slow);
9567 %}
9568
9569 // alternative CompareAndSwapX when we are eliding barriers
9570
9571 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
9572
9573 predicate(needs_acquiring_load_exclusive(n));
9574 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
9575 ins_cost(VOLATILE_REF_COST);
9576
9577 effect(KILL cr);
9578
9579 format %{
9580 "cmpxchgw_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
9581 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9582 %}
9583
9584 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
9585 aarch64_enc_cset_eq(res));
9586
9587 ins_pipe(pipe_slow);
9588 %}
9589
9590 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
9591
9592 predicate(needs_acquiring_load_exclusive(n));
9593 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
9594 ins_cost(VOLATILE_REF_COST);
9595
9596 effect(KILL cr);
9597
9598 format %{
9599 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
9600 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9601 %}
9602
9603 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
9604 aarch64_enc_cset_eq(res));
9605
9606 ins_pipe(pipe_slow);
9607 %}
9608
9609 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9610
9611 predicate(needs_acquiring_load_exclusive(n));
9612 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
9613 ins_cost(VOLATILE_REF_COST);
9614
9615 effect(KILL cr);
9616
9617 format %{
9618 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
9619 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9620 %}
9621
9622 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
9623 aarch64_enc_cset_eq(res));
9624
9625 ins_pipe(pipe_slow);
9626 %}
9627
9628 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
9629
9630 predicate(needs_acquiring_load_exclusive(n));
9631 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
9632 ins_cost(VOLATILE_REF_COST);
9633
9634 effect(KILL cr);
9635
9636 format %{
9637 "cmpxchgw_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
9638 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9639 %}
9640
9641 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
9642 aarch64_enc_cset_eq(res));
9643
9644 ins_pipe(pipe_slow);
9645 %}
9646
9647
9648 // ---------------------------------------------------------------------
9649 // Sundry CAS operations. Note that release is always true,
9650 // regardless of the memory ordering of the CAS. This is because we
9651 // need the volatile case to be sequentially consistent but there is
9652 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
9653 // can't check the type of memory ordering here, so we always emit a
9654 // STLXR.
9655
9656 // This section is generated from aarch64_ad_cas.m4
9657
9658
9659 instruct compareAndExchangeB(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9660 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
9661 ins_cost(2 * VOLATILE_REF_COST);
9662 effect(KILL cr);
9663 format %{
9664 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9665 %}
9666 ins_encode %{
9667 __ uxtbw(rscratch2, $oldval$$Register);
9668 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9669 Assembler::byte, /*acquire*/ false, /*release*/ true,
9670 /*weak*/ false, $res$$Register);
9671 __ sxtbw($res$$Register, $res$$Register);
9672 %}
9673 ins_pipe(pipe_slow);
9674 %}
9675
9676 instruct compareAndExchangeS(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9677 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
9678 ins_cost(2 * VOLATILE_REF_COST);
9679 effect(KILL cr);
9680 format %{
9681 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9682 %}
9683 ins_encode %{
9684 __ uxthw(rscratch2, $oldval$$Register);
9685 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9686 Assembler::halfword, /*acquire*/ false, /*release*/ true,
9687 /*weak*/ false, $res$$Register);
9688 __ sxthw($res$$Register, $res$$Register);
9689 %}
9690 ins_pipe(pipe_slow);
9691 %}
9692
9693 instruct compareAndExchangeI(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9694 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
9695 ins_cost(2 * VOLATILE_REF_COST);
9696 effect(KILL cr);
9697 format %{
9698 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9699 %}
9700 ins_encode %{
9701 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9702 Assembler::word, /*acquire*/ false, /*release*/ true,
9703 /*weak*/ false, $res$$Register);
9704 %}
9705 ins_pipe(pipe_slow);
9706 %}
9707
9708 instruct compareAndExchangeL(iRegL_R0 res, indirect mem, iRegL_R2 oldval, iRegL_R3 newval, rFlagsReg cr) %{
9709 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
9710 ins_cost(2 * VOLATILE_REF_COST);
9711 effect(KILL cr);
9712 format %{
9713 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9714 %}
9715 ins_encode %{
9716 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9717 Assembler::xword, /*acquire*/ false, /*release*/ true,
9718 /*weak*/ false, $res$$Register);
9719 %}
9720 ins_pipe(pipe_slow);
9721 %}
9722
9723 instruct compareAndExchangeN(iRegN_R0 res, indirect mem, iRegN_R2 oldval, iRegN_R3 newval, rFlagsReg cr) %{
9724 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
9725 ins_cost(2 * VOLATILE_REF_COST);
9726 effect(KILL cr);
9727 format %{
9728 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9729 %}
9730 ins_encode %{
9731 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9732 Assembler::word, /*acquire*/ false, /*release*/ true,
9733 /*weak*/ false, $res$$Register);
9734 %}
9735 ins_pipe(pipe_slow);
9736 %}
9737
9738 instruct compareAndExchangeP(iRegP_R0 res, indirect mem, iRegP_R2 oldval, iRegP_R3 newval, rFlagsReg cr) %{
9739 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
9740 ins_cost(2 * VOLATILE_REF_COST);
9741 effect(KILL cr);
9742 format %{
9743 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9744 %}
9745 ins_encode %{
9746 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9747 Assembler::xword, /*acquire*/ false, /*release*/ true,
9748 /*weak*/ false, $res$$Register);
9749 %}
9750 ins_pipe(pipe_slow);
9751 %}
9752
9753 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9754 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
9755 ins_cost(2 * VOLATILE_REF_COST);
9756 effect(KILL cr);
9757 format %{
9758 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9759 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9760 %}
9761 ins_encode %{
9762 __ uxtbw(rscratch2, $oldval$$Register);
9763 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9764 Assembler::byte, /*acquire*/ false, /*release*/ true,
9765 /*weak*/ true, noreg);
9766 __ csetw($res$$Register, Assembler::EQ);
9767 %}
9768 ins_pipe(pipe_slow);
9769 %}
9770
9771 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9772 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
9773 ins_cost(2 * VOLATILE_REF_COST);
9774 effect(KILL cr);
9775 format %{
9776 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9777 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9778 %}
9779 ins_encode %{
9780 __ uxthw(rscratch2, $oldval$$Register);
9781 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9782 Assembler::halfword, /*acquire*/ false, /*release*/ true,
9783 /*weak*/ true, noreg);
9784 __ csetw($res$$Register, Assembler::EQ);
9785 %}
9786 ins_pipe(pipe_slow);
9787 %}
9788
9789 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9790 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
9791 ins_cost(2 * VOLATILE_REF_COST);
9792 effect(KILL cr);
9793 format %{
9794 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9795 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9796 %}
9797 ins_encode %{
9798 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9799 Assembler::word, /*acquire*/ false, /*release*/ true,
9800 /*weak*/ true, noreg);
9801 __ csetw($res$$Register, Assembler::EQ);
9802 %}
9803 ins_pipe(pipe_slow);
9804 %}
9805
9806 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
9807 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
9808 ins_cost(2 * VOLATILE_REF_COST);
9809 effect(KILL cr);
9810 format %{
9811 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9812 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9813 %}
9814 ins_encode %{
9815 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9816 Assembler::xword, /*acquire*/ false, /*release*/ true,
9817 /*weak*/ true, noreg);
9818 __ csetw($res$$Register, Assembler::EQ);
9819 %}
9820 ins_pipe(pipe_slow);
9821 %}
9822
9823 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
9824 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
9825 ins_cost(2 * VOLATILE_REF_COST);
9826 effect(KILL cr);
9827 format %{
9828 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9829 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9830 %}
9831 ins_encode %{
9832 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9833 Assembler::word, /*acquire*/ false, /*release*/ true,
9834 /*weak*/ true, noreg);
9835 __ csetw($res$$Register, Assembler::EQ);
9836 %}
9837 ins_pipe(pipe_slow);
9838 %}
9839
9840 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9841 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
9842 ins_cost(2 * VOLATILE_REF_COST);
9843 effect(KILL cr);
9844 format %{
9845 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9846 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9847 %}
9848 ins_encode %{
9849 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9850 Assembler::xword, /*acquire*/ false, /*release*/ true,
9851 /*weak*/ true, noreg);
9852 __ csetw($res$$Register, Assembler::EQ);
9853 %}
9854 ins_pipe(pipe_slow);
9855 %}
9856 // ---------------------------------------------------------------------
9857
9858 instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
9859 match(Set prev (GetAndSetI mem newv));
9860 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9861 ins_encode %{
9862 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9863 %}
9864 ins_pipe(pipe_serial);
9865 %}
9866
9867 instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
9868 match(Set prev (GetAndSetL mem newv));
9869 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9870 ins_encode %{
9871 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9872 %}
9873 ins_pipe(pipe_serial);
9874 %}
9875
9876 instruct get_and_setN(indirect mem, iRegNNoSp newv, iRegI prev) %{
9877 match(Set prev (GetAndSetN mem newv));
9878 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9879 ins_encode %{
9880 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9881 %}
9882 ins_pipe(pipe_serial);
9883 %}
9884
9885 instruct get_and_setP(indirect mem, iRegPNoSp newv, iRegP prev) %{
9886 match(Set prev (GetAndSetP mem newv));
9887 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9888 ins_encode %{
9889 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9890 %}
9891 ins_pipe(pipe_serial);
9892 %}
9893
9894
9895 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{
9896 match(Set newval (GetAndAddL mem incr));
9897 ins_cost(INSN_COST * 10);
9898 format %{ "get_and_addL $newval, [$mem], $incr" %}
9899 ins_encode %{
9900 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
9901 %}
9902 ins_pipe(pipe_serial);
9903 %}
9904
9905 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
9906 predicate(n->as_LoadStore()->result_not_used());
9907 match(Set dummy (GetAndAddL mem incr));
9908 ins_cost(INSN_COST * 9);
9909 format %{ "get_and_addL [$mem], $incr" %}
9910 ins_encode %{
9911 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
9912 %}
9913 ins_pipe(pipe_serial);
9914 %}
9915
9916 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
9917 match(Set newval (GetAndAddL mem incr));
9918 ins_cost(INSN_COST * 10);
9919 format %{ "get_and_addL $newval, [$mem], $incr" %}
9920 ins_encode %{
9921 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
9922 %}
9923 ins_pipe(pipe_serial);
9924 %}
9925
9926 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
9927 predicate(n->as_LoadStore()->result_not_used());
9928 match(Set dummy (GetAndAddL mem incr));
9929 ins_cost(INSN_COST * 9);
9930 format %{ "get_and_addL [$mem], $incr" %}
9931 ins_encode %{
9932 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
9933 %}
9934 ins_pipe(pipe_serial);
9935 %}
9936
9937 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
9938 match(Set newval (GetAndAddI mem incr));
9939 ins_cost(INSN_COST * 10);
9940 format %{ "get_and_addI $newval, [$mem], $incr" %}
9941 ins_encode %{
9942 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
9943 %}
9944 ins_pipe(pipe_serial);
9945 %}
9946
9947 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
9948 predicate(n->as_LoadStore()->result_not_used());
9949 match(Set dummy (GetAndAddI mem incr));
9950 ins_cost(INSN_COST * 9);
9951 format %{ "get_and_addI [$mem], $incr" %}
9952 ins_encode %{
9953 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
9954 %}
9955 ins_pipe(pipe_serial);
9956 %}
9957
9958 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
9959 match(Set newval (GetAndAddI mem incr));
9960 ins_cost(INSN_COST * 10);
9961 format %{ "get_and_addI $newval, [$mem], $incr" %}
9962 ins_encode %{
9963 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
9964 %}
9965 ins_pipe(pipe_serial);
9966 %}
9967
9968 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
9969 predicate(n->as_LoadStore()->result_not_used());
9970 match(Set dummy (GetAndAddI mem incr));
9971 ins_cost(INSN_COST * 9);
9972 format %{ "get_and_addI [$mem], $incr" %}
9973 ins_encode %{
9974 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
9975 %}
9976 ins_pipe(pipe_serial);
9977 %}
9978
9979 // Manifest a CmpL result in an integer register.
9980 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9981 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
9982 %{
9983 match(Set dst (CmpL3 src1 src2));
9984 effect(KILL flags);
9985
9986 ins_cost(INSN_COST * 6);
9987 format %{
9988 "cmp $src1, $src2"
9989 "csetw $dst, ne"
9990 "cnegw $dst, lt"
9991 %}
9992 // format %{ "CmpL3 $dst, $src1, $src2" %}
9993 ins_encode %{
9994 __ cmp($src1$$Register, $src2$$Register);
9995 __ csetw($dst$$Register, Assembler::NE);
9996 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
9997 %}
9998
9999 ins_pipe(pipe_class_default);
10000 %}
10001
10002 instruct cmpL3_reg_imm(iRegINoSp dst, iRegL src1, immLAddSub src2, rFlagsReg flags)
10003 %{
10004 match(Set dst (CmpL3 src1 src2));
10005 effect(KILL flags);
10006
10007 ins_cost(INSN_COST * 6);
10008 format %{
10009 "cmp $src1, $src2"
10010 "csetw $dst, ne"
10011 "cnegw $dst, lt"
10012 %}
10013 ins_encode %{
10014 int32_t con = (int32_t)$src2$$constant;
10015 if (con < 0) {
10016 __ adds(zr, $src1$$Register, -con);
10017 } else {
10018 __ subs(zr, $src1$$Register, con);
10019 }
10020 __ csetw($dst$$Register, Assembler::NE);
10021 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
10022 %}
10023
10024 ins_pipe(pipe_class_default);
10025 %}
10026
10027 // ============================================================================
10028 // Conditional Move Instructions
10029
10030 // n.b. we have identical rules for both a signed compare op (cmpOp)
10031 // and an unsigned compare op (cmpOpU). it would be nice if we could
10032 // define an op class which merged both inputs and use it to type the
10033 // argument to a single rule. unfortunatelyt his fails because the
10034 // opclass does not live up to the COND_INTER interface of its
10035 // component operands. When the generic code tries to negate the
10036 // operand it ends up running the generci Machoper::negate method
10037 // which throws a ShouldNotHappen. So, we have to provide two flavours
10038 // of each rule, one for a cmpOp and a second for a cmpOpU (sigh).
10039
10040 instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10041 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
10042
10043 ins_cost(INSN_COST * 2);
10044 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, int" %}
10045
10046 ins_encode %{
10047 __ cselw(as_Register($dst$$reg),
10048 as_Register($src2$$reg),
10049 as_Register($src1$$reg),
10050 (Assembler::Condition)$cmp$$cmpcode);
10051 %}
10052
10053 ins_pipe(icond_reg_reg);
10054 %}
10055
10056 instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10057 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
10058
10059 ins_cost(INSN_COST * 2);
10060 format %{ "cselw $dst, $src2, $src1 $cmp\t# unsigned, int" %}
10061
10062 ins_encode %{
10063 __ cselw(as_Register($dst$$reg),
10064 as_Register($src2$$reg),
10065 as_Register($src1$$reg),
10066 (Assembler::Condition)$cmp$$cmpcode);
10067 %}
10068
10069 ins_pipe(icond_reg_reg);
10070 %}
10071
10072 // special cases where one arg is zero
10073
10074 // n.b. this is selected in preference to the rule above because it
10075 // avoids loading constant 0 into a source register
10076
10077 // TODO
10078 // we ought only to be able to cull one of these variants as the ideal
10079 // transforms ought always to order the zero consistently (to left/right?)
10080
10081 instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
10082 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
10083
10084 ins_cost(INSN_COST * 2);
10085 format %{ "cselw $dst, $src, zr $cmp\t# signed, int" %}
10086
10087 ins_encode %{
10088 __ cselw(as_Register($dst$$reg),
10089 as_Register($src$$reg),
10090 zr,
10091 (Assembler::Condition)$cmp$$cmpcode);
10092 %}
10093
10094 ins_pipe(icond_reg);
10095 %}
10096
10097 instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
10098 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
10099
10100 ins_cost(INSN_COST * 2);
10101 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, int" %}
10102
10103 ins_encode %{
10104 __ cselw(as_Register($dst$$reg),
10105 as_Register($src$$reg),
10106 zr,
10107 (Assembler::Condition)$cmp$$cmpcode);
10108 %}
10109
10110 ins_pipe(icond_reg);
10111 %}
10112
10113 instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
10114 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
10115
10116 ins_cost(INSN_COST * 2);
10117 format %{ "cselw $dst, zr, $src $cmp\t# signed, int" %}
10118
10119 ins_encode %{
10120 __ cselw(as_Register($dst$$reg),
10121 zr,
10122 as_Register($src$$reg),
10123 (Assembler::Condition)$cmp$$cmpcode);
10124 %}
10125
10126 ins_pipe(icond_reg);
10127 %}
10128
10129 instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
10130 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
10131
10132 ins_cost(INSN_COST * 2);
10133 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, int" %}
10134
10135 ins_encode %{
10136 __ cselw(as_Register($dst$$reg),
10137 zr,
10138 as_Register($src$$reg),
10139 (Assembler::Condition)$cmp$$cmpcode);
10140 %}
10141
10142 ins_pipe(icond_reg);
10143 %}
10144
10145 // special case for creating a boolean 0 or 1
10146
10147 // n.b. this is selected in preference to the rule above because it
10148 // avoids loading constants 0 and 1 into a source register
10149
10150 instruct cmovI_reg_zero_one(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
10151 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
10152
10153 ins_cost(INSN_COST * 2);
10154 format %{ "csincw $dst, zr, zr $cmp\t# signed, int" %}
10155
10156 ins_encode %{
10157 // equivalently
10158 // cset(as_Register($dst$$reg),
10159 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
10160 __ csincw(as_Register($dst$$reg),
10161 zr,
10162 zr,
10163 (Assembler::Condition)$cmp$$cmpcode);
10164 %}
10165
10166 ins_pipe(icond_none);
10167 %}
10168
10169 instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
10170 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
10171
10172 ins_cost(INSN_COST * 2);
10173 format %{ "csincw $dst, zr, zr $cmp\t# unsigned, int" %}
10174
10175 ins_encode %{
10176 // equivalently
10177 // cset(as_Register($dst$$reg),
10178 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
10179 __ csincw(as_Register($dst$$reg),
10180 zr,
10181 zr,
10182 (Assembler::Condition)$cmp$$cmpcode);
10183 %}
10184
10185 ins_pipe(icond_none);
10186 %}
10187
10188 instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
10189 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
10190
10191 ins_cost(INSN_COST * 2);
10192 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long" %}
10193
10194 ins_encode %{
10195 __ csel(as_Register($dst$$reg),
10196 as_Register($src2$$reg),
10197 as_Register($src1$$reg),
10198 (Assembler::Condition)$cmp$$cmpcode);
10199 %}
10200
10201 ins_pipe(icond_reg_reg);
10202 %}
10203
10204 instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
10205 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
10206
10207 ins_cost(INSN_COST * 2);
10208 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long" %}
10209
10210 ins_encode %{
10211 __ csel(as_Register($dst$$reg),
10212 as_Register($src2$$reg),
10213 as_Register($src1$$reg),
10214 (Assembler::Condition)$cmp$$cmpcode);
10215 %}
10216
10217 ins_pipe(icond_reg_reg);
10218 %}
10219
10220 // special cases where one arg is zero
10221
10222 instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
10223 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
10224
10225 ins_cost(INSN_COST * 2);
10226 format %{ "csel $dst, zr, $src $cmp\t# signed, long" %}
10227
10228 ins_encode %{
10229 __ csel(as_Register($dst$$reg),
10230 zr,
10231 as_Register($src$$reg),
10232 (Assembler::Condition)$cmp$$cmpcode);
10233 %}
10234
10235 ins_pipe(icond_reg);
10236 %}
10237
10238 instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
10239 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
10240
10241 ins_cost(INSN_COST * 2);
10242 format %{ "csel $dst, zr, $src $cmp\t# unsigned, long" %}
10243
10244 ins_encode %{
10245 __ csel(as_Register($dst$$reg),
10246 zr,
10247 as_Register($src$$reg),
10248 (Assembler::Condition)$cmp$$cmpcode);
10249 %}
10250
10251 ins_pipe(icond_reg);
10252 %}
10253
10254 instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
10255 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
10256
10257 ins_cost(INSN_COST * 2);
10258 format %{ "csel $dst, $src, zr $cmp\t# signed, long" %}
10259
10260 ins_encode %{
10261 __ csel(as_Register($dst$$reg),
10262 as_Register($src$$reg),
10263 zr,
10264 (Assembler::Condition)$cmp$$cmpcode);
10265 %}
10266
10267 ins_pipe(icond_reg);
10268 %}
10269
10270 instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
10271 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
10272
10273 ins_cost(INSN_COST * 2);
10274 format %{ "csel $dst, $src, zr $cmp\t# unsigned, long" %}
10275
10276 ins_encode %{
10277 __ csel(as_Register($dst$$reg),
10278 as_Register($src$$reg),
10279 zr,
10280 (Assembler::Condition)$cmp$$cmpcode);
10281 %}
10282
10283 ins_pipe(icond_reg);
10284 %}
10285
10286 instruct cmovP_reg_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
10287 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
10288
10289 ins_cost(INSN_COST * 2);
10290 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, ptr" %}
10291
10292 ins_encode %{
10293 __ csel(as_Register($dst$$reg),
10294 as_Register($src2$$reg),
10295 as_Register($src1$$reg),
10296 (Assembler::Condition)$cmp$$cmpcode);
10297 %}
10298
10299 ins_pipe(icond_reg_reg);
10300 %}
10301
10302 instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
10303 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
10304
10305 ins_cost(INSN_COST * 2);
10306 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, ptr" %}
10307
10308 ins_encode %{
10309 __ csel(as_Register($dst$$reg),
10310 as_Register($src2$$reg),
10311 as_Register($src1$$reg),
10312 (Assembler::Condition)$cmp$$cmpcode);
10313 %}
10314
10315 ins_pipe(icond_reg_reg);
10316 %}
10317
10318 // special cases where one arg is zero
10319
10320 instruct cmovP_reg_zero(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
10321 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
10322
10323 ins_cost(INSN_COST * 2);
10324 format %{ "csel $dst, zr, $src $cmp\t# signed, ptr" %}
10325
10326 ins_encode %{
10327 __ csel(as_Register($dst$$reg),
10328 zr,
10329 as_Register($src$$reg),
10330 (Assembler::Condition)$cmp$$cmpcode);
10331 %}
10332
10333 ins_pipe(icond_reg);
10334 %}
10335
10336 instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
10337 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
10338
10339 ins_cost(INSN_COST * 2);
10340 format %{ "csel $dst, zr, $src $cmp\t# unsigned, ptr" %}
10341
10342 ins_encode %{
10343 __ csel(as_Register($dst$$reg),
10344 zr,
10345 as_Register($src$$reg),
10346 (Assembler::Condition)$cmp$$cmpcode);
10347 %}
10348
10349 ins_pipe(icond_reg);
10350 %}
10351
10352 instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
10353 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
10354
10355 ins_cost(INSN_COST * 2);
10356 format %{ "csel $dst, $src, zr $cmp\t# signed, ptr" %}
10357
10358 ins_encode %{
10359 __ csel(as_Register($dst$$reg),
10360 as_Register($src$$reg),
10361 zr,
10362 (Assembler::Condition)$cmp$$cmpcode);
10363 %}
10364
10365 ins_pipe(icond_reg);
10366 %}
10367
10368 instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
10369 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
10370
10371 ins_cost(INSN_COST * 2);
10372 format %{ "csel $dst, $src, zr $cmp\t# unsigned, ptr" %}
10373
10374 ins_encode %{
10375 __ csel(as_Register($dst$$reg),
10376 as_Register($src$$reg),
10377 zr,
10378 (Assembler::Condition)$cmp$$cmpcode);
10379 %}
10380
10381 ins_pipe(icond_reg);
10382 %}
10383
10384 instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
10385 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
10386
10387 ins_cost(INSN_COST * 2);
10388 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
10389
10390 ins_encode %{
10391 __ cselw(as_Register($dst$$reg),
10392 as_Register($src2$$reg),
10393 as_Register($src1$$reg),
10394 (Assembler::Condition)$cmp$$cmpcode);
10395 %}
10396
10397 ins_pipe(icond_reg_reg);
10398 %}
10399
10400 instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
10401 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
10402
10403 ins_cost(INSN_COST * 2);
10404 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
10405
10406 ins_encode %{
10407 __ cselw(as_Register($dst$$reg),
10408 as_Register($src2$$reg),
10409 as_Register($src1$$reg),
10410 (Assembler::Condition)$cmp$$cmpcode);
10411 %}
10412
10413 ins_pipe(icond_reg_reg);
10414 %}
10415
10416 // special cases where one arg is zero
10417
10418 instruct cmovN_reg_zero(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
10419 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
10420
10421 ins_cost(INSN_COST * 2);
10422 format %{ "cselw $dst, zr, $src $cmp\t# signed, compressed ptr" %}
10423
10424 ins_encode %{
10425 __ cselw(as_Register($dst$$reg),
10426 zr,
10427 as_Register($src$$reg),
10428 (Assembler::Condition)$cmp$$cmpcode);
10429 %}
10430
10431 ins_pipe(icond_reg);
10432 %}
10433
10434 instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
10435 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
10436
10437 ins_cost(INSN_COST * 2);
10438 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, compressed ptr" %}
10439
10440 ins_encode %{
10441 __ cselw(as_Register($dst$$reg),
10442 zr,
10443 as_Register($src$$reg),
10444 (Assembler::Condition)$cmp$$cmpcode);
10445 %}
10446
10447 ins_pipe(icond_reg);
10448 %}
10449
10450 instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
10451 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
10452
10453 ins_cost(INSN_COST * 2);
10454 format %{ "cselw $dst, $src, zr $cmp\t# signed, compressed ptr" %}
10455
10456 ins_encode %{
10457 __ cselw(as_Register($dst$$reg),
10458 as_Register($src$$reg),
10459 zr,
10460 (Assembler::Condition)$cmp$$cmpcode);
10461 %}
10462
10463 ins_pipe(icond_reg);
10464 %}
10465
10466 instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
10467 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
10468
10469 ins_cost(INSN_COST * 2);
10470 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, compressed ptr" %}
10471
10472 ins_encode %{
10473 __ cselw(as_Register($dst$$reg),
10474 as_Register($src$$reg),
10475 zr,
10476 (Assembler::Condition)$cmp$$cmpcode);
10477 %}
10478
10479 ins_pipe(icond_reg);
10480 %}
10481
10482 instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1, vRegF src2)
10483 %{
10484 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
10485
10486 ins_cost(INSN_COST * 3);
10487
10488 format %{ "fcsels $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
10489 ins_encode %{
10490 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10491 __ fcsels(as_FloatRegister($dst$$reg),
10492 as_FloatRegister($src2$$reg),
10493 as_FloatRegister($src1$$reg),
10494 cond);
10495 %}
10496
10497 ins_pipe(fp_cond_reg_reg_s);
10498 %}
10499
10500 instruct cmovUF_reg(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1, vRegF src2)
10501 %{
10502 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
10503
10504 ins_cost(INSN_COST * 3);
10505
10506 format %{ "fcsels $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
10507 ins_encode %{
10508 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10509 __ fcsels(as_FloatRegister($dst$$reg),
10510 as_FloatRegister($src2$$reg),
10511 as_FloatRegister($src1$$reg),
10512 cond);
10513 %}
10514
10515 ins_pipe(fp_cond_reg_reg_s);
10516 %}
10517
10518 instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1, vRegD src2)
10519 %{
10520 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
10521
10522 ins_cost(INSN_COST * 3);
10523
10524 format %{ "fcseld $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
10525 ins_encode %{
10526 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10527 __ fcseld(as_FloatRegister($dst$$reg),
10528 as_FloatRegister($src2$$reg),
10529 as_FloatRegister($src1$$reg),
10530 cond);
10531 %}
10532
10533 ins_pipe(fp_cond_reg_reg_d);
10534 %}
10535
10536 instruct cmovUD_reg(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1, vRegD src2)
10537 %{
10538 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
10539
10540 ins_cost(INSN_COST * 3);
10541
10542 format %{ "fcseld $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
10543 ins_encode %{
10544 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10545 __ fcseld(as_FloatRegister($dst$$reg),
10546 as_FloatRegister($src2$$reg),
10547 as_FloatRegister($src1$$reg),
10548 cond);
10549 %}
10550
10551 ins_pipe(fp_cond_reg_reg_d);
10552 %}
10553
10554 // ============================================================================
10555 // Arithmetic Instructions
10556 //
10557
10558 // Integer Addition
10559
10560 // TODO
10561 // these currently employ operations which do not set CR and hence are
10562 // not flagged as killing CR but we would like to isolate the cases
10563 // where we want to set flags from those where we don't. need to work
10564 // out how to do that.
10565
10566 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10567 match(Set dst (AddI src1 src2));
10568
10569 ins_cost(INSN_COST);
10570 format %{ "addw $dst, $src1, $src2" %}
10571
10572 ins_encode %{
10573 __ addw(as_Register($dst$$reg),
10574 as_Register($src1$$reg),
10575 as_Register($src2$$reg));
10576 %}
10577
10578 ins_pipe(ialu_reg_reg);
10579 %}
10580
10581 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
10582 match(Set dst (AddI src1 src2));
10583
10584 ins_cost(INSN_COST);
10585 format %{ "addw $dst, $src1, $src2" %}
10586
10587 // use opcode to indicate that this is an add not a sub
10588 opcode(0x0);
10589
10590 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10591
10592 ins_pipe(ialu_reg_imm);
10593 %}
10594
10595 instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
10596 match(Set dst (AddI (ConvL2I src1) src2));
10597
10598 ins_cost(INSN_COST);
10599 format %{ "addw $dst, $src1, $src2" %}
10600
10601 // use opcode to indicate that this is an add not a sub
10602 opcode(0x0);
10603
10604 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10605
10606 ins_pipe(ialu_reg_imm);
10607 %}
10608
10609 // Pointer Addition
10610 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
10611 match(Set dst (AddP src1 src2));
10612
10613 ins_cost(INSN_COST);
10614 format %{ "add $dst, $src1, $src2\t# ptr" %}
10615
10616 ins_encode %{
10617 __ add(as_Register($dst$$reg),
10618 as_Register($src1$$reg),
10619 as_Register($src2$$reg));
10620 %}
10621
10622 ins_pipe(ialu_reg_reg);
10623 %}
10624
10625 instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
10626 match(Set dst (AddP src1 (ConvI2L src2)));
10627
10628 ins_cost(1.9 * INSN_COST);
10629 format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}
10630
10631 ins_encode %{
10632 __ add(as_Register($dst$$reg),
10633 as_Register($src1$$reg),
10634 as_Register($src2$$reg), ext::sxtw);
10635 %}
10636
10637 ins_pipe(ialu_reg_reg);
10638 %}
10639
10640 instruct addP_reg_reg_lsl(iRegPNoSp dst, iRegP src1, iRegL src2, immIScale scale) %{
10641 match(Set dst (AddP src1 (LShiftL src2 scale)));
10642
10643 ins_cost(1.9 * INSN_COST);
10644 format %{ "add $dst, $src1, $src2, LShiftL $scale\t# ptr" %}
10645
10646 ins_encode %{
10647 __ lea(as_Register($dst$$reg),
10648 Address(as_Register($src1$$reg), as_Register($src2$$reg),
10649 Address::lsl($scale$$constant)));
10650 %}
10651
10652 ins_pipe(ialu_reg_reg_shift);
10653 %}
10654
10655 instruct addP_reg_reg_ext_shift(iRegPNoSp dst, iRegP src1, iRegIorL2I src2, immIScale scale) %{
10656 match(Set dst (AddP src1 (LShiftL (ConvI2L src2) scale)));
10657
10658 ins_cost(1.9 * INSN_COST);
10659 format %{ "add $dst, $src1, $src2, I2L $scale\t# ptr" %}
10660
10661 ins_encode %{
10662 __ lea(as_Register($dst$$reg),
10663 Address(as_Register($src1$$reg), as_Register($src2$$reg),
10664 Address::sxtw($scale$$constant)));
10665 %}
10666
10667 ins_pipe(ialu_reg_reg_shift);
10668 %}
10669
10670 instruct lshift_ext(iRegLNoSp dst, iRegIorL2I src, immI scale, rFlagsReg cr) %{
10671 match(Set dst (LShiftL (ConvI2L src) scale));
10672
10673 ins_cost(INSN_COST);
10674 format %{ "sbfiz $dst, $src, $scale & 63, -$scale & 63\t" %}
10675
10676 ins_encode %{
10677 __ sbfiz(as_Register($dst$$reg),
10678 as_Register($src$$reg),
10679 $scale$$constant & 63, MIN(32, (-$scale$$constant) & 63));
10680 %}
10681
10682 ins_pipe(ialu_reg_shift);
10683 %}
10684
10685 // Pointer Immediate Addition
10686 // n.b. this needs to be more expensive than using an indirect memory
10687 // operand
10688 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAddSub src2) %{
10689 match(Set dst (AddP src1 src2));
10690
10691 ins_cost(INSN_COST);
10692 format %{ "add $dst, $src1, $src2\t# ptr" %}
10693
10694 // use opcode to indicate that this is an add not a sub
10695 opcode(0x0);
10696
10697 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10698
10699 ins_pipe(ialu_reg_imm);
10700 %}
10701
10702 // Long Addition
10703 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10704
10705 match(Set dst (AddL src1 src2));
10706
10707 ins_cost(INSN_COST);
10708 format %{ "add $dst, $src1, $src2" %}
10709
10710 ins_encode %{
10711 __ add(as_Register($dst$$reg),
10712 as_Register($src1$$reg),
10713 as_Register($src2$$reg));
10714 %}
10715
10716 ins_pipe(ialu_reg_reg);
10717 %}
10718
10719 // No constant pool entries requiredLong Immediate Addition.
10720 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
10721 match(Set dst (AddL src1 src2));
10722
10723 ins_cost(INSN_COST);
10724 format %{ "add $dst, $src1, $src2" %}
10725
10726 // use opcode to indicate that this is an add not a sub
10727 opcode(0x0);
10728
10729 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10730
10731 ins_pipe(ialu_reg_imm);
10732 %}
10733
10734 // Integer Subtraction
10735 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10736 match(Set dst (SubI src1 src2));
10737
10738 ins_cost(INSN_COST);
10739 format %{ "subw $dst, $src1, $src2" %}
10740
10741 ins_encode %{
10742 __ subw(as_Register($dst$$reg),
10743 as_Register($src1$$reg),
10744 as_Register($src2$$reg));
10745 %}
10746
10747 ins_pipe(ialu_reg_reg);
10748 %}
10749
10750 // Immediate Subtraction
10751 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
10752 match(Set dst (SubI src1 src2));
10753
10754 ins_cost(INSN_COST);
10755 format %{ "subw $dst, $src1, $src2" %}
10756
10757 // use opcode to indicate that this is a sub not an add
10758 opcode(0x1);
10759
10760 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10761
10762 ins_pipe(ialu_reg_imm);
10763 %}
10764
10765 // Long Subtraction
10766 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10767
10768 match(Set dst (SubL src1 src2));
10769
10770 ins_cost(INSN_COST);
10771 format %{ "sub $dst, $src1, $src2" %}
10772
10773 ins_encode %{
10774 __ sub(as_Register($dst$$reg),
10775 as_Register($src1$$reg),
10776 as_Register($src2$$reg));
10777 %}
10778
10779 ins_pipe(ialu_reg_reg);
10780 %}
10781
10782 // No constant pool entries requiredLong Immediate Subtraction.
10783 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
10784 match(Set dst (SubL src1 src2));
10785
10786 ins_cost(INSN_COST);
10787 format %{ "sub$dst, $src1, $src2" %}
10788
10789 // use opcode to indicate that this is a sub not an add
10790 opcode(0x1);
10791
10792 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10793
10794 ins_pipe(ialu_reg_imm);
10795 %}
10796
10797 // Integer Negation (special case for sub)
10798
10799 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{
10800 match(Set dst (SubI zero src));
10801
10802 ins_cost(INSN_COST);
10803 format %{ "negw $dst, $src\t# int" %}
10804
10805 ins_encode %{
10806 __ negw(as_Register($dst$$reg),
10807 as_Register($src$$reg));
10808 %}
10809
10810 ins_pipe(ialu_reg);
10811 %}
10812
10813 // Long Negation
10814
10815 instruct negL_reg(iRegLNoSp dst, iRegIorL2I src, immL0 zero, rFlagsReg cr) %{
10816 match(Set dst (SubL zero src));
10817
10818 ins_cost(INSN_COST);
10819 format %{ "neg $dst, $src\t# long" %}
10820
10821 ins_encode %{
10822 __ neg(as_Register($dst$$reg),
10823 as_Register($src$$reg));
10824 %}
10825
10826 ins_pipe(ialu_reg);
10827 %}
10828
10829 // Integer Multiply
10830
10831 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10832 match(Set dst (MulI src1 src2));
10833
10834 ins_cost(INSN_COST * 3);
10835 format %{ "mulw $dst, $src1, $src2" %}
10836
10837 ins_encode %{
10838 __ mulw(as_Register($dst$$reg),
10839 as_Register($src1$$reg),
10840 as_Register($src2$$reg));
10841 %}
10842
10843 ins_pipe(imul_reg_reg);
10844 %}
10845
10846 instruct smulI(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10847 match(Set dst (MulL (ConvI2L src1) (ConvI2L src2)));
10848
10849 ins_cost(INSN_COST * 3);
10850 format %{ "smull $dst, $src1, $src2" %}
10851
10852 ins_encode %{
10853 __ smull(as_Register($dst$$reg),
10854 as_Register($src1$$reg),
10855 as_Register($src2$$reg));
10856 %}
10857
10858 ins_pipe(imul_reg_reg);
10859 %}
10860
10861 // Long Multiply
10862
10863 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10864 match(Set dst (MulL src1 src2));
10865
10866 ins_cost(INSN_COST * 5);
10867 format %{ "mul $dst, $src1, $src2" %}
10868
10869 ins_encode %{
10870 __ mul(as_Register($dst$$reg),
10871 as_Register($src1$$reg),
10872 as_Register($src2$$reg));
10873 %}
10874
10875 ins_pipe(lmul_reg_reg);
10876 %}
10877
10878 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
10879 %{
10880 match(Set dst (MulHiL src1 src2));
10881
10882 ins_cost(INSN_COST * 7);
10883 format %{ "smulh $dst, $src1, $src2, \t# mulhi" %}
10884
10885 ins_encode %{
10886 __ smulh(as_Register($dst$$reg),
10887 as_Register($src1$$reg),
10888 as_Register($src2$$reg));
10889 %}
10890
10891 ins_pipe(lmul_reg_reg);
10892 %}
10893
10894 // Combined Integer Multiply & Add/Sub
10895
10896 instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10897 match(Set dst (AddI src3 (MulI src1 src2)));
10898
10899 ins_cost(INSN_COST * 3);
10900 format %{ "madd $dst, $src1, $src2, $src3" %}
10901
10902 ins_encode %{
10903 __ maddw(as_Register($dst$$reg),
10904 as_Register($src1$$reg),
10905 as_Register($src2$$reg),
10906 as_Register($src3$$reg));
10907 %}
10908
10909 ins_pipe(imac_reg_reg);
10910 %}
10911
10912 instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10913 match(Set dst (SubI src3 (MulI src1 src2)));
10914
10915 ins_cost(INSN_COST * 3);
10916 format %{ "msub $dst, $src1, $src2, $src3" %}
10917
10918 ins_encode %{
10919 __ msubw(as_Register($dst$$reg),
10920 as_Register($src1$$reg),
10921 as_Register($src2$$reg),
10922 as_Register($src3$$reg));
10923 %}
10924
10925 ins_pipe(imac_reg_reg);
10926 %}
10927
10928 // Combined Long Multiply & Add/Sub
10929
10930 instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10931 match(Set dst (AddL src3 (MulL src1 src2)));
10932
10933 ins_cost(INSN_COST * 5);
10934 format %{ "madd $dst, $src1, $src2, $src3" %}
10935
10936 ins_encode %{
10937 __ madd(as_Register($dst$$reg),
10938 as_Register($src1$$reg),
10939 as_Register($src2$$reg),
10940 as_Register($src3$$reg));
10941 %}
10942
10943 ins_pipe(lmac_reg_reg);
10944 %}
10945
10946 instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10947 match(Set dst (SubL src3 (MulL src1 src2)));
10948
10949 ins_cost(INSN_COST * 5);
10950 format %{ "msub $dst, $src1, $src2, $src3" %}
10951
10952 ins_encode %{
10953 __ msub(as_Register($dst$$reg),
10954 as_Register($src1$$reg),
10955 as_Register($src2$$reg),
10956 as_Register($src3$$reg));
10957 %}
10958
10959 ins_pipe(lmac_reg_reg);
10960 %}
10961
10962 // Integer Divide
10963
10964 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10965 match(Set dst (DivI src1 src2));
10966
10967 ins_cost(INSN_COST * 19);
10968 format %{ "sdivw $dst, $src1, $src2" %}
10969
10970 ins_encode(aarch64_enc_divw(dst, src1, src2));
10971 ins_pipe(idiv_reg_reg);
10972 %}
10973
10974 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
10975 match(Set dst (URShiftI (RShiftI src1 div1) div2));
10976 ins_cost(INSN_COST);
10977 format %{ "lsrw $dst, $src1, $div1" %}
10978 ins_encode %{
10979 __ lsrw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
10980 %}
10981 ins_pipe(ialu_reg_shift);
10982 %}
10983
10984 instruct div2Round(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{
10985 match(Set dst (AddI src (URShiftI (RShiftI src div1) div2)));
10986 ins_cost(INSN_COST);
10987 format %{ "addw $dst, $src, LSR $div1" %}
10988
10989 ins_encode %{
10990 __ addw(as_Register($dst$$reg),
10991 as_Register($src$$reg),
10992 as_Register($src$$reg),
10993 Assembler::LSR, 31);
10994 %}
10995 ins_pipe(ialu_reg);
10996 %}
10997
10998 // Long Divide
10999
11000 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
11001 match(Set dst (DivL src1 src2));
11002
11003 ins_cost(INSN_COST * 35);
11004 format %{ "sdiv $dst, $src1, $src2" %}
11005
11006 ins_encode(aarch64_enc_div(dst, src1, src2));
11007 ins_pipe(ldiv_reg_reg);
11008 %}
11009
11010 instruct signExtractL(iRegLNoSp dst, iRegL src1, immL_63 div1, immL_63 div2) %{
11011 match(Set dst (URShiftL (RShiftL src1 div1) div2));
11012 ins_cost(INSN_COST);
11013 format %{ "lsr $dst, $src1, $div1" %}
11014 ins_encode %{
11015 __ lsr(as_Register($dst$$reg), as_Register($src1$$reg), 63);
11016 %}
11017 ins_pipe(ialu_reg_shift);
11018 %}
11019
11020 instruct div2RoundL(iRegLNoSp dst, iRegL src, immL_63 div1, immL_63 div2) %{
11021 match(Set dst (AddL src (URShiftL (RShiftL src div1) div2)));
11022 ins_cost(INSN_COST);
11023 format %{ "add $dst, $src, $div1" %}
11024
11025 ins_encode %{
11026 __ add(as_Register($dst$$reg),
11027 as_Register($src$$reg),
11028 as_Register($src$$reg),
11029 Assembler::LSR, 63);
11030 %}
11031 ins_pipe(ialu_reg);
11032 %}
11033
11034 // Integer Remainder
11035
11036 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
11037 match(Set dst (ModI src1 src2));
11038
11039 ins_cost(INSN_COST * 22);
11040 format %{ "sdivw rscratch1, $src1, $src2\n\t"
11041 "msubw($dst, rscratch1, $src2, $src1" %}
11042
11043 ins_encode(aarch64_enc_modw(dst, src1, src2));
11044 ins_pipe(idiv_reg_reg);
11045 %}
11046
11047 // Long Remainder
11048
11049 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
11050 match(Set dst (ModL src1 src2));
11051
11052 ins_cost(INSN_COST * 38);
11053 format %{ "sdiv rscratch1, $src1, $src2\n"
11054 "msub($dst, rscratch1, $src2, $src1" %}
11055
11056 ins_encode(aarch64_enc_mod(dst, src1, src2));
11057 ins_pipe(ldiv_reg_reg);
11058 %}
11059
11060 // Integer Shifts
11061
11062 // Shift Left Register
11063 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
11064 match(Set dst (LShiftI src1 src2));
11065
11066 ins_cost(INSN_COST * 2);
11067 format %{ "lslvw $dst, $src1, $src2" %}
11068
11069 ins_encode %{
11070 __ lslvw(as_Register($dst$$reg),
11071 as_Register($src1$$reg),
11072 as_Register($src2$$reg));
11073 %}
11074
11075 ins_pipe(ialu_reg_reg_vshift);
11076 %}
11077
11078 // Shift Left Immediate
11079 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
11080 match(Set dst (LShiftI src1 src2));
11081
11082 ins_cost(INSN_COST);
11083 format %{ "lslw $dst, $src1, ($src2 & 0x1f)" %}
11084
11085 ins_encode %{
11086 __ lslw(as_Register($dst$$reg),
11087 as_Register($src1$$reg),
11088 $src2$$constant & 0x1f);
11089 %}
11090
11091 ins_pipe(ialu_reg_shift);
11092 %}
11093
11094 // Shift Right Logical Register
11095 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
11096 match(Set dst (URShiftI src1 src2));
11097
11098 ins_cost(INSN_COST * 2);
11099 format %{ "lsrvw $dst, $src1, $src2" %}
11100
11101 ins_encode %{
11102 __ lsrvw(as_Register($dst$$reg),
11103 as_Register($src1$$reg),
11104 as_Register($src2$$reg));
11105 %}
11106
11107 ins_pipe(ialu_reg_reg_vshift);
11108 %}
11109
11110 // Shift Right Logical Immediate
11111 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
11112 match(Set dst (URShiftI src1 src2));
11113
11114 ins_cost(INSN_COST);
11115 format %{ "lsrw $dst, $src1, ($src2 & 0x1f)" %}
11116
11117 ins_encode %{
11118 __ lsrw(as_Register($dst$$reg),
11119 as_Register($src1$$reg),
11120 $src2$$constant & 0x1f);
11121 %}
11122
11123 ins_pipe(ialu_reg_shift);
11124 %}
11125
11126 // Shift Right Arithmetic Register
11127 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
11128 match(Set dst (RShiftI src1 src2));
11129
11130 ins_cost(INSN_COST * 2);
11131 format %{ "asrvw $dst, $src1, $src2" %}
11132
11133 ins_encode %{
11134 __ asrvw(as_Register($dst$$reg),
11135 as_Register($src1$$reg),
11136 as_Register($src2$$reg));
11137 %}
11138
11139 ins_pipe(ialu_reg_reg_vshift);
11140 %}
11141
11142 // Shift Right Arithmetic Immediate
11143 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
11144 match(Set dst (RShiftI src1 src2));
11145
11146 ins_cost(INSN_COST);
11147 format %{ "asrw $dst, $src1, ($src2 & 0x1f)" %}
11148
11149 ins_encode %{
11150 __ asrw(as_Register($dst$$reg),
11151 as_Register($src1$$reg),
11152 $src2$$constant & 0x1f);
11153 %}
11154
11155 ins_pipe(ialu_reg_shift);
11156 %}
11157
11158 // Combined Int Mask and Right Shift (using UBFM)
11159 // TODO
11160
11161 // Long Shifts
11162
11163 // Shift Left Register
11164 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
11165 match(Set dst (LShiftL src1 src2));
11166
11167 ins_cost(INSN_COST * 2);
11168 format %{ "lslv $dst, $src1, $src2" %}
11169
11170 ins_encode %{
11171 __ lslv(as_Register($dst$$reg),
11172 as_Register($src1$$reg),
11173 as_Register($src2$$reg));
11174 %}
11175
11176 ins_pipe(ialu_reg_reg_vshift);
11177 %}
11178
11179 // Shift Left Immediate
11180 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
11181 match(Set dst (LShiftL src1 src2));
11182
11183 ins_cost(INSN_COST);
11184 format %{ "lsl $dst, $src1, ($src2 & 0x3f)" %}
11185
11186 ins_encode %{
11187 __ lsl(as_Register($dst$$reg),
11188 as_Register($src1$$reg),
11189 $src2$$constant & 0x3f);
11190 %}
11191
11192 ins_pipe(ialu_reg_shift);
11193 %}
11194
11195 // Shift Right Logical Register
11196 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
11197 match(Set dst (URShiftL src1 src2));
11198
11199 ins_cost(INSN_COST * 2);
11200 format %{ "lsrv $dst, $src1, $src2" %}
11201
11202 ins_encode %{
11203 __ lsrv(as_Register($dst$$reg),
11204 as_Register($src1$$reg),
11205 as_Register($src2$$reg));
11206 %}
11207
11208 ins_pipe(ialu_reg_reg_vshift);
11209 %}
11210
11211 // Shift Right Logical Immediate
11212 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
11213 match(Set dst (URShiftL src1 src2));
11214
11215 ins_cost(INSN_COST);
11216 format %{ "lsr $dst, $src1, ($src2 & 0x3f)" %}
11217
11218 ins_encode %{
11219 __ lsr(as_Register($dst$$reg),
11220 as_Register($src1$$reg),
11221 $src2$$constant & 0x3f);
11222 %}
11223
11224 ins_pipe(ialu_reg_shift);
11225 %}
11226
11227 // A special-case pattern for card table stores.
11228 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
11229 match(Set dst (URShiftL (CastP2X src1) src2));
11230
11231 ins_cost(INSN_COST);
11232 format %{ "lsr $dst, p2x($src1), ($src2 & 0x3f)" %}
11233
11234 ins_encode %{
11235 __ lsr(as_Register($dst$$reg),
11236 as_Register($src1$$reg),
11237 $src2$$constant & 0x3f);
11238 %}
11239
11240 ins_pipe(ialu_reg_shift);
11241 %}
11242
11243 // Shift Right Arithmetic Register
11244 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
11245 match(Set dst (RShiftL src1 src2));
11246
11247 ins_cost(INSN_COST * 2);
11248 format %{ "asrv $dst, $src1, $src2" %}
11249
11250 ins_encode %{
11251 __ asrv(as_Register($dst$$reg),
11252 as_Register($src1$$reg),
11253 as_Register($src2$$reg));
11254 %}
11255
11256 ins_pipe(ialu_reg_reg_vshift);
11257 %}
11258
11259 // Shift Right Arithmetic Immediate
11260 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
11261 match(Set dst (RShiftL src1 src2));
11262
11263 ins_cost(INSN_COST);
11264 format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
11265
11266 ins_encode %{
11267 __ asr(as_Register($dst$$reg),
11268 as_Register($src1$$reg),
11269 $src2$$constant & 0x3f);
11270 %}
11271
11272 ins_pipe(ialu_reg_shift);
11273 %}
11274
11275 // BEGIN This section of the file is automatically generated. Do not edit --------------
11276
11277 instruct regL_not_reg(iRegLNoSp dst,
11278 iRegL src1, immL_M1 m1,
11279 rFlagsReg cr) %{
11280 match(Set dst (XorL src1 m1));
11281 ins_cost(INSN_COST);
11282 format %{ "eon $dst, $src1, zr" %}
11283
11284 ins_encode %{
11285 __ eon(as_Register($dst$$reg),
11286 as_Register($src1$$reg),
11287 zr,
11288 Assembler::LSL, 0);
11289 %}
11290
11291 ins_pipe(ialu_reg);
11292 %}
11293 instruct regI_not_reg(iRegINoSp dst,
11294 iRegIorL2I src1, immI_M1 m1,
11295 rFlagsReg cr) %{
11296 match(Set dst (XorI src1 m1));
11297 ins_cost(INSN_COST);
11298 format %{ "eonw $dst, $src1, zr" %}
11299
11300 ins_encode %{
11301 __ eonw(as_Register($dst$$reg),
11302 as_Register($src1$$reg),
11303 zr,
11304 Assembler::LSL, 0);
11305 %}
11306
11307 ins_pipe(ialu_reg);
11308 %}
11309
11310 instruct AndI_reg_not_reg(iRegINoSp dst,
11311 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
11312 rFlagsReg cr) %{
11313 match(Set dst (AndI src1 (XorI src2 m1)));
11314 ins_cost(INSN_COST);
11315 format %{ "bicw $dst, $src1, $src2" %}
11316
11317 ins_encode %{
11318 __ bicw(as_Register($dst$$reg),
11319 as_Register($src1$$reg),
11320 as_Register($src2$$reg),
11321 Assembler::LSL, 0);
11322 %}
11323
11324 ins_pipe(ialu_reg_reg);
11325 %}
11326
11327 instruct AndL_reg_not_reg(iRegLNoSp dst,
11328 iRegL src1, iRegL src2, immL_M1 m1,
11329 rFlagsReg cr) %{
11330 match(Set dst (AndL src1 (XorL src2 m1)));
11331 ins_cost(INSN_COST);
11332 format %{ "bic $dst, $src1, $src2" %}
11333
11334 ins_encode %{
11335 __ bic(as_Register($dst$$reg),
11336 as_Register($src1$$reg),
11337 as_Register($src2$$reg),
11338 Assembler::LSL, 0);
11339 %}
11340
11341 ins_pipe(ialu_reg_reg);
11342 %}
11343
11344 instruct OrI_reg_not_reg(iRegINoSp dst,
11345 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
11346 rFlagsReg cr) %{
11347 match(Set dst (OrI src1 (XorI src2 m1)));
11348 ins_cost(INSN_COST);
11349 format %{ "ornw $dst, $src1, $src2" %}
11350
11351 ins_encode %{
11352 __ ornw(as_Register($dst$$reg),
11353 as_Register($src1$$reg),
11354 as_Register($src2$$reg),
11355 Assembler::LSL, 0);
11356 %}
11357
11358 ins_pipe(ialu_reg_reg);
11359 %}
11360
11361 instruct OrL_reg_not_reg(iRegLNoSp dst,
11362 iRegL src1, iRegL src2, immL_M1 m1,
11363 rFlagsReg cr) %{
11364 match(Set dst (OrL src1 (XorL src2 m1)));
11365 ins_cost(INSN_COST);
11366 format %{ "orn $dst, $src1, $src2" %}
11367
11368 ins_encode %{
11369 __ orn(as_Register($dst$$reg),
11370 as_Register($src1$$reg),
11371 as_Register($src2$$reg),
11372 Assembler::LSL, 0);
11373 %}
11374
11375 ins_pipe(ialu_reg_reg);
11376 %}
11377
11378 instruct XorI_reg_not_reg(iRegINoSp dst,
11379 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
11380 rFlagsReg cr) %{
11381 match(Set dst (XorI m1 (XorI src2 src1)));
11382 ins_cost(INSN_COST);
11383 format %{ "eonw $dst, $src1, $src2" %}
11384
11385 ins_encode %{
11386 __ eonw(as_Register($dst$$reg),
11387 as_Register($src1$$reg),
11388 as_Register($src2$$reg),
11389 Assembler::LSL, 0);
11390 %}
11391
11392 ins_pipe(ialu_reg_reg);
11393 %}
11394
11395 instruct XorL_reg_not_reg(iRegLNoSp dst,
11396 iRegL src1, iRegL src2, immL_M1 m1,
11397 rFlagsReg cr) %{
11398 match(Set dst (XorL m1 (XorL src2 src1)));
11399 ins_cost(INSN_COST);
11400 format %{ "eon $dst, $src1, $src2" %}
11401
11402 ins_encode %{
11403 __ eon(as_Register($dst$$reg),
11404 as_Register($src1$$reg),
11405 as_Register($src2$$reg),
11406 Assembler::LSL, 0);
11407 %}
11408
11409 ins_pipe(ialu_reg_reg);
11410 %}
11411
11412 instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
11413 iRegIorL2I src1, iRegIorL2I src2,
11414 immI src3, immI_M1 src4, rFlagsReg cr) %{
11415 match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
11416 ins_cost(1.9 * INSN_COST);
11417 format %{ "bicw $dst, $src1, $src2, LSR $src3" %}
11418
11419 ins_encode %{
11420 __ bicw(as_Register($dst$$reg),
11421 as_Register($src1$$reg),
11422 as_Register($src2$$reg),
11423 Assembler::LSR,
11424 $src3$$constant & 0x1f);
11425 %}
11426
11427 ins_pipe(ialu_reg_reg_shift);
11428 %}
11429
11430 instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
11431 iRegL src1, iRegL src2,
11432 immI src3, immL_M1 src4, rFlagsReg cr) %{
11433 match(Set dst (AndL src1 (XorL(URShiftL src2 src3) src4)));
11434 ins_cost(1.9 * INSN_COST);
11435 format %{ "bic $dst, $src1, $src2, LSR $src3" %}
11436
11437 ins_encode %{
11438 __ bic(as_Register($dst$$reg),
11439 as_Register($src1$$reg),
11440 as_Register($src2$$reg),
11441 Assembler::LSR,
11442 $src3$$constant & 0x3f);
11443 %}
11444
11445 ins_pipe(ialu_reg_reg_shift);
11446 %}
11447
11448 instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
11449 iRegIorL2I src1, iRegIorL2I src2,
11450 immI src3, immI_M1 src4, rFlagsReg cr) %{
11451 match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
11452 ins_cost(1.9 * INSN_COST);
11453 format %{ "bicw $dst, $src1, $src2, ASR $src3" %}
11454
11455 ins_encode %{
11456 __ bicw(as_Register($dst$$reg),
11457 as_Register($src1$$reg),
11458 as_Register($src2$$reg),
11459 Assembler::ASR,
11460 $src3$$constant & 0x1f);
11461 %}
11462
11463 ins_pipe(ialu_reg_reg_shift);
11464 %}
11465
11466 instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
11467 iRegL src1, iRegL src2,
11468 immI src3, immL_M1 src4, rFlagsReg cr) %{
11469 match(Set dst (AndL src1 (XorL(RShiftL src2 src3) src4)));
11470 ins_cost(1.9 * INSN_COST);
11471 format %{ "bic $dst, $src1, $src2, ASR $src3" %}
11472
11473 ins_encode %{
11474 __ bic(as_Register($dst$$reg),
11475 as_Register($src1$$reg),
11476 as_Register($src2$$reg),
11477 Assembler::ASR,
11478 $src3$$constant & 0x3f);
11479 %}
11480
11481 ins_pipe(ialu_reg_reg_shift);
11482 %}
11483
11484 instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
11485 iRegIorL2I src1, iRegIorL2I src2,
11486 immI src3, immI_M1 src4, rFlagsReg cr) %{
11487 match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
11488 ins_cost(1.9 * INSN_COST);
11489 format %{ "bicw $dst, $src1, $src2, LSL $src3" %}
11490
11491 ins_encode %{
11492 __ bicw(as_Register($dst$$reg),
11493 as_Register($src1$$reg),
11494 as_Register($src2$$reg),
11495 Assembler::LSL,
11496 $src3$$constant & 0x1f);
11497 %}
11498
11499 ins_pipe(ialu_reg_reg_shift);
11500 %}
11501
11502 instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
11503 iRegL src1, iRegL src2,
11504 immI src3, immL_M1 src4, rFlagsReg cr) %{
11505 match(Set dst (AndL src1 (XorL(LShiftL src2 src3) src4)));
11506 ins_cost(1.9 * INSN_COST);
11507 format %{ "bic $dst, $src1, $src2, LSL $src3" %}
11508
11509 ins_encode %{
11510 __ bic(as_Register($dst$$reg),
11511 as_Register($src1$$reg),
11512 as_Register($src2$$reg),
11513 Assembler::LSL,
11514 $src3$$constant & 0x3f);
11515 %}
11516
11517 ins_pipe(ialu_reg_reg_shift);
11518 %}
11519
11520 instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
11521 iRegIorL2I src1, iRegIorL2I src2,
11522 immI src3, immI_M1 src4, rFlagsReg cr) %{
11523 match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
11524 ins_cost(1.9 * INSN_COST);
11525 format %{ "eonw $dst, $src1, $src2, LSR $src3" %}
11526
11527 ins_encode %{
11528 __ eonw(as_Register($dst$$reg),
11529 as_Register($src1$$reg),
11530 as_Register($src2$$reg),
11531 Assembler::LSR,
11532 $src3$$constant & 0x1f);
11533 %}
11534
11535 ins_pipe(ialu_reg_reg_shift);
11536 %}
11537
11538 instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
11539 iRegL src1, iRegL src2,
11540 immI src3, immL_M1 src4, rFlagsReg cr) %{
11541 match(Set dst (XorL src4 (XorL(URShiftL src2 src3) src1)));
11542 ins_cost(1.9 * INSN_COST);
11543 format %{ "eon $dst, $src1, $src2, LSR $src3" %}
11544
11545 ins_encode %{
11546 __ eon(as_Register($dst$$reg),
11547 as_Register($src1$$reg),
11548 as_Register($src2$$reg),
11549 Assembler::LSR,
11550 $src3$$constant & 0x3f);
11551 %}
11552
11553 ins_pipe(ialu_reg_reg_shift);
11554 %}
11555
11556 instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
11557 iRegIorL2I src1, iRegIorL2I src2,
11558 immI src3, immI_M1 src4, rFlagsReg cr) %{
11559 match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
11560 ins_cost(1.9 * INSN_COST);
11561 format %{ "eonw $dst, $src1, $src2, ASR $src3" %}
11562
11563 ins_encode %{
11564 __ eonw(as_Register($dst$$reg),
11565 as_Register($src1$$reg),
11566 as_Register($src2$$reg),
11567 Assembler::ASR,
11568 $src3$$constant & 0x1f);
11569 %}
11570
11571 ins_pipe(ialu_reg_reg_shift);
11572 %}
11573
11574 instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
11575 iRegL src1, iRegL src2,
11576 immI src3, immL_M1 src4, rFlagsReg cr) %{
11577 match(Set dst (XorL src4 (XorL(RShiftL src2 src3) src1)));
11578 ins_cost(1.9 * INSN_COST);
11579 format %{ "eon $dst, $src1, $src2, ASR $src3" %}
11580
11581 ins_encode %{
11582 __ eon(as_Register($dst$$reg),
11583 as_Register($src1$$reg),
11584 as_Register($src2$$reg),
11585 Assembler::ASR,
11586 $src3$$constant & 0x3f);
11587 %}
11588
11589 ins_pipe(ialu_reg_reg_shift);
11590 %}
11591
11592 instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
11593 iRegIorL2I src1, iRegIorL2I src2,
11594 immI src3, immI_M1 src4, rFlagsReg cr) %{
11595 match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
11596 ins_cost(1.9 * INSN_COST);
11597 format %{ "eonw $dst, $src1, $src2, LSL $src3" %}
11598
11599 ins_encode %{
11600 __ eonw(as_Register($dst$$reg),
11601 as_Register($src1$$reg),
11602 as_Register($src2$$reg),
11603 Assembler::LSL,
11604 $src3$$constant & 0x1f);
11605 %}
11606
11607 ins_pipe(ialu_reg_reg_shift);
11608 %}
11609
11610 instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
11611 iRegL src1, iRegL src2,
11612 immI src3, immL_M1 src4, rFlagsReg cr) %{
11613 match(Set dst (XorL src4 (XorL(LShiftL src2 src3) src1)));
11614 ins_cost(1.9 * INSN_COST);
11615 format %{ "eon $dst, $src1, $src2, LSL $src3" %}
11616
11617 ins_encode %{
11618 __ eon(as_Register($dst$$reg),
11619 as_Register($src1$$reg),
11620 as_Register($src2$$reg),
11621 Assembler::LSL,
11622 $src3$$constant & 0x3f);
11623 %}
11624
11625 ins_pipe(ialu_reg_reg_shift);
11626 %}
11627
11628 instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
11629 iRegIorL2I src1, iRegIorL2I src2,
11630 immI src3, immI_M1 src4, rFlagsReg cr) %{
11631 match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
11632 ins_cost(1.9 * INSN_COST);
11633 format %{ "ornw $dst, $src1, $src2, LSR $src3" %}
11634
11635 ins_encode %{
11636 __ ornw(as_Register($dst$$reg),
11637 as_Register($src1$$reg),
11638 as_Register($src2$$reg),
11639 Assembler::LSR,
11640 $src3$$constant & 0x1f);
11641 %}
11642
11643 ins_pipe(ialu_reg_reg_shift);
11644 %}
11645
11646 instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
11647 iRegL src1, iRegL src2,
11648 immI src3, immL_M1 src4, rFlagsReg cr) %{
11649 match(Set dst (OrL src1 (XorL(URShiftL src2 src3) src4)));
11650 ins_cost(1.9 * INSN_COST);
11651 format %{ "orn $dst, $src1, $src2, LSR $src3" %}
11652
11653 ins_encode %{
11654 __ orn(as_Register($dst$$reg),
11655 as_Register($src1$$reg),
11656 as_Register($src2$$reg),
11657 Assembler::LSR,
11658 $src3$$constant & 0x3f);
11659 %}
11660
11661 ins_pipe(ialu_reg_reg_shift);
11662 %}
11663
11664 instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
11665 iRegIorL2I src1, iRegIorL2I src2,
11666 immI src3, immI_M1 src4, rFlagsReg cr) %{
11667 match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
11668 ins_cost(1.9 * INSN_COST);
11669 format %{ "ornw $dst, $src1, $src2, ASR $src3" %}
11670
11671 ins_encode %{
11672 __ ornw(as_Register($dst$$reg),
11673 as_Register($src1$$reg),
11674 as_Register($src2$$reg),
11675 Assembler::ASR,
11676 $src3$$constant & 0x1f);
11677 %}
11678
11679 ins_pipe(ialu_reg_reg_shift);
11680 %}
11681
11682 instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
11683 iRegL src1, iRegL src2,
11684 immI src3, immL_M1 src4, rFlagsReg cr) %{
11685 match(Set dst (OrL src1 (XorL(RShiftL src2 src3) src4)));
11686 ins_cost(1.9 * INSN_COST);
11687 format %{ "orn $dst, $src1, $src2, ASR $src3" %}
11688
11689 ins_encode %{
11690 __ orn(as_Register($dst$$reg),
11691 as_Register($src1$$reg),
11692 as_Register($src2$$reg),
11693 Assembler::ASR,
11694 $src3$$constant & 0x3f);
11695 %}
11696
11697 ins_pipe(ialu_reg_reg_shift);
11698 %}
11699
11700 instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
11701 iRegIorL2I src1, iRegIorL2I src2,
11702 immI src3, immI_M1 src4, rFlagsReg cr) %{
11703 match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
11704 ins_cost(1.9 * INSN_COST);
11705 format %{ "ornw $dst, $src1, $src2, LSL $src3" %}
11706
11707 ins_encode %{
11708 __ ornw(as_Register($dst$$reg),
11709 as_Register($src1$$reg),
11710 as_Register($src2$$reg),
11711 Assembler::LSL,
11712 $src3$$constant & 0x1f);
11713 %}
11714
11715 ins_pipe(ialu_reg_reg_shift);
11716 %}
11717
11718 instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
11719 iRegL src1, iRegL src2,
11720 immI src3, immL_M1 src4, rFlagsReg cr) %{
11721 match(Set dst (OrL src1 (XorL(LShiftL src2 src3) src4)));
11722 ins_cost(1.9 * INSN_COST);
11723 format %{ "orn $dst, $src1, $src2, LSL $src3" %}
11724
11725 ins_encode %{
11726 __ orn(as_Register($dst$$reg),
11727 as_Register($src1$$reg),
11728 as_Register($src2$$reg),
11729 Assembler::LSL,
11730 $src3$$constant & 0x3f);
11731 %}
11732
11733 ins_pipe(ialu_reg_reg_shift);
11734 %}
11735
11736 instruct AndI_reg_URShift_reg(iRegINoSp dst,
11737 iRegIorL2I src1, iRegIorL2I src2,
11738 immI src3, rFlagsReg cr) %{
11739 match(Set dst (AndI src1 (URShiftI src2 src3)));
11740
11741 ins_cost(1.9 * INSN_COST);
11742 format %{ "andw $dst, $src1, $src2, LSR $src3" %}
11743
11744 ins_encode %{
11745 __ andw(as_Register($dst$$reg),
11746 as_Register($src1$$reg),
11747 as_Register($src2$$reg),
11748 Assembler::LSR,
11749 $src3$$constant & 0x1f);
11750 %}
11751
11752 ins_pipe(ialu_reg_reg_shift);
11753 %}
11754
11755 instruct AndL_reg_URShift_reg(iRegLNoSp dst,
11756 iRegL src1, iRegL src2,
11757 immI src3, rFlagsReg cr) %{
11758 match(Set dst (AndL src1 (URShiftL src2 src3)));
11759
11760 ins_cost(1.9 * INSN_COST);
11761 format %{ "andr $dst, $src1, $src2, LSR $src3" %}
11762
11763 ins_encode %{
11764 __ andr(as_Register($dst$$reg),
11765 as_Register($src1$$reg),
11766 as_Register($src2$$reg),
11767 Assembler::LSR,
11768 $src3$$constant & 0x3f);
11769 %}
11770
11771 ins_pipe(ialu_reg_reg_shift);
11772 %}
11773
11774 instruct AndI_reg_RShift_reg(iRegINoSp dst,
11775 iRegIorL2I src1, iRegIorL2I src2,
11776 immI src3, rFlagsReg cr) %{
11777 match(Set dst (AndI src1 (RShiftI src2 src3)));
11778
11779 ins_cost(1.9 * INSN_COST);
11780 format %{ "andw $dst, $src1, $src2, ASR $src3" %}
11781
11782 ins_encode %{
11783 __ andw(as_Register($dst$$reg),
11784 as_Register($src1$$reg),
11785 as_Register($src2$$reg),
11786 Assembler::ASR,
11787 $src3$$constant & 0x1f);
11788 %}
11789
11790 ins_pipe(ialu_reg_reg_shift);
11791 %}
11792
11793 instruct AndL_reg_RShift_reg(iRegLNoSp dst,
11794 iRegL src1, iRegL src2,
11795 immI src3, rFlagsReg cr) %{
11796 match(Set dst (AndL src1 (RShiftL src2 src3)));
11797
11798 ins_cost(1.9 * INSN_COST);
11799 format %{ "andr $dst, $src1, $src2, ASR $src3" %}
11800
11801 ins_encode %{
11802 __ andr(as_Register($dst$$reg),
11803 as_Register($src1$$reg),
11804 as_Register($src2$$reg),
11805 Assembler::ASR,
11806 $src3$$constant & 0x3f);
11807 %}
11808
11809 ins_pipe(ialu_reg_reg_shift);
11810 %}
11811
11812 instruct AndI_reg_LShift_reg(iRegINoSp dst,
11813 iRegIorL2I src1, iRegIorL2I src2,
11814 immI src3, rFlagsReg cr) %{
11815 match(Set dst (AndI src1 (LShiftI src2 src3)));
11816
11817 ins_cost(1.9 * INSN_COST);
11818 format %{ "andw $dst, $src1, $src2, LSL $src3" %}
11819
11820 ins_encode %{
11821 __ andw(as_Register($dst$$reg),
11822 as_Register($src1$$reg),
11823 as_Register($src2$$reg),
11824 Assembler::LSL,
11825 $src3$$constant & 0x1f);
11826 %}
11827
11828 ins_pipe(ialu_reg_reg_shift);
11829 %}
11830
11831 instruct AndL_reg_LShift_reg(iRegLNoSp dst,
11832 iRegL src1, iRegL src2,
11833 immI src3, rFlagsReg cr) %{
11834 match(Set dst (AndL src1 (LShiftL src2 src3)));
11835
11836 ins_cost(1.9 * INSN_COST);
11837 format %{ "andr $dst, $src1, $src2, LSL $src3" %}
11838
11839 ins_encode %{
11840 __ andr(as_Register($dst$$reg),
11841 as_Register($src1$$reg),
11842 as_Register($src2$$reg),
11843 Assembler::LSL,
11844 $src3$$constant & 0x3f);
11845 %}
11846
11847 ins_pipe(ialu_reg_reg_shift);
11848 %}
11849
11850 instruct XorI_reg_URShift_reg(iRegINoSp dst,
11851 iRegIorL2I src1, iRegIorL2I src2,
11852 immI src3, rFlagsReg cr) %{
11853 match(Set dst (XorI src1 (URShiftI src2 src3)));
11854
11855 ins_cost(1.9 * INSN_COST);
11856 format %{ "eorw $dst, $src1, $src2, LSR $src3" %}
11857
11858 ins_encode %{
11859 __ eorw(as_Register($dst$$reg),
11860 as_Register($src1$$reg),
11861 as_Register($src2$$reg),
11862 Assembler::LSR,
11863 $src3$$constant & 0x1f);
11864 %}
11865
11866 ins_pipe(ialu_reg_reg_shift);
11867 %}
11868
11869 instruct XorL_reg_URShift_reg(iRegLNoSp dst,
11870 iRegL src1, iRegL src2,
11871 immI src3, rFlagsReg cr) %{
11872 match(Set dst (XorL src1 (URShiftL src2 src3)));
11873
11874 ins_cost(1.9 * INSN_COST);
11875 format %{ "eor $dst, $src1, $src2, LSR $src3" %}
11876
11877 ins_encode %{
11878 __ eor(as_Register($dst$$reg),
11879 as_Register($src1$$reg),
11880 as_Register($src2$$reg),
11881 Assembler::LSR,
11882 $src3$$constant & 0x3f);
11883 %}
11884
11885 ins_pipe(ialu_reg_reg_shift);
11886 %}
11887
11888 instruct XorI_reg_RShift_reg(iRegINoSp dst,
11889 iRegIorL2I src1, iRegIorL2I src2,
11890 immI src3, rFlagsReg cr) %{
11891 match(Set dst (XorI src1 (RShiftI src2 src3)));
11892
11893 ins_cost(1.9 * INSN_COST);
11894 format %{ "eorw $dst, $src1, $src2, ASR $src3" %}
11895
11896 ins_encode %{
11897 __ eorw(as_Register($dst$$reg),
11898 as_Register($src1$$reg),
11899 as_Register($src2$$reg),
11900 Assembler::ASR,
11901 $src3$$constant & 0x1f);
11902 %}
11903
11904 ins_pipe(ialu_reg_reg_shift);
11905 %}
11906
11907 instruct XorL_reg_RShift_reg(iRegLNoSp dst,
11908 iRegL src1, iRegL src2,
11909 immI src3, rFlagsReg cr) %{
11910 match(Set dst (XorL src1 (RShiftL src2 src3)));
11911
11912 ins_cost(1.9 * INSN_COST);
11913 format %{ "eor $dst, $src1, $src2, ASR $src3" %}
11914
11915 ins_encode %{
11916 __ eor(as_Register($dst$$reg),
11917 as_Register($src1$$reg),
11918 as_Register($src2$$reg),
11919 Assembler::ASR,
11920 $src3$$constant & 0x3f);
11921 %}
11922
11923 ins_pipe(ialu_reg_reg_shift);
11924 %}
11925
11926 instruct XorI_reg_LShift_reg(iRegINoSp dst,
11927 iRegIorL2I src1, iRegIorL2I src2,
11928 immI src3, rFlagsReg cr) %{
11929 match(Set dst (XorI src1 (LShiftI src2 src3)));
11930
11931 ins_cost(1.9 * INSN_COST);
11932 format %{ "eorw $dst, $src1, $src2, LSL $src3" %}
11933
11934 ins_encode %{
11935 __ eorw(as_Register($dst$$reg),
11936 as_Register($src1$$reg),
11937 as_Register($src2$$reg),
11938 Assembler::LSL,
11939 $src3$$constant & 0x1f);
11940 %}
11941
11942 ins_pipe(ialu_reg_reg_shift);
11943 %}
11944
11945 instruct XorL_reg_LShift_reg(iRegLNoSp dst,
11946 iRegL src1, iRegL src2,
11947 immI src3, rFlagsReg cr) %{
11948 match(Set dst (XorL src1 (LShiftL src2 src3)));
11949
11950 ins_cost(1.9 * INSN_COST);
11951 format %{ "eor $dst, $src1, $src2, LSL $src3" %}
11952
11953 ins_encode %{
11954 __ eor(as_Register($dst$$reg),
11955 as_Register($src1$$reg),
11956 as_Register($src2$$reg),
11957 Assembler::LSL,
11958 $src3$$constant & 0x3f);
11959 %}
11960
11961 ins_pipe(ialu_reg_reg_shift);
11962 %}
11963
11964 instruct OrI_reg_URShift_reg(iRegINoSp dst,
11965 iRegIorL2I src1, iRegIorL2I src2,
11966 immI src3, rFlagsReg cr) %{
11967 match(Set dst (OrI src1 (URShiftI src2 src3)));
11968
11969 ins_cost(1.9 * INSN_COST);
11970 format %{ "orrw $dst, $src1, $src2, LSR $src3" %}
11971
11972 ins_encode %{
11973 __ orrw(as_Register($dst$$reg),
11974 as_Register($src1$$reg),
11975 as_Register($src2$$reg),
11976 Assembler::LSR,
11977 $src3$$constant & 0x1f);
11978 %}
11979
11980 ins_pipe(ialu_reg_reg_shift);
11981 %}
11982
11983 instruct OrL_reg_URShift_reg(iRegLNoSp dst,
11984 iRegL src1, iRegL src2,
11985 immI src3, rFlagsReg cr) %{
11986 match(Set dst (OrL src1 (URShiftL src2 src3)));
11987
11988 ins_cost(1.9 * INSN_COST);
11989 format %{ "orr $dst, $src1, $src2, LSR $src3" %}
11990
11991 ins_encode %{
11992 __ orr(as_Register($dst$$reg),
11993 as_Register($src1$$reg),
11994 as_Register($src2$$reg),
11995 Assembler::LSR,
11996 $src3$$constant & 0x3f);
11997 %}
11998
11999 ins_pipe(ialu_reg_reg_shift);
12000 %}
12001
12002 instruct OrI_reg_RShift_reg(iRegINoSp dst,
12003 iRegIorL2I src1, iRegIorL2I src2,
12004 immI src3, rFlagsReg cr) %{
12005 match(Set dst (OrI src1 (RShiftI src2 src3)));
12006
12007 ins_cost(1.9 * INSN_COST);
12008 format %{ "orrw $dst, $src1, $src2, ASR $src3" %}
12009
12010 ins_encode %{
12011 __ orrw(as_Register($dst$$reg),
12012 as_Register($src1$$reg),
12013 as_Register($src2$$reg),
12014 Assembler::ASR,
12015 $src3$$constant & 0x1f);
12016 %}
12017
12018 ins_pipe(ialu_reg_reg_shift);
12019 %}
12020
12021 instruct OrL_reg_RShift_reg(iRegLNoSp dst,
12022 iRegL src1, iRegL src2,
12023 immI src3, rFlagsReg cr) %{
12024 match(Set dst (OrL src1 (RShiftL src2 src3)));
12025
12026 ins_cost(1.9 * INSN_COST);
12027 format %{ "orr $dst, $src1, $src2, ASR $src3" %}
12028
12029 ins_encode %{
12030 __ orr(as_Register($dst$$reg),
12031 as_Register($src1$$reg),
12032 as_Register($src2$$reg),
12033 Assembler::ASR,
12034 $src3$$constant & 0x3f);
12035 %}
12036
12037 ins_pipe(ialu_reg_reg_shift);
12038 %}
12039
12040 instruct OrI_reg_LShift_reg(iRegINoSp dst,
12041 iRegIorL2I src1, iRegIorL2I src2,
12042 immI src3, rFlagsReg cr) %{
12043 match(Set dst (OrI src1 (LShiftI src2 src3)));
12044
12045 ins_cost(1.9 * INSN_COST);
12046 format %{ "orrw $dst, $src1, $src2, LSL $src3" %}
12047
12048 ins_encode %{
12049 __ orrw(as_Register($dst$$reg),
12050 as_Register($src1$$reg),
12051 as_Register($src2$$reg),
12052 Assembler::LSL,
12053 $src3$$constant & 0x1f);
12054 %}
12055
12056 ins_pipe(ialu_reg_reg_shift);
12057 %}
12058
12059 instruct OrL_reg_LShift_reg(iRegLNoSp dst,
12060 iRegL src1, iRegL src2,
12061 immI src3, rFlagsReg cr) %{
12062 match(Set dst (OrL src1 (LShiftL src2 src3)));
12063
12064 ins_cost(1.9 * INSN_COST);
12065 format %{ "orr $dst, $src1, $src2, LSL $src3" %}
12066
12067 ins_encode %{
12068 __ orr(as_Register($dst$$reg),
12069 as_Register($src1$$reg),
12070 as_Register($src2$$reg),
12071 Assembler::LSL,
12072 $src3$$constant & 0x3f);
12073 %}
12074
12075 ins_pipe(ialu_reg_reg_shift);
12076 %}
12077
12078 instruct AddI_reg_URShift_reg(iRegINoSp dst,
12079 iRegIorL2I src1, iRegIorL2I src2,
12080 immI src3, rFlagsReg cr) %{
12081 match(Set dst (AddI src1 (URShiftI src2 src3)));
12082
12083 ins_cost(1.9 * INSN_COST);
12084 format %{ "addw $dst, $src1, $src2, LSR $src3" %}
12085
12086 ins_encode %{
12087 __ addw(as_Register($dst$$reg),
12088 as_Register($src1$$reg),
12089 as_Register($src2$$reg),
12090 Assembler::LSR,
12091 $src3$$constant & 0x1f);
12092 %}
12093
12094 ins_pipe(ialu_reg_reg_shift);
12095 %}
12096
12097 instruct AddL_reg_URShift_reg(iRegLNoSp dst,
12098 iRegL src1, iRegL src2,
12099 immI src3, rFlagsReg cr) %{
12100 match(Set dst (AddL src1 (URShiftL src2 src3)));
12101
12102 ins_cost(1.9 * INSN_COST);
12103 format %{ "add $dst, $src1, $src2, LSR $src3" %}
12104
12105 ins_encode %{
12106 __ add(as_Register($dst$$reg),
12107 as_Register($src1$$reg),
12108 as_Register($src2$$reg),
12109 Assembler::LSR,
12110 $src3$$constant & 0x3f);
12111 %}
12112
12113 ins_pipe(ialu_reg_reg_shift);
12114 %}
12115
12116 instruct AddI_reg_RShift_reg(iRegINoSp dst,
12117 iRegIorL2I src1, iRegIorL2I src2,
12118 immI src3, rFlagsReg cr) %{
12119 match(Set dst (AddI src1 (RShiftI src2 src3)));
12120
12121 ins_cost(1.9 * INSN_COST);
12122 format %{ "addw $dst, $src1, $src2, ASR $src3" %}
12123
12124 ins_encode %{
12125 __ addw(as_Register($dst$$reg),
12126 as_Register($src1$$reg),
12127 as_Register($src2$$reg),
12128 Assembler::ASR,
12129 $src3$$constant & 0x1f);
12130 %}
12131
12132 ins_pipe(ialu_reg_reg_shift);
12133 %}
12134
12135 instruct AddL_reg_RShift_reg(iRegLNoSp dst,
12136 iRegL src1, iRegL src2,
12137 immI src3, rFlagsReg cr) %{
12138 match(Set dst (AddL src1 (RShiftL src2 src3)));
12139
12140 ins_cost(1.9 * INSN_COST);
12141 format %{ "add $dst, $src1, $src2, ASR $src3" %}
12142
12143 ins_encode %{
12144 __ add(as_Register($dst$$reg),
12145 as_Register($src1$$reg),
12146 as_Register($src2$$reg),
12147 Assembler::ASR,
12148 $src3$$constant & 0x3f);
12149 %}
12150
12151 ins_pipe(ialu_reg_reg_shift);
12152 %}
12153
12154 instruct AddI_reg_LShift_reg(iRegINoSp dst,
12155 iRegIorL2I src1, iRegIorL2I src2,
12156 immI src3, rFlagsReg cr) %{
12157 match(Set dst (AddI src1 (LShiftI src2 src3)));
12158
12159 ins_cost(1.9 * INSN_COST);
12160 format %{ "addw $dst, $src1, $src2, LSL $src3" %}
12161
12162 ins_encode %{
12163 __ addw(as_Register($dst$$reg),
12164 as_Register($src1$$reg),
12165 as_Register($src2$$reg),
12166 Assembler::LSL,
12167 $src3$$constant & 0x1f);
12168 %}
12169
12170 ins_pipe(ialu_reg_reg_shift);
12171 %}
12172
12173 instruct AddL_reg_LShift_reg(iRegLNoSp dst,
12174 iRegL src1, iRegL src2,
12175 immI src3, rFlagsReg cr) %{
12176 match(Set dst (AddL src1 (LShiftL src2 src3)));
12177
12178 ins_cost(1.9 * INSN_COST);
12179 format %{ "add $dst, $src1, $src2, LSL $src3" %}
12180
12181 ins_encode %{
12182 __ add(as_Register($dst$$reg),
12183 as_Register($src1$$reg),
12184 as_Register($src2$$reg),
12185 Assembler::LSL,
12186 $src3$$constant & 0x3f);
12187 %}
12188
12189 ins_pipe(ialu_reg_reg_shift);
12190 %}
12191
12192 instruct SubI_reg_URShift_reg(iRegINoSp dst,
12193 iRegIorL2I src1, iRegIorL2I src2,
12194 immI src3, rFlagsReg cr) %{
12195 match(Set dst (SubI src1 (URShiftI src2 src3)));
12196
12197 ins_cost(1.9 * INSN_COST);
12198 format %{ "subw $dst, $src1, $src2, LSR $src3" %}
12199
12200 ins_encode %{
12201 __ subw(as_Register($dst$$reg),
12202 as_Register($src1$$reg),
12203 as_Register($src2$$reg),
12204 Assembler::LSR,
12205 $src3$$constant & 0x1f);
12206 %}
12207
12208 ins_pipe(ialu_reg_reg_shift);
12209 %}
12210
12211 instruct SubL_reg_URShift_reg(iRegLNoSp dst,
12212 iRegL src1, iRegL src2,
12213 immI src3, rFlagsReg cr) %{
12214 match(Set dst (SubL src1 (URShiftL src2 src3)));
12215
12216 ins_cost(1.9 * INSN_COST);
12217 format %{ "sub $dst, $src1, $src2, LSR $src3" %}
12218
12219 ins_encode %{
12220 __ sub(as_Register($dst$$reg),
12221 as_Register($src1$$reg),
12222 as_Register($src2$$reg),
12223 Assembler::LSR,
12224 $src3$$constant & 0x3f);
12225 %}
12226
12227 ins_pipe(ialu_reg_reg_shift);
12228 %}
12229
12230 instruct SubI_reg_RShift_reg(iRegINoSp dst,
12231 iRegIorL2I src1, iRegIorL2I src2,
12232 immI src3, rFlagsReg cr) %{
12233 match(Set dst (SubI src1 (RShiftI src2 src3)));
12234
12235 ins_cost(1.9 * INSN_COST);
12236 format %{ "subw $dst, $src1, $src2, ASR $src3" %}
12237
12238 ins_encode %{
12239 __ subw(as_Register($dst$$reg),
12240 as_Register($src1$$reg),
12241 as_Register($src2$$reg),
12242 Assembler::ASR,
12243 $src3$$constant & 0x1f);
12244 %}
12245
12246 ins_pipe(ialu_reg_reg_shift);
12247 %}
12248
12249 instruct SubL_reg_RShift_reg(iRegLNoSp dst,
12250 iRegL src1, iRegL src2,
12251 immI src3, rFlagsReg cr) %{
12252 match(Set dst (SubL src1 (RShiftL src2 src3)));
12253
12254 ins_cost(1.9 * INSN_COST);
12255 format %{ "sub $dst, $src1, $src2, ASR $src3" %}
12256
12257 ins_encode %{
12258 __ sub(as_Register($dst$$reg),
12259 as_Register($src1$$reg),
12260 as_Register($src2$$reg),
12261 Assembler::ASR,
12262 $src3$$constant & 0x3f);
12263 %}
12264
12265 ins_pipe(ialu_reg_reg_shift);
12266 %}
12267
12268 instruct SubI_reg_LShift_reg(iRegINoSp dst,
12269 iRegIorL2I src1, iRegIorL2I src2,
12270 immI src3, rFlagsReg cr) %{
12271 match(Set dst (SubI src1 (LShiftI src2 src3)));
12272
12273 ins_cost(1.9 * INSN_COST);
12274 format %{ "subw $dst, $src1, $src2, LSL $src3" %}
12275
12276 ins_encode %{
12277 __ subw(as_Register($dst$$reg),
12278 as_Register($src1$$reg),
12279 as_Register($src2$$reg),
12280 Assembler::LSL,
12281 $src3$$constant & 0x1f);
12282 %}
12283
12284 ins_pipe(ialu_reg_reg_shift);
12285 %}
12286
12287 instruct SubL_reg_LShift_reg(iRegLNoSp dst,
12288 iRegL src1, iRegL src2,
12289 immI src3, rFlagsReg cr) %{
12290 match(Set dst (SubL src1 (LShiftL src2 src3)));
12291
12292 ins_cost(1.9 * INSN_COST);
12293 format %{ "sub $dst, $src1, $src2, LSL $src3" %}
12294
12295 ins_encode %{
12296 __ sub(as_Register($dst$$reg),
12297 as_Register($src1$$reg),
12298 as_Register($src2$$reg),
12299 Assembler::LSL,
12300 $src3$$constant & 0x3f);
12301 %}
12302
12303 ins_pipe(ialu_reg_reg_shift);
12304 %}
12305
12306
12307
12308 // Shift Left followed by Shift Right.
12309 // This idiom is used by the compiler for the i2b bytecode etc.
12310 instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12311 %{
12312 match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));
12313 // Make sure we are not going to exceed what sbfm can do.
12314 predicate((unsigned int)n->in(2)->get_int() <= 63
12315 && (unsigned int)n->in(1)->in(2)->get_int() <= 63);
12316
12317 ins_cost(INSN_COST * 2);
12318 format %{ "sbfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12319 ins_encode %{
12320 int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12321 int s = 63 - lshift;
12322 int r = (rshift - lshift) & 63;
12323 __ sbfm(as_Register($dst$$reg),
12324 as_Register($src$$reg),
12325 r, s);
12326 %}
12327
12328 ins_pipe(ialu_reg_shift);
12329 %}
12330
12331 // Shift Left followed by Shift Right.
12332 // This idiom is used by the compiler for the i2b bytecode etc.
12333 instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12334 %{
12335 match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
12336 // Make sure we are not going to exceed what sbfmw can do.
12337 predicate((unsigned int)n->in(2)->get_int() <= 31
12338 && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
12339
12340 ins_cost(INSN_COST * 2);
12341 format %{ "sbfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12342 ins_encode %{
12343 int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12344 int s = 31 - lshift;
12345 int r = (rshift - lshift) & 31;
12346 __ sbfmw(as_Register($dst$$reg),
12347 as_Register($src$$reg),
12348 r, s);
12349 %}
12350
12351 ins_pipe(ialu_reg_shift);
12352 %}
12353
12354 // Shift Left followed by Shift Right.
12355 // This idiom is used by the compiler for the i2b bytecode etc.
12356 instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12357 %{
12358 match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));
12359 // Make sure we are not going to exceed what ubfm can do.
12360 predicate((unsigned int)n->in(2)->get_int() <= 63
12361 && (unsigned int)n->in(1)->in(2)->get_int() <= 63);
12362
12363 ins_cost(INSN_COST * 2);
12364 format %{ "ubfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12365 ins_encode %{
12366 int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12367 int s = 63 - lshift;
12368 int r = (rshift - lshift) & 63;
12369 __ ubfm(as_Register($dst$$reg),
12370 as_Register($src$$reg),
12371 r, s);
12372 %}
12373
12374 ins_pipe(ialu_reg_shift);
12375 %}
12376
12377 // Shift Left followed by Shift Right.
12378 // This idiom is used by the compiler for the i2b bytecode etc.
12379 instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12380 %{
12381 match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
12382 // Make sure we are not going to exceed what ubfmw can do.
12383 predicate((unsigned int)n->in(2)->get_int() <= 31
12384 && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
12385
12386 ins_cost(INSN_COST * 2);
12387 format %{ "ubfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12388 ins_encode %{
12389 int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12390 int s = 31 - lshift;
12391 int r = (rshift - lshift) & 31;
12392 __ ubfmw(as_Register($dst$$reg),
12393 as_Register($src$$reg),
12394 r, s);
12395 %}
12396
12397 ins_pipe(ialu_reg_shift);
12398 %}
12399 // Bitfield extract with shift & mask
12400
12401 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12402 %{
12403 match(Set dst (AndI (URShiftI src rshift) mask));
12404
12405 ins_cost(INSN_COST);
12406 format %{ "ubfxw $dst, $src, $mask" %}
12407 ins_encode %{
12408 int rshift = $rshift$$constant;
12409 long mask = $mask$$constant;
12410 int width = exact_log2(mask+1);
12411 __ ubfxw(as_Register($dst$$reg),
12412 as_Register($src$$reg), rshift, width);
12413 %}
12414 ins_pipe(ialu_reg_shift);
12415 %}
12416 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
12417 %{
12418 match(Set dst (AndL (URShiftL src rshift) mask));
12419
12420 ins_cost(INSN_COST);
12421 format %{ "ubfx $dst, $src, $mask" %}
12422 ins_encode %{
12423 int rshift = $rshift$$constant;
12424 long mask = $mask$$constant;
12425 int width = exact_log2(mask+1);
12426 __ ubfx(as_Register($dst$$reg),
12427 as_Register($src$$reg), rshift, width);
12428 %}
12429 ins_pipe(ialu_reg_shift);
12430 %}
12431
12432 // We can use ubfx when extending an And with a mask when we know mask
12433 // is positive. We know that because immI_bitmask guarantees it.
12434 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12435 %{
12436 match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
12437
12438 ins_cost(INSN_COST * 2);
12439 format %{ "ubfx $dst, $src, $mask" %}
12440 ins_encode %{
12441 int rshift = $rshift$$constant;
12442 long mask = $mask$$constant;
12443 int width = exact_log2(mask+1);
12444 __ ubfx(as_Register($dst$$reg),
12445 as_Register($src$$reg), rshift, width);
12446 %}
12447 ins_pipe(ialu_reg_shift);
12448 %}
12449
12450 // Rotations
12451
12452 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12453 %{
12454 match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12455 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
12456
12457 ins_cost(INSN_COST);
12458 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12459
12460 ins_encode %{
12461 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12462 $rshift$$constant & 63);
12463 %}
12464 ins_pipe(ialu_reg_reg_extr);
12465 %}
12466
12467 instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12468 %{
12469 match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12470 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
12471
12472 ins_cost(INSN_COST);
12473 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12474
12475 ins_encode %{
12476 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12477 $rshift$$constant & 31);
12478 %}
12479 ins_pipe(ialu_reg_reg_extr);
12480 %}
12481
12482 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12483 %{
12484 match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12485 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
12486
12487 ins_cost(INSN_COST);
12488 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12489
12490 ins_encode %{
12491 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12492 $rshift$$constant & 63);
12493 %}
12494 ins_pipe(ialu_reg_reg_extr);
12495 %}
12496
12497 instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12498 %{
12499 match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12500 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
12501
12502 ins_cost(INSN_COST);
12503 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12504
12505 ins_encode %{
12506 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12507 $rshift$$constant & 31);
12508 %}
12509 ins_pipe(ialu_reg_reg_extr);
12510 %}
12511
12512
12513 // rol expander
12514
12515 instruct rolL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
12516 %{
12517 effect(DEF dst, USE src, USE shift);
12518
12519 format %{ "rol $dst, $src, $shift" %}
12520 ins_cost(INSN_COST * 3);
12521 ins_encode %{
12522 __ subw(rscratch1, zr, as_Register($shift$$reg));
12523 __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
12524 rscratch1);
12525 %}
12526 ins_pipe(ialu_reg_reg_vshift);
12527 %}
12528
12529 // rol expander
12530
12531 instruct rolI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr)
12532 %{
12533 effect(DEF dst, USE src, USE shift);
12534
12535 format %{ "rol $dst, $src, $shift" %}
12536 ins_cost(INSN_COST * 3);
12537 ins_encode %{
12538 __ subw(rscratch1, zr, as_Register($shift$$reg));
12539 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
12540 rscratch1);
12541 %}
12542 ins_pipe(ialu_reg_reg_vshift);
12543 %}
12544
12545 instruct rolL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
12546 %{
12547 match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift))));
12548
12549 expand %{
12550 rolL_rReg(dst, src, shift, cr);
12551 %}
12552 %}
12553
12554 instruct rolL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
12555 %{
12556 match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c0 shift))));
12557
12558 expand %{
12559 rolL_rReg(dst, src, shift, cr);
12560 %}
12561 %}
12562
12563 instruct rolI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
12564 %{
12565 match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
12566
12567 expand %{
12568 rolI_rReg(dst, src, shift, cr);
12569 %}
12570 %}
12571
12572 instruct rolI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
12573 %{
12574 match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
12575
12576 expand %{
12577 rolI_rReg(dst, src, shift, cr);
12578 %}
12579 %}
12580
12581 // ror expander
12582
12583 instruct rorL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
12584 %{
12585 effect(DEF dst, USE src, USE shift);
12586
12587 format %{ "ror $dst, $src, $shift" %}
12588 ins_cost(INSN_COST);
12589 ins_encode %{
12590 __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
12591 as_Register($shift$$reg));
12592 %}
12593 ins_pipe(ialu_reg_reg_vshift);
12594 %}
12595
12596 // ror expander
12597
12598 instruct rorI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr)
12599 %{
12600 effect(DEF dst, USE src, USE shift);
12601
12602 format %{ "ror $dst, $src, $shift" %}
12603 ins_cost(INSN_COST);
12604 ins_encode %{
12605 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
12606 as_Register($shift$$reg));
12607 %}
12608 ins_pipe(ialu_reg_reg_vshift);
12609 %}
12610
12611 instruct rorL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
12612 %{
12613 match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift))));
12614
12615 expand %{
12616 rorL_rReg(dst, src, shift, cr);
12617 %}
12618 %}
12619
12620 instruct rorL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
12621 %{
12622 match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c0 shift))));
12623
12624 expand %{
12625 rorL_rReg(dst, src, shift, cr);
12626 %}
12627 %}
12628
12629 instruct rorI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
12630 %{
12631 match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
12632
12633 expand %{
12634 rorI_rReg(dst, src, shift, cr);
12635 %}
12636 %}
12637
12638 instruct rorI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
12639 %{
12640 match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
12641
12642 expand %{
12643 rorI_rReg(dst, src, shift, cr);
12644 %}
12645 %}
12646
12647 // Add/subtract (extended)
12648
12649 instruct AddExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
12650 %{
12651 match(Set dst (AddL src1 (ConvI2L src2)));
12652 ins_cost(INSN_COST);
12653 format %{ "add $dst, $src1, sxtw $src2" %}
12654
12655 ins_encode %{
12656 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12657 as_Register($src2$$reg), ext::sxtw);
12658 %}
12659 ins_pipe(ialu_reg_reg);
12660 %};
12661
12662 instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
12663 %{
12664 match(Set dst (SubL src1 (ConvI2L src2)));
12665 ins_cost(INSN_COST);
12666 format %{ "sub $dst, $src1, sxtw $src2" %}
12667
12668 ins_encode %{
12669 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12670 as_Register($src2$$reg), ext::sxtw);
12671 %}
12672 ins_pipe(ialu_reg_reg);
12673 %};
12674
12675
12676 instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
12677 %{
12678 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
12679 ins_cost(INSN_COST);
12680 format %{ "add $dst, $src1, sxth $src2" %}
12681
12682 ins_encode %{
12683 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12684 as_Register($src2$$reg), ext::sxth);
12685 %}
12686 ins_pipe(ialu_reg_reg);
12687 %}
12688
12689 instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
12690 %{
12691 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
12692 ins_cost(INSN_COST);
12693 format %{ "add $dst, $src1, sxtb $src2" %}
12694
12695 ins_encode %{
12696 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12697 as_Register($src2$$reg), ext::sxtb);
12698 %}
12699 ins_pipe(ialu_reg_reg);
12700 %}
12701
12702 instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
12703 %{
12704 match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
12705 ins_cost(INSN_COST);
12706 format %{ "add $dst, $src1, uxtb $src2" %}
12707
12708 ins_encode %{
12709 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12710 as_Register($src2$$reg), ext::uxtb);
12711 %}
12712 ins_pipe(ialu_reg_reg);
12713 %}
12714
12715 instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
12716 %{
12717 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12718 ins_cost(INSN_COST);
12719 format %{ "add $dst, $src1, sxth $src2" %}
12720
12721 ins_encode %{
12722 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12723 as_Register($src2$$reg), ext::sxth);
12724 %}
12725 ins_pipe(ialu_reg_reg);
12726 %}
12727
12728 instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
12729 %{
12730 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12731 ins_cost(INSN_COST);
12732 format %{ "add $dst, $src1, sxtw $src2" %}
12733
12734 ins_encode %{
12735 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12736 as_Register($src2$$reg), ext::sxtw);
12737 %}
12738 ins_pipe(ialu_reg_reg);
12739 %}
12740
12741 instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
12742 %{
12743 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12744 ins_cost(INSN_COST);
12745 format %{ "add $dst, $src1, sxtb $src2" %}
12746
12747 ins_encode %{
12748 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12749 as_Register($src2$$reg), ext::sxtb);
12750 %}
12751 ins_pipe(ialu_reg_reg);
12752 %}
12753
12754 instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
12755 %{
12756 match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
12757 ins_cost(INSN_COST);
12758 format %{ "add $dst, $src1, uxtb $src2" %}
12759
12760 ins_encode %{
12761 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12762 as_Register($src2$$reg), ext::uxtb);
12763 %}
12764 ins_pipe(ialu_reg_reg);
12765 %}
12766
12767
12768 instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
12769 %{
12770 match(Set dst (AddI src1 (AndI src2 mask)));
12771 ins_cost(INSN_COST);
12772 format %{ "addw $dst, $src1, $src2, uxtb" %}
12773
12774 ins_encode %{
12775 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12776 as_Register($src2$$reg), ext::uxtb);
12777 %}
12778 ins_pipe(ialu_reg_reg);
12779 %}
12780
12781 instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
12782 %{
12783 match(Set dst (AddI src1 (AndI src2 mask)));
12784 ins_cost(INSN_COST);
12785 format %{ "addw $dst, $src1, $src2, uxth" %}
12786
12787 ins_encode %{
12788 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12789 as_Register($src2$$reg), ext::uxth);
12790 %}
12791 ins_pipe(ialu_reg_reg);
12792 %}
12793
12794 instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
12795 %{
12796 match(Set dst (AddL src1 (AndL src2 mask)));
12797 ins_cost(INSN_COST);
12798 format %{ "add $dst, $src1, $src2, uxtb" %}
12799
12800 ins_encode %{
12801 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12802 as_Register($src2$$reg), ext::uxtb);
12803 %}
12804 ins_pipe(ialu_reg_reg);
12805 %}
12806
12807 instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
12808 %{
12809 match(Set dst (AddL src1 (AndL src2 mask)));
12810 ins_cost(INSN_COST);
12811 format %{ "add $dst, $src1, $src2, uxth" %}
12812
12813 ins_encode %{
12814 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12815 as_Register($src2$$reg), ext::uxth);
12816 %}
12817 ins_pipe(ialu_reg_reg);
12818 %}
12819
12820 instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
12821 %{
12822 match(Set dst (AddL src1 (AndL src2 mask)));
12823 ins_cost(INSN_COST);
12824 format %{ "add $dst, $src1, $src2, uxtw" %}
12825
12826 ins_encode %{
12827 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12828 as_Register($src2$$reg), ext::uxtw);
12829 %}
12830 ins_pipe(ialu_reg_reg);
12831 %}
12832
12833 instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
12834 %{
12835 match(Set dst (SubI src1 (AndI src2 mask)));
12836 ins_cost(INSN_COST);
12837 format %{ "subw $dst, $src1, $src2, uxtb" %}
12838
12839 ins_encode %{
12840 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
12841 as_Register($src2$$reg), ext::uxtb);
12842 %}
12843 ins_pipe(ialu_reg_reg);
12844 %}
12845
12846 instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
12847 %{
12848 match(Set dst (SubI src1 (AndI src2 mask)));
12849 ins_cost(INSN_COST);
12850 format %{ "subw $dst, $src1, $src2, uxth" %}
12851
12852 ins_encode %{
12853 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
12854 as_Register($src2$$reg), ext::uxth);
12855 %}
12856 ins_pipe(ialu_reg_reg);
12857 %}
12858
12859 instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
12860 %{
12861 match(Set dst (SubL src1 (AndL src2 mask)));
12862 ins_cost(INSN_COST);
12863 format %{ "sub $dst, $src1, $src2, uxtb" %}
12864
12865 ins_encode %{
12866 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12867 as_Register($src2$$reg), ext::uxtb);
12868 %}
12869 ins_pipe(ialu_reg_reg);
12870 %}
12871
12872 instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
12873 %{
12874 match(Set dst (SubL src1 (AndL src2 mask)));
12875 ins_cost(INSN_COST);
12876 format %{ "sub $dst, $src1, $src2, uxth" %}
12877
12878 ins_encode %{
12879 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12880 as_Register($src2$$reg), ext::uxth);
12881 %}
12882 ins_pipe(ialu_reg_reg);
12883 %}
12884
12885 instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
12886 %{
12887 match(Set dst (SubL src1 (AndL src2 mask)));
12888 ins_cost(INSN_COST);
12889 format %{ "sub $dst, $src1, $src2, uxtw" %}
12890
12891 ins_encode %{
12892 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12893 as_Register($src2$$reg), ext::uxtw);
12894 %}
12895 ins_pipe(ialu_reg_reg);
12896 %}
12897
12898 // END This section of the file is automatically generated. Do not edit --------------
12899
12900 // ============================================================================
12901 // Floating Point Arithmetic Instructions
12902
12903 instruct addF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
12904 match(Set dst (AddF src1 src2));
12905
12906 ins_cost(INSN_COST * 5);
12907 format %{ "fadds $dst, $src1, $src2" %}
12908
12909 ins_encode %{
12910 __ fadds(as_FloatRegister($dst$$reg),
12911 as_FloatRegister($src1$$reg),
12912 as_FloatRegister($src2$$reg));
12913 %}
12914
12915 ins_pipe(fp_dop_reg_reg_s);
12916 %}
12917
12918 instruct addD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
12919 match(Set dst (AddD src1 src2));
12920
12921 ins_cost(INSN_COST * 5);
12922 format %{ "faddd $dst, $src1, $src2" %}
12923
12924 ins_encode %{
12925 __ faddd(as_FloatRegister($dst$$reg),
12926 as_FloatRegister($src1$$reg),
12927 as_FloatRegister($src2$$reg));
12928 %}
12929
12930 ins_pipe(fp_dop_reg_reg_d);
12931 %}
12932
12933 instruct subF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
12934 match(Set dst (SubF src1 src2));
12935
12936 ins_cost(INSN_COST * 5);
12937 format %{ "fsubs $dst, $src1, $src2" %}
12938
12939 ins_encode %{
12940 __ fsubs(as_FloatRegister($dst$$reg),
12941 as_FloatRegister($src1$$reg),
12942 as_FloatRegister($src2$$reg));
12943 %}
12944
12945 ins_pipe(fp_dop_reg_reg_s);
12946 %}
12947
12948 instruct subD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
12949 match(Set dst (SubD src1 src2));
12950
12951 ins_cost(INSN_COST * 5);
12952 format %{ "fsubd $dst, $src1, $src2" %}
12953
12954 ins_encode %{
12955 __ fsubd(as_FloatRegister($dst$$reg),
12956 as_FloatRegister($src1$$reg),
12957 as_FloatRegister($src2$$reg));
12958 %}
12959
12960 ins_pipe(fp_dop_reg_reg_d);
12961 %}
12962
12963 instruct mulF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
12964 match(Set dst (MulF src1 src2));
12965
12966 ins_cost(INSN_COST * 6);
12967 format %{ "fmuls $dst, $src1, $src2" %}
12968
12969 ins_encode %{
12970 __ fmuls(as_FloatRegister($dst$$reg),
12971 as_FloatRegister($src1$$reg),
12972 as_FloatRegister($src2$$reg));
12973 %}
12974
12975 ins_pipe(fp_dop_reg_reg_s);
12976 %}
12977
12978 instruct mulD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
12979 match(Set dst (MulD src1 src2));
12980
12981 ins_cost(INSN_COST * 6);
12982 format %{ "fmuld $dst, $src1, $src2" %}
12983
12984 ins_encode %{
12985 __ fmuld(as_FloatRegister($dst$$reg),
12986 as_FloatRegister($src1$$reg),
12987 as_FloatRegister($src2$$reg));
12988 %}
12989
12990 ins_pipe(fp_dop_reg_reg_d);
12991 %}
12992
12993 // We cannot use these fused mul w add/sub ops because they don't
12994 // produce the same result as the equivalent separated ops
12995 // (essentially they don't round the intermediate result). that's a
12996 // shame. leaving them here in case we can idenitfy cases where it is
12997 // legitimate to use them
12998
12999
13000 // instruct maddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13001 // match(Set dst (AddF (MulF src1 src2) src3));
13002
13003 // format %{ "fmadds $dst, $src1, $src2, $src3" %}
13004
13005 // ins_encode %{
13006 // __ fmadds(as_FloatRegister($dst$$reg),
13007 // as_FloatRegister($src1$$reg),
13008 // as_FloatRegister($src2$$reg),
13009 // as_FloatRegister($src3$$reg));
13010 // %}
13011
13012 // ins_pipe(pipe_class_default);
13013 // %}
13014
13015 // instruct maddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13016 // match(Set dst (AddD (MulD src1 src2) src3));
13017
13018 // format %{ "fmaddd $dst, $src1, $src2, $src3" %}
13019
13020 // ins_encode %{
13021 // __ fmaddd(as_FloatRegister($dst$$reg),
13022 // as_FloatRegister($src1$$reg),
13023 // as_FloatRegister($src2$$reg),
13024 // as_FloatRegister($src3$$reg));
13025 // %}
13026
13027 // ins_pipe(pipe_class_default);
13028 // %}
13029
13030 // instruct msubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13031 // match(Set dst (AddF (MulF (NegF src1) src2) src3));
13032 // match(Set dst (AddF (NegF (MulF src1 src2)) src3));
13033
13034 // format %{ "fmsubs $dst, $src1, $src2, $src3" %}
13035
13036 // ins_encode %{
13037 // __ fmsubs(as_FloatRegister($dst$$reg),
13038 // as_FloatRegister($src1$$reg),
13039 // as_FloatRegister($src2$$reg),
13040 // as_FloatRegister($src3$$reg));
13041 // %}
13042
13043 // ins_pipe(pipe_class_default);
13044 // %}
13045
13046 // instruct msubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13047 // match(Set dst (AddD (MulD (NegD src1) src2) src3));
13048 // match(Set dst (AddD (NegD (MulD src1 src2)) src3));
13049
13050 // format %{ "fmsubd $dst, $src1, $src2, $src3" %}
13051
13052 // ins_encode %{
13053 // __ fmsubd(as_FloatRegister($dst$$reg),
13054 // as_FloatRegister($src1$$reg),
13055 // as_FloatRegister($src2$$reg),
13056 // as_FloatRegister($src3$$reg));
13057 // %}
13058
13059 // ins_pipe(pipe_class_default);
13060 // %}
13061
13062 // instruct mnaddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13063 // match(Set dst (SubF (MulF (NegF src1) src2) src3));
13064 // match(Set dst (SubF (NegF (MulF src1 src2)) src3));
13065
13066 // format %{ "fnmadds $dst, $src1, $src2, $src3" %}
13067
13068 // ins_encode %{
13069 // __ fnmadds(as_FloatRegister($dst$$reg),
13070 // as_FloatRegister($src1$$reg),
13071 // as_FloatRegister($src2$$reg),
13072 // as_FloatRegister($src3$$reg));
13073 // %}
13074
13075 // ins_pipe(pipe_class_default);
13076 // %}
13077
13078 // instruct mnaddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13079 // match(Set dst (SubD (MulD (NegD src1) src2) src3));
13080 // match(Set dst (SubD (NegD (MulD src1 src2)) src3));
13081
13082 // format %{ "fnmaddd $dst, $src1, $src2, $src3" %}
13083
13084 // ins_encode %{
13085 // __ fnmaddd(as_FloatRegister($dst$$reg),
13086 // as_FloatRegister($src1$$reg),
13087 // as_FloatRegister($src2$$reg),
13088 // as_FloatRegister($src3$$reg));
13089 // %}
13090
13091 // ins_pipe(pipe_class_default);
13092 // %}
13093
13094 // instruct mnsubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3, immF0 zero) %{
13095 // match(Set dst (SubF (MulF src1 src2) src3));
13096
13097 // format %{ "fnmsubs $dst, $src1, $src2, $src3" %}
13098
13099 // ins_encode %{
13100 // __ fnmsubs(as_FloatRegister($dst$$reg),
13101 // as_FloatRegister($src1$$reg),
13102 // as_FloatRegister($src2$$reg),
13103 // as_FloatRegister($src3$$reg));
13104 // %}
13105
13106 // ins_pipe(pipe_class_default);
13107 // %}
13108
13109 // instruct mnsubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3, immD0 zero) %{
13110 // match(Set dst (SubD (MulD src1 src2) src3));
13111
13112 // format %{ "fnmsubd $dst, $src1, $src2, $src3" %}
13113
13114 // ins_encode %{
13115 // // n.b. insn name should be fnmsubd
13116 // __ fnmsub(as_FloatRegister($dst$$reg),
13117 // as_FloatRegister($src1$$reg),
13118 // as_FloatRegister($src2$$reg),
13119 // as_FloatRegister($src3$$reg));
13120 // %}
13121
13122 // ins_pipe(pipe_class_default);
13123 // %}
13124
13125
13126 instruct divF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13127 match(Set dst (DivF src1 src2));
13128
13129 ins_cost(INSN_COST * 18);
13130 format %{ "fdivs $dst, $src1, $src2" %}
13131
13132 ins_encode %{
13133 __ fdivs(as_FloatRegister($dst$$reg),
13134 as_FloatRegister($src1$$reg),
13135 as_FloatRegister($src2$$reg));
13136 %}
13137
13138 ins_pipe(fp_div_s);
13139 %}
13140
13141 instruct divD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13142 match(Set dst (DivD src1 src2));
13143
13144 ins_cost(INSN_COST * 32);
13145 format %{ "fdivd $dst, $src1, $src2" %}
13146
13147 ins_encode %{
13148 __ fdivd(as_FloatRegister($dst$$reg),
13149 as_FloatRegister($src1$$reg),
13150 as_FloatRegister($src2$$reg));
13151 %}
13152
13153 ins_pipe(fp_div_d);
13154 %}
13155
13156 instruct negF_reg_reg(vRegF dst, vRegF src) %{
13157 match(Set dst (NegF src));
13158
13159 ins_cost(INSN_COST * 3);
13160 format %{ "fneg $dst, $src" %}
13161
13162 ins_encode %{
13163 __ fnegs(as_FloatRegister($dst$$reg),
13164 as_FloatRegister($src$$reg));
13165 %}
13166
13167 ins_pipe(fp_uop_s);
13168 %}
13169
13170 instruct negD_reg_reg(vRegD dst, vRegD src) %{
13171 match(Set dst (NegD src));
13172
13173 ins_cost(INSN_COST * 3);
13174 format %{ "fnegd $dst, $src" %}
13175
13176 ins_encode %{
13177 __ fnegd(as_FloatRegister($dst$$reg),
13178 as_FloatRegister($src$$reg));
13179 %}
13180
13181 ins_pipe(fp_uop_d);
13182 %}
13183
13184 instruct absF_reg(vRegF dst, vRegF src) %{
13185 match(Set dst (AbsF src));
13186
13187 ins_cost(INSN_COST * 3);
13188 format %{ "fabss $dst, $src" %}
13189 ins_encode %{
13190 __ fabss(as_FloatRegister($dst$$reg),
13191 as_FloatRegister($src$$reg));
13192 %}
13193
13194 ins_pipe(fp_uop_s);
13195 %}
13196
13197 instruct absD_reg(vRegD dst, vRegD src) %{
13198 match(Set dst (AbsD src));
13199
13200 ins_cost(INSN_COST * 3);
13201 format %{ "fabsd $dst, $src" %}
13202 ins_encode %{
13203 __ fabsd(as_FloatRegister($dst$$reg),
13204 as_FloatRegister($src$$reg));
13205 %}
13206
13207 ins_pipe(fp_uop_d);
13208 %}
13209
13210 instruct sqrtD_reg(vRegD dst, vRegD src) %{
13211 match(Set dst (SqrtD src));
13212
13213 ins_cost(INSN_COST * 50);
13214 format %{ "fsqrtd $dst, $src" %}
13215 ins_encode %{
13216 __ fsqrtd(as_FloatRegister($dst$$reg),
13217 as_FloatRegister($src$$reg));
13218 %}
13219
13220 ins_pipe(fp_div_s);
13221 %}
13222
13223 instruct sqrtF_reg(vRegF dst, vRegF src) %{
13224 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
13225
13226 ins_cost(INSN_COST * 50);
13227 format %{ "fsqrts $dst, $src" %}
13228 ins_encode %{
13229 __ fsqrts(as_FloatRegister($dst$$reg),
13230 as_FloatRegister($src$$reg));
13231 %}
13232
13233 ins_pipe(fp_div_d);
13234 %}
13235
13236 // ============================================================================
13237 // Logical Instructions
13238
13239 // Integer Logical Instructions
13240
13241 // And Instructions
13242
13243
13244 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
13245 match(Set dst (AndI src1 src2));
13246
13247 format %{ "andw $dst, $src1, $src2\t# int" %}
13248
13249 ins_cost(INSN_COST);
13250 ins_encode %{
13251 __ andw(as_Register($dst$$reg),
13252 as_Register($src1$$reg),
13253 as_Register($src2$$reg));
13254 %}
13255
13256 ins_pipe(ialu_reg_reg);
13257 %}
13258
13259 instruct andI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2, rFlagsReg cr) %{
13260 match(Set dst (AndI src1 src2));
13261
13262 format %{ "andsw $dst, $src1, $src2\t# int" %}
13263
13264 ins_cost(INSN_COST);
13265 ins_encode %{
13266 __ andw(as_Register($dst$$reg),
13267 as_Register($src1$$reg),
13268 (unsigned long)($src2$$constant));
13269 %}
13270
13271 ins_pipe(ialu_reg_imm);
13272 %}
13273
13274 // Or Instructions
13275
13276 instruct orI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
13277 match(Set dst (OrI src1 src2));
13278
13279 format %{ "orrw $dst, $src1, $src2\t# int" %}
13280
13281 ins_cost(INSN_COST);
13282 ins_encode %{
13283 __ orrw(as_Register($dst$$reg),
13284 as_Register($src1$$reg),
13285 as_Register($src2$$reg));
13286 %}
13287
13288 ins_pipe(ialu_reg_reg);
13289 %}
13290
13291 instruct orI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
13292 match(Set dst (OrI src1 src2));
13293
13294 format %{ "orrw $dst, $src1, $src2\t# int" %}
13295
13296 ins_cost(INSN_COST);
13297 ins_encode %{
13298 __ orrw(as_Register($dst$$reg),
13299 as_Register($src1$$reg),
13300 (unsigned long)($src2$$constant));
13301 %}
13302
13303 ins_pipe(ialu_reg_imm);
13304 %}
13305
13306 // Xor Instructions
13307
13308 instruct xorI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
13309 match(Set dst (XorI src1 src2));
13310
13311 format %{ "eorw $dst, $src1, $src2\t# int" %}
13312
13313 ins_cost(INSN_COST);
13314 ins_encode %{
13315 __ eorw(as_Register($dst$$reg),
13316 as_Register($src1$$reg),
13317 as_Register($src2$$reg));
13318 %}
13319
13320 ins_pipe(ialu_reg_reg);
13321 %}
13322
13323 instruct xorI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
13324 match(Set dst (XorI src1 src2));
13325
13326 format %{ "eorw $dst, $src1, $src2\t# int" %}
13327
13328 ins_cost(INSN_COST);
13329 ins_encode %{
13330 __ eorw(as_Register($dst$$reg),
13331 as_Register($src1$$reg),
13332 (unsigned long)($src2$$constant));
13333 %}
13334
13335 ins_pipe(ialu_reg_imm);
13336 %}
13337
13338 // Long Logical Instructions
13339 // TODO
13340
13341 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr) %{
13342 match(Set dst (AndL src1 src2));
13343
13344 format %{ "and $dst, $src1, $src2\t# int" %}
13345
13346 ins_cost(INSN_COST);
13347 ins_encode %{
13348 __ andr(as_Register($dst$$reg),
13349 as_Register($src1$$reg),
13350 as_Register($src2$$reg));
13351 %}
13352
13353 ins_pipe(ialu_reg_reg);
13354 %}
13355
13356 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2, rFlagsReg cr) %{
13357 match(Set dst (AndL src1 src2));
13358
13359 format %{ "and $dst, $src1, $src2\t# int" %}
13360
13361 ins_cost(INSN_COST);
13362 ins_encode %{
13363 __ andr(as_Register($dst$$reg),
13364 as_Register($src1$$reg),
13365 (unsigned long)($src2$$constant));
13366 %}
13367
13368 ins_pipe(ialu_reg_imm);
13369 %}
13370
13371 // Or Instructions
13372
13373 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
13374 match(Set dst (OrL src1 src2));
13375
13376 format %{ "orr $dst, $src1, $src2\t# int" %}
13377
13378 ins_cost(INSN_COST);
13379 ins_encode %{
13380 __ orr(as_Register($dst$$reg),
13381 as_Register($src1$$reg),
13382 as_Register($src2$$reg));
13383 %}
13384
13385 ins_pipe(ialu_reg_reg);
13386 %}
13387
13388 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
13389 match(Set dst (OrL src1 src2));
13390
13391 format %{ "orr $dst, $src1, $src2\t# int" %}
13392
13393 ins_cost(INSN_COST);
13394 ins_encode %{
13395 __ orr(as_Register($dst$$reg),
13396 as_Register($src1$$reg),
13397 (unsigned long)($src2$$constant));
13398 %}
13399
13400 ins_pipe(ialu_reg_imm);
13401 %}
13402
13403 // Xor Instructions
13404
13405 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
13406 match(Set dst (XorL src1 src2));
13407
13408 format %{ "eor $dst, $src1, $src2\t# int" %}
13409
13410 ins_cost(INSN_COST);
13411 ins_encode %{
13412 __ eor(as_Register($dst$$reg),
13413 as_Register($src1$$reg),
13414 as_Register($src2$$reg));
13415 %}
13416
13417 ins_pipe(ialu_reg_reg);
13418 %}
13419
13420 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
13421 match(Set dst (XorL src1 src2));
13422
13423 ins_cost(INSN_COST);
13424 format %{ "eor $dst, $src1, $src2\t# int" %}
13425
13426 ins_encode %{
13427 __ eor(as_Register($dst$$reg),
13428 as_Register($src1$$reg),
13429 (unsigned long)($src2$$constant));
13430 %}
13431
13432 ins_pipe(ialu_reg_imm);
13433 %}
13434
13435 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
13436 %{
13437 match(Set dst (ConvI2L src));
13438
13439 ins_cost(INSN_COST);
13440 format %{ "sxtw $dst, $src\t# i2l" %}
13441 ins_encode %{
13442 __ sbfm($dst$$Register, $src$$Register, 0, 31);
13443 %}
13444 ins_pipe(ialu_reg_shift);
13445 %}
13446
13447 // this pattern occurs in bigmath arithmetic
13448 instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
13449 %{
13450 match(Set dst (AndL (ConvI2L src) mask));
13451
13452 ins_cost(INSN_COST);
13453 format %{ "ubfm $dst, $src, 0, 31\t# ui2l" %}
13454 ins_encode %{
13455 __ ubfm($dst$$Register, $src$$Register, 0, 31);
13456 %}
13457
13458 ins_pipe(ialu_reg_shift);
13459 %}
13460
13461 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
13462 match(Set dst (ConvL2I src));
13463
13464 ins_cost(INSN_COST);
13465 format %{ "movw $dst, $src \t// l2i" %}
13466
13467 ins_encode %{
13468 __ movw(as_Register($dst$$reg), as_Register($src$$reg));
13469 %}
13470
13471 ins_pipe(ialu_reg);
13472 %}
13473
13474 instruct convI2B(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
13475 %{
13476 match(Set dst (Conv2B src));
13477 effect(KILL cr);
13478
13479 format %{
13480 "cmpw $src, zr\n\t"
13481 "cset $dst, ne"
13482 %}
13483
13484 ins_encode %{
13485 __ cmpw(as_Register($src$$reg), zr);
13486 __ cset(as_Register($dst$$reg), Assembler::NE);
13487 %}
13488
13489 ins_pipe(ialu_reg);
13490 %}
13491
13492 instruct convP2B(iRegINoSp dst, iRegP src, rFlagsReg cr)
13493 %{
13494 match(Set dst (Conv2B src));
13495 effect(KILL cr);
13496
13497 format %{
13498 "cmp $src, zr\n\t"
13499 "cset $dst, ne"
13500 %}
13501
13502 ins_encode %{
13503 __ cmp(as_Register($src$$reg), zr);
13504 __ cset(as_Register($dst$$reg), Assembler::NE);
13505 %}
13506
13507 ins_pipe(ialu_reg);
13508 %}
13509
13510 instruct convD2F_reg(vRegF dst, vRegD src) %{
13511 match(Set dst (ConvD2F src));
13512
13513 ins_cost(INSN_COST * 5);
13514 format %{ "fcvtd $dst, $src \t// d2f" %}
13515
13516 ins_encode %{
13517 __ fcvtd(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
13518 %}
13519
13520 ins_pipe(fp_d2f);
13521 %}
13522
13523 instruct convF2D_reg(vRegD dst, vRegF src) %{
13524 match(Set dst (ConvF2D src));
13525
13526 ins_cost(INSN_COST * 5);
13527 format %{ "fcvts $dst, $src \t// f2d" %}
13528
13529 ins_encode %{
13530 __ fcvts(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
13531 %}
13532
13533 ins_pipe(fp_f2d);
13534 %}
13535
13536 instruct convF2I_reg_reg(iRegINoSp dst, vRegF src) %{
13537 match(Set dst (ConvF2I src));
13538
13539 ins_cost(INSN_COST * 5);
13540 format %{ "fcvtzsw $dst, $src \t// f2i" %}
13541
13542 ins_encode %{
13543 __ fcvtzsw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
13544 %}
13545
13546 ins_pipe(fp_f2i);
13547 %}
13548
13549 instruct convF2L_reg_reg(iRegLNoSp dst, vRegF src) %{
13550 match(Set dst (ConvF2L src));
13551
13552 ins_cost(INSN_COST * 5);
13553 format %{ "fcvtzs $dst, $src \t// f2l" %}
13554
13555 ins_encode %{
13556 __ fcvtzs(as_Register($dst$$reg), as_FloatRegister($src$$reg));
13557 %}
13558
13559 ins_pipe(fp_f2l);
13560 %}
13561
13562 instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
13563 match(Set dst (ConvI2F src));
13564
13565 ins_cost(INSN_COST * 5);
13566 format %{ "scvtfws $dst, $src \t// i2f" %}
13567
13568 ins_encode %{
13569 __ scvtfws(as_FloatRegister($dst$$reg), as_Register($src$$reg));
13570 %}
13571
13572 ins_pipe(fp_i2f);
13573 %}
13574
13575 instruct convL2F_reg_reg(vRegF dst, iRegL src) %{
13576 match(Set dst (ConvL2F src));
13577
13578 ins_cost(INSN_COST * 5);
13579 format %{ "scvtfs $dst, $src \t// l2f" %}
13580
13581 ins_encode %{
13582 __ scvtfs(as_FloatRegister($dst$$reg), as_Register($src$$reg));
13583 %}
13584
13585 ins_pipe(fp_l2f);
13586 %}
13587
13588 instruct convD2I_reg_reg(iRegINoSp dst, vRegD src) %{
13589 match(Set dst (ConvD2I src));
13590
13591 ins_cost(INSN_COST * 5);
13592 format %{ "fcvtzdw $dst, $src \t// d2i" %}
13593
13594 ins_encode %{
13595 __ fcvtzdw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
13596 %}
13597
13598 ins_pipe(fp_d2i);
13599 %}
13600
13601 instruct convD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
13602 match(Set dst (ConvD2L src));
13603
13604 ins_cost(INSN_COST * 5);
13605 format %{ "fcvtzd $dst, $src \t// d2l" %}
13606
13607 ins_encode %{
13608 __ fcvtzd(as_Register($dst$$reg), as_FloatRegister($src$$reg));
13609 %}
13610
13611 ins_pipe(fp_d2l);
13612 %}
13613
13614 instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
13615 match(Set dst (ConvI2D src));
13616
13617 ins_cost(INSN_COST * 5);
13618 format %{ "scvtfwd $dst, $src \t// i2d" %}
13619
13620 ins_encode %{
13621 __ scvtfwd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
13622 %}
13623
13624 ins_pipe(fp_i2d);
13625 %}
13626
13627 instruct convL2D_reg_reg(vRegD dst, iRegL src) %{
13628 match(Set dst (ConvL2D src));
13629
13630 ins_cost(INSN_COST * 5);
13631 format %{ "scvtfd $dst, $src \t// l2d" %}
13632
13633 ins_encode %{
13634 __ scvtfd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
13635 %}
13636
13637 ins_pipe(fp_l2d);
13638 %}
13639
13640 // stack <-> reg and reg <-> reg shuffles with no conversion
13641
13642 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
13643
13644 match(Set dst (MoveF2I src));
13645
13646 effect(DEF dst, USE src);
13647
13648 ins_cost(4 * INSN_COST);
13649
13650 format %{ "ldrw $dst, $src\t# MoveF2I_stack_reg" %}
13651
13652 ins_encode %{
13653 __ ldrw($dst$$Register, Address(sp, $src$$disp));
13654 %}
13655
13656 ins_pipe(iload_reg_reg);
13657
13658 %}
13659
13660 instruct MoveI2F_stack_reg(vRegF dst, stackSlotI src) %{
13661
13662 match(Set dst (MoveI2F src));
13663
13664 effect(DEF dst, USE src);
13665
13666 ins_cost(4 * INSN_COST);
13667
13668 format %{ "ldrs $dst, $src\t# MoveI2F_stack_reg" %}
13669
13670 ins_encode %{
13671 __ ldrs(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
13672 %}
13673
13674 ins_pipe(pipe_class_memory);
13675
13676 %}
13677
13678 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
13679
13680 match(Set dst (MoveD2L src));
13681
13682 effect(DEF dst, USE src);
13683
13684 ins_cost(4 * INSN_COST);
13685
13686 format %{ "ldr $dst, $src\t# MoveD2L_stack_reg" %}
13687
13688 ins_encode %{
13689 __ ldr($dst$$Register, Address(sp, $src$$disp));
13690 %}
13691
13692 ins_pipe(iload_reg_reg);
13693
13694 %}
13695
13696 instruct MoveL2D_stack_reg(vRegD dst, stackSlotL src) %{
13697
13698 match(Set dst (MoveL2D src));
13699
13700 effect(DEF dst, USE src);
13701
13702 ins_cost(4 * INSN_COST);
13703
13704 format %{ "ldrd $dst, $src\t# MoveL2D_stack_reg" %}
13705
13706 ins_encode %{
13707 __ ldrd(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
13708 %}
13709
13710 ins_pipe(pipe_class_memory);
13711
13712 %}
13713
13714 instruct MoveF2I_reg_stack(stackSlotI dst, vRegF src) %{
13715
13716 match(Set dst (MoveF2I src));
13717
13718 effect(DEF dst, USE src);
13719
13720 ins_cost(INSN_COST);
13721
13722 format %{ "strs $src, $dst\t# MoveF2I_reg_stack" %}
13723
13724 ins_encode %{
13725 __ strs(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
13726 %}
13727
13728 ins_pipe(pipe_class_memory);
13729
13730 %}
13731
13732 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
13733
13734 match(Set dst (MoveI2F src));
13735
13736 effect(DEF dst, USE src);
13737
13738 ins_cost(INSN_COST);
13739
13740 format %{ "strw $src, $dst\t# MoveI2F_reg_stack" %}
13741
13742 ins_encode %{
13743 __ strw($src$$Register, Address(sp, $dst$$disp));
13744 %}
13745
13746 ins_pipe(istore_reg_reg);
13747
13748 %}
13749
13750 instruct MoveD2L_reg_stack(stackSlotL dst, vRegD src) %{
13751
13752 match(Set dst (MoveD2L src));
13753
13754 effect(DEF dst, USE src);
13755
13756 ins_cost(INSN_COST);
13757
13758 format %{ "strd $dst, $src\t# MoveD2L_reg_stack" %}
13759
13760 ins_encode %{
13761 __ strd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
13762 %}
13763
13764 ins_pipe(pipe_class_memory);
13765
13766 %}
13767
13768 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
13769
13770 match(Set dst (MoveL2D src));
13771
13772 effect(DEF dst, USE src);
13773
13774 ins_cost(INSN_COST);
13775
13776 format %{ "str $src, $dst\t# MoveL2D_reg_stack" %}
13777
13778 ins_encode %{
13779 __ str($src$$Register, Address(sp, $dst$$disp));
13780 %}
13781
13782 ins_pipe(istore_reg_reg);
13783
13784 %}
13785
13786 instruct MoveF2I_reg_reg(iRegINoSp dst, vRegF src) %{
13787
13788 match(Set dst (MoveF2I src));
13789
13790 effect(DEF dst, USE src);
13791
13792 ins_cost(INSN_COST);
13793
13794 format %{ "fmovs $dst, $src\t# MoveF2I_reg_reg" %}
13795
13796 ins_encode %{
13797 __ fmovs($dst$$Register, as_FloatRegister($src$$reg));
13798 %}
13799
13800 ins_pipe(fp_f2i);
13801
13802 %}
13803
13804 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{
13805
13806 match(Set dst (MoveI2F src));
13807
13808 effect(DEF dst, USE src);
13809
13810 ins_cost(INSN_COST);
13811
13812 format %{ "fmovs $dst, $src\t# MoveI2F_reg_reg" %}
13813
13814 ins_encode %{
13815 __ fmovs(as_FloatRegister($dst$$reg), $src$$Register);
13816 %}
13817
13818 ins_pipe(fp_i2f);
13819
13820 %}
13821
13822 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
13823
13824 match(Set dst (MoveD2L src));
13825
13826 effect(DEF dst, USE src);
13827
13828 ins_cost(INSN_COST);
13829
13830 format %{ "fmovd $dst, $src\t# MoveD2L_reg_reg" %}
13831
13832 ins_encode %{
13833 __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
13834 %}
13835
13836 ins_pipe(fp_d2l);
13837
13838 %}
13839
13840 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{
13841
13842 match(Set dst (MoveL2D src));
13843
13844 effect(DEF dst, USE src);
13845
13846 ins_cost(INSN_COST);
13847
13848 format %{ "fmovd $dst, $src\t# MoveL2D_reg_reg" %}
13849
13850 ins_encode %{
13851 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
13852 %}
13853
13854 ins_pipe(fp_l2d);
13855
13856 %}
13857
13858 // ============================================================================
13859 // clearing of an array
13860
13861 instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
13862 %{
13863 match(Set dummy (ClearArray cnt base));
13864 effect(USE_KILL cnt, USE_KILL base);
13865
13866 ins_cost(4 * INSN_COST);
13867 format %{ "ClearArray $cnt, $base" %}
13868
13869 ins_encode %{
13870 __ zero_words($base$$Register, $cnt$$Register);
13871 %}
13872
13873 ins_pipe(pipe_class_memory);
13874 %}
13875
13876 instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, iRegL_R11 tmp, Universe dummy, rFlagsReg cr)
13877 %{
13878 match(Set dummy (ClearArray cnt base));
13879 effect(USE_KILL base, TEMP tmp);
13880
13881 ins_cost(4 * INSN_COST);
13882 format %{ "ClearArray $cnt, $base" %}
13883
13884 ins_encode %{
13885 __ zero_words($base$$Register, (u_int64_t)$cnt$$constant);
13886 %}
13887
13888 ins_pipe(pipe_class_memory);
13889 %}
13890
13891 // ============================================================================
13892 // Overflow Math Instructions
13893
13894 instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
13895 %{
13896 match(Set cr (OverflowAddI op1 op2));
13897
13898 format %{ "cmnw $op1, $op2\t# overflow check int" %}
13899 ins_cost(INSN_COST);
13900 ins_encode %{
13901 __ cmnw($op1$$Register, $op2$$Register);
13902 %}
13903
13904 ins_pipe(icmp_reg_reg);
13905 %}
13906
13907 instruct overflowAddI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
13908 %{
13909 match(Set cr (OverflowAddI op1 op2));
13910
13911 format %{ "cmnw $op1, $op2\t# overflow check int" %}
13912 ins_cost(INSN_COST);
13913 ins_encode %{
13914 __ cmnw($op1$$Register, $op2$$constant);
13915 %}
13916
13917 ins_pipe(icmp_reg_imm);
13918 %}
13919
13920 instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
13921 %{
13922 match(Set cr (OverflowAddL op1 op2));
13923
13924 format %{ "cmn $op1, $op2\t# overflow check long" %}
13925 ins_cost(INSN_COST);
13926 ins_encode %{
13927 __ cmn($op1$$Register, $op2$$Register);
13928 %}
13929
13930 ins_pipe(icmp_reg_reg);
13931 %}
13932
13933 instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
13934 %{
13935 match(Set cr (OverflowAddL op1 op2));
13936
13937 format %{ "cmn $op1, $op2\t# overflow check long" %}
13938 ins_cost(INSN_COST);
13939 ins_encode %{
13940 __ cmn($op1$$Register, $op2$$constant);
13941 %}
13942
13943 ins_pipe(icmp_reg_imm);
13944 %}
13945
13946 instruct overflowSubI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
13947 %{
13948 match(Set cr (OverflowSubI op1 op2));
13949
13950 format %{ "cmpw $op1, $op2\t# overflow check int" %}
13951 ins_cost(INSN_COST);
13952 ins_encode %{
13953 __ cmpw($op1$$Register, $op2$$Register);
13954 %}
13955
13956 ins_pipe(icmp_reg_reg);
13957 %}
13958
13959 instruct overflowSubI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
13960 %{
13961 match(Set cr (OverflowSubI op1 op2));
13962
13963 format %{ "cmpw $op1, $op2\t# overflow check int" %}
13964 ins_cost(INSN_COST);
13965 ins_encode %{
13966 __ cmpw($op1$$Register, $op2$$constant);
13967 %}
13968
13969 ins_pipe(icmp_reg_imm);
13970 %}
13971
13972 instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
13973 %{
13974 match(Set cr (OverflowSubL op1 op2));
13975
13976 format %{ "cmp $op1, $op2\t# overflow check long" %}
13977 ins_cost(INSN_COST);
13978 ins_encode %{
13979 __ cmp($op1$$Register, $op2$$Register);
13980 %}
13981
13982 ins_pipe(icmp_reg_reg);
13983 %}
13984
13985 instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
13986 %{
13987 match(Set cr (OverflowSubL op1 op2));
13988
13989 format %{ "cmp $op1, $op2\t# overflow check long" %}
13990 ins_cost(INSN_COST);
13991 ins_encode %{
13992 __ cmp($op1$$Register, $op2$$constant);
13993 %}
13994
13995 ins_pipe(icmp_reg_imm);
13996 %}
13997
13998 instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegIorL2I op1)
13999 %{
14000 match(Set cr (OverflowSubI zero op1));
14001
14002 format %{ "cmpw zr, $op1\t# overflow check int" %}
14003 ins_cost(INSN_COST);
14004 ins_encode %{
14005 __ cmpw(zr, $op1$$Register);
14006 %}
14007
14008 ins_pipe(icmp_reg_imm);
14009 %}
14010
14011 instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op1)
14012 %{
14013 match(Set cr (OverflowSubL zero op1));
14014
14015 format %{ "cmp zr, $op1\t# overflow check long" %}
14016 ins_cost(INSN_COST);
14017 ins_encode %{
14018 __ cmp(zr, $op1$$Register);
14019 %}
14020
14021 ins_pipe(icmp_reg_imm);
14022 %}
14023
14024 instruct overflowMulI_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
14025 %{
14026 match(Set cr (OverflowMulI op1 op2));
14027
14028 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
14029 "cmp rscratch1, rscratch1, sxtw\n\t"
14030 "movw rscratch1, #0x80000000\n\t"
14031 "cselw rscratch1, rscratch1, zr, NE\n\t"
14032 "cmpw rscratch1, #1" %}
14033 ins_cost(5 * INSN_COST);
14034 ins_encode %{
14035 __ smull(rscratch1, $op1$$Register, $op2$$Register);
14036 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
14037 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
14038 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
14039 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
14040 %}
14041
14042 ins_pipe(pipe_slow);
14043 %}
14044
14045 instruct overflowMulI_reg_branch(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, label labl, rFlagsReg cr)
14046 %{
14047 match(If cmp (OverflowMulI op1 op2));
14048 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
14049 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
14050 effect(USE labl, KILL cr);
14051
14052 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
14053 "cmp rscratch1, rscratch1, sxtw\n\t"
14054 "b$cmp $labl" %}
14055 ins_cost(3 * INSN_COST); // Branch is rare so treat as INSN_COST
14056 ins_encode %{
14057 Label* L = $labl$$label;
14058 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14059 __ smull(rscratch1, $op1$$Register, $op2$$Register);
14060 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
14061 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
14062 %}
14063
14064 ins_pipe(pipe_serial);
14065 %}
14066
14067 instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
14068 %{
14069 match(Set cr (OverflowMulL op1 op2));
14070
14071 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
14072 "smulh rscratch2, $op1, $op2\n\t"
14073 "cmp rscratch2, rscratch1, ASR #31\n\t"
14074 "movw rscratch1, #0x80000000\n\t"
14075 "cselw rscratch1, rscratch1, zr, NE\n\t"
14076 "cmpw rscratch1, #1" %}
14077 ins_cost(6 * INSN_COST);
14078 ins_encode %{
14079 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
14080 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
14081 __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
14082 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
14083 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
14084 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
14085 %}
14086
14087 ins_pipe(pipe_slow);
14088 %}
14089
14090 instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rFlagsReg cr)
14091 %{
14092 match(If cmp (OverflowMulL op1 op2));
14093 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
14094 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
14095 effect(USE labl, KILL cr);
14096
14097 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
14098 "smulh rscratch2, $op1, $op2\n\t"
14099 "cmp rscratch2, rscratch1, ASR #31\n\t"
14100 "b$cmp $labl" %}
14101 ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
14102 ins_encode %{
14103 Label* L = $labl$$label;
14104 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14105 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
14106 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
14107 __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
14108 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
14109 %}
14110
14111 ins_pipe(pipe_serial);
14112 %}
14113
14114 // ============================================================================
14115 // Compare Instructions
14116
14117 instruct compI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
14118 %{
14119 match(Set cr (CmpI op1 op2));
14120
14121 effect(DEF cr, USE op1, USE op2);
14122
14123 ins_cost(INSN_COST);
14124 format %{ "cmpw $op1, $op2" %}
14125
14126 ins_encode(aarch64_enc_cmpw(op1, op2));
14127
14128 ins_pipe(icmp_reg_reg);
14129 %}
14130
14131 instruct compI_reg_immI0(rFlagsReg cr, iRegI op1, immI0 zero)
14132 %{
14133 match(Set cr (CmpI op1 zero));
14134
14135 effect(DEF cr, USE op1);
14136
14137 ins_cost(INSN_COST);
14138 format %{ "cmpw $op1, 0" %}
14139
14140 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
14141
14142 ins_pipe(icmp_reg_imm);
14143 %}
14144
14145 instruct compI_reg_immIAddSub(rFlagsReg cr, iRegI op1, immIAddSub op2)
14146 %{
14147 match(Set cr (CmpI op1 op2));
14148
14149 effect(DEF cr, USE op1);
14150
14151 ins_cost(INSN_COST);
14152 format %{ "cmpw $op1, $op2" %}
14153
14154 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
14155
14156 ins_pipe(icmp_reg_imm);
14157 %}
14158
14159 instruct compI_reg_immI(rFlagsReg cr, iRegI op1, immI op2)
14160 %{
14161 match(Set cr (CmpI op1 op2));
14162
14163 effect(DEF cr, USE op1);
14164
14165 ins_cost(INSN_COST * 2);
14166 format %{ "cmpw $op1, $op2" %}
14167
14168 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
14169
14170 ins_pipe(icmp_reg_imm);
14171 %}
14172
14173 // Unsigned compare Instructions; really, same as signed compare
14174 // except it should only be used to feed an If or a CMovI which takes a
14175 // cmpOpU.
14176
14177 instruct compU_reg_reg(rFlagsRegU cr, iRegI op1, iRegI op2)
14178 %{
14179 match(Set cr (CmpU op1 op2));
14180
14181 effect(DEF cr, USE op1, USE op2);
14182
14183 ins_cost(INSN_COST);
14184 format %{ "cmpw $op1, $op2\t# unsigned" %}
14185
14186 ins_encode(aarch64_enc_cmpw(op1, op2));
14187
14188 ins_pipe(icmp_reg_reg);
14189 %}
14190
14191 instruct compU_reg_immI0(rFlagsRegU cr, iRegI op1, immI0 zero)
14192 %{
14193 match(Set cr (CmpU op1 zero));
14194
14195 effect(DEF cr, USE op1);
14196
14197 ins_cost(INSN_COST);
14198 format %{ "cmpw $op1, #0\t# unsigned" %}
14199
14200 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
14201
14202 ins_pipe(icmp_reg_imm);
14203 %}
14204
14205 instruct compU_reg_immIAddSub(rFlagsRegU cr, iRegI op1, immIAddSub op2)
14206 %{
14207 match(Set cr (CmpU op1 op2));
14208
14209 effect(DEF cr, USE op1);
14210
14211 ins_cost(INSN_COST);
14212 format %{ "cmpw $op1, $op2\t# unsigned" %}
14213
14214 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
14215
14216 ins_pipe(icmp_reg_imm);
14217 %}
14218
14219 instruct compU_reg_immI(rFlagsRegU cr, iRegI op1, immI op2)
14220 %{
14221 match(Set cr (CmpU op1 op2));
14222
14223 effect(DEF cr, USE op1);
14224
14225 ins_cost(INSN_COST * 2);
14226 format %{ "cmpw $op1, $op2\t# unsigned" %}
14227
14228 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
14229
14230 ins_pipe(icmp_reg_imm);
14231 %}
14232
14233 instruct compL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
14234 %{
14235 match(Set cr (CmpL op1 op2));
14236
14237 effect(DEF cr, USE op1, USE op2);
14238
14239 ins_cost(INSN_COST);
14240 format %{ "cmp $op1, $op2" %}
14241
14242 ins_encode(aarch64_enc_cmp(op1, op2));
14243
14244 ins_pipe(icmp_reg_reg);
14245 %}
14246
14247 instruct compL_reg_immI0(rFlagsReg cr, iRegL op1, immI0 zero)
14248 %{
14249 match(Set cr (CmpL op1 zero));
14250
14251 effect(DEF cr, USE op1);
14252
14253 ins_cost(INSN_COST);
14254 format %{ "tst $op1" %}
14255
14256 ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
14257
14258 ins_pipe(icmp_reg_imm);
14259 %}
14260
14261 instruct compL_reg_immLAddSub(rFlagsReg cr, iRegL op1, immLAddSub op2)
14262 %{
14263 match(Set cr (CmpL op1 op2));
14264
14265 effect(DEF cr, USE op1);
14266
14267 ins_cost(INSN_COST);
14268 format %{ "cmp $op1, $op2" %}
14269
14270 ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
14271
14272 ins_pipe(icmp_reg_imm);
14273 %}
14274
14275 instruct compL_reg_immL(rFlagsReg cr, iRegL op1, immL op2)
14276 %{
14277 match(Set cr (CmpL op1 op2));
14278
14279 effect(DEF cr, USE op1);
14280
14281 ins_cost(INSN_COST * 2);
14282 format %{ "cmp $op1, $op2" %}
14283
14284 ins_encode(aarch64_enc_cmp_imm(op1, op2));
14285
14286 ins_pipe(icmp_reg_imm);
14287 %}
14288
14289 instruct compP_reg_reg(rFlagsRegU cr, iRegP op1, iRegP op2)
14290 %{
14291 match(Set cr (CmpP op1 op2));
14292
14293 effect(DEF cr, USE op1, USE op2);
14294
14295 ins_cost(INSN_COST);
14296 format %{ "cmp $op1, $op2\t // ptr" %}
14297
14298 ins_encode(aarch64_enc_cmpp(op1, op2));
14299
14300 ins_pipe(icmp_reg_reg);
14301 %}
14302
14303 instruct compN_reg_reg(rFlagsRegU cr, iRegN op1, iRegN op2)
14304 %{
14305 match(Set cr (CmpN op1 op2));
14306
14307 effect(DEF cr, USE op1, USE op2);
14308
14309 ins_cost(INSN_COST);
14310 format %{ "cmp $op1, $op2\t // compressed ptr" %}
14311
14312 ins_encode(aarch64_enc_cmpn(op1, op2));
14313
14314 ins_pipe(icmp_reg_reg);
14315 %}
14316
14317 instruct testP_reg(rFlagsRegU cr, iRegP op1, immP0 zero)
14318 %{
14319 match(Set cr (CmpP op1 zero));
14320
14321 effect(DEF cr, USE op1, USE zero);
14322
14323 ins_cost(INSN_COST);
14324 format %{ "cmp $op1, 0\t // ptr" %}
14325
14326 ins_encode(aarch64_enc_testp(op1));
14327
14328 ins_pipe(icmp_reg_imm);
14329 %}
14330
14331 instruct testN_reg(rFlagsRegU cr, iRegN op1, immN0 zero)
14332 %{
14333 match(Set cr (CmpN op1 zero));
14334
14335 effect(DEF cr, USE op1, USE zero);
14336
14337 ins_cost(INSN_COST);
14338 format %{ "cmp $op1, 0\t // compressed ptr" %}
14339
14340 ins_encode(aarch64_enc_testn(op1));
14341
14342 ins_pipe(icmp_reg_imm);
14343 %}
14344
14345 // FP comparisons
14346 //
14347 // n.b. CmpF/CmpD set a normal flags reg which then gets compared
14348 // using normal cmpOp. See declaration of rFlagsReg for details.
14349
14350 instruct compF_reg_reg(rFlagsReg cr, vRegF src1, vRegF src2)
14351 %{
14352 match(Set cr (CmpF src1 src2));
14353
14354 ins_cost(3 * INSN_COST);
14355 format %{ "fcmps $src1, $src2" %}
14356
14357 ins_encode %{
14358 __ fcmps(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
14359 %}
14360
14361 ins_pipe(pipe_class_compare);
14362 %}
14363
14364 instruct compF_reg_zero(rFlagsReg cr, vRegF src1, immF0 src2)
14365 %{
14366 match(Set cr (CmpF src1 src2));
14367
14368 ins_cost(3 * INSN_COST);
14369 format %{ "fcmps $src1, 0.0" %}
14370
14371 ins_encode %{
14372 __ fcmps(as_FloatRegister($src1$$reg), 0.0D);
14373 %}
14374
14375 ins_pipe(pipe_class_compare);
14376 %}
14377 // FROM HERE
14378
14379 instruct compD_reg_reg(rFlagsReg cr, vRegD src1, vRegD src2)
14380 %{
14381 match(Set cr (CmpD src1 src2));
14382
14383 ins_cost(3 * INSN_COST);
14384 format %{ "fcmpd $src1, $src2" %}
14385
14386 ins_encode %{
14387 __ fcmpd(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
14388 %}
14389
14390 ins_pipe(pipe_class_compare);
14391 %}
14392
14393 instruct compD_reg_zero(rFlagsReg cr, vRegD src1, immD0 src2)
14394 %{
14395 match(Set cr (CmpD src1 src2));
14396
14397 ins_cost(3 * INSN_COST);
14398 format %{ "fcmpd $src1, 0.0" %}
14399
14400 ins_encode %{
14401 __ fcmpd(as_FloatRegister($src1$$reg), 0.0D);
14402 %}
14403
14404 ins_pipe(pipe_class_compare);
14405 %}
14406
14407 instruct compF3_reg_reg(iRegINoSp dst, vRegF src1, vRegF src2, rFlagsReg cr)
14408 %{
14409 match(Set dst (CmpF3 src1 src2));
14410 effect(KILL cr);
14411
14412 ins_cost(5 * INSN_COST);
14413 format %{ "fcmps $src1, $src2\n\t"
14414 "csinvw($dst, zr, zr, eq\n\t"
14415 "csnegw($dst, $dst, $dst, lt)"
14416 %}
14417
14418 ins_encode %{
14419 Label done;
14420 FloatRegister s1 = as_FloatRegister($src1$$reg);
14421 FloatRegister s2 = as_FloatRegister($src2$$reg);
14422 Register d = as_Register($dst$$reg);
14423 __ fcmps(s1, s2);
14424 // installs 0 if EQ else -1
14425 __ csinvw(d, zr, zr, Assembler::EQ);
14426 // keeps -1 if less or unordered else installs 1
14427 __ csnegw(d, d, d, Assembler::LT);
14428 __ bind(done);
14429 %}
14430
14431 ins_pipe(pipe_class_default);
14432
14433 %}
14434
14435 instruct compD3_reg_reg(iRegINoSp dst, vRegD src1, vRegD src2, rFlagsReg cr)
14436 %{
14437 match(Set dst (CmpD3 src1 src2));
14438 effect(KILL cr);
14439
14440 ins_cost(5 * INSN_COST);
14441 format %{ "fcmpd $src1, $src2\n\t"
14442 "csinvw($dst, zr, zr, eq\n\t"
14443 "csnegw($dst, $dst, $dst, lt)"
14444 %}
14445
14446 ins_encode %{
14447 Label done;
14448 FloatRegister s1 = as_FloatRegister($src1$$reg);
14449 FloatRegister s2 = as_FloatRegister($src2$$reg);
14450 Register d = as_Register($dst$$reg);
14451 __ fcmpd(s1, s2);
14452 // installs 0 if EQ else -1
14453 __ csinvw(d, zr, zr, Assembler::EQ);
14454 // keeps -1 if less or unordered else installs 1
14455 __ csnegw(d, d, d, Assembler::LT);
14456 __ bind(done);
14457 %}
14458 ins_pipe(pipe_class_default);
14459
14460 %}
14461
14462 instruct compF3_reg_immF0(iRegINoSp dst, vRegF src1, immF0 zero, rFlagsReg cr)
14463 %{
14464 match(Set dst (CmpF3 src1 zero));
14465 effect(KILL cr);
14466
14467 ins_cost(5 * INSN_COST);
14468 format %{ "fcmps $src1, 0.0\n\t"
14469 "csinvw($dst, zr, zr, eq\n\t"
14470 "csnegw($dst, $dst, $dst, lt)"
14471 %}
14472
14473 ins_encode %{
14474 Label done;
14475 FloatRegister s1 = as_FloatRegister($src1$$reg);
14476 Register d = as_Register($dst$$reg);
14477 __ fcmps(s1, 0.0D);
14478 // installs 0 if EQ else -1
14479 __ csinvw(d, zr, zr, Assembler::EQ);
14480 // keeps -1 if less or unordered else installs 1
14481 __ csnegw(d, d, d, Assembler::LT);
14482 __ bind(done);
14483 %}
14484
14485 ins_pipe(pipe_class_default);
14486
14487 %}
14488
14489 instruct compD3_reg_immD0(iRegINoSp dst, vRegD src1, immD0 zero, rFlagsReg cr)
14490 %{
14491 match(Set dst (CmpD3 src1 zero));
14492 effect(KILL cr);
14493
14494 ins_cost(5 * INSN_COST);
14495 format %{ "fcmpd $src1, 0.0\n\t"
14496 "csinvw($dst, zr, zr, eq\n\t"
14497 "csnegw($dst, $dst, $dst, lt)"
14498 %}
14499
14500 ins_encode %{
14501 Label done;
14502 FloatRegister s1 = as_FloatRegister($src1$$reg);
14503 Register d = as_Register($dst$$reg);
14504 __ fcmpd(s1, 0.0D);
14505 // installs 0 if EQ else -1
14506 __ csinvw(d, zr, zr, Assembler::EQ);
14507 // keeps -1 if less or unordered else installs 1
14508 __ csnegw(d, d, d, Assembler::LT);
14509 __ bind(done);
14510 %}
14511 ins_pipe(pipe_class_default);
14512
14513 %}
14514
14515 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
14516 %{
14517 match(Set dst (CmpLTMask p q));
14518 effect(KILL cr);
14519
14520 ins_cost(3 * INSN_COST);
14521
14522 format %{ "cmpw $p, $q\t# cmpLTMask\n\t"
14523 "csetw $dst, lt\n\t"
14524 "subw $dst, zr, $dst"
14525 %}
14526
14527 ins_encode %{
14528 __ cmpw(as_Register($p$$reg), as_Register($q$$reg));
14529 __ csetw(as_Register($dst$$reg), Assembler::LT);
14530 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
14531 %}
14532
14533 ins_pipe(ialu_reg_reg);
14534 %}
14535
14536 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
14537 %{
14538 match(Set dst (CmpLTMask src zero));
14539 effect(KILL cr);
14540
14541 ins_cost(INSN_COST);
14542
14543 format %{ "asrw $dst, $src, #31\t# cmpLTMask0" %}
14544
14545 ins_encode %{
14546 __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
14547 %}
14548
14549 ins_pipe(ialu_reg_shift);
14550 %}
14551
14552 // ============================================================================
14553 // Max and Min
14554
14555 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14556 %{
14557 match(Set dst (MinI src1 src2));
14558
14559 effect(DEF dst, USE src1, USE src2, KILL cr);
14560 size(8);
14561
14562 ins_cost(INSN_COST * 3);
14563 format %{
14564 "cmpw $src1 $src2\t signed int\n\t"
14565 "cselw $dst, $src1, $src2 lt\t"
14566 %}
14567
14568 ins_encode %{
14569 __ cmpw(as_Register($src1$$reg),
14570 as_Register($src2$$reg));
14571 __ cselw(as_Register($dst$$reg),
14572 as_Register($src1$$reg),
14573 as_Register($src2$$reg),
14574 Assembler::LT);
14575 %}
14576
14577 ins_pipe(ialu_reg_reg);
14578 %}
14579 // FROM HERE
14580
14581 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14582 %{
14583 match(Set dst (MaxI src1 src2));
14584
14585 effect(DEF dst, USE src1, USE src2, KILL cr);
14586 size(8);
14587
14588 ins_cost(INSN_COST * 3);
14589 format %{
14590 "cmpw $src1 $src2\t signed int\n\t"
14591 "cselw $dst, $src1, $src2 gt\t"
14592 %}
14593
14594 ins_encode %{
14595 __ cmpw(as_Register($src1$$reg),
14596 as_Register($src2$$reg));
14597 __ cselw(as_Register($dst$$reg),
14598 as_Register($src1$$reg),
14599 as_Register($src2$$reg),
14600 Assembler::GT);
14601 %}
14602
14603 ins_pipe(ialu_reg_reg);
14604 %}
14605
14606 // ============================================================================
14607 // Branch Instructions
14608
14609 // Direct Branch.
14610 instruct branch(label lbl)
14611 %{
14612 match(Goto);
14613
14614 effect(USE lbl);
14615
14616 ins_cost(BRANCH_COST);
14617 format %{ "b $lbl" %}
14618
14619 ins_encode(aarch64_enc_b(lbl));
14620
14621 ins_pipe(pipe_branch);
14622 %}
14623
14624 // Conditional Near Branch
14625 instruct branchCon(cmpOp cmp, rFlagsReg cr, label lbl)
14626 %{
14627 // Same match rule as `branchConFar'.
14628 match(If cmp cr);
14629
14630 effect(USE lbl);
14631
14632 ins_cost(BRANCH_COST);
14633 // If set to 1 this indicates that the current instruction is a
14634 // short variant of a long branch. This avoids using this
14635 // instruction in first-pass matching. It will then only be used in
14636 // the `Shorten_branches' pass.
14637 // ins_short_branch(1);
14638 format %{ "b$cmp $lbl" %}
14639
14640 ins_encode(aarch64_enc_br_con(cmp, lbl));
14641
14642 ins_pipe(pipe_branch_cond);
14643 %}
14644
14645 // Conditional Near Branch Unsigned
14646 instruct branchConU(cmpOpU cmp, rFlagsRegU cr, label lbl)
14647 %{
14648 // Same match rule as `branchConFar'.
14649 match(If cmp cr);
14650
14651 effect(USE lbl);
14652
14653 ins_cost(BRANCH_COST);
14654 // If set to 1 this indicates that the current instruction is a
14655 // short variant of a long branch. This avoids using this
14656 // instruction in first-pass matching. It will then only be used in
14657 // the `Shorten_branches' pass.
14658 // ins_short_branch(1);
14659 format %{ "b$cmp $lbl\t# unsigned" %}
14660
14661 ins_encode(aarch64_enc_br_conU(cmp, lbl));
14662
14663 ins_pipe(pipe_branch_cond);
14664 %}
14665
14666 // Make use of CBZ and CBNZ. These instructions, as well as being
14667 // shorter than (cmp; branch), have the additional benefit of not
14668 // killing the flags.
14669
14670 instruct cmpI_imm0_branch(cmpOpEqNe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
14671 match(If cmp (CmpI op1 op2));
14672 effect(USE labl);
14673
14674 ins_cost(BRANCH_COST);
14675 format %{ "cbw$cmp $op1, $labl" %}
14676 ins_encode %{
14677 Label* L = $labl$$label;
14678 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14679 if (cond == Assembler::EQ)
14680 __ cbzw($op1$$Register, *L);
14681 else
14682 __ cbnzw($op1$$Register, *L);
14683 %}
14684 ins_pipe(pipe_cmp_branch);
14685 %}
14686
14687 instruct cmpL_imm0_branch(cmpOpEqNe cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
14688 match(If cmp (CmpL op1 op2));
14689 effect(USE labl);
14690
14691 ins_cost(BRANCH_COST);
14692 format %{ "cb$cmp $op1, $labl" %}
14693 ins_encode %{
14694 Label* L = $labl$$label;
14695 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14696 if (cond == Assembler::EQ)
14697 __ cbz($op1$$Register, *L);
14698 else
14699 __ cbnz($op1$$Register, *L);
14700 %}
14701 ins_pipe(pipe_cmp_branch);
14702 %}
14703
14704 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 op2, label labl, rFlagsReg cr) %{
14705 match(If cmp (CmpP op1 op2));
14706 effect(USE labl);
14707
14708 ins_cost(BRANCH_COST);
14709 format %{ "cb$cmp $op1, $labl" %}
14710 ins_encode %{
14711 Label* L = $labl$$label;
14712 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14713 if (cond == Assembler::EQ)
14714 __ cbz($op1$$Register, *L);
14715 else
14716 __ cbnz($op1$$Register, *L);
14717 %}
14718 ins_pipe(pipe_cmp_branch);
14719 %}
14720
14721 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 op2, label labl, rFlagsReg cr) %{
14722 match(If cmp (CmpN op1 op2));
14723 effect(USE labl);
14724
14725 ins_cost(BRANCH_COST);
14726 format %{ "cbw$cmp $op1, $labl" %}
14727 ins_encode %{
14728 Label* L = $labl$$label;
14729 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14730 if (cond == Assembler::EQ)
14731 __ cbzw($op1$$Register, *L);
14732 else
14733 __ cbnzw($op1$$Register, *L);
14734 %}
14735 ins_pipe(pipe_cmp_branch);
14736 %}
14737
14738 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN oop, immP0 zero, label labl, rFlagsReg cr) %{
14739 match(If cmp (CmpP (DecodeN oop) zero));
14740 effect(USE labl);
14741
14742 ins_cost(BRANCH_COST);
14743 format %{ "cb$cmp $oop, $labl" %}
14744 ins_encode %{
14745 Label* L = $labl$$label;
14746 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14747 if (cond == Assembler::EQ)
14748 __ cbzw($oop$$Register, *L);
14749 else
14750 __ cbnzw($oop$$Register, *L);
14751 %}
14752 ins_pipe(pipe_cmp_branch);
14753 %}
14754
14755 instruct cmpUI_imm0_branch(cmpOpUEqNeLtGe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsRegU cr) %{
14756 match(If cmp (CmpU op1 op2));
14757 effect(USE labl);
14758
14759 ins_cost(BRANCH_COST);
14760 format %{ "cbw$cmp $op1, $labl" %}
14761 ins_encode %{
14762 Label* L = $labl$$label;
14763 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14764 if (cond == Assembler::EQ || cond == Assembler::LS)
14765 __ cbzw($op1$$Register, *L);
14766 else
14767 __ cbnzw($op1$$Register, *L);
14768 %}
14769 ins_pipe(pipe_cmp_branch);
14770 %}
14771
14772 instruct cmpUL_imm0_branch(cmpOpUEqNeLtGe cmp, iRegL op1, immL0 op2, label labl, rFlagsRegU cr) %{
14773 match(If cmp (CmpU op1 op2));
14774 effect(USE labl);
14775
14776 ins_cost(BRANCH_COST);
14777 format %{ "cb$cmp $op1, $labl" %}
14778 ins_encode %{
14779 Label* L = $labl$$label;
14780 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14781 if (cond == Assembler::EQ || cond == Assembler::LS)
14782 __ cbz($op1$$Register, *L);
14783 else
14784 __ cbnz($op1$$Register, *L);
14785 %}
14786 ins_pipe(pipe_cmp_branch);
14787 %}
14788
14789 // Test bit and Branch
14790
14791 // Patterns for short (< 32KiB) variants
14792 instruct cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
14793 match(If cmp (CmpL op1 op2));
14794 effect(USE labl);
14795
14796 ins_cost(BRANCH_COST);
14797 format %{ "cb$cmp $op1, $labl # long" %}
14798 ins_encode %{
14799 Label* L = $labl$$label;
14800 Assembler::Condition cond =
14801 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
14802 __ tbr(cond, $op1$$Register, 63, *L);
14803 %}
14804 ins_pipe(pipe_cmp_branch);
14805 ins_short_branch(1);
14806 %}
14807
14808 instruct cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
14809 match(If cmp (CmpI op1 op2));
14810 effect(USE labl);
14811
14812 ins_cost(BRANCH_COST);
14813 format %{ "cb$cmp $op1, $labl # int" %}
14814 ins_encode %{
14815 Label* L = $labl$$label;
14816 Assembler::Condition cond =
14817 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
14818 __ tbr(cond, $op1$$Register, 31, *L);
14819 %}
14820 ins_pipe(pipe_cmp_branch);
14821 ins_short_branch(1);
14822 %}
14823
14824 instruct cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
14825 match(If cmp (CmpL (AndL op1 op2) op3));
14826 predicate(is_power_of_2(n->in(2)->in(1)->in(2)->get_long()));
14827 effect(USE labl);
14828
14829 ins_cost(BRANCH_COST);
14830 format %{ "tb$cmp $op1, $op2, $labl" %}
14831 ins_encode %{
14832 Label* L = $labl$$label;
14833 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14834 int bit = exact_log2($op2$$constant);
14835 __ tbr(cond, $op1$$Register, bit, *L);
14836 %}
14837 ins_pipe(pipe_cmp_branch);
14838 ins_short_branch(1);
14839 %}
14840
14841 instruct cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
14842 match(If cmp (CmpI (AndI op1 op2) op3));
14843 predicate(is_power_of_2(n->in(2)->in(1)->in(2)->get_int()));
14844 effect(USE labl);
14845
14846 ins_cost(BRANCH_COST);
14847 format %{ "tb$cmp $op1, $op2, $labl" %}
14848 ins_encode %{
14849 Label* L = $labl$$label;
14850 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14851 int bit = exact_log2($op2$$constant);
14852 __ tbr(cond, $op1$$Register, bit, *L);
14853 %}
14854 ins_pipe(pipe_cmp_branch);
14855 ins_short_branch(1);
14856 %}
14857
14858 // And far variants
14859 instruct far_cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
14860 match(If cmp (CmpL op1 op2));
14861 effect(USE labl);
14862
14863 ins_cost(BRANCH_COST);
14864 format %{ "cb$cmp $op1, $labl # long" %}
14865 ins_encode %{
14866 Label* L = $labl$$label;
14867 Assembler::Condition cond =
14868 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
14869 __ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
14870 %}
14871 ins_pipe(pipe_cmp_branch);
14872 %}
14873
14874 instruct far_cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
14875 match(If cmp (CmpI op1 op2));
14876 effect(USE labl);
14877
14878 ins_cost(BRANCH_COST);
14879 format %{ "cb$cmp $op1, $labl # int" %}
14880 ins_encode %{
14881 Label* L = $labl$$label;
14882 Assembler::Condition cond =
14883 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
14884 __ tbr(cond, $op1$$Register, 31, *L, /*far*/true);
14885 %}
14886 ins_pipe(pipe_cmp_branch);
14887 %}
14888
14889 instruct far_cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
14890 match(If cmp (CmpL (AndL op1 op2) op3));
14891 predicate(is_power_of_2(n->in(2)->in(1)->in(2)->get_long()));
14892 effect(USE labl);
14893
14894 ins_cost(BRANCH_COST);
14895 format %{ "tb$cmp $op1, $op2, $labl" %}
14896 ins_encode %{
14897 Label* L = $labl$$label;
14898 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14899 int bit = exact_log2($op2$$constant);
14900 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
14901 %}
14902 ins_pipe(pipe_cmp_branch);
14903 %}
14904
14905 instruct far_cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
14906 match(If cmp (CmpI (AndI op1 op2) op3));
14907 predicate(is_power_of_2(n->in(2)->in(1)->in(2)->get_int()));
14908 effect(USE labl);
14909
14910 ins_cost(BRANCH_COST);
14911 format %{ "tb$cmp $op1, $op2, $labl" %}
14912 ins_encode %{
14913 Label* L = $labl$$label;
14914 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14915 int bit = exact_log2($op2$$constant);
14916 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
14917 %}
14918 ins_pipe(pipe_cmp_branch);
14919 %}
14920
14921 // Test bits
14922
14923 instruct cmpL_and(cmpOp cmp, iRegL op1, immL op2, immL0 op3, rFlagsReg cr) %{
14924 match(Set cr (CmpL (AndL op1 op2) op3));
14925 predicate(Assembler::operand_valid_for_logical_immediate
14926 (/*is_32*/false, n->in(1)->in(2)->get_long()));
14927
14928 ins_cost(INSN_COST);
14929 format %{ "tst $op1, $op2 # long" %}
14930 ins_encode %{
14931 __ tst($op1$$Register, $op2$$constant);
14932 %}
14933 ins_pipe(ialu_reg_reg);
14934 %}
14935
14936 instruct cmpI_and(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, rFlagsReg cr) %{
14937 match(Set cr (CmpI (AndI op1 op2) op3));
14938 predicate(Assembler::operand_valid_for_logical_immediate
14939 (/*is_32*/true, n->in(1)->in(2)->get_int()));
14940
14941 ins_cost(INSN_COST);
14942 format %{ "tst $op1, $op2 # int" %}
14943 ins_encode %{
14944 __ tstw($op1$$Register, $op2$$constant);
14945 %}
14946 ins_pipe(ialu_reg_reg);
14947 %}
14948
14949 instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
14950 match(Set cr (CmpL (AndL op1 op2) op3));
14951
14952 ins_cost(INSN_COST);
14953 format %{ "tst $op1, $op2 # long" %}
14954 ins_encode %{
14955 __ tst($op1$$Register, $op2$$Register);
14956 %}
14957 ins_pipe(ialu_reg_reg);
14958 %}
14959
14960 instruct cmpI_and_reg(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, immI0 op3, rFlagsReg cr) %{
14961 match(Set cr (CmpI (AndI op1 op2) op3));
14962
14963 ins_cost(INSN_COST);
14964 format %{ "tstw $op1, $op2 # int" %}
14965 ins_encode %{
14966 __ tstw($op1$$Register, $op2$$Register);
14967 %}
14968 ins_pipe(ialu_reg_reg);
14969 %}
14970
14971
14972 // Conditional Far Branch
14973 // Conditional Far Branch Unsigned
14974 // TODO: fixme
14975
14976 // counted loop end branch near
14977 instruct branchLoopEnd(cmpOp cmp, rFlagsReg cr, label lbl)
14978 %{
14979 match(CountedLoopEnd cmp cr);
14980
14981 effect(USE lbl);
14982
14983 ins_cost(BRANCH_COST);
14984 // short variant.
14985 // ins_short_branch(1);
14986 format %{ "b$cmp $lbl \t// counted loop end" %}
14987
14988 ins_encode(aarch64_enc_br_con(cmp, lbl));
14989
14990 ins_pipe(pipe_branch);
14991 %}
14992
14993 // counted loop end branch near Unsigned
14994 instruct branchLoopEndU(cmpOpU cmp, rFlagsRegU cr, label lbl)
14995 %{
14996 match(CountedLoopEnd cmp cr);
14997
14998 effect(USE lbl);
14999
15000 ins_cost(BRANCH_COST);
15001 // short variant.
15002 // ins_short_branch(1);
15003 format %{ "b$cmp $lbl \t// counted loop end unsigned" %}
15004
15005 ins_encode(aarch64_enc_br_conU(cmp, lbl));
15006
15007 ins_pipe(pipe_branch);
15008 %}
15009
15010 // counted loop end branch far
15011 // counted loop end branch far unsigned
15012 // TODO: fixme
15013
15014 // ============================================================================
15015 // inlined locking and unlocking
15016
15017 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
15018 %{
15019 match(Set cr (FastLock object box));
15020 effect(TEMP tmp, TEMP tmp2);
15021
15022 // TODO
15023 // identify correct cost
15024 ins_cost(5 * INSN_COST);
15025 format %{ "fastlock $object,$box\t! kills $tmp,$tmp2" %}
15026
15027 ins_encode(aarch64_enc_fast_lock(object, box, tmp, tmp2));
15028
15029 ins_pipe(pipe_serial);
15030 %}
15031
15032 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
15033 %{
15034 match(Set cr (FastUnlock object box));
15035 effect(TEMP tmp, TEMP tmp2);
15036
15037 ins_cost(5 * INSN_COST);
15038 format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2" %}
15039
15040 ins_encode(aarch64_enc_fast_unlock(object, box, tmp, tmp2));
15041
15042 ins_pipe(pipe_serial);
15043 %}
15044
15045
15046 // ============================================================================
15047 // Safepoint Instructions
15048
15049 // TODO
15050 // provide a near and far version of this code
15051
15052 instruct safePoint(iRegP poll)
15053 %{
15054 match(SafePoint poll);
15055
15056 format %{
15057 "ldrw zr, [$poll]\t# Safepoint: poll for GC"
15058 %}
15059 ins_encode %{
15060 __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
15061 %}
15062 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
15063 %}
15064
15065
15066 // ============================================================================
15067 // Procedure Call/Return Instructions
15068
15069 // Call Java Static Instruction
15070
15071 instruct CallStaticJavaDirect(method meth)
15072 %{
15073 match(CallStaticJava);
15074
15075 effect(USE meth);
15076
15077 ins_cost(CALL_COST);
15078
15079 format %{ "call,static $meth \t// ==> " %}
15080
15081 ins_encode( aarch64_enc_java_static_call(meth),
15082 aarch64_enc_call_epilog );
15083
15084 ins_pipe(pipe_class_call);
15085 %}
15086
15087 // TO HERE
15088
15089 // Call Java Dynamic Instruction
15090 instruct CallDynamicJavaDirect(method meth)
15091 %{
15092 match(CallDynamicJava);
15093
15094 effect(USE meth);
15095
15096 ins_cost(CALL_COST);
15097
15098 format %{ "CALL,dynamic $meth \t// ==> " %}
15099
15100 ins_encode( aarch64_enc_java_dynamic_call(meth),
15101 aarch64_enc_call_epilog );
15102
15103 ins_pipe(pipe_class_call);
15104 %}
15105
15106 // Call Runtime Instruction
15107
15108 instruct CallRuntimeDirect(method meth)
15109 %{
15110 match(CallRuntime);
15111
15112 effect(USE meth);
15113
15114 ins_cost(CALL_COST);
15115
15116 format %{ "CALL, runtime $meth" %}
15117
15118 ins_encode( aarch64_enc_java_to_runtime(meth) );
15119
15120 ins_pipe(pipe_class_call);
15121 %}
15122
15123 // Call Runtime Instruction
15124
15125 instruct CallLeafDirect(method meth)
15126 %{
15127 match(CallLeaf);
15128
15129 effect(USE meth);
15130
15131 ins_cost(CALL_COST);
15132
15133 format %{ "CALL, runtime leaf $meth" %}
15134
15135 ins_encode( aarch64_enc_java_to_runtime(meth) );
15136
15137 ins_pipe(pipe_class_call);
15138 %}
15139
15140 // Call Runtime Instruction
15141
15142 instruct CallLeafNoFPDirect(method meth)
15143 %{
15144 match(CallLeafNoFP);
15145
15146 effect(USE meth);
15147
15148 ins_cost(CALL_COST);
15149
15150 format %{ "CALL, runtime leaf nofp $meth" %}
15151
15152 ins_encode( aarch64_enc_java_to_runtime(meth) );
15153
15154 ins_pipe(pipe_class_call);
15155 %}
15156
15157 // Tail Call; Jump from runtime stub to Java code.
15158 // Also known as an 'interprocedural jump'.
15159 // Target of jump will eventually return to caller.
15160 // TailJump below removes the return address.
15161 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
15162 %{
15163 match(TailCall jump_target method_oop);
15164
15165 ins_cost(CALL_COST);
15166
15167 format %{ "br $jump_target\t# $method_oop holds method oop" %}
15168
15169 ins_encode(aarch64_enc_tail_call(jump_target));
15170
15171 ins_pipe(pipe_class_call);
15172 %}
15173
15174 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R0 ex_oop)
15175 %{
15176 match(TailJump jump_target ex_oop);
15177
15178 ins_cost(CALL_COST);
15179
15180 format %{ "br $jump_target\t# $ex_oop holds exception oop" %}
15181
15182 ins_encode(aarch64_enc_tail_jmp(jump_target));
15183
15184 ins_pipe(pipe_class_call);
15185 %}
15186
15187 // Create exception oop: created by stack-crawling runtime code.
15188 // Created exception is now available to this handler, and is setup
15189 // just prior to jumping to this handler. No code emitted.
15190 // TODO check
15191 // should ex_oop be in r0? intel uses rax, ppc cannot use r0 so uses rarg1
15192 instruct CreateException(iRegP_R0 ex_oop)
15193 %{
15194 match(Set ex_oop (CreateEx));
15195
15196 format %{ " -- \t// exception oop; no code emitted" %}
15197
15198 size(0);
15199
15200 ins_encode( /*empty*/ );
15201
15202 ins_pipe(pipe_class_empty);
15203 %}
15204
15205 // Rethrow exception: The exception oop will come in the first
15206 // argument position. Then JUMP (not call) to the rethrow stub code.
15207 instruct RethrowException() %{
15208 match(Rethrow);
15209 ins_cost(CALL_COST);
15210
15211 format %{ "b rethrow_stub" %}
15212
15213 ins_encode( aarch64_enc_rethrow() );
15214
15215 ins_pipe(pipe_class_call);
15216 %}
15217
15218
15219 // Return Instruction
15220 // epilog node loads ret address into lr as part of frame pop
15221 instruct Ret()
15222 %{
15223 match(Return);
15224
15225 format %{ "ret\t// return register" %}
15226
15227 ins_encode( aarch64_enc_ret() );
15228
15229 ins_pipe(pipe_branch);
15230 %}
15231
15232 // Die now.
15233 instruct ShouldNotReachHere() %{
15234 match(Halt);
15235
15236 ins_cost(CALL_COST);
15237 format %{ "ShouldNotReachHere" %}
15238
15239 ins_encode %{
15240 // TODO
15241 // implement proper trap call here
15242 __ brk(999);
15243 %}
15244
15245 ins_pipe(pipe_class_default);
15246 %}
15247
15248 // ============================================================================
15249 // Partial Subtype Check
15250 //
15251 // superklass array for an instance of the superklass. Set a hidden
15252 // internal cache on a hit (cache is checked with exposed code in
15253 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
15254 // encoding ALSO sets flags.
15255
15256 instruct partialSubtypeCheck(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, rFlagsReg cr)
15257 %{
15258 match(Set result (PartialSubtypeCheck sub super));
15259 effect(KILL cr, KILL temp);
15260
15261 ins_cost(1100); // slightly larger than the next version
15262 format %{ "partialSubtypeCheck $result, $sub, $super" %}
15263
15264 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
15265
15266 opcode(0x1); // Force zero of result reg on hit
15267
15268 ins_pipe(pipe_class_memory);
15269 %}
15270
15271 instruct partialSubtypeCheckVsZero(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, immP0 zero, rFlagsReg cr)
15272 %{
15273 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
15274 effect(KILL temp, KILL result);
15275
15276 ins_cost(1100); // slightly larger than the next version
15277 format %{ "partialSubtypeCheck $result, $sub, $super == 0" %}
15278
15279 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
15280
15281 opcode(0x0); // Don't zero result reg on hit
15282
15283 ins_pipe(pipe_class_memory);
15284 %}
15285
15286 instruct string_compareU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
15287 iRegI_R0 result, iRegP_R10 tmp1, rFlagsReg cr)
15288 %{
15289 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
15290 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
15291 effect(KILL tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
15292
15293 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
15294 ins_encode %{
15295 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
15296 __ string_compare($str1$$Register, $str2$$Register,
15297 $cnt1$$Register, $cnt2$$Register, $result$$Register,
15298 $tmp1$$Register,
15299 fnoreg, fnoreg, StrIntrinsicNode::UU);
15300 %}
15301 ins_pipe(pipe_class_memory);
15302 %}
15303
15304 instruct string_compareL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
15305 iRegI_R0 result, iRegP_R10 tmp1, rFlagsReg cr)
15306 %{
15307 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
15308 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
15309 effect(KILL tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
15310
15311 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
15312 ins_encode %{
15313 __ string_compare($str1$$Register, $str2$$Register,
15314 $cnt1$$Register, $cnt2$$Register, $result$$Register,
15315 $tmp1$$Register,
15316 fnoreg, fnoreg, StrIntrinsicNode::LL);
15317 %}
15318 ins_pipe(pipe_class_memory);
15319 %}
15320
15321 instruct string_compareUL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
15322 iRegI_R0 result, vRegD vtmp1, vRegD vtmp2, iRegP_R10 tmp1, rFlagsReg cr)
15323 %{
15324 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
15325 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
15326 effect(KILL tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP vtmp1, TEMP vtmp2, KILL cr);
15327
15328 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
15329 ins_encode %{
15330 __ string_compare($str1$$Register, $str2$$Register,
15331 $cnt1$$Register, $cnt2$$Register, $result$$Register,
15332 $tmp1$$Register,
15333 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, StrIntrinsicNode::UL);
15334 %}
15335 ins_pipe(pipe_class_memory);
15336 %}
15337
15338 instruct string_compareLU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
15339 iRegI_R0 result, vRegD vtmp1, vRegD vtmp2, iRegP_R10 tmp1, rFlagsReg cr)
15340 %{
15341 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
15342 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
15343 effect(KILL tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP vtmp1, TEMP vtmp2, KILL cr);
15344
15345 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
15346 ins_encode %{
15347 __ string_compare($str1$$Register, $str2$$Register,
15348 $cnt1$$Register, $cnt2$$Register, $result$$Register,
15349 $tmp1$$Register,
15350 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, StrIntrinsicNode::LU);
15351 %}
15352 ins_pipe(pipe_class_memory);
15353 %}
15354
15355 instruct string_indexofUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
15356 iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15357 %{
15358 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
15359 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
15360 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
15361 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15362 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
15363
15364 ins_encode %{
15365 __ string_indexof($str1$$Register, $str2$$Register,
15366 $cnt1$$Register, $cnt2$$Register,
15367 $tmp1$$Register, $tmp2$$Register,
15368 $tmp3$$Register, $tmp4$$Register,
15369 -1, $result$$Register, StrIntrinsicNode::UU);
15370 %}
15371 ins_pipe(pipe_class_memory);
15372 %}
15373
15374 instruct string_indexofLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
15375 iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15376 %{
15377 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
15378 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
15379 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
15380 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15381 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
15382
15383 ins_encode %{
15384 __ string_indexof($str1$$Register, $str2$$Register,
15385 $cnt1$$Register, $cnt2$$Register,
15386 $tmp1$$Register, $tmp2$$Register,
15387 $tmp3$$Register, $tmp4$$Register,
15388 -1, $result$$Register, StrIntrinsicNode::LL);
15389 %}
15390 ins_pipe(pipe_class_memory);
15391 %}
15392
15393 instruct string_indexofUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
15394 iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15395 %{
15396 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
15397 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
15398 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
15399 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15400 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
15401
15402 ins_encode %{
15403 __ string_indexof($str1$$Register, $str2$$Register,
15404 $cnt1$$Register, $cnt2$$Register,
15405 $tmp1$$Register, $tmp2$$Register,
15406 $tmp3$$Register, $tmp4$$Register,
15407 -1, $result$$Register, StrIntrinsicNode::UL);
15408 %}
15409 ins_pipe(pipe_class_memory);
15410 %}
15411
15412 instruct string_indexofLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
15413 iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15414 %{
15415 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LU);
15416 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
15417 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
15418 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15419 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LU)" %}
15420
15421 ins_encode %{
15422 __ string_indexof($str1$$Register, $str2$$Register,
15423 $cnt1$$Register, $cnt2$$Register,
15424 $tmp1$$Register, $tmp2$$Register,
15425 $tmp3$$Register, $tmp4$$Register,
15426 -1, $result$$Register, StrIntrinsicNode::LU);
15427 %}
15428 ins_pipe(pipe_class_memory);
15429 %}
15430
15431 instruct string_indexof_conUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
15432 immI_le_4 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
15433 iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15434 %{
15435 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
15436 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
15437 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
15438 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15439 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
15440
15441 ins_encode %{
15442 int icnt2 = (int)$int_cnt2$$constant;
15443 __ string_indexof($str1$$Register, $str2$$Register,
15444 $cnt1$$Register, zr,
15445 $tmp1$$Register, $tmp2$$Register,
15446 $tmp3$$Register, $tmp4$$Register,
15447 icnt2, $result$$Register, StrIntrinsicNode::UU);
15448 %}
15449 ins_pipe(pipe_class_memory);
15450 %}
15451
15452 instruct string_indexof_conLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
15453 immI_le_4 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
15454 iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15455 %{
15456 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
15457 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
15458 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
15459 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15460 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
15461
15462 ins_encode %{
15463 int icnt2 = (int)$int_cnt2$$constant;
15464 __ string_indexof($str1$$Register, $str2$$Register,
15465 $cnt1$$Register, zr,
15466 $tmp1$$Register, $tmp2$$Register,
15467 $tmp3$$Register, $tmp4$$Register,
15468 icnt2, $result$$Register, StrIntrinsicNode::LL);
15469 %}
15470 ins_pipe(pipe_class_memory);
15471 %}
15472
15473 instruct string_indexof_conUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
15474 immI_1 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
15475 iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15476 %{
15477 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
15478 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
15479 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
15480 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15481 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
15482
15483 ins_encode %{
15484 int icnt2 = (int)$int_cnt2$$constant;
15485 __ string_indexof($str1$$Register, $str2$$Register,
15486 $cnt1$$Register, zr,
15487 $tmp1$$Register, $tmp2$$Register,
15488 $tmp3$$Register, $tmp4$$Register,
15489 icnt2, $result$$Register, StrIntrinsicNode::UL);
15490 %}
15491 ins_pipe(pipe_class_memory);
15492 %}
15493
15494 instruct string_indexof_conLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
15495 immI_1 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
15496 iRegI tmp3, iRegI tmp4, rFlagsReg cr)
15497 %{
15498 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LU);
15499 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
15500 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
15501 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
15502 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LU)" %}
15503
15504 ins_encode %{
15505 int icnt2 = (int)$int_cnt2$$constant;
15506 __ string_indexof($str1$$Register, $str2$$Register,
15507 $cnt1$$Register, zr,
15508 $tmp1$$Register, $tmp2$$Register,
15509 $tmp3$$Register, $tmp4$$Register,
15510 icnt2, $result$$Register, StrIntrinsicNode::LU);
15511 %}
15512 ins_pipe(pipe_class_memory);
15513 %}
15514
15515 instruct string_indexofU_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
15516 iRegI_R0 result, iRegI tmp1, iRegI tmp2,
15517 iRegI tmp3, rFlagsReg cr)
15518 %{
15519 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
15520 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
15521 TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
15522
15523 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result" %}
15524
15525 ins_encode %{
15526 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
15527 $result$$Register, $tmp1$$Register, $tmp2$$Register,
15528 $tmp3$$Register);
15529 %}
15530 ins_pipe(pipe_class_memory);
15531 %}
15532
15533 instruct string_equalsL(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
15534 iRegI_R0 result, rFlagsReg cr)
15535 %{
15536 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
15537 match(Set result (StrEquals (Binary str1 str2) cnt));
15538 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
15539
15540 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
15541 ins_encode %{
15542 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
15543 __ arrays_equals($str1$$Register, $str2$$Register,
15544 $result$$Register, $cnt$$Register,
15545 1, /*is_string*/true);
15546 %}
15547 ins_pipe(pipe_class_memory);
15548 %}
15549
15550 instruct string_equalsU(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
15551 iRegI_R0 result, rFlagsReg cr)
15552 %{
15553 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
15554 match(Set result (StrEquals (Binary str1 str2) cnt));
15555 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
15556
15557 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
15558 ins_encode %{
15559 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
15560 __ asrw($cnt$$Register, $cnt$$Register, 1);
15561 __ arrays_equals($str1$$Register, $str2$$Register,
15562 $result$$Register, $cnt$$Register,
15563 2, /*is_string*/true);
15564 %}
15565 ins_pipe(pipe_class_memory);
15566 %}
15567
15568 instruct array_equalsB(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
15569 iRegP_R10 tmp, rFlagsReg cr)
15570 %{
15571 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
15572 match(Set result (AryEq ary1 ary2));
15573 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, KILL cr);
15574
15575 format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %}
15576 ins_encode %{
15577 __ arrays_equals($ary1$$Register, $ary2$$Register,
15578 $result$$Register, $tmp$$Register,
15579 1, /*is_string*/false);
15580 %}
15581 ins_pipe(pipe_class_memory);
15582 %}
15583
15584 instruct array_equalsC(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
15585 iRegP_R10 tmp, rFlagsReg cr)
15586 %{
15587 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
15588 match(Set result (AryEq ary1 ary2));
15589 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, KILL cr);
15590
15591 format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %}
15592 ins_encode %{
15593 __ arrays_equals($ary1$$Register, $ary2$$Register,
15594 $result$$Register, $tmp$$Register,
15595 2, /*is_string*/false);
15596 %}
15597 ins_pipe(pipe_class_memory);
15598 %}
15599
15600
15601 // fast char[] to byte[] compression
15602 instruct string_compress(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
15603 vRegD_V0 tmp1, vRegD_V1 tmp2,
15604 vRegD_V2 tmp3, vRegD_V3 tmp4,
15605 iRegI_R0 result, rFlagsReg cr)
15606 %{
15607 match(Set result (StrCompressedCopy src (Binary dst len)));
15608 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
15609
15610 format %{ "String Compress $src,$dst -> $result // KILL R1, R2, R3, R4" %}
15611 ins_encode %{
15612 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
15613 $tmp1$$FloatRegister, $tmp2$$FloatRegister,
15614 $tmp3$$FloatRegister, $tmp4$$FloatRegister,
15615 $result$$Register);
15616 %}
15617 ins_pipe( pipe_slow );
15618 %}
15619
15620 // fast byte[] to char[] inflation
15621 instruct string_inflate(Universe dummy, iRegP_R0 src, iRegP_R1 dst, iRegI_R2 len,
15622 vRegD tmp1, vRegD tmp2, vRegD tmp3, iRegP_R3 tmp4, rFlagsReg cr)
15623 %{
15624 match(Set dummy (StrInflatedCopy src (Binary dst len)));
15625 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
15626
15627 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
15628 ins_encode %{
15629 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
15630 $tmp1$$FloatRegister, $tmp2$$FloatRegister, $tmp3$$FloatRegister, $tmp4$$Register);
15631 %}
15632 ins_pipe(pipe_class_memory);
15633 %}
15634
15635 // encode char[] to byte[] in ISO_8859_1
15636 instruct encode_iso_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
15637 vRegD_V0 Vtmp1, vRegD_V1 Vtmp2,
15638 vRegD_V2 Vtmp3, vRegD_V3 Vtmp4,
15639 iRegI_R0 result, rFlagsReg cr)
15640 %{
15641 match(Set result (EncodeISOArray src (Binary dst len)));
15642 effect(USE_KILL src, USE_KILL dst, USE_KILL len,
15643 KILL Vtmp1, KILL Vtmp2, KILL Vtmp3, KILL Vtmp4, KILL cr);
15644
15645 format %{ "Encode array $src,$dst,$len -> $result" %}
15646 ins_encode %{
15647 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
15648 $result$$Register, $Vtmp1$$FloatRegister, $Vtmp2$$FloatRegister,
15649 $Vtmp3$$FloatRegister, $Vtmp4$$FloatRegister);
15650 %}
15651 ins_pipe( pipe_class_memory );
15652 %}
15653
15654 // ============================================================================
15655 // This name is KNOWN by the ADLC and cannot be changed.
15656 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
15657 // for this guy.
15658 instruct tlsLoadP(thread_RegP dst)
15659 %{
15660 match(Set dst (ThreadLocal));
15661
15662 ins_cost(0);
15663
15664 format %{ " -- \t// $dst=Thread::current(), empty" %}
15665
15666 size(0);
15667
15668 ins_encode( /*empty*/ );
15669
15670 ins_pipe(pipe_class_empty);
15671 %}
15672
15673 // ====================VECTOR INSTRUCTIONS=====================================
15674
15675 // Load vector (32 bits)
15676 instruct loadV4(vecD dst, vmem4 mem)
15677 %{
15678 predicate(n->as_LoadVector()->memory_size() == 4);
15679 match(Set dst (LoadVector mem));
15680 ins_cost(4 * INSN_COST);
15681 format %{ "ldrs $dst,$mem\t# vector (32 bits)" %}
15682 ins_encode( aarch64_enc_ldrvS(dst, mem) );
15683 ins_pipe(vload_reg_mem64);
15684 %}
15685
15686 // Load vector (64 bits)
15687 instruct loadV8(vecD dst, vmem8 mem)
15688 %{
15689 predicate(n->as_LoadVector()->memory_size() == 8);
15690 match(Set dst (LoadVector mem));
15691 ins_cost(4 * INSN_COST);
15692 format %{ "ldrd $dst,$mem\t# vector (64 bits)" %}
15693 ins_encode( aarch64_enc_ldrvD(dst, mem) );
15694 ins_pipe(vload_reg_mem64);
15695 %}
15696
15697 // Load Vector (128 bits)
15698 instruct loadV16(vecX dst, vmem16 mem)
15699 %{
15700 predicate(n->as_LoadVector()->memory_size() == 16);
15701 match(Set dst (LoadVector mem));
15702 ins_cost(4 * INSN_COST);
15703 format %{ "ldrq $dst,$mem\t# vector (128 bits)" %}
15704 ins_encode( aarch64_enc_ldrvQ(dst, mem) );
15705 ins_pipe(vload_reg_mem128);
15706 %}
15707
15708 // Store Vector (32 bits)
15709 instruct storeV4(vecD src, vmem4 mem)
15710 %{
15711 predicate(n->as_StoreVector()->memory_size() == 4);
15712 match(Set mem (StoreVector mem src));
15713 ins_cost(4 * INSN_COST);
15714 format %{ "strs $mem,$src\t# vector (32 bits)" %}
15715 ins_encode( aarch64_enc_strvS(src, mem) );
15716 ins_pipe(vstore_reg_mem64);
15717 %}
15718
15719 // Store Vector (64 bits)
15720 instruct storeV8(vecD src, vmem8 mem)
15721 %{
15722 predicate(n->as_StoreVector()->memory_size() == 8);
15723 match(Set mem (StoreVector mem src));
15724 ins_cost(4 * INSN_COST);
15725 format %{ "strd $mem,$src\t# vector (64 bits)" %}
15726 ins_encode( aarch64_enc_strvD(src, mem) );
15727 ins_pipe(vstore_reg_mem64);
15728 %}
15729
15730 // Store Vector (128 bits)
15731 instruct storeV16(vecX src, vmem16 mem)
15732 %{
15733 predicate(n->as_StoreVector()->memory_size() == 16);
15734 match(Set mem (StoreVector mem src));
15735 ins_cost(4 * INSN_COST);
15736 format %{ "strq $mem,$src\t# vector (128 bits)" %}
15737 ins_encode( aarch64_enc_strvQ(src, mem) );
15738 ins_pipe(vstore_reg_mem128);
15739 %}
15740
15741 instruct replicate8B(vecD dst, iRegIorL2I src)
15742 %{
15743 predicate(n->as_Vector()->length() == 4 ||
15744 n->as_Vector()->length() == 8);
15745 match(Set dst (ReplicateB src));
15746 ins_cost(INSN_COST);
15747 format %{ "dup $dst, $src\t# vector (8B)" %}
15748 ins_encode %{
15749 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($src$$reg));
15750 %}
15751 ins_pipe(vdup_reg_reg64);
15752 %}
15753
15754 instruct replicate16B(vecX dst, iRegIorL2I src)
15755 %{
15756 predicate(n->as_Vector()->length() == 16);
15757 match(Set dst (ReplicateB src));
15758 ins_cost(INSN_COST);
15759 format %{ "dup $dst, $src\t# vector (16B)" %}
15760 ins_encode %{
15761 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($src$$reg));
15762 %}
15763 ins_pipe(vdup_reg_reg128);
15764 %}
15765
15766 instruct replicate8B_imm(vecD dst, immI con)
15767 %{
15768 predicate(n->as_Vector()->length() == 4 ||
15769 n->as_Vector()->length() == 8);
15770 match(Set dst (ReplicateB con));
15771 ins_cost(INSN_COST);
15772 format %{ "movi $dst, $con\t# vector(8B)" %}
15773 ins_encode %{
15774 __ mov(as_FloatRegister($dst$$reg), __ T8B, $con$$constant & 0xff);
15775 %}
15776 ins_pipe(vmovi_reg_imm64);
15777 %}
15778
15779 instruct replicate16B_imm(vecX dst, immI con)
15780 %{
15781 predicate(n->as_Vector()->length() == 16);
15782 match(Set dst (ReplicateB con));
15783 ins_cost(INSN_COST);
15784 format %{ "movi $dst, $con\t# vector(16B)" %}
15785 ins_encode %{
15786 __ mov(as_FloatRegister($dst$$reg), __ T16B, $con$$constant & 0xff);
15787 %}
15788 ins_pipe(vmovi_reg_imm128);
15789 %}
15790
15791 instruct replicate4S(vecD dst, iRegIorL2I src)
15792 %{
15793 predicate(n->as_Vector()->length() == 2 ||
15794 n->as_Vector()->length() == 4);
15795 match(Set dst (ReplicateS src));
15796 ins_cost(INSN_COST);
15797 format %{ "dup $dst, $src\t# vector (4S)" %}
15798 ins_encode %{
15799 __ dup(as_FloatRegister($dst$$reg), __ T4H, as_Register($src$$reg));
15800 %}
15801 ins_pipe(vdup_reg_reg64);
15802 %}
15803
15804 instruct replicate8S(vecX dst, iRegIorL2I src)
15805 %{
15806 predicate(n->as_Vector()->length() == 8);
15807 match(Set dst (ReplicateS src));
15808 ins_cost(INSN_COST);
15809 format %{ "dup $dst, $src\t# vector (8S)" %}
15810 ins_encode %{
15811 __ dup(as_FloatRegister($dst$$reg), __ T8H, as_Register($src$$reg));
15812 %}
15813 ins_pipe(vdup_reg_reg128);
15814 %}
15815
15816 instruct replicate4S_imm(vecD dst, immI con)
15817 %{
15818 predicate(n->as_Vector()->length() == 2 ||
15819 n->as_Vector()->length() == 4);
15820 match(Set dst (ReplicateS con));
15821 ins_cost(INSN_COST);
15822 format %{ "movi $dst, $con\t# vector(4H)" %}
15823 ins_encode %{
15824 __ mov(as_FloatRegister($dst$$reg), __ T4H, $con$$constant & 0xffff);
15825 %}
15826 ins_pipe(vmovi_reg_imm64);
15827 %}
15828
15829 instruct replicate8S_imm(vecX dst, immI con)
15830 %{
15831 predicate(n->as_Vector()->length() == 8);
15832 match(Set dst (ReplicateS con));
15833 ins_cost(INSN_COST);
15834 format %{ "movi $dst, $con\t# vector(8H)" %}
15835 ins_encode %{
15836 __ mov(as_FloatRegister($dst$$reg), __ T8H, $con$$constant & 0xffff);
15837 %}
15838 ins_pipe(vmovi_reg_imm128);
15839 %}
15840
15841 instruct replicate2I(vecD dst, iRegIorL2I src)
15842 %{
15843 predicate(n->as_Vector()->length() == 2);
15844 match(Set dst (ReplicateI src));
15845 ins_cost(INSN_COST);
15846 format %{ "dup $dst, $src\t# vector (2I)" %}
15847 ins_encode %{
15848 __ dup(as_FloatRegister($dst$$reg), __ T2S, as_Register($src$$reg));
15849 %}
15850 ins_pipe(vdup_reg_reg64);
15851 %}
15852
15853 instruct replicate4I(vecX dst, iRegIorL2I src)
15854 %{
15855 predicate(n->as_Vector()->length() == 4);
15856 match(Set dst (ReplicateI src));
15857 ins_cost(INSN_COST);
15858 format %{ "dup $dst, $src\t# vector (4I)" %}
15859 ins_encode %{
15860 __ dup(as_FloatRegister($dst$$reg), __ T4S, as_Register($src$$reg));
15861 %}
15862 ins_pipe(vdup_reg_reg128);
15863 %}
15864
15865 instruct replicate2I_imm(vecD dst, immI con)
15866 %{
15867 predicate(n->as_Vector()->length() == 2);
15868 match(Set dst (ReplicateI con));
15869 ins_cost(INSN_COST);
15870 format %{ "movi $dst, $con\t# vector(2I)" %}
15871 ins_encode %{
15872 __ mov(as_FloatRegister($dst$$reg), __ T2S, $con$$constant);
15873 %}
15874 ins_pipe(vmovi_reg_imm64);
15875 %}
15876
15877 instruct replicate4I_imm(vecX dst, immI con)
15878 %{
15879 predicate(n->as_Vector()->length() == 4);
15880 match(Set dst (ReplicateI con));
15881 ins_cost(INSN_COST);
15882 format %{ "movi $dst, $con\t# vector(4I)" %}
15883 ins_encode %{
15884 __ mov(as_FloatRegister($dst$$reg), __ T4S, $con$$constant);
15885 %}
15886 ins_pipe(vmovi_reg_imm128);
15887 %}
15888
15889 instruct replicate2L(vecX dst, iRegL src)
15890 %{
15891 predicate(n->as_Vector()->length() == 2);
15892 match(Set dst (ReplicateL src));
15893 ins_cost(INSN_COST);
15894 format %{ "dup $dst, $src\t# vector (2L)" %}
15895 ins_encode %{
15896 __ dup(as_FloatRegister($dst$$reg), __ T2D, as_Register($src$$reg));
15897 %}
15898 ins_pipe(vdup_reg_reg128);
15899 %}
15900
15901 instruct replicate2L_zero(vecX dst, immI0 zero)
15902 %{
15903 predicate(n->as_Vector()->length() == 2);
15904 match(Set dst (ReplicateI zero));
15905 ins_cost(INSN_COST);
15906 format %{ "movi $dst, $zero\t# vector(4I)" %}
15907 ins_encode %{
15908 __ eor(as_FloatRegister($dst$$reg), __ T16B,
15909 as_FloatRegister($dst$$reg),
15910 as_FloatRegister($dst$$reg));
15911 %}
15912 ins_pipe(vmovi_reg_imm128);
15913 %}
15914
15915 instruct replicate2F(vecD dst, vRegF src)
15916 %{
15917 predicate(n->as_Vector()->length() == 2);
15918 match(Set dst (ReplicateF src));
15919 ins_cost(INSN_COST);
15920 format %{ "dup $dst, $src\t# vector (2F)" %}
15921 ins_encode %{
15922 __ dup(as_FloatRegister($dst$$reg), __ T2S,
15923 as_FloatRegister($src$$reg));
15924 %}
15925 ins_pipe(vdup_reg_freg64);
15926 %}
15927
15928 instruct replicate4F(vecX dst, vRegF src)
15929 %{
15930 predicate(n->as_Vector()->length() == 4);
15931 match(Set dst (ReplicateF src));
15932 ins_cost(INSN_COST);
15933 format %{ "dup $dst, $src\t# vector (4F)" %}
15934 ins_encode %{
15935 __ dup(as_FloatRegister($dst$$reg), __ T4S,
15936 as_FloatRegister($src$$reg));
15937 %}
15938 ins_pipe(vdup_reg_freg128);
15939 %}
15940
15941 instruct replicate2D(vecX dst, vRegD src)
15942 %{
15943 predicate(n->as_Vector()->length() == 2);
15944 match(Set dst (ReplicateD src));
15945 ins_cost(INSN_COST);
15946 format %{ "dup $dst, $src\t# vector (2D)" %}
15947 ins_encode %{
15948 __ dup(as_FloatRegister($dst$$reg), __ T2D,
15949 as_FloatRegister($src$$reg));
15950 %}
15951 ins_pipe(vdup_reg_dreg128);
15952 %}
15953
15954 // ====================REDUCTION ARITHMETIC====================================
15955
15956 instruct reduce_add2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp, iRegI tmp2)
15957 %{
15958 match(Set dst (AddReductionVI src1 src2));
15959 ins_cost(INSN_COST);
15960 effect(TEMP tmp, TEMP tmp2);
15961 format %{ "umov $tmp, $src2, S, 0\n\t"
15962 "umov $tmp2, $src2, S, 1\n\t"
15963 "addw $dst, $src1, $tmp\n\t"
15964 "addw $dst, $dst, $tmp2\t add reduction2i"
15965 %}
15966 ins_encode %{
15967 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0);
15968 __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ S, 1);
15969 __ addw($dst$$Register, $src1$$Register, $tmp$$Register);
15970 __ addw($dst$$Register, $dst$$Register, $tmp2$$Register);
15971 %}
15972 ins_pipe(pipe_class_default);
15973 %}
15974
15975 instruct reduce_add4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegI tmp2)
15976 %{
15977 match(Set dst (AddReductionVI src1 src2));
15978 ins_cost(INSN_COST);
15979 effect(TEMP tmp, TEMP tmp2);
15980 format %{ "addv $tmp, T4S, $src2\n\t"
15981 "umov $tmp2, $tmp, S, 0\n\t"
15982 "addw $dst, $tmp2, $src1\t add reduction4i"
15983 %}
15984 ins_encode %{
15985 __ addv(as_FloatRegister($tmp$$reg), __ T4S,
15986 as_FloatRegister($src2$$reg));
15987 __ umov($tmp2$$Register, as_FloatRegister($tmp$$reg), __ S, 0);
15988 __ addw($dst$$Register, $tmp2$$Register, $src1$$Register);
15989 %}
15990 ins_pipe(pipe_class_default);
15991 %}
15992
15993 instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp)
15994 %{
15995 match(Set dst (MulReductionVI src1 src2));
15996 ins_cost(INSN_COST);
15997 effect(TEMP tmp, TEMP dst);
15998 format %{ "umov $tmp, $src2, S, 0\n\t"
15999 "mul $dst, $tmp, $src1\n\t"
16000 "umov $tmp, $src2, S, 1\n\t"
16001 "mul $dst, $tmp, $dst\t mul reduction2i\n\t"
16002 %}
16003 ins_encode %{
16004 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0);
16005 __ mul($dst$$Register, $tmp$$Register, $src1$$Register);
16006 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 1);
16007 __ mul($dst$$Register, $tmp$$Register, $dst$$Register);
16008 %}
16009 ins_pipe(pipe_class_default);
16010 %}
16011
16012 instruct reduce_mul4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegI tmp2)
16013 %{
16014 match(Set dst (MulReductionVI src1 src2));
16015 ins_cost(INSN_COST);
16016 effect(TEMP tmp, TEMP tmp2, TEMP dst);
16017 format %{ "ins $tmp, $src2, 0, 1\n\t"
16018 "mul $tmp, $tmp, $src2\n\t"
16019 "umov $tmp2, $tmp, S, 0\n\t"
16020 "mul $dst, $tmp2, $src1\n\t"
16021 "umov $tmp2, $tmp, S, 1\n\t"
16022 "mul $dst, $tmp2, $dst\t mul reduction4i\n\t"
16023 %}
16024 ins_encode %{
16025 __ ins(as_FloatRegister($tmp$$reg), __ D,
16026 as_FloatRegister($src2$$reg), 0, 1);
16027 __ mulv(as_FloatRegister($tmp$$reg), __ T2S,
16028 as_FloatRegister($tmp$$reg), as_FloatRegister($src2$$reg));
16029 __ umov($tmp2$$Register, as_FloatRegister($tmp$$reg), __ S, 0);
16030 __ mul($dst$$Register, $tmp2$$Register, $src1$$Register);
16031 __ umov($tmp2$$Register, as_FloatRegister($tmp$$reg), __ S, 1);
16032 __ mul($dst$$Register, $tmp2$$Register, $dst$$Register);
16033 %}
16034 ins_pipe(pipe_class_default);
16035 %}
16036
16037 instruct reduce_add2F(vRegF dst, vRegF src1, vecD src2, vecD tmp)
16038 %{
16039 match(Set dst (AddReductionVF src1 src2));
16040 ins_cost(INSN_COST);
16041 effect(TEMP tmp, TEMP dst);
16042 format %{ "fadds $dst, $src1, $src2\n\t"
16043 "ins $tmp, S, $src2, 0, 1\n\t"
16044 "fadds $dst, $dst, $tmp\t add reduction2f"
16045 %}
16046 ins_encode %{
16047 __ fadds(as_FloatRegister($dst$$reg),
16048 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16049 __ ins(as_FloatRegister($tmp$$reg), __ S,
16050 as_FloatRegister($src2$$reg), 0, 1);
16051 __ fadds(as_FloatRegister($dst$$reg),
16052 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16053 %}
16054 ins_pipe(pipe_class_default);
16055 %}
16056
16057 instruct reduce_add4F(vRegF dst, vRegF src1, vecX src2, vecX tmp)
16058 %{
16059 match(Set dst (AddReductionVF src1 src2));
16060 ins_cost(INSN_COST);
16061 effect(TEMP tmp, TEMP dst);
16062 format %{ "fadds $dst, $src1, $src2\n\t"
16063 "ins $tmp, S, $src2, 0, 1\n\t"
16064 "fadds $dst, $dst, $tmp\n\t"
16065 "ins $tmp, S, $src2, 0, 2\n\t"
16066 "fadds $dst, $dst, $tmp\n\t"
16067 "ins $tmp, S, $src2, 0, 3\n\t"
16068 "fadds $dst, $dst, $tmp\t add reduction4f"
16069 %}
16070 ins_encode %{
16071 __ fadds(as_FloatRegister($dst$$reg),
16072 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16073 __ ins(as_FloatRegister($tmp$$reg), __ S,
16074 as_FloatRegister($src2$$reg), 0, 1);
16075 __ fadds(as_FloatRegister($dst$$reg),
16076 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16077 __ ins(as_FloatRegister($tmp$$reg), __ S,
16078 as_FloatRegister($src2$$reg), 0, 2);
16079 __ fadds(as_FloatRegister($dst$$reg),
16080 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16081 __ ins(as_FloatRegister($tmp$$reg), __ S,
16082 as_FloatRegister($src2$$reg), 0, 3);
16083 __ fadds(as_FloatRegister($dst$$reg),
16084 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16085 %}
16086 ins_pipe(pipe_class_default);
16087 %}
16088
16089 instruct reduce_mul2F(vRegF dst, vRegF src1, vecD src2, vecD tmp)
16090 %{
16091 match(Set dst (MulReductionVF src1 src2));
16092 ins_cost(INSN_COST);
16093 effect(TEMP tmp, TEMP dst);
16094 format %{ "fmuls $dst, $src1, $src2\n\t"
16095 "ins $tmp, S, $src2, 0, 1\n\t"
16096 "fmuls $dst, $dst, $tmp\t add reduction4f"
16097 %}
16098 ins_encode %{
16099 __ fmuls(as_FloatRegister($dst$$reg),
16100 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16101 __ ins(as_FloatRegister($tmp$$reg), __ S,
16102 as_FloatRegister($src2$$reg), 0, 1);
16103 __ fmuls(as_FloatRegister($dst$$reg),
16104 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16105 %}
16106 ins_pipe(pipe_class_default);
16107 %}
16108
16109 instruct reduce_mul4F(vRegF dst, vRegF src1, vecX src2, vecX tmp)
16110 %{
16111 match(Set dst (MulReductionVF src1 src2));
16112 ins_cost(INSN_COST);
16113 effect(TEMP tmp, TEMP dst);
16114 format %{ "fmuls $dst, $src1, $src2\n\t"
16115 "ins $tmp, S, $src2, 0, 1\n\t"
16116 "fmuls $dst, $dst, $tmp\n\t"
16117 "ins $tmp, S, $src2, 0, 2\n\t"
16118 "fmuls $dst, $dst, $tmp\n\t"
16119 "ins $tmp, S, $src2, 0, 3\n\t"
16120 "fmuls $dst, $dst, $tmp\t add reduction4f"
16121 %}
16122 ins_encode %{
16123 __ fmuls(as_FloatRegister($dst$$reg),
16124 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16125 __ ins(as_FloatRegister($tmp$$reg), __ S,
16126 as_FloatRegister($src2$$reg), 0, 1);
16127 __ fmuls(as_FloatRegister($dst$$reg),
16128 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16129 __ ins(as_FloatRegister($tmp$$reg), __ S,
16130 as_FloatRegister($src2$$reg), 0, 2);
16131 __ fmuls(as_FloatRegister($dst$$reg),
16132 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16133 __ ins(as_FloatRegister($tmp$$reg), __ S,
16134 as_FloatRegister($src2$$reg), 0, 3);
16135 __ fmuls(as_FloatRegister($dst$$reg),
16136 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16137 %}
16138 ins_pipe(pipe_class_default);
16139 %}
16140
16141 instruct reduce_add2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
16142 %{
16143 match(Set dst (AddReductionVD src1 src2));
16144 ins_cost(INSN_COST);
16145 effect(TEMP tmp, TEMP dst);
16146 format %{ "faddd $dst, $src1, $src2\n\t"
16147 "ins $tmp, D, $src2, 0, 1\n\t"
16148 "faddd $dst, $dst, $tmp\t add reduction2d"
16149 %}
16150 ins_encode %{
16151 __ faddd(as_FloatRegister($dst$$reg),
16152 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16153 __ ins(as_FloatRegister($tmp$$reg), __ D,
16154 as_FloatRegister($src2$$reg), 0, 1);
16155 __ faddd(as_FloatRegister($dst$$reg),
16156 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16157 %}
16158 ins_pipe(pipe_class_default);
16159 %}
16160
16161 instruct reduce_mul2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
16162 %{
16163 match(Set dst (MulReductionVD src1 src2));
16164 ins_cost(INSN_COST);
16165 effect(TEMP tmp, TEMP dst);
16166 format %{ "fmuld $dst, $src1, $src2\n\t"
16167 "ins $tmp, D, $src2, 0, 1\n\t"
16168 "fmuld $dst, $dst, $tmp\t add reduction2d"
16169 %}
16170 ins_encode %{
16171 __ fmuld(as_FloatRegister($dst$$reg),
16172 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
16173 __ ins(as_FloatRegister($tmp$$reg), __ D,
16174 as_FloatRegister($src2$$reg), 0, 1);
16175 __ fmuld(as_FloatRegister($dst$$reg),
16176 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
16177 %}
16178 ins_pipe(pipe_class_default);
16179 %}
16180
16181 // ====================VECTOR ARITHMETIC=======================================
16182
16183 // --------------------------------- ADD --------------------------------------
16184
16185 instruct vadd8B(vecD dst, vecD src1, vecD src2)
16186 %{
16187 predicate(n->as_Vector()->length() == 4 ||
16188 n->as_Vector()->length() == 8);
16189 match(Set dst (AddVB src1 src2));
16190 ins_cost(INSN_COST);
16191 format %{ "addv $dst,$src1,$src2\t# vector (8B)" %}
16192 ins_encode %{
16193 __ addv(as_FloatRegister($dst$$reg), __ T8B,
16194 as_FloatRegister($src1$$reg),
16195 as_FloatRegister($src2$$reg));
16196 %}
16197 ins_pipe(vdop64);
16198 %}
16199
16200 instruct vadd16B(vecX dst, vecX src1, vecX src2)
16201 %{
16202 predicate(n->as_Vector()->length() == 16);
16203 match(Set dst (AddVB src1 src2));
16204 ins_cost(INSN_COST);
16205 format %{ "addv $dst,$src1,$src2\t# vector (16B)" %}
16206 ins_encode %{
16207 __ addv(as_FloatRegister($dst$$reg), __ T16B,
16208 as_FloatRegister($src1$$reg),
16209 as_FloatRegister($src2$$reg));
16210 %}
16211 ins_pipe(vdop128);
16212 %}
16213
16214 instruct vadd4S(vecD dst, vecD src1, vecD src2)
16215 %{
16216 predicate(n->as_Vector()->length() == 2 ||
16217 n->as_Vector()->length() == 4);
16218 match(Set dst (AddVS src1 src2));
16219 ins_cost(INSN_COST);
16220 format %{ "addv $dst,$src1,$src2\t# vector (4H)" %}
16221 ins_encode %{
16222 __ addv(as_FloatRegister($dst$$reg), __ T4H,
16223 as_FloatRegister($src1$$reg),
16224 as_FloatRegister($src2$$reg));
16225 %}
16226 ins_pipe(vdop64);
16227 %}
16228
16229 instruct vadd8S(vecX dst, vecX src1, vecX src2)
16230 %{
16231 predicate(n->as_Vector()->length() == 8);
16232 match(Set dst (AddVS src1 src2));
16233 ins_cost(INSN_COST);
16234 format %{ "addv $dst,$src1,$src2\t# vector (8H)" %}
16235 ins_encode %{
16236 __ addv(as_FloatRegister($dst$$reg), __ T8H,
16237 as_FloatRegister($src1$$reg),
16238 as_FloatRegister($src2$$reg));
16239 %}
16240 ins_pipe(vdop128);
16241 %}
16242
16243 instruct vadd2I(vecD dst, vecD src1, vecD src2)
16244 %{
16245 predicate(n->as_Vector()->length() == 2);
16246 match(Set dst (AddVI src1 src2));
16247 ins_cost(INSN_COST);
16248 format %{ "addv $dst,$src1,$src2\t# vector (2S)" %}
16249 ins_encode %{
16250 __ addv(as_FloatRegister($dst$$reg), __ T2S,
16251 as_FloatRegister($src1$$reg),
16252 as_FloatRegister($src2$$reg));
16253 %}
16254 ins_pipe(vdop64);
16255 %}
16256
16257 instruct vadd4I(vecX dst, vecX src1, vecX src2)
16258 %{
16259 predicate(n->as_Vector()->length() == 4);
16260 match(Set dst (AddVI src1 src2));
16261 ins_cost(INSN_COST);
16262 format %{ "addv $dst,$src1,$src2\t# vector (4S)" %}
16263 ins_encode %{
16264 __ addv(as_FloatRegister($dst$$reg), __ T4S,
16265 as_FloatRegister($src1$$reg),
16266 as_FloatRegister($src2$$reg));
16267 %}
16268 ins_pipe(vdop128);
16269 %}
16270
16271 instruct vadd2L(vecX dst, vecX src1, vecX src2)
16272 %{
16273 predicate(n->as_Vector()->length() == 2);
16274 match(Set dst (AddVL src1 src2));
16275 ins_cost(INSN_COST);
16276 format %{ "addv $dst,$src1,$src2\t# vector (2L)" %}
16277 ins_encode %{
16278 __ addv(as_FloatRegister($dst$$reg), __ T2D,
16279 as_FloatRegister($src1$$reg),
16280 as_FloatRegister($src2$$reg));
16281 %}
16282 ins_pipe(vdop128);
16283 %}
16284
16285 instruct vadd2F(vecD dst, vecD src1, vecD src2)
16286 %{
16287 predicate(n->as_Vector()->length() == 2);
16288 match(Set dst (AddVF src1 src2));
16289 ins_cost(INSN_COST);
16290 format %{ "fadd $dst,$src1,$src2\t# vector (2S)" %}
16291 ins_encode %{
16292 __ fadd(as_FloatRegister($dst$$reg), __ T2S,
16293 as_FloatRegister($src1$$reg),
16294 as_FloatRegister($src2$$reg));
16295 %}
16296 ins_pipe(vdop_fp64);
16297 %}
16298
16299 instruct vadd4F(vecX dst, vecX src1, vecX src2)
16300 %{
16301 predicate(n->as_Vector()->length() == 4);
16302 match(Set dst (AddVF src1 src2));
16303 ins_cost(INSN_COST);
16304 format %{ "fadd $dst,$src1,$src2\t# vector (4S)" %}
16305 ins_encode %{
16306 __ fadd(as_FloatRegister($dst$$reg), __ T4S,
16307 as_FloatRegister($src1$$reg),
16308 as_FloatRegister($src2$$reg));
16309 %}
16310 ins_pipe(vdop_fp128);
16311 %}
16312
16313 instruct vadd2D(vecX dst, vecX src1, vecX src2)
16314 %{
16315 match(Set dst (AddVD src1 src2));
16316 ins_cost(INSN_COST);
16317 format %{ "fadd $dst,$src1,$src2\t# vector (2D)" %}
16318 ins_encode %{
16319 __ fadd(as_FloatRegister($dst$$reg), __ T2D,
16320 as_FloatRegister($src1$$reg),
16321 as_FloatRegister($src2$$reg));
16322 %}
16323 ins_pipe(vdop_fp128);
16324 %}
16325
16326 // --------------------------------- SUB --------------------------------------
16327
16328 instruct vsub8B(vecD dst, vecD src1, vecD src2)
16329 %{
16330 predicate(n->as_Vector()->length() == 4 ||
16331 n->as_Vector()->length() == 8);
16332 match(Set dst (SubVB src1 src2));
16333 ins_cost(INSN_COST);
16334 format %{ "subv $dst,$src1,$src2\t# vector (8B)" %}
16335 ins_encode %{
16336 __ subv(as_FloatRegister($dst$$reg), __ T8B,
16337 as_FloatRegister($src1$$reg),
16338 as_FloatRegister($src2$$reg));
16339 %}
16340 ins_pipe(vdop64);
16341 %}
16342
16343 instruct vsub16B(vecX dst, vecX src1, vecX src2)
16344 %{
16345 predicate(n->as_Vector()->length() == 16);
16346 match(Set dst (SubVB src1 src2));
16347 ins_cost(INSN_COST);
16348 format %{ "subv $dst,$src1,$src2\t# vector (16B)" %}
16349 ins_encode %{
16350 __ subv(as_FloatRegister($dst$$reg), __ T16B,
16351 as_FloatRegister($src1$$reg),
16352 as_FloatRegister($src2$$reg));
16353 %}
16354 ins_pipe(vdop128);
16355 %}
16356
16357 instruct vsub4S(vecD dst, vecD src1, vecD src2)
16358 %{
16359 predicate(n->as_Vector()->length() == 2 ||
16360 n->as_Vector()->length() == 4);
16361 match(Set dst (SubVS src1 src2));
16362 ins_cost(INSN_COST);
16363 format %{ "subv $dst,$src1,$src2\t# vector (4H)" %}
16364 ins_encode %{
16365 __ subv(as_FloatRegister($dst$$reg), __ T4H,
16366 as_FloatRegister($src1$$reg),
16367 as_FloatRegister($src2$$reg));
16368 %}
16369 ins_pipe(vdop64);
16370 %}
16371
16372 instruct vsub8S(vecX dst, vecX src1, vecX src2)
16373 %{
16374 predicate(n->as_Vector()->length() == 8);
16375 match(Set dst (SubVS src1 src2));
16376 ins_cost(INSN_COST);
16377 format %{ "subv $dst,$src1,$src2\t# vector (8H)" %}
16378 ins_encode %{
16379 __ subv(as_FloatRegister($dst$$reg), __ T8H,
16380 as_FloatRegister($src1$$reg),
16381 as_FloatRegister($src2$$reg));
16382 %}
16383 ins_pipe(vdop128);
16384 %}
16385
16386 instruct vsub2I(vecD dst, vecD src1, vecD src2)
16387 %{
16388 predicate(n->as_Vector()->length() == 2);
16389 match(Set dst (SubVI src1 src2));
16390 ins_cost(INSN_COST);
16391 format %{ "subv $dst,$src1,$src2\t# vector (2S)" %}
16392 ins_encode %{
16393 __ subv(as_FloatRegister($dst$$reg), __ T2S,
16394 as_FloatRegister($src1$$reg),
16395 as_FloatRegister($src2$$reg));
16396 %}
16397 ins_pipe(vdop64);
16398 %}
16399
16400 instruct vsub4I(vecX dst, vecX src1, vecX src2)
16401 %{
16402 predicate(n->as_Vector()->length() == 4);
16403 match(Set dst (SubVI src1 src2));
16404 ins_cost(INSN_COST);
16405 format %{ "subv $dst,$src1,$src2\t# vector (4S)" %}
16406 ins_encode %{
16407 __ subv(as_FloatRegister($dst$$reg), __ T4S,
16408 as_FloatRegister($src1$$reg),
16409 as_FloatRegister($src2$$reg));
16410 %}
16411 ins_pipe(vdop128);
16412 %}
16413
16414 instruct vsub2L(vecX dst, vecX src1, vecX src2)
16415 %{
16416 predicate(n->as_Vector()->length() == 2);
16417 match(Set dst (SubVL src1 src2));
16418 ins_cost(INSN_COST);
16419 format %{ "subv $dst,$src1,$src2\t# vector (2L)" %}
16420 ins_encode %{
16421 __ subv(as_FloatRegister($dst$$reg), __ T2D,
16422 as_FloatRegister($src1$$reg),
16423 as_FloatRegister($src2$$reg));
16424 %}
16425 ins_pipe(vdop128);
16426 %}
16427
16428 instruct vsub2F(vecD dst, vecD src1, vecD src2)
16429 %{
16430 predicate(n->as_Vector()->length() == 2);
16431 match(Set dst (SubVF src1 src2));
16432 ins_cost(INSN_COST);
16433 format %{ "fsub $dst,$src1,$src2\t# vector (2S)" %}
16434 ins_encode %{
16435 __ fsub(as_FloatRegister($dst$$reg), __ T2S,
16436 as_FloatRegister($src1$$reg),
16437 as_FloatRegister($src2$$reg));
16438 %}
16439 ins_pipe(vdop_fp64);
16440 %}
16441
16442 instruct vsub4F(vecX dst, vecX src1, vecX src2)
16443 %{
16444 predicate(n->as_Vector()->length() == 4);
16445 match(Set dst (SubVF src1 src2));
16446 ins_cost(INSN_COST);
16447 format %{ "fsub $dst,$src1,$src2\t# vector (4S)" %}
16448 ins_encode %{
16449 __ fsub(as_FloatRegister($dst$$reg), __ T4S,
16450 as_FloatRegister($src1$$reg),
16451 as_FloatRegister($src2$$reg));
16452 %}
16453 ins_pipe(vdop_fp128);
16454 %}
16455
16456 instruct vsub2D(vecX dst, vecX src1, vecX src2)
16457 %{
16458 predicate(n->as_Vector()->length() == 2);
16459 match(Set dst (SubVD src1 src2));
16460 ins_cost(INSN_COST);
16461 format %{ "fsub $dst,$src1,$src2\t# vector (2D)" %}
16462 ins_encode %{
16463 __ fsub(as_FloatRegister($dst$$reg), __ T2D,
16464 as_FloatRegister($src1$$reg),
16465 as_FloatRegister($src2$$reg));
16466 %}
16467 ins_pipe(vdop_fp128);
16468 %}
16469
16470 // --------------------------------- MUL --------------------------------------
16471
16472 instruct vmul4S(vecD dst, vecD src1, vecD src2)
16473 %{
16474 predicate(n->as_Vector()->length() == 2 ||
16475 n->as_Vector()->length() == 4);
16476 match(Set dst (MulVS src1 src2));
16477 ins_cost(INSN_COST);
16478 format %{ "mulv $dst,$src1,$src2\t# vector (4H)" %}
16479 ins_encode %{
16480 __ mulv(as_FloatRegister($dst$$reg), __ T4H,
16481 as_FloatRegister($src1$$reg),
16482 as_FloatRegister($src2$$reg));
16483 %}
16484 ins_pipe(vmul64);
16485 %}
16486
16487 instruct vmul8S(vecX dst, vecX src1, vecX src2)
16488 %{
16489 predicate(n->as_Vector()->length() == 8);
16490 match(Set dst (MulVS src1 src2));
16491 ins_cost(INSN_COST);
16492 format %{ "mulv $dst,$src1,$src2\t# vector (8H)" %}
16493 ins_encode %{
16494 __ mulv(as_FloatRegister($dst$$reg), __ T8H,
16495 as_FloatRegister($src1$$reg),
16496 as_FloatRegister($src2$$reg));
16497 %}
16498 ins_pipe(vmul128);
16499 %}
16500
16501 instruct vmul2I(vecD dst, vecD src1, vecD src2)
16502 %{
16503 predicate(n->as_Vector()->length() == 2);
16504 match(Set dst (MulVI src1 src2));
16505 ins_cost(INSN_COST);
16506 format %{ "mulv $dst,$src1,$src2\t# vector (2S)" %}
16507 ins_encode %{
16508 __ mulv(as_FloatRegister($dst$$reg), __ T2S,
16509 as_FloatRegister($src1$$reg),
16510 as_FloatRegister($src2$$reg));
16511 %}
16512 ins_pipe(vmul64);
16513 %}
16514
16515 instruct vmul4I(vecX dst, vecX src1, vecX src2)
16516 %{
16517 predicate(n->as_Vector()->length() == 4);
16518 match(Set dst (MulVI src1 src2));
16519 ins_cost(INSN_COST);
16520 format %{ "mulv $dst,$src1,$src2\t# vector (4S)" %}
16521 ins_encode %{
16522 __ mulv(as_FloatRegister($dst$$reg), __ T4S,
16523 as_FloatRegister($src1$$reg),
16524 as_FloatRegister($src2$$reg));
16525 %}
16526 ins_pipe(vmul128);
16527 %}
16528
16529 instruct vmul2F(vecD dst, vecD src1, vecD src2)
16530 %{
16531 predicate(n->as_Vector()->length() == 2);
16532 match(Set dst (MulVF src1 src2));
16533 ins_cost(INSN_COST);
16534 format %{ "fmul $dst,$src1,$src2\t# vector (2S)" %}
16535 ins_encode %{
16536 __ fmul(as_FloatRegister($dst$$reg), __ T2S,
16537 as_FloatRegister($src1$$reg),
16538 as_FloatRegister($src2$$reg));
16539 %}
16540 ins_pipe(vmuldiv_fp64);
16541 %}
16542
16543 instruct vmul4F(vecX dst, vecX src1, vecX src2)
16544 %{
16545 predicate(n->as_Vector()->length() == 4);
16546 match(Set dst (MulVF src1 src2));
16547 ins_cost(INSN_COST);
16548 format %{ "fmul $dst,$src1,$src2\t# vector (4S)" %}
16549 ins_encode %{
16550 __ fmul(as_FloatRegister($dst$$reg), __ T4S,
16551 as_FloatRegister($src1$$reg),
16552 as_FloatRegister($src2$$reg));
16553 %}
16554 ins_pipe(vmuldiv_fp128);
16555 %}
16556
16557 instruct vmul2D(vecX dst, vecX src1, vecX src2)
16558 %{
16559 predicate(n->as_Vector()->length() == 2);
16560 match(Set dst (MulVD src1 src2));
16561 ins_cost(INSN_COST);
16562 format %{ "fmul $dst,$src1,$src2\t# vector (2D)" %}
16563 ins_encode %{
16564 __ fmul(as_FloatRegister($dst$$reg), __ T2D,
16565 as_FloatRegister($src1$$reg),
16566 as_FloatRegister($src2$$reg));
16567 %}
16568 ins_pipe(vmuldiv_fp128);
16569 %}
16570
16571 // --------------------------------- MLA --------------------------------------
16572
16573 instruct vmla4S(vecD dst, vecD src1, vecD src2)
16574 %{
16575 predicate(n->as_Vector()->length() == 2 ||
16576 n->as_Vector()->length() == 4);
16577 match(Set dst (AddVS dst (MulVS src1 src2)));
16578 ins_cost(INSN_COST);
16579 format %{ "mlav $dst,$src1,$src2\t# vector (4H)" %}
16580 ins_encode %{
16581 __ mlav(as_FloatRegister($dst$$reg), __ T4H,
16582 as_FloatRegister($src1$$reg),
16583 as_FloatRegister($src2$$reg));
16584 %}
16585 ins_pipe(vmla64);
16586 %}
16587
16588 instruct vmla8S(vecX dst, vecX src1, vecX src2)
16589 %{
16590 predicate(n->as_Vector()->length() == 8);
16591 match(Set dst (AddVS dst (MulVS src1 src2)));
16592 ins_cost(INSN_COST);
16593 format %{ "mlav $dst,$src1,$src2\t# vector (8H)" %}
16594 ins_encode %{
16595 __ mlav(as_FloatRegister($dst$$reg), __ T8H,
16596 as_FloatRegister($src1$$reg),
16597 as_FloatRegister($src2$$reg));
16598 %}
16599 ins_pipe(vmla128);
16600 %}
16601
16602 instruct vmla2I(vecD dst, vecD src1, vecD src2)
16603 %{
16604 predicate(n->as_Vector()->length() == 2);
16605 match(Set dst (AddVI dst (MulVI src1 src2)));
16606 ins_cost(INSN_COST);
16607 format %{ "mlav $dst,$src1,$src2\t# vector (2S)" %}
16608 ins_encode %{
16609 __ mlav(as_FloatRegister($dst$$reg), __ T2S,
16610 as_FloatRegister($src1$$reg),
16611 as_FloatRegister($src2$$reg));
16612 %}
16613 ins_pipe(vmla64);
16614 %}
16615
16616 instruct vmla4I(vecX dst, vecX src1, vecX src2)
16617 %{
16618 predicate(n->as_Vector()->length() == 4);
16619 match(Set dst (AddVI dst (MulVI src1 src2)));
16620 ins_cost(INSN_COST);
16621 format %{ "mlav $dst,$src1,$src2\t# vector (4S)" %}
16622 ins_encode %{
16623 __ mlav(as_FloatRegister($dst$$reg), __ T4S,
16624 as_FloatRegister($src1$$reg),
16625 as_FloatRegister($src2$$reg));
16626 %}
16627 ins_pipe(vmla128);
16628 %}
16629
16630 // --------------------------------- MLS --------------------------------------
16631
16632 instruct vmls4S(vecD dst, vecD src1, vecD src2)
16633 %{
16634 predicate(n->as_Vector()->length() == 2 ||
16635 n->as_Vector()->length() == 4);
16636 match(Set dst (SubVS dst (MulVS src1 src2)));
16637 ins_cost(INSN_COST);
16638 format %{ "mlsv $dst,$src1,$src2\t# vector (4H)" %}
16639 ins_encode %{
16640 __ mlsv(as_FloatRegister($dst$$reg), __ T4H,
16641 as_FloatRegister($src1$$reg),
16642 as_FloatRegister($src2$$reg));
16643 %}
16644 ins_pipe(vmla64);
16645 %}
16646
16647 instruct vmls8S(vecX dst, vecX src1, vecX src2)
16648 %{
16649 predicate(n->as_Vector()->length() == 8);
16650 match(Set dst (SubVS dst (MulVS src1 src2)));
16651 ins_cost(INSN_COST);
16652 format %{ "mlsv $dst,$src1,$src2\t# vector (8H)" %}
16653 ins_encode %{
16654 __ mlsv(as_FloatRegister($dst$$reg), __ T8H,
16655 as_FloatRegister($src1$$reg),
16656 as_FloatRegister($src2$$reg));
16657 %}
16658 ins_pipe(vmla128);
16659 %}
16660
16661 instruct vmls2I(vecD dst, vecD src1, vecD src2)
16662 %{
16663 predicate(n->as_Vector()->length() == 2);
16664 match(Set dst (SubVI dst (MulVI src1 src2)));
16665 ins_cost(INSN_COST);
16666 format %{ "mlsv $dst,$src1,$src2\t# vector (2S)" %}
16667 ins_encode %{
16668 __ mlsv(as_FloatRegister($dst$$reg), __ T2S,
16669 as_FloatRegister($src1$$reg),
16670 as_FloatRegister($src2$$reg));
16671 %}
16672 ins_pipe(vmla64);
16673 %}
16674
16675 instruct vmls4I(vecX dst, vecX src1, vecX src2)
16676 %{
16677 predicate(n->as_Vector()->length() == 4);
16678 match(Set dst (SubVI dst (MulVI src1 src2)));
16679 ins_cost(INSN_COST);
16680 format %{ "mlsv $dst,$src1,$src2\t# vector (4S)" %}
16681 ins_encode %{
16682 __ mlsv(as_FloatRegister($dst$$reg), __ T4S,
16683 as_FloatRegister($src1$$reg),
16684 as_FloatRegister($src2$$reg));
16685 %}
16686 ins_pipe(vmla128);
16687 %}
16688
16689 // --------------------------------- DIV --------------------------------------
16690
16691 instruct vdiv2F(vecD dst, vecD src1, vecD src2)
16692 %{
16693 predicate(n->as_Vector()->length() == 2);
16694 match(Set dst (DivVF src1 src2));
16695 ins_cost(INSN_COST);
16696 format %{ "fdiv $dst,$src1,$src2\t# vector (2S)" %}
16697 ins_encode %{
16698 __ fdiv(as_FloatRegister($dst$$reg), __ T2S,
16699 as_FloatRegister($src1$$reg),
16700 as_FloatRegister($src2$$reg));
16701 %}
16702 ins_pipe(vmuldiv_fp64);
16703 %}
16704
16705 instruct vdiv4F(vecX dst, vecX src1, vecX src2)
16706 %{
16707 predicate(n->as_Vector()->length() == 4);
16708 match(Set dst (DivVF src1 src2));
16709 ins_cost(INSN_COST);
16710 format %{ "fdiv $dst,$src1,$src2\t# vector (4S)" %}
16711 ins_encode %{
16712 __ fdiv(as_FloatRegister($dst$$reg), __ T4S,
16713 as_FloatRegister($src1$$reg),
16714 as_FloatRegister($src2$$reg));
16715 %}
16716 ins_pipe(vmuldiv_fp128);
16717 %}
16718
16719 instruct vdiv2D(vecX dst, vecX src1, vecX src2)
16720 %{
16721 predicate(n->as_Vector()->length() == 2);
16722 match(Set dst (DivVD src1 src2));
16723 ins_cost(INSN_COST);
16724 format %{ "fdiv $dst,$src1,$src2\t# vector (2D)" %}
16725 ins_encode %{
16726 __ fdiv(as_FloatRegister($dst$$reg), __ T2D,
16727 as_FloatRegister($src1$$reg),
16728 as_FloatRegister($src2$$reg));
16729 %}
16730 ins_pipe(vmuldiv_fp128);
16731 %}
16732
16733 // --------------------------------- SQRT -------------------------------------
16734
16735 instruct vsqrt2D(vecX dst, vecX src)
16736 %{
16737 predicate(n->as_Vector()->length() == 2);
16738 match(Set dst (SqrtVD src));
16739 format %{ "fsqrt $dst, $src\t# vector (2D)" %}
16740 ins_encode %{
16741 __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
16742 as_FloatRegister($src$$reg));
16743 %}
16744 ins_pipe(vsqrt_fp128);
16745 %}
16746
16747 // --------------------------------- ABS --------------------------------------
16748
16749 instruct vabs2F(vecD dst, vecD src)
16750 %{
16751 predicate(n->as_Vector()->length() == 2);
16752 match(Set dst (AbsVF src));
16753 ins_cost(INSN_COST * 3);
16754 format %{ "fabs $dst,$src\t# vector (2S)" %}
16755 ins_encode %{
16756 __ fabs(as_FloatRegister($dst$$reg), __ T2S,
16757 as_FloatRegister($src$$reg));
16758 %}
16759 ins_pipe(vunop_fp64);
16760 %}
16761
16762 instruct vabs4F(vecX dst, vecX src)
16763 %{
16764 predicate(n->as_Vector()->length() == 4);
16765 match(Set dst (AbsVF src));
16766 ins_cost(INSN_COST * 3);
16767 format %{ "fabs $dst,$src\t# vector (4S)" %}
16768 ins_encode %{
16769 __ fabs(as_FloatRegister($dst$$reg), __ T4S,
16770 as_FloatRegister($src$$reg));
16771 %}
16772 ins_pipe(vunop_fp128);
16773 %}
16774
16775 instruct vabs2D(vecX dst, vecX src)
16776 %{
16777 predicate(n->as_Vector()->length() == 2);
16778 match(Set dst (AbsVD src));
16779 ins_cost(INSN_COST * 3);
16780 format %{ "fabs $dst,$src\t# vector (2D)" %}
16781 ins_encode %{
16782 __ fabs(as_FloatRegister($dst$$reg), __ T2D,
16783 as_FloatRegister($src$$reg));
16784 %}
16785 ins_pipe(vunop_fp128);
16786 %}
16787
16788 // --------------------------------- NEG --------------------------------------
16789
16790 instruct vneg2F(vecD dst, vecD src)
16791 %{
16792 predicate(n->as_Vector()->length() == 2);
16793 match(Set dst (NegVF src));
16794 ins_cost(INSN_COST * 3);
16795 format %{ "fneg $dst,$src\t# vector (2S)" %}
16796 ins_encode %{
16797 __ fneg(as_FloatRegister($dst$$reg), __ T2S,
16798 as_FloatRegister($src$$reg));
16799 %}
16800 ins_pipe(vunop_fp64);
16801 %}
16802
16803 instruct vneg4F(vecX dst, vecX src)
16804 %{
16805 predicate(n->as_Vector()->length() == 4);
16806 match(Set dst (NegVF src));
16807 ins_cost(INSN_COST * 3);
16808 format %{ "fneg $dst,$src\t# vector (4S)" %}
16809 ins_encode %{
16810 __ fneg(as_FloatRegister($dst$$reg), __ T4S,
16811 as_FloatRegister($src$$reg));
16812 %}
16813 ins_pipe(vunop_fp128);
16814 %}
16815
16816 instruct vneg2D(vecX dst, vecX src)
16817 %{
16818 predicate(n->as_Vector()->length() == 2);
16819 match(Set dst (NegVD src));
16820 ins_cost(INSN_COST * 3);
16821 format %{ "fneg $dst,$src\t# vector (2D)" %}
16822 ins_encode %{
16823 __ fneg(as_FloatRegister($dst$$reg), __ T2D,
16824 as_FloatRegister($src$$reg));
16825 %}
16826 ins_pipe(vunop_fp128);
16827 %}
16828
16829 // --------------------------------- AND --------------------------------------
16830
16831 instruct vand8B(vecD dst, vecD src1, vecD src2)
16832 %{
16833 predicate(n->as_Vector()->length_in_bytes() == 4 ||
16834 n->as_Vector()->length_in_bytes() == 8);
16835 match(Set dst (AndV src1 src2));
16836 ins_cost(INSN_COST);
16837 format %{ "and $dst,$src1,$src2\t# vector (8B)" %}
16838 ins_encode %{
16839 __ andr(as_FloatRegister($dst$$reg), __ T8B,
16840 as_FloatRegister($src1$$reg),
16841 as_FloatRegister($src2$$reg));
16842 %}
16843 ins_pipe(vlogical64);
16844 %}
16845
16846 instruct vand16B(vecX dst, vecX src1, vecX src2)
16847 %{
16848 predicate(n->as_Vector()->length_in_bytes() == 16);
16849 match(Set dst (AndV src1 src2));
16850 ins_cost(INSN_COST);
16851 format %{ "and $dst,$src1,$src2\t# vector (16B)" %}
16852 ins_encode %{
16853 __ andr(as_FloatRegister($dst$$reg), __ T16B,
16854 as_FloatRegister($src1$$reg),
16855 as_FloatRegister($src2$$reg));
16856 %}
16857 ins_pipe(vlogical128);
16858 %}
16859
16860 // --------------------------------- OR ---------------------------------------
16861
16862 instruct vor8B(vecD dst, vecD src1, vecD src2)
16863 %{
16864 predicate(n->as_Vector()->length_in_bytes() == 4 ||
16865 n->as_Vector()->length_in_bytes() == 8);
16866 match(Set dst (OrV src1 src2));
16867 ins_cost(INSN_COST);
16868 format %{ "and $dst,$src1,$src2\t# vector (8B)" %}
16869 ins_encode %{
16870 __ orr(as_FloatRegister($dst$$reg), __ T8B,
16871 as_FloatRegister($src1$$reg),
16872 as_FloatRegister($src2$$reg));
16873 %}
16874 ins_pipe(vlogical64);
16875 %}
16876
16877 instruct vor16B(vecX dst, vecX src1, vecX src2)
16878 %{
16879 predicate(n->as_Vector()->length_in_bytes() == 16);
16880 match(Set dst (OrV src1 src2));
16881 ins_cost(INSN_COST);
16882 format %{ "orr $dst,$src1,$src2\t# vector (16B)" %}
16883 ins_encode %{
16884 __ orr(as_FloatRegister($dst$$reg), __ T16B,
16885 as_FloatRegister($src1$$reg),
16886 as_FloatRegister($src2$$reg));
16887 %}
16888 ins_pipe(vlogical128);
16889 %}
16890
16891 // --------------------------------- XOR --------------------------------------
16892
16893 instruct vxor8B(vecD dst, vecD src1, vecD src2)
16894 %{
16895 predicate(n->as_Vector()->length_in_bytes() == 4 ||
16896 n->as_Vector()->length_in_bytes() == 8);
16897 match(Set dst (XorV src1 src2));
16898 ins_cost(INSN_COST);
16899 format %{ "xor $dst,$src1,$src2\t# vector (8B)" %}
16900 ins_encode %{
16901 __ eor(as_FloatRegister($dst$$reg), __ T8B,
16902 as_FloatRegister($src1$$reg),
16903 as_FloatRegister($src2$$reg));
16904 %}
16905 ins_pipe(vlogical64);
16906 %}
16907
16908 instruct vxor16B(vecX dst, vecX src1, vecX src2)
16909 %{
16910 predicate(n->as_Vector()->length_in_bytes() == 16);
16911 match(Set dst (XorV src1 src2));
16912 ins_cost(INSN_COST);
16913 format %{ "xor $dst,$src1,$src2\t# vector (16B)" %}
16914 ins_encode %{
16915 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16916 as_FloatRegister($src1$$reg),
16917 as_FloatRegister($src2$$reg));
16918 %}
16919 ins_pipe(vlogical128);
16920 %}
16921
16922 // ------------------------------ Shift ---------------------------------------
16923
16924 instruct vshiftcntL(vecX dst, iRegIorL2I cnt) %{
16925 match(Set dst (LShiftCntV cnt));
16926 format %{ "dup $dst, $cnt\t# shift count (vecX)" %}
16927 ins_encode %{
16928 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
16929 %}
16930 ins_pipe(vdup_reg_reg128);
16931 %}
16932
16933 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount
16934 instruct vshiftcntR(vecX dst, iRegIorL2I cnt) %{
16935 match(Set dst (RShiftCntV cnt));
16936 format %{ "dup $dst, $cnt\t# shift count (vecX)\n\tneg $dst, $dst\t T16B" %}
16937 ins_encode %{
16938 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
16939 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
16940 %}
16941 ins_pipe(vdup_reg_reg128);
16942 %}
16943
16944 instruct vsll8B(vecD dst, vecD src, vecX shift) %{
16945 predicate(n->as_Vector()->length() == 4 ||
16946 n->as_Vector()->length() == 8);
16947 match(Set dst (LShiftVB src shift));
16948 match(Set dst (RShiftVB src shift));
16949 ins_cost(INSN_COST);
16950 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %}
16951 ins_encode %{
16952 __ sshl(as_FloatRegister($dst$$reg), __ T8B,
16953 as_FloatRegister($src$$reg),
16954 as_FloatRegister($shift$$reg));
16955 %}
16956 ins_pipe(vshift64);
16957 %}
16958
16959 instruct vsll16B(vecX dst, vecX src, vecX shift) %{
16960 predicate(n->as_Vector()->length() == 16);
16961 match(Set dst (LShiftVB src shift));
16962 match(Set dst (RShiftVB src shift));
16963 ins_cost(INSN_COST);
16964 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %}
16965 ins_encode %{
16966 __ sshl(as_FloatRegister($dst$$reg), __ T16B,
16967 as_FloatRegister($src$$reg),
16968 as_FloatRegister($shift$$reg));
16969 %}
16970 ins_pipe(vshift128);
16971 %}
16972
16973 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{
16974 predicate(n->as_Vector()->length() == 4 ||
16975 n->as_Vector()->length() == 8);
16976 match(Set dst (URShiftVB src shift));
16977 ins_cost(INSN_COST);
16978 format %{ "ushl $dst,$src,$shift\t# vector (8B)" %}
16979 ins_encode %{
16980 __ ushl(as_FloatRegister($dst$$reg), __ T8B,
16981 as_FloatRegister($src$$reg),
16982 as_FloatRegister($shift$$reg));
16983 %}
16984 ins_pipe(vshift64);
16985 %}
16986
16987 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{
16988 predicate(n->as_Vector()->length() == 16);
16989 match(Set dst (URShiftVB src shift));
16990 ins_cost(INSN_COST);
16991 format %{ "ushl $dst,$src,$shift\t# vector (16B)" %}
16992 ins_encode %{
16993 __ ushl(as_FloatRegister($dst$$reg), __ T16B,
16994 as_FloatRegister($src$$reg),
16995 as_FloatRegister($shift$$reg));
16996 %}
16997 ins_pipe(vshift128);
16998 %}
16999
17000 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{
17001 predicate(n->as_Vector()->length() == 4 ||
17002 n->as_Vector()->length() == 8);
17003 match(Set dst (LShiftVB src shift));
17004 ins_cost(INSN_COST);
17005 format %{ "shl $dst, $src, $shift\t# vector (8B)" %}
17006 ins_encode %{
17007 int sh = (int)$shift$$constant & 31;
17008 if (sh >= 8) {
17009 __ eor(as_FloatRegister($dst$$reg), __ T8B,
17010 as_FloatRegister($src$$reg),
17011 as_FloatRegister($src$$reg));
17012 } else {
17013 __ shl(as_FloatRegister($dst$$reg), __ T8B,
17014 as_FloatRegister($src$$reg), sh);
17015 }
17016 %}
17017 ins_pipe(vshift64_imm);
17018 %}
17019
17020 instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
17021 predicate(n->as_Vector()->length() == 16);
17022 match(Set dst (LShiftVB src shift));
17023 ins_cost(INSN_COST);
17024 format %{ "shl $dst, $src, $shift\t# vector (16B)" %}
17025 ins_encode %{
17026 int sh = (int)$shift$$constant & 31;
17027 if (sh >= 8) {
17028 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17029 as_FloatRegister($src$$reg),
17030 as_FloatRegister($src$$reg));
17031 } else {
17032 __ shl(as_FloatRegister($dst$$reg), __ T16B,
17033 as_FloatRegister($src$$reg), sh);
17034 }
17035 %}
17036 ins_pipe(vshift128_imm);
17037 %}
17038
17039 instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
17040 predicate(n->as_Vector()->length() == 4 ||
17041 n->as_Vector()->length() == 8);
17042 match(Set dst (RShiftVB src shift));
17043 ins_cost(INSN_COST);
17044 format %{ "sshr $dst, $src, $shift\t# vector (8B)" %}
17045 ins_encode %{
17046 int sh = (int)$shift$$constant & 31;
17047 if (sh >= 8) sh = 7;
17048 sh = -sh & 7;
17049 __ sshr(as_FloatRegister($dst$$reg), __ T8B,
17050 as_FloatRegister($src$$reg), sh);
17051 %}
17052 ins_pipe(vshift64_imm);
17053 %}
17054
17055 instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
17056 predicate(n->as_Vector()->length() == 16);
17057 match(Set dst (RShiftVB src shift));
17058 ins_cost(INSN_COST);
17059 format %{ "sshr $dst, $src, $shift\t# vector (16B)" %}
17060 ins_encode %{
17061 int sh = (int)$shift$$constant & 31;
17062 if (sh >= 8) sh = 7;
17063 sh = -sh & 7;
17064 __ sshr(as_FloatRegister($dst$$reg), __ T16B,
17065 as_FloatRegister($src$$reg), sh);
17066 %}
17067 ins_pipe(vshift128_imm);
17068 %}
17069
17070 instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
17071 predicate(n->as_Vector()->length() == 4 ||
17072 n->as_Vector()->length() == 8);
17073 match(Set dst (URShiftVB src shift));
17074 ins_cost(INSN_COST);
17075 format %{ "ushr $dst, $src, $shift\t# vector (8B)" %}
17076 ins_encode %{
17077 int sh = (int)$shift$$constant & 31;
17078 if (sh >= 8) {
17079 __ eor(as_FloatRegister($dst$$reg), __ T8B,
17080 as_FloatRegister($src$$reg),
17081 as_FloatRegister($src$$reg));
17082 } else {
17083 __ ushr(as_FloatRegister($dst$$reg), __ T8B,
17084 as_FloatRegister($src$$reg), -sh & 7);
17085 }
17086 %}
17087 ins_pipe(vshift64_imm);
17088 %}
17089
17090 instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
17091 predicate(n->as_Vector()->length() == 16);
17092 match(Set dst (URShiftVB src shift));
17093 ins_cost(INSN_COST);
17094 format %{ "ushr $dst, $src, $shift\t# vector (16B)" %}
17095 ins_encode %{
17096 int sh = (int)$shift$$constant & 31;
17097 if (sh >= 8) {
17098 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17099 as_FloatRegister($src$$reg),
17100 as_FloatRegister($src$$reg));
17101 } else {
17102 __ ushr(as_FloatRegister($dst$$reg), __ T16B,
17103 as_FloatRegister($src$$reg), -sh & 7);
17104 }
17105 %}
17106 ins_pipe(vshift128_imm);
17107 %}
17108
17109 instruct vsll4S(vecD dst, vecD src, vecX shift) %{
17110 predicate(n->as_Vector()->length() == 2 ||
17111 n->as_Vector()->length() == 4);
17112 match(Set dst (LShiftVS src shift));
17113 match(Set dst (RShiftVS src shift));
17114 ins_cost(INSN_COST);
17115 format %{ "sshl $dst,$src,$shift\t# vector (4H)" %}
17116 ins_encode %{
17117 __ sshl(as_FloatRegister($dst$$reg), __ T4H,
17118 as_FloatRegister($src$$reg),
17119 as_FloatRegister($shift$$reg));
17120 %}
17121 ins_pipe(vshift64);
17122 %}
17123
17124 instruct vsll8S(vecX dst, vecX src, vecX shift) %{
17125 predicate(n->as_Vector()->length() == 8);
17126 match(Set dst (LShiftVS src shift));
17127 match(Set dst (RShiftVS src shift));
17128 ins_cost(INSN_COST);
17129 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %}
17130 ins_encode %{
17131 __ sshl(as_FloatRegister($dst$$reg), __ T8H,
17132 as_FloatRegister($src$$reg),
17133 as_FloatRegister($shift$$reg));
17134 %}
17135 ins_pipe(vshift128);
17136 %}
17137
17138 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{
17139 predicate(n->as_Vector()->length() == 2 ||
17140 n->as_Vector()->length() == 4);
17141 match(Set dst (URShiftVS src shift));
17142 ins_cost(INSN_COST);
17143 format %{ "ushl $dst,$src,$shift\t# vector (4H)" %}
17144 ins_encode %{
17145 __ ushl(as_FloatRegister($dst$$reg), __ T4H,
17146 as_FloatRegister($src$$reg),
17147 as_FloatRegister($shift$$reg));
17148 %}
17149 ins_pipe(vshift64);
17150 %}
17151
17152 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{
17153 predicate(n->as_Vector()->length() == 8);
17154 match(Set dst (URShiftVS src shift));
17155 ins_cost(INSN_COST);
17156 format %{ "ushl $dst,$src,$shift\t# vector (8H)" %}
17157 ins_encode %{
17158 __ ushl(as_FloatRegister($dst$$reg), __ T8H,
17159 as_FloatRegister($src$$reg),
17160 as_FloatRegister($shift$$reg));
17161 %}
17162 ins_pipe(vshift128);
17163 %}
17164
17165 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{
17166 predicate(n->as_Vector()->length() == 2 ||
17167 n->as_Vector()->length() == 4);
17168 match(Set dst (LShiftVS src shift));
17169 ins_cost(INSN_COST);
17170 format %{ "shl $dst, $src, $shift\t# vector (4H)" %}
17171 ins_encode %{
17172 int sh = (int)$shift$$constant & 31;
17173 if (sh >= 16) {
17174 __ eor(as_FloatRegister($dst$$reg), __ T8B,
17175 as_FloatRegister($src$$reg),
17176 as_FloatRegister($src$$reg));
17177 } else {
17178 __ shl(as_FloatRegister($dst$$reg), __ T4H,
17179 as_FloatRegister($src$$reg), sh);
17180 }
17181 %}
17182 ins_pipe(vshift64_imm);
17183 %}
17184
17185 instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
17186 predicate(n->as_Vector()->length() == 8);
17187 match(Set dst (LShiftVS src shift));
17188 ins_cost(INSN_COST);
17189 format %{ "shl $dst, $src, $shift\t# vector (8H)" %}
17190 ins_encode %{
17191 int sh = (int)$shift$$constant & 31;
17192 if (sh >= 16) {
17193 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17194 as_FloatRegister($src$$reg),
17195 as_FloatRegister($src$$reg));
17196 } else {
17197 __ shl(as_FloatRegister($dst$$reg), __ T8H,
17198 as_FloatRegister($src$$reg), sh);
17199 }
17200 %}
17201 ins_pipe(vshift128_imm);
17202 %}
17203
17204 instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
17205 predicate(n->as_Vector()->length() == 2 ||
17206 n->as_Vector()->length() == 4);
17207 match(Set dst (RShiftVS src shift));
17208 ins_cost(INSN_COST);
17209 format %{ "sshr $dst, $src, $shift\t# vector (4H)" %}
17210 ins_encode %{
17211 int sh = (int)$shift$$constant & 31;
17212 if (sh >= 16) sh = 15;
17213 sh = -sh & 15;
17214 __ sshr(as_FloatRegister($dst$$reg), __ T4H,
17215 as_FloatRegister($src$$reg), sh);
17216 %}
17217 ins_pipe(vshift64_imm);
17218 %}
17219
17220 instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
17221 predicate(n->as_Vector()->length() == 8);
17222 match(Set dst (RShiftVS src shift));
17223 ins_cost(INSN_COST);
17224 format %{ "sshr $dst, $src, $shift\t# vector (8H)" %}
17225 ins_encode %{
17226 int sh = (int)$shift$$constant & 31;
17227 if (sh >= 16) sh = 15;
17228 sh = -sh & 15;
17229 __ sshr(as_FloatRegister($dst$$reg), __ T8H,
17230 as_FloatRegister($src$$reg), sh);
17231 %}
17232 ins_pipe(vshift128_imm);
17233 %}
17234
17235 instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
17236 predicate(n->as_Vector()->length() == 2 ||
17237 n->as_Vector()->length() == 4);
17238 match(Set dst (URShiftVS src shift));
17239 ins_cost(INSN_COST);
17240 format %{ "ushr $dst, $src, $shift\t# vector (4H)" %}
17241 ins_encode %{
17242 int sh = (int)$shift$$constant & 31;
17243 if (sh >= 16) {
17244 __ eor(as_FloatRegister($dst$$reg), __ T8B,
17245 as_FloatRegister($src$$reg),
17246 as_FloatRegister($src$$reg));
17247 } else {
17248 __ ushr(as_FloatRegister($dst$$reg), __ T4H,
17249 as_FloatRegister($src$$reg), -sh & 15);
17250 }
17251 %}
17252 ins_pipe(vshift64_imm);
17253 %}
17254
17255 instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
17256 predicate(n->as_Vector()->length() == 8);
17257 match(Set dst (URShiftVS src shift));
17258 ins_cost(INSN_COST);
17259 format %{ "ushr $dst, $src, $shift\t# vector (8H)" %}
17260 ins_encode %{
17261 int sh = (int)$shift$$constant & 31;
17262 if (sh >= 16) {
17263 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17264 as_FloatRegister($src$$reg),
17265 as_FloatRegister($src$$reg));
17266 } else {
17267 __ ushr(as_FloatRegister($dst$$reg), __ T8H,
17268 as_FloatRegister($src$$reg), -sh & 15);
17269 }
17270 %}
17271 ins_pipe(vshift128_imm);
17272 %}
17273
17274 instruct vsll2I(vecD dst, vecD src, vecX shift) %{
17275 predicate(n->as_Vector()->length() == 2);
17276 match(Set dst (LShiftVI src shift));
17277 match(Set dst (RShiftVI src shift));
17278 ins_cost(INSN_COST);
17279 format %{ "sshl $dst,$src,$shift\t# vector (2S)" %}
17280 ins_encode %{
17281 __ sshl(as_FloatRegister($dst$$reg), __ T2S,
17282 as_FloatRegister($src$$reg),
17283 as_FloatRegister($shift$$reg));
17284 %}
17285 ins_pipe(vshift64);
17286 %}
17287
17288 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
17289 predicate(n->as_Vector()->length() == 4);
17290 match(Set dst (LShiftVI src shift));
17291 match(Set dst (RShiftVI src shift));
17292 ins_cost(INSN_COST);
17293 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %}
17294 ins_encode %{
17295 __ sshl(as_FloatRegister($dst$$reg), __ T4S,
17296 as_FloatRegister($src$$reg),
17297 as_FloatRegister($shift$$reg));
17298 %}
17299 ins_pipe(vshift128);
17300 %}
17301
17302 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{
17303 predicate(n->as_Vector()->length() == 2);
17304 match(Set dst (URShiftVI src shift));
17305 ins_cost(INSN_COST);
17306 format %{ "ushl $dst,$src,$shift\t# vector (2S)" %}
17307 ins_encode %{
17308 __ ushl(as_FloatRegister($dst$$reg), __ T2S,
17309 as_FloatRegister($src$$reg),
17310 as_FloatRegister($shift$$reg));
17311 %}
17312 ins_pipe(vshift64);
17313 %}
17314
17315 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
17316 predicate(n->as_Vector()->length() == 4);
17317 match(Set dst (URShiftVI src shift));
17318 ins_cost(INSN_COST);
17319 format %{ "ushl $dst,$src,$shift\t# vector (4S)" %}
17320 ins_encode %{
17321 __ ushl(as_FloatRegister($dst$$reg), __ T4S,
17322 as_FloatRegister($src$$reg),
17323 as_FloatRegister($shift$$reg));
17324 %}
17325 ins_pipe(vshift128);
17326 %}
17327
17328 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
17329 predicate(n->as_Vector()->length() == 2);
17330 match(Set dst (LShiftVI src shift));
17331 ins_cost(INSN_COST);
17332 format %{ "shl $dst, $src, $shift\t# vector (2S)" %}
17333 ins_encode %{
17334 __ shl(as_FloatRegister($dst$$reg), __ T2S,
17335 as_FloatRegister($src$$reg),
17336 (int)$shift$$constant & 31);
17337 %}
17338 ins_pipe(vshift64_imm);
17339 %}
17340
17341 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
17342 predicate(n->as_Vector()->length() == 4);
17343 match(Set dst (LShiftVI src shift));
17344 ins_cost(INSN_COST);
17345 format %{ "shl $dst, $src, $shift\t# vector (4S)" %}
17346 ins_encode %{
17347 __ shl(as_FloatRegister($dst$$reg), __ T4S,
17348 as_FloatRegister($src$$reg),
17349 (int)$shift$$constant & 31);
17350 %}
17351 ins_pipe(vshift128_imm);
17352 %}
17353
17354 instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
17355 predicate(n->as_Vector()->length() == 2);
17356 match(Set dst (RShiftVI src shift));
17357 ins_cost(INSN_COST);
17358 format %{ "sshr $dst, $src, $shift\t# vector (2S)" %}
17359 ins_encode %{
17360 __ sshr(as_FloatRegister($dst$$reg), __ T2S,
17361 as_FloatRegister($src$$reg),
17362 -(int)$shift$$constant & 31);
17363 %}
17364 ins_pipe(vshift64_imm);
17365 %}
17366
17367 instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
17368 predicate(n->as_Vector()->length() == 4);
17369 match(Set dst (RShiftVI src shift));
17370 ins_cost(INSN_COST);
17371 format %{ "sshr $dst, $src, $shift\t# vector (4S)" %}
17372 ins_encode %{
17373 __ sshr(as_FloatRegister($dst$$reg), __ T4S,
17374 as_FloatRegister($src$$reg),
17375 -(int)$shift$$constant & 31);
17376 %}
17377 ins_pipe(vshift128_imm);
17378 %}
17379
17380 instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
17381 predicate(n->as_Vector()->length() == 2);
17382 match(Set dst (URShiftVI src shift));
17383 ins_cost(INSN_COST);
17384 format %{ "ushr $dst, $src, $shift\t# vector (2S)" %}
17385 ins_encode %{
17386 __ ushr(as_FloatRegister($dst$$reg), __ T2S,
17387 as_FloatRegister($src$$reg),
17388 -(int)$shift$$constant & 31);
17389 %}
17390 ins_pipe(vshift64_imm);
17391 %}
17392
17393 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
17394 predicate(n->as_Vector()->length() == 4);
17395 match(Set dst (URShiftVI src shift));
17396 ins_cost(INSN_COST);
17397 format %{ "ushr $dst, $src, $shift\t# vector (4S)" %}
17398 ins_encode %{
17399 __ ushr(as_FloatRegister($dst$$reg), __ T4S,
17400 as_FloatRegister($src$$reg),
17401 -(int)$shift$$constant & 31);
17402 %}
17403 ins_pipe(vshift128_imm);
17404 %}
17405
17406 instruct vsll2L(vecX dst, vecX src, vecX shift) %{
17407 predicate(n->as_Vector()->length() == 2);
17408 match(Set dst (LShiftVL src shift));
17409 match(Set dst (RShiftVL src shift));
17410 ins_cost(INSN_COST);
17411 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %}
17412 ins_encode %{
17413 __ sshl(as_FloatRegister($dst$$reg), __ T2D,
17414 as_FloatRegister($src$$reg),
17415 as_FloatRegister($shift$$reg));
17416 %}
17417 ins_pipe(vshift128);
17418 %}
17419
17420 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{
17421 predicate(n->as_Vector()->length() == 2);
17422 match(Set dst (URShiftVL src shift));
17423 ins_cost(INSN_COST);
17424 format %{ "ushl $dst,$src,$shift\t# vector (2D)" %}
17425 ins_encode %{
17426 __ ushl(as_FloatRegister($dst$$reg), __ T2D,
17427 as_FloatRegister($src$$reg),
17428 as_FloatRegister($shift$$reg));
17429 %}
17430 ins_pipe(vshift128);
17431 %}
17432
17433 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
17434 predicate(n->as_Vector()->length() == 2);
17435 match(Set dst (LShiftVL src shift));
17436 ins_cost(INSN_COST);
17437 format %{ "shl $dst, $src, $shift\t# vector (2D)" %}
17438 ins_encode %{
17439 __ shl(as_FloatRegister($dst$$reg), __ T2D,
17440 as_FloatRegister($src$$reg),
17441 (int)$shift$$constant & 63);
17442 %}
17443 ins_pipe(vshift128_imm);
17444 %}
17445
17446 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
17447 predicate(n->as_Vector()->length() == 2);
17448 match(Set dst (RShiftVL src shift));
17449 ins_cost(INSN_COST);
17450 format %{ "sshr $dst, $src, $shift\t# vector (2D)" %}
17451 ins_encode %{
17452 __ sshr(as_FloatRegister($dst$$reg), __ T2D,
17453 as_FloatRegister($src$$reg),
17454 -(int)$shift$$constant & 63);
17455 %}
17456 ins_pipe(vshift128_imm);
17457 %}
17458
17459 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
17460 predicate(n->as_Vector()->length() == 2);
17461 match(Set dst (URShiftVL src shift));
17462 ins_cost(INSN_COST);
17463 format %{ "ushr $dst, $src, $shift\t# vector (2D)" %}
17464 ins_encode %{
17465 __ ushr(as_FloatRegister($dst$$reg), __ T2D,
17466 as_FloatRegister($src$$reg),
17467 -(int)$shift$$constant & 63);
17468 %}
17469 ins_pipe(vshift128_imm);
17470 %}
17471
17472 //----------PEEPHOLE RULES-----------------------------------------------------
17473 // These must follow all instruction definitions as they use the names
17474 // defined in the instructions definitions.
17475 //
17476 // peepmatch ( root_instr_name [preceding_instruction]* );
17477 //
17478 // peepconstraint %{
17479 // (instruction_number.operand_name relational_op instruction_number.operand_name
17480 // [, ...] );
17481 // // instruction numbers are zero-based using left to right order in peepmatch
17482 //
17483 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
17484 // // provide an instruction_number.operand_name for each operand that appears
17485 // // in the replacement instruction's match rule
17486 //
17487 // ---------VM FLAGS---------------------------------------------------------
17488 //
17489 // All peephole optimizations can be turned off using -XX:-OptoPeephole
17490 //
17491 // Each peephole rule is given an identifying number starting with zero and
17492 // increasing by one in the order seen by the parser. An individual peephole
17493 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
17494 // on the command-line.
17495 //
17496 // ---------CURRENT LIMITATIONS----------------------------------------------
17497 //
17498 // Only match adjacent instructions in same basic block
17499 // Only equality constraints
17500 // Only constraints between operands, not (0.dest_reg == RAX_enc)
17501 // Only one replacement instruction
17502 //
17503 // ---------EXAMPLE----------------------------------------------------------
17504 //
17505 // // pertinent parts of existing instructions in architecture description
17506 // instruct movI(iRegINoSp dst, iRegI src)
17507 // %{
17508 // match(Set dst (CopyI src));
17509 // %}
17510 //
17511 // instruct incI_iReg(iRegINoSp dst, immI1 src, rFlagsReg cr)
17512 // %{
17513 // match(Set dst (AddI dst src));
17514 // effect(KILL cr);
17515 // %}
17516 //
17517 // // Change (inc mov) to lea
17518 // peephole %{
17519 // // increment preceeded by register-register move
17520 // peepmatch ( incI_iReg movI );
17521 // // require that the destination register of the increment
17522 // // match the destination register of the move
17523 // peepconstraint ( 0.dst == 1.dst );
17524 // // construct a replacement instruction that sets
17525 // // the destination to ( move's source register + one )
17526 // peepreplace ( leaI_iReg_immI( 0.dst 1.src 0.src ) );
17527 // %}
17528 //
17529
17530 // Implementation no longer uses movX instructions since
17531 // machine-independent system no longer uses CopyX nodes.
17532 //
17533 // peephole
17534 // %{
17535 // peepmatch (incI_iReg movI);
17536 // peepconstraint (0.dst == 1.dst);
17537 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17538 // %}
17539
17540 // peephole
17541 // %{
17542 // peepmatch (decI_iReg movI);
17543 // peepconstraint (0.dst == 1.dst);
17544 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17545 // %}
17546
17547 // peephole
17548 // %{
17549 // peepmatch (addI_iReg_imm movI);
17550 // peepconstraint (0.dst == 1.dst);
17551 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17552 // %}
17553
17554 // peephole
17555 // %{
17556 // peepmatch (incL_iReg movL);
17557 // peepconstraint (0.dst == 1.dst);
17558 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17559 // %}
17560
17561 // peephole
17562 // %{
17563 // peepmatch (decL_iReg movL);
17564 // peepconstraint (0.dst == 1.dst);
17565 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17566 // %}
17567
17568 // peephole
17569 // %{
17570 // peepmatch (addL_iReg_imm movL);
17571 // peepconstraint (0.dst == 1.dst);
17572 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17573 // %}
17574
17575 // peephole
17576 // %{
17577 // peepmatch (addP_iReg_imm movP);
17578 // peepconstraint (0.dst == 1.dst);
17579 // peepreplace (leaP_iReg_imm(0.dst 1.src 0.src));
17580 // %}
17581
17582 // // Change load of spilled value to only a spill
17583 // instruct storeI(memory mem, iRegI src)
17584 // %{
17585 // match(Set mem (StoreI mem src));
17586 // %}
17587 //
17588 // instruct loadI(iRegINoSp dst, memory mem)
17589 // %{
17590 // match(Set dst (LoadI mem));
17591 // %}
17592 //
17593
17594 //----------SMARTSPILL RULES---------------------------------------------------
17595 // These must follow all instruction definitions as they use the names
17596 // defined in the instructions definitions.
17597
17598 // Local Variables:
17599 // mode: c++
17600 // End: