9629
9630 predicate(needs_acquiring_load_exclusive(n));
9631 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
9632 ins_cost(VOLATILE_REF_COST);
9633
9634 effect(KILL cr);
9635
9636 format %{
9637 "cmpxchgw_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
9638 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9639 %}
9640
9641 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
9642 aarch64_enc_cset_eq(res));
9643
9644 ins_pipe(pipe_slow);
9645 %}
9646
9647
9648 // ---------------------------------------------------------------------
9649 // Sundry CAS operations. Note that release is always true,
9650 // regardless of the memory ordering of the CAS. This is because we
9651 // need the volatile case to be sequentially consistent but there is
9652 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
9653 // can't check the type of memory ordering here, so we always emit a
9654 // STLXR.
9655
9656 // This section is generated from aarch64_ad_cas.m4
9657
9658
9659 instruct compareAndExchangeB(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9660 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
9661 ins_cost(2 * VOLATILE_REF_COST);
9662 effect(KILL cr);
9663 format %{
9664 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9665 %}
9666 ins_encode %{
9667 __ uxtbw(rscratch2, $oldval$$Register);
9668 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9669 Assembler::byte, /*acquire*/ false, /*release*/ true,
9670 /*weak*/ false, $res$$Register);
9671 __ sxtbw($res$$Register, $res$$Register);
9672 %}
9673 ins_pipe(pipe_slow);
9674 %}
9675
9676 instruct compareAndExchangeS(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9677 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
9678 ins_cost(2 * VOLATILE_REF_COST);
9679 effect(KILL cr);
9680 format %{
9681 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9682 %}
9683 ins_encode %{
9684 __ uxthw(rscratch2, $oldval$$Register);
9685 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9686 Assembler::halfword, /*acquire*/ false, /*release*/ true,
9687 /*weak*/ false, $res$$Register);
9688 __ sxthw($res$$Register, $res$$Register);
9689 %}
9690 ins_pipe(pipe_slow);
9691 %}
9692
9693 instruct compareAndExchangeI(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
9694 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
9695 ins_cost(2 * VOLATILE_REF_COST);
9696 effect(KILL cr);
9697 format %{
9698 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9699 %}
9700 ins_encode %{
9701 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9702 Assembler::word, /*acquire*/ false, /*release*/ true,
9703 /*weak*/ false, $res$$Register);
9704 %}
9705 ins_pipe(pipe_slow);
9706 %}
9707
9708 instruct compareAndExchangeL(iRegL_R0 res, indirect mem, iRegL_R2 oldval, iRegL_R3 newval, rFlagsReg cr) %{
9709 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
9710 ins_cost(2 * VOLATILE_REF_COST);
9711 effect(KILL cr);
9712 format %{
9713 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9714 %}
9715 ins_encode %{
9716 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9717 Assembler::xword, /*acquire*/ false, /*release*/ true,
9718 /*weak*/ false, $res$$Register);
9719 %}
9720 ins_pipe(pipe_slow);
9721 %}
9722
9723 instruct compareAndExchangeN(iRegN_R0 res, indirect mem, iRegN_R2 oldval, iRegN_R3 newval, rFlagsReg cr) %{
9724 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
9725 ins_cost(2 * VOLATILE_REF_COST);
9726 effect(KILL cr);
9727 format %{
9728 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9729 %}
9730 ins_encode %{
9731 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9732 Assembler::word, /*acquire*/ false, /*release*/ true,
9733 /*weak*/ false, $res$$Register);
9734 %}
9735 ins_pipe(pipe_slow);
9736 %}
9737
9738 instruct compareAndExchangeP(iRegP_R0 res, indirect mem, iRegP_R2 oldval, iRegP_R3 newval, rFlagsReg cr) %{
9739 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
9740 ins_cost(2 * VOLATILE_REF_COST);
9741 effect(KILL cr);
9742 format %{
9743 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9744 %}
9745 ins_encode %{
9746 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9747 Assembler::xword, /*acquire*/ false, /*release*/ true,
9748 /*weak*/ false, $res$$Register);
9749 %}
9750 ins_pipe(pipe_slow);
9751 %}
9752
9753 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9754 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
9755 ins_cost(2 * VOLATILE_REF_COST);
9756 effect(KILL cr);
9757 format %{
9758 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9759 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9760 %}
9761 ins_encode %{
9836 %}
9837 ins_pipe(pipe_slow);
9838 %}
9839
9840 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9841 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
9842 ins_cost(2 * VOLATILE_REF_COST);
9843 effect(KILL cr);
9844 format %{
9845 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9846 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9847 %}
9848 ins_encode %{
9849 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9850 Assembler::xword, /*acquire*/ false, /*release*/ true,
9851 /*weak*/ true, noreg);
9852 __ csetw($res$$Register, Assembler::EQ);
9853 %}
9854 ins_pipe(pipe_slow);
9855 %}
9856 // ---------------------------------------------------------------------
9857
9858 instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
9859 match(Set prev (GetAndSetI mem newv));
9860 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9861 ins_encode %{
9862 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9863 %}
9864 ins_pipe(pipe_serial);
9865 %}
9866
9867 instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
9868 match(Set prev (GetAndSetL mem newv));
9869 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9870 ins_encode %{
9871 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9872 %}
9873 ins_pipe(pipe_serial);
9874 %}
9875
|
9629
9630 predicate(needs_acquiring_load_exclusive(n));
9631 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
9632 ins_cost(VOLATILE_REF_COST);
9633
9634 effect(KILL cr);
9635
9636 format %{
9637 "cmpxchgw_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
9638 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9639 %}
9640
9641 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
9642 aarch64_enc_cset_eq(res));
9643
9644 ins_pipe(pipe_slow);
9645 %}
9646
9647
9648 // ---------------------------------------------------------------------
9649
9650
9651 // BEGIN This section of the file is automatically generated. Do not edit --------------
9652
9653 // Sundry CAS operations. Note that release is always true,
9654 // regardless of the memory ordering of the CAS. This is because we
9655 // need the volatile case to be sequentially consistent but there is
9656 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
9657 // can't check the type of memory ordering here, so we always emit a
9658 // STLXR.
9659
9660 // This section is generated from aarch64_ad_cas.m4
9661
9662
9663
9664 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9665 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
9666 ins_cost(2 * VOLATILE_REF_COST);
9667 effect(TEMP_DEF res, KILL cr);
9668 format %{
9669 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9670 %}
9671 ins_encode %{
9672 __ uxtbw(rscratch2, $oldval$$Register);
9673 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9674 Assembler::byte, /*acquire*/ false, /*release*/ true,
9675 /*weak*/ false, $res$$Register);
9676 __ sxtbw($res$$Register, $res$$Register);
9677 %}
9678 ins_pipe(pipe_slow);
9679 %}
9680
9681 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9682 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
9683 ins_cost(2 * VOLATILE_REF_COST);
9684 effect(TEMP_DEF res, KILL cr);
9685 format %{
9686 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9687 %}
9688 ins_encode %{
9689 __ uxthw(rscratch2, $oldval$$Register);
9690 __ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
9691 Assembler::halfword, /*acquire*/ false, /*release*/ true,
9692 /*weak*/ false, $res$$Register);
9693 __ sxthw($res$$Register, $res$$Register);
9694 %}
9695 ins_pipe(pipe_slow);
9696 %}
9697
9698 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9699 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
9700 ins_cost(2 * VOLATILE_REF_COST);
9701 effect(TEMP_DEF res, KILL cr);
9702 format %{
9703 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9704 %}
9705 ins_encode %{
9706 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9707 Assembler::word, /*acquire*/ false, /*release*/ true,
9708 /*weak*/ false, $res$$Register);
9709 %}
9710 ins_pipe(pipe_slow);
9711 %}
9712
9713 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
9714 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
9715 ins_cost(2 * VOLATILE_REF_COST);
9716 effect(TEMP_DEF res, KILL cr);
9717 format %{
9718 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9719 %}
9720 ins_encode %{
9721 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9722 Assembler::xword, /*acquire*/ false, /*release*/ true,
9723 /*weak*/ false, $res$$Register);
9724 %}
9725 ins_pipe(pipe_slow);
9726 %}
9727
9728 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
9729 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
9730 ins_cost(2 * VOLATILE_REF_COST);
9731 effect(TEMP_DEF res, KILL cr);
9732 format %{
9733 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9734 %}
9735 ins_encode %{
9736 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9737 Assembler::word, /*acquire*/ false, /*release*/ true,
9738 /*weak*/ false, $res$$Register);
9739 %}
9740 ins_pipe(pipe_slow);
9741 %}
9742
9743 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9744 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
9745 ins_cost(2 * VOLATILE_REF_COST);
9746 effect(TEMP_DEF res, KILL cr);
9747 format %{
9748 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9749 %}
9750 ins_encode %{
9751 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9752 Assembler::xword, /*acquire*/ false, /*release*/ true,
9753 /*weak*/ false, $res$$Register);
9754 %}
9755 ins_pipe(pipe_slow);
9756 %}
9757
9758 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9759 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
9760 ins_cost(2 * VOLATILE_REF_COST);
9761 effect(KILL cr);
9762 format %{
9763 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9764 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9765 %}
9766 ins_encode %{
9841 %}
9842 ins_pipe(pipe_slow);
9843 %}
9844
9845 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9846 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
9847 ins_cost(2 * VOLATILE_REF_COST);
9848 effect(KILL cr);
9849 format %{
9850 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9851 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9852 %}
9853 ins_encode %{
9854 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9855 Assembler::xword, /*acquire*/ false, /*release*/ true,
9856 /*weak*/ true, noreg);
9857 __ csetw($res$$Register, Assembler::EQ);
9858 %}
9859 ins_pipe(pipe_slow);
9860 %}
9861
9862 // END This section of the file is automatically generated. Do not edit --------------
9863 // ---------------------------------------------------------------------
9864
9865 instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
9866 match(Set prev (GetAndSetI mem newv));
9867 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9868 ins_encode %{
9869 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9870 %}
9871 ins_pipe(pipe_serial);
9872 %}
9873
9874 instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
9875 match(Set prev (GetAndSetL mem newv));
9876 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9877 ins_encode %{
9878 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9879 %}
9880 ins_pipe(pipe_serial);
9881 %}
9882
|