1600 }
1601
1602
1603 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1604 Register addr = as_reg(op->addr());
1605 Register newval = as_reg(op->new_value());
1606 Register cmpval = as_reg(op->cmp_value());
1607 Register res = op->result_opr()->as_register();
1608
1609 if (op->code() == lir_cas_obj) {
1610 assert(op->tmp1()->is_valid(), "must be");
1611 Register t1 = op->tmp1()->as_register();
1612 if (UseCompressedOops) {
1613 if (UseShenandoahGC) {
1614 __ encode_heap_oop(t1, cmpval);
1615 cmpval = t1;
1616 assert(op->tmp2()->is_valid(), "must be");
1617 Register t2 = op->tmp2()->as_register();
1618 __ encode_heap_oop(t2, newval);
1619 newval = t2;
1620 __ cmpxchg_oop_shenandoah(addr, cmpval, newval, Assembler::word, true, true, false);
1621 __ csetw(res, Assembler::EQ);
1622 } else {
1623 __ encode_heap_oop(t1, cmpval);
1624 cmpval = t1;
1625 __ encode_heap_oop(rscratch2, newval);
1626 newval = rscratch2;
1627 casw(addr, newval, cmpval);
1628 __ eorw (res, r8, 1);
1629 }
1630 } else {
1631 if (UseShenandoahGC) {
1632 __ cmpxchg_oop_shenandoah(addr, cmpval, newval, Assembler::xword, true, true, false);
1633 __ csetw(res, Assembler::EQ);
1634 } else {
1635 casl(addr, newval, cmpval);
1636 __ eorw (res, r8, 1);
1637 }
1638 }
1639 } else if (op->code() == lir_cas_int) {
1640 casw(addr, newval, cmpval);
1641 __ eorw (res, r8, 1);
1642 } else {
1643 casl(addr, newval, cmpval);
1644 __ eorw (res, r8, 1);
1645 }
1646 }
1647
1648
1649 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1650
1651 Assembler::Condition acond, ncond;
1652 switch (condition) {
|
1600 }
1601
1602
1603 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1604 Register addr = as_reg(op->addr());
1605 Register newval = as_reg(op->new_value());
1606 Register cmpval = as_reg(op->cmp_value());
1607 Register res = op->result_opr()->as_register();
1608
1609 if (op->code() == lir_cas_obj) {
1610 assert(op->tmp1()->is_valid(), "must be");
1611 Register t1 = op->tmp1()->as_register();
1612 if (UseCompressedOops) {
1613 if (UseShenandoahGC) {
1614 __ encode_heap_oop(t1, cmpval);
1615 cmpval = t1;
1616 assert(op->tmp2()->is_valid(), "must be");
1617 Register t2 = op->tmp2()->as_register();
1618 __ encode_heap_oop(t2, newval);
1619 newval = t2;
1620 __ cmpxchg_oop_shenandoah(addr, cmpval, newval, Assembler::word, /*acquire*/ false, /*release*/ true, /*weak*/ false);
1621 __ csetw(res, Assembler::EQ);
1622 } else {
1623 __ encode_heap_oop(t1, cmpval);
1624 cmpval = t1;
1625 __ encode_heap_oop(rscratch2, newval);
1626 newval = rscratch2;
1627 casw(addr, newval, cmpval);
1628 __ eorw (res, r8, 1);
1629 }
1630 } else {
1631 if (UseShenandoahGC) {
1632 __ cmpxchg_oop_shenandoah(addr, cmpval, newval, Assembler::xword, /*acquire*/ false, /*release*/ true, /*weak*/ false);
1633 __ csetw(res, Assembler::EQ);
1634 } else {
1635 casl(addr, newval, cmpval);
1636 __ eorw (res, r8, 1);
1637 }
1638 }
1639 } else if (op->code() == lir_cas_int) {
1640 casw(addr, newval, cmpval);
1641 __ eorw (res, r8, 1);
1642 } else {
1643 casl(addr, newval, cmpval);
1644 __ eorw (res, r8, 1);
1645 }
1646 }
1647
1648
1649 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1650
1651 Assembler::Condition acond, ncond;
1652 switch (condition) {
|