1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 switch (rtype) {
137 case relocInfo::external_word_type:
138 _rspec = external_word_Relocation::spec(loc);
139 break;
140 case relocInfo::internal_word_type:
141 _rspec = internal_word_Relocation::spec(loc);
142 break;
143 case relocInfo::runtime_call_type:
144 // HMM
145 _rspec = runtime_call_Relocation::spec();
146 break;
147 case relocInfo::poll_type:
148 case relocInfo::poll_return_type:
149 _rspec = Relocation::spec_simple(rtype);
150 break;
151 case relocInfo::none:
152 break;
153 default:
154 ShouldNotReachHere();
155 }
156 }
157 #else // LP64
158
159 Address Address::make_array(ArrayAddress adr) {
160 AddressLiteral base = adr.base();
161 Address index = adr.index();
162 assert(index._disp == 0, "must not have disp"); // maybe it can?
163 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
164 array._rspec = base._rspec;
165 return array;
166 }
167
168 // exceedingly dangerous constructor
169 Address::Address(address loc, RelocationHolder spec) {
170 _base = noreg;
171 _index = noreg;
172 _scale = no_scale;
173 _disp = (intptr_t) loc;
174 _rspec = spec;
175 }
176
177 #endif // _LP64
178
179
180
181 // Convert the raw encoding form into the form expected by the constructor for
182 // Address. An index of 4 (rsp) corresponds to having no index, so convert
183 // that to noreg for the Address constructor.
184 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
185 RelocationHolder rspec;
186 if (disp_reloc != relocInfo::none) {
187 rspec = Relocation::spec_simple(disp_reloc);
188 }
189 bool valid_index = index != rsp->encoding();
190 if (valid_index) {
191 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
192 madr._rspec = rspec;
193 return madr;
194 } else {
195 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 }
199 }
200
201 // Implementation of Assembler
202
203 int AbstractAssembler::code_fill_byte() {
204 return (u_char)'\xF4'; // hlt
205 }
206
207 // make this go away someday
208 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
209 if (rtype == relocInfo::none)
210 emit_int32(data);
211 else
212 emit_data(data, Relocation::spec_simple(rtype), format);
213 }
214
215 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
216 assert(imm_operand == 0, "default format must be immediate in this file");
217 assert(inst_mark() != NULL, "must be inside InstructionMark");
218 if (rspec.type() != relocInfo::none) {
219 #ifdef ASSERT
220 check_relocation(rspec, format);
221 #endif
222 // Do not use AbstractAssembler::relocate, which is not intended for
223 // embedded words. Instead, relocate to the enclosing instruction.
224
225 // hack. call32 is too wide for mask so use disp32
226 if (format == call32_operand)
227 code_section()->relocate(inst_mark(), rspec, disp32_operand);
228 else
229 code_section()->relocate(inst_mark(), rspec, format);
230 }
231 emit_int32(data);
232 }
233
234 static int encode(Register r) {
235 int enc = r->encoding();
236 if (enc >= 8) {
237 enc -= 8;
238 }
239 return enc;
240 }
241
242 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
243 assert(dst->has_byte_register(), "must have byte register");
244 assert(isByte(op1) && isByte(op2), "wrong opcode");
245 assert(isByte(imm8), "not a byte");
246 assert((op1 & 0x01) == 0, "should be 8bit operation");
247 emit_int8(op1);
248 emit_int8(op2 | encode(dst));
249 emit_int8(imm8);
250 }
251
252
253 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
254 assert(isByte(op1) && isByte(op2), "wrong opcode");
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_int8(op2 | encode(dst));
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_int8(op2 | encode(dst));
264 emit_int32(imm32);
265 }
266 }
267
268 // Force generation of a 4 byte immediate value even if it fits into 8bit
269 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 assert((op1 & 0x01) == 1, "should be 32bit operation");
272 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
273 emit_int8(op1);
274 emit_int8(op2 | encode(dst));
275 emit_int32(imm32);
276 }
277
278 // immediate-to-memory forms
279 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
280 assert((op1 & 0x01) == 1, "should be 32bit operation");
281 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
282 if (is8bit(imm32)) {
283 emit_int8(op1 | 0x02); // set sign bit
284 emit_operand(rm, adr, 1);
285 emit_int8(imm32 & 0xFF);
286 } else {
287 emit_int8(op1);
288 emit_operand(rm, adr, 4);
289 emit_int32(imm32);
290 }
291 }
292
293
294 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
295 assert(isByte(op1) && isByte(op2), "wrong opcode");
296 emit_int8(op1);
297 emit_int8(op2 | encode(dst) << 3 | encode(src));
298 }
299
300
301 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
302 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
303 int mod_idx = 0;
304 // We will test if the displacement fits the compressed format and if so
305 // apply the compression to the displacment iff the result is8bit.
306 if (VM_Version::supports_evex() && is_evex_inst) {
307 switch (cur_tuple_type) {
308 case EVEX_FV:
309 if ((cur_encoding & VEX_W) == VEX_W) {
310 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
311 } else {
312 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
313 }
314 break;
315
316 case EVEX_HV:
317 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
318 break;
319
320 case EVEX_FVM:
321 break;
322
323 case EVEX_T1S:
324 switch (in_size_in_bits) {
325 case EVEX_8bit:
326 break;
327
328 case EVEX_16bit:
329 mod_idx = 1;
330 break;
331
332 case EVEX_32bit:
333 mod_idx = 2;
334 break;
335
336 case EVEX_64bit:
337 mod_idx = 3;
338 break;
339 }
340 break;
341
342 case EVEX_T1F:
343 case EVEX_T2:
344 case EVEX_T4:
345 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
346 break;
347
348 case EVEX_T8:
349 break;
350
351 case EVEX_HVM:
352 break;
353
354 case EVEX_QVM:
355 break;
356
357 case EVEX_OVM:
358 break;
359
360 case EVEX_M128:
361 break;
362
363 case EVEX_DUP:
364 break;
365
366 default:
367 assert(0, "no valid evex tuple_table entry");
368 break;
369 }
370
371 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
372 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
373 if ((disp % disp_factor) == 0) {
374 int new_disp = disp / disp_factor;
375 if ((-0x80 <= new_disp && new_disp < 0x80)) {
376 disp = new_disp;
377 }
378 } else {
379 return false;
380 }
381 }
382 }
383 return (-0x80 <= disp && disp < 0x80);
384 }
385
386
387 bool Assembler::emit_compressed_disp_byte(int &disp) {
388 int mod_idx = 0;
389 // We will test if the displacement fits the compressed format and if so
390 // apply the compression to the displacment iff the result is8bit.
391 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
392 int evex_encoding = _attributes->get_evex_encoding();
393 int tuple_type = _attributes->get_tuple_type();
394 switch (tuple_type) {
395 case EVEX_FV:
396 if ((evex_encoding & VEX_W) == VEX_W) {
397 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
398 } else {
399 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
400 }
401 break;
402
403 case EVEX_HV:
404 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
405 break;
406
407 case EVEX_FVM:
408 break;
409
410 case EVEX_T1S:
411 switch (_attributes->get_input_size()) {
412 case EVEX_8bit:
413 break;
414
415 case EVEX_16bit:
416 mod_idx = 1;
417 break;
418
419 case EVEX_32bit:
420 mod_idx = 2;
421 break;
422
423 case EVEX_64bit:
424 mod_idx = 3;
425 break;
426 }
427 break;
428
429 case EVEX_T1F:
430 case EVEX_T2:
431 case EVEX_T4:
432 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
433 break;
434
435 case EVEX_T8:
436 break;
437
438 case EVEX_HVM:
439 break;
440
441 case EVEX_QVM:
442 break;
443
444 case EVEX_OVM:
445 break;
446
447 case EVEX_M128:
448 break;
449
450 case EVEX_DUP:
451 break;
452
453 default:
454 assert(0, "no valid evex tuple_table entry");
455 break;
456 }
457
458 int vector_len = _attributes->get_vector_len();
459 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
460 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
461 if ((disp % disp_factor) == 0) {
462 int new_disp = disp / disp_factor;
463 if (is8bit(new_disp)) {
464 disp = new_disp;
465 }
466 } else {
467 return false;
468 }
469 }
470 }
471 return is8bit(disp);
472 }
473
474
475 void Assembler::emit_operand(Register reg, Register base, Register index,
476 Address::ScaleFactor scale, int disp,
477 RelocationHolder const& rspec,
478 int rip_relative_correction) {
479 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
480
481 // Encode the registers as needed in the fields they are used in
482
483 int regenc = encode(reg) << 3;
484 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
485 int baseenc = base->is_valid() ? encode(base) : 0;
486
487 if (base->is_valid()) {
488 if (index->is_valid()) {
489 assert(scale != Address::no_scale, "inconsistent address");
490 // [base + index*scale + disp]
491 if (disp == 0 && rtype == relocInfo::none &&
492 base != rbp LP64_ONLY(&& base != r13)) {
493 // [base + index*scale]
494 // [00 reg 100][ss index base]
495 assert(index != rsp, "illegal addressing mode");
496 emit_int8(0x04 | regenc);
497 emit_int8(scale << 6 | indexenc | baseenc);
498 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
499 // [base + index*scale + imm8]
500 // [01 reg 100][ss index base] imm8
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x44 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 emit_int8(disp & 0xFF);
505 } else {
506 // [base + index*scale + disp32]
507 // [10 reg 100][ss index base] disp32
508 assert(index != rsp, "illegal addressing mode");
509 emit_int8(0x84 | regenc);
510 emit_int8(scale << 6 | indexenc | baseenc);
511 emit_data(disp, rspec, disp32_operand);
512 }
513 } else if (base == rsp LP64_ONLY(|| base == r12)) {
514 // [rsp + disp]
515 if (disp == 0 && rtype == relocInfo::none) {
516 // [rsp]
517 // [00 reg 100][00 100 100]
518 emit_int8(0x04 | regenc);
519 emit_int8(0x24);
520 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
521 // [rsp + imm8]
522 // [01 reg 100][00 100 100] disp8
523 emit_int8(0x44 | regenc);
524 emit_int8(0x24);
525 emit_int8(disp & 0xFF);
526 } else {
527 // [rsp + imm32]
528 // [10 reg 100][00 100 100] disp32
529 emit_int8(0x84 | regenc);
530 emit_int8(0x24);
531 emit_data(disp, rspec, disp32_operand);
532 }
533 } else {
534 // [base + disp]
535 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
536 if (disp == 0 && rtype == relocInfo::none &&
537 base != rbp LP64_ONLY(&& base != r13)) {
538 // [base]
539 // [00 reg base]
540 emit_int8(0x00 | regenc | baseenc);
541 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
542 // [base + disp8]
543 // [01 reg base] disp8
544 emit_int8(0x40 | regenc | baseenc);
545 emit_int8(disp & 0xFF);
546 } else {
547 // [base + disp32]
548 // [10 reg base] disp32
549 emit_int8(0x80 | regenc | baseenc);
550 emit_data(disp, rspec, disp32_operand);
551 }
552 }
553 } else {
554 if (index->is_valid()) {
555 assert(scale != Address::no_scale, "inconsistent address");
556 // [index*scale + disp]
557 // [00 reg 100][ss index 101] disp32
558 assert(index != rsp, "illegal addressing mode");
559 emit_int8(0x04 | regenc);
560 emit_int8(scale << 6 | indexenc | 0x05);
561 emit_data(disp, rspec, disp32_operand);
562 } else if (rtype != relocInfo::none ) {
563 // [disp] (64bit) RIP-RELATIVE (32bit) abs
564 // [00 000 101] disp32
565
566 emit_int8(0x05 | regenc);
567 // Note that the RIP-rel. correction applies to the generated
568 // disp field, but _not_ to the target address in the rspec.
569
570 // disp was created by converting the target address minus the pc
571 // at the start of the instruction. That needs more correction here.
572 // intptr_t disp = target - next_ip;
573 assert(inst_mark() != NULL, "must be inside InstructionMark");
574 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
575 int64_t adjusted = disp;
576 // Do rip-rel adjustment for 64bit
577 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
578 assert(is_simm32(adjusted),
579 "must be 32bit offset (RIP relative address)");
580 emit_data((int32_t) adjusted, rspec, disp32_operand);
581
582 } else {
583 // 32bit never did this, did everything as the rip-rel/disp code above
584 // [disp] ABSOLUTE
585 // [00 reg 100][00 100 101] disp32
586 emit_int8(0x04 | regenc);
587 emit_int8(0x25);
588 emit_data(disp, rspec, disp32_operand);
589 }
590 }
591 }
592
593 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
594 Address::ScaleFactor scale, int disp,
595 RelocationHolder const& rspec) {
596 if (UseAVX > 2) {
597 int xreg_enc = reg->encoding();
598 if (xreg_enc > 15) {
599 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
600 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
601 return;
602 }
603 }
604 emit_operand((Register)reg, base, index, scale, disp, rspec);
605 }
606
607 // Secret local extension to Assembler::WhichOperand:
608 #define end_pc_operand (_WhichOperand_limit)
609
610 address Assembler::locate_operand(address inst, WhichOperand which) {
611 // Decode the given instruction, and return the address of
612 // an embedded 32-bit operand word.
613
614 // If "which" is disp32_operand, selects the displacement portion
615 // of an effective address specifier.
616 // If "which" is imm64_operand, selects the trailing immediate constant.
617 // If "which" is call32_operand, selects the displacement of a call or jump.
618 // Caller is responsible for ensuring that there is such an operand,
619 // and that it is 32/64 bits wide.
620
621 // If "which" is end_pc_operand, find the end of the instruction.
622
623 address ip = inst;
624 bool is_64bit = false;
625
626 debug_only(bool has_disp32 = false);
627 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
628
629 again_after_prefix:
630 switch (0xFF & *ip++) {
631
632 // These convenience macros generate groups of "case" labels for the switch.
633 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
634 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
635 case (x)+4: case (x)+5: case (x)+6: case (x)+7
636 #define REP16(x) REP8((x)+0): \
637 case REP8((x)+8)
638
639 case CS_segment:
640 case SS_segment:
641 case DS_segment:
642 case ES_segment:
643 case FS_segment:
644 case GS_segment:
645 // Seems dubious
646 LP64_ONLY(assert(false, "shouldn't have that prefix"));
647 assert(ip == inst+1, "only one prefix allowed");
648 goto again_after_prefix;
649
650 case 0x67:
651 case REX:
652 case REX_B:
653 case REX_X:
654 case REX_XB:
655 case REX_R:
656 case REX_RB:
657 case REX_RX:
658 case REX_RXB:
659 NOT_LP64(assert(false, "64bit prefixes"));
660 goto again_after_prefix;
661
662 case REX_W:
663 case REX_WB:
664 case REX_WX:
665 case REX_WXB:
666 case REX_WR:
667 case REX_WRB:
668 case REX_WRX:
669 case REX_WRXB:
670 NOT_LP64(assert(false, "64bit prefixes"));
671 is_64bit = true;
672 goto again_after_prefix;
673
674 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
675 case 0x88: // movb a, r
676 case 0x89: // movl a, r
677 case 0x8A: // movb r, a
678 case 0x8B: // movl r, a
679 case 0x8F: // popl a
680 debug_only(has_disp32 = true);
681 break;
682
683 case 0x68: // pushq #32
684 if (which == end_pc_operand) {
685 return ip + 4;
686 }
687 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
688 return ip; // not produced by emit_operand
689
690 case 0x66: // movw ... (size prefix)
691 again_after_size_prefix2:
692 switch (0xFF & *ip++) {
693 case REX:
694 case REX_B:
695 case REX_X:
696 case REX_XB:
697 case REX_R:
698 case REX_RB:
699 case REX_RX:
700 case REX_RXB:
701 case REX_W:
702 case REX_WB:
703 case REX_WX:
704 case REX_WXB:
705 case REX_WR:
706 case REX_WRB:
707 case REX_WRX:
708 case REX_WRXB:
709 NOT_LP64(assert(false, "64bit prefix found"));
710 goto again_after_size_prefix2;
711 case 0x8B: // movw r, a
712 case 0x89: // movw a, r
713 debug_only(has_disp32 = true);
714 break;
715 case 0xC7: // movw a, #16
716 debug_only(has_disp32 = true);
717 tail_size = 2; // the imm16
718 break;
719 case 0x0F: // several SSE/SSE2 variants
720 ip--; // reparse the 0x0F
721 goto again_after_prefix;
722 default:
723 ShouldNotReachHere();
724 }
725 break;
726
727 case REP8(0xB8): // movl/q r, #32/#64(oop?)
728 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
729 // these asserts are somewhat nonsensical
730 #ifndef _LP64
731 assert(which == imm_operand || which == disp32_operand,
732 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
733 #else
734 assert((which == call32_operand || which == imm_operand) && is_64bit ||
735 which == narrow_oop_operand && !is_64bit,
736 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
737 #endif // _LP64
738 return ip;
739
740 case 0x69: // imul r, a, #32
741 case 0xC7: // movl a, #32(oop?)
742 tail_size = 4;
743 debug_only(has_disp32 = true); // has both kinds of operands!
744 break;
745
746 case 0x0F: // movx..., etc.
747 switch (0xFF & *ip++) {
748 case 0x3A: // pcmpestri
749 tail_size = 1;
750 case 0x38: // ptest, pmovzxbw
751 ip++; // skip opcode
752 debug_only(has_disp32 = true); // has both kinds of operands!
753 break;
754
755 case 0x70: // pshufd r, r/a, #8
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 case 0x73: // psrldq r, #8
758 tail_size = 1;
759 break;
760
761 case 0x12: // movlps
762 case 0x28: // movaps
763 case 0x2E: // ucomiss
764 case 0x2F: // comiss
765 case 0x54: // andps
766 case 0x55: // andnps
767 case 0x56: // orps
768 case 0x57: // xorps
769 case 0x58: // addpd
770 case 0x59: // mulpd
771 case 0x6E: // movd
772 case 0x7E: // movd
773 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
774 case 0xFE: // paddd
775 debug_only(has_disp32 = true);
776 break;
777
778 case 0xAD: // shrd r, a, %cl
779 case 0xAF: // imul r, a
780 case 0xBE: // movsbl r, a (movsxb)
781 case 0xBF: // movswl r, a (movsxw)
782 case 0xB6: // movzbl r, a (movzxb)
783 case 0xB7: // movzwl r, a (movzxw)
784 case REP16(0x40): // cmovl cc, r, a
785 case 0xB0: // cmpxchgb
786 case 0xB1: // cmpxchg
787 case 0xC1: // xaddl
788 case 0xC7: // cmpxchg8
789 case REP16(0x90): // setcc a
790 debug_only(has_disp32 = true);
791 // fall out of the switch to decode the address
792 break;
793
794 case 0xC4: // pinsrw r, a, #8
795 debug_only(has_disp32 = true);
796 case 0xC5: // pextrw r, r, #8
797 tail_size = 1; // the imm8
798 break;
799
800 case 0xAC: // shrd r, a, #8
801 debug_only(has_disp32 = true);
802 tail_size = 1; // the imm8
803 break;
804
805 case REP16(0x80): // jcc rdisp32
806 if (which == end_pc_operand) return ip + 4;
807 assert(which == call32_operand, "jcc has no disp32 or imm");
808 return ip;
809 default:
810 ShouldNotReachHere();
811 }
812 break;
813
814 case 0x81: // addl a, #32; addl r, #32
815 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
816 // on 32bit in the case of cmpl, the imm might be an oop
817 tail_size = 4;
818 debug_only(has_disp32 = true); // has both kinds of operands!
819 break;
820
821 case 0x83: // addl a, #8; addl r, #8
822 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
823 debug_only(has_disp32 = true); // has both kinds of operands!
824 tail_size = 1;
825 break;
826
827 case 0x9B:
828 switch (0xFF & *ip++) {
829 case 0xD9: // fnstcw a
830 debug_only(has_disp32 = true);
831 break;
832 default:
833 ShouldNotReachHere();
834 }
835 break;
836
837 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
838 case REP4(0x10): // adc...
839 case REP4(0x20): // and...
840 case REP4(0x30): // xor...
841 case REP4(0x08): // or...
842 case REP4(0x18): // sbb...
843 case REP4(0x28): // sub...
844 case 0xF7: // mull a
845 case 0x8D: // lea r, a
846 case 0x87: // xchg r, a
847 case REP4(0x38): // cmp...
848 case 0x85: // test r, a
849 debug_only(has_disp32 = true); // has both kinds of operands!
850 break;
851
852 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
853 case 0xC6: // movb a, #8
854 case 0x80: // cmpb a, #8
855 case 0x6B: // imul r, a, #8
856 debug_only(has_disp32 = true); // has both kinds of operands!
857 tail_size = 1; // the imm8
858 break;
859
860 case 0xC4: // VEX_3bytes
861 case 0xC5: // VEX_2bytes
862 assert((UseAVX > 0), "shouldn't have VEX prefix");
863 assert(ip == inst+1, "no prefixes allowed");
864 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
865 // but they have prefix 0x0F and processed when 0x0F processed above.
866 //
867 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
868 // instructions (these instructions are not supported in 64-bit mode).
869 // To distinguish them bits [7:6] are set in the VEX second byte since
870 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
871 // those VEX bits REX and vvvv bits are inverted.
872 //
873 // Fortunately C2 doesn't generate these instructions so we don't need
874 // to check for them in product version.
875
876 // Check second byte
877 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
878
879 int vex_opcode;
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 vex_opcode = VEX_OPCODE_MASK & *ip;
883 ip++; // third byte
884 is_64bit = ((VEX_W & *ip) == VEX_W);
885 } else {
886 vex_opcode = VEX_OPCODE_0F;
887 }
888 ip++; // opcode
889 // To find the end of instruction (which == end_pc_operand).
890 switch (vex_opcode) {
891 case VEX_OPCODE_0F:
892 switch (0xFF & *ip) {
893 case 0x70: // pshufd r, r/a, #8
894 case 0x71: // ps[rl|ra|ll]w r, #8
895 case 0x72: // ps[rl|ra|ll]d r, #8
896 case 0x73: // ps[rl|ra|ll]q r, #8
897 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
898 case 0xC4: // pinsrw r, r, r/a, #8
899 case 0xC5: // pextrw r/a, r, #8
900 case 0xC6: // shufp[s|d] r, r, r/a, #8
901 tail_size = 1; // the imm8
902 break;
903 }
904 break;
905 case VEX_OPCODE_0F_3A:
906 tail_size = 1;
907 break;
908 }
909 ip++; // skip opcode
910 debug_only(has_disp32 = true); // has both kinds of operands!
911 break;
912
913 case 0x62: // EVEX_4bytes
914 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
915 assert(ip == inst+1, "no prefixes allowed");
916 // no EVEX collisions, all instructions that have 0x62 opcodes
917 // have EVEX versions and are subopcodes of 0x66
918 ip++; // skip P0 and exmaine W in P1
919 is_64bit = ((VEX_W & *ip) == VEX_W);
920 ip++; // move to P2
921 ip++; // skip P2, move to opcode
922 // To find the end of instruction (which == end_pc_operand).
923 switch (0xFF & *ip) {
924 case 0x22: // pinsrd r, r/a, #8
925 case 0x61: // pcmpestri r, r/a, #8
926 case 0x70: // pshufd r, r/a, #8
927 case 0x73: // psrldq r, #8
928 tail_size = 1; // the imm8
929 break;
930 default:
931 break;
932 }
933 ip++; // skip opcode
934 debug_only(has_disp32 = true); // has both kinds of operands!
935 break;
936
937 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
938 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
939 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
940 case 0xDD: // fld_d a; fst_d a; fstp_d a
941 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
942 case 0xDF: // fild_d a; fistp_d a
943 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
944 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
945 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
946 debug_only(has_disp32 = true);
947 break;
948
949 case 0xE8: // call rdisp32
950 case 0xE9: // jmp rdisp32
951 if (which == end_pc_operand) return ip + 4;
952 assert(which == call32_operand, "call has no disp32 or imm");
953 return ip;
954
955 case 0xF0: // Lock
956 assert(os::is_MP(), "only on MP");
957 goto again_after_prefix;
958
959 case 0xF3: // For SSE
960 case 0xF2: // For SSE2
961 switch (0xFF & *ip++) {
962 case REX:
963 case REX_B:
964 case REX_X:
965 case REX_XB:
966 case REX_R:
967 case REX_RB:
968 case REX_RX:
969 case REX_RXB:
970 case REX_W:
971 case REX_WB:
972 case REX_WX:
973 case REX_WXB:
974 case REX_WR:
975 case REX_WRB:
976 case REX_WRX:
977 case REX_WRXB:
978 NOT_LP64(assert(false, "found 64bit prefix"));
979 ip++;
980 default:
981 ip++;
982 }
983 debug_only(has_disp32 = true); // has both kinds of operands!
984 break;
985
986 default:
987 ShouldNotReachHere();
988
989 #undef REP8
990 #undef REP16
991 }
992
993 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
994 #ifdef _LP64
995 assert(which != imm_operand, "instruction is not a movq reg, imm64");
996 #else
997 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
998 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
999 #endif // LP64
1000 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1001
1002 // parse the output of emit_operand
1003 int op2 = 0xFF & *ip++;
1004 int base = op2 & 0x07;
1005 int op3 = -1;
1006 const int b100 = 4;
1007 const int b101 = 5;
1008 if (base == b100 && (op2 >> 6) != 3) {
1009 op3 = 0xFF & *ip++;
1010 base = op3 & 0x07; // refetch the base
1011 }
1012 // now ip points at the disp (if any)
1013
1014 switch (op2 >> 6) {
1015 case 0:
1016 // [00 reg 100][ss index base]
1017 // [00 reg 100][00 100 esp]
1018 // [00 reg base]
1019 // [00 reg 100][ss index 101][disp32]
1020 // [00 reg 101] [disp32]
1021
1022 if (base == b101) {
1023 if (which == disp32_operand)
1024 return ip; // caller wants the disp32
1025 ip += 4; // skip the disp32
1026 }
1027 break;
1028
1029 case 1:
1030 // [01 reg 100][ss index base][disp8]
1031 // [01 reg 100][00 100 esp][disp8]
1032 // [01 reg base] [disp8]
1033 ip += 1; // skip the disp8
1034 break;
1035
1036 case 2:
1037 // [10 reg 100][ss index base][disp32]
1038 // [10 reg 100][00 100 esp][disp32]
1039 // [10 reg base] [disp32]
1040 if (which == disp32_operand)
1041 return ip; // caller wants the disp32
1042 ip += 4; // skip the disp32
1043 break;
1044
1045 case 3:
1046 // [11 reg base] (not a memory addressing mode)
1047 break;
1048 }
1049
1050 if (which == end_pc_operand) {
1051 return ip + tail_size;
1052 }
1053
1054 #ifdef _LP64
1055 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1056 #else
1057 assert(which == imm_operand, "instruction has only an imm field");
1058 #endif // LP64
1059 return ip;
1060 }
1061
1062 address Assembler::locate_next_instruction(address inst) {
1063 // Secretly share code with locate_operand:
1064 return locate_operand(inst, end_pc_operand);
1065 }
1066
1067
1068 #ifdef ASSERT
1069 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1070 address inst = inst_mark();
1071 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1072 address opnd;
1073
1074 Relocation* r = rspec.reloc();
1075 if (r->type() == relocInfo::none) {
1076 return;
1077 } else if (r->is_call() || format == call32_operand) {
1078 // assert(format == imm32_operand, "cannot specify a nonzero format");
1079 opnd = locate_operand(inst, call32_operand);
1080 } else if (r->is_data()) {
1081 assert(format == imm_operand || format == disp32_operand
1082 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1083 opnd = locate_operand(inst, (WhichOperand)format);
1084 } else {
1085 assert(format == imm_operand, "cannot specify a format");
1086 return;
1087 }
1088 assert(opnd == pc(), "must put operand where relocs can find it");
1089 }
1090 #endif // ASSERT
1091
1092 void Assembler::emit_operand32(Register reg, Address adr) {
1093 assert(reg->encoding() < 8, "no extended registers");
1094 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1095 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1096 adr._rspec);
1097 }
1098
1099 void Assembler::emit_operand(Register reg, Address adr,
1100 int rip_relative_correction) {
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec,
1103 rip_relative_correction);
1104 }
1105
1106 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec);
1109 }
1110
1111 // MMX operations
1112 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1113 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1114 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1115 }
1116
1117 // work around gcc (3.2.1-7a) bug
1118 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123
1124 void Assembler::emit_farith(int b1, int b2, int i) {
1125 assert(isByte(b1) && isByte(b2), "wrong opcode");
1126 assert(0 <= i && i < 8, "illegal stack offset");
1127 emit_int8(b1);
1128 emit_int8(b2 + i);
1129 }
1130
1131
1132 // Now the Assembler instructions (identical for 32/64 bits)
1133
1134 void Assembler::adcl(Address dst, int32_t imm32) {
1135 InstructionMark im(this);
1136 prefix(dst);
1137 emit_arith_operand(0x81, rdx, dst, imm32);
1138 }
1139
1140 void Assembler::adcl(Address dst, Register src) {
1141 InstructionMark im(this);
1142 prefix(dst, src);
1143 emit_int8(0x11);
1144 emit_operand(src, dst);
1145 }
1146
1147 void Assembler::adcl(Register dst, int32_t imm32) {
1148 prefix(dst);
1149 emit_arith(0x81, 0xD0, dst, imm32);
1150 }
1151
1152 void Assembler::adcl(Register dst, Address src) {
1153 InstructionMark im(this);
1154 prefix(src, dst);
1155 emit_int8(0x13);
1156 emit_operand(dst, src);
1157 }
1158
1159 void Assembler::adcl(Register dst, Register src) {
1160 (void) prefix_and_encode(dst->encoding(), src->encoding());
1161 emit_arith(0x13, 0xC0, dst, src);
1162 }
1163
1164 void Assembler::addl(Address dst, int32_t imm32) {
1165 InstructionMark im(this);
1166 prefix(dst);
1167 emit_arith_operand(0x81, rax, dst, imm32);
1168 }
1169
1170 void Assembler::addb(Address dst, int imm8) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_int8((unsigned char)0x80);
1174 emit_operand(rax, dst, 1);
1175 emit_int8(imm8);
1176 }
1177
1178 void Assembler::addw(Address dst, int imm16) {
1179 InstructionMark im(this);
1180 emit_int8(0x66);
1181 prefix(dst);
1182 emit_int8((unsigned char)0x81);
1183 emit_operand(rax, dst, 2);
1184 emit_int16(imm16);
1185 }
1186
1187 void Assembler::addl(Address dst, Register src) {
1188 InstructionMark im(this);
1189 prefix(dst, src);
1190 emit_int8(0x01);
1191 emit_operand(src, dst);
1192 }
1193
1194 void Assembler::addl(Register dst, int32_t imm32) {
1195 prefix(dst);
1196 emit_arith(0x81, 0xC0, dst, imm32);
1197 }
1198
1199 void Assembler::addl(Register dst, Address src) {
1200 InstructionMark im(this);
1201 prefix(src, dst);
1202 emit_int8(0x03);
1203 emit_operand(dst, src);
1204 }
1205
1206 void Assembler::addl(Register dst, Register src) {
1207 (void) prefix_and_encode(dst->encoding(), src->encoding());
1208 emit_arith(0x03, 0xC0, dst, src);
1209 }
1210
1211 void Assembler::addr_nop_4() {
1212 assert(UseAddressNop, "no CPU support");
1213 // 4 bytes: NOP DWORD PTR [EAX+0]
1214 emit_int8(0x0F);
1215 emit_int8(0x1F);
1216 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1217 emit_int8(0); // 8-bits offset (1 byte)
1218 }
1219
1220 void Assembler::addr_nop_5() {
1221 assert(UseAddressNop, "no CPU support");
1222 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1223 emit_int8(0x0F);
1224 emit_int8(0x1F);
1225 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1226 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1227 emit_int8(0); // 8-bits offset (1 byte)
1228 }
1229
1230 void Assembler::addr_nop_7() {
1231 assert(UseAddressNop, "no CPU support");
1232 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1233 emit_int8(0x0F);
1234 emit_int8(0x1F);
1235 emit_int8((unsigned char)0x80);
1236 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addr_nop_8() {
1241 assert(UseAddressNop, "no CPU support");
1242 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1243 emit_int8(0x0F);
1244 emit_int8(0x1F);
1245 emit_int8((unsigned char)0x84);
1246 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1247 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1248 emit_int32(0); // 32-bits offset (4 bytes)
1249 }
1250
1251 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1252 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1253 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1254 attributes.set_rex_vex_w_reverted();
1255 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1256 emit_int8(0x58);
1257 emit_int8((unsigned char)(0xC0 | encode));
1258 }
1259
1260 void Assembler::addsd(XMMRegister dst, Address src) {
1261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1262 InstructionMark im(this);
1263 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1264 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1265 attributes.set_rex_vex_w_reverted();
1266 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1267 emit_int8(0x58);
1268 emit_operand(dst, src);
1269 }
1270
1271 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1272 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1274 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1275 emit_int8(0x58);
1276 emit_int8((unsigned char)(0xC0 | encode));
1277 }
1278
1279 void Assembler::addss(XMMRegister dst, Address src) {
1280 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1281 InstructionMark im(this);
1282 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1283 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1284 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1285 emit_int8(0x58);
1286 emit_operand(dst, src);
1287 }
1288
1289 void Assembler::aesdec(XMMRegister dst, Address src) {
1290 assert(VM_Version::supports_aes(), "");
1291 InstructionMark im(this);
1292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1293 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1294 emit_int8((unsigned char)0xDE);
1295 emit_operand(dst, src);
1296 }
1297
1298 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1299 assert(VM_Version::supports_aes(), "");
1300 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1301 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1302 emit_int8((unsigned char)0xDE);
1303 emit_int8(0xC0 | encode);
1304 }
1305
1306 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1307 assert(VM_Version::supports_aes(), "");
1308 InstructionMark im(this);
1309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1310 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1311 emit_int8((unsigned char)0xDF);
1312 emit_operand(dst, src);
1313 }
1314
1315 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1316 assert(VM_Version::supports_aes(), "");
1317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1318 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1319 emit_int8((unsigned char)0xDF);
1320 emit_int8((unsigned char)(0xC0 | encode));
1321 }
1322
1323 void Assembler::aesenc(XMMRegister dst, Address src) {
1324 assert(VM_Version::supports_aes(), "");
1325 InstructionMark im(this);
1326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1327 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1328 emit_int8((unsigned char)0xDC);
1329 emit_operand(dst, src);
1330 }
1331
1332 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1333 assert(VM_Version::supports_aes(), "");
1334 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1335 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1336 emit_int8((unsigned char)0xDC);
1337 emit_int8(0xC0 | encode);
1338 }
1339
1340 void Assembler::aesenclast(XMMRegister dst, Address src) {
1341 assert(VM_Version::supports_aes(), "");
1342 InstructionMark im(this);
1343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1344 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1345 emit_int8((unsigned char)0xDD);
1346 emit_operand(dst, src);
1347 }
1348
1349 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1350 assert(VM_Version::supports_aes(), "");
1351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1353 emit_int8((unsigned char)0xDD);
1354 emit_int8((unsigned char)(0xC0 | encode));
1355 }
1356
1357 void Assembler::andl(Address dst, int32_t imm32) {
1358 InstructionMark im(this);
1359 prefix(dst);
1360 emit_int8((unsigned char)0x81);
1361 emit_operand(rsp, dst, 4);
1362 emit_int32(imm32);
1363 }
1364
1365 void Assembler::andl(Register dst, int32_t imm32) {
1366 prefix(dst);
1367 emit_arith(0x81, 0xE0, dst, imm32);
1368 }
1369
1370 void Assembler::andl(Register dst, Address src) {
1371 InstructionMark im(this);
1372 prefix(src, dst);
1373 emit_int8(0x23);
1374 emit_operand(dst, src);
1375 }
1376
1377 void Assembler::andl(Register dst, Register src) {
1378 (void) prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_arith(0x23, 0xC0, dst, src);
1380 }
1381
1382 void Assembler::andnl(Register dst, Register src1, Register src2) {
1383 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1386 emit_int8((unsigned char)0xF2);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::andnl(Register dst, Register src1, Address src2) {
1391 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1392 InstructionMark im(this);
1393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1394 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1395 emit_int8((unsigned char)0xF2);
1396 emit_operand(dst, src2);
1397 }
1398
1399 void Assembler::bsfl(Register dst, Register src) {
1400 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1401 emit_int8(0x0F);
1402 emit_int8((unsigned char)0xBC);
1403 emit_int8((unsigned char)(0xC0 | encode));
1404 }
1405
1406 void Assembler::bsrl(Register dst, Register src) {
1407 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1408 emit_int8(0x0F);
1409 emit_int8((unsigned char)0xBD);
1410 emit_int8((unsigned char)(0xC0 | encode));
1411 }
1412
1413 void Assembler::bswapl(Register reg) { // bswap
1414 int encode = prefix_and_encode(reg->encoding());
1415 emit_int8(0x0F);
1416 emit_int8((unsigned char)(0xC8 | encode));
1417 }
1418
1419 void Assembler::blsil(Register dst, Register src) {
1420 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1421 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1422 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1423 emit_int8((unsigned char)0xF3);
1424 emit_int8((unsigned char)(0xC0 | encode));
1425 }
1426
1427 void Assembler::blsil(Register dst, Address src) {
1428 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1429 InstructionMark im(this);
1430 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1431 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1432 emit_int8((unsigned char)0xF3);
1433 emit_operand(rbx, src);
1434 }
1435
1436 void Assembler::blsmskl(Register dst, Register src) {
1437 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1438 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1439 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1440 emit_int8((unsigned char)0xF3);
1441 emit_int8((unsigned char)(0xC0 | encode));
1442 }
1443
1444 void Assembler::blsmskl(Register dst, Address src) {
1445 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1446 InstructionMark im(this);
1447 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1448 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1449 emit_int8((unsigned char)0xF3);
1450 emit_operand(rdx, src);
1451 }
1452
1453 void Assembler::blsrl(Register dst, Register src) {
1454 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1455 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1456 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1457 emit_int8((unsigned char)0xF3);
1458 emit_int8((unsigned char)(0xC0 | encode));
1459 }
1460
1461 void Assembler::blsrl(Register dst, Address src) {
1462 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1463 InstructionMark im(this);
1464 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1465 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1466 emit_int8((unsigned char)0xF3);
1467 emit_operand(rcx, src);
1468 }
1469
1470 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1471 // suspect disp32 is always good
1472 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1473
1474 if (L.is_bound()) {
1475 const int long_size = 5;
1476 int offs = (int)( target(L) - pc() );
1477 assert(offs <= 0, "assembler error");
1478 InstructionMark im(this);
1479 // 1110 1000 #32-bit disp
1480 emit_int8((unsigned char)0xE8);
1481 emit_data(offs - long_size, rtype, operand);
1482 } else {
1483 InstructionMark im(this);
1484 // 1110 1000 #32-bit disp
1485 L.add_patch_at(code(), locator());
1486
1487 emit_int8((unsigned char)0xE8);
1488 emit_data(int(0), rtype, operand);
1489 }
1490 }
1491
1492 void Assembler::call(Register dst) {
1493 int encode = prefix_and_encode(dst->encoding());
1494 emit_int8((unsigned char)0xFF);
1495 emit_int8((unsigned char)(0xD0 | encode));
1496 }
1497
1498
1499 void Assembler::call(Address adr) {
1500 InstructionMark im(this);
1501 prefix(adr);
1502 emit_int8((unsigned char)0xFF);
1503 emit_operand(rdx, adr);
1504 }
1505
1506 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1507 InstructionMark im(this);
1508 emit_int8((unsigned char)0xE8);
1509 intptr_t disp = entry - (pc() + sizeof(int32_t));
1510 // Entry is NULL in case of a scratch emit.
1511 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1512 // Technically, should use call32_operand, but this format is
1513 // implied by the fact that we're emitting a call instruction.
1514
1515 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1516 emit_data((int) disp, rspec, operand);
1517 }
1518
1519 void Assembler::cdql() {
1520 emit_int8((unsigned char)0x99);
1521 }
1522
1523 void Assembler::cld() {
1524 emit_int8((unsigned char)0xFC);
1525 }
1526
1527 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1528 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1529 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1530 emit_int8(0x0F);
1531 emit_int8(0x40 | cc);
1532 emit_int8((unsigned char)(0xC0 | encode));
1533 }
1534
1535
1536 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1537 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1538 prefix(src, dst);
1539 emit_int8(0x0F);
1540 emit_int8(0x40 | cc);
1541 emit_operand(dst, src);
1542 }
1543
1544 void Assembler::cmpb(Address dst, int imm8) {
1545 InstructionMark im(this);
1546 prefix(dst);
1547 emit_int8((unsigned char)0x80);
1548 emit_operand(rdi, dst, 1);
1549 emit_int8(imm8);
1550 }
1551
1552 void Assembler::cmpl(Address dst, int32_t imm32) {
1553 InstructionMark im(this);
1554 prefix(dst);
1555 emit_int8((unsigned char)0x81);
1556 emit_operand(rdi, dst, 4);
1557 emit_int32(imm32);
1558 }
1559
1560 void Assembler::cmpl(Register dst, int32_t imm32) {
1561 prefix(dst);
1562 emit_arith(0x81, 0xF8, dst, imm32);
1563 }
1564
1565 void Assembler::cmpl(Register dst, Register src) {
1566 (void) prefix_and_encode(dst->encoding(), src->encoding());
1567 emit_arith(0x3B, 0xC0, dst, src);
1568 }
1569
1570 void Assembler::cmpl(Register dst, Address src) {
1571 InstructionMark im(this);
1572 prefix(src, dst);
1573 emit_int8((unsigned char)0x3B);
1574 emit_operand(dst, src);
1575 }
1576
1577 void Assembler::cmpw(Address dst, int imm16) {
1578 InstructionMark im(this);
1579 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1580 emit_int8(0x66);
1581 emit_int8((unsigned char)0x81);
1582 emit_operand(rdi, dst, 2);
1583 emit_int16(imm16);
1584 }
1585
1586 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1587 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1588 // The ZF is set if the compared values were equal, and cleared otherwise.
1589 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1590 InstructionMark im(this);
1591 prefix(adr, reg);
1592 emit_int8(0x0F);
1593 emit_int8((unsigned char)0xB1);
1594 emit_operand(reg, adr);
1595 }
1596
1597 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1598 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1599 // The ZF is set if the compared values were equal, and cleared otherwise.
1600 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1601 InstructionMark im(this);
1602 prefix(adr, reg, true);
1603 emit_int8(0x0F);
1604 emit_int8((unsigned char)0xB0);
1605 emit_operand(reg, adr);
1606 }
1607
1608 void Assembler::comisd(XMMRegister dst, Address src) {
1609 // NOTE: dbx seems to decode this as comiss even though the
1610 // 0x66 is there. Strangly ucomisd comes out correct
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 InstructionMark im(this);
1613 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1614 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1615 attributes.set_rex_vex_w_reverted();
1616 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1617 emit_int8(0x2F);
1618 emit_operand(dst, src);
1619 }
1620
1621 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1623 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1624 attributes.set_rex_vex_w_reverted();
1625 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1626 emit_int8(0x2F);
1627 emit_int8((unsigned char)(0xC0 | encode));
1628 }
1629
1630 void Assembler::comiss(XMMRegister dst, Address src) {
1631 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1632 InstructionMark im(this);
1633 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1634 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1635 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1636 emit_int8(0x2F);
1637 emit_operand(dst, src);
1638 }
1639
1640 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1641 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1643 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1644 emit_int8(0x2F);
1645 emit_int8((unsigned char)(0xC0 | encode));
1646 }
1647
1648 void Assembler::cpuid() {
1649 emit_int8(0x0F);
1650 emit_int8((unsigned char)0xA2);
1651 }
1652
1653 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1654 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1655 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1656 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1657 //
1658 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1659 //
1660 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1661 //
1662 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1663 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1664 assert(VM_Version::supports_sse4_2(), "");
1665 int8_t w = 0x01;
1666 Prefix p = Prefix_EMPTY;
1667
1668 emit_int8((int8_t)0xF2);
1669 switch (sizeInBytes) {
1670 case 1:
1671 w = 0;
1672 break;
1673 case 2:
1674 case 4:
1675 break;
1676 LP64_ONLY(case 8:)
1677 // This instruction is not valid in 32 bits
1678 // Note:
1679 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1680 //
1681 // Page B - 72 Vol. 2C says
1682 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1683 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1684 // F0!!!
1685 // while 3 - 208 Vol. 2A
1686 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1687 //
1688 // the 0 on a last bit is reserved for a different flavor of this instruction :
1689 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1690 p = REX_W;
1691 break;
1692 default:
1693 assert(0, "Unsupported value for a sizeInBytes argument");
1694 break;
1695 }
1696 LP64_ONLY(prefix(crc, v, p);)
1697 emit_int8((int8_t)0x0F);
1698 emit_int8(0x38);
1699 emit_int8((int8_t)(0xF0 | w));
1700 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1701 }
1702
1703 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1704 assert(VM_Version::supports_sse4_2(), "");
1705 InstructionMark im(this);
1706 int8_t w = 0x01;
1707 Prefix p = Prefix_EMPTY;
1708
1709 emit_int8((int8_t)0xF2);
1710 switch (sizeInBytes) {
1711 case 1:
1712 w = 0;
1713 break;
1714 case 2:
1715 case 4:
1716 break;
1717 LP64_ONLY(case 8:)
1718 // This instruction is not valid in 32 bits
1719 p = REX_W;
1720 break;
1721 default:
1722 assert(0, "Unsupported value for a sizeInBytes argument");
1723 break;
1724 }
1725 LP64_ONLY(prefix(crc, adr, p);)
1726 emit_int8((int8_t)0x0F);
1727 emit_int8(0x38);
1728 emit_int8((int8_t)(0xF0 | w));
1729 emit_operand(crc, adr);
1730 }
1731
1732 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1734 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1735 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1736 emit_int8((unsigned char)0xE6);
1737 emit_int8((unsigned char)(0xC0 | encode));
1738 }
1739
1740 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1742 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1743 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1744 emit_int8(0x5B);
1745 emit_int8((unsigned char)(0xC0 | encode));
1746 }
1747
1748 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1750 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1751 attributes.set_rex_vex_w_reverted();
1752 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x5A);
1754 emit_int8((unsigned char)(0xC0 | encode));
1755 }
1756
1757 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionMark im(this);
1760 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1761 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1762 attributes.set_rex_vex_w_reverted();
1763 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1764 emit_int8(0x5A);
1765 emit_operand(dst, src);
1766 }
1767
1768 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1769 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1770 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1771 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1772 emit_int8(0x2A);
1773 emit_int8((unsigned char)(0xC0 | encode));
1774 }
1775
1776 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1777 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1778 InstructionMark im(this);
1779 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1780 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1781 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1782 emit_int8(0x2A);
1783 emit_operand(dst, src);
1784 }
1785
1786 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1788 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1789 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1790 emit_int8(0x2A);
1791 emit_int8((unsigned char)(0xC0 | encode));
1792 }
1793
1794 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1795 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1796 InstructionMark im(this);
1797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1799 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1800 emit_int8(0x2A);
1801 emit_operand(dst, src);
1802 }
1803
1804 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1805 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1806 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1807 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1808 emit_int8(0x2A);
1809 emit_int8((unsigned char)(0xC0 | encode));
1810 }
1811
1812 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1815 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1816 emit_int8(0x5A);
1817 emit_int8((unsigned char)(0xC0 | encode));
1818 }
1819
1820 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1822 InstructionMark im(this);
1823 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1824 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1825 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x5A);
1827 emit_operand(dst, src);
1828 }
1829
1830
1831 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1832 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1833 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1834 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1835 emit_int8(0x2C);
1836 emit_int8((unsigned char)(0xC0 | encode));
1837 }
1838
1839 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1842 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1843 emit_int8(0x2C);
1844 emit_int8((unsigned char)(0xC0 | encode));
1845 }
1846
1847 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1850 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1851 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1852 emit_int8((unsigned char)0xE6);
1853 emit_int8((unsigned char)(0xC0 | encode));
1854 }
1855
1856 void Assembler::decl(Address dst) {
1857 // Don't use it directly. Use MacroAssembler::decrement() instead.
1858 InstructionMark im(this);
1859 prefix(dst);
1860 emit_int8((unsigned char)0xFF);
1861 emit_operand(rcx, dst);
1862 }
1863
1864 void Assembler::divsd(XMMRegister dst, Address src) {
1865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1866 InstructionMark im(this);
1867 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1868 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1869 attributes.set_rex_vex_w_reverted();
1870 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1871 emit_int8(0x5E);
1872 emit_operand(dst, src);
1873 }
1874
1875 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1877 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1878 attributes.set_rex_vex_w_reverted();
1879 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1880 emit_int8(0x5E);
1881 emit_int8((unsigned char)(0xC0 | encode));
1882 }
1883
1884 void Assembler::divss(XMMRegister dst, Address src) {
1885 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1886 InstructionMark im(this);
1887 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1888 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1889 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1890 emit_int8(0x5E);
1891 emit_operand(dst, src);
1892 }
1893
1894 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1895 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1896 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1897 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1898 emit_int8(0x5E);
1899 emit_int8((unsigned char)(0xC0 | encode));
1900 }
1901
1902 void Assembler::emms() {
1903 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1904 emit_int8(0x0F);
1905 emit_int8(0x77);
1906 }
1907
1908 void Assembler::hlt() {
1909 emit_int8((unsigned char)0xF4);
1910 }
1911
1912 void Assembler::idivl(Register src) {
1913 int encode = prefix_and_encode(src->encoding());
1914 emit_int8((unsigned char)0xF7);
1915 emit_int8((unsigned char)(0xF8 | encode));
1916 }
1917
1918 void Assembler::divl(Register src) { // Unsigned
1919 int encode = prefix_and_encode(src->encoding());
1920 emit_int8((unsigned char)0xF7);
1921 emit_int8((unsigned char)(0xF0 | encode));
1922 }
1923
1924 void Assembler::imull(Register src) {
1925 int encode = prefix_and_encode(src->encoding());
1926 emit_int8((unsigned char)0xF7);
1927 emit_int8((unsigned char)(0xE8 | encode));
1928 }
1929
1930 void Assembler::imull(Register dst, Register src) {
1931 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1932 emit_int8(0x0F);
1933 emit_int8((unsigned char)0xAF);
1934 emit_int8((unsigned char)(0xC0 | encode));
1935 }
1936
1937
1938 void Assembler::imull(Register dst, Register src, int value) {
1939 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1940 if (is8bit(value)) {
1941 emit_int8(0x6B);
1942 emit_int8((unsigned char)(0xC0 | encode));
1943 emit_int8(value & 0xFF);
1944 } else {
1945 emit_int8(0x69);
1946 emit_int8((unsigned char)(0xC0 | encode));
1947 emit_int32(value);
1948 }
1949 }
1950
1951 void Assembler::imull(Register dst, Address src) {
1952 InstructionMark im(this);
1953 prefix(src, dst);
1954 emit_int8(0x0F);
1955 emit_int8((unsigned char) 0xAF);
1956 emit_operand(dst, src);
1957 }
1958
1959
1960 void Assembler::incl(Address dst) {
1961 // Don't use it directly. Use MacroAssembler::increment() instead.
1962 InstructionMark im(this);
1963 prefix(dst);
1964 emit_int8((unsigned char)0xFF);
1965 emit_operand(rax, dst);
1966 }
1967
1968 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1969 InstructionMark im(this);
1970 assert((0 <= cc) && (cc < 16), "illegal cc");
1971 if (L.is_bound()) {
1972 address dst = target(L);
1973 assert(dst != NULL, "jcc most probably wrong");
1974
1975 const int short_size = 2;
1976 const int long_size = 6;
1977 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1978 if (maybe_short && is8bit(offs - short_size)) {
1979 // 0111 tttn #8-bit disp
1980 emit_int8(0x70 | cc);
1981 emit_int8((offs - short_size) & 0xFF);
1982 } else {
1983 // 0000 1111 1000 tttn #32-bit disp
1984 assert(is_simm32(offs - long_size),
1985 "must be 32bit offset (call4)");
1986 emit_int8(0x0F);
1987 emit_int8((unsigned char)(0x80 | cc));
1988 emit_int32(offs - long_size);
1989 }
1990 } else {
1991 // Note: could eliminate cond. jumps to this jump if condition
1992 // is the same however, seems to be rather unlikely case.
1993 // Note: use jccb() if label to be bound is very close to get
1994 // an 8-bit displacement
1995 L.add_patch_at(code(), locator());
1996 emit_int8(0x0F);
1997 emit_int8((unsigned char)(0x80 | cc));
1998 emit_int32(0);
1999 }
2000 }
2001
2002 void Assembler::jccb(Condition cc, Label& L) {
2003 if (L.is_bound()) {
2004 const int short_size = 2;
2005 address entry = target(L);
2006 #ifdef ASSERT
2007 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2008 intptr_t delta = short_branch_delta();
2009 if (delta != 0) {
2010 dist += (dist < 0 ? (-delta) :delta);
2011 }
2012 assert(is8bit(dist), "Dispacement too large for a short jmp");
2013 #endif
2014 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2015 // 0111 tttn #8-bit disp
2016 emit_int8(0x70 | cc);
2017 emit_int8((offs - short_size) & 0xFF);
2018 } else {
2019 InstructionMark im(this);
2020 L.add_patch_at(code(), locator());
2021 emit_int8(0x70 | cc);
2022 emit_int8(0);
2023 }
2024 }
2025
2026 void Assembler::jccb_if_possible(Condition cc, Label& L) {
2027
2028 #ifdef ASSERT
2029 if (UseShenandoahGC) {
2030 jcc(cc, L);
2031 } else
2032 #endif
2033 jccb(cc, L);
2034 }
2035
2036 void Assembler::jmp(Address adr) {
2037 InstructionMark im(this);
2038 prefix(adr);
2039 emit_int8((unsigned char)0xFF);
2040 emit_operand(rsp, adr);
2041 }
2042
2043 void Assembler::jmp(Label& L, bool maybe_short) {
2044 if (L.is_bound()) {
2045 address entry = target(L);
2046 assert(entry != NULL, "jmp most probably wrong");
2047 InstructionMark im(this);
2048 const int short_size = 2;
2049 const int long_size = 5;
2050 intptr_t offs = entry - pc();
2051 if (maybe_short && is8bit(offs - short_size)) {
2052 emit_int8((unsigned char)0xEB);
2053 emit_int8((offs - short_size) & 0xFF);
2054 } else {
2055 emit_int8((unsigned char)0xE9);
2056 emit_int32(offs - long_size);
2057 }
2058 } else {
2059 // By default, forward jumps are always 32-bit displacements, since
2060 // we can't yet know where the label will be bound. If you're sure that
2061 // the forward jump will not run beyond 256 bytes, use jmpb to
2062 // force an 8-bit displacement.
2063 InstructionMark im(this);
2064 L.add_patch_at(code(), locator());
2065 emit_int8((unsigned char)0xE9);
2066 emit_int32(0);
2067 }
2068 }
2069
2070 void Assembler::jmp(Register entry) {
2071 int encode = prefix_and_encode(entry->encoding());
2072 emit_int8((unsigned char)0xFF);
2073 emit_int8((unsigned char)(0xE0 | encode));
2074 }
2075
2076 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2077 InstructionMark im(this);
2078 emit_int8((unsigned char)0xE9);
2079 assert(dest != NULL, "must have a target");
2080 intptr_t disp = dest - (pc() + sizeof(int32_t));
2081 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2082 emit_data(disp, rspec.reloc(), call32_operand);
2083 }
2084
2085 void Assembler::jmpb(Label& L) {
2086 if (L.is_bound()) {
2087 const int short_size = 2;
2088 address entry = target(L);
2089 assert(entry != NULL, "jmp most probably wrong");
2090 #ifdef ASSERT
2091 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2092 intptr_t delta = short_branch_delta();
2093 if (delta != 0) {
2094 dist += (dist < 0 ? (-delta) :delta);
2095 }
2096 assert(is8bit(dist), "Dispacement too large for a short jmp");
2097 #endif
2098 intptr_t offs = entry - pc();
2099 emit_int8((unsigned char)0xEB);
2100 emit_int8((offs - short_size) & 0xFF);
2101 } else {
2102 InstructionMark im(this);
2103 L.add_patch_at(code(), locator());
2104 emit_int8((unsigned char)0xEB);
2105 emit_int8(0);
2106 }
2107 }
2108
2109 void Assembler::jmpb_if_possible(Label& L) {
2110
2111 #ifdef ASSERT
2112 if (UseShenandoahGC) {
2113 jmp(L);
2114 } else
2115 #endif
2116 jmpb(L);
2117 }
2118
2119 void Assembler::ldmxcsr( Address src) {
2120 if (UseAVX > 0 ) {
2121 InstructionMark im(this);
2122 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2123 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2124 emit_int8((unsigned char)0xAE);
2125 emit_operand(as_Register(2), src);
2126 } else {
2127 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2128 InstructionMark im(this);
2129 prefix(src);
2130 emit_int8(0x0F);
2131 emit_int8((unsigned char)0xAE);
2132 emit_operand(as_Register(2), src);
2133 }
2134 }
2135
2136 void Assembler::leal(Register dst, Address src) {
2137 InstructionMark im(this);
2138 #ifdef _LP64
2139 emit_int8(0x67); // addr32
2140 prefix(src, dst);
2141 #endif // LP64
2142 emit_int8((unsigned char)0x8D);
2143 emit_operand(dst, src);
2144 }
2145
2146 void Assembler::lfence() {
2147 emit_int8(0x0F);
2148 emit_int8((unsigned char)0xAE);
2149 emit_int8((unsigned char)0xE8);
2150 }
2151
2152 void Assembler::lock() {
2153 emit_int8((unsigned char)0xF0);
2154 }
2155
2156 void Assembler::lzcntl(Register dst, Register src) {
2157 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2158 emit_int8((unsigned char)0xF3);
2159 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2160 emit_int8(0x0F);
2161 emit_int8((unsigned char)0xBD);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 // Emit mfence instruction
2166 void Assembler::mfence() {
2167 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2168 emit_int8(0x0F);
2169 emit_int8((unsigned char)0xAE);
2170 emit_int8((unsigned char)0xF0);
2171 }
2172
2173 void Assembler::mov(Register dst, Register src) {
2174 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2175 }
2176
2177 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2179 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2180 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2181 attributes.set_rex_vex_w_reverted();
2182 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2183 emit_int8(0x28);
2184 emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186
2187 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2188 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2189 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2190 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2191 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2192 emit_int8(0x28);
2193 emit_int8((unsigned char)(0xC0 | encode));
2194 }
2195
2196 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2197 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2199 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2200 emit_int8(0x16);
2201 emit_int8((unsigned char)(0xC0 | encode));
2202 }
2203
2204 void Assembler::movb(Register dst, Address src) {
2205 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2206 InstructionMark im(this);
2207 prefix(src, dst, true);
2208 emit_int8((unsigned char)0x8A);
2209 emit_operand(dst, src);
2210 }
2211
2212 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2213 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2214 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2215 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2216 attributes.set_rex_vex_w_reverted();
2217 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2218 emit_int8(0x12);
2219 emit_int8(0xC0 | encode);
2220 }
2221
2222 void Assembler::kmovbl(KRegister dst, Register src) {
2223 assert(VM_Version::supports_avx512dq(), "");
2224 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2225 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2226 emit_int8((unsigned char)0x92);
2227 emit_int8((unsigned char)(0xC0 | encode));
2228 }
2229
2230 void Assembler::kmovbl(Register dst, KRegister src) {
2231 assert(VM_Version::supports_avx512dq(), "");
2232 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2234 emit_int8((unsigned char)0x93);
2235 emit_int8((unsigned char)(0xC0 | encode));
2236 }
2237
2238 void Assembler::kmovwl(KRegister dst, Register src) {
2239 assert(VM_Version::supports_evex(), "");
2240 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2241 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2242 emit_int8((unsigned char)0x92);
2243 emit_int8((unsigned char)(0xC0 | encode));
2244 }
2245
2246 void Assembler::kmovwl(Register dst, KRegister src) {
2247 assert(VM_Version::supports_evex(), "");
2248 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2249 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2250 emit_int8((unsigned char)0x93);
2251 emit_int8((unsigned char)(0xC0 | encode));
2252 }
2253
2254 void Assembler::kmovwl(KRegister dst, Address src) {
2255 assert(VM_Version::supports_evex(), "");
2256 InstructionMark im(this);
2257 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2259 emit_int8((unsigned char)0x90);
2260 emit_operand((Register)dst, src);
2261 }
2262
2263 void Assembler::kmovdl(KRegister dst, Register src) {
2264 assert(VM_Version::supports_avx512bw(), "");
2265 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2266 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2267 emit_int8((unsigned char)0x92);
2268 emit_int8((unsigned char)(0xC0 | encode));
2269 }
2270
2271 void Assembler::kmovdl(Register dst, KRegister src) {
2272 assert(VM_Version::supports_avx512bw(), "");
2273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2274 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2275 emit_int8((unsigned char)0x93);
2276 emit_int8((unsigned char)(0xC0 | encode));
2277 }
2278
2279 void Assembler::kmovql(KRegister dst, KRegister src) {
2280 assert(VM_Version::supports_avx512bw(), "");
2281 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2282 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2283 emit_int8((unsigned char)0x90);
2284 emit_int8((unsigned char)(0xC0 | encode));
2285 }
2286
2287 void Assembler::kmovql(KRegister dst, Address src) {
2288 assert(VM_Version::supports_avx512bw(), "");
2289 InstructionMark im(this);
2290 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2291 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2292 emit_int8((unsigned char)0x90);
2293 emit_operand((Register)dst, src);
2294 }
2295
2296 void Assembler::kmovql(Address dst, KRegister src) {
2297 assert(VM_Version::supports_avx512bw(), "");
2298 InstructionMark im(this);
2299 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2300 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2301 emit_int8((unsigned char)0x90);
2302 emit_operand((Register)src, dst);
2303 }
2304
2305 void Assembler::kmovql(KRegister dst, Register src) {
2306 assert(VM_Version::supports_avx512bw(), "");
2307 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2308 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2309 emit_int8((unsigned char)0x92);
2310 emit_int8((unsigned char)(0xC0 | encode));
2311 }
2312
2313 void Assembler::kmovql(Register dst, KRegister src) {
2314 assert(VM_Version::supports_avx512bw(), "");
2315 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2316 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2317 emit_int8((unsigned char)0x93);
2318 emit_int8((unsigned char)(0xC0 | encode));
2319 }
2320
2321 void Assembler::knotwl(KRegister dst, KRegister src) {
2322 assert(VM_Version::supports_evex(), "");
2323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2324 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2325 emit_int8((unsigned char)0x44);
2326 emit_int8((unsigned char)(0xC0 | encode));
2327 }
2328
2329 // This instruction produces ZF or CF flags
2330 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2331 assert(VM_Version::supports_avx512dq(), "");
2332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2333 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2334 emit_int8((unsigned char)0x98);
2335 emit_int8((unsigned char)(0xC0 | encode));
2336 }
2337
2338 // This instruction produces ZF or CF flags
2339 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2340 assert(VM_Version::supports_evex(), "");
2341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2342 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2343 emit_int8((unsigned char)0x98);
2344 emit_int8((unsigned char)(0xC0 | encode));
2345 }
2346
2347 // This instruction produces ZF or CF flags
2348 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2349 assert(VM_Version::supports_avx512bw(), "");
2350 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2351 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2352 emit_int8((unsigned char)0x98);
2353 emit_int8((unsigned char)(0xC0 | encode));
2354 }
2355
2356 // This instruction produces ZF or CF flags
2357 void Assembler::kortestql(KRegister src1, KRegister src2) {
2358 assert(VM_Version::supports_avx512bw(), "");
2359 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2360 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2361 emit_int8((unsigned char)0x98);
2362 emit_int8((unsigned char)(0xC0 | encode));
2363 }
2364
2365 // This instruction produces ZF or CF flags
2366 void Assembler::ktestql(KRegister src1, KRegister src2) {
2367 assert(VM_Version::supports_avx512bw(), "");
2368 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2369 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2370 emit_int8((unsigned char)0x99);
2371 emit_int8((unsigned char)(0xC0 | encode));
2372 }
2373
2374 void Assembler::ktestq(KRegister src1, KRegister src2) {
2375 assert(VM_Version::supports_avx512bw(), "");
2376 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2377 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2378 emit_int8((unsigned char)0x99);
2379 emit_int8((unsigned char)(0xC0 | encode));
2380 }
2381
2382 void Assembler::ktestd(KRegister src1, KRegister src2) {
2383 assert(VM_Version::supports_avx512bw(), "");
2384 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2385 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2386 emit_int8((unsigned char)0x99);
2387 emit_int8((unsigned char)(0xC0 | encode));
2388 }
2389
2390 void Assembler::movb(Address dst, int imm8) {
2391 InstructionMark im(this);
2392 prefix(dst);
2393 emit_int8((unsigned char)0xC6);
2394 emit_operand(rax, dst, 1);
2395 emit_int8(imm8);
2396 }
2397
2398
2399 void Assembler::movb(Address dst, Register src) {
2400 assert(src->has_byte_register(), "must have byte register");
2401 InstructionMark im(this);
2402 prefix(dst, src, true);
2403 emit_int8((unsigned char)0x88);
2404 emit_operand(src, dst);
2405 }
2406
2407 void Assembler::movdl(XMMRegister dst, Register src) {
2408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2409 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2410 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2411 emit_int8(0x6E);
2412 emit_int8((unsigned char)(0xC0 | encode));
2413 }
2414
2415 void Assembler::movdl(Register dst, XMMRegister src) {
2416 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2417 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2418 // swap src/dst to get correct prefix
2419 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2420 emit_int8(0x7E);
2421 emit_int8((unsigned char)(0xC0 | encode));
2422 }
2423
2424 void Assembler::movdl(XMMRegister dst, Address src) {
2425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2426 InstructionMark im(this);
2427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2428 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2429 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2430 emit_int8(0x6E);
2431 emit_operand(dst, src);
2432 }
2433
2434 void Assembler::movdl(Address dst, XMMRegister src) {
2435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2436 InstructionMark im(this);
2437 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2438 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2439 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2440 emit_int8(0x7E);
2441 emit_operand(src, dst);
2442 }
2443
2444 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2446 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2447 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2448 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2449 emit_int8(0x6F);
2450 emit_int8((unsigned char)(0xC0 | encode));
2451 }
2452
2453 void Assembler::movdqa(XMMRegister dst, Address src) {
2454 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2455 InstructionMark im(this);
2456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2457 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2458 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2459 emit_int8(0x6F);
2460 emit_operand(dst, src);
2461 }
2462
2463 void Assembler::movdqu(XMMRegister dst, Address src) {
2464 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2465 InstructionMark im(this);
2466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2467 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2468 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2469 emit_int8(0x6F);
2470 emit_operand(dst, src);
2471 }
2472
2473 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2475 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2476 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2477 emit_int8(0x6F);
2478 emit_int8((unsigned char)(0xC0 | encode));
2479 }
2480
2481 void Assembler::movdqu(Address dst, XMMRegister src) {
2482 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2483 InstructionMark im(this);
2484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2485 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2486 attributes.reset_is_clear_context();
2487 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2488 emit_int8(0x7F);
2489 emit_operand(src, dst);
2490 }
2491
2492 // Move Unaligned 256bit Vector
2493 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2494 assert(UseAVX > 0, "");
2495 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2496 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2497 emit_int8(0x6F);
2498 emit_int8((unsigned char)(0xC0 | encode));
2499 }
2500
2501 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2502 assert(UseAVX > 0, "");
2503 InstructionMark im(this);
2504 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2505 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2506 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2507 emit_int8(0x6F);
2508 emit_operand(dst, src);
2509 }
2510
2511 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2512 assert(UseAVX > 0, "");
2513 InstructionMark im(this);
2514 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2515 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2516 attributes.reset_is_clear_context();
2517 // swap src<->dst for encoding
2518 assert(src != xnoreg, "sanity");
2519 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2520 emit_int8(0x7F);
2521 emit_operand(src, dst);
2522 }
2523
2524 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2525 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2526 assert(VM_Version::supports_evex(), "");
2527 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2528 attributes.set_is_evex_instruction();
2529 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2530 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2531 emit_int8(0x6F);
2532 emit_int8((unsigned char)(0xC0 | encode));
2533 }
2534
2535 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2536 assert(VM_Version::supports_evex(), "");
2537 InstructionMark im(this);
2538 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2539 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2540 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2541 attributes.set_is_evex_instruction();
2542 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2543 emit_int8(0x6F);
2544 emit_operand(dst, src);
2545 }
2546
2547 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2548 assert(VM_Version::supports_evex(), "");
2549 assert(src != xnoreg, "sanity");
2550 InstructionMark im(this);
2551 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2552 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2553 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2554 attributes.set_is_evex_instruction();
2555 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2556 emit_int8(0x7F);
2557 emit_operand(src, dst);
2558 }
2559
2560 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2561 assert(VM_Version::supports_avx512vlbw(), "");
2562 assert(is_vector_masking(), ""); // For stub code use only
2563 InstructionMark im(this);
2564 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2565 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2566 attributes.set_embedded_opmask_register_specifier(mask);
2567 attributes.set_is_evex_instruction();
2568 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2569 emit_int8(0x6F);
2570 emit_operand(dst, src);
2571 }
2572
2573 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2574 assert(VM_Version::supports_evex(), "");
2575 InstructionMark im(this);
2576 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2577 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2578 attributes.set_is_evex_instruction();
2579 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2580 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2581 emit_int8(0x6F);
2582 emit_operand(dst, src);
2583 }
2584
2585 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2586 assert(is_vector_masking(), "");
2587 assert(VM_Version::supports_avx512vlbw(), "");
2588 InstructionMark im(this);
2589 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2590 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2591 attributes.set_embedded_opmask_register_specifier(mask);
2592 attributes.set_is_evex_instruction();
2593 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2594 emit_int8(0x6F);
2595 emit_operand(dst, src);
2596 }
2597
2598 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2599 assert(VM_Version::supports_evex(), "");
2600 assert(src != xnoreg, "sanity");
2601 InstructionMark im(this);
2602 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2603 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2604 attributes.set_is_evex_instruction();
2605 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2606 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2607 emit_int8(0x7F);
2608 emit_operand(src, dst);
2609 }
2610
2611 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2612 assert(VM_Version::supports_avx512vlbw(), "");
2613 assert(src != xnoreg, "sanity");
2614 InstructionMark im(this);
2615 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2616 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2617 attributes.reset_is_clear_context();
2618 attributes.set_embedded_opmask_register_specifier(mask);
2619 attributes.set_is_evex_instruction();
2620 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2621 emit_int8(0x7F);
2622 emit_operand(src, dst);
2623 }
2624
2625 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2626 assert(VM_Version::supports_evex(), "");
2627 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2628 attributes.set_is_evex_instruction();
2629 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2630 emit_int8(0x6F);
2631 emit_int8((unsigned char)(0xC0 | encode));
2632 }
2633
2634 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2635 assert(VM_Version::supports_evex(), "");
2636 InstructionMark im(this);
2637 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2638 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2639 attributes.set_is_evex_instruction();
2640 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2641 emit_int8(0x6F);
2642 emit_operand(dst, src);
2643 }
2644
2645 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2646 assert(VM_Version::supports_evex(), "");
2647 assert(src != xnoreg, "sanity");
2648 InstructionMark im(this);
2649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2650 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2651 attributes.reset_is_clear_context();
2652 attributes.set_is_evex_instruction();
2653 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2654 emit_int8(0x7F);
2655 emit_operand(src, dst);
2656 }
2657
2658 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2659 assert(VM_Version::supports_evex(), "");
2660 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2661 attributes.set_is_evex_instruction();
2662 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2663 emit_int8(0x6F);
2664 emit_int8((unsigned char)(0xC0 | encode));
2665 }
2666
2667 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2668 assert(VM_Version::supports_evex(), "");
2669 InstructionMark im(this);
2670 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2671 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2672 attributes.set_is_evex_instruction();
2673 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2674 emit_int8(0x6F);
2675 emit_operand(dst, src);
2676 }
2677
2678 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2679 assert(VM_Version::supports_evex(), "");
2680 assert(src != xnoreg, "sanity");
2681 InstructionMark im(this);
2682 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2683 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2684 attributes.reset_is_clear_context();
2685 attributes.set_is_evex_instruction();
2686 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2687 emit_int8(0x7F);
2688 emit_operand(src, dst);
2689 }
2690
2691 // Uses zero extension on 64bit
2692
2693 void Assembler::movl(Register dst, int32_t imm32) {
2694 int encode = prefix_and_encode(dst->encoding());
2695 emit_int8((unsigned char)(0xB8 | encode));
2696 emit_int32(imm32);
2697 }
2698
2699 void Assembler::movl(Register dst, Register src) {
2700 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2701 emit_int8((unsigned char)0x8B);
2702 emit_int8((unsigned char)(0xC0 | encode));
2703 }
2704
2705 void Assembler::movl(Register dst, Address src) {
2706 InstructionMark im(this);
2707 prefix(src, dst);
2708 emit_int8((unsigned char)0x8B);
2709 emit_operand(dst, src);
2710 }
2711
2712 void Assembler::movl(Address dst, int32_t imm32) {
2713 InstructionMark im(this);
2714 prefix(dst);
2715 emit_int8((unsigned char)0xC7);
2716 emit_operand(rax, dst, 4);
2717 emit_int32(imm32);
2718 }
2719
2720 void Assembler::movl(Address dst, Register src) {
2721 InstructionMark im(this);
2722 prefix(dst, src);
2723 emit_int8((unsigned char)0x89);
2724 emit_operand(src, dst);
2725 }
2726
2727 // New cpus require to use movsd and movss to avoid partial register stall
2728 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2729 // The selection is done in MacroAssembler::movdbl() and movflt().
2730 void Assembler::movlpd(XMMRegister dst, Address src) {
2731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2732 InstructionMark im(this);
2733 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2734 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2735 attributes.set_rex_vex_w_reverted();
2736 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2737 emit_int8(0x12);
2738 emit_operand(dst, src);
2739 }
2740
2741 void Assembler::movq( MMXRegister dst, Address src ) {
2742 assert( VM_Version::supports_mmx(), "" );
2743 emit_int8(0x0F);
2744 emit_int8(0x6F);
2745 emit_operand(dst, src);
2746 }
2747
2748 void Assembler::movq( Address dst, MMXRegister src ) {
2749 assert( VM_Version::supports_mmx(), "" );
2750 emit_int8(0x0F);
2751 emit_int8(0x7F);
2752 // workaround gcc (3.2.1-7a) bug
2753 // In that version of gcc with only an emit_operand(MMX, Address)
2754 // gcc will tail jump and try and reverse the parameters completely
2755 // obliterating dst in the process. By having a version available
2756 // that doesn't need to swap the args at the tail jump the bug is
2757 // avoided.
2758 emit_operand(dst, src);
2759 }
2760
2761 void Assembler::movq(XMMRegister dst, Address src) {
2762 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2763 InstructionMark im(this);
2764 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2765 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2766 attributes.set_rex_vex_w_reverted();
2767 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2768 emit_int8(0x7E);
2769 emit_operand(dst, src);
2770 }
2771
2772 void Assembler::movq(Address dst, XMMRegister src) {
2773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2774 InstructionMark im(this);
2775 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2776 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2777 attributes.set_rex_vex_w_reverted();
2778 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2779 emit_int8((unsigned char)0xD6);
2780 emit_operand(src, dst);
2781 }
2782
2783 void Assembler::movsbl(Register dst, Address src) { // movsxb
2784 InstructionMark im(this);
2785 prefix(src, dst);
2786 emit_int8(0x0F);
2787 emit_int8((unsigned char)0xBE);
2788 emit_operand(dst, src);
2789 }
2790
2791 void Assembler::movsbl(Register dst, Register src) { // movsxb
2792 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2793 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2794 emit_int8(0x0F);
2795 emit_int8((unsigned char)0xBE);
2796 emit_int8((unsigned char)(0xC0 | encode));
2797 }
2798
2799 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2802 attributes.set_rex_vex_w_reverted();
2803 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2804 emit_int8(0x10);
2805 emit_int8((unsigned char)(0xC0 | encode));
2806 }
2807
2808 void Assembler::movsd(XMMRegister dst, Address src) {
2809 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2810 InstructionMark im(this);
2811 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2812 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2813 attributes.set_rex_vex_w_reverted();
2814 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2815 emit_int8(0x10);
2816 emit_operand(dst, src);
2817 }
2818
2819 void Assembler::movsd(Address dst, XMMRegister src) {
2820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2821 InstructionMark im(this);
2822 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2823 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2824 attributes.reset_is_clear_context();
2825 attributes.set_rex_vex_w_reverted();
2826 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2827 emit_int8(0x11);
2828 emit_operand(src, dst);
2829 }
2830
2831 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2832 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2833 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2834 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2835 emit_int8(0x10);
2836 emit_int8((unsigned char)(0xC0 | encode));
2837 }
2838
2839 void Assembler::movss(XMMRegister dst, Address src) {
2840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2841 InstructionMark im(this);
2842 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2843 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2844 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2845 emit_int8(0x10);
2846 emit_operand(dst, src);
2847 }
2848
2849 void Assembler::movss(Address dst, XMMRegister src) {
2850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2851 InstructionMark im(this);
2852 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2853 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2854 attributes.reset_is_clear_context();
2855 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2856 emit_int8(0x11);
2857 emit_operand(src, dst);
2858 }
2859
2860 void Assembler::movswl(Register dst, Address src) { // movsxw
2861 InstructionMark im(this);
2862 prefix(src, dst);
2863 emit_int8(0x0F);
2864 emit_int8((unsigned char)0xBF);
2865 emit_operand(dst, src);
2866 }
2867
2868 void Assembler::movswl(Register dst, Register src) { // movsxw
2869 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2870 emit_int8(0x0F);
2871 emit_int8((unsigned char)0xBF);
2872 emit_int8((unsigned char)(0xC0 | encode));
2873 }
2874
2875 void Assembler::movw(Address dst, int imm16) {
2876 InstructionMark im(this);
2877
2878 emit_int8(0x66); // switch to 16-bit mode
2879 prefix(dst);
2880 emit_int8((unsigned char)0xC7);
2881 emit_operand(rax, dst, 2);
2882 emit_int16(imm16);
2883 }
2884
2885 void Assembler::movw(Register dst, Address src) {
2886 InstructionMark im(this);
2887 emit_int8(0x66);
2888 prefix(src, dst);
2889 emit_int8((unsigned char)0x8B);
2890 emit_operand(dst, src);
2891 }
2892
2893 void Assembler::movw(Address dst, Register src) {
2894 InstructionMark im(this);
2895 emit_int8(0x66);
2896 prefix(dst, src);
2897 emit_int8((unsigned char)0x89);
2898 emit_operand(src, dst);
2899 }
2900
2901 void Assembler::movzbl(Register dst, Address src) { // movzxb
2902 InstructionMark im(this);
2903 prefix(src, dst);
2904 emit_int8(0x0F);
2905 emit_int8((unsigned char)0xB6);
2906 emit_operand(dst, src);
2907 }
2908
2909 void Assembler::movzbl(Register dst, Register src) { // movzxb
2910 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2911 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2912 emit_int8(0x0F);
2913 emit_int8((unsigned char)0xB6);
2914 emit_int8(0xC0 | encode);
2915 }
2916
2917 void Assembler::movzwl(Register dst, Address src) { // movzxw
2918 InstructionMark im(this);
2919 prefix(src, dst);
2920 emit_int8(0x0F);
2921 emit_int8((unsigned char)0xB7);
2922 emit_operand(dst, src);
2923 }
2924
2925 void Assembler::movzwl(Register dst, Register src) { // movzxw
2926 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2927 emit_int8(0x0F);
2928 emit_int8((unsigned char)0xB7);
2929 emit_int8(0xC0 | encode);
2930 }
2931
2932 void Assembler::mull(Address src) {
2933 InstructionMark im(this);
2934 prefix(src);
2935 emit_int8((unsigned char)0xF7);
2936 emit_operand(rsp, src);
2937 }
2938
2939 void Assembler::mull(Register src) {
2940 int encode = prefix_and_encode(src->encoding());
2941 emit_int8((unsigned char)0xF7);
2942 emit_int8((unsigned char)(0xE0 | encode));
2943 }
2944
2945 void Assembler::mulsd(XMMRegister dst, Address src) {
2946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2947 InstructionMark im(this);
2948 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2949 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2950 attributes.set_rex_vex_w_reverted();
2951 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2952 emit_int8(0x59);
2953 emit_operand(dst, src);
2954 }
2955
2956 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2957 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2958 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2959 attributes.set_rex_vex_w_reverted();
2960 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2961 emit_int8(0x59);
2962 emit_int8((unsigned char)(0xC0 | encode));
2963 }
2964
2965 void Assembler::mulss(XMMRegister dst, Address src) {
2966 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2967 InstructionMark im(this);
2968 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2969 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2970 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2971 emit_int8(0x59);
2972 emit_operand(dst, src);
2973 }
2974
2975 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2976 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2977 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2979 emit_int8(0x59);
2980 emit_int8((unsigned char)(0xC0 | encode));
2981 }
2982
2983 void Assembler::negl(Register dst) {
2984 int encode = prefix_and_encode(dst->encoding());
2985 emit_int8((unsigned char)0xF7);
2986 emit_int8((unsigned char)(0xD8 | encode));
2987 }
2988
2989 void Assembler::nop(int i) {
2990 #ifdef ASSERT
2991 assert(i > 0, " ");
2992 // The fancy nops aren't currently recognized by debuggers making it a
2993 // pain to disassemble code while debugging. If asserts are on clearly
2994 // speed is not an issue so simply use the single byte traditional nop
2995 // to do alignment.
2996
2997 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2998 return;
2999
3000 #endif // ASSERT
3001
3002 if (UseAddressNop && VM_Version::is_intel()) {
3003 //
3004 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3005 // 1: 0x90
3006 // 2: 0x66 0x90
3007 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3008 // 4: 0x0F 0x1F 0x40 0x00
3009 // 5: 0x0F 0x1F 0x44 0x00 0x00
3010 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3011 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3012 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3013 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3014 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3015 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3016
3017 // The rest coding is Intel specific - don't use consecutive address nops
3018
3019 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3020 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3021 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3022 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3023
3024 while(i >= 15) {
3025 // For Intel don't generate consecutive addess nops (mix with regular nops)
3026 i -= 15;
3027 emit_int8(0x66); // size prefix
3028 emit_int8(0x66); // size prefix
3029 emit_int8(0x66); // size prefix
3030 addr_nop_8();
3031 emit_int8(0x66); // size prefix
3032 emit_int8(0x66); // size prefix
3033 emit_int8(0x66); // size prefix
3034 emit_int8((unsigned char)0x90);
3035 // nop
3036 }
3037 switch (i) {
3038 case 14:
3039 emit_int8(0x66); // size prefix
3040 case 13:
3041 emit_int8(0x66); // size prefix
3042 case 12:
3043 addr_nop_8();
3044 emit_int8(0x66); // size prefix
3045 emit_int8(0x66); // size prefix
3046 emit_int8(0x66); // size prefix
3047 emit_int8((unsigned char)0x90);
3048 // nop
3049 break;
3050 case 11:
3051 emit_int8(0x66); // size prefix
3052 case 10:
3053 emit_int8(0x66); // size prefix
3054 case 9:
3055 emit_int8(0x66); // size prefix
3056 case 8:
3057 addr_nop_8();
3058 break;
3059 case 7:
3060 addr_nop_7();
3061 break;
3062 case 6:
3063 emit_int8(0x66); // size prefix
3064 case 5:
3065 addr_nop_5();
3066 break;
3067 case 4:
3068 addr_nop_4();
3069 break;
3070 case 3:
3071 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3072 emit_int8(0x66); // size prefix
3073 case 2:
3074 emit_int8(0x66); // size prefix
3075 case 1:
3076 emit_int8((unsigned char)0x90);
3077 // nop
3078 break;
3079 default:
3080 assert(i == 0, " ");
3081 }
3082 return;
3083 }
3084 if (UseAddressNop && VM_Version::is_amd()) {
3085 //
3086 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3087 // 1: 0x90
3088 // 2: 0x66 0x90
3089 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3090 // 4: 0x0F 0x1F 0x40 0x00
3091 // 5: 0x0F 0x1F 0x44 0x00 0x00
3092 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3093 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3094 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3095 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3096 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3097 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3098
3099 // The rest coding is AMD specific - use consecutive address nops
3100
3101 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3102 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3103 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3104 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3105 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3106 // Size prefixes (0x66) are added for larger sizes
3107
3108 while(i >= 22) {
3109 i -= 11;
3110 emit_int8(0x66); // size prefix
3111 emit_int8(0x66); // size prefix
3112 emit_int8(0x66); // size prefix
3113 addr_nop_8();
3114 }
3115 // Generate first nop for size between 21-12
3116 switch (i) {
3117 case 21:
3118 i -= 1;
3119 emit_int8(0x66); // size prefix
3120 case 20:
3121 case 19:
3122 i -= 1;
3123 emit_int8(0x66); // size prefix
3124 case 18:
3125 case 17:
3126 i -= 1;
3127 emit_int8(0x66); // size prefix
3128 case 16:
3129 case 15:
3130 i -= 8;
3131 addr_nop_8();
3132 break;
3133 case 14:
3134 case 13:
3135 i -= 7;
3136 addr_nop_7();
3137 break;
3138 case 12:
3139 i -= 6;
3140 emit_int8(0x66); // size prefix
3141 addr_nop_5();
3142 break;
3143 default:
3144 assert(i < 12, " ");
3145 }
3146
3147 // Generate second nop for size between 11-1
3148 switch (i) {
3149 case 11:
3150 emit_int8(0x66); // size prefix
3151 case 10:
3152 emit_int8(0x66); // size prefix
3153 case 9:
3154 emit_int8(0x66); // size prefix
3155 case 8:
3156 addr_nop_8();
3157 break;
3158 case 7:
3159 addr_nop_7();
3160 break;
3161 case 6:
3162 emit_int8(0x66); // size prefix
3163 case 5:
3164 addr_nop_5();
3165 break;
3166 case 4:
3167 addr_nop_4();
3168 break;
3169 case 3:
3170 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3171 emit_int8(0x66); // size prefix
3172 case 2:
3173 emit_int8(0x66); // size prefix
3174 case 1:
3175 emit_int8((unsigned char)0x90);
3176 // nop
3177 break;
3178 default:
3179 assert(i == 0, " ");
3180 }
3181 return;
3182 }
3183
3184 if (UseAddressNop && VM_Version::is_zx()) {
3185 //
3186 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3187 // 1: 0x90
3188 // 2: 0x66 0x90
3189 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3190 // 4: 0x0F 0x1F 0x40 0x00
3191 // 5: 0x0F 0x1F 0x44 0x00 0x00
3192 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3193 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3194 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3195 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3196 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3197 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3198
3199 // The rest coding is ZX specific - don't use consecutive address nops
3200
3201 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3202 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3203 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3204 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3205
3206 while (i >= 15) {
3207 // For ZX don't generate consecutive addess nops (mix with regular nops)
3208 i -= 15;
3209 emit_int8(0x66); // size prefix
3210 emit_int8(0x66); // size prefix
3211 emit_int8(0x66); // size prefix
3212 addr_nop_8();
3213 emit_int8(0x66); // size prefix
3214 emit_int8(0x66); // size prefix
3215 emit_int8(0x66); // size prefix
3216 emit_int8((unsigned char)0x90);
3217 // nop
3218 }
3219 switch (i) {
3220 case 14:
3221 emit_int8(0x66); // size prefix
3222 case 13:
3223 emit_int8(0x66); // size prefix
3224 case 12:
3225 addr_nop_8();
3226 emit_int8(0x66); // size prefix
3227 emit_int8(0x66); // size prefix
3228 emit_int8(0x66); // size prefix
3229 emit_int8((unsigned char)0x90);
3230 // nop
3231 break;
3232 case 11:
3233 emit_int8(0x66); // size prefix
3234 case 10:
3235 emit_int8(0x66); // size prefix
3236 case 9:
3237 emit_int8(0x66); // size prefix
3238 case 8:
3239 addr_nop_8();
3240 break;
3241 case 7:
3242 addr_nop_7();
3243 break;
3244 case 6:
3245 emit_int8(0x66); // size prefix
3246 case 5:
3247 addr_nop_5();
3248 break;
3249 case 4:
3250 addr_nop_4();
3251 break;
3252 case 3:
3253 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3254 emit_int8(0x66); // size prefix
3255 case 2:
3256 emit_int8(0x66); // size prefix
3257 case 1:
3258 emit_int8((unsigned char)0x90);
3259 // nop
3260 break;
3261 default:
3262 assert(i == 0, " ");
3263 }
3264 return;
3265 }
3266
3267 // Using nops with size prefixes "0x66 0x90".
3268 // From AMD Optimization Guide:
3269 // 1: 0x90
3270 // 2: 0x66 0x90
3271 // 3: 0x66 0x66 0x90
3272 // 4: 0x66 0x66 0x66 0x90
3273 // 5: 0x66 0x66 0x90 0x66 0x90
3274 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3275 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3276 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3277 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3278 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3279 //
3280 while(i > 12) {
3281 i -= 4;
3282 emit_int8(0x66); // size prefix
3283 emit_int8(0x66);
3284 emit_int8(0x66);
3285 emit_int8((unsigned char)0x90);
3286 // nop
3287 }
3288 // 1 - 12 nops
3289 if(i > 8) {
3290 if(i > 9) {
3291 i -= 1;
3292 emit_int8(0x66);
3293 }
3294 i -= 3;
3295 emit_int8(0x66);
3296 emit_int8(0x66);
3297 emit_int8((unsigned char)0x90);
3298 }
3299 // 1 - 8 nops
3300 if(i > 4) {
3301 if(i > 6) {
3302 i -= 1;
3303 emit_int8(0x66);
3304 }
3305 i -= 3;
3306 emit_int8(0x66);
3307 emit_int8(0x66);
3308 emit_int8((unsigned char)0x90);
3309 }
3310 switch (i) {
3311 case 4:
3312 emit_int8(0x66);
3313 case 3:
3314 emit_int8(0x66);
3315 case 2:
3316 emit_int8(0x66);
3317 case 1:
3318 emit_int8((unsigned char)0x90);
3319 break;
3320 default:
3321 assert(i == 0, " ");
3322 }
3323 }
3324
3325 void Assembler::notl(Register dst) {
3326 int encode = prefix_and_encode(dst->encoding());
3327 emit_int8((unsigned char)0xF7);
3328 emit_int8((unsigned char)(0xD0 | encode));
3329 }
3330
3331 void Assembler::orl(Address dst, int32_t imm32) {
3332 InstructionMark im(this);
3333 prefix(dst);
3334 emit_arith_operand(0x81, rcx, dst, imm32);
3335 }
3336
3337 void Assembler::orl(Register dst, int32_t imm32) {
3338 prefix(dst);
3339 emit_arith(0x81, 0xC8, dst, imm32);
3340 }
3341
3342 void Assembler::orl(Register dst, Address src) {
3343 InstructionMark im(this);
3344 prefix(src, dst);
3345 emit_int8(0x0B);
3346 emit_operand(dst, src);
3347 }
3348
3349 void Assembler::orl(Register dst, Register src) {
3350 (void) prefix_and_encode(dst->encoding(), src->encoding());
3351 emit_arith(0x0B, 0xC0, dst, src);
3352 }
3353
3354 void Assembler::orl(Address dst, Register src) {
3355 InstructionMark im(this);
3356 prefix(dst, src);
3357 emit_int8(0x09);
3358 emit_operand(src, dst);
3359 }
3360
3361 void Assembler::orb(Address dst, int imm8) {
3362 InstructionMark im(this);
3363 prefix(dst);
3364 emit_int8((unsigned char)0x80);
3365 emit_operand(rcx, dst, 1);
3366 emit_int8(imm8);
3367 }
3368
3369 void Assembler::packuswb(XMMRegister dst, Address src) {
3370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3371 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3372 InstructionMark im(this);
3373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3374 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3375 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3376 emit_int8(0x67);
3377 emit_operand(dst, src);
3378 }
3379
3380 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3383 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3384 emit_int8(0x67);
3385 emit_int8((unsigned char)(0xC0 | encode));
3386 }
3387
3388 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3389 assert(UseAVX > 0, "some form of AVX must be enabled");
3390 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3391 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3392 emit_int8(0x67);
3393 emit_int8((unsigned char)(0xC0 | encode));
3394 }
3395
3396 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3397 assert(VM_Version::supports_avx2(), "");
3398 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3399 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3400 emit_int8(0x00);
3401 emit_int8(0xC0 | encode);
3402 emit_int8(imm8);
3403 }
3404
3405 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3406 assert(VM_Version::supports_avx2(), "");
3407 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3408 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3409 emit_int8(0x46);
3410 emit_int8(0xC0 | encode);
3411 emit_int8(imm8);
3412 }
3413
3414 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3415 assert(VM_Version::supports_avx(), "");
3416 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3417 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3418 emit_int8(0x06);
3419 emit_int8(0xC0 | encode);
3420 emit_int8(imm8);
3421 }
3422
3423
3424 void Assembler::pause() {
3425 emit_int8((unsigned char)0xF3);
3426 emit_int8((unsigned char)0x90);
3427 }
3428
3429 void Assembler::ud2() {
3430 emit_int8(0x0F);
3431 emit_int8(0x0B);
3432 }
3433
3434 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3435 assert(VM_Version::supports_sse4_2(), "");
3436 InstructionMark im(this);
3437 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3438 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3439 emit_int8(0x61);
3440 emit_operand(dst, src);
3441 emit_int8(imm8);
3442 }
3443
3444 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3445 assert(VM_Version::supports_sse4_2(), "");
3446 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3447 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3448 emit_int8(0x61);
3449 emit_int8((unsigned char)(0xC0 | encode));
3450 emit_int8(imm8);
3451 }
3452
3453 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3454 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3455 assert(VM_Version::supports_sse2(), "");
3456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3457 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3458 emit_int8(0x74);
3459 emit_int8((unsigned char)(0xC0 | encode));
3460 }
3461
3462 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3463 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3464 assert(VM_Version::supports_avx(), "");
3465 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3466 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3467 emit_int8(0x74);
3468 emit_int8((unsigned char)(0xC0 | encode));
3469 }
3470
3471 // In this context, kdst is written the mask used to process the equal components
3472 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3473 assert(VM_Version::supports_avx512bw(), "");
3474 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3475 attributes.set_is_evex_instruction();
3476 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3477 emit_int8(0x74);
3478 emit_int8((unsigned char)(0xC0 | encode));
3479 }
3480
3481 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3482 assert(VM_Version::supports_avx512vlbw(), "");
3483 InstructionMark im(this);
3484 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3485 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3486 attributes.set_is_evex_instruction();
3487 int dst_enc = kdst->encoding();
3488 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3489 emit_int8(0x64);
3490 emit_operand(as_Register(dst_enc), src);
3491 }
3492
3493 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3494 assert(is_vector_masking(), "");
3495 assert(VM_Version::supports_avx512vlbw(), "");
3496 InstructionMark im(this);
3497 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3498 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3499 attributes.reset_is_clear_context();
3500 attributes.set_embedded_opmask_register_specifier(mask);
3501 attributes.set_is_evex_instruction();
3502 int dst_enc = kdst->encoding();
3503 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3504 emit_int8(0x64);
3505 emit_operand(as_Register(dst_enc), src);
3506 }
3507
3508 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3509 assert(VM_Version::supports_avx512vlbw(), "");
3510 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3511 attributes.set_is_evex_instruction();
3512 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3513 emit_int8(0x3E);
3514 emit_int8((unsigned char)(0xC0 | encode));
3515 emit_int8(vcc);
3516 }
3517
3518 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3519 assert(is_vector_masking(), "");
3520 assert(VM_Version::supports_avx512vlbw(), "");
3521 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3522 attributes.reset_is_clear_context();
3523 attributes.set_embedded_opmask_register_specifier(mask);
3524 attributes.set_is_evex_instruction();
3525 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3526 emit_int8(0x3E);
3527 emit_int8((unsigned char)(0xC0 | encode));
3528 emit_int8(vcc);
3529 }
3530
3531 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3532 assert(VM_Version::supports_avx512vlbw(), "");
3533 InstructionMark im(this);
3534 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3535 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3536 attributes.set_is_evex_instruction();
3537 int dst_enc = kdst->encoding();
3538 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3539 emit_int8(0x3E);
3540 emit_operand(as_Register(dst_enc), src);
3541 emit_int8(vcc);
3542 }
3543
3544 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3545 assert(VM_Version::supports_avx512bw(), "");
3546 InstructionMark im(this);
3547 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3548 attributes.set_is_evex_instruction();
3549 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3550 int dst_enc = kdst->encoding();
3551 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3552 emit_int8(0x74);
3553 emit_operand(as_Register(dst_enc), src);
3554 }
3555
3556 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3557 assert(VM_Version::supports_avx512vlbw(), "");
3558 assert(is_vector_masking(), ""); // For stub code use only
3559 InstructionMark im(this);
3560 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3561 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3562 attributes.reset_is_clear_context();
3563 attributes.set_embedded_opmask_register_specifier(mask);
3564 attributes.set_is_evex_instruction();
3565 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3566 emit_int8(0x74);
3567 emit_operand(as_Register(kdst->encoding()), src);
3568 }
3569
3570 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3571 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3572 assert(VM_Version::supports_sse2(), "");
3573 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3574 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3575 emit_int8(0x75);
3576 emit_int8((unsigned char)(0xC0 | encode));
3577 }
3578
3579 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3580 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3581 assert(VM_Version::supports_avx(), "");
3582 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3583 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3584 emit_int8(0x75);
3585 emit_int8((unsigned char)(0xC0 | encode));
3586 }
3587
3588 // In this context, kdst is written the mask used to process the equal components
3589 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3590 assert(VM_Version::supports_avx512bw(), "");
3591 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3592 attributes.set_is_evex_instruction();
3593 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3594 emit_int8(0x75);
3595 emit_int8((unsigned char)(0xC0 | encode));
3596 }
3597
3598 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3599 assert(VM_Version::supports_avx512bw(), "");
3600 InstructionMark im(this);
3601 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3602 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3603 attributes.set_is_evex_instruction();
3604 int dst_enc = kdst->encoding();
3605 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3606 emit_int8(0x75);
3607 emit_operand(as_Register(dst_enc), src);
3608 }
3609
3610 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3611 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3612 assert(VM_Version::supports_sse2(), "");
3613 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3614 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3615 emit_int8(0x76);
3616 emit_int8((unsigned char)(0xC0 | encode));
3617 }
3618
3619 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3620 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3621 assert(VM_Version::supports_avx(), "");
3622 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3623 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3624 emit_int8(0x76);
3625 emit_int8((unsigned char)(0xC0 | encode));
3626 }
3627
3628 // In this context, kdst is written the mask used to process the equal components
3629 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3630 assert(VM_Version::supports_evex(), "");
3631 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3632 attributes.set_is_evex_instruction();
3633 attributes.reset_is_clear_context();
3634 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3635 emit_int8(0x76);
3636 emit_int8((unsigned char)(0xC0 | encode));
3637 }
3638
3639 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3640 assert(VM_Version::supports_evex(), "");
3641 InstructionMark im(this);
3642 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3643 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3644 attributes.reset_is_clear_context();
3645 attributes.set_is_evex_instruction();
3646 int dst_enc = kdst->encoding();
3647 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x76);
3649 emit_operand(as_Register(dst_enc), src);
3650 }
3651
3652 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3653 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3654 assert(VM_Version::supports_sse4_1(), "");
3655 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3656 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3657 emit_int8(0x29);
3658 emit_int8((unsigned char)(0xC0 | encode));
3659 }
3660
3661 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3662 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3663 assert(VM_Version::supports_avx(), "");
3664 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3665 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3666 emit_int8(0x29);
3667 emit_int8((unsigned char)(0xC0 | encode));
3668 }
3669
3670 // In this context, kdst is written the mask used to process the equal components
3671 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3672 assert(VM_Version::supports_evex(), "");
3673 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3674 attributes.reset_is_clear_context();
3675 attributes.set_is_evex_instruction();
3676 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3677 emit_int8(0x29);
3678 emit_int8((unsigned char)(0xC0 | encode));
3679 }
3680
3681 // In this context, kdst is written the mask used to process the equal components
3682 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3683 assert(VM_Version::supports_evex(), "");
3684 InstructionMark im(this);
3685 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3686 attributes.reset_is_clear_context();
3687 attributes.set_is_evex_instruction();
3688 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3689 int dst_enc = kdst->encoding();
3690 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3691 emit_int8(0x29);
3692 emit_operand(as_Register(dst_enc), src);
3693 }
3694
3695 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3696 assert(VM_Version::supports_sse2(), "");
3697 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3698 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3699 emit_int8((unsigned char)0xD7);
3700 emit_int8((unsigned char)(0xC0 | encode));
3701 }
3702
3703 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3704 assert(VM_Version::supports_avx2(), "");
3705 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3706 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3707 emit_int8((unsigned char)0xD7);
3708 emit_int8((unsigned char)(0xC0 | encode));
3709 }
3710
3711 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3712 assert(VM_Version::supports_sse4_1(), "");
3713 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3714 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3715 emit_int8(0x16);
3716 emit_int8((unsigned char)(0xC0 | encode));
3717 emit_int8(imm8);
3718 }
3719
3720 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3721 assert(VM_Version::supports_sse4_1(), "");
3722 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3723 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3724 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3725 emit_int8(0x16);
3726 emit_operand(src, dst);
3727 emit_int8(imm8);
3728 }
3729
3730 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3731 assert(VM_Version::supports_sse4_1(), "");
3732 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3733 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3734 emit_int8(0x16);
3735 emit_int8((unsigned char)(0xC0 | encode));
3736 emit_int8(imm8);
3737 }
3738
3739 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3740 assert(VM_Version::supports_sse4_1(), "");
3741 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3742 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3743 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3744 emit_int8(0x16);
3745 emit_operand(src, dst);
3746 emit_int8(imm8);
3747 }
3748
3749 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3750 assert(VM_Version::supports_sse2(), "");
3751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3752 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3753 emit_int8((unsigned char)0xC5);
3754 emit_int8((unsigned char)(0xC0 | encode));
3755 emit_int8(imm8);
3756 }
3757
3758 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3759 assert(VM_Version::supports_sse4_1(), "");
3760 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3761 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3762 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3763 emit_int8((unsigned char)0x15);
3764 emit_operand(src, dst);
3765 emit_int8(imm8);
3766 }
3767
3768 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3769 assert(VM_Version::supports_sse4_1(), "");
3770 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3771 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3772 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3773 emit_int8(0x14);
3774 emit_operand(src, dst);
3775 emit_int8(imm8);
3776 }
3777
3778 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3779 assert(VM_Version::supports_sse4_1(), "");
3780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3781 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3782 emit_int8(0x22);
3783 emit_int8((unsigned char)(0xC0 | encode));
3784 emit_int8(imm8);
3785 }
3786
3787 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3788 assert(VM_Version::supports_sse4_1(), "");
3789 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3790 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3791 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3792 emit_int8(0x22);
3793 emit_operand(dst,src);
3794 emit_int8(imm8);
3795 }
3796
3797 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3798 assert(VM_Version::supports_sse4_1(), "");
3799 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3800 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3801 emit_int8(0x22);
3802 emit_int8((unsigned char)(0xC0 | encode));
3803 emit_int8(imm8);
3804 }
3805
3806 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3807 assert(VM_Version::supports_sse4_1(), "");
3808 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3809 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3810 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3811 emit_int8(0x22);
3812 emit_operand(dst, src);
3813 emit_int8(imm8);
3814 }
3815
3816 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3817 assert(VM_Version::supports_sse2(), "");
3818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3819 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3820 emit_int8((unsigned char)0xC4);
3821 emit_int8((unsigned char)(0xC0 | encode));
3822 emit_int8(imm8);
3823 }
3824
3825 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3826 assert(VM_Version::supports_sse2(), "");
3827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3828 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3829 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3830 emit_int8((unsigned char)0xC4);
3831 emit_operand(dst, src);
3832 emit_int8(imm8);
3833 }
3834
3835 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3836 assert(VM_Version::supports_sse4_1(), "");
3837 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3838 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3839 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3840 emit_int8(0x20);
3841 emit_operand(dst, src);
3842 emit_int8(imm8);
3843 }
3844
3845 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3846 assert(VM_Version::supports_sse4_1(), "");
3847 InstructionMark im(this);
3848 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3849 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3850 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3851 emit_int8(0x30);
3852 emit_operand(dst, src);
3853 }
3854
3855 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3856 assert(VM_Version::supports_sse4_1(), "");
3857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3858 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3859 emit_int8(0x30);
3860 emit_int8((unsigned char)(0xC0 | encode));
3861 }
3862
3863 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3864 assert(VM_Version::supports_avx(), "");
3865 InstructionMark im(this);
3866 assert(dst != xnoreg, "sanity");
3867 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3868 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3869 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3870 emit_int8(0x30);
3871 emit_operand(dst, src);
3872 }
3873
3874 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3875 assert(is_vector_masking(), "");
3876 assert(VM_Version::supports_avx512vlbw(), "");
3877 assert(dst != xnoreg, "sanity");
3878 InstructionMark im(this);
3879 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3880 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3881 attributes.set_embedded_opmask_register_specifier(mask);
3882 attributes.set_is_evex_instruction();
3883 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3884 emit_int8(0x30);
3885 emit_operand(dst, src);
3886 }
3887
3888 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3889 assert(VM_Version::supports_avx512vlbw(), "");
3890 assert(src != xnoreg, "sanity");
3891 InstructionMark im(this);
3892 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3893 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3894 attributes.set_is_evex_instruction();
3895 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3896 emit_int8(0x30);
3897 emit_operand(src, dst);
3898 }
3899
3900 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3901 assert(is_vector_masking(), "");
3902 assert(VM_Version::supports_avx512vlbw(), "");
3903 assert(src != xnoreg, "sanity");
3904 InstructionMark im(this);
3905 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3906 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3907 attributes.reset_is_clear_context();
3908 attributes.set_embedded_opmask_register_specifier(mask);
3909 attributes.set_is_evex_instruction();
3910 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3911 emit_int8(0x30);
3912 emit_operand(src, dst);
3913 }
3914
3915 // generic
3916 void Assembler::pop(Register dst) {
3917 int encode = prefix_and_encode(dst->encoding());
3918 emit_int8(0x58 | encode);
3919 }
3920
3921 void Assembler::popcntl(Register dst, Address src) {
3922 assert(VM_Version::supports_popcnt(), "must support");
3923 InstructionMark im(this);
3924 emit_int8((unsigned char)0xF3);
3925 prefix(src, dst);
3926 emit_int8(0x0F);
3927 emit_int8((unsigned char)0xB8);
3928 emit_operand(dst, src);
3929 }
3930
3931 void Assembler::popcntl(Register dst, Register src) {
3932 assert(VM_Version::supports_popcnt(), "must support");
3933 emit_int8((unsigned char)0xF3);
3934 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3935 emit_int8(0x0F);
3936 emit_int8((unsigned char)0xB8);
3937 emit_int8((unsigned char)(0xC0 | encode));
3938 }
3939
3940 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
3941 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
3942 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3943 attributes.set_is_evex_instruction();
3944 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3945 emit_int8(0x55);
3946 emit_int8((unsigned char)(0xC0 | encode));
3947 }
3948
3949 void Assembler::popf() {
3950 emit_int8((unsigned char)0x9D);
3951 }
3952
3953 #ifndef _LP64 // no 32bit push/pop on amd64
3954 void Assembler::popl(Address dst) {
3955 // NOTE: this will adjust stack by 8byte on 64bits
3956 InstructionMark im(this);
3957 prefix(dst);
3958 emit_int8((unsigned char)0x8F);
3959 emit_operand(rax, dst);
3960 }
3961 #endif
3962
3963 void Assembler::prefetch_prefix(Address src) {
3964 prefix(src);
3965 emit_int8(0x0F);
3966 }
3967
3968 void Assembler::prefetchnta(Address src) {
3969 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3970 InstructionMark im(this);
3971 prefetch_prefix(src);
3972 emit_int8(0x18);
3973 emit_operand(rax, src); // 0, src
3974 }
3975
3976 void Assembler::prefetchr(Address src) {
3977 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3978 InstructionMark im(this);
3979 prefetch_prefix(src);
3980 emit_int8(0x0D);
3981 emit_operand(rax, src); // 0, src
3982 }
3983
3984 void Assembler::prefetcht0(Address src) {
3985 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3986 InstructionMark im(this);
3987 prefetch_prefix(src);
3988 emit_int8(0x18);
3989 emit_operand(rcx, src); // 1, src
3990 }
3991
3992 void Assembler::prefetcht1(Address src) {
3993 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3994 InstructionMark im(this);
3995 prefetch_prefix(src);
3996 emit_int8(0x18);
3997 emit_operand(rdx, src); // 2, src
3998 }
3999
4000 void Assembler::prefetcht2(Address src) {
4001 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4002 InstructionMark im(this);
4003 prefetch_prefix(src);
4004 emit_int8(0x18);
4005 emit_operand(rbx, src); // 3, src
4006 }
4007
4008 void Assembler::prefetchw(Address src) {
4009 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4010 InstructionMark im(this);
4011 prefetch_prefix(src);
4012 emit_int8(0x0D);
4013 emit_operand(rcx, src); // 1, src
4014 }
4015
4016 void Assembler::prefix(Prefix p) {
4017 emit_int8(p);
4018 }
4019
4020 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4021 assert(VM_Version::supports_ssse3(), "");
4022 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4024 emit_int8(0x00);
4025 emit_int8((unsigned char)(0xC0 | encode));
4026 }
4027
4028 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4029 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4030 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4031 0, "");
4032 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4033 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4034 emit_int8(0x00);
4035 emit_int8((unsigned char)(0xC0 | encode));
4036 }
4037
4038 void Assembler::pshufb(XMMRegister dst, Address src) {
4039 assert(VM_Version::supports_ssse3(), "");
4040 InstructionMark im(this);
4041 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4042 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4043 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4044 emit_int8(0x00);
4045 emit_operand(dst, src);
4046 }
4047
4048 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4049 assert(isByte(mode), "invalid value");
4050 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4051 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4052 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4053 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4054 emit_int8(0x70);
4055 emit_int8((unsigned char)(0xC0 | encode));
4056 emit_int8(mode & 0xFF);
4057 }
4058
4059 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4060 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4061 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4062 0, "");
4063 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4064 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4065 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4066 emit_int8(0x70);
4067 emit_int8((unsigned char)(0xC0 | encode));
4068 emit_int8(mode & 0xFF);
4069 }
4070
4071 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4072 assert(isByte(mode), "invalid value");
4073 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4074 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4075 InstructionMark im(this);
4076 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4077 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4078 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4079 emit_int8(0x70);
4080 emit_operand(dst, src);
4081 emit_int8(mode & 0xFF);
4082 }
4083
4084 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4085 assert(isByte(mode), "invalid value");
4086 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4087 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4088 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4089 emit_int8(0x70);
4090 emit_int8((unsigned char)(0xC0 | encode));
4091 emit_int8(mode & 0xFF);
4092 }
4093
4094 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4095 assert(isByte(mode), "invalid value");
4096 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4097 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4098 InstructionMark im(this);
4099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4100 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4101 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4102 emit_int8(0x70);
4103 emit_operand(dst, src);
4104 emit_int8(mode & 0xFF);
4105 }
4106 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4107 assert(VM_Version::supports_evex(), "requires EVEX support");
4108 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4109 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4110 attributes.set_is_evex_instruction();
4111 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4112 emit_int8(0x43);
4113 emit_int8((unsigned char)(0xC0 | encode));
4114 emit_int8(imm8 & 0xFF);
4115 }
4116
4117 void Assembler::psrldq(XMMRegister dst, int shift) {
4118 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4119 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4121 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4122 emit_int8(0x73);
4123 emit_int8((unsigned char)(0xC0 | encode));
4124 emit_int8(shift);
4125 }
4126
4127 void Assembler::pslldq(XMMRegister dst, int shift) {
4128 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4130 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4131 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4132 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4133 emit_int8(0x73);
4134 emit_int8((unsigned char)(0xC0 | encode));
4135 emit_int8(shift);
4136 }
4137
4138 void Assembler::ptest(XMMRegister dst, Address src) {
4139 assert(VM_Version::supports_sse4_1(), "");
4140 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4141 InstructionMark im(this);
4142 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4143 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4144 emit_int8(0x17);
4145 emit_operand(dst, src);
4146 }
4147
4148 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4149 assert(VM_Version::supports_sse4_1(), "");
4150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4151 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4152 emit_int8(0x17);
4153 emit_int8((unsigned char)(0xC0 | encode));
4154 }
4155
4156 void Assembler::vptest(XMMRegister dst, Address src) {
4157 assert(VM_Version::supports_avx(), "");
4158 InstructionMark im(this);
4159 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4160 assert(dst != xnoreg, "sanity");
4161 // swap src<->dst for encoding
4162 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4163 emit_int8(0x17);
4164 emit_operand(dst, src);
4165 }
4166
4167 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4168 assert(VM_Version::supports_avx(), "");
4169 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4170 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4171 emit_int8(0x17);
4172 emit_int8((unsigned char)(0xC0 | encode));
4173 }
4174
4175 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4177 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4178 InstructionMark im(this);
4179 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4180 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4181 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4182 emit_int8(0x60);
4183 emit_operand(dst, src);
4184 }
4185
4186 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4189 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4190 emit_int8(0x60);
4191 emit_int8((unsigned char)(0xC0 | encode));
4192 }
4193
4194 void Assembler::punpckldq(XMMRegister dst, Address src) {
4195 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4196 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4197 InstructionMark im(this);
4198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4199 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4200 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4201 emit_int8(0x62);
4202 emit_operand(dst, src);
4203 }
4204
4205 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4207 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4208 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4209 emit_int8(0x62);
4210 emit_int8((unsigned char)(0xC0 | encode));
4211 }
4212
4213 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4215 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4216 attributes.set_rex_vex_w_reverted();
4217 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4218 emit_int8(0x6C);
4219 emit_int8((unsigned char)(0xC0 | encode));
4220 }
4221
4222 void Assembler::push(int32_t imm32) {
4223 // in 64bits we push 64bits onto the stack but only
4224 // take a 32bit immediate
4225 emit_int8(0x68);
4226 emit_int32(imm32);
4227 }
4228
4229 void Assembler::push(Register src) {
4230 int encode = prefix_and_encode(src->encoding());
4231
4232 emit_int8(0x50 | encode);
4233 }
4234
4235 void Assembler::pushf() {
4236 emit_int8((unsigned char)0x9C);
4237 }
4238
4239 #ifndef _LP64 // no 32bit push/pop on amd64
4240 void Assembler::pushl(Address src) {
4241 // Note this will push 64bit on 64bit
4242 InstructionMark im(this);
4243 prefix(src);
4244 emit_int8((unsigned char)0xFF);
4245 emit_operand(rsi, src);
4246 }
4247 #endif
4248
4249 void Assembler::rcll(Register dst, int imm8) {
4250 assert(isShiftCount(imm8), "illegal shift count");
4251 int encode = prefix_and_encode(dst->encoding());
4252 if (imm8 == 1) {
4253 emit_int8((unsigned char)0xD1);
4254 emit_int8((unsigned char)(0xD0 | encode));
4255 } else {
4256 emit_int8((unsigned char)0xC1);
4257 emit_int8((unsigned char)0xD0 | encode);
4258 emit_int8(imm8);
4259 }
4260 }
4261
4262 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4263 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4266 emit_int8(0x53);
4267 emit_int8((unsigned char)(0xC0 | encode));
4268 }
4269
4270 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4271 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4272 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4273 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4274 emit_int8(0x53);
4275 emit_int8((unsigned char)(0xC0 | encode));
4276 }
4277
4278 void Assembler::rdtsc() {
4279 emit_int8((unsigned char)0x0F);
4280 emit_int8((unsigned char)0x31);
4281 }
4282
4283 // copies data from [esi] to [edi] using rcx pointer sized words
4284 // generic
4285 void Assembler::rep_mov() {
4286 emit_int8((unsigned char)0xF3);
4287 // MOVSQ
4288 LP64_ONLY(prefix(REX_W));
4289 emit_int8((unsigned char)0xA5);
4290 }
4291
4292 // sets rcx bytes with rax, value at [edi]
4293 void Assembler::rep_stosb() {
4294 emit_int8((unsigned char)0xF3); // REP
4295 LP64_ONLY(prefix(REX_W));
4296 emit_int8((unsigned char)0xAA); // STOSB
4297 }
4298
4299 // sets rcx pointer sized words with rax, value at [edi]
4300 // generic
4301 void Assembler::rep_stos() {
4302 emit_int8((unsigned char)0xF3); // REP
4303 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4304 emit_int8((unsigned char)0xAB);
4305 }
4306
4307 // scans rcx pointer sized words at [edi] for occurance of rax,
4308 // generic
4309 void Assembler::repne_scan() { // repne_scan
4310 emit_int8((unsigned char)0xF2);
4311 // SCASQ
4312 LP64_ONLY(prefix(REX_W));
4313 emit_int8((unsigned char)0xAF);
4314 }
4315
4316 #ifdef _LP64
4317 // scans rcx 4 byte words at [edi] for occurance of rax,
4318 // generic
4319 void Assembler::repne_scanl() { // repne_scan
4320 emit_int8((unsigned char)0xF2);
4321 // SCASL
4322 emit_int8((unsigned char)0xAF);
4323 }
4324 #endif
4325
4326 void Assembler::ret(int imm16) {
4327 if (imm16 == 0) {
4328 emit_int8((unsigned char)0xC3);
4329 } else {
4330 emit_int8((unsigned char)0xC2);
4331 emit_int16(imm16);
4332 }
4333 }
4334
4335 void Assembler::sahf() {
4336 #ifdef _LP64
4337 // Not supported in 64bit mode
4338 ShouldNotReachHere();
4339 #endif
4340 emit_int8((unsigned char)0x9E);
4341 }
4342
4343 void Assembler::sarl(Register dst, int imm8) {
4344 int encode = prefix_and_encode(dst->encoding());
4345 assert(isShiftCount(imm8), "illegal shift count");
4346 if (imm8 == 1) {
4347 emit_int8((unsigned char)0xD1);
4348 emit_int8((unsigned char)(0xF8 | encode));
4349 } else {
4350 emit_int8((unsigned char)0xC1);
4351 emit_int8((unsigned char)(0xF8 | encode));
4352 emit_int8(imm8);
4353 }
4354 }
4355
4356 void Assembler::sarl(Register dst) {
4357 int encode = prefix_and_encode(dst->encoding());
4358 emit_int8((unsigned char)0xD3);
4359 emit_int8((unsigned char)(0xF8 | encode));
4360 }
4361
4362 void Assembler::sbbl(Address dst, int32_t imm32) {
4363 InstructionMark im(this);
4364 prefix(dst);
4365 emit_arith_operand(0x81, rbx, dst, imm32);
4366 }
4367
4368 void Assembler::sbbl(Register dst, int32_t imm32) {
4369 prefix(dst);
4370 emit_arith(0x81, 0xD8, dst, imm32);
4371 }
4372
4373
4374 void Assembler::sbbl(Register dst, Address src) {
4375 InstructionMark im(this);
4376 prefix(src, dst);
4377 emit_int8(0x1B);
4378 emit_operand(dst, src);
4379 }
4380
4381 void Assembler::sbbl(Register dst, Register src) {
4382 (void) prefix_and_encode(dst->encoding(), src->encoding());
4383 emit_arith(0x1B, 0xC0, dst, src);
4384 }
4385
4386 void Assembler::setb(Condition cc, Register dst) {
4387 assert(0 <= cc && cc < 16, "illegal cc");
4388 int encode = prefix_and_encode(dst->encoding(), true);
4389 emit_int8(0x0F);
4390 emit_int8((unsigned char)0x90 | cc);
4391 emit_int8((unsigned char)(0xC0 | encode));
4392 }
4393
4394 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4395 assert(VM_Version::supports_ssse3(), "");
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4398 emit_int8((unsigned char)0x0F);
4399 emit_int8((unsigned char)(0xC0 | encode));
4400 emit_int8(imm8);
4401 }
4402
4403 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4404 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4405 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4406 0, "");
4407 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4408 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4409 emit_int8((unsigned char)0x0F);
4410 emit_int8((unsigned char)(0xC0 | encode));
4411 emit_int8(imm8);
4412 }
4413
4414 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4415 assert(VM_Version::supports_sse4_1(), "");
4416 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4417 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4418 emit_int8((unsigned char)0x0E);
4419 emit_int8((unsigned char)(0xC0 | encode));
4420 emit_int8(imm8);
4421 }
4422
4423 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4424 assert(VM_Version::supports_sha(), "");
4425 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4426 emit_int8((unsigned char)0xCC);
4427 emit_int8((unsigned char)(0xC0 | encode));
4428 emit_int8((unsigned char)imm8);
4429 }
4430
4431 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4432 assert(VM_Version::supports_sha(), "");
4433 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4434 emit_int8((unsigned char)0xC8);
4435 emit_int8((unsigned char)(0xC0 | encode));
4436 }
4437
4438 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4439 assert(VM_Version::supports_sha(), "");
4440 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4441 emit_int8((unsigned char)0xC9);
4442 emit_int8((unsigned char)(0xC0 | encode));
4443 }
4444
4445 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4446 assert(VM_Version::supports_sha(), "");
4447 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4448 emit_int8((unsigned char)0xCA);
4449 emit_int8((unsigned char)(0xC0 | encode));
4450 }
4451
4452 // xmm0 is implicit additional source to this instruction.
4453 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4454 assert(VM_Version::supports_sha(), "");
4455 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4456 emit_int8((unsigned char)0xCB);
4457 emit_int8((unsigned char)(0xC0 | encode));
4458 }
4459
4460 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4461 assert(VM_Version::supports_sha(), "");
4462 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4463 emit_int8((unsigned char)0xCC);
4464 emit_int8((unsigned char)(0xC0 | encode));
4465 }
4466
4467 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4468 assert(VM_Version::supports_sha(), "");
4469 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4470 emit_int8((unsigned char)0xCD);
4471 emit_int8((unsigned char)(0xC0 | encode));
4472 }
4473
4474
4475 void Assembler::shll(Register dst, int imm8) {
4476 assert(isShiftCount(imm8), "illegal shift count");
4477 int encode = prefix_and_encode(dst->encoding());
4478 if (imm8 == 1 ) {
4479 emit_int8((unsigned char)0xD1);
4480 emit_int8((unsigned char)(0xE0 | encode));
4481 } else {
4482 emit_int8((unsigned char)0xC1);
4483 emit_int8((unsigned char)(0xE0 | encode));
4484 emit_int8(imm8);
4485 }
4486 }
4487
4488 void Assembler::shll(Register dst) {
4489 int encode = prefix_and_encode(dst->encoding());
4490 emit_int8((unsigned char)0xD3);
4491 emit_int8((unsigned char)(0xE0 | encode));
4492 }
4493
4494 void Assembler::shrl(Register dst, int imm8) {
4495 assert(isShiftCount(imm8), "illegal shift count");
4496 int encode = prefix_and_encode(dst->encoding());
4497 emit_int8((unsigned char)0xC1);
4498 emit_int8((unsigned char)(0xE8 | encode));
4499 emit_int8(imm8);
4500 }
4501
4502 void Assembler::shrl(Register dst) {
4503 int encode = prefix_and_encode(dst->encoding());
4504 emit_int8((unsigned char)0xD3);
4505 emit_int8((unsigned char)(0xE8 | encode));
4506 }
4507
4508 // copies a single word from [esi] to [edi]
4509 void Assembler::smovl() {
4510 emit_int8((unsigned char)0xA5);
4511 }
4512
4513 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4515 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4516 attributes.set_rex_vex_w_reverted();
4517 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4518 emit_int8(0x51);
4519 emit_int8((unsigned char)(0xC0 | encode));
4520 }
4521
4522 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4523 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4524 InstructionMark im(this);
4525 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4526 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4527 attributes.set_rex_vex_w_reverted();
4528 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4529 emit_int8(0x51);
4530 emit_operand(dst, src);
4531 }
4532
4533 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4534 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4535 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4536 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4537 emit_int8(0x51);
4538 emit_int8((unsigned char)(0xC0 | encode));
4539 }
4540
4541 void Assembler::std() {
4542 emit_int8((unsigned char)0xFD);
4543 }
4544
4545 void Assembler::sqrtss(XMMRegister dst, Address src) {
4546 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4547 InstructionMark im(this);
4548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4549 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4550 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4551 emit_int8(0x51);
4552 emit_operand(dst, src);
4553 }
4554
4555 void Assembler::stmxcsr( Address dst) {
4556 if (UseAVX > 0 ) {
4557 assert(VM_Version::supports_avx(), "");
4558 InstructionMark im(this);
4559 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4560 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4561 emit_int8((unsigned char)0xAE);
4562 emit_operand(as_Register(3), dst);
4563 } else {
4564 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4565 InstructionMark im(this);
4566 prefix(dst);
4567 emit_int8(0x0F);
4568 emit_int8((unsigned char)0xAE);
4569 emit_operand(as_Register(3), dst);
4570 }
4571 }
4572
4573 void Assembler::subl(Address dst, int32_t imm32) {
4574 InstructionMark im(this);
4575 prefix(dst);
4576 emit_arith_operand(0x81, rbp, dst, imm32);
4577 }
4578
4579 void Assembler::subl(Address dst, Register src) {
4580 InstructionMark im(this);
4581 prefix(dst, src);
4582 emit_int8(0x29);
4583 emit_operand(src, dst);
4584 }
4585
4586 void Assembler::subl(Register dst, int32_t imm32) {
4587 prefix(dst);
4588 emit_arith(0x81, 0xE8, dst, imm32);
4589 }
4590
4591 // Force generation of a 4 byte immediate value even if it fits into 8bit
4592 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4593 prefix(dst);
4594 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4595 }
4596
4597 void Assembler::subl(Register dst, Address src) {
4598 InstructionMark im(this);
4599 prefix(src, dst);
4600 emit_int8(0x2B);
4601 emit_operand(dst, src);
4602 }
4603
4604 void Assembler::subl(Register dst, Register src) {
4605 (void) prefix_and_encode(dst->encoding(), src->encoding());
4606 emit_arith(0x2B, 0xC0, dst, src);
4607 }
4608
4609 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4611 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4612 attributes.set_rex_vex_w_reverted();
4613 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4614 emit_int8(0x5C);
4615 emit_int8((unsigned char)(0xC0 | encode));
4616 }
4617
4618 void Assembler::subsd(XMMRegister dst, Address src) {
4619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4620 InstructionMark im(this);
4621 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4622 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4623 attributes.set_rex_vex_w_reverted();
4624 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4625 emit_int8(0x5C);
4626 emit_operand(dst, src);
4627 }
4628
4629 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4632 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4633 emit_int8(0x5C);
4634 emit_int8((unsigned char)(0xC0 | encode));
4635 }
4636
4637 void Assembler::subss(XMMRegister dst, Address src) {
4638 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4639 InstructionMark im(this);
4640 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4641 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4642 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4643 emit_int8(0x5C);
4644 emit_operand(dst, src);
4645 }
4646
4647 void Assembler::testb(Register dst, int imm8) {
4648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4649 (void) prefix_and_encode(dst->encoding(), true);
4650 emit_arith_b(0xF6, 0xC0, dst, imm8);
4651 }
4652
4653 void Assembler::testb(Address dst, int imm8) {
4654 InstructionMark im(this);
4655 prefix(dst);
4656 emit_int8((unsigned char)0xF6);
4657 emit_operand(rax, dst, 1);
4658 emit_int8(imm8);
4659 }
4660
4661 void Assembler::testl(Register dst, int32_t imm32) {
4662 // not using emit_arith because test
4663 // doesn't support sign-extension of
4664 // 8bit operands
4665 int encode = dst->encoding();
4666 if (encode == 0) {
4667 emit_int8((unsigned char)0xA9);
4668 } else {
4669 encode = prefix_and_encode(encode);
4670 emit_int8((unsigned char)0xF7);
4671 emit_int8((unsigned char)(0xC0 | encode));
4672 }
4673 emit_int32(imm32);
4674 }
4675
4676 void Assembler::testl(Register dst, Register src) {
4677 (void) prefix_and_encode(dst->encoding(), src->encoding());
4678 emit_arith(0x85, 0xC0, dst, src);
4679 }
4680
4681 void Assembler::testl(Register dst, Address src) {
4682 InstructionMark im(this);
4683 prefix(src, dst);
4684 emit_int8((unsigned char)0x85);
4685 emit_operand(dst, src);
4686 }
4687
4688 void Assembler::tzcntl(Register dst, Register src) {
4689 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4690 emit_int8((unsigned char)0xF3);
4691 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4692 emit_int8(0x0F);
4693 emit_int8((unsigned char)0xBC);
4694 emit_int8((unsigned char)0xC0 | encode);
4695 }
4696
4697 void Assembler::tzcntq(Register dst, Register src) {
4698 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4699 emit_int8((unsigned char)0xF3);
4700 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4701 emit_int8(0x0F);
4702 emit_int8((unsigned char)0xBC);
4703 emit_int8((unsigned char)(0xC0 | encode));
4704 }
4705
4706 void Assembler::ucomisd(XMMRegister dst, Address src) {
4707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4708 InstructionMark im(this);
4709 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4710 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4711 attributes.set_rex_vex_w_reverted();
4712 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4713 emit_int8(0x2E);
4714 emit_operand(dst, src);
4715 }
4716
4717 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4719 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4720 attributes.set_rex_vex_w_reverted();
4721 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4722 emit_int8(0x2E);
4723 emit_int8((unsigned char)(0xC0 | encode));
4724 }
4725
4726 void Assembler::ucomiss(XMMRegister dst, Address src) {
4727 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4728 InstructionMark im(this);
4729 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4730 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4731 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4732 emit_int8(0x2E);
4733 emit_operand(dst, src);
4734 }
4735
4736 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4737 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4738 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4739 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4740 emit_int8(0x2E);
4741 emit_int8((unsigned char)(0xC0 | encode));
4742 }
4743
4744 void Assembler::xabort(int8_t imm8) {
4745 emit_int8((unsigned char)0xC6);
4746 emit_int8((unsigned char)0xF8);
4747 emit_int8((unsigned char)(imm8 & 0xFF));
4748 }
4749
4750 void Assembler::xaddb(Address dst, Register src) {
4751 InstructionMark im(this);
4752 prefix(dst, src, true);
4753 emit_int8(0x0F);
4754 emit_int8((unsigned char)0xC0);
4755 emit_operand(src, dst);
4756 }
4757
4758 void Assembler::xaddw(Address dst, Register src) {
4759 InstructionMark im(this);
4760 emit_int8(0x66);
4761 prefix(dst, src);
4762 emit_int8(0x0F);
4763 emit_int8((unsigned char)0xC1);
4764 emit_operand(src, dst);
4765 }
4766
4767 void Assembler::xaddl(Address dst, Register src) {
4768 InstructionMark im(this);
4769 prefix(dst, src);
4770 emit_int8(0x0F);
4771 emit_int8((unsigned char)0xC1);
4772 emit_operand(src, dst);
4773 }
4774
4775 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4776 InstructionMark im(this);
4777 relocate(rtype);
4778 if (abort.is_bound()) {
4779 address entry = target(abort);
4780 assert(entry != NULL, "abort entry NULL");
4781 intptr_t offset = entry - pc();
4782 emit_int8((unsigned char)0xC7);
4783 emit_int8((unsigned char)0xF8);
4784 emit_int32(offset - 6); // 2 opcode + 4 address
4785 } else {
4786 abort.add_patch_at(code(), locator());
4787 emit_int8((unsigned char)0xC7);
4788 emit_int8((unsigned char)0xF8);
4789 emit_int32(0);
4790 }
4791 }
4792
4793 void Assembler::xchgb(Register dst, Address src) { // xchg
4794 InstructionMark im(this);
4795 prefix(src, dst, true);
4796 emit_int8((unsigned char)0x86);
4797 emit_operand(dst, src);
4798 }
4799
4800 void Assembler::xchgw(Register dst, Address src) { // xchg
4801 InstructionMark im(this);
4802 emit_int8(0x66);
4803 prefix(src, dst);
4804 emit_int8((unsigned char)0x87);
4805 emit_operand(dst, src);
4806 }
4807
4808 void Assembler::xchgl(Register dst, Address src) { // xchg
4809 InstructionMark im(this);
4810 prefix(src, dst);
4811 emit_int8((unsigned char)0x87);
4812 emit_operand(dst, src);
4813 }
4814
4815 void Assembler::xchgl(Register dst, Register src) {
4816 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4817 emit_int8((unsigned char)0x87);
4818 emit_int8((unsigned char)(0xC0 | encode));
4819 }
4820
4821 void Assembler::xend() {
4822 emit_int8((unsigned char)0x0F);
4823 emit_int8((unsigned char)0x01);
4824 emit_int8((unsigned char)0xD5);
4825 }
4826
4827 void Assembler::xgetbv() {
4828 emit_int8(0x0F);
4829 emit_int8(0x01);
4830 emit_int8((unsigned char)0xD0);
4831 }
4832
4833 void Assembler::xorl(Register dst, int32_t imm32) {
4834 prefix(dst);
4835 emit_arith(0x81, 0xF0, dst, imm32);
4836 }
4837
4838 void Assembler::xorl(Register dst, Address src) {
4839 InstructionMark im(this);
4840 prefix(src, dst);
4841 emit_int8(0x33);
4842 emit_operand(dst, src);
4843 }
4844
4845 void Assembler::xorl(Register dst, Register src) {
4846 (void) prefix_and_encode(dst->encoding(), src->encoding());
4847 emit_arith(0x33, 0xC0, dst, src);
4848 }
4849
4850 void Assembler::xorb(Register dst, Address src) {
4851 InstructionMark im(this);
4852 prefix(src, dst);
4853 emit_int8(0x32);
4854 emit_operand(dst, src);
4855 }
4856
4857 // AVX 3-operands scalar float-point arithmetic instructions
4858
4859 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4860 assert(VM_Version::supports_avx(), "");
4861 InstructionMark im(this);
4862 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4863 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4864 attributes.set_rex_vex_w_reverted();
4865 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4866 emit_int8(0x58);
4867 emit_operand(dst, src);
4868 }
4869
4870 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4871 assert(VM_Version::supports_avx(), "");
4872 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4873 attributes.set_rex_vex_w_reverted();
4874 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4875 emit_int8(0x58);
4876 emit_int8((unsigned char)(0xC0 | encode));
4877 }
4878
4879 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4880 assert(VM_Version::supports_avx(), "");
4881 InstructionMark im(this);
4882 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4883 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4884 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4885 emit_int8(0x58);
4886 emit_operand(dst, src);
4887 }
4888
4889 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4890 assert(VM_Version::supports_avx(), "");
4891 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4893 emit_int8(0x58);
4894 emit_int8((unsigned char)(0xC0 | encode));
4895 }
4896
4897 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4898 assert(VM_Version::supports_avx(), "");
4899 InstructionMark im(this);
4900 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4901 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4902 attributes.set_rex_vex_w_reverted();
4903 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4904 emit_int8(0x5E);
4905 emit_operand(dst, src);
4906 }
4907
4908 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4909 assert(VM_Version::supports_avx(), "");
4910 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4911 attributes.set_rex_vex_w_reverted();
4912 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4913 emit_int8(0x5E);
4914 emit_int8((unsigned char)(0xC0 | encode));
4915 }
4916
4917 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4918 assert(VM_Version::supports_avx(), "");
4919 InstructionMark im(this);
4920 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4921 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4922 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4923 emit_int8(0x5E);
4924 emit_operand(dst, src);
4925 }
4926
4927 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4928 assert(VM_Version::supports_avx(), "");
4929 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4930 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4931 emit_int8(0x5E);
4932 emit_int8((unsigned char)(0xC0 | encode));
4933 }
4934
4935 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4936 assert(VM_Version::supports_fma(), "");
4937 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4938 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4939 emit_int8((unsigned char)0xB9);
4940 emit_int8((unsigned char)(0xC0 | encode));
4941 }
4942
4943 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4944 assert(VM_Version::supports_fma(), "");
4945 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4946 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4947 emit_int8((unsigned char)0xB9);
4948 emit_int8((unsigned char)(0xC0 | encode));
4949 }
4950
4951 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4952 assert(VM_Version::supports_avx(), "");
4953 InstructionMark im(this);
4954 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4956 attributes.set_rex_vex_w_reverted();
4957 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4958 emit_int8(0x59);
4959 emit_operand(dst, src);
4960 }
4961
4962 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4963 assert(VM_Version::supports_avx(), "");
4964 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4965 attributes.set_rex_vex_w_reverted();
4966 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4967 emit_int8(0x59);
4968 emit_int8((unsigned char)(0xC0 | encode));
4969 }
4970
4971 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4972 assert(VM_Version::supports_avx(), "");
4973 InstructionMark im(this);
4974 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4975 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4976 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x59);
4978 emit_operand(dst, src);
4979 }
4980
4981 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4982 assert(VM_Version::supports_avx(), "");
4983 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4984 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4985 emit_int8(0x59);
4986 emit_int8((unsigned char)(0xC0 | encode));
4987 }
4988
4989 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4990 assert(VM_Version::supports_avx(), "");
4991 InstructionMark im(this);
4992 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4993 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4994 attributes.set_rex_vex_w_reverted();
4995 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4996 emit_int8(0x5C);
4997 emit_operand(dst, src);
4998 }
4999
5000 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5001 assert(VM_Version::supports_avx(), "");
5002 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5003 attributes.set_rex_vex_w_reverted();
5004 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5005 emit_int8(0x5C);
5006 emit_int8((unsigned char)(0xC0 | encode));
5007 }
5008
5009 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5010 assert(VM_Version::supports_avx(), "");
5011 InstructionMark im(this);
5012 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5013 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5014 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5015 emit_int8(0x5C);
5016 emit_operand(dst, src);
5017 }
5018
5019 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5020 assert(VM_Version::supports_avx(), "");
5021 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5022 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5023 emit_int8(0x5C);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 //====================VECTOR ARITHMETIC=====================================
5028
5029 // Float-point vector arithmetic
5030
5031 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5032 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5033 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5034 attributes.set_rex_vex_w_reverted();
5035 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5036 emit_int8(0x58);
5037 emit_int8((unsigned char)(0xC0 | encode));
5038 }
5039
5040 void Assembler::addpd(XMMRegister dst, Address src) {
5041 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5042 InstructionMark im(this);
5043 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5044 attributes.set_rex_vex_w_reverted();
5045 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5047 emit_int8(0x58);
5048 emit_operand(dst, src);
5049 }
5050
5051
5052 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5054 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5056 emit_int8(0x58);
5057 emit_int8((unsigned char)(0xC0 | encode));
5058 }
5059
5060 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5061 assert(VM_Version::supports_avx(), "");
5062 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5063 attributes.set_rex_vex_w_reverted();
5064 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5065 emit_int8(0x58);
5066 emit_int8((unsigned char)(0xC0 | encode));
5067 }
5068
5069 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5070 assert(VM_Version::supports_avx(), "");
5071 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5072 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5073 emit_int8(0x58);
5074 emit_int8((unsigned char)(0xC0 | encode));
5075 }
5076
5077 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5078 assert(VM_Version::supports_avx(), "");
5079 InstructionMark im(this);
5080 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5081 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5082 attributes.set_rex_vex_w_reverted();
5083 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5084 emit_int8(0x58);
5085 emit_operand(dst, src);
5086 }
5087
5088 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5089 assert(VM_Version::supports_avx(), "");
5090 InstructionMark im(this);
5091 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5092 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5093 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5094 emit_int8(0x58);
5095 emit_operand(dst, src);
5096 }
5097
5098 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5099 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5100 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5101 attributes.set_rex_vex_w_reverted();
5102 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5103 emit_int8(0x5C);
5104 emit_int8((unsigned char)(0xC0 | encode));
5105 }
5106
5107 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5109 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5110 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5111 emit_int8(0x5C);
5112 emit_int8((unsigned char)(0xC0 | encode));
5113 }
5114
5115 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5116 assert(VM_Version::supports_avx(), "");
5117 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5118 attributes.set_rex_vex_w_reverted();
5119 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5120 emit_int8(0x5C);
5121 emit_int8((unsigned char)(0xC0 | encode));
5122 }
5123
5124 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5125 assert(VM_Version::supports_avx(), "");
5126 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5127 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5128 emit_int8(0x5C);
5129 emit_int8((unsigned char)(0xC0 | encode));
5130 }
5131
5132 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5133 assert(VM_Version::supports_avx(), "");
5134 InstructionMark im(this);
5135 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5136 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5137 attributes.set_rex_vex_w_reverted();
5138 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5139 emit_int8(0x5C);
5140 emit_operand(dst, src);
5141 }
5142
5143 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5144 assert(VM_Version::supports_avx(), "");
5145 InstructionMark im(this);
5146 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5147 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5148 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5149 emit_int8(0x5C);
5150 emit_operand(dst, src);
5151 }
5152
5153 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5154 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5155 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5156 attributes.set_rex_vex_w_reverted();
5157 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5158 emit_int8(0x59);
5159 emit_int8((unsigned char)(0xC0 | encode));
5160 }
5161
5162 void Assembler::mulpd(XMMRegister dst, Address src) {
5163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5164 InstructionMark im(this);
5165 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5166 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5167 attributes.set_rex_vex_w_reverted();
5168 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5169 emit_int8(0x59);
5170 emit_operand(dst, src);
5171 }
5172
5173 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5175 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5176 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5177 emit_int8(0x59);
5178 emit_int8((unsigned char)(0xC0 | encode));
5179 }
5180
5181 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5182 assert(VM_Version::supports_avx(), "");
5183 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5184 attributes.set_rex_vex_w_reverted();
5185 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5186 emit_int8(0x59);
5187 emit_int8((unsigned char)(0xC0 | encode));
5188 }
5189
5190 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5191 assert(VM_Version::supports_avx(), "");
5192 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5194 emit_int8(0x59);
5195 emit_int8((unsigned char)(0xC0 | encode));
5196 }
5197
5198 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5199 assert(VM_Version::supports_avx(), "");
5200 InstructionMark im(this);
5201 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5202 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5203 attributes.set_rex_vex_w_reverted();
5204 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5205 emit_int8(0x59);
5206 emit_operand(dst, src);
5207 }
5208
5209 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5210 assert(VM_Version::supports_avx(), "");
5211 InstructionMark im(this);
5212 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5213 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5214 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5215 emit_int8(0x59);
5216 emit_operand(dst, src);
5217 }
5218
5219 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5220 assert(VM_Version::supports_fma(), "");
5221 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5222 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5223 emit_int8((unsigned char)0xB8);
5224 emit_int8((unsigned char)(0xC0 | encode));
5225 }
5226
5227 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5228 assert(VM_Version::supports_fma(), "");
5229 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5230 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5231 emit_int8((unsigned char)0xB8);
5232 emit_int8((unsigned char)(0xC0 | encode));
5233 }
5234
5235 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5236 assert(VM_Version::supports_fma(), "");
5237 InstructionMark im(this);
5238 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5239 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5240 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5241 emit_int8((unsigned char)0xB8);
5242 emit_operand(dst, src2);
5243 }
5244
5245 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5246 assert(VM_Version::supports_fma(), "");
5247 InstructionMark im(this);
5248 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5249 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5250 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5251 emit_int8((unsigned char)0xB8);
5252 emit_operand(dst, src2);
5253 }
5254
5255 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5257 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5258 attributes.set_rex_vex_w_reverted();
5259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5260 emit_int8(0x5E);
5261 emit_int8((unsigned char)(0xC0 | encode));
5262 }
5263
5264 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5265 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5267 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5268 emit_int8(0x5E);
5269 emit_int8((unsigned char)(0xC0 | encode));
5270 }
5271
5272 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5273 assert(VM_Version::supports_avx(), "");
5274 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5275 attributes.set_rex_vex_w_reverted();
5276 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5277 emit_int8(0x5E);
5278 emit_int8((unsigned char)(0xC0 | encode));
5279 }
5280
5281 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5282 assert(VM_Version::supports_avx(), "");
5283 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5284 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5285 emit_int8(0x5E);
5286 emit_int8((unsigned char)(0xC0 | encode));
5287 }
5288
5289 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5290 assert(VM_Version::supports_avx(), "");
5291 InstructionMark im(this);
5292 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5293 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5294 attributes.set_rex_vex_w_reverted();
5295 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5296 emit_int8(0x5E);
5297 emit_operand(dst, src);
5298 }
5299
5300 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5301 assert(VM_Version::supports_avx(), "");
5302 InstructionMark im(this);
5303 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5304 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5305 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5306 emit_int8(0x5E);
5307 emit_operand(dst, src);
5308 }
5309
5310 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5311 assert(VM_Version::supports_avx(), "");
5312 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5313 attributes.set_rex_vex_w_reverted();
5314 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5315 emit_int8(0x51);
5316 emit_int8((unsigned char)(0xC0 | encode));
5317 }
5318
5319 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5320 assert(VM_Version::supports_avx(), "");
5321 InstructionMark im(this);
5322 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5323 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5324 attributes.set_rex_vex_w_reverted();
5325 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5326 emit_int8(0x51);
5327 emit_operand(dst, src);
5328 }
5329
5330 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5331 assert(VM_Version::supports_avx(), "");
5332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5333 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5334 emit_int8(0x51);
5335 emit_int8((unsigned char)(0xC0 | encode));
5336 }
5337
5338 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5339 assert(VM_Version::supports_avx(), "");
5340 InstructionMark im(this);
5341 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5342 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5343 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5344 emit_int8(0x51);
5345 emit_operand(dst, src);
5346 }
5347
5348 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5350 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5351 attributes.set_rex_vex_w_reverted();
5352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5353 emit_int8(0x54);
5354 emit_int8((unsigned char)(0xC0 | encode));
5355 }
5356
5357 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5358 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5359 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5360 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5361 emit_int8(0x54);
5362 emit_int8((unsigned char)(0xC0 | encode));
5363 }
5364
5365 void Assembler::andps(XMMRegister dst, Address src) {
5366 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5367 InstructionMark im(this);
5368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5369 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5370 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5371 emit_int8(0x54);
5372 emit_operand(dst, src);
5373 }
5374
5375 void Assembler::andpd(XMMRegister dst, Address src) {
5376 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5377 InstructionMark im(this);
5378 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5379 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5380 attributes.set_rex_vex_w_reverted();
5381 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8(0x54);
5383 emit_operand(dst, src);
5384 }
5385
5386 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5387 assert(VM_Version::supports_avx(), "");
5388 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5389 attributes.set_rex_vex_w_reverted();
5390 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5391 emit_int8(0x54);
5392 emit_int8((unsigned char)(0xC0 | encode));
5393 }
5394
5395 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5396 assert(VM_Version::supports_avx(), "");
5397 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5398 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5399 emit_int8(0x54);
5400 emit_int8((unsigned char)(0xC0 | encode));
5401 }
5402
5403 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5404 assert(VM_Version::supports_avx(), "");
5405 InstructionMark im(this);
5406 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5407 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5408 attributes.set_rex_vex_w_reverted();
5409 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5410 emit_int8(0x54);
5411 emit_operand(dst, src);
5412 }
5413
5414 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5415 assert(VM_Version::supports_avx(), "");
5416 InstructionMark im(this);
5417 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5418 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5419 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5420 emit_int8(0x54);
5421 emit_operand(dst, src);
5422 }
5423
5424 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5426 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5427 attributes.set_rex_vex_w_reverted();
5428 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5429 emit_int8(0x15);
5430 emit_int8((unsigned char)(0xC0 | encode));
5431 }
5432
5433 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5435 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5436 attributes.set_rex_vex_w_reverted();
5437 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5438 emit_int8(0x14);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 }
5441
5442 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5444 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5445 attributes.set_rex_vex_w_reverted();
5446 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5447 emit_int8(0x57);
5448 emit_int8((unsigned char)(0xC0 | encode));
5449 }
5450
5451 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5452 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5454 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5455 emit_int8(0x57);
5456 emit_int8((unsigned char)(0xC0 | encode));
5457 }
5458
5459 void Assembler::xorpd(XMMRegister dst, Address src) {
5460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5461 InstructionMark im(this);
5462 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5463 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5464 attributes.set_rex_vex_w_reverted();
5465 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5466 emit_int8(0x57);
5467 emit_operand(dst, src);
5468 }
5469
5470 void Assembler::xorps(XMMRegister dst, Address src) {
5471 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5472 InstructionMark im(this);
5473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5474 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5475 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5476 emit_int8(0x57);
5477 emit_operand(dst, src);
5478 }
5479
5480 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5481 assert(VM_Version::supports_avx(), "");
5482 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5483 attributes.set_rex_vex_w_reverted();
5484 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5485 emit_int8(0x57);
5486 emit_int8((unsigned char)(0xC0 | encode));
5487 }
5488
5489 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5490 assert(VM_Version::supports_avx(), "");
5491 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5492 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5493 emit_int8(0x57);
5494 emit_int8((unsigned char)(0xC0 | encode));
5495 }
5496
5497 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5498 assert(VM_Version::supports_avx(), "");
5499 InstructionMark im(this);
5500 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5501 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5502 attributes.set_rex_vex_w_reverted();
5503 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5504 emit_int8(0x57);
5505 emit_operand(dst, src);
5506 }
5507
5508 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5509 assert(VM_Version::supports_avx(), "");
5510 InstructionMark im(this);
5511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5512 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5513 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5514 emit_int8(0x57);
5515 emit_operand(dst, src);
5516 }
5517
5518 // Integer vector arithmetic
5519 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5520 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5521 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5522 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5523 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5524 emit_int8(0x01);
5525 emit_int8((unsigned char)(0xC0 | encode));
5526 }
5527
5528 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5529 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5530 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5532 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5533 emit_int8(0x02);
5534 emit_int8((unsigned char)(0xC0 | encode));
5535 }
5536
5537 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5540 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5541 emit_int8((unsigned char)0xFC);
5542 emit_int8((unsigned char)(0xC0 | encode));
5543 }
5544
5545 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5548 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5549 emit_int8((unsigned char)0xFD);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5554 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5555 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5556 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5557 emit_int8((unsigned char)0xFE);
5558 emit_int8((unsigned char)(0xC0 | encode));
5559 }
5560
5561 void Assembler::paddd(XMMRegister dst, Address src) {
5562 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5563 InstructionMark im(this);
5564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5565 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5566 emit_int8((unsigned char)0xFE);
5567 emit_operand(dst, src);
5568 }
5569
5570 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5571 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5572 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5573 attributes.set_rex_vex_w_reverted();
5574 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5575 emit_int8((unsigned char)0xD4);
5576 emit_int8((unsigned char)(0xC0 | encode));
5577 }
5578
5579 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5580 assert(VM_Version::supports_sse3(), "");
5581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5582 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5583 emit_int8(0x01);
5584 emit_int8((unsigned char)(0xC0 | encode));
5585 }
5586
5587 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5588 assert(VM_Version::supports_sse3(), "");
5589 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5590 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5591 emit_int8(0x02);
5592 emit_int8((unsigned char)(0xC0 | encode));
5593 }
5594
5595 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5596 assert(UseAVX > 0, "requires some form of AVX");
5597 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5598 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5599 emit_int8((unsigned char)0xFC);
5600 emit_int8((unsigned char)(0xC0 | encode));
5601 }
5602
5603 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5604 assert(UseAVX > 0, "requires some form of AVX");
5605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5606 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5607 emit_int8((unsigned char)0xFD);
5608 emit_int8((unsigned char)(0xC0 | encode));
5609 }
5610
5611 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5612 assert(UseAVX > 0, "requires some form of AVX");
5613 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5614 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5615 emit_int8((unsigned char)0xFE);
5616 emit_int8((unsigned char)(0xC0 | encode));
5617 }
5618
5619 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5620 assert(UseAVX > 0, "requires some form of AVX");
5621 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5622 attributes.set_rex_vex_w_reverted();
5623 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5624 emit_int8((unsigned char)0xD4);
5625 emit_int8((unsigned char)(0xC0 | encode));
5626 }
5627
5628 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5629 assert(UseAVX > 0, "requires some form of AVX");
5630 InstructionMark im(this);
5631 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5632 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5633 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int8((unsigned char)0xFC);
5635 emit_operand(dst, src);
5636 }
5637
5638 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5639 assert(UseAVX > 0, "requires some form of AVX");
5640 InstructionMark im(this);
5641 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5642 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5643 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5644 emit_int8((unsigned char)0xFD);
5645 emit_operand(dst, src);
5646 }
5647
5648 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5649 assert(UseAVX > 0, "requires some form of AVX");
5650 InstructionMark im(this);
5651 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5652 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5653 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5654 emit_int8((unsigned char)0xFE);
5655 emit_operand(dst, src);
5656 }
5657
5658 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5659 assert(UseAVX > 0, "requires some form of AVX");
5660 InstructionMark im(this);
5661 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5662 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5663 attributes.set_rex_vex_w_reverted();
5664 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5665 emit_int8((unsigned char)0xD4);
5666 emit_operand(dst, src);
5667 }
5668
5669 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5670 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5672 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5673 emit_int8((unsigned char)0xF8);
5674 emit_int8((unsigned char)(0xC0 | encode));
5675 }
5676
5677 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5681 emit_int8((unsigned char)0xF9);
5682 emit_int8((unsigned char)(0xC0 | encode));
5683 }
5684
5685 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5687 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5688 emit_int8((unsigned char)0xFA);
5689 emit_int8((unsigned char)(0xC0 | encode));
5690 }
5691
5692 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5694 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5695 attributes.set_rex_vex_w_reverted();
5696 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5697 emit_int8((unsigned char)0xFB);
5698 emit_int8((unsigned char)(0xC0 | encode));
5699 }
5700
5701 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5702 assert(UseAVX > 0, "requires some form of AVX");
5703 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5704 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5705 emit_int8((unsigned char)0xF8);
5706 emit_int8((unsigned char)(0xC0 | encode));
5707 }
5708
5709 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5710 assert(UseAVX > 0, "requires some form of AVX");
5711 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5712 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5713 emit_int8((unsigned char)0xF9);
5714 emit_int8((unsigned char)(0xC0 | encode));
5715 }
5716
5717 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5718 assert(UseAVX > 0, "requires some form of AVX");
5719 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5720 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5721 emit_int8((unsigned char)0xFA);
5722 emit_int8((unsigned char)(0xC0 | encode));
5723 }
5724
5725 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5726 assert(UseAVX > 0, "requires some form of AVX");
5727 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5728 attributes.set_rex_vex_w_reverted();
5729 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5730 emit_int8((unsigned char)0xFB);
5731 emit_int8((unsigned char)(0xC0 | encode));
5732 }
5733
5734 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5735 assert(UseAVX > 0, "requires some form of AVX");
5736 InstructionMark im(this);
5737 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5738 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5739 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5740 emit_int8((unsigned char)0xF8);
5741 emit_operand(dst, src);
5742 }
5743
5744 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5745 assert(UseAVX > 0, "requires some form of AVX");
5746 InstructionMark im(this);
5747 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5748 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5749 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5750 emit_int8((unsigned char)0xF9);
5751 emit_operand(dst, src);
5752 }
5753
5754 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5755 assert(UseAVX > 0, "requires some form of AVX");
5756 InstructionMark im(this);
5757 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5758 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5759 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5760 emit_int8((unsigned char)0xFA);
5761 emit_operand(dst, src);
5762 }
5763
5764 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5765 assert(UseAVX > 0, "requires some form of AVX");
5766 InstructionMark im(this);
5767 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5768 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5769 attributes.set_rex_vex_w_reverted();
5770 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5771 emit_int8((unsigned char)0xFB);
5772 emit_operand(dst, src);
5773 }
5774
5775 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5778 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5779 emit_int8((unsigned char)0xD5);
5780 emit_int8((unsigned char)(0xC0 | encode));
5781 }
5782
5783 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5784 assert(VM_Version::supports_sse4_1(), "");
5785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5787 emit_int8(0x40);
5788 emit_int8((unsigned char)(0xC0 | encode));
5789 }
5790
5791 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5792 assert(UseAVX > 0, "requires some form of AVX");
5793 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5794 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5795 emit_int8((unsigned char)0xD5);
5796 emit_int8((unsigned char)(0xC0 | encode));
5797 }
5798
5799 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5800 assert(UseAVX > 0, "requires some form of AVX");
5801 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5802 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5803 emit_int8(0x40);
5804 emit_int8((unsigned char)(0xC0 | encode));
5805 }
5806
5807 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5808 assert(UseAVX > 2, "requires some form of EVEX");
5809 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5810 attributes.set_is_evex_instruction();
5811 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5812 emit_int8(0x40);
5813 emit_int8((unsigned char)(0xC0 | encode));
5814 }
5815
5816 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5817 assert(UseAVX > 0, "requires some form of AVX");
5818 InstructionMark im(this);
5819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5820 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5821 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5822 emit_int8((unsigned char)0xD5);
5823 emit_operand(dst, src);
5824 }
5825
5826 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5827 assert(UseAVX > 0, "requires some form of AVX");
5828 InstructionMark im(this);
5829 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5830 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5831 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5832 emit_int8(0x40);
5833 emit_operand(dst, src);
5834 }
5835
5836 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5837 assert(UseAVX > 2, "requires some form of EVEX");
5838 InstructionMark im(this);
5839 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5840 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5841 attributes.set_is_evex_instruction();
5842 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5843 emit_int8(0x40);
5844 emit_operand(dst, src);
5845 }
5846
5847 // Shift packed integers left by specified number of bits.
5848 void Assembler::psllw(XMMRegister dst, int shift) {
5849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5850 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5851 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5852 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5853 emit_int8(0x71);
5854 emit_int8((unsigned char)(0xC0 | encode));
5855 emit_int8(shift & 0xFF);
5856 }
5857
5858 void Assembler::pslld(XMMRegister dst, int shift) {
5859 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5861 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5862 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5863 emit_int8(0x72);
5864 emit_int8((unsigned char)(0xC0 | encode));
5865 emit_int8(shift & 0xFF);
5866 }
5867
5868 void Assembler::psllq(XMMRegister dst, int shift) {
5869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5870 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5871 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5872 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5873 emit_int8(0x73);
5874 emit_int8((unsigned char)(0xC0 | encode));
5875 emit_int8(shift & 0xFF);
5876 }
5877
5878 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5879 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5880 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5881 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5882 emit_int8((unsigned char)0xF1);
5883 emit_int8((unsigned char)(0xC0 | encode));
5884 }
5885
5886 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5888 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5889 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5890 emit_int8((unsigned char)0xF2);
5891 emit_int8((unsigned char)(0xC0 | encode));
5892 }
5893
5894 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5896 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5897 attributes.set_rex_vex_w_reverted();
5898 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5899 emit_int8((unsigned char)0xF3);
5900 emit_int8((unsigned char)(0xC0 | encode));
5901 }
5902
5903 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5904 assert(UseAVX > 0, "requires some form of AVX");
5905 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5906 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5907 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5908 emit_int8(0x71);
5909 emit_int8((unsigned char)(0xC0 | encode));
5910 emit_int8(shift & 0xFF);
5911 }
5912
5913 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5914 assert(UseAVX > 0, "requires some form of AVX");
5915 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5916 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5917 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5918 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5919 emit_int8(0x72);
5920 emit_int8((unsigned char)(0xC0 | encode));
5921 emit_int8(shift & 0xFF);
5922 }
5923
5924 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5925 assert(UseAVX > 0, "requires some form of AVX");
5926 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5927 attributes.set_rex_vex_w_reverted();
5928 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5929 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5930 emit_int8(0x73);
5931 emit_int8((unsigned char)(0xC0 | encode));
5932 emit_int8(shift & 0xFF);
5933 }
5934
5935 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5936 assert(UseAVX > 0, "requires some form of AVX");
5937 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5938 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5939 emit_int8((unsigned char)0xF1);
5940 emit_int8((unsigned char)(0xC0 | encode));
5941 }
5942
5943 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5944 assert(UseAVX > 0, "requires some form of AVX");
5945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5946 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5947 emit_int8((unsigned char)0xF2);
5948 emit_int8((unsigned char)(0xC0 | encode));
5949 }
5950
5951 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5952 assert(UseAVX > 0, "requires some form of AVX");
5953 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5954 attributes.set_rex_vex_w_reverted();
5955 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5956 emit_int8((unsigned char)0xF3);
5957 emit_int8((unsigned char)(0xC0 | encode));
5958 }
5959
5960 // Shift packed integers logically right by specified number of bits.
5961 void Assembler::psrlw(XMMRegister dst, int shift) {
5962 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5963 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5964 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5965 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5966 emit_int8(0x71);
5967 emit_int8((unsigned char)(0xC0 | encode));
5968 emit_int8(shift & 0xFF);
5969 }
5970
5971 void Assembler::psrld(XMMRegister dst, int shift) {
5972 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5973 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5974 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5975 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5976 emit_int8(0x72);
5977 emit_int8((unsigned char)(0xC0 | encode));
5978 emit_int8(shift & 0xFF);
5979 }
5980
5981 void Assembler::psrlq(XMMRegister dst, int shift) {
5982 // Do not confuse it with psrldq SSE2 instruction which
5983 // shifts 128 bit value in xmm register by number of bytes.
5984 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5985 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5986 attributes.set_rex_vex_w_reverted();
5987 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5988 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5989 emit_int8(0x73);
5990 emit_int8((unsigned char)(0xC0 | encode));
5991 emit_int8(shift & 0xFF);
5992 }
5993
5994 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5995 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5996 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5997 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5998 emit_int8((unsigned char)0xD1);
5999 emit_int8((unsigned char)(0xC0 | encode));
6000 }
6001
6002 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6004 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6005 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6006 emit_int8((unsigned char)0xD2);
6007 emit_int8((unsigned char)(0xC0 | encode));
6008 }
6009
6010 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6012 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6013 attributes.set_rex_vex_w_reverted();
6014 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6015 emit_int8((unsigned char)0xD3);
6016 emit_int8((unsigned char)(0xC0 | encode));
6017 }
6018
6019 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6020 assert(UseAVX > 0, "requires some form of AVX");
6021 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6022 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6023 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6024 emit_int8(0x71);
6025 emit_int8((unsigned char)(0xC0 | encode));
6026 emit_int8(shift & 0xFF);
6027 }
6028
6029 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6030 assert(UseAVX > 0, "requires some form of AVX");
6031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6032 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6033 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6034 emit_int8(0x72);
6035 emit_int8((unsigned char)(0xC0 | encode));
6036 emit_int8(shift & 0xFF);
6037 }
6038
6039 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6040 assert(UseAVX > 0, "requires some form of AVX");
6041 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6042 attributes.set_rex_vex_w_reverted();
6043 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6044 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6045 emit_int8(0x73);
6046 emit_int8((unsigned char)(0xC0 | encode));
6047 emit_int8(shift & 0xFF);
6048 }
6049
6050 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6051 assert(UseAVX > 0, "requires some form of AVX");
6052 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6053 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6054 emit_int8((unsigned char)0xD1);
6055 emit_int8((unsigned char)(0xC0 | encode));
6056 }
6057
6058 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6059 assert(UseAVX > 0, "requires some form of AVX");
6060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6061 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6062 emit_int8((unsigned char)0xD2);
6063 emit_int8((unsigned char)(0xC0 | encode));
6064 }
6065
6066 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6067 assert(UseAVX > 0, "requires some form of AVX");
6068 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6069 attributes.set_rex_vex_w_reverted();
6070 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6071 emit_int8((unsigned char)0xD3);
6072 emit_int8((unsigned char)(0xC0 | encode));
6073 }
6074
6075 // Shift packed integers arithmetically right by specified number of bits.
6076 void Assembler::psraw(XMMRegister dst, int shift) {
6077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6078 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6079 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6080 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6081 emit_int8(0x71);
6082 emit_int8((unsigned char)(0xC0 | encode));
6083 emit_int8(shift & 0xFF);
6084 }
6085
6086 void Assembler::psrad(XMMRegister dst, int shift) {
6087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6089 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6090 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6091 emit_int8(0x72);
6092 emit_int8((unsigned char)(0xC0 | encode));
6093 emit_int8(shift & 0xFF);
6094 }
6095
6096 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6098 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6099 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6100 emit_int8((unsigned char)0xE1);
6101 emit_int8((unsigned char)(0xC0 | encode));
6102 }
6103
6104 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6106 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6107 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6108 emit_int8((unsigned char)0xE2);
6109 emit_int8((unsigned char)(0xC0 | encode));
6110 }
6111
6112 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6113 assert(UseAVX > 0, "requires some form of AVX");
6114 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6115 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6116 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6117 emit_int8(0x71);
6118 emit_int8((unsigned char)(0xC0 | encode));
6119 emit_int8(shift & 0xFF);
6120 }
6121
6122 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6123 assert(UseAVX > 0, "requires some form of AVX");
6124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6125 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6126 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6127 emit_int8(0x72);
6128 emit_int8((unsigned char)(0xC0 | encode));
6129 emit_int8(shift & 0xFF);
6130 }
6131
6132 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6133 assert(UseAVX > 0, "requires some form of AVX");
6134 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6135 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6136 emit_int8((unsigned char)0xE1);
6137 emit_int8((unsigned char)(0xC0 | encode));
6138 }
6139
6140 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6141 assert(UseAVX > 0, "requires some form of AVX");
6142 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6143 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6144 emit_int8((unsigned char)0xE2);
6145 emit_int8((unsigned char)(0xC0 | encode));
6146 }
6147
6148
6149 // logical operations packed integers
6150 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6151 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6152 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6153 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6154 emit_int8((unsigned char)0xDB);
6155 emit_int8((unsigned char)(0xC0 | encode));
6156 }
6157
6158 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6159 assert(UseAVX > 0, "requires some form of AVX");
6160 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6161 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6162 emit_int8((unsigned char)0xDB);
6163 emit_int8((unsigned char)(0xC0 | encode));
6164 }
6165
6166 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6167 assert(UseAVX > 0, "requires some form of AVX");
6168 InstructionMark im(this);
6169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6170 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6171 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6172 emit_int8((unsigned char)0xDB);
6173 emit_operand(dst, src);
6174 }
6175
6176 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6178 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6179 attributes.set_rex_vex_w_reverted();
6180 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6181 emit_int8((unsigned char)0xDF);
6182 emit_int8((unsigned char)(0xC0 | encode));
6183 }
6184
6185 void Assembler::por(XMMRegister dst, XMMRegister src) {
6186 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6187 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6188 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6189 emit_int8((unsigned char)0xEB);
6190 emit_int8((unsigned char)(0xC0 | encode));
6191 }
6192
6193 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6194 assert(UseAVX > 0, "requires some form of AVX");
6195 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6196 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6197 emit_int8((unsigned char)0xEB);
6198 emit_int8((unsigned char)(0xC0 | encode));
6199 }
6200
6201 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6202 assert(UseAVX > 0, "requires some form of AVX");
6203 InstructionMark im(this);
6204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6205 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6206 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6207 emit_int8((unsigned char)0xEB);
6208 emit_operand(dst, src);
6209 }
6210
6211 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6212 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6213 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6214 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6215 emit_int8((unsigned char)0xEF);
6216 emit_int8((unsigned char)(0xC0 | encode));
6217 }
6218
6219 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6220 assert(UseAVX > 0, "requires some form of AVX");
6221 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6222 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6223 emit_int8((unsigned char)0xEF);
6224 emit_int8((unsigned char)(0xC0 | encode));
6225 }
6226
6227 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6228 assert(UseAVX > 0, "requires some form of AVX");
6229 InstructionMark im(this);
6230 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6231 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6232 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6233 emit_int8((unsigned char)0xEF);
6234 emit_operand(dst, src);
6235 }
6236
6237 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6238 assert(VM_Version::supports_evex(), "requires EVEX support");
6239 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6240 attributes.set_is_evex_instruction();
6241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6242 emit_int8((unsigned char)0xEF);
6243 emit_int8((unsigned char)(0xC0 | encode));
6244 }
6245
6246 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6247 assert(VM_Version::supports_evex(), "requires EVEX support");
6248 assert(dst != xnoreg, "sanity");
6249 InstructionMark im(this);
6250 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6251 attributes.set_is_evex_instruction();
6252 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6253 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6254 emit_int8((unsigned char)0xEF);
6255 emit_operand(dst, src);
6256 }
6257
6258
6259 // vinserti forms
6260
6261 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6262 assert(VM_Version::supports_avx2(), "");
6263 assert(imm8 <= 0x01, "imm8: %u", imm8);
6264 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6265 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6266 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6267 emit_int8(0x38);
6268 emit_int8((unsigned char)(0xC0 | encode));
6269 // 0x00 - insert into lower 128 bits
6270 // 0x01 - insert into upper 128 bits
6271 emit_int8(imm8 & 0x01);
6272 }
6273
6274 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6275 assert(VM_Version::supports_avx2(), "");
6276 assert(dst != xnoreg, "sanity");
6277 assert(imm8 <= 0x01, "imm8: %u", imm8);
6278 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6279 InstructionMark im(this);
6280 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6281 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6282 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6283 emit_int8(0x38);
6284 emit_operand(dst, src);
6285 // 0x00 - insert into lower 128 bits
6286 // 0x01 - insert into upper 128 bits
6287 emit_int8(imm8 & 0x01);
6288 }
6289
6290 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6291 assert(VM_Version::supports_evex(), "");
6292 assert(imm8 <= 0x03, "imm8: %u", imm8);
6293 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6294 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6295 emit_int8(0x38);
6296 emit_int8((unsigned char)(0xC0 | encode));
6297 // 0x00 - insert into q0 128 bits (0..127)
6298 // 0x01 - insert into q1 128 bits (128..255)
6299 // 0x02 - insert into q2 128 bits (256..383)
6300 // 0x03 - insert into q3 128 bits (384..511)
6301 emit_int8(imm8 & 0x03);
6302 }
6303
6304 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6305 assert(VM_Version::supports_avx(), "");
6306 assert(dst != xnoreg, "sanity");
6307 assert(imm8 <= 0x03, "imm8: %u", imm8);
6308 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6309 InstructionMark im(this);
6310 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6311 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6312 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6313 emit_int8(0x18);
6314 emit_operand(dst, src);
6315 // 0x00 - insert into q0 128 bits (0..127)
6316 // 0x01 - insert into q1 128 bits (128..255)
6317 // 0x02 - insert into q2 128 bits (256..383)
6318 // 0x03 - insert into q3 128 bits (384..511)
6319 emit_int8(imm8 & 0x03);
6320 }
6321
6322 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6323 assert(VM_Version::supports_evex(), "");
6324 assert(imm8 <= 0x01, "imm8: %u", imm8);
6325 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6326 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6327 emit_int8(0x38);
6328 emit_int8((unsigned char)(0xC0 | encode));
6329 // 0x00 - insert into lower 256 bits
6330 // 0x01 - insert into upper 256 bits
6331 emit_int8(imm8 & 0x01);
6332 }
6333
6334
6335 // vinsertf forms
6336
6337 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6338 assert(VM_Version::supports_avx(), "");
6339 assert(imm8 <= 0x01, "imm8: %u", imm8);
6340 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6341 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6343 emit_int8(0x18);
6344 emit_int8((unsigned char)(0xC0 | encode));
6345 // 0x00 - insert into lower 128 bits
6346 // 0x01 - insert into upper 128 bits
6347 emit_int8(imm8 & 0x01);
6348 }
6349
6350 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6351 assert(VM_Version::supports_avx(), "");
6352 assert(dst != xnoreg, "sanity");
6353 assert(imm8 <= 0x01, "imm8: %u", imm8);
6354 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6355 InstructionMark im(this);
6356 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6357 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6358 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6359 emit_int8(0x18);
6360 emit_operand(dst, src);
6361 // 0x00 - insert into lower 128 bits
6362 // 0x01 - insert into upper 128 bits
6363 emit_int8(imm8 & 0x01);
6364 }
6365
6366 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6367 assert(VM_Version::supports_evex(), "");
6368 assert(imm8 <= 0x03, "imm8: %u", imm8);
6369 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6370 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6371 emit_int8(0x18);
6372 emit_int8((unsigned char)(0xC0 | encode));
6373 // 0x00 - insert into q0 128 bits (0..127)
6374 // 0x01 - insert into q1 128 bits (128..255)
6375 // 0x02 - insert into q2 128 bits (256..383)
6376 // 0x03 - insert into q3 128 bits (384..511)
6377 emit_int8(imm8 & 0x03);
6378 }
6379
6380 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6381 assert(VM_Version::supports_avx(), "");
6382 assert(dst != xnoreg, "sanity");
6383 assert(imm8 <= 0x03, "imm8: %u", imm8);
6384 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6385 InstructionMark im(this);
6386 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6387 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6388 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6389 emit_int8(0x18);
6390 emit_operand(dst, src);
6391 // 0x00 - insert into q0 128 bits (0..127)
6392 // 0x01 - insert into q1 128 bits (128..255)
6393 // 0x02 - insert into q2 128 bits (256..383)
6394 // 0x03 - insert into q3 128 bits (384..511)
6395 emit_int8(imm8 & 0x03);
6396 }
6397
6398 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6399 assert(VM_Version::supports_evex(), "");
6400 assert(imm8 <= 0x01, "imm8: %u", imm8);
6401 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6402 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6403 emit_int8(0x1A);
6404 emit_int8((unsigned char)(0xC0 | encode));
6405 // 0x00 - insert into lower 256 bits
6406 // 0x01 - insert into upper 256 bits
6407 emit_int8(imm8 & 0x01);
6408 }
6409
6410 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6411 assert(VM_Version::supports_evex(), "");
6412 assert(dst != xnoreg, "sanity");
6413 assert(imm8 <= 0x01, "imm8: %u", imm8);
6414 InstructionMark im(this);
6415 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6416 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6417 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6418 emit_int8(0x1A);
6419 emit_operand(dst, src);
6420 // 0x00 - insert into lower 256 bits
6421 // 0x01 - insert into upper 256 bits
6422 emit_int8(imm8 & 0x01);
6423 }
6424
6425
6426 // vextracti forms
6427
6428 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6429 assert(VM_Version::supports_avx(), "");
6430 assert(imm8 <= 0x01, "imm8: %u", imm8);
6431 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6432 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6433 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6434 emit_int8(0x39);
6435 emit_int8((unsigned char)(0xC0 | encode));
6436 // 0x00 - extract from lower 128 bits
6437 // 0x01 - extract from upper 128 bits
6438 emit_int8(imm8 & 0x01);
6439 }
6440
6441 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6442 assert(VM_Version::supports_avx2(), "");
6443 assert(src != xnoreg, "sanity");
6444 assert(imm8 <= 0x01, "imm8: %u", imm8);
6445 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6446 InstructionMark im(this);
6447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6448 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6449 attributes.reset_is_clear_context();
6450 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6451 emit_int8(0x39);
6452 emit_operand(src, dst);
6453 // 0x00 - extract from lower 128 bits
6454 // 0x01 - extract from upper 128 bits
6455 emit_int8(imm8 & 0x01);
6456 }
6457
6458 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6459 assert(VM_Version::supports_avx(), "");
6460 assert(imm8 <= 0x03, "imm8: %u", imm8);
6461 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6462 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6463 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6464 emit_int8(0x39);
6465 emit_int8((unsigned char)(0xC0 | encode));
6466 // 0x00 - extract from bits 127:0
6467 // 0x01 - extract from bits 255:128
6468 // 0x02 - extract from bits 383:256
6469 // 0x03 - extract from bits 511:384
6470 emit_int8(imm8 & 0x03);
6471 }
6472
6473 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6474 assert(VM_Version::supports_evex(), "");
6475 assert(src != xnoreg, "sanity");
6476 assert(imm8 <= 0x03, "imm8: %u", imm8);
6477 InstructionMark im(this);
6478 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6479 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6480 attributes.reset_is_clear_context();
6481 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6482 emit_int8(0x39);
6483 emit_operand(src, dst);
6484 // 0x00 - extract from bits 127:0
6485 // 0x01 - extract from bits 255:128
6486 // 0x02 - extract from bits 383:256
6487 // 0x03 - extract from bits 511:384
6488 emit_int8(imm8 & 0x03);
6489 }
6490
6491 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6492 assert(VM_Version::supports_avx512dq(), "");
6493 assert(imm8 <= 0x03, "imm8: %u", imm8);
6494 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6495 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6496 emit_int8(0x39);
6497 emit_int8((unsigned char)(0xC0 | encode));
6498 // 0x00 - extract from bits 127:0
6499 // 0x01 - extract from bits 255:128
6500 // 0x02 - extract from bits 383:256
6501 // 0x03 - extract from bits 511:384
6502 emit_int8(imm8 & 0x03);
6503 }
6504
6505 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6506 assert(VM_Version::supports_evex(), "");
6507 assert(imm8 <= 0x01, "imm8: %u", imm8);
6508 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6509 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6510 emit_int8(0x3B);
6511 emit_int8((unsigned char)(0xC0 | encode));
6512 // 0x00 - extract from lower 256 bits
6513 // 0x01 - extract from upper 256 bits
6514 emit_int8(imm8 & 0x01);
6515 }
6516
6517
6518 // vextractf forms
6519
6520 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6521 assert(VM_Version::supports_avx(), "");
6522 assert(imm8 <= 0x01, "imm8: %u", imm8);
6523 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6525 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6526 emit_int8(0x19);
6527 emit_int8((unsigned char)(0xC0 | encode));
6528 // 0x00 - extract from lower 128 bits
6529 // 0x01 - extract from upper 128 bits
6530 emit_int8(imm8 & 0x01);
6531 }
6532
6533 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6534 assert(VM_Version::supports_avx(), "");
6535 assert(src != xnoreg, "sanity");
6536 assert(imm8 <= 0x01, "imm8: %u", imm8);
6537 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6538 InstructionMark im(this);
6539 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6540 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6541 attributes.reset_is_clear_context();
6542 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6543 emit_int8(0x19);
6544 emit_operand(src, dst);
6545 // 0x00 - extract from lower 128 bits
6546 // 0x01 - extract from upper 128 bits
6547 emit_int8(imm8 & 0x01);
6548 }
6549
6550 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6551 assert(VM_Version::supports_avx(), "");
6552 assert(imm8 <= 0x03, "imm8: %u", imm8);
6553 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6555 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6556 emit_int8(0x19);
6557 emit_int8((unsigned char)(0xC0 | encode));
6558 // 0x00 - extract from bits 127:0
6559 // 0x01 - extract from bits 255:128
6560 // 0x02 - extract from bits 383:256
6561 // 0x03 - extract from bits 511:384
6562 emit_int8(imm8 & 0x03);
6563 }
6564
6565 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6566 assert(VM_Version::supports_evex(), "");
6567 assert(src != xnoreg, "sanity");
6568 assert(imm8 <= 0x03, "imm8: %u", imm8);
6569 InstructionMark im(this);
6570 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6571 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6572 attributes.reset_is_clear_context();
6573 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6574 emit_int8(0x19);
6575 emit_operand(src, dst);
6576 // 0x00 - extract from bits 127:0
6577 // 0x01 - extract from bits 255:128
6578 // 0x02 - extract from bits 383:256
6579 // 0x03 - extract from bits 511:384
6580 emit_int8(imm8 & 0x03);
6581 }
6582
6583 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6584 assert(VM_Version::supports_avx512dq(), "");
6585 assert(imm8 <= 0x03, "imm8: %u", imm8);
6586 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6587 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6588 emit_int8(0x19);
6589 emit_int8((unsigned char)(0xC0 | encode));
6590 // 0x00 - extract from bits 127:0
6591 // 0x01 - extract from bits 255:128
6592 // 0x02 - extract from bits 383:256
6593 // 0x03 - extract from bits 511:384
6594 emit_int8(imm8 & 0x03);
6595 }
6596
6597 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6598 assert(VM_Version::supports_evex(), "");
6599 assert(imm8 <= 0x01, "imm8: %u", imm8);
6600 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6601 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6602 emit_int8(0x1B);
6603 emit_int8((unsigned char)(0xC0 | encode));
6604 // 0x00 - extract from lower 256 bits
6605 // 0x01 - extract from upper 256 bits
6606 emit_int8(imm8 & 0x01);
6607 }
6608
6609 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6610 assert(VM_Version::supports_evex(), "");
6611 assert(src != xnoreg, "sanity");
6612 assert(imm8 <= 0x01, "imm8: %u", imm8);
6613 InstructionMark im(this);
6614 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6615 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6616 attributes.reset_is_clear_context();
6617 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6618 emit_int8(0x1B);
6619 emit_operand(src, dst);
6620 // 0x00 - extract from lower 256 bits
6621 // 0x01 - extract from upper 256 bits
6622 emit_int8(imm8 & 0x01);
6623 }
6624
6625
6626 // legacy word/dword replicate
6627 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6628 assert(VM_Version::supports_avx2(), "");
6629 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6630 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6631 emit_int8(0x79);
6632 emit_int8((unsigned char)(0xC0 | encode));
6633 }
6634
6635 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6636 assert(VM_Version::supports_avx2(), "");
6637 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6638 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6639 emit_int8(0x58);
6640 emit_int8((unsigned char)(0xC0 | encode));
6641 }
6642
6643
6644 // xmm/mem sourced byte/word/dword/qword replicate
6645
6646 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6647 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6648 assert(VM_Version::supports_evex(), "");
6649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6650 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6651 emit_int8(0x78);
6652 emit_int8((unsigned char)(0xC0 | encode));
6653 }
6654
6655 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6656 assert(VM_Version::supports_evex(), "");
6657 assert(dst != xnoreg, "sanity");
6658 InstructionMark im(this);
6659 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6660 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6661 // swap src<->dst for encoding
6662 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6663 emit_int8(0x78);
6664 emit_operand(dst, src);
6665 }
6666
6667 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6668 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6669 assert(VM_Version::supports_evex(), "");
6670 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6671 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6672 emit_int8(0x79);
6673 emit_int8((unsigned char)(0xC0 | encode));
6674 }
6675
6676 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6677 assert(VM_Version::supports_evex(), "");
6678 assert(dst != xnoreg, "sanity");
6679 InstructionMark im(this);
6680 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6681 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6682 // swap src<->dst for encoding
6683 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6684 emit_int8(0x79);
6685 emit_operand(dst, src);
6686 }
6687
6688 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6689 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6690 assert(VM_Version::supports_evex(), "");
6691 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6692 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6693 emit_int8(0x58);
6694 emit_int8((unsigned char)(0xC0 | encode));
6695 }
6696
6697 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6698 assert(VM_Version::supports_evex(), "");
6699 assert(dst != xnoreg, "sanity");
6700 InstructionMark im(this);
6701 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6702 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6703 // swap src<->dst for encoding
6704 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6705 emit_int8(0x58);
6706 emit_operand(dst, src);
6707 }
6708
6709 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6710 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6711 assert(VM_Version::supports_evex(), "");
6712 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6713 attributes.set_rex_vex_w_reverted();
6714 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6715 emit_int8(0x59);
6716 emit_int8((unsigned char)(0xC0 | encode));
6717 }
6718
6719 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6720 assert(VM_Version::supports_evex(), "");
6721 assert(dst != xnoreg, "sanity");
6722 InstructionMark im(this);
6723 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6724 attributes.set_rex_vex_w_reverted();
6725 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6726 // swap src<->dst for encoding
6727 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6728 emit_int8(0x59);
6729 emit_operand(dst, src);
6730 }
6731
6732
6733 // scalar single/double precision replicate
6734
6735 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6736 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6737 assert(VM_Version::supports_evex(), "");
6738 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6739 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6740 emit_int8(0x18);
6741 emit_int8((unsigned char)(0xC0 | encode));
6742 }
6743
6744 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6745 assert(VM_Version::supports_evex(), "");
6746 assert(dst != xnoreg, "sanity");
6747 InstructionMark im(this);
6748 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6749 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6750 // swap src<->dst for encoding
6751 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6752 emit_int8(0x18);
6753 emit_operand(dst, src);
6754 }
6755
6756 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6757 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6758 assert(VM_Version::supports_evex(), "");
6759 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6760 attributes.set_rex_vex_w_reverted();
6761 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6762 emit_int8(0x19);
6763 emit_int8((unsigned char)(0xC0 | encode));
6764 }
6765
6766 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6767 assert(VM_Version::supports_evex(), "");
6768 assert(dst != xnoreg, "sanity");
6769 InstructionMark im(this);
6770 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6771 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6772 attributes.set_rex_vex_w_reverted();
6773 // swap src<->dst for encoding
6774 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6775 emit_int8(0x19);
6776 emit_operand(dst, src);
6777 }
6778
6779
6780 // gpr source broadcast forms
6781
6782 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6783 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6784 assert(VM_Version::supports_evex(), "");
6785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6786 attributes.set_is_evex_instruction();
6787 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6788 emit_int8(0x7A);
6789 emit_int8((unsigned char)(0xC0 | encode));
6790 }
6791
6792 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6793 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6794 assert(VM_Version::supports_evex(), "");
6795 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6796 attributes.set_is_evex_instruction();
6797 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6798 emit_int8(0x7B);
6799 emit_int8((unsigned char)(0xC0 | encode));
6800 }
6801
6802 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6803 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6804 assert(VM_Version::supports_evex(), "");
6805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6806 attributes.set_is_evex_instruction();
6807 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6808 emit_int8(0x7C);
6809 emit_int8((unsigned char)(0xC0 | encode));
6810 }
6811
6812 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6813 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6814 assert(VM_Version::supports_evex(), "");
6815 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6816 attributes.set_is_evex_instruction();
6817 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6818 emit_int8(0x7C);
6819 emit_int8((unsigned char)(0xC0 | encode));
6820 }
6821
6822
6823 // Carry-Less Multiplication Quadword
6824 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6825 assert(VM_Version::supports_clmul(), "");
6826 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6827 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6828 emit_int8(0x44);
6829 emit_int8((unsigned char)(0xC0 | encode));
6830 emit_int8((unsigned char)mask);
6831 }
6832
6833 // Carry-Less Multiplication Quadword
6834 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6835 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6836 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6837 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6838 emit_int8(0x44);
6839 emit_int8((unsigned char)(0xC0 | encode));
6840 emit_int8((unsigned char)mask);
6841 }
6842
6843 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
6844 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
6845 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6846 attributes.set_is_evex_instruction();
6847 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6848 emit_int8(0x44);
6849 emit_int8((unsigned char)(0xC0 | encode));
6850 emit_int8((unsigned char)mask);
6851 }
6852
6853 void Assembler::vzeroupper() {
6854 if (VM_Version::supports_vzeroupper()) {
6855 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6856 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6857 emit_int8(0x77);
6858 }
6859 }
6860
6861 #ifndef _LP64
6862 // 32bit only pieces of the assembler
6863
6864 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6865 // NO PREFIX AS NEVER 64BIT
6866 InstructionMark im(this);
6867 emit_int8((unsigned char)0x81);
6868 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6869 emit_data(imm32, rspec, 0);
6870 }
6871
6872 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6873 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6874 InstructionMark im(this);
6875 emit_int8((unsigned char)0x81);
6876 emit_operand(rdi, src1);
6877 emit_data(imm32, rspec, 0);
6878 }
6879
6880 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6881 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6882 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6883 void Assembler::cmpxchg8(Address adr) {
6884 InstructionMark im(this);
6885 emit_int8(0x0F);
6886 emit_int8((unsigned char)0xC7);
6887 emit_operand(rcx, adr);
6888 }
6889
6890 void Assembler::decl(Register dst) {
6891 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6892 emit_int8(0x48 | dst->encoding());
6893 }
6894
6895 #endif // _LP64
6896
6897 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6898
6899 void Assembler::fabs() {
6900 emit_int8((unsigned char)0xD9);
6901 emit_int8((unsigned char)0xE1);
6902 }
6903
6904 void Assembler::fadd(int i) {
6905 emit_farith(0xD8, 0xC0, i);
6906 }
6907
6908 void Assembler::fadd_d(Address src) {
6909 InstructionMark im(this);
6910 emit_int8((unsigned char)0xDC);
6911 emit_operand32(rax, src);
6912 }
6913
6914 void Assembler::fadd_s(Address src) {
6915 InstructionMark im(this);
6916 emit_int8((unsigned char)0xD8);
6917 emit_operand32(rax, src);
6918 }
6919
6920 void Assembler::fadda(int i) {
6921 emit_farith(0xDC, 0xC0, i);
6922 }
6923
6924 void Assembler::faddp(int i) {
6925 emit_farith(0xDE, 0xC0, i);
6926 }
6927
6928 void Assembler::fchs() {
6929 emit_int8((unsigned char)0xD9);
6930 emit_int8((unsigned char)0xE0);
6931 }
6932
6933 void Assembler::fcom(int i) {
6934 emit_farith(0xD8, 0xD0, i);
6935 }
6936
6937 void Assembler::fcomp(int i) {
6938 emit_farith(0xD8, 0xD8, i);
6939 }
6940
6941 void Assembler::fcomp_d(Address src) {
6942 InstructionMark im(this);
6943 emit_int8((unsigned char)0xDC);
6944 emit_operand32(rbx, src);
6945 }
6946
6947 void Assembler::fcomp_s(Address src) {
6948 InstructionMark im(this);
6949 emit_int8((unsigned char)0xD8);
6950 emit_operand32(rbx, src);
6951 }
6952
6953 void Assembler::fcompp() {
6954 emit_int8((unsigned char)0xDE);
6955 emit_int8((unsigned char)0xD9);
6956 }
6957
6958 void Assembler::fcos() {
6959 emit_int8((unsigned char)0xD9);
6960 emit_int8((unsigned char)0xFF);
6961 }
6962
6963 void Assembler::fdecstp() {
6964 emit_int8((unsigned char)0xD9);
6965 emit_int8((unsigned char)0xF6);
6966 }
6967
6968 void Assembler::fdiv(int i) {
6969 emit_farith(0xD8, 0xF0, i);
6970 }
6971
6972 void Assembler::fdiv_d(Address src) {
6973 InstructionMark im(this);
6974 emit_int8((unsigned char)0xDC);
6975 emit_operand32(rsi, src);
6976 }
6977
6978 void Assembler::fdiv_s(Address src) {
6979 InstructionMark im(this);
6980 emit_int8((unsigned char)0xD8);
6981 emit_operand32(rsi, src);
6982 }
6983
6984 void Assembler::fdiva(int i) {
6985 emit_farith(0xDC, 0xF8, i);
6986 }
6987
6988 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6989 // is erroneous for some of the floating-point instructions below.
6990
6991 void Assembler::fdivp(int i) {
6992 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6993 }
6994
6995 void Assembler::fdivr(int i) {
6996 emit_farith(0xD8, 0xF8, i);
6997 }
6998
6999 void Assembler::fdivr_d(Address src) {
7000 InstructionMark im(this);
7001 emit_int8((unsigned char)0xDC);
7002 emit_operand32(rdi, src);
7003 }
7004
7005 void Assembler::fdivr_s(Address src) {
7006 InstructionMark im(this);
7007 emit_int8((unsigned char)0xD8);
7008 emit_operand32(rdi, src);
7009 }
7010
7011 void Assembler::fdivra(int i) {
7012 emit_farith(0xDC, 0xF0, i);
7013 }
7014
7015 void Assembler::fdivrp(int i) {
7016 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7017 }
7018
7019 void Assembler::ffree(int i) {
7020 emit_farith(0xDD, 0xC0, i);
7021 }
7022
7023 void Assembler::fild_d(Address adr) {
7024 InstructionMark im(this);
7025 emit_int8((unsigned char)0xDF);
7026 emit_operand32(rbp, adr);
7027 }
7028
7029 void Assembler::fild_s(Address adr) {
7030 InstructionMark im(this);
7031 emit_int8((unsigned char)0xDB);
7032 emit_operand32(rax, adr);
7033 }
7034
7035 void Assembler::fincstp() {
7036 emit_int8((unsigned char)0xD9);
7037 emit_int8((unsigned char)0xF7);
7038 }
7039
7040 void Assembler::finit() {
7041 emit_int8((unsigned char)0x9B);
7042 emit_int8((unsigned char)0xDB);
7043 emit_int8((unsigned char)0xE3);
7044 }
7045
7046 void Assembler::fist_s(Address adr) {
7047 InstructionMark im(this);
7048 emit_int8((unsigned char)0xDB);
7049 emit_operand32(rdx, adr);
7050 }
7051
7052 void Assembler::fistp_d(Address adr) {
7053 InstructionMark im(this);
7054 emit_int8((unsigned char)0xDF);
7055 emit_operand32(rdi, adr);
7056 }
7057
7058 void Assembler::fistp_s(Address adr) {
7059 InstructionMark im(this);
7060 emit_int8((unsigned char)0xDB);
7061 emit_operand32(rbx, adr);
7062 }
7063
7064 void Assembler::fld1() {
7065 emit_int8((unsigned char)0xD9);
7066 emit_int8((unsigned char)0xE8);
7067 }
7068
7069 void Assembler::fld_d(Address adr) {
7070 InstructionMark im(this);
7071 emit_int8((unsigned char)0xDD);
7072 emit_operand32(rax, adr);
7073 }
7074
7075 void Assembler::fld_s(Address adr) {
7076 InstructionMark im(this);
7077 emit_int8((unsigned char)0xD9);
7078 emit_operand32(rax, adr);
7079 }
7080
7081
7082 void Assembler::fld_s(int index) {
7083 emit_farith(0xD9, 0xC0, index);
7084 }
7085
7086 void Assembler::fld_x(Address adr) {
7087 InstructionMark im(this);
7088 emit_int8((unsigned char)0xDB);
7089 emit_operand32(rbp, adr);
7090 }
7091
7092 void Assembler::fldcw(Address src) {
7093 InstructionMark im(this);
7094 emit_int8((unsigned char)0xD9);
7095 emit_operand32(rbp, src);
7096 }
7097
7098 void Assembler::fldenv(Address src) {
7099 InstructionMark im(this);
7100 emit_int8((unsigned char)0xD9);
7101 emit_operand32(rsp, src);
7102 }
7103
7104 void Assembler::fldlg2() {
7105 emit_int8((unsigned char)0xD9);
7106 emit_int8((unsigned char)0xEC);
7107 }
7108
7109 void Assembler::fldln2() {
7110 emit_int8((unsigned char)0xD9);
7111 emit_int8((unsigned char)0xED);
7112 }
7113
7114 void Assembler::fldz() {
7115 emit_int8((unsigned char)0xD9);
7116 emit_int8((unsigned char)0xEE);
7117 }
7118
7119 void Assembler::flog() {
7120 fldln2();
7121 fxch();
7122 fyl2x();
7123 }
7124
7125 void Assembler::flog10() {
7126 fldlg2();
7127 fxch();
7128 fyl2x();
7129 }
7130
7131 void Assembler::fmul(int i) {
7132 emit_farith(0xD8, 0xC8, i);
7133 }
7134
7135 void Assembler::fmul_d(Address src) {
7136 InstructionMark im(this);
7137 emit_int8((unsigned char)0xDC);
7138 emit_operand32(rcx, src);
7139 }
7140
7141 void Assembler::fmul_s(Address src) {
7142 InstructionMark im(this);
7143 emit_int8((unsigned char)0xD8);
7144 emit_operand32(rcx, src);
7145 }
7146
7147 void Assembler::fmula(int i) {
7148 emit_farith(0xDC, 0xC8, i);
7149 }
7150
7151 void Assembler::fmulp(int i) {
7152 emit_farith(0xDE, 0xC8, i);
7153 }
7154
7155 void Assembler::fnsave(Address dst) {
7156 InstructionMark im(this);
7157 emit_int8((unsigned char)0xDD);
7158 emit_operand32(rsi, dst);
7159 }
7160
7161 void Assembler::fnstcw(Address src) {
7162 InstructionMark im(this);
7163 emit_int8((unsigned char)0x9B);
7164 emit_int8((unsigned char)0xD9);
7165 emit_operand32(rdi, src);
7166 }
7167
7168 void Assembler::fnstsw_ax() {
7169 emit_int8((unsigned char)0xDF);
7170 emit_int8((unsigned char)0xE0);
7171 }
7172
7173 void Assembler::fprem() {
7174 emit_int8((unsigned char)0xD9);
7175 emit_int8((unsigned char)0xF8);
7176 }
7177
7178 void Assembler::fprem1() {
7179 emit_int8((unsigned char)0xD9);
7180 emit_int8((unsigned char)0xF5);
7181 }
7182
7183 void Assembler::frstor(Address src) {
7184 InstructionMark im(this);
7185 emit_int8((unsigned char)0xDD);
7186 emit_operand32(rsp, src);
7187 }
7188
7189 void Assembler::fsin() {
7190 emit_int8((unsigned char)0xD9);
7191 emit_int8((unsigned char)0xFE);
7192 }
7193
7194 void Assembler::fsqrt() {
7195 emit_int8((unsigned char)0xD9);
7196 emit_int8((unsigned char)0xFA);
7197 }
7198
7199 void Assembler::fst_d(Address adr) {
7200 InstructionMark im(this);
7201 emit_int8((unsigned char)0xDD);
7202 emit_operand32(rdx, adr);
7203 }
7204
7205 void Assembler::fst_s(Address adr) {
7206 InstructionMark im(this);
7207 emit_int8((unsigned char)0xD9);
7208 emit_operand32(rdx, adr);
7209 }
7210
7211 void Assembler::fstp_d(Address adr) {
7212 InstructionMark im(this);
7213 emit_int8((unsigned char)0xDD);
7214 emit_operand32(rbx, adr);
7215 }
7216
7217 void Assembler::fstp_d(int index) {
7218 emit_farith(0xDD, 0xD8, index);
7219 }
7220
7221 void Assembler::fstp_s(Address adr) {
7222 InstructionMark im(this);
7223 emit_int8((unsigned char)0xD9);
7224 emit_operand32(rbx, adr);
7225 }
7226
7227 void Assembler::fstp_x(Address adr) {
7228 InstructionMark im(this);
7229 emit_int8((unsigned char)0xDB);
7230 emit_operand32(rdi, adr);
7231 }
7232
7233 void Assembler::fsub(int i) {
7234 emit_farith(0xD8, 0xE0, i);
7235 }
7236
7237 void Assembler::fsub_d(Address src) {
7238 InstructionMark im(this);
7239 emit_int8((unsigned char)0xDC);
7240 emit_operand32(rsp, src);
7241 }
7242
7243 void Assembler::fsub_s(Address src) {
7244 InstructionMark im(this);
7245 emit_int8((unsigned char)0xD8);
7246 emit_operand32(rsp, src);
7247 }
7248
7249 void Assembler::fsuba(int i) {
7250 emit_farith(0xDC, 0xE8, i);
7251 }
7252
7253 void Assembler::fsubp(int i) {
7254 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7255 }
7256
7257 void Assembler::fsubr(int i) {
7258 emit_farith(0xD8, 0xE8, i);
7259 }
7260
7261 void Assembler::fsubr_d(Address src) {
7262 InstructionMark im(this);
7263 emit_int8((unsigned char)0xDC);
7264 emit_operand32(rbp, src);
7265 }
7266
7267 void Assembler::fsubr_s(Address src) {
7268 InstructionMark im(this);
7269 emit_int8((unsigned char)0xD8);
7270 emit_operand32(rbp, src);
7271 }
7272
7273 void Assembler::fsubra(int i) {
7274 emit_farith(0xDC, 0xE0, i);
7275 }
7276
7277 void Assembler::fsubrp(int i) {
7278 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7279 }
7280
7281 void Assembler::ftan() {
7282 emit_int8((unsigned char)0xD9);
7283 emit_int8((unsigned char)0xF2);
7284 emit_int8((unsigned char)0xDD);
7285 emit_int8((unsigned char)0xD8);
7286 }
7287
7288 void Assembler::ftst() {
7289 emit_int8((unsigned char)0xD9);
7290 emit_int8((unsigned char)0xE4);
7291 }
7292
7293 void Assembler::fucomi(int i) {
7294 // make sure the instruction is supported (introduced for P6, together with cmov)
7295 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7296 emit_farith(0xDB, 0xE8, i);
7297 }
7298
7299 void Assembler::fucomip(int i) {
7300 // make sure the instruction is supported (introduced for P6, together with cmov)
7301 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7302 emit_farith(0xDF, 0xE8, i);
7303 }
7304
7305 void Assembler::fwait() {
7306 emit_int8((unsigned char)0x9B);
7307 }
7308
7309 void Assembler::fxch(int i) {
7310 emit_farith(0xD9, 0xC8, i);
7311 }
7312
7313 void Assembler::fyl2x() {
7314 emit_int8((unsigned char)0xD9);
7315 emit_int8((unsigned char)0xF1);
7316 }
7317
7318 void Assembler::frndint() {
7319 emit_int8((unsigned char)0xD9);
7320 emit_int8((unsigned char)0xFC);
7321 }
7322
7323 void Assembler::f2xm1() {
7324 emit_int8((unsigned char)0xD9);
7325 emit_int8((unsigned char)0xF0);
7326 }
7327
7328 void Assembler::fldl2e() {
7329 emit_int8((unsigned char)0xD9);
7330 emit_int8((unsigned char)0xEA);
7331 }
7332
7333 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7334 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7335 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7336 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7337
7338 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7339 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7340 if (pre > 0) {
7341 emit_int8(simd_pre[pre]);
7342 }
7343 if (rex_w) {
7344 prefixq(adr, xreg);
7345 } else {
7346 prefix(adr, xreg);
7347 }
7348 if (opc > 0) {
7349 emit_int8(0x0F);
7350 int opc2 = simd_opc[opc];
7351 if (opc2 > 0) {
7352 emit_int8(opc2);
7353 }
7354 }
7355 }
7356
7357 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7358 if (pre > 0) {
7359 emit_int8(simd_pre[pre]);
7360 }
7361 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7362 if (opc > 0) {
7363 emit_int8(0x0F);
7364 int opc2 = simd_opc[opc];
7365 if (opc2 > 0) {
7366 emit_int8(opc2);
7367 }
7368 }
7369 return encode;
7370 }
7371
7372
7373 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7374 int vector_len = _attributes->get_vector_len();
7375 bool vex_w = _attributes->is_rex_vex_w();
7376 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7377 prefix(VEX_3bytes);
7378
7379 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7380 byte1 = (~byte1) & 0xE0;
7381 byte1 |= opc;
7382 emit_int8(byte1);
7383
7384 int byte2 = ((~nds_enc) & 0xf) << 3;
7385 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7386 emit_int8(byte2);
7387 } else {
7388 prefix(VEX_2bytes);
7389
7390 int byte1 = vex_r ? VEX_R : 0;
7391 byte1 = (~byte1) & 0x80;
7392 byte1 |= ((~nds_enc) & 0xf) << 3;
7393 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7394 emit_int8(byte1);
7395 }
7396 }
7397
7398 // This is a 4 byte encoding
7399 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7400 // EVEX 0x62 prefix
7401 prefix(EVEX_4bytes);
7402 bool vex_w = _attributes->is_rex_vex_w();
7403 int evex_encoding = (vex_w ? VEX_W : 0);
7404 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7405 _attributes->set_evex_encoding(evex_encoding);
7406
7407 // P0: byte 2, initialized to RXBR`00mm
7408 // instead of not'd
7409 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7410 byte2 = (~byte2) & 0xF0;
7411 // confine opc opcode extensions in mm bits to lower two bits
7412 // of form {0F, 0F_38, 0F_3A}
7413 byte2 |= opc;
7414 emit_int8(byte2);
7415
7416 // P1: byte 3 as Wvvvv1pp
7417 int byte3 = ((~nds_enc) & 0xf) << 3;
7418 // p[10] is always 1
7419 byte3 |= EVEX_F;
7420 byte3 |= (vex_w & 1) << 7;
7421 // confine pre opcode extensions in pp bits to lower two bits
7422 // of form {66, F3, F2}
7423 byte3 |= pre;
7424 emit_int8(byte3);
7425
7426 // P2: byte 4 as zL'Lbv'aaa
7427 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7428 int byte4 = (_attributes->is_no_reg_mask()) ?
7429 0 :
7430 _attributes->get_embedded_opmask_register_specifier();
7431 // EVEX.v` for extending EVEX.vvvv or VIDX
7432 byte4 |= (evex_v ? 0: EVEX_V);
7433 // third EXEC.b for broadcast actions
7434 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7435 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7436 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7437 // last is EVEX.z for zero/merge actions
7438 if (_attributes->is_no_reg_mask() == false) {
7439 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7440 }
7441 emit_int8(byte4);
7442 }
7443
7444 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7445 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7446 bool vex_b = adr.base_needs_rex();
7447 bool vex_x = adr.index_needs_rex();
7448 set_attributes(attributes);
7449 attributes->set_current_assembler(this);
7450
7451 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7452 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7453 switch (attributes->get_vector_len()) {
7454 case AVX_128bit:
7455 case AVX_256bit:
7456 attributes->set_is_legacy_mode();
7457 break;
7458 }
7459 }
7460
7461 // For pure EVEX check and see if this instruction
7462 // is allowed in legacy mode and has resources which will
7463 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7464 // else that field is set when we encode to EVEX
7465 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7466 !_is_managed && !attributes->is_evex_instruction()) {
7467 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7468 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7469 if (check_register_bank) {
7470 // check nds_enc and xreg_enc for upper bank usage
7471 if (nds_enc < 16 && xreg_enc < 16) {
7472 attributes->set_is_legacy_mode();
7473 }
7474 } else {
7475 attributes->set_is_legacy_mode();
7476 }
7477 }
7478 }
7479
7480 _is_managed = false;
7481 if (UseAVX > 2 && !attributes->is_legacy_mode())
7482 {
7483 bool evex_r = (xreg_enc >= 16);
7484 bool evex_v = (nds_enc >= 16);
7485 attributes->set_is_evex_instruction();
7486 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7487 } else {
7488 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7489 attributes->set_rex_vex_w(false);
7490 }
7491 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7492 }
7493 }
7494
7495 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7496 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7497 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7498 bool vex_x = false;
7499 set_attributes(attributes);
7500 attributes->set_current_assembler(this);
7501 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7502
7503 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7504 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7505 switch (attributes->get_vector_len()) {
7506 case AVX_128bit:
7507 case AVX_256bit:
7508 if (check_register_bank) {
7509 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7510 // up propagate arithmetic instructions to meet RA requirements
7511 attributes->set_vector_len(AVX_512bit);
7512 } else {
7513 attributes->set_is_legacy_mode();
7514 }
7515 } else {
7516 attributes->set_is_legacy_mode();
7517 }
7518 break;
7519 }
7520 }
7521
7522 // For pure EVEX check and see if this instruction
7523 // is allowed in legacy mode and has resources which will
7524 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7525 // else that field is set when we encode to EVEX
7526 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7527 !_is_managed && !attributes->is_evex_instruction()) {
7528 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7529 if (check_register_bank) {
7530 // check dst_enc, nds_enc and src_enc for upper bank usage
7531 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7532 attributes->set_is_legacy_mode();
7533 }
7534 } else {
7535 attributes->set_is_legacy_mode();
7536 }
7537 }
7538 }
7539
7540 _is_managed = false;
7541 if (UseAVX > 2 && !attributes->is_legacy_mode())
7542 {
7543 bool evex_r = (dst_enc >= 16);
7544 bool evex_v = (nds_enc >= 16);
7545 // can use vex_x as bank extender on rm encoding
7546 vex_x = (src_enc >= 16);
7547 attributes->set_is_evex_instruction();
7548 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7549 } else {
7550 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7551 attributes->set_rex_vex_w(false);
7552 }
7553 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7554 }
7555
7556 // return modrm byte components for operands
7557 return (((dst_enc & 7) << 3) | (src_enc & 7));
7558 }
7559
7560
7561 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7562 VexOpcode opc, InstructionAttr *attributes) {
7563 if (UseAVX > 0) {
7564 int xreg_enc = xreg->encoding();
7565 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7566 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7567 } else {
7568 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7569 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7570 }
7571 }
7572
7573 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7574 VexOpcode opc, InstructionAttr *attributes) {
7575 int dst_enc = dst->encoding();
7576 int src_enc = src->encoding();
7577 if (UseAVX > 0) {
7578 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7579 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7580 } else {
7581 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7582 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7583 }
7584 }
7585
7586 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7587 assert(VM_Version::supports_avx(), "");
7588 assert(!VM_Version::supports_evex(), "");
7589 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7590 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7591 emit_int8((unsigned char)0xC2);
7592 emit_int8((unsigned char)(0xC0 | encode));
7593 emit_int8((unsigned char)(0xF & cop));
7594 }
7595
7596 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7597 assert(VM_Version::supports_avx(), "");
7598 assert(!VM_Version::supports_evex(), "");
7599 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7600 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7601 emit_int8((unsigned char)0x4B);
7602 emit_int8((unsigned char)(0xC0 | encode));
7603 int src2_enc = src2->encoding();
7604 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7605 }
7606
7607 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7608 assert(VM_Version::supports_avx(), "");
7609 assert(!VM_Version::supports_evex(), "");
7610 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7611 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7612 emit_int8((unsigned char)0xC2);
7613 emit_int8((unsigned char)(0xC0 | encode));
7614 emit_int8((unsigned char)(0xF & cop));
7615 }
7616
7617 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7618 assert(VM_Version::supports_avx(), "");
7619 assert(!VM_Version::supports_evex(), "");
7620 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7621 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7622 emit_int8((unsigned char)0x4A);
7623 emit_int8((unsigned char)(0xC0 | encode));
7624 int src2_enc = src2->encoding();
7625 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7626 }
7627
7628 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7629 assert(VM_Version::supports_avx2(), "");
7630 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7631 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7632 emit_int8((unsigned char)0x02);
7633 emit_int8((unsigned char)(0xC0 | encode));
7634 emit_int8((unsigned char)imm8);
7635 }
7636
7637 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7638 assert(VM_Version::supports_bmi2(), "");
7639 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7640 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7641 emit_int8((unsigned char)0xF7);
7642 emit_int8((unsigned char)(0xC0 | encode));
7643 }
7644
7645 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7646 assert(VM_Version::supports_bmi2(), "");
7647 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7648 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7649 emit_int8((unsigned char)0xF7);
7650 emit_int8((unsigned char)(0xC0 | encode));
7651 }
7652
7653 #ifndef _LP64
7654
7655 void Assembler::incl(Register dst) {
7656 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7657 emit_int8(0x40 | dst->encoding());
7658 }
7659
7660 void Assembler::lea(Register dst, Address src) {
7661 leal(dst, src);
7662 }
7663
7664 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7665 InstructionMark im(this);
7666 emit_int8((unsigned char)0xC7);
7667 emit_operand(rax, dst);
7668 emit_data((int)imm32, rspec, 0);
7669 }
7670
7671 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7672 InstructionMark im(this);
7673 int encode = prefix_and_encode(dst->encoding());
7674 emit_int8((unsigned char)(0xB8 | encode));
7675 emit_data((int)imm32, rspec, 0);
7676 }
7677
7678 void Assembler::popa() { // 32bit
7679 emit_int8(0x61);
7680 }
7681
7682 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7683 InstructionMark im(this);
7684 emit_int8(0x68);
7685 emit_data(imm32, rspec, 0);
7686 }
7687
7688 void Assembler::pusha() { // 32bit
7689 emit_int8(0x60);
7690 }
7691
7692 void Assembler::set_byte_if_not_zero(Register dst) {
7693 emit_int8(0x0F);
7694 emit_int8((unsigned char)0x95);
7695 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7696 }
7697
7698 void Assembler::shldl(Register dst, Register src) {
7699 emit_int8(0x0F);
7700 emit_int8((unsigned char)0xA5);
7701 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7702 }
7703
7704 // 0F A4 / r ib
7705 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7706 emit_int8(0x0F);
7707 emit_int8((unsigned char)0xA4);
7708 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7709 emit_int8(imm8);
7710 }
7711
7712 void Assembler::shrdl(Register dst, Register src) {
7713 emit_int8(0x0F);
7714 emit_int8((unsigned char)0xAD);
7715 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7716 }
7717
7718 #else // LP64
7719
7720 void Assembler::set_byte_if_not_zero(Register dst) {
7721 int enc = prefix_and_encode(dst->encoding(), true);
7722 emit_int8(0x0F);
7723 emit_int8((unsigned char)0x95);
7724 emit_int8((unsigned char)(0xE0 | enc));
7725 }
7726
7727 // 64bit only pieces of the assembler
7728 // This should only be used by 64bit instructions that can use rip-relative
7729 // it cannot be used by instructions that want an immediate value.
7730
7731 bool Assembler::reachable(AddressLiteral adr) {
7732 int64_t disp;
7733 // None will force a 64bit literal to the code stream. Likely a placeholder
7734 // for something that will be patched later and we need to certain it will
7735 // always be reachable.
7736 if (adr.reloc() == relocInfo::none) {
7737 return false;
7738 }
7739 if (adr.reloc() == relocInfo::internal_word_type) {
7740 // This should be rip relative and easily reachable.
7741 return true;
7742 }
7743 if (adr.reloc() == relocInfo::virtual_call_type ||
7744 adr.reloc() == relocInfo::opt_virtual_call_type ||
7745 adr.reloc() == relocInfo::static_call_type ||
7746 adr.reloc() == relocInfo::static_stub_type ) {
7747 // This should be rip relative within the code cache and easily
7748 // reachable until we get huge code caches. (At which point
7749 // ic code is going to have issues).
7750 return true;
7751 }
7752 if (adr.reloc() != relocInfo::external_word_type &&
7753 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7754 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7755 adr.reloc() != relocInfo::runtime_call_type ) {
7756 return false;
7757 }
7758
7759 // Stress the correction code
7760 if (ForceUnreachable) {
7761 // Must be runtimecall reloc, see if it is in the codecache
7762 // Flipping stuff in the codecache to be unreachable causes issues
7763 // with things like inline caches where the additional instructions
7764 // are not handled.
7765 if (CodeCache::find_blob(adr._target) == NULL) {
7766 return false;
7767 }
7768 }
7769 // For external_word_type/runtime_call_type if it is reachable from where we
7770 // are now (possibly a temp buffer) and where we might end up
7771 // anywhere in the codeCache then we are always reachable.
7772 // This would have to change if we ever save/restore shared code
7773 // to be more pessimistic.
7774 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7775 if (!is_simm32(disp)) return false;
7776 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7777 if (!is_simm32(disp)) return false;
7778
7779 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7780
7781 // Because rip relative is a disp + address_of_next_instruction and we
7782 // don't know the value of address_of_next_instruction we apply a fudge factor
7783 // to make sure we will be ok no matter the size of the instruction we get placed into.
7784 // We don't have to fudge the checks above here because they are already worst case.
7785
7786 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7787 // + 4 because better safe than sorry.
7788 const int fudge = 12 + 4;
7789 if (disp < 0) {
7790 disp -= fudge;
7791 } else {
7792 disp += fudge;
7793 }
7794 return is_simm32(disp);
7795 }
7796
7797 // Check if the polling page is not reachable from the code cache using rip-relative
7798 // addressing.
7799 bool Assembler::is_polling_page_far() {
7800 intptr_t addr = (intptr_t)os::get_polling_page();
7801 return ForceUnreachable ||
7802 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7803 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7804 }
7805
7806 void Assembler::emit_data64(jlong data,
7807 relocInfo::relocType rtype,
7808 int format) {
7809 if (rtype == relocInfo::none) {
7810 emit_int64(data);
7811 } else {
7812 emit_data64(data, Relocation::spec_simple(rtype), format);
7813 }
7814 }
7815
7816 void Assembler::emit_data64(jlong data,
7817 RelocationHolder const& rspec,
7818 int format) {
7819 assert(imm_operand == 0, "default format must be immediate in this file");
7820 assert(imm_operand == format, "must be immediate");
7821 assert(inst_mark() != NULL, "must be inside InstructionMark");
7822 // Do not use AbstractAssembler::relocate, which is not intended for
7823 // embedded words. Instead, relocate to the enclosing instruction.
7824 code_section()->relocate(inst_mark(), rspec, format);
7825 #ifdef ASSERT
7826 check_relocation(rspec, format);
7827 #endif
7828 emit_int64(data);
7829 }
7830
7831 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7832 if (reg_enc >= 8) {
7833 prefix(REX_B);
7834 reg_enc -= 8;
7835 } else if (byteinst && reg_enc >= 4) {
7836 prefix(REX);
7837 }
7838 return reg_enc;
7839 }
7840
7841 int Assembler::prefixq_and_encode(int reg_enc) {
7842 if (reg_enc < 8) {
7843 prefix(REX_W);
7844 } else {
7845 prefix(REX_WB);
7846 reg_enc -= 8;
7847 }
7848 return reg_enc;
7849 }
7850
7851 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7852 if (dst_enc < 8) {
7853 if (src_enc >= 8) {
7854 prefix(REX_B);
7855 src_enc -= 8;
7856 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7857 prefix(REX);
7858 }
7859 } else {
7860 if (src_enc < 8) {
7861 prefix(REX_R);
7862 } else {
7863 prefix(REX_RB);
7864 src_enc -= 8;
7865 }
7866 dst_enc -= 8;
7867 }
7868 return dst_enc << 3 | src_enc;
7869 }
7870
7871 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7872 if (dst_enc < 8) {
7873 if (src_enc < 8) {
7874 prefix(REX_W);
7875 } else {
7876 prefix(REX_WB);
7877 src_enc -= 8;
7878 }
7879 } else {
7880 if (src_enc < 8) {
7881 prefix(REX_WR);
7882 } else {
7883 prefix(REX_WRB);
7884 src_enc -= 8;
7885 }
7886 dst_enc -= 8;
7887 }
7888 return dst_enc << 3 | src_enc;
7889 }
7890
7891 void Assembler::prefix(Register reg) {
7892 if (reg->encoding() >= 8) {
7893 prefix(REX_B);
7894 }
7895 }
7896
7897 void Assembler::prefix(Register dst, Register src, Prefix p) {
7898 if (src->encoding() >= 8) {
7899 p = (Prefix)(p | REX_B);
7900 }
7901 if (dst->encoding() >= 8) {
7902 p = (Prefix)( p | REX_R);
7903 }
7904 if (p != Prefix_EMPTY) {
7905 // do not generate an empty prefix
7906 prefix(p);
7907 }
7908 }
7909
7910 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7911 if (adr.base_needs_rex()) {
7912 if (adr.index_needs_rex()) {
7913 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7914 } else {
7915 prefix(REX_B);
7916 }
7917 } else {
7918 if (adr.index_needs_rex()) {
7919 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7920 }
7921 }
7922 if (dst->encoding() >= 8) {
7923 p = (Prefix)(p | REX_R);
7924 }
7925 if (p != Prefix_EMPTY) {
7926 // do not generate an empty prefix
7927 prefix(p);
7928 }
7929 }
7930
7931 void Assembler::prefix(Address adr) {
7932 if (adr.base_needs_rex()) {
7933 if (adr.index_needs_rex()) {
7934 prefix(REX_XB);
7935 } else {
7936 prefix(REX_B);
7937 }
7938 } else {
7939 if (adr.index_needs_rex()) {
7940 prefix(REX_X);
7941 }
7942 }
7943 }
7944
7945 void Assembler::prefixq(Address adr) {
7946 if (adr.base_needs_rex()) {
7947 if (adr.index_needs_rex()) {
7948 prefix(REX_WXB);
7949 } else {
7950 prefix(REX_WB);
7951 }
7952 } else {
7953 if (adr.index_needs_rex()) {
7954 prefix(REX_WX);
7955 } else {
7956 prefix(REX_W);
7957 }
7958 }
7959 }
7960
7961
7962 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7963 if (reg->encoding() < 8) {
7964 if (adr.base_needs_rex()) {
7965 if (adr.index_needs_rex()) {
7966 prefix(REX_XB);
7967 } else {
7968 prefix(REX_B);
7969 }
7970 } else {
7971 if (adr.index_needs_rex()) {
7972 prefix(REX_X);
7973 } else if (byteinst && reg->encoding() >= 4 ) {
7974 prefix(REX);
7975 }
7976 }
7977 } else {
7978 if (adr.base_needs_rex()) {
7979 if (adr.index_needs_rex()) {
7980 prefix(REX_RXB);
7981 } else {
7982 prefix(REX_RB);
7983 }
7984 } else {
7985 if (adr.index_needs_rex()) {
7986 prefix(REX_RX);
7987 } else {
7988 prefix(REX_R);
7989 }
7990 }
7991 }
7992 }
7993
7994 void Assembler::prefixq(Address adr, Register src) {
7995 if (src->encoding() < 8) {
7996 if (adr.base_needs_rex()) {
7997 if (adr.index_needs_rex()) {
7998 prefix(REX_WXB);
7999 } else {
8000 prefix(REX_WB);
8001 }
8002 } else {
8003 if (adr.index_needs_rex()) {
8004 prefix(REX_WX);
8005 } else {
8006 prefix(REX_W);
8007 }
8008 }
8009 } else {
8010 if (adr.base_needs_rex()) {
8011 if (adr.index_needs_rex()) {
8012 prefix(REX_WRXB);
8013 } else {
8014 prefix(REX_WRB);
8015 }
8016 } else {
8017 if (adr.index_needs_rex()) {
8018 prefix(REX_WRX);
8019 } else {
8020 prefix(REX_WR);
8021 }
8022 }
8023 }
8024 }
8025
8026 void Assembler::prefix(Address adr, XMMRegister reg) {
8027 if (reg->encoding() < 8) {
8028 if (adr.base_needs_rex()) {
8029 if (adr.index_needs_rex()) {
8030 prefix(REX_XB);
8031 } else {
8032 prefix(REX_B);
8033 }
8034 } else {
8035 if (adr.index_needs_rex()) {
8036 prefix(REX_X);
8037 }
8038 }
8039 } else {
8040 if (adr.base_needs_rex()) {
8041 if (adr.index_needs_rex()) {
8042 prefix(REX_RXB);
8043 } else {
8044 prefix(REX_RB);
8045 }
8046 } else {
8047 if (adr.index_needs_rex()) {
8048 prefix(REX_RX);
8049 } else {
8050 prefix(REX_R);
8051 }
8052 }
8053 }
8054 }
8055
8056 void Assembler::prefixq(Address adr, XMMRegister src) {
8057 if (src->encoding() < 8) {
8058 if (adr.base_needs_rex()) {
8059 if (adr.index_needs_rex()) {
8060 prefix(REX_WXB);
8061 } else {
8062 prefix(REX_WB);
8063 }
8064 } else {
8065 if (adr.index_needs_rex()) {
8066 prefix(REX_WX);
8067 } else {
8068 prefix(REX_W);
8069 }
8070 }
8071 } else {
8072 if (adr.base_needs_rex()) {
8073 if (adr.index_needs_rex()) {
8074 prefix(REX_WRXB);
8075 } else {
8076 prefix(REX_WRB);
8077 }
8078 } else {
8079 if (adr.index_needs_rex()) {
8080 prefix(REX_WRX);
8081 } else {
8082 prefix(REX_WR);
8083 }
8084 }
8085 }
8086 }
8087
8088 void Assembler::adcq(Register dst, int32_t imm32) {
8089 (void) prefixq_and_encode(dst->encoding());
8090 emit_arith(0x81, 0xD0, dst, imm32);
8091 }
8092
8093 void Assembler::adcq(Register dst, Address src) {
8094 InstructionMark im(this);
8095 prefixq(src, dst);
8096 emit_int8(0x13);
8097 emit_operand(dst, src);
8098 }
8099
8100 void Assembler::adcq(Register dst, Register src) {
8101 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8102 emit_arith(0x13, 0xC0, dst, src);
8103 }
8104
8105 void Assembler::addq(Address dst, int32_t imm32) {
8106 InstructionMark im(this);
8107 prefixq(dst);
8108 emit_arith_operand(0x81, rax, dst,imm32);
8109 }
8110
8111 void Assembler::addq(Address dst, Register src) {
8112 InstructionMark im(this);
8113 prefixq(dst, src);
8114 emit_int8(0x01);
8115 emit_operand(src, dst);
8116 }
8117
8118 void Assembler::addq(Register dst, int32_t imm32) {
8119 (void) prefixq_and_encode(dst->encoding());
8120 emit_arith(0x81, 0xC0, dst, imm32);
8121 }
8122
8123 void Assembler::addq(Register dst, Address src) {
8124 InstructionMark im(this);
8125 prefixq(src, dst);
8126 emit_int8(0x03);
8127 emit_operand(dst, src);
8128 }
8129
8130 void Assembler::addq(Register dst, Register src) {
8131 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8132 emit_arith(0x03, 0xC0, dst, src);
8133 }
8134
8135 void Assembler::adcxq(Register dst, Register src) {
8136 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8137 emit_int8((unsigned char)0x66);
8138 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8139 emit_int8(0x0F);
8140 emit_int8(0x38);
8141 emit_int8((unsigned char)0xF6);
8142 emit_int8((unsigned char)(0xC0 | encode));
8143 }
8144
8145 void Assembler::adoxq(Register dst, Register src) {
8146 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8147 emit_int8((unsigned char)0xF3);
8148 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8149 emit_int8(0x0F);
8150 emit_int8(0x38);
8151 emit_int8((unsigned char)0xF6);
8152 emit_int8((unsigned char)(0xC0 | encode));
8153 }
8154
8155 void Assembler::andq(Address dst, int32_t imm32) {
8156 InstructionMark im(this);
8157 prefixq(dst);
8158 emit_int8((unsigned char)0x81);
8159 emit_operand(rsp, dst, 4);
8160 emit_int32(imm32);
8161 }
8162
8163 void Assembler::andq(Register dst, int32_t imm32) {
8164 (void) prefixq_and_encode(dst->encoding());
8165 emit_arith(0x81, 0xE0, dst, imm32);
8166 }
8167
8168 void Assembler::andq(Register dst, Address src) {
8169 InstructionMark im(this);
8170 prefixq(src, dst);
8171 emit_int8(0x23);
8172 emit_operand(dst, src);
8173 }
8174
8175 void Assembler::andq(Register dst, Register src) {
8176 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8177 emit_arith(0x23, 0xC0, dst, src);
8178 }
8179
8180 void Assembler::andnq(Register dst, Register src1, Register src2) {
8181 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8182 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8183 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8184 emit_int8((unsigned char)0xF2);
8185 emit_int8((unsigned char)(0xC0 | encode));
8186 }
8187
8188 void Assembler::andnq(Register dst, Register src1, Address src2) {
8189 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8190 InstructionMark im(this);
8191 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8192 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8193 emit_int8((unsigned char)0xF2);
8194 emit_operand(dst, src2);
8195 }
8196
8197 void Assembler::bsfq(Register dst, Register src) {
8198 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8199 emit_int8(0x0F);
8200 emit_int8((unsigned char)0xBC);
8201 emit_int8((unsigned char)(0xC0 | encode));
8202 }
8203
8204 void Assembler::bsrq(Register dst, Register src) {
8205 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8206 emit_int8(0x0F);
8207 emit_int8((unsigned char)0xBD);
8208 emit_int8((unsigned char)(0xC0 | encode));
8209 }
8210
8211 void Assembler::bswapq(Register reg) {
8212 int encode = prefixq_and_encode(reg->encoding());
8213 emit_int8(0x0F);
8214 emit_int8((unsigned char)(0xC8 | encode));
8215 }
8216
8217 void Assembler::blsiq(Register dst, Register src) {
8218 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8219 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8220 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8221 emit_int8((unsigned char)0xF3);
8222 emit_int8((unsigned char)(0xC0 | encode));
8223 }
8224
8225 void Assembler::blsiq(Register dst, Address src) {
8226 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8227 InstructionMark im(this);
8228 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8229 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8230 emit_int8((unsigned char)0xF3);
8231 emit_operand(rbx, src);
8232 }
8233
8234 void Assembler::blsmskq(Register dst, Register src) {
8235 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8236 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8237 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8238 emit_int8((unsigned char)0xF3);
8239 emit_int8((unsigned char)(0xC0 | encode));
8240 }
8241
8242 void Assembler::blsmskq(Register dst, Address src) {
8243 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8244 InstructionMark im(this);
8245 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8246 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8247 emit_int8((unsigned char)0xF3);
8248 emit_operand(rdx, src);
8249 }
8250
8251 void Assembler::blsrq(Register dst, Register src) {
8252 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8253 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8254 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8255 emit_int8((unsigned char)0xF3);
8256 emit_int8((unsigned char)(0xC0 | encode));
8257 }
8258
8259 void Assembler::blsrq(Register dst, Address src) {
8260 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8261 InstructionMark im(this);
8262 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8263 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8264 emit_int8((unsigned char)0xF3);
8265 emit_operand(rcx, src);
8266 }
8267
8268 void Assembler::cdqq() {
8269 prefix(REX_W);
8270 emit_int8((unsigned char)0x99);
8271 }
8272
8273 void Assembler::clflush(Address adr) {
8274 prefix(adr);
8275 emit_int8(0x0F);
8276 emit_int8((unsigned char)0xAE);
8277 emit_operand(rdi, adr);
8278 }
8279
8280 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8281 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8282 emit_int8(0x0F);
8283 emit_int8(0x40 | cc);
8284 emit_int8((unsigned char)(0xC0 | encode));
8285 }
8286
8287 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8288 InstructionMark im(this);
8289 prefixq(src, dst);
8290 emit_int8(0x0F);
8291 emit_int8(0x40 | cc);
8292 emit_operand(dst, src);
8293 }
8294
8295 void Assembler::cmpq(Address dst, int32_t imm32) {
8296 InstructionMark im(this);
8297 prefixq(dst);
8298 emit_int8((unsigned char)0x81);
8299 emit_operand(rdi, dst, 4);
8300 emit_int32(imm32);
8301 }
8302
8303 void Assembler::cmpq(Register dst, int32_t imm32) {
8304 (void) prefixq_and_encode(dst->encoding());
8305 emit_arith(0x81, 0xF8, dst, imm32);
8306 }
8307
8308 void Assembler::cmpq(Address dst, Register src) {
8309 InstructionMark im(this);
8310 prefixq(dst, src);
8311 emit_int8(0x3B);
8312 emit_operand(src, dst);
8313 }
8314
8315 void Assembler::cmpq(Register dst, Register src) {
8316 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8317 emit_arith(0x3B, 0xC0, dst, src);
8318 }
8319
8320 void Assembler::cmpq(Register dst, Address src) {
8321 InstructionMark im(this);
8322 prefixq(src, dst);
8323 emit_int8(0x3B);
8324 emit_operand(dst, src);
8325 }
8326
8327 void Assembler::cmpxchgq(Register reg, Address adr) {
8328 InstructionMark im(this);
8329 prefixq(adr, reg);
8330 emit_int8(0x0F);
8331 emit_int8((unsigned char)0xB1);
8332 emit_operand(reg, adr);
8333 }
8334
8335 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8338 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8339 emit_int8(0x2A);
8340 emit_int8((unsigned char)(0xC0 | encode));
8341 }
8342
8343 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8345 InstructionMark im(this);
8346 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8347 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8348 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8349 emit_int8(0x2A);
8350 emit_operand(dst, src);
8351 }
8352
8353 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8354 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8355 InstructionMark im(this);
8356 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8357 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8358 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8359 emit_int8(0x2A);
8360 emit_operand(dst, src);
8361 }
8362
8363 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8365 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8366 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8367 emit_int8(0x2C);
8368 emit_int8((unsigned char)(0xC0 | encode));
8369 }
8370
8371 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8372 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8373 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8374 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8375 emit_int8(0x2C);
8376 emit_int8((unsigned char)(0xC0 | encode));
8377 }
8378
8379 void Assembler::decl(Register dst) {
8380 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8381 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8382 int encode = prefix_and_encode(dst->encoding());
8383 emit_int8((unsigned char)0xFF);
8384 emit_int8((unsigned char)(0xC8 | encode));
8385 }
8386
8387 void Assembler::decq(Register dst) {
8388 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8389 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8390 int encode = prefixq_and_encode(dst->encoding());
8391 emit_int8((unsigned char)0xFF);
8392 emit_int8(0xC8 | encode);
8393 }
8394
8395 void Assembler::decq(Address dst) {
8396 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8397 InstructionMark im(this);
8398 prefixq(dst);
8399 emit_int8((unsigned char)0xFF);
8400 emit_operand(rcx, dst);
8401 }
8402
8403 void Assembler::fxrstor(Address src) {
8404 prefixq(src);
8405 emit_int8(0x0F);
8406 emit_int8((unsigned char)0xAE);
8407 emit_operand(as_Register(1), src);
8408 }
8409
8410 void Assembler::xrstor(Address src) {
8411 prefixq(src);
8412 emit_int8(0x0F);
8413 emit_int8((unsigned char)0xAE);
8414 emit_operand(as_Register(5), src);
8415 }
8416
8417 void Assembler::fxsave(Address dst) {
8418 prefixq(dst);
8419 emit_int8(0x0F);
8420 emit_int8((unsigned char)0xAE);
8421 emit_operand(as_Register(0), dst);
8422 }
8423
8424 void Assembler::xsave(Address dst) {
8425 prefixq(dst);
8426 emit_int8(0x0F);
8427 emit_int8((unsigned char)0xAE);
8428 emit_operand(as_Register(4), dst);
8429 }
8430
8431 void Assembler::idivq(Register src) {
8432 int encode = prefixq_and_encode(src->encoding());
8433 emit_int8((unsigned char)0xF7);
8434 emit_int8((unsigned char)(0xF8 | encode));
8435 }
8436
8437 void Assembler::imulq(Register dst, Register src) {
8438 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8439 emit_int8(0x0F);
8440 emit_int8((unsigned char)0xAF);
8441 emit_int8((unsigned char)(0xC0 | encode));
8442 }
8443
8444 void Assembler::imulq(Register dst, Register src, int value) {
8445 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8446 if (is8bit(value)) {
8447 emit_int8(0x6B);
8448 emit_int8((unsigned char)(0xC0 | encode));
8449 emit_int8(value & 0xFF);
8450 } else {
8451 emit_int8(0x69);
8452 emit_int8((unsigned char)(0xC0 | encode));
8453 emit_int32(value);
8454 }
8455 }
8456
8457 void Assembler::imulq(Register dst, Address src) {
8458 InstructionMark im(this);
8459 prefixq(src, dst);
8460 emit_int8(0x0F);
8461 emit_int8((unsigned char) 0xAF);
8462 emit_operand(dst, src);
8463 }
8464
8465 void Assembler::incl(Register dst) {
8466 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8467 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8468 int encode = prefix_and_encode(dst->encoding());
8469 emit_int8((unsigned char)0xFF);
8470 emit_int8((unsigned char)(0xC0 | encode));
8471 }
8472
8473 void Assembler::incq(Register dst) {
8474 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8475 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8476 int encode = prefixq_and_encode(dst->encoding());
8477 emit_int8((unsigned char)0xFF);
8478 emit_int8((unsigned char)(0xC0 | encode));
8479 }
8480
8481 void Assembler::incq(Address dst) {
8482 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8483 InstructionMark im(this);
8484 prefixq(dst);
8485 emit_int8((unsigned char)0xFF);
8486 emit_operand(rax, dst);
8487 }
8488
8489 void Assembler::lea(Register dst, Address src) {
8490 leaq(dst, src);
8491 }
8492
8493 void Assembler::leaq(Register dst, Address src) {
8494 InstructionMark im(this);
8495 prefixq(src, dst);
8496 emit_int8((unsigned char)0x8D);
8497 emit_operand(dst, src);
8498 }
8499
8500 void Assembler::mov64(Register dst, int64_t imm64) {
8501 InstructionMark im(this);
8502 int encode = prefixq_and_encode(dst->encoding());
8503 emit_int8((unsigned char)(0xB8 | encode));
8504 emit_int64(imm64);
8505 }
8506
8507 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8508 InstructionMark im(this);
8509 int encode = prefixq_and_encode(dst->encoding());
8510 emit_int8(0xB8 | encode);
8511 emit_data64(imm64, rspec);
8512 }
8513
8514 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8515 InstructionMark im(this);
8516 int encode = prefix_and_encode(dst->encoding());
8517 emit_int8((unsigned char)(0xB8 | encode));
8518 emit_data((int)imm32, rspec, narrow_oop_operand);
8519 }
8520
8521 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8522 InstructionMark im(this);
8523 prefix(dst);
8524 emit_int8((unsigned char)0xC7);
8525 emit_operand(rax, dst, 4);
8526 emit_data((int)imm32, rspec, narrow_oop_operand);
8527 }
8528
8529 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8530 InstructionMark im(this);
8531 int encode = prefix_and_encode(src1->encoding());
8532 emit_int8((unsigned char)0x81);
8533 emit_int8((unsigned char)(0xF8 | encode));
8534 emit_data((int)imm32, rspec, narrow_oop_operand);
8535 }
8536
8537 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8538 InstructionMark im(this);
8539 prefix(src1);
8540 emit_int8((unsigned char)0x81);
8541 emit_operand(rax, src1, 4);
8542 emit_data((int)imm32, rspec, narrow_oop_operand);
8543 }
8544
8545 void Assembler::lzcntq(Register dst, Register src) {
8546 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8547 emit_int8((unsigned char)0xF3);
8548 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8549 emit_int8(0x0F);
8550 emit_int8((unsigned char)0xBD);
8551 emit_int8((unsigned char)(0xC0 | encode));
8552 }
8553
8554 void Assembler::movdq(XMMRegister dst, Register src) {
8555 // table D-1 says MMX/SSE2
8556 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8557 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8558 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8559 emit_int8(0x6E);
8560 emit_int8((unsigned char)(0xC0 | encode));
8561 }
8562
8563 void Assembler::movdq(Register dst, XMMRegister src) {
8564 // table D-1 says MMX/SSE2
8565 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8566 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8567 // swap src/dst to get correct prefix
8568 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8569 emit_int8(0x7E);
8570 emit_int8((unsigned char)(0xC0 | encode));
8571 }
8572
8573 void Assembler::movq(Register dst, Register src) {
8574 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8575 emit_int8((unsigned char)0x8B);
8576 emit_int8((unsigned char)(0xC0 | encode));
8577 }
8578
8579 void Assembler::movq(Register dst, Address src) {
8580 InstructionMark im(this);
8581 prefixq(src, dst);
8582 emit_int8((unsigned char)0x8B);
8583 emit_operand(dst, src);
8584 }
8585
8586 void Assembler::movq(Address dst, Register src) {
8587 InstructionMark im(this);
8588 prefixq(dst, src);
8589 emit_int8((unsigned char)0x89);
8590 emit_operand(src, dst);
8591 }
8592
8593 void Assembler::movsbq(Register dst, Address src) {
8594 InstructionMark im(this);
8595 prefixq(src, dst);
8596 emit_int8(0x0F);
8597 emit_int8((unsigned char)0xBE);
8598 emit_operand(dst, src);
8599 }
8600
8601 void Assembler::movsbq(Register dst, Register src) {
8602 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8603 emit_int8(0x0F);
8604 emit_int8((unsigned char)0xBE);
8605 emit_int8((unsigned char)(0xC0 | encode));
8606 }
8607
8608 void Assembler::movslq(Register dst, int32_t imm32) {
8609 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8610 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8611 // as a result we shouldn't use until tested at runtime...
8612 ShouldNotReachHere();
8613 InstructionMark im(this);
8614 int encode = prefixq_and_encode(dst->encoding());
8615 emit_int8((unsigned char)(0xC7 | encode));
8616 emit_int32(imm32);
8617 }
8618
8619 void Assembler::movslq(Address dst, int32_t imm32) {
8620 assert(is_simm32(imm32), "lost bits");
8621 InstructionMark im(this);
8622 prefixq(dst);
8623 emit_int8((unsigned char)0xC7);
8624 emit_operand(rax, dst, 4);
8625 emit_int32(imm32);
8626 }
8627
8628 void Assembler::movslq(Register dst, Address src) {
8629 InstructionMark im(this);
8630 prefixq(src, dst);
8631 emit_int8(0x63);
8632 emit_operand(dst, src);
8633 }
8634
8635 void Assembler::movslq(Register dst, Register src) {
8636 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8637 emit_int8(0x63);
8638 emit_int8((unsigned char)(0xC0 | encode));
8639 }
8640
8641 void Assembler::movswq(Register dst, Address src) {
8642 InstructionMark im(this);
8643 prefixq(src, dst);
8644 emit_int8(0x0F);
8645 emit_int8((unsigned char)0xBF);
8646 emit_operand(dst, src);
8647 }
8648
8649 void Assembler::movswq(Register dst, Register src) {
8650 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8651 emit_int8((unsigned char)0x0F);
8652 emit_int8((unsigned char)0xBF);
8653 emit_int8((unsigned char)(0xC0 | encode));
8654 }
8655
8656 void Assembler::movzbq(Register dst, Address src) {
8657 InstructionMark im(this);
8658 prefixq(src, dst);
8659 emit_int8((unsigned char)0x0F);
8660 emit_int8((unsigned char)0xB6);
8661 emit_operand(dst, src);
8662 }
8663
8664 void Assembler::movzbq(Register dst, Register src) {
8665 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8666 emit_int8(0x0F);
8667 emit_int8((unsigned char)0xB6);
8668 emit_int8(0xC0 | encode);
8669 }
8670
8671 void Assembler::movzwq(Register dst, Address src) {
8672 InstructionMark im(this);
8673 prefixq(src, dst);
8674 emit_int8((unsigned char)0x0F);
8675 emit_int8((unsigned char)0xB7);
8676 emit_operand(dst, src);
8677 }
8678
8679 void Assembler::movzwq(Register dst, Register src) {
8680 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8681 emit_int8((unsigned char)0x0F);
8682 emit_int8((unsigned char)0xB7);
8683 emit_int8((unsigned char)(0xC0 | encode));
8684 }
8685
8686 void Assembler::mulq(Address src) {
8687 InstructionMark im(this);
8688 prefixq(src);
8689 emit_int8((unsigned char)0xF7);
8690 emit_operand(rsp, src);
8691 }
8692
8693 void Assembler::mulq(Register src) {
8694 int encode = prefixq_and_encode(src->encoding());
8695 emit_int8((unsigned char)0xF7);
8696 emit_int8((unsigned char)(0xE0 | encode));
8697 }
8698
8699 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8700 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8701 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8702 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8703 emit_int8((unsigned char)0xF6);
8704 emit_int8((unsigned char)(0xC0 | encode));
8705 }
8706
8707 void Assembler::negq(Register dst) {
8708 int encode = prefixq_and_encode(dst->encoding());
8709 emit_int8((unsigned char)0xF7);
8710 emit_int8((unsigned char)(0xD8 | encode));
8711 }
8712
8713 void Assembler::notq(Register dst) {
8714 int encode = prefixq_and_encode(dst->encoding());
8715 emit_int8((unsigned char)0xF7);
8716 emit_int8((unsigned char)(0xD0 | encode));
8717 }
8718
8719 void Assembler::orq(Address dst, int32_t imm32) {
8720 InstructionMark im(this);
8721 prefixq(dst);
8722 emit_int8((unsigned char)0x81);
8723 emit_operand(rcx, dst, 4);
8724 emit_int32(imm32);
8725 }
8726
8727 void Assembler::orq(Register dst, int32_t imm32) {
8728 (void) prefixq_and_encode(dst->encoding());
8729 emit_arith(0x81, 0xC8, dst, imm32);
8730 }
8731
8732 void Assembler::orq(Register dst, Address src) {
8733 InstructionMark im(this);
8734 prefixq(src, dst);
8735 emit_int8(0x0B);
8736 emit_operand(dst, src);
8737 }
8738
8739 void Assembler::orq(Register dst, Register src) {
8740 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8741 emit_arith(0x0B, 0xC0, dst, src);
8742 }
8743
8744 void Assembler::popa() { // 64bit
8745 movq(r15, Address(rsp, 0));
8746 movq(r14, Address(rsp, wordSize));
8747 movq(r13, Address(rsp, 2 * wordSize));
8748 movq(r12, Address(rsp, 3 * wordSize));
8749 movq(r11, Address(rsp, 4 * wordSize));
8750 movq(r10, Address(rsp, 5 * wordSize));
8751 movq(r9, Address(rsp, 6 * wordSize));
8752 movq(r8, Address(rsp, 7 * wordSize));
8753 movq(rdi, Address(rsp, 8 * wordSize));
8754 movq(rsi, Address(rsp, 9 * wordSize));
8755 movq(rbp, Address(rsp, 10 * wordSize));
8756 // skip rsp
8757 movq(rbx, Address(rsp, 12 * wordSize));
8758 movq(rdx, Address(rsp, 13 * wordSize));
8759 movq(rcx, Address(rsp, 14 * wordSize));
8760 movq(rax, Address(rsp, 15 * wordSize));
8761
8762 addq(rsp, 16 * wordSize);
8763 }
8764
8765 void Assembler::popcntq(Register dst, Address src) {
8766 assert(VM_Version::supports_popcnt(), "must support");
8767 InstructionMark im(this);
8768 emit_int8((unsigned char)0xF3);
8769 prefixq(src, dst);
8770 emit_int8((unsigned char)0x0F);
8771 emit_int8((unsigned char)0xB8);
8772 emit_operand(dst, src);
8773 }
8774
8775 void Assembler::popcntq(Register dst, Register src) {
8776 assert(VM_Version::supports_popcnt(), "must support");
8777 emit_int8((unsigned char)0xF3);
8778 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8779 emit_int8((unsigned char)0x0F);
8780 emit_int8((unsigned char)0xB8);
8781 emit_int8((unsigned char)(0xC0 | encode));
8782 }
8783
8784 void Assembler::popq(Address dst) {
8785 InstructionMark im(this);
8786 prefixq(dst);
8787 emit_int8((unsigned char)0x8F);
8788 emit_operand(rax, dst);
8789 }
8790
8791 void Assembler::pusha() { // 64bit
8792 // we have to store original rsp. ABI says that 128 bytes
8793 // below rsp are local scratch.
8794 movq(Address(rsp, -5 * wordSize), rsp);
8795
8796 subq(rsp, 16 * wordSize);
8797
8798 movq(Address(rsp, 15 * wordSize), rax);
8799 movq(Address(rsp, 14 * wordSize), rcx);
8800 movq(Address(rsp, 13 * wordSize), rdx);
8801 movq(Address(rsp, 12 * wordSize), rbx);
8802 // skip rsp
8803 movq(Address(rsp, 10 * wordSize), rbp);
8804 movq(Address(rsp, 9 * wordSize), rsi);
8805 movq(Address(rsp, 8 * wordSize), rdi);
8806 movq(Address(rsp, 7 * wordSize), r8);
8807 movq(Address(rsp, 6 * wordSize), r9);
8808 movq(Address(rsp, 5 * wordSize), r10);
8809 movq(Address(rsp, 4 * wordSize), r11);
8810 movq(Address(rsp, 3 * wordSize), r12);
8811 movq(Address(rsp, 2 * wordSize), r13);
8812 movq(Address(rsp, wordSize), r14);
8813 movq(Address(rsp, 0), r15);
8814 }
8815
8816 void Assembler::pushq(Address src) {
8817 InstructionMark im(this);
8818 prefixq(src);
8819 emit_int8((unsigned char)0xFF);
8820 emit_operand(rsi, src);
8821 }
8822
8823 void Assembler::rclq(Register dst, int imm8) {
8824 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8825 int encode = prefixq_and_encode(dst->encoding());
8826 if (imm8 == 1) {
8827 emit_int8((unsigned char)0xD1);
8828 emit_int8((unsigned char)(0xD0 | encode));
8829 } else {
8830 emit_int8((unsigned char)0xC1);
8831 emit_int8((unsigned char)(0xD0 | encode));
8832 emit_int8(imm8);
8833 }
8834 }
8835
8836 void Assembler::rcrq(Register dst, int imm8) {
8837 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8838 int encode = prefixq_and_encode(dst->encoding());
8839 if (imm8 == 1) {
8840 emit_int8((unsigned char)0xD1);
8841 emit_int8((unsigned char)(0xD8 | encode));
8842 } else {
8843 emit_int8((unsigned char)0xC1);
8844 emit_int8((unsigned char)(0xD8 | encode));
8845 emit_int8(imm8);
8846 }
8847 }
8848
8849 void Assembler::rorq(Register dst, int imm8) {
8850 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8851 int encode = prefixq_and_encode(dst->encoding());
8852 if (imm8 == 1) {
8853 emit_int8((unsigned char)0xD1);
8854 emit_int8((unsigned char)(0xC8 | encode));
8855 } else {
8856 emit_int8((unsigned char)0xC1);
8857 emit_int8((unsigned char)(0xc8 | encode));
8858 emit_int8(imm8);
8859 }
8860 }
8861
8862 void Assembler::rorxq(Register dst, Register src, int imm8) {
8863 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8864 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8865 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8866 emit_int8((unsigned char)0xF0);
8867 emit_int8((unsigned char)(0xC0 | encode));
8868 emit_int8(imm8);
8869 }
8870
8871 void Assembler::rorxd(Register dst, Register src, int imm8) {
8872 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8873 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8874 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8875 emit_int8((unsigned char)0xF0);
8876 emit_int8((unsigned char)(0xC0 | encode));
8877 emit_int8(imm8);
8878 }
8879
8880 void Assembler::sarq(Register dst, int imm8) {
8881 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8882 int encode = prefixq_and_encode(dst->encoding());
8883 if (imm8 == 1) {
8884 emit_int8((unsigned char)0xD1);
8885 emit_int8((unsigned char)(0xF8 | encode));
8886 } else {
8887 emit_int8((unsigned char)0xC1);
8888 emit_int8((unsigned char)(0xF8 | encode));
8889 emit_int8(imm8);
8890 }
8891 }
8892
8893 void Assembler::sarq(Register dst) {
8894 int encode = prefixq_and_encode(dst->encoding());
8895 emit_int8((unsigned char)0xD3);
8896 emit_int8((unsigned char)(0xF8 | encode));
8897 }
8898
8899 void Assembler::sbbq(Address dst, int32_t imm32) {
8900 InstructionMark im(this);
8901 prefixq(dst);
8902 emit_arith_operand(0x81, rbx, dst, imm32);
8903 }
8904
8905 void Assembler::sbbq(Register dst, int32_t imm32) {
8906 (void) prefixq_and_encode(dst->encoding());
8907 emit_arith(0x81, 0xD8, dst, imm32);
8908 }
8909
8910 void Assembler::sbbq(Register dst, Address src) {
8911 InstructionMark im(this);
8912 prefixq(src, dst);
8913 emit_int8(0x1B);
8914 emit_operand(dst, src);
8915 }
8916
8917 void Assembler::sbbq(Register dst, Register src) {
8918 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8919 emit_arith(0x1B, 0xC0, dst, src);
8920 }
8921
8922 void Assembler::shlq(Register dst, int imm8) {
8923 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8924 int encode = prefixq_and_encode(dst->encoding());
8925 if (imm8 == 1) {
8926 emit_int8((unsigned char)0xD1);
8927 emit_int8((unsigned char)(0xE0 | encode));
8928 } else {
8929 emit_int8((unsigned char)0xC1);
8930 emit_int8((unsigned char)(0xE0 | encode));
8931 emit_int8(imm8);
8932 }
8933 }
8934
8935 void Assembler::shlq(Register dst) {
8936 int encode = prefixq_and_encode(dst->encoding());
8937 emit_int8((unsigned char)0xD3);
8938 emit_int8((unsigned char)(0xE0 | encode));
8939 }
8940
8941 void Assembler::shrq(Register dst, int imm8) {
8942 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8943 int encode = prefixq_and_encode(dst->encoding());
8944 emit_int8((unsigned char)0xC1);
8945 emit_int8((unsigned char)(0xE8 | encode));
8946 emit_int8(imm8);
8947 }
8948
8949 void Assembler::shrq(Register dst) {
8950 int encode = prefixq_and_encode(dst->encoding());
8951 emit_int8((unsigned char)0xD3);
8952 emit_int8(0xE8 | encode);
8953 }
8954
8955 void Assembler::subq(Address dst, int32_t imm32) {
8956 InstructionMark im(this);
8957 prefixq(dst);
8958 emit_arith_operand(0x81, rbp, dst, imm32);
8959 }
8960
8961 void Assembler::subq(Address dst, Register src) {
8962 InstructionMark im(this);
8963 prefixq(dst, src);
8964 emit_int8(0x29);
8965 emit_operand(src, dst);
8966 }
8967
8968 void Assembler::subq(Register dst, int32_t imm32) {
8969 (void) prefixq_and_encode(dst->encoding());
8970 emit_arith(0x81, 0xE8, dst, imm32);
8971 }
8972
8973 // Force generation of a 4 byte immediate value even if it fits into 8bit
8974 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8975 (void) prefixq_and_encode(dst->encoding());
8976 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8977 }
8978
8979 void Assembler::subq(Register dst, Address src) {
8980 InstructionMark im(this);
8981 prefixq(src, dst);
8982 emit_int8(0x2B);
8983 emit_operand(dst, src);
8984 }
8985
8986 void Assembler::subq(Register dst, Register src) {
8987 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8988 emit_arith(0x2B, 0xC0, dst, src);
8989 }
8990
8991 void Assembler::testq(Register dst, int32_t imm32) {
8992 // not using emit_arith because test
8993 // doesn't support sign-extension of
8994 // 8bit operands
8995 int encode = dst->encoding();
8996 if (encode == 0) {
8997 prefix(REX_W);
8998 emit_int8((unsigned char)0xA9);
8999 } else {
9000 encode = prefixq_and_encode(encode);
9001 emit_int8((unsigned char)0xF7);
9002 emit_int8((unsigned char)(0xC0 | encode));
9003 }
9004 emit_int32(imm32);
9005 }
9006
9007 void Assembler::testq(Register dst, Register src) {
9008 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9009 emit_arith(0x85, 0xC0, dst, src);
9010 }
9011
9012 void Assembler::testq(Register dst, Address src) {
9013 InstructionMark im(this);
9014 prefixq(src, dst);
9015 emit_int8((unsigned char)0x85);
9016 emit_operand(dst, src);
9017 }
9018
9019 void Assembler::xaddq(Address dst, Register src) {
9020 InstructionMark im(this);
9021 prefixq(dst, src);
9022 emit_int8(0x0F);
9023 emit_int8((unsigned char)0xC1);
9024 emit_operand(src, dst);
9025 }
9026
9027 void Assembler::xchgq(Register dst, Address src) {
9028 InstructionMark im(this);
9029 prefixq(src, dst);
9030 emit_int8((unsigned char)0x87);
9031 emit_operand(dst, src);
9032 }
9033
9034 void Assembler::xchgq(Register dst, Register src) {
9035 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9036 emit_int8((unsigned char)0x87);
9037 emit_int8((unsigned char)(0xc0 | encode));
9038 }
9039
9040 void Assembler::xorq(Register dst, Register src) {
9041 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9042 emit_arith(0x33, 0xC0, dst, src);
9043 }
9044
9045 void Assembler::xorq(Register dst, Address src) {
9046 InstructionMark im(this);
9047 prefixq(src, dst);
9048 emit_int8(0x33);
9049 emit_operand(dst, src);
9050 }
9051
9052 #endif // !LP64