# HG changeset patch
# Parent 1f6b36ea7a7e919f685ea934484d3ad860c52f41
# Parent  4339678a51da2c129cdad1cf352a8a604f2f6a0b
Streamline+cleanup ShenandoahBarrierSetC1 and related code

diff -r 1f6b36ea7a7e src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp
--- a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -710,8 +710,9 @@
   LIR_Opr ill = LIR_OprFact::illegalOpr;  // for convenience
   new_value.load_item();
   cmp_value.load_item();
+  LIR_Opr result = new_register(T_INT);
   if (type == T_OBJECT || type == T_ARRAY) {
-    __ cas_obj(addr, cmp_value.result(), new_value.result(), new_register(T_INT), new_register(T_INT));
+    __ cas_obj(addr, cmp_value.result(), new_value.result(), new_register(T_INT), new_register(T_INT), result);
   } else if (type == T_INT) {
     __ cas_int(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill);
   } else if (type == T_LONG) {
@@ -720,9 +721,7 @@
     ShouldNotReachHere();
     Unimplemented();
   }
-  LIR_Opr result = new_register(T_INT);
-  __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
-           result, type);
+  __ logical_xor(FrameMap::r8_opr, LIR_OprFact::intConst(1), result);
   return result;
 }
 
diff -r 1f6b36ea7a7e src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetC1_aarch64.cpp
--- a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetC1_aarch64.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetC1_aarch64.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -45,22 +45,54 @@
 
 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
   BasicType bt = access.type();
-  if (bt == T_OBJECT || bt == T_ARRAY) {
+  if (access.is_oop()) {
     LIRGenerator *gen = access.gen();
-    cmp_value.load_item();
-    new_value.load_item();
+    if (ShenandoahSATBBarrier) {
+      pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
+                  LIR_OprFact::illegalOpr /* pre_val */);
+    }
+    if (ShenandoahCASBarrier) {
+      cmp_value.load_item();
+      new_value.load_item();
 
-    LIR_Opr t1 = gen->new_register(T_OBJECT);
-    LIR_Opr t2 = gen->new_register(T_OBJECT);
-    LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
+      LIR_Opr t1 = gen->new_register(T_OBJECT);
+      LIR_Opr t2 = gen->new_register(T_OBJECT);
+      LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
 
-    __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, LIR_OprFact::illegalOpr));
+      __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2,
+                                                   LIR_OprFact::illegalOpr));
 
-    LIR_Opr result = gen->new_register(T_INT);
-    __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
-             result, T_INT);
-    return result;
-  } else {
-    return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
+      LIR_Opr result = gen->new_register(T_INT);
+      __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
+               result, T_INT);
+      return result;
+    }
   }
+  return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
 }
+
+LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
+  LIRGenerator* gen = access.gen();
+  BasicType type = access.type();
+
+  LIR_Opr result = gen->new_register(type);
+  value.load_item();
+  LIR_Opr value_opr = value.result();
+
+  if (access.is_oop()) {
+    value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
+  }
+
+  assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");
+  LIR_Opr tmp = gen->new_register(T_INT);
+  __ xchg(access.resolved_addr(), value_opr, result, tmp);
+
+  if (access.is_oop()) {
+    if (ShenandoahSATBBarrier) {
+      pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
+                  result /* pre_val */);
+    }
+  }
+
+  return result;
+}
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
--- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -3982,8 +3982,17 @@
   } else if (data->is_oop()) {
     assert (code == lir_xchg, "xadd for oops");
     Register obj = data->as_register();
-    assert (tmp->is_register(), "should be register");
-    __ xchg_oop(obj, as_Address(src->as_address_ptr()), tmp->as_register());
+#ifdef _LP64
+    if (UseCompressedOops) {
+      __ encode_heap_oop(obj);
+      __ xchgl(obj, as_Address(src->as_address_ptr()));
+      __ decode_heap_oop(obj);
+    } else {
+      __ xchgptr(obj, as_Address(src->as_address_ptr()));
+    }
+#else
+    __ xchgl(obj, as_Address(src->as_address_ptr()));
+#endif
   } else if (data->type() == T_LONG) {
 #ifdef _LP64
     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp
--- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -685,8 +685,7 @@
   // Because we want a 2-arg form of xchg and xadd
   __ move(value.result(), result);
   assert(type == T_INT || is_oop LP64_ONLY( || type == T_LONG ), "unexpected type");
-  LIR_Opr tmp = is_oop ? new_register(type) : LIR_OprFact::illegalOpr;
-  __ xchg(addr, result, result, tmp);
+  __ xchg(addr, result, result, LIR_OprFact::illegalOpr);
   return result;
 }
 
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp
--- a/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -322,18 +322,3 @@
   __ adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
 #endif
 }
-
-void BarrierSetAssembler::xchg_oop(MacroAssembler* masm, DecoratorSet decorators,
-                                   Register obj, Address addr, Register tmp) {
-#ifdef _LP64
-    if (UseCompressedOops) {
-      __ encode_heap_oop(obj);
-      __ xchgl(obj, addr);
-      __ decode_heap_oop(obj);
-    } else {
-      __ xchgptr(obj, addr);
-    }
-#else
-    __ xchgl(obj, addr);
-#endif
-}
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp
--- a/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp	Thu Sep 27 06:25:32 2018 -0400
@@ -82,9 +82,6 @@
                              Register t1,
                              Label& slow_case);
 
-  virtual void xchg_oop(MacroAssembler* masm, DecoratorSet decorators,
-                        Register obj, Address addr, Register tmp);
-
   virtual void barrier_stubs_init() {}
 };
 
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
--- a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -732,12 +732,6 @@
 }
 #endif // LP64
 
-void ShenandoahBarrierSetAssembler::xchg_oop(MacroAssembler* masm, DecoratorSet decorators,
-                                             Register obj, Address addr, Register tmp) {
-  storeval_barrier(masm, obj, tmp);
-  BarrierSetAssembler::xchg_oop(masm, decorators, obj, addr, tmp);
-}
-
 #ifdef COMPILER1
 
 #undef __
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp
--- a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp	Thu Sep 27 06:25:32 2018 -0400
@@ -85,9 +85,6 @@
   void cmpxchg_oop(MacroAssembler* masm,
                    Register res, Address addr, Register oldval, Register newval,
                    bool exchange, bool encode, Register tmp1, Register tmp2);
-  virtual void xchg_oop(MacroAssembler* masm, DecoratorSet decorators,
-                        Register obj, Address addr, Register tmp);
-
   virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
                                   Register src, Register dst, Register count);
   virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetC1_x86.cpp
--- a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetC1_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetC1_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -49,23 +49,56 @@
 #endif
 
 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
-  BasicType bt = access.type();
-  if (ShenandoahCASBarrier && (bt == T_OBJECT || bt == T_ARRAY)) {
-    LIRGenerator *gen = access.gen();
-    cmp_value.load_item_force(FrameMap::rax_oop_opr);
-    new_value.load_item();
 
-    LIR_Opr t1 = gen->new_register(T_OBJECT);
-    LIR_Opr t2 = gen->new_register(T_OBJECT);
-    LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
+  if (access.is_oop()) {
+    LIRGenerator* gen = access.gen();
+    if (ShenandoahSATBBarrier) {
+      pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
+                  LIR_OprFact::illegalOpr /* pre_val */);
+    }
+    if (ShenandoahCASBarrier) {
+      cmp_value.load_item_force(FrameMap::rax_oop_opr);
+      new_value.load_item();
 
-    __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, LIR_OprFact::illegalOpr));
+      LIR_Opr t1 = gen->new_register(T_OBJECT);
+      LIR_Opr t2 = gen->new_register(T_OBJECT);
+      LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
 
-    LIR_Opr result = gen->new_register(T_INT);
-    __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
-             result, T_INT);
-    return result;
-  } else {
-    return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
+      __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, LIR_OprFact::illegalOpr));
+
+      LIR_Opr result = gen->new_register(T_INT);
+      __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
+               result, T_INT);
+      return result;
+    }
   }
+  return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
 }
+
+LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
+  LIRGenerator* gen = access.gen();
+  BasicType type = access.type();
+
+  LIR_Opr result = gen->new_register(type);
+  value.load_item();
+  LIR_Opr value_opr = value.result();
+
+  if (access.is_oop()) {
+    value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
+  }
+
+  // Because we want a 2-arg form of xchg and xadd
+  __ move(value_opr, result);
+
+  assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");
+  __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr);
+
+  if (access.is_oop()) {
+    if (ShenandoahSATBBarrier) {
+      pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
+                  result /* pre_val */);
+    }
+  }
+
+  return result;
+}
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/macroAssembler_x86.cpp
--- a/src/hotspot/cpu/x86/macroAssembler_x86.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/macroAssembler_x86.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -3583,11 +3583,6 @@
   movl(as_Address(ArrayAddress(page, index)), tmp);
 }
 
-void MacroAssembler::xchg_oop(Register obj, Address addr, Register tmp) {
-  BarrierSetAssembler* bsa = BarrierSet::barrier_set()->barrier_set_assembler();
-  bsa->xchg_oop(this, IN_HEAP, obj, addr, tmp);
-}
-
 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
   if (SafepointMechanism::uses_thread_local_poll()) {
 #ifdef _LP64
diff -r 1f6b36ea7a7e src/hotspot/cpu/x86/macroAssembler_x86.hpp
--- a/src/hotspot/cpu/x86/macroAssembler_x86.hpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/cpu/x86/macroAssembler_x86.hpp	Thu Sep 27 06:25:32 2018 -0400
@@ -772,8 +772,6 @@
 
   void cmpxchgptr(Register reg, Address adr);
 
-  void xchg_oop(Register obj, Address addr, Register tmp);
-
   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 
 
diff -r 1f6b36ea7a7e src/hotspot/share/gc/shared/c1/barrierSetC1.cpp
--- a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -43,26 +43,21 @@
   bool is_array = (decorators & IS_ARRAY) != 0;
   bool needs_patching = (decorators & C1_NEEDS_PATCHING) != 0;
 
-  LIR_Opr base;
-  if (access.base().opr() != NULL) {
-    base = access.base().opr();
-  } else {
-    base = access.base().item().result();
-  }
+  LIRItem& base = access.base().item();
   LIR_Opr offset = access.offset().opr();
   LIRGenerator *gen = access.gen();
 
   LIR_Opr addr_opr;
   if (is_array) {
-    addr_opr = LIR_OprFact::address(gen->emit_array_address(base, offset, access.type()));
+    addr_opr = LIR_OprFact::address(gen->emit_array_address(base.result(), offset, access.type()));
   } else if (needs_patching) {
     // we need to patch the offset in the instruction so don't allow
     // generate_address to try to be smart about emitting the -1.
     // Otherwise the patching code won't know how to find the
     // instruction to patch.
-    addr_opr = LIR_OprFact::address(new LIR_Address(base, PATCHED_ADDR, access.type()));
+    addr_opr = LIR_OprFact::address(new LIR_Address(base.result(), PATCHED_ADDR, access.type()));
   } else {
-    addr_opr = LIR_OprFact::address(gen->generate_address(base, offset, 0, 0, access.type()));
+    addr_opr = LIR_OprFact::address(gen->generate_address(base.result(), offset, 0, 0, access.type()));
   }
 
   if (resolve_in_register) {
diff -r 1f6b36ea7a7e src/hotspot/share/gc/shared/c1/barrierSetC1.hpp
--- a/src/hotspot/share/gc/shared/c1/barrierSetC1.hpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.hpp	Thu Sep 27 06:25:32 2018 -0400
@@ -96,7 +96,6 @@
   CodeEmitInfo*& patch_emit_info()     { return _patch_emit_info; }
   CodeEmitInfo*& access_emit_info()    { return _access_emit_info; }
   LIRAddressOpr& base()                { return _base; }
-  void set_base(LIRAddressOpr base)    { _base = base; }
   LIRAddressOpr& offset()              { return _offset; }
   BasicType type() const               { return _type; }
   LIR_Opr resolved_addr() const        { return _resolved_addr; }
@@ -104,7 +103,6 @@
   bool is_oop() const                  { return _type == T_ARRAY || _type == T_OBJECT; }
   DecoratorSet decorators() const      { return _decorators; }
   bool is_raw() const                  { return (_decorators & AS_RAW) != 0; }
-  bool needs_null_check() const        { return (_decorators & IS_NOT_NULL) == 0; }
 };
 
 // The BarrierSetC1 class is the main entry point for the GC backend of the Access API in C1.
diff -r 1f6b36ea7a7e src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp
--- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp	Thu Sep 27 06:25:32 2018 -0400
@@ -31,6 +31,10 @@
 #include "gc/shenandoah/shenandoahThreadLocalData.hpp"
 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
 
+#ifndef PATCHED_ADDR
+#define PATCHED_ADDR  (max_jint)
+#endif
+
 #ifdef ASSERT
 #define __ gen->lir(__FILE__, __LINE__)->
 #else
@@ -197,10 +201,49 @@
   return obj;
 }
 
-void ShenandoahBarrierSetC1::store_at(LIRAccess& access, LIR_Opr value) {
-  access.set_base(write_barrier(access.gen(), access.base().item().result(), access.access_emit_info(), access.needs_null_check()));
-  LIR_Opr resolved = resolve_address(access, false);
-  access.set_resolved_addr(resolved);
+LIR_Opr ShenandoahBarrierSetC1::resolve_address(LIRAccess& access, bool resolve_in_register) {
+  DecoratorSet decorators = access.decorators();
+  bool is_array = (decorators & IS_ARRAY) != 0;
+  bool needs_patching = (decorators & C1_NEEDS_PATCHING) != 0;
+
+  bool is_write = (decorators & ACCESS_WRITE) != 0;
+  bool needs_null_check = (decorators & IS_NOT_NULL) == 0;
+
+  LIR_Opr base = access.base().item().result();
+  LIR_Opr offset = access.offset().opr();
+  LIRGenerator* gen = access.gen();
+
+  if (is_write) {
+    base = write_barrier(gen, base, access.access_emit_info(), needs_null_check);
+  } else {
+    base = read_barrier(gen, base, access.access_emit_info(), needs_null_check);
+  }
+
+  LIR_Opr addr_opr;
+  if (is_array) {
+    addr_opr = LIR_OprFact::address(gen->emit_array_address(base, offset, access.type()));
+  } else if (needs_patching) {
+    // we need to patch the offset in the instruction so don't allow
+    // generate_address to try to be smart about emitting the -1.
+    // Otherwise the patching code won't know how to find the
+    // instruction to patch.
+    addr_opr = LIR_OprFact::address(new LIR_Address(base, PATCHED_ADDR, access.type()));
+  } else {
+    addr_opr = LIR_OprFact::address(gen->generate_address(base, offset, 0, 0, access.type()));
+  }
+
+  if (resolve_in_register) {
+    LIR_Opr resolved_addr = gen->new_pointer_register();
+    __ leal(addr_opr, resolved_addr);
+    resolved_addr = LIR_OprFact::address(new LIR_Address(resolved_addr, access.type()));
+    return resolved_addr;
+  } else {
+    return addr_opr;
+  }
+}
+
+
+void ShenandoahBarrierSetC1::store_at_resolved(LIRAccess& access, LIR_Opr value) {
   if (access.is_oop()) {
     if (ShenandoahSATBBarrier) {
       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), access.resolved_addr(), LIR_OprFact::illegalOpr /* pre_val */);
@@ -210,13 +253,8 @@
   BarrierSetC1::store_at_resolved(access, value);
 }
 
-void ShenandoahBarrierSetC1::load_at(LIRAccess& access, LIR_Opr result) {
-  LIRItem& base_item = access.base().item();
-  access.set_base(read_barrier(access.gen(), access.base().item().result(), access.access_emit_info(), access.needs_null_check()));
-  LIR_Opr resolved = resolve_address(access, false);
-  access.set_resolved_addr(resolved);
+void ShenandoahBarrierSetC1::load_at_resolved(LIRAccess& access, LIR_Opr result) {
   BarrierSetC1::load_at_resolved(access, result);
-  access.set_base(base_item);
 
   if (ShenandoahKeepAliveBarrier) {
     DecoratorSet decorators = access.decorators();
@@ -240,38 +278,7 @@
   }
 }
 
-LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
-  access.load_address();
-  access.set_base(write_barrier(access.gen(), access.base().item().result(), access.access_emit_info(), access.needs_null_check()));
-  LIR_Opr resolved = resolve_address(access, true);
-  access.set_resolved_addr(resolved);
-  if (access.is_oop()) {
-    if (ShenandoahSATBBarrier) {
-      pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), access.resolved_addr(),
-                  LIR_OprFact::illegalOpr /* pre_val */);
-    }
-  }
-  return atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
-}
-
-LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at(LIRAccess& access, LIRItem& value) {
-  access.set_base(write_barrier(access.gen(), access.base().item().result(), access.access_emit_info(), access.needs_null_check()));
-  LIR_Opr resolved = resolve_address(access, true);
-  access.set_resolved_addr(resolved);
-  if (access.is_oop()) {
-    if (ShenandoahSATBBarrier) {
-      pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), access.resolved_addr(),
-                  LIR_OprFact::illegalOpr /* pre_val */);
-    }
-  }
-  return BarrierSetC1::atomic_xchg_at_resolved(access, value);
-}
-
-LIR_Opr ShenandoahBarrierSetC1::atomic_add_at(LIRAccess& access, LIRItem& value) {
-  access.load_address();
-  access.set_base(write_barrier(access.gen(), access.base().item().result(), access.access_emit_info(), access.needs_null_check()));
-  LIR_Opr resolved = resolve_address(access, true);
-  access.set_resolved_addr(resolved);
+LIR_Opr ShenandoahBarrierSetC1::atomic_add_at_resolved(LIRAccess& access, LIRItem& value) {
   return BarrierSetC1::atomic_add_at_resolved(access, value);
 }
 
diff -r 1f6b36ea7a7e src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.hpp
--- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.hpp	Wed Sep 26 14:11:36 2018 -0400
+++ b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.hpp	Thu Sep 27 06:25:32 2018 -0400
@@ -191,19 +191,21 @@
 
   LIR_Opr ensure_in_register(LIRGenerator* gen, LIR_Opr obj);
 
-  virtual LIR_Opr atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value);
-
 public:
   CodeBlob* pre_barrier_c1_runtime_code_blob() { return _pre_barrier_c1_runtime_code_blob; }
 
-  virtual void store_at(LIRAccess& access, LIR_Opr value);
-  virtual void load_at(LIRAccess& access, LIR_Opr result);
+protected:
+  virtual LIR_Opr resolve_address(LIRAccess& access, bool resolve_in_register);
 
-  virtual LIR_Opr atomic_cmpxchg_at(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value);
+  virtual void store_at_resolved(LIRAccess& access, LIR_Opr value);
+  virtual void load_at_resolved(LIRAccess& access, LIR_Opr result);
 
-  virtual LIR_Opr atomic_xchg_at(LIRAccess& access, LIRItem& value);
-  virtual LIR_Opr atomic_add_at(LIRAccess& access, LIRItem& value);
+  virtual LIR_Opr atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value);
 
+  virtual LIR_Opr atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value);
+  virtual LIR_Opr atomic_add_at_resolved(LIRAccess& access, LIRItem& value);
+
+public:
   virtual LIR_Opr resolve(LIRGenerator* gen, DecoratorSet decorators, LIR_Opr obj);
 
   virtual void generate_c1_runtime_stubs(BufferBlob* buffer_blob);