1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71
72 NEEDS_CLEANUP // remove this definitions ?
73 const Register IC_Klass = rax; // where the IC klass is cached
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == NULL) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == NULL) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164
165 void LIR_Assembler::set_24bit_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
167 }
168
169 void LIR_Assembler::reset_FPU() {
170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
171 }
172
173 void LIR_Assembler::fpop() {
174 __ fpop();
175 }
176
177 void LIR_Assembler::fxch(int i) {
178 __ fxch(i);
179 }
180
181 void LIR_Assembler::fld(int i) {
182 __ fld_s(i);
183 }
184
185 void LIR_Assembler::ffree(int i) {
186 __ ffree(i);
187 }
188
189 void LIR_Assembler::breakpoint() {
190 __ int3();
191 }
192
193 void LIR_Assembler::push(LIR_Opr opr) {
194 if (opr->is_single_cpu()) {
195 __ push_reg(opr->as_register());
196 } else if (opr->is_double_cpu()) {
197 NOT_LP64(__ push_reg(opr->as_register_hi()));
198 __ push_reg(opr->as_register_lo());
199 } else if (opr->is_stack()) {
200 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
201 } else if (opr->is_constant()) {
202 LIR_Const* const_opr = opr->as_constant_ptr();
203 if (const_opr->type() == T_OBJECT) {
204 __ push_oop(const_opr->as_jobject());
205 } else if (const_opr->type() == T_INT) {
206 __ push_jint(const_opr->as_jint());
207 } else {
208 ShouldNotReachHere();
209 }
210
211 } else {
212 ShouldNotReachHere();
213 }
214 }
215
216 void LIR_Assembler::pop(LIR_Opr opr) {
217 if (opr->is_single_cpu()) {
218 __ pop_reg(opr->as_register());
219 } else {
220 ShouldNotReachHere();
221 }
222 }
223
224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
225 return addr->base()->is_illegal() && addr->index()->is_illegal();
226 }
227
228 //-------------------------------------------
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr) {
231 return as_Address(addr, rscratch1);
232 }
233
234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
235 if (addr->base()->is_illegal()) {
236 assert(addr->index()->is_illegal(), "must be illegal too");
237 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
238 if (! __ reachable(laddr)) {
239 __ movptr(tmp, laddr.addr());
240 Address res(tmp, 0);
241 return res;
242 } else {
243 return __ as_Address(laddr);
244 }
245 }
246
247 Register base = addr->base()->as_pointer_register();
248
249 if (addr->index()->is_illegal()) {
250 return Address( base, addr->disp());
251 } else if (addr->index()->is_cpu_register()) {
252 Register index = addr->index()->as_pointer_register();
253 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
254 } else if (addr->index()->is_constant()) {
255 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
256 assert(Assembler::is_simm32(addr_offset), "must be");
257
258 return Address(base, addr_offset);
259 } else {
260 Unimplemented();
261 return Address();
262 }
263 }
264
265
266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
267 Address base = as_Address(addr);
268 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
269 }
270
271
272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
273 return as_Address(addr);
274 }
275
276
277 void LIR_Assembler::osr_entry() {
278 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
279 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
280 ValueStack* entry_state = osr_entry->state();
281 int number_of_locks = entry_state->locks_size();
282
283 // we jump here if osr happens with the interpreter
284 // state set up to continue at the beginning of the
285 // loop that triggered osr - in particular, we have
286 // the following registers setup:
287 //
288 // rcx: osr buffer
289 //
290
291 // build frame
292 ciMethod* m = compilation()->method();
293 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
294
295 // OSR buffer is
296 //
297 // locals[nlocals-1..0]
298 // monitors[0..number_of_locks]
299 //
300 // locals is a direct copy of the interpreter frame so in the osr buffer
301 // so first slot in the local array is the last local from the interpreter
302 // and last slot is local[0] (receiver) from the interpreter
303 //
304 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
305 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
306 // in the interpreter frame (the method lock if a sync method)
307
308 // Initialize monitors in the compiled activation.
309 // rcx: pointer to osr buffer
310 //
311 // All other registers are dead at this point and the locals will be
312 // copied into place by code emitted in the IR.
313
314 Register OSR_buf = osrBufferPointer()->as_pointer_register();
315 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
316 int monitor_offset = BytesPerWord * method()->max_locals() +
317 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
318 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
319 // the OSR buffer using 2 word entries: first the lock and then
320 // the oop.
321 for (int i = 0; i < number_of_locks; i++) {
322 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
323 #ifdef ASSERT
324 // verify the interpreter's monitor has a non-null object
325 {
326 Label L;
327 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
328 __ jcc(Assembler::notZero, L);
329 __ stop("locked object is NULL");
330 __ bind(L);
331 }
332 #endif
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
334 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
335 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
336 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
337 }
338 }
339 }
340
341
342 // inline cache check; done before the frame is built.
343 int LIR_Assembler::check_icache() {
344 Register receiver = FrameMap::receiver_opr->as_register();
345 Register ic_klass = IC_Klass;
346 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
347 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
348 if (!do_post_padding) {
349 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
350 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
351 }
352 int offset = __ offset();
353 __ inline_cache_check(receiver, IC_Klass);
354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
355 if (do_post_padding) {
356 // force alignment after the cache check.
357 // It's been verified to be aligned if !VerifyOops
358 __ align(CodeEntryAlignment);
359 }
360 return offset;
361 }
362
363
364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 jobject o = NULL;
366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
367 __ movoop(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
372 Metadata* o = NULL;
373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
374 __ mov_metadata(reg, o);
375 patching_epilog(patch, lir_patch_normal, reg, info);
376 }
377
378 // This specifies the rsp decrement needed to build the frame
379 int LIR_Assembler::initial_frame_size_in_bytes() const {
380 // if rounding, must let FrameMap know!
381
382 // The frame_map records size in slots (32bit word)
383
384 // subtract two words to account for return address and link
385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
386 }
387
388
389 int LIR_Assembler::emit_exception_handler() {
390 // if the last instruction is a call (typically to do a throw which
391 // is coming at the end after block reordering) the return address
392 // must still point into the code area in order to avoid assertion
393 // failures when searching for the corresponding bci => add a nop
394 // (was bug 5/14/1999 - gri)
395 __ nop();
396
397 // generate code for exception handler
398 address handler_base = __ start_a_stub(exception_handler_size());
399 if (handler_base == NULL) {
400 // not enough space left for the handler
401 bailout("exception handler overflow");
402 return -1;
403 }
404
405 int offset = code_offset();
406
407 // the exception oop and pc are in rax, and rdx
408 // no other registers need to be preserved, so invalidate them
409 __ invalidate_registers(false, true, true, false, true, true);
410
411 // check that there is really an exception
412 __ verify_not_null_oop(rax);
413
414 // search an exception handler (rax: exception oop, rdx: throwing pc)
415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
416 __ should_not_reach_here();
417 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
418 __ end_a_stub();
419
420 return offset;
421 }
422
423
424 // Emit the code to remove the frame from the stack in the exception
425 // unwind path.
426 int LIR_Assembler::emit_unwind_handler() {
427 #ifndef PRODUCT
428 if (CommentedAssembly) {
429 _masm->block_comment("Unwind handler");
430 }
431 #endif
432
433 int offset = code_offset();
434
435 // Fetch the exception from TLS and clear out exception related thread state
436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
437 NOT_LP64(__ get_thread(rsi));
438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
441
442 __ bind(_unwind_handler_entry);
443 __ verify_not_null_oop(rax);
444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
446 }
447
448 // Preform needed unlocking
449 MonitorExitStub* stub = NULL;
450 if (method()->is_synchronized()) {
451 monitor_address(0, FrameMap::rax_opr);
452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
453 __ unlock_object(rdi, rsi, rax, *stub->entry());
454 __ bind(*stub->continuation());
455 }
456
457 if (compilation()->env()->dtrace_method_probes()) {
458 #ifdef _LP64
459 __ mov(rdi, r15_thread);
460 __ mov_metadata(rsi, method()->constant_encoding());
461 #else
462 __ get_thread(rax);
463 __ movptr(Address(rsp, 0), rax);
464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
465 #endif
466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
467 }
468
469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
470 __ mov(rax, rbx); // Restore the exception
471 }
472
473 // remove the activation and dispatch to the unwind handler
474 __ remove_frame(initial_frame_size_in_bytes());
475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
476
477 // Emit the slow path assembly
478 if (stub != NULL) {
479 stub->emit_code(this);
480 }
481
482 return offset;
483 }
484
485
486 int LIR_Assembler::emit_deopt_handler() {
487 // if the last instruction is a call (typically to do a throw which
488 // is coming at the end after block reordering) the return address
489 // must still point into the code area in order to avoid assertion
490 // failures when searching for the corresponding bci => add a nop
491 // (was bug 5/14/1999 - gri)
492 __ nop();
493
494 // generate code for exception handler
495 address handler_base = __ start_a_stub(deopt_handler_size());
496 if (handler_base == NULL) {
497 // not enough space left for the handler
498 bailout("deopt handler overflow");
499 return -1;
500 }
501
502 int offset = code_offset();
503 InternalAddress here(__ pc());
504
505 __ pushptr(here.addr());
506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
507 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
508 __ end_a_stub();
509
510 return offset;
511 }
512
513
514 void LIR_Assembler::return_op(LIR_Opr result) {
515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
517 assert(result->fpu() == 0, "result must already be on TOS");
518 }
519
520 // Pop the stack before the safepoint code
521 __ remove_frame(initial_frame_size_in_bytes());
522
523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
524 __ reserved_stack_check();
525 }
526
527 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
528
529 // Note: we do not need to round double result; float result has the right precision
530 // the poll sets the condition code, but no data registers
531
532 if (SafepointMechanism::uses_thread_local_poll()) {
533 #ifdef _LP64
534 const Register poll_addr = rscratch1;
535 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
536 #else
537 const Register poll_addr = rbx;
538 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
539 __ get_thread(poll_addr);
540 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
541 #endif
542 __ relocate(relocInfo::poll_return_type);
543 __ testl(rax, Address(poll_addr, 0));
544 } else {
545 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
546
547 if (Assembler::is_polling_page_far()) {
548 __ lea(rscratch1, polling_page);
549 __ relocate(relocInfo::poll_return_type);
550 __ testl(rax, Address(rscratch1, 0));
551 } else {
552 __ testl(rax, polling_page);
553 }
554 }
555 __ ret(0);
556 }
557
558
559 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
560 guarantee(info != NULL, "Shouldn't be NULL");
561 int offset = __ offset();
562 if (SafepointMechanism::uses_thread_local_poll()) {
563 #ifdef _LP64
564 const Register poll_addr = rscratch1;
565 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
566 #else
567 assert(tmp->is_cpu_register(), "needed");
568 const Register poll_addr = tmp->as_register();
569 __ get_thread(poll_addr);
570 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
571 #endif
572 add_debug_info_for_branch(info);
573 __ relocate(relocInfo::poll_type);
574 address pre_pc = __ pc();
575 __ testl(rax, Address(poll_addr, 0));
576 address post_pc = __ pc();
577 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
578 } else {
579 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
580 if (Assembler::is_polling_page_far()) {
581 __ lea(rscratch1, polling_page);
582 offset = __ offset();
583 add_debug_info_for_branch(info);
584 __ relocate(relocInfo::poll_type);
585 __ testl(rax, Address(rscratch1, 0));
586 } else {
587 add_debug_info_for_branch(info);
588 __ testl(rax, polling_page);
589 }
590 }
591 return offset;
592 }
593
594
595 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
596 if (from_reg != to_reg) __ mov(to_reg, from_reg);
597 }
598
599 void LIR_Assembler::swap_reg(Register a, Register b) {
600 __ xchgptr(a, b);
601 }
602
603
604 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
605 assert(src->is_constant(), "should not call otherwise");
606 assert(dest->is_register(), "should not call otherwise");
607 LIR_Const* c = src->as_constant_ptr();
608
609 switch (c->type()) {
610 case T_INT: {
611 assert(patch_code == lir_patch_none, "no patching handled here");
612 __ movl(dest->as_register(), c->as_jint());
613 break;
614 }
615
616 case T_ADDRESS: {
617 assert(patch_code == lir_patch_none, "no patching handled here");
618 __ movptr(dest->as_register(), c->as_jint());
619 break;
620 }
621
622 case T_LONG: {
623 assert(patch_code == lir_patch_none, "no patching handled here");
624 #ifdef _LP64
625 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
626 #else
627 __ movptr(dest->as_register_lo(), c->as_jint_lo());
628 __ movptr(dest->as_register_hi(), c->as_jint_hi());
629 #endif // _LP64
630 break;
631 }
632
633 case T_OBJECT: {
634 if (patch_code != lir_patch_none) {
635 jobject2reg_with_patching(dest->as_register(), info);
636 } else {
637 __ movoop(dest->as_register(), c->as_jobject());
638 }
639 break;
640 }
641
642 case T_METADATA: {
643 if (patch_code != lir_patch_none) {
644 klass2reg_with_patching(dest->as_register(), info);
645 } else {
646 __ mov_metadata(dest->as_register(), c->as_metadata());
647 }
648 break;
649 }
650
651 case T_FLOAT: {
652 if (dest->is_single_xmm()) {
653 if (c->is_zero_float()) {
654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
655 } else {
656 __ movflt(dest->as_xmm_float_reg(),
657 InternalAddress(float_constant(c->as_jfloat())));
658 }
659 } else {
660 assert(dest->is_single_fpu(), "must be");
661 assert(dest->fpu_regnr() == 0, "dest must be TOS");
662 if (c->is_zero_float()) {
663 __ fldz();
664 } else if (c->is_one_float()) {
665 __ fld1();
666 } else {
667 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
668 }
669 }
670 break;
671 }
672
673 case T_DOUBLE: {
674 if (dest->is_double_xmm()) {
675 if (c->is_zero_double()) {
676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
677 } else {
678 __ movdbl(dest->as_xmm_double_reg(),
679 InternalAddress(double_constant(c->as_jdouble())));
680 }
681 } else {
682 assert(dest->is_double_fpu(), "must be");
683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
684 if (c->is_zero_double()) {
685 __ fldz();
686 } else if (c->is_one_double()) {
687 __ fld1();
688 } else {
689 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
690 }
691 }
692 break;
693 }
694
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
701 assert(src->is_constant(), "should not call otherwise");
702 assert(dest->is_stack(), "should not call otherwise");
703 LIR_Const* c = src->as_constant_ptr();
704
705 switch (c->type()) {
706 case T_INT: // fall through
707 case T_FLOAT:
708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
709 break;
710
711 case T_ADDRESS:
712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
713 break;
714
715 case T_OBJECT:
716 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
717 break;
718
719 case T_LONG: // fall through
720 case T_DOUBLE:
721 #ifdef _LP64
722 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
723 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
724 #else
725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
726 lo_word_offset_in_bytes), c->as_jint_lo_bits());
727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
728 hi_word_offset_in_bytes), c->as_jint_hi_bits());
729 #endif // _LP64
730 break;
731
732 default:
733 ShouldNotReachHere();
734 }
735 }
736
737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
738 assert(src->is_constant(), "should not call otherwise");
739 assert(dest->is_address(), "should not call otherwise");
740 LIR_Const* c = src->as_constant_ptr();
741 LIR_Address* addr = dest->as_address_ptr();
742
743 int null_check_here = code_offset();
744 switch (type) {
745 case T_INT: // fall through
746 case T_FLOAT:
747 __ movl(as_Address(addr), c->as_jint_bits());
748 break;
749
750 case T_ADDRESS:
751 __ movptr(as_Address(addr), c->as_jint_bits());
752 break;
753
754 case T_OBJECT: // fall through
755 case T_ARRAY:
756 if (c->as_jobject() == NULL) {
757 if (UseCompressedOops && !wide) {
758 __ movl(as_Address(addr), (int32_t)NULL_WORD);
759 } else {
760 #ifdef _LP64
761 __ xorptr(rscratch1, rscratch1);
762 null_check_here = code_offset();
763 __ movptr(as_Address(addr), rscratch1);
764 #else
765 __ movptr(as_Address(addr), NULL_WORD);
766 #endif
767 }
768 } else {
769 if (is_literal_address(addr)) {
770 ShouldNotReachHere();
771 __ movoop(as_Address(addr, noreg), c->as_jobject());
772 } else {
773 #ifdef _LP64
774 __ movoop(rscratch1, c->as_jobject());
775 if (UseCompressedOops && !wide) {
776 __ encode_heap_oop(rscratch1);
777 null_check_here = code_offset();
778 __ movl(as_Address_lo(addr), rscratch1);
779 } else {
780 null_check_here = code_offset();
781 __ movptr(as_Address_lo(addr), rscratch1);
782 }
783 #else
784 __ movoop(as_Address(addr), c->as_jobject());
785 #endif
786 }
787 }
788 break;
789
790 case T_LONG: // fall through
791 case T_DOUBLE:
792 #ifdef _LP64
793 if (is_literal_address(addr)) {
794 ShouldNotReachHere();
795 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
796 } else {
797 __ movptr(r10, (intptr_t)c->as_jlong_bits());
798 null_check_here = code_offset();
799 __ movptr(as_Address_lo(addr), r10);
800 }
801 #else
802 // Always reachable in 32bit so this doesn't produce useless move literal
803 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
804 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
805 #endif // _LP64
806 break;
807
808 case T_BOOLEAN: // fall through
809 case T_BYTE:
810 __ movb(as_Address(addr), c->as_jint() & 0xFF);
811 break;
812
813 case T_CHAR: // fall through
814 case T_SHORT:
815 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
816 break;
817
818 default:
819 ShouldNotReachHere();
820 };
821
822 if (info != NULL) {
823 add_debug_info_for_null_check(null_check_here, info);
824 }
825 }
826
827
828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
829 assert(src->is_register(), "should not call otherwise");
830 assert(dest->is_register(), "should not call otherwise");
831
832 // move between cpu-registers
833 if (dest->is_single_cpu()) {
834 #ifdef _LP64
835 if (src->type() == T_LONG) {
836 // Can do LONG -> OBJECT
837 move_regs(src->as_register_lo(), dest->as_register());
838 return;
839 }
840 #endif
841 assert(src->is_single_cpu(), "must match");
842 if (src->type() == T_OBJECT) {
843 __ verify_oop(src->as_register());
844 }
845 move_regs(src->as_register(), dest->as_register());
846
847 } else if (dest->is_double_cpu()) {
848 #ifdef _LP64
849 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
850 // Surprising to me but we can see move of a long to t_object
851 __ verify_oop(src->as_register());
852 move_regs(src->as_register(), dest->as_register_lo());
853 return;
854 }
855 #endif
856 assert(src->is_double_cpu(), "must match");
857 Register f_lo = src->as_register_lo();
858 Register f_hi = src->as_register_hi();
859 Register t_lo = dest->as_register_lo();
860 Register t_hi = dest->as_register_hi();
861 #ifdef _LP64
862 assert(f_hi == f_lo, "must be same");
863 assert(t_hi == t_lo, "must be same");
864 move_regs(f_lo, t_lo);
865 #else
866 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
867
868
869 if (f_lo == t_hi && f_hi == t_lo) {
870 swap_reg(f_lo, f_hi);
871 } else if (f_hi == t_lo) {
872 assert(f_lo != t_hi, "overwriting register");
873 move_regs(f_hi, t_hi);
874 move_regs(f_lo, t_lo);
875 } else {
876 assert(f_hi != t_lo, "overwriting register");
877 move_regs(f_lo, t_lo);
878 move_regs(f_hi, t_hi);
879 }
880 #endif // LP64
881
882 // special moves from fpu-register to xmm-register
883 // necessary for method results
884 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
885 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
886 __ fld_s(Address(rsp, 0));
887 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
888 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
889 __ fld_d(Address(rsp, 0));
890 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
891 __ fstp_s(Address(rsp, 0));
892 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
893 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
894 __ fstp_d(Address(rsp, 0));
895 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
896
897 // move between xmm-registers
898 } else if (dest->is_single_xmm()) {
899 assert(src->is_single_xmm(), "must match");
900 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
901 } else if (dest->is_double_xmm()) {
902 assert(src->is_double_xmm(), "must match");
903 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
904
905 // move between fpu-registers (no instruction necessary because of fpu-stack)
906 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
907 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
908 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
909 } else {
910 ShouldNotReachHere();
911 }
912 }
913
914 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
915 assert(src->is_register(), "should not call otherwise");
916 assert(dest->is_stack(), "should not call otherwise");
917
918 if (src->is_single_cpu()) {
919 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
920 if (type == T_OBJECT || type == T_ARRAY) {
921 __ verify_oop(src->as_register());
922 __ movptr (dst, src->as_register());
923 } else if (type == T_METADATA) {
924 __ movptr (dst, src->as_register());
925 } else {
926 __ movl (dst, src->as_register());
927 }
928
929 } else if (src->is_double_cpu()) {
930 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
931 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
932 __ movptr (dstLO, src->as_register_lo());
933 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
934
935 } else if (src->is_single_xmm()) {
936 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
937 __ movflt(dst_addr, src->as_xmm_float_reg());
938
939 } else if (src->is_double_xmm()) {
940 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
941 __ movdbl(dst_addr, src->as_xmm_double_reg());
942
943 } else if (src->is_single_fpu()) {
944 assert(src->fpu_regnr() == 0, "argument must be on TOS");
945 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
946 if (pop_fpu_stack) __ fstp_s (dst_addr);
947 else __ fst_s (dst_addr);
948
949 } else if (src->is_double_fpu()) {
950 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
951 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
952 if (pop_fpu_stack) __ fstp_d (dst_addr);
953 else __ fst_d (dst_addr);
954
955 } else {
956 ShouldNotReachHere();
957 }
958 }
959
960
961 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
962 LIR_Address* to_addr = dest->as_address_ptr();
963 PatchingStub* patch = NULL;
964 Register compressed_src = rscratch1;
965
966 if (type == T_ARRAY || type == T_OBJECT) {
967 __ verify_oop(src->as_register());
968 #ifdef _LP64
969 if (UseCompressedOops && !wide) {
970 __ movptr(compressed_src, src->as_register());
971 __ encode_heap_oop(compressed_src);
972 if (patch_code != lir_patch_none) {
973 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
974 }
975 }
976 #endif
977 }
978
979 if (patch_code != lir_patch_none) {
980 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
981 Address toa = as_Address(to_addr);
982 assert(toa.disp() != 0, "must have");
983 }
984
985 int null_check_here = code_offset();
986 switch (type) {
987 case T_FLOAT: {
988 if (src->is_single_xmm()) {
989 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
990 } else {
991 assert(src->is_single_fpu(), "must be");
992 assert(src->fpu_regnr() == 0, "argument must be on TOS");
993 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
994 else __ fst_s (as_Address(to_addr));
995 }
996 break;
997 }
998
999 case T_DOUBLE: {
1000 if (src->is_double_xmm()) {
1001 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1002 } else {
1003 assert(src->is_double_fpu(), "must be");
1004 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1005 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1006 else __ fst_d (as_Address(to_addr));
1007 }
1008 break;
1009 }
1010
1011 case T_ARRAY: // fall through
1012 case T_OBJECT: // fall through
1013 if (UseCompressedOops && !wide) {
1014 __ movl(as_Address(to_addr), compressed_src);
1015 } else {
1016 __ movptr(as_Address(to_addr), src->as_register());
1017 }
1018 break;
1019 case T_METADATA:
1020 // We get here to store a method pointer to the stack to pass to
1021 // a dtrace runtime call. This can't work on 64 bit with
1022 // compressed klass ptrs: T_METADATA can be a compressed klass
1023 // ptr or a 64 bit method pointer.
1024 LP64_ONLY(ShouldNotReachHere());
1025 __ movptr(as_Address(to_addr), src->as_register());
1026 break;
1027 case T_ADDRESS:
1028 __ movptr(as_Address(to_addr), src->as_register());
1029 break;
1030 case T_INT:
1031 __ movl(as_Address(to_addr), src->as_register());
1032 break;
1033
1034 case T_LONG: {
1035 Register from_lo = src->as_register_lo();
1036 Register from_hi = src->as_register_hi();
1037 #ifdef _LP64
1038 __ movptr(as_Address_lo(to_addr), from_lo);
1039 #else
1040 Register base = to_addr->base()->as_register();
1041 Register index = noreg;
1042 if (to_addr->index()->is_register()) {
1043 index = to_addr->index()->as_register();
1044 }
1045 if (base == from_lo || index == from_lo) {
1046 assert(base != from_hi, "can't be");
1047 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1048 __ movl(as_Address_hi(to_addr), from_hi);
1049 if (patch != NULL) {
1050 patching_epilog(patch, lir_patch_high, base, info);
1051 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1052 patch_code = lir_patch_low;
1053 }
1054 __ movl(as_Address_lo(to_addr), from_lo);
1055 } else {
1056 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1057 __ movl(as_Address_lo(to_addr), from_lo);
1058 if (patch != NULL) {
1059 patching_epilog(patch, lir_patch_low, base, info);
1060 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1061 patch_code = lir_patch_high;
1062 }
1063 __ movl(as_Address_hi(to_addr), from_hi);
1064 }
1065 #endif // _LP64
1066 break;
1067 }
1068
1069 case T_BYTE: // fall through
1070 case T_BOOLEAN: {
1071 Register src_reg = src->as_register();
1072 Address dst_addr = as_Address(to_addr);
1073 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1074 __ movb(dst_addr, src_reg);
1075 break;
1076 }
1077
1078 case T_CHAR: // fall through
1079 case T_SHORT:
1080 __ movw(as_Address(to_addr), src->as_register());
1081 break;
1082
1083 default:
1084 ShouldNotReachHere();
1085 }
1086 if (info != NULL) {
1087 add_debug_info_for_null_check(null_check_here, info);
1088 }
1089
1090 if (patch_code != lir_patch_none) {
1091 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1092 }
1093 }
1094
1095
1096 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1097 assert(src->is_stack(), "should not call otherwise");
1098 assert(dest->is_register(), "should not call otherwise");
1099
1100 if (dest->is_single_cpu()) {
1101 if (type == T_ARRAY || type == T_OBJECT) {
1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1103 __ verify_oop(dest->as_register());
1104 } else if (type == T_METADATA) {
1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1106 } else {
1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1108 }
1109
1110 } else if (dest->is_double_cpu()) {
1111 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1112 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1113 __ movptr(dest->as_register_lo(), src_addr_LO);
1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1115
1116 } else if (dest->is_single_xmm()) {
1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1118 __ movflt(dest->as_xmm_float_reg(), src_addr);
1119
1120 } else if (dest->is_double_xmm()) {
1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1122 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1123
1124 } else if (dest->is_single_fpu()) {
1125 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1126 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1127 __ fld_s(src_addr);
1128
1129 } else if (dest->is_double_fpu()) {
1130 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1131 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1132 __ fld_d(src_addr);
1133
1134 } else {
1135 ShouldNotReachHere();
1136 }
1137 }
1138
1139
1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1141 if (src->is_single_stack()) {
1142 if (type == T_OBJECT || type == T_ARRAY) {
1143 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1145 } else {
1146 #ifndef _LP64
1147 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1148 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1149 #else
1150 //no pushl on 64bits
1151 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1152 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1153 #endif
1154 }
1155
1156 } else if (src->is_double_stack()) {
1157 #ifdef _LP64
1158 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1159 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1160 #else
1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1162 // push and pop the part at src + wordSize, adding wordSize for the previous push
1163 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1165 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1166 #endif // _LP64
1167
1168 } else {
1169 ShouldNotReachHere();
1170 }
1171 }
1172
1173
1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1175 assert(src->is_address(), "should not call otherwise");
1176 assert(dest->is_register(), "should not call otherwise");
1177
1178 LIR_Address* addr = src->as_address_ptr();
1179 Address from_addr = as_Address(addr);
1180
1181 if (addr->base()->type() == T_OBJECT) {
1182 __ verify_oop(addr->base()->as_pointer_register());
1183 }
1184
1185 switch (type) {
1186 case T_BOOLEAN: // fall through
1187 case T_BYTE: // fall through
1188 case T_CHAR: // fall through
1189 case T_SHORT:
1190 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1191 // on pre P6 processors we may get partial register stalls
1192 // so blow away the value of to_rinfo before loading a
1193 // partial word into it. Do it here so that it precedes
1194 // the potential patch point below.
1195 __ xorptr(dest->as_register(), dest->as_register());
1196 }
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 PatchingStub* patch = NULL;
1203 if (patch_code != lir_patch_none) {
1204 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1205 assert(from_addr.disp() != 0, "must have");
1206 }
1207 if (info != NULL) {
1208 add_debug_info_for_null_check_here(info);
1209 }
1210
1211 switch (type) {
1212 case T_FLOAT: {
1213 if (dest->is_single_xmm()) {
1214 __ movflt(dest->as_xmm_float_reg(), from_addr);
1215 } else {
1216 assert(dest->is_single_fpu(), "must be");
1217 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1218 __ fld_s(from_addr);
1219 }
1220 break;
1221 }
1222
1223 case T_DOUBLE: {
1224 if (dest->is_double_xmm()) {
1225 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226 } else {
1227 assert(dest->is_double_fpu(), "must be");
1228 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1229 __ fld_d(from_addr);
1230 }
1231 break;
1232 }
1233
1234 case T_OBJECT: // fall through
1235 case T_ARRAY: // fall through
1236 if (UseCompressedOops && !wide) {
1237 __ movl(dest->as_register(), from_addr);
1238 } else {
1239 __ movptr(dest->as_register(), from_addr);
1240 }
1241 break;
1242
1243 case T_ADDRESS:
1244 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1245 __ movl(dest->as_register(), from_addr);
1246 } else {
1247 __ movptr(dest->as_register(), from_addr);
1248 }
1249 break;
1250 case T_INT:
1251 __ movl(dest->as_register(), from_addr);
1252 break;
1253
1254 case T_LONG: {
1255 Register to_lo = dest->as_register_lo();
1256 Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258 __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260 Register base = addr->base()->as_register();
1261 Register index = noreg;
1262 if (addr->index()->is_register()) {
1263 index = addr->index()->as_register();
1264 }
1265 if ((base == to_lo && index == to_hi) ||
1266 (base == to_hi && index == to_lo)) {
1267 // addresses with 2 registers are only formed as a result of
1268 // array access so this code will never have to deal with
1269 // patches or null checks.
1270 assert(info == NULL && patch == NULL, "must be");
1271 __ lea(to_hi, as_Address(addr));
1272 __ movl(to_lo, Address(to_hi, 0));
1273 __ movl(to_hi, Address(to_hi, BytesPerWord));
1274 } else if (base == to_lo || index == to_lo) {
1275 assert(base != to_hi, "can't be");
1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277 __ movl(to_hi, as_Address_hi(addr));
1278 if (patch != NULL) {
1279 patching_epilog(patch, lir_patch_high, base, info);
1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281 patch_code = lir_patch_low;
1282 }
1283 __ movl(to_lo, as_Address_lo(addr));
1284 } else {
1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286 __ movl(to_lo, as_Address_lo(addr));
1287 if (patch != NULL) {
1288 patching_epilog(patch, lir_patch_low, base, info);
1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290 patch_code = lir_patch_high;
1291 }
1292 __ movl(to_hi, as_Address_hi(addr));
1293 }
1294 #endif // _LP64
1295 break;
1296 }
1297
1298 case T_BOOLEAN: // fall through
1299 case T_BYTE: {
1300 Register dest_reg = dest->as_register();
1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303 __ movsbl(dest_reg, from_addr);
1304 } else {
1305 __ movb(dest_reg, from_addr);
1306 __ shll(dest_reg, 24);
1307 __ sarl(dest_reg, 24);
1308 }
1309 break;
1310 }
1311
1312 case T_CHAR: {
1313 Register dest_reg = dest->as_register();
1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316 __ movzwl(dest_reg, from_addr);
1317 } else {
1318 __ movw(dest_reg, from_addr);
1319 }
1320 break;
1321 }
1322
1323 case T_SHORT: {
1324 Register dest_reg = dest->as_register();
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movswl(dest_reg, from_addr);
1327 } else {
1328 __ movw(dest_reg, from_addr);
1329 __ shll(dest_reg, 16);
1330 __ sarl(dest_reg, 16);
1331 }
1332 break;
1333 }
1334
1335 default:
1336 ShouldNotReachHere();
1337 }
1338
1339 if (patch != NULL) {
1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341 }
1342
1343 if (type == T_ARRAY || type == T_OBJECT) {
1344 #ifdef _LP64
1345 if (UseCompressedOops && !wide) {
1346 __ decode_heap_oop(dest->as_register());
1347 }
1348 #endif
1349
1350 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1351 if (!UseZGC) {
1352 __ verify_oop(dest->as_register());
1353 }
1354 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1355 #ifdef _LP64
1356 if (UseCompressedClassPointers) {
1357 __ decode_klass_not_null(dest->as_register());
1358 }
1359 #endif
1360 }
1361 }
1362
1363
1364 NEEDS_CLEANUP; // This could be static?
1365 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1366 int elem_size = type2aelembytes(type);
1367 switch (elem_size) {
1368 case 1: return Address::times_1;
1369 case 2: return Address::times_2;
1370 case 4: return Address::times_4;
1371 case 8: return Address::times_8;
1372 }
1373 ShouldNotReachHere();
1374 return Address::no_scale;
1375 }
1376
1377
1378 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1379 switch (op->code()) {
1380 case lir_idiv:
1381 case lir_irem:
1382 arithmetic_idiv(op->code(),
1383 op->in_opr1(),
1384 op->in_opr2(),
1385 op->in_opr3(),
1386 op->result_opr(),
1387 op->info());
1388 break;
1389 case lir_fmad:
1390 __ fmad(op->result_opr()->as_xmm_double_reg(),
1391 op->in_opr1()->as_xmm_double_reg(),
1392 op->in_opr2()->as_xmm_double_reg(),
1393 op->in_opr3()->as_xmm_double_reg());
1394 break;
1395 case lir_fmaf:
1396 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1397 op->in_opr1()->as_xmm_float_reg(),
1398 op->in_opr2()->as_xmm_float_reg(),
1399 op->in_opr3()->as_xmm_float_reg());
1400 break;
1401 default: ShouldNotReachHere(); break;
1402 }
1403 }
1404
1405 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1406 #ifdef ASSERT
1407 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1408 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1409 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1410 #endif
1411
1412 if (op->cond() == lir_cond_always) {
1413 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1414 __ jmp (*(op->label()));
1415 } else {
1416 Assembler::Condition acond = Assembler::zero;
1417 if (op->code() == lir_cond_float_branch) {
1418 assert(op->ublock() != NULL, "must have unordered successor");
1419 __ jcc(Assembler::parity, *(op->ublock()->label()));
1420 switch(op->cond()) {
1421 case lir_cond_equal: acond = Assembler::equal; break;
1422 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1423 case lir_cond_less: acond = Assembler::below; break;
1424 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1425 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1426 case lir_cond_greater: acond = Assembler::above; break;
1427 default: ShouldNotReachHere();
1428 }
1429 } else {
1430 switch (op->cond()) {
1431 case lir_cond_equal: acond = Assembler::equal; break;
1432 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1433 case lir_cond_less: acond = Assembler::less; break;
1434 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1435 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1436 case lir_cond_greater: acond = Assembler::greater; break;
1437 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1438 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1439 default: ShouldNotReachHere();
1440 }
1441 }
1442 __ jcc(acond,*(op->label()));
1443 }
1444 }
1445
1446 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1447 LIR_Opr src = op->in_opr();
1448 LIR_Opr dest = op->result_opr();
1449
1450 switch (op->bytecode()) {
1451 case Bytecodes::_i2l:
1452 #ifdef _LP64
1453 __ movl2ptr(dest->as_register_lo(), src->as_register());
1454 #else
1455 move_regs(src->as_register(), dest->as_register_lo());
1456 move_regs(src->as_register(), dest->as_register_hi());
1457 __ sarl(dest->as_register_hi(), 31);
1458 #endif // LP64
1459 break;
1460
1461 case Bytecodes::_l2i:
1462 #ifdef _LP64
1463 __ movl(dest->as_register(), src->as_register_lo());
1464 #else
1465 move_regs(src->as_register_lo(), dest->as_register());
1466 #endif
1467 break;
1468
1469 case Bytecodes::_i2b:
1470 move_regs(src->as_register(), dest->as_register());
1471 __ sign_extend_byte(dest->as_register());
1472 break;
1473
1474 case Bytecodes::_i2c:
1475 move_regs(src->as_register(), dest->as_register());
1476 __ andl(dest->as_register(), 0xFFFF);
1477 break;
1478
1479 case Bytecodes::_i2s:
1480 move_regs(src->as_register(), dest->as_register());
1481 __ sign_extend_short(dest->as_register());
1482 break;
1483
1484
1485 case Bytecodes::_f2d:
1486 case Bytecodes::_d2f:
1487 if (dest->is_single_xmm()) {
1488 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1489 } else if (dest->is_double_xmm()) {
1490 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1491 } else {
1492 assert(src->fpu() == dest->fpu(), "register must be equal");
1493 // do nothing (float result is rounded later through spilling)
1494 }
1495 break;
1496
1497 case Bytecodes::_i2f:
1498 case Bytecodes::_i2d:
1499 if (dest->is_single_xmm()) {
1500 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1501 } else if (dest->is_double_xmm()) {
1502 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1503 } else {
1504 assert(dest->fpu() == 0, "result must be on TOS");
1505 __ movl(Address(rsp, 0), src->as_register());
1506 __ fild_s(Address(rsp, 0));
1507 }
1508 break;
1509
1510 case Bytecodes::_f2i:
1511 case Bytecodes::_d2i:
1512 if (src->is_single_xmm()) {
1513 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1514 } else if (src->is_double_xmm()) {
1515 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1516 } else {
1517 assert(src->fpu() == 0, "input must be on TOS");
1518 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1519 __ fist_s(Address(rsp, 0));
1520 __ movl(dest->as_register(), Address(rsp, 0));
1521 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1522 }
1523
1524 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1525 assert(op->stub() != NULL, "stub required");
1526 __ cmpl(dest->as_register(), 0x80000000);
1527 __ jcc(Assembler::equal, *op->stub()->entry());
1528 __ bind(*op->stub()->continuation());
1529 break;
1530
1531 case Bytecodes::_l2f:
1532 case Bytecodes::_l2d:
1533 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1534 assert(dest->fpu() == 0, "result must be on TOS");
1535
1536 __ movptr(Address(rsp, 0), src->as_register_lo());
1537 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1538 __ fild_d(Address(rsp, 0));
1539 // float result is rounded later through spilling
1540 break;
1541
1542 case Bytecodes::_f2l:
1543 case Bytecodes::_d2l:
1544 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1545 assert(src->fpu() == 0, "input must be on TOS");
1546 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1547
1548 // instruction sequence too long to inline it here
1549 {
1550 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1551 }
1552 break;
1553
1554 default: ShouldNotReachHere();
1555 }
1556 }
1557
1558 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1559 if (op->init_check()) {
1560 add_debug_info_for_null_check_here(op->stub()->info());
1561 __ cmpb(Address(op->klass()->as_register(),
1562 InstanceKlass::init_state_offset()),
1563 InstanceKlass::fully_initialized);
1564 __ jcc(Assembler::notEqual, *op->stub()->entry());
1565 }
1566 __ allocate_object(op->obj()->as_register(),
1567 op->tmp1()->as_register(),
1568 op->tmp2()->as_register(),
1569 op->header_size(),
1570 op->object_size(),
1571 op->klass()->as_register(),
1572 *op->stub()->entry());
1573 __ bind(*op->stub()->continuation());
1574 }
1575
1576 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1577 Register len = op->len()->as_register();
1578 LP64_ONLY( __ movslq(len, len); )
1579
1580 if (UseSlowPath ||
1581 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1582 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1583 __ jmp(*op->stub()->entry());
1584 } else {
1585 Register tmp1 = op->tmp1()->as_register();
1586 Register tmp2 = op->tmp2()->as_register();
1587 Register tmp3 = op->tmp3()->as_register();
1588 if (len == tmp1) {
1589 tmp1 = tmp3;
1590 } else if (len == tmp2) {
1591 tmp2 = tmp3;
1592 } else if (len == tmp3) {
1593 // everything is ok
1594 } else {
1595 __ mov(tmp3, len);
1596 }
1597 __ allocate_array(op->obj()->as_register(),
1598 len,
1599 tmp1,
1600 tmp2,
1601 arrayOopDesc::header_size(op->type()),
1602 array_element_size(op->type()),
1603 op->klass()->as_register(),
1604 *op->stub()->entry());
1605 }
1606 __ bind(*op->stub()->continuation());
1607 }
1608
1609 void LIR_Assembler::type_profile_helper(Register mdo,
1610 ciMethodData *md, ciProfileData *data,
1611 Register recv, Label* update_done) {
1612 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1613 Label next_test;
1614 // See if the receiver is receiver[n].
1615 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1616 __ jccb(Assembler::notEqual, next_test);
1617 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1618 __ addptr(data_addr, DataLayout::counter_increment);
1619 __ jmp(*update_done);
1620 __ bind(next_test);
1621 }
1622
1623 // Didn't find receiver; find next empty slot and fill it in
1624 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1625 Label next_test;
1626 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1627 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1628 __ jccb(Assembler::notEqual, next_test);
1629 __ movptr(recv_addr, recv);
1630 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1631 __ jmp(*update_done);
1632 __ bind(next_test);
1633 }
1634 }
1635
1636 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1637 // we always need a stub for the failure case.
1638 CodeStub* stub = op->stub();
1639 Register obj = op->object()->as_register();
1640 Register k_RInfo = op->tmp1()->as_register();
1641 Register klass_RInfo = op->tmp2()->as_register();
1642 Register dst = op->result_opr()->as_register();
1643 ciKlass* k = op->klass();
1644 Register Rtmp1 = noreg;
1645
1646 // check if it needs to be profiled
1647 ciMethodData* md = NULL;
1648 ciProfileData* data = NULL;
1649
1650 if (op->should_profile()) {
1651 ciMethod* method = op->profiled_method();
1652 assert(method != NULL, "Should have method");
1653 int bci = op->profiled_bci();
1654 md = method->method_data_or_null();
1655 assert(md != NULL, "Sanity");
1656 data = md->bci_to_data(bci);
1657 assert(data != NULL, "need data for type check");
1658 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1659 }
1660 Label profile_cast_success, profile_cast_failure;
1661 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1662 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1663
1664 if (obj == k_RInfo) {
1665 k_RInfo = dst;
1666 } else if (obj == klass_RInfo) {
1667 klass_RInfo = dst;
1668 }
1669 if (k->is_loaded() && !UseCompressedClassPointers) {
1670 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1671 } else {
1672 Rtmp1 = op->tmp3()->as_register();
1673 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1674 }
1675
1676 assert_different_registers(obj, k_RInfo, klass_RInfo);
1677
1678 __ cmpptr(obj, (int32_t)NULL_WORD);
1679 if (op->should_profile()) {
1680 Label not_null;
1681 __ jccb(Assembler::notEqual, not_null);
1682 // Object is null; update MDO and exit
1683 Register mdo = klass_RInfo;
1684 __ mov_metadata(mdo, md->constant_encoding());
1685 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1686 int header_bits = BitData::null_seen_byte_constant();
1687 __ orb(data_addr, header_bits);
1688 __ jmp(*obj_is_null);
1689 __ bind(not_null);
1690 } else {
1691 __ jcc(Assembler::equal, *obj_is_null);
1692 }
1693
1694 if (!k->is_loaded()) {
1695 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1696 } else {
1697 #ifdef _LP64
1698 __ mov_metadata(k_RInfo, k->constant_encoding());
1699 #endif // _LP64
1700 }
1701 __ verify_oop(obj);
1702
1703 if (op->fast_check()) {
1704 // get object class
1705 // not a safepoint as obj null check happens earlier
1706 #ifdef _LP64
1707 if (UseCompressedClassPointers) {
1708 __ load_klass(Rtmp1, obj);
1709 __ cmpptr(k_RInfo, Rtmp1);
1710 } else {
1711 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1712 }
1713 #else
1714 if (k->is_loaded()) {
1715 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1716 } else {
1717 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1718 }
1719 #endif
1720 __ jcc(Assembler::notEqual, *failure_target);
1721 // successful cast, fall through to profile or jump
1722 } else {
1723 // get object class
1724 // not a safepoint as obj null check happens earlier
1725 __ load_klass(klass_RInfo, obj);
1726 if (k->is_loaded()) {
1727 // See if we get an immediate positive hit
1728 #ifdef _LP64
1729 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1730 #else
1731 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1732 #endif // _LP64
1733 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1734 __ jcc(Assembler::notEqual, *failure_target);
1735 // successful cast, fall through to profile or jump
1736 } else {
1737 // See if we get an immediate positive hit
1738 __ jcc(Assembler::equal, *success_target);
1739 // check for self
1740 #ifdef _LP64
1741 __ cmpptr(klass_RInfo, k_RInfo);
1742 #else
1743 __ cmpklass(klass_RInfo, k->constant_encoding());
1744 #endif // _LP64
1745 __ jcc(Assembler::equal, *success_target);
1746
1747 __ push(klass_RInfo);
1748 #ifdef _LP64
1749 __ push(k_RInfo);
1750 #else
1751 __ pushklass(k->constant_encoding());
1752 #endif // _LP64
1753 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1754 __ pop(klass_RInfo);
1755 __ pop(klass_RInfo);
1756 // result is a boolean
1757 __ cmpl(klass_RInfo, 0);
1758 __ jcc(Assembler::equal, *failure_target);
1759 // successful cast, fall through to profile or jump
1760 }
1761 } else {
1762 // perform the fast part of the checking logic
1763 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1764 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1765 __ push(klass_RInfo);
1766 __ push(k_RInfo);
1767 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1768 __ pop(klass_RInfo);
1769 __ pop(k_RInfo);
1770 // result is a boolean
1771 __ cmpl(k_RInfo, 0);
1772 __ jcc(Assembler::equal, *failure_target);
1773 // successful cast, fall through to profile or jump
1774 }
1775 }
1776 if (op->should_profile()) {
1777 Register mdo = klass_RInfo, recv = k_RInfo;
1778 __ bind(profile_cast_success);
1779 __ mov_metadata(mdo, md->constant_encoding());
1780 __ load_klass(recv, obj);
1781 Label update_done;
1782 type_profile_helper(mdo, md, data, recv, success);
1783 __ jmp(*success);
1784
1785 __ bind(profile_cast_failure);
1786 __ mov_metadata(mdo, md->constant_encoding());
1787 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1788 __ subptr(counter_addr, DataLayout::counter_increment);
1789 __ jmp(*failure);
1790 }
1791 __ jmp(*success);
1792 }
1793
1794
1795 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1796 LIR_Code code = op->code();
1797 if (code == lir_store_check) {
1798 Register value = op->object()->as_register();
1799 Register array = op->array()->as_register();
1800 Register k_RInfo = op->tmp1()->as_register();
1801 Register klass_RInfo = op->tmp2()->as_register();
1802 Register Rtmp1 = op->tmp3()->as_register();
1803
1804 CodeStub* stub = op->stub();
1805
1806 // check if it needs to be profiled
1807 ciMethodData* md = NULL;
1808 ciProfileData* data = NULL;
1809
1810 if (op->should_profile()) {
1811 ciMethod* method = op->profiled_method();
1812 assert(method != NULL, "Should have method");
1813 int bci = op->profiled_bci();
1814 md = method->method_data_or_null();
1815 assert(md != NULL, "Sanity");
1816 data = md->bci_to_data(bci);
1817 assert(data != NULL, "need data for type check");
1818 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1819 }
1820 Label profile_cast_success, profile_cast_failure, done;
1821 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1822 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1823
1824 __ cmpptr(value, (int32_t)NULL_WORD);
1825 if (op->should_profile()) {
1826 Label not_null;
1827 __ jccb(Assembler::notEqual, not_null);
1828 // Object is null; update MDO and exit
1829 Register mdo = klass_RInfo;
1830 __ mov_metadata(mdo, md->constant_encoding());
1831 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1832 int header_bits = BitData::null_seen_byte_constant();
1833 __ orb(data_addr, header_bits);
1834 __ jmp(done);
1835 __ bind(not_null);
1836 } else {
1837 __ jcc(Assembler::equal, done);
1838 }
1839
1840 add_debug_info_for_null_check_here(op->info_for_exception());
1841 __ load_klass(k_RInfo, array);
1842 __ load_klass(klass_RInfo, value);
1843
1844 // get instance klass (it's already uncompressed)
1845 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1846 // perform the fast part of the checking logic
1847 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1848 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1849 __ push(klass_RInfo);
1850 __ push(k_RInfo);
1851 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1852 __ pop(klass_RInfo);
1853 __ pop(k_RInfo);
1854 // result is a boolean
1855 __ cmpl(k_RInfo, 0);
1856 __ jcc(Assembler::equal, *failure_target);
1857 // fall through to the success case
1858
1859 if (op->should_profile()) {
1860 Register mdo = klass_RInfo, recv = k_RInfo;
1861 __ bind(profile_cast_success);
1862 __ mov_metadata(mdo, md->constant_encoding());
1863 __ load_klass(recv, value);
1864 Label update_done;
1865 type_profile_helper(mdo, md, data, recv, &done);
1866 __ jmpb(done);
1867
1868 __ bind(profile_cast_failure);
1869 __ mov_metadata(mdo, md->constant_encoding());
1870 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1871 __ subptr(counter_addr, DataLayout::counter_increment);
1872 __ jmp(*stub->entry());
1873 }
1874
1875 __ bind(done);
1876 } else
1877 if (code == lir_checkcast) {
1878 Register obj = op->object()->as_register();
1879 Register dst = op->result_opr()->as_register();
1880 Label success;
1881 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1882 __ bind(success);
1883 if (dst != obj) {
1884 __ mov(dst, obj);
1885 }
1886 } else
1887 if (code == lir_instanceof) {
1888 Register obj = op->object()->as_register();
1889 Register dst = op->result_opr()->as_register();
1890 Label success, failure, done;
1891 emit_typecheck_helper(op, &success, &failure, &failure);
1892 __ bind(failure);
1893 __ xorptr(dst, dst);
1894 __ jmpb(done);
1895 __ bind(success);
1896 __ movptr(dst, 1);
1897 __ bind(done);
1898 } else {
1899 ShouldNotReachHere();
1900 }
1901
1902 }
1903
1904
1905 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1906 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1907 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1908 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1909 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1910 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1911 Register addr = op->addr()->as_register();
1912 if (os::is_MP()) {
1913 __ lock();
1914 }
1915 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1916
1917 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1918 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1919 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1920 Register newval = op->new_value()->as_register();
1921 Register cmpval = op->cmp_value()->as_register();
1922 assert(cmpval == rax, "wrong register");
1923 assert(newval != NULL, "new val must be register");
1924 assert(cmpval != newval, "cmp and new values must be in different registers");
1925 assert(cmpval != addr, "cmp and addr must be in different registers");
1926 assert(newval != addr, "new value and addr must be in different registers");
1927
1928 if ( op->code() == lir_cas_obj) {
1929 Register tmp1 = op->tmp1()->as_register();
1930 Register tmp2 = op->tmp2()->as_register();
1931 __ cmpxchg_oop(NULL, Address(addr, 0), cmpval, newval, true, true, tmp1, tmp2);
1932 } else {
1933 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1934 if (os::is_MP()) {
1935 __ lock();
1936 }
1937 __ cmpxchgl(newval, Address(addr, 0));
1938 }
1939 #ifdef _LP64
1940 } else if (op->code() == lir_cas_long) {
1941 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1942 Register newval = op->new_value()->as_register_lo();
1943 Register cmpval = op->cmp_value()->as_register_lo();
1944 assert(cmpval == rax, "wrong register");
1945 assert(newval != NULL, "new val must be register");
1946 assert(cmpval != newval, "cmp and new values must be in different registers");
1947 assert(cmpval != addr, "cmp and addr must be in different registers");
1948 assert(newval != addr, "new value and addr must be in different registers");
1949 if (os::is_MP()) {
1950 __ lock();
1951 }
1952 __ cmpxchgq(newval, Address(addr, 0));
1953 #endif // _LP64
1954 } else {
1955 Unimplemented();
1956 }
1957 }
1958
1959 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1960 Assembler::Condition acond, ncond;
1961 switch (condition) {
1962 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1963 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1964 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1965 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1966 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1967 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1968 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1969 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1970 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1971 ShouldNotReachHere();
1972 }
1973
1974 if (opr1->is_cpu_register()) {
1975 reg2reg(opr1, result);
1976 } else if (opr1->is_stack()) {
1977 stack2reg(opr1, result, result->type());
1978 } else if (opr1->is_constant()) {
1979 const2reg(opr1, result, lir_patch_none, NULL);
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983
1984 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1985 // optimized version that does not require a branch
1986 if (opr2->is_single_cpu()) {
1987 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1988 __ cmov(ncond, result->as_register(), opr2->as_register());
1989 } else if (opr2->is_double_cpu()) {
1990 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1991 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1992 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1993 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1994 } else if (opr2->is_single_stack()) {
1995 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1996 } else if (opr2->is_double_stack()) {
1997 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1998 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1999 } else {
2000 ShouldNotReachHere();
2001 }
2002
2003 } else {
2004 Label skip;
2005 __ jcc (acond, skip);
2006 if (opr2->is_cpu_register()) {
2007 reg2reg(opr2, result);
2008 } else if (opr2->is_stack()) {
2009 stack2reg(opr2, result, result->type());
2010 } else if (opr2->is_constant()) {
2011 const2reg(opr2, result, lir_patch_none, NULL);
2012 } else {
2013 ShouldNotReachHere();
2014 }
2015 __ bind(skip);
2016 }
2017 }
2018
2019
2020 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2021 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2022
2023 if (left->is_single_cpu()) {
2024 assert(left == dest, "left and dest must be equal");
2025 Register lreg = left->as_register();
2026
2027 if (right->is_single_cpu()) {
2028 // cpu register - cpu register
2029 Register rreg = right->as_register();
2030 switch (code) {
2031 case lir_add: __ addl (lreg, rreg); break;
2032 case lir_sub: __ subl (lreg, rreg); break;
2033 case lir_mul: __ imull(lreg, rreg); break;
2034 default: ShouldNotReachHere();
2035 }
2036
2037 } else if (right->is_stack()) {
2038 // cpu register - stack
2039 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2040 switch (code) {
2041 case lir_add: __ addl(lreg, raddr); break;
2042 case lir_sub: __ subl(lreg, raddr); break;
2043 default: ShouldNotReachHere();
2044 }
2045
2046 } else if (right->is_constant()) {
2047 // cpu register - constant
2048 jint c = right->as_constant_ptr()->as_jint();
2049 switch (code) {
2050 case lir_add: {
2051 __ incrementl(lreg, c);
2052 break;
2053 }
2054 case lir_sub: {
2055 __ decrementl(lreg, c);
2056 break;
2057 }
2058 default: ShouldNotReachHere();
2059 }
2060
2061 } else {
2062 ShouldNotReachHere();
2063 }
2064
2065 } else if (left->is_double_cpu()) {
2066 assert(left == dest, "left and dest must be equal");
2067 Register lreg_lo = left->as_register_lo();
2068 Register lreg_hi = left->as_register_hi();
2069
2070 if (right->is_double_cpu()) {
2071 // cpu register - cpu register
2072 Register rreg_lo = right->as_register_lo();
2073 Register rreg_hi = right->as_register_hi();
2074 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2075 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2076 switch (code) {
2077 case lir_add:
2078 __ addptr(lreg_lo, rreg_lo);
2079 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2080 break;
2081 case lir_sub:
2082 __ subptr(lreg_lo, rreg_lo);
2083 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2084 break;
2085 case lir_mul:
2086 #ifdef _LP64
2087 __ imulq(lreg_lo, rreg_lo);
2088 #else
2089 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2090 __ imull(lreg_hi, rreg_lo);
2091 __ imull(rreg_hi, lreg_lo);
2092 __ addl (rreg_hi, lreg_hi);
2093 __ mull (rreg_lo);
2094 __ addl (lreg_hi, rreg_hi);
2095 #endif // _LP64
2096 break;
2097 default:
2098 ShouldNotReachHere();
2099 }
2100
2101 } else if (right->is_constant()) {
2102 // cpu register - constant
2103 #ifdef _LP64
2104 jlong c = right->as_constant_ptr()->as_jlong_bits();
2105 __ movptr(r10, (intptr_t) c);
2106 switch (code) {
2107 case lir_add:
2108 __ addptr(lreg_lo, r10);
2109 break;
2110 case lir_sub:
2111 __ subptr(lreg_lo, r10);
2112 break;
2113 default:
2114 ShouldNotReachHere();
2115 }
2116 #else
2117 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2118 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2119 switch (code) {
2120 case lir_add:
2121 __ addptr(lreg_lo, c_lo);
2122 __ adcl(lreg_hi, c_hi);
2123 break;
2124 case lir_sub:
2125 __ subptr(lreg_lo, c_lo);
2126 __ sbbl(lreg_hi, c_hi);
2127 break;
2128 default:
2129 ShouldNotReachHere();
2130 }
2131 #endif // _LP64
2132
2133 } else {
2134 ShouldNotReachHere();
2135 }
2136
2137 } else if (left->is_single_xmm()) {
2138 assert(left == dest, "left and dest must be equal");
2139 XMMRegister lreg = left->as_xmm_float_reg();
2140
2141 if (right->is_single_xmm()) {
2142 XMMRegister rreg = right->as_xmm_float_reg();
2143 switch (code) {
2144 case lir_add: __ addss(lreg, rreg); break;
2145 case lir_sub: __ subss(lreg, rreg); break;
2146 case lir_mul_strictfp: // fall through
2147 case lir_mul: __ mulss(lreg, rreg); break;
2148 case lir_div_strictfp: // fall through
2149 case lir_div: __ divss(lreg, rreg); break;
2150 default: ShouldNotReachHere();
2151 }
2152 } else {
2153 Address raddr;
2154 if (right->is_single_stack()) {
2155 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2156 } else if (right->is_constant()) {
2157 // hack for now
2158 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2159 } else {
2160 ShouldNotReachHere();
2161 }
2162 switch (code) {
2163 case lir_add: __ addss(lreg, raddr); break;
2164 case lir_sub: __ subss(lreg, raddr); break;
2165 case lir_mul_strictfp: // fall through
2166 case lir_mul: __ mulss(lreg, raddr); break;
2167 case lir_div_strictfp: // fall through
2168 case lir_div: __ divss(lreg, raddr); break;
2169 default: ShouldNotReachHere();
2170 }
2171 }
2172
2173 } else if (left->is_double_xmm()) {
2174 assert(left == dest, "left and dest must be equal");
2175
2176 XMMRegister lreg = left->as_xmm_double_reg();
2177 if (right->is_double_xmm()) {
2178 XMMRegister rreg = right->as_xmm_double_reg();
2179 switch (code) {
2180 case lir_add: __ addsd(lreg, rreg); break;
2181 case lir_sub: __ subsd(lreg, rreg); break;
2182 case lir_mul_strictfp: // fall through
2183 case lir_mul: __ mulsd(lreg, rreg); break;
2184 case lir_div_strictfp: // fall through
2185 case lir_div: __ divsd(lreg, rreg); break;
2186 default: ShouldNotReachHere();
2187 }
2188 } else {
2189 Address raddr;
2190 if (right->is_double_stack()) {
2191 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2192 } else if (right->is_constant()) {
2193 // hack for now
2194 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2195 } else {
2196 ShouldNotReachHere();
2197 }
2198 switch (code) {
2199 case lir_add: __ addsd(lreg, raddr); break;
2200 case lir_sub: __ subsd(lreg, raddr); break;
2201 case lir_mul_strictfp: // fall through
2202 case lir_mul: __ mulsd(lreg, raddr); break;
2203 case lir_div_strictfp: // fall through
2204 case lir_div: __ divsd(lreg, raddr); break;
2205 default: ShouldNotReachHere();
2206 }
2207 }
2208
2209 } else if (left->is_single_fpu()) {
2210 assert(dest->is_single_fpu(), "fpu stack allocation required");
2211
2212 if (right->is_single_fpu()) {
2213 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2214
2215 } else {
2216 assert(left->fpu_regnr() == 0, "left must be on TOS");
2217 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2218
2219 Address raddr;
2220 if (right->is_single_stack()) {
2221 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2222 } else if (right->is_constant()) {
2223 address const_addr = float_constant(right->as_jfloat());
2224 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2225 // hack for now
2226 raddr = __ as_Address(InternalAddress(const_addr));
2227 } else {
2228 ShouldNotReachHere();
2229 }
2230
2231 switch (code) {
2232 case lir_add: __ fadd_s(raddr); break;
2233 case lir_sub: __ fsub_s(raddr); break;
2234 case lir_mul_strictfp: // fall through
2235 case lir_mul: __ fmul_s(raddr); break;
2236 case lir_div_strictfp: // fall through
2237 case lir_div: __ fdiv_s(raddr); break;
2238 default: ShouldNotReachHere();
2239 }
2240 }
2241
2242 } else if (left->is_double_fpu()) {
2243 assert(dest->is_double_fpu(), "fpu stack allocation required");
2244
2245 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2246 // Double values require special handling for strictfp mul/div on x86
2247 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2248 __ fmulp(left->fpu_regnrLo() + 1);
2249 }
2250
2251 if (right->is_double_fpu()) {
2252 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2253
2254 } else {
2255 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2256 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2257
2258 Address raddr;
2259 if (right->is_double_stack()) {
2260 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2261 } else if (right->is_constant()) {
2262 // hack for now
2263 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2264 } else {
2265 ShouldNotReachHere();
2266 }
2267
2268 switch (code) {
2269 case lir_add: __ fadd_d(raddr); break;
2270 case lir_sub: __ fsub_d(raddr); break;
2271 case lir_mul_strictfp: // fall through
2272 case lir_mul: __ fmul_d(raddr); break;
2273 case lir_div_strictfp: // fall through
2274 case lir_div: __ fdiv_d(raddr); break;
2275 default: ShouldNotReachHere();
2276 }
2277 }
2278
2279 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2280 // Double values require special handling for strictfp mul/div on x86
2281 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2282 __ fmulp(dest->fpu_regnrLo() + 1);
2283 }
2284
2285 } else if (left->is_single_stack() || left->is_address()) {
2286 assert(left == dest, "left and dest must be equal");
2287
2288 Address laddr;
2289 if (left->is_single_stack()) {
2290 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2291 } else if (left->is_address()) {
2292 laddr = as_Address(left->as_address_ptr());
2293 } else {
2294 ShouldNotReachHere();
2295 }
2296
2297 if (right->is_single_cpu()) {
2298 Register rreg = right->as_register();
2299 switch (code) {
2300 case lir_add: __ addl(laddr, rreg); break;
2301 case lir_sub: __ subl(laddr, rreg); break;
2302 default: ShouldNotReachHere();
2303 }
2304 } else if (right->is_constant()) {
2305 jint c = right->as_constant_ptr()->as_jint();
2306 switch (code) {
2307 case lir_add: {
2308 __ incrementl(laddr, c);
2309 break;
2310 }
2311 case lir_sub: {
2312 __ decrementl(laddr, c);
2313 break;
2314 }
2315 default: ShouldNotReachHere();
2316 }
2317 } else {
2318 ShouldNotReachHere();
2319 }
2320
2321 } else {
2322 ShouldNotReachHere();
2323 }
2324 }
2325
2326 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2327 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2328 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2329 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2330
2331 bool left_is_tos = (left_index == 0);
2332 bool dest_is_tos = (dest_index == 0);
2333 int non_tos_index = (left_is_tos ? right_index : left_index);
2334
2335 switch (code) {
2336 case lir_add:
2337 if (pop_fpu_stack) __ faddp(non_tos_index);
2338 else if (dest_is_tos) __ fadd (non_tos_index);
2339 else __ fadda(non_tos_index);
2340 break;
2341
2342 case lir_sub:
2343 if (left_is_tos) {
2344 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2345 else if (dest_is_tos) __ fsub (non_tos_index);
2346 else __ fsubra(non_tos_index);
2347 } else {
2348 if (pop_fpu_stack) __ fsubp (non_tos_index);
2349 else if (dest_is_tos) __ fsubr (non_tos_index);
2350 else __ fsuba (non_tos_index);
2351 }
2352 break;
2353
2354 case lir_mul_strictfp: // fall through
2355 case lir_mul:
2356 if (pop_fpu_stack) __ fmulp(non_tos_index);
2357 else if (dest_is_tos) __ fmul (non_tos_index);
2358 else __ fmula(non_tos_index);
2359 break;
2360
2361 case lir_div_strictfp: // fall through
2362 case lir_div:
2363 if (left_is_tos) {
2364 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2365 else if (dest_is_tos) __ fdiv (non_tos_index);
2366 else __ fdivra(non_tos_index);
2367 } else {
2368 if (pop_fpu_stack) __ fdivp (non_tos_index);
2369 else if (dest_is_tos) __ fdivr (non_tos_index);
2370 else __ fdiva (non_tos_index);
2371 }
2372 break;
2373
2374 case lir_rem:
2375 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2376 __ fremr(noreg);
2377 break;
2378
2379 default:
2380 ShouldNotReachHere();
2381 }
2382 }
2383
2384
2385 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2386 if (value->is_double_xmm()) {
2387 switch(code) {
2388 case lir_abs :
2389 {
2390 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2391 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2392 }
2393 __ andpd(dest->as_xmm_double_reg(),
2394 ExternalAddress((address)double_signmask_pool));
2395 }
2396 break;
2397
2398 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2399 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2400 default : ShouldNotReachHere();
2401 }
2402
2403 } else if (value->is_double_fpu()) {
2404 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2405 switch(code) {
2406 case lir_abs : __ fabs() ; break;
2407 case lir_sqrt : __ fsqrt(); break;
2408 default : ShouldNotReachHere();
2409 }
2410 } else {
2411 Unimplemented();
2412 }
2413 }
2414
2415 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2416 // assert(left->destroys_register(), "check");
2417 if (left->is_single_cpu()) {
2418 Register reg = left->as_register();
2419 if (right->is_constant()) {
2420 int val = right->as_constant_ptr()->as_jint();
2421 switch (code) {
2422 case lir_logic_and: __ andl (reg, val); break;
2423 case lir_logic_or: __ orl (reg, val); break;
2424 case lir_logic_xor: __ xorl (reg, val); break;
2425 default: ShouldNotReachHere();
2426 }
2427 } else if (right->is_stack()) {
2428 // added support for stack operands
2429 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2430 switch (code) {
2431 case lir_logic_and: __ andl (reg, raddr); break;
2432 case lir_logic_or: __ orl (reg, raddr); break;
2433 case lir_logic_xor: __ xorl (reg, raddr); break;
2434 default: ShouldNotReachHere();
2435 }
2436 } else {
2437 Register rright = right->as_register();
2438 switch (code) {
2439 case lir_logic_and: __ andptr (reg, rright); break;
2440 case lir_logic_or : __ orptr (reg, rright); break;
2441 case lir_logic_xor: __ xorptr (reg, rright); break;
2442 default: ShouldNotReachHere();
2443 }
2444 }
2445 move_regs(reg, dst->as_register());
2446 } else {
2447 Register l_lo = left->as_register_lo();
2448 Register l_hi = left->as_register_hi();
2449 if (right->is_constant()) {
2450 #ifdef _LP64
2451 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2452 switch (code) {
2453 case lir_logic_and:
2454 __ andq(l_lo, rscratch1);
2455 break;
2456 case lir_logic_or:
2457 __ orq(l_lo, rscratch1);
2458 break;
2459 case lir_logic_xor:
2460 __ xorq(l_lo, rscratch1);
2461 break;
2462 default: ShouldNotReachHere();
2463 }
2464 #else
2465 int r_lo = right->as_constant_ptr()->as_jint_lo();
2466 int r_hi = right->as_constant_ptr()->as_jint_hi();
2467 switch (code) {
2468 case lir_logic_and:
2469 __ andl(l_lo, r_lo);
2470 __ andl(l_hi, r_hi);
2471 break;
2472 case lir_logic_or:
2473 __ orl(l_lo, r_lo);
2474 __ orl(l_hi, r_hi);
2475 break;
2476 case lir_logic_xor:
2477 __ xorl(l_lo, r_lo);
2478 __ xorl(l_hi, r_hi);
2479 break;
2480 default: ShouldNotReachHere();
2481 }
2482 #endif // _LP64
2483 } else {
2484 #ifdef _LP64
2485 Register r_lo;
2486 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2487 r_lo = right->as_register();
2488 } else {
2489 r_lo = right->as_register_lo();
2490 }
2491 #else
2492 Register r_lo = right->as_register_lo();
2493 Register r_hi = right->as_register_hi();
2494 assert(l_lo != r_hi, "overwriting registers");
2495 #endif
2496 switch (code) {
2497 case lir_logic_and:
2498 __ andptr(l_lo, r_lo);
2499 NOT_LP64(__ andptr(l_hi, r_hi);)
2500 break;
2501 case lir_logic_or:
2502 __ orptr(l_lo, r_lo);
2503 NOT_LP64(__ orptr(l_hi, r_hi);)
2504 break;
2505 case lir_logic_xor:
2506 __ xorptr(l_lo, r_lo);
2507 NOT_LP64(__ xorptr(l_hi, r_hi);)
2508 break;
2509 default: ShouldNotReachHere();
2510 }
2511 }
2512
2513 Register dst_lo = dst->as_register_lo();
2514 Register dst_hi = dst->as_register_hi();
2515
2516 #ifdef _LP64
2517 move_regs(l_lo, dst_lo);
2518 #else
2519 if (dst_lo == l_hi) {
2520 assert(dst_hi != l_lo, "overwriting registers");
2521 move_regs(l_hi, dst_hi);
2522 move_regs(l_lo, dst_lo);
2523 } else {
2524 assert(dst_lo != l_hi, "overwriting registers");
2525 move_regs(l_lo, dst_lo);
2526 move_regs(l_hi, dst_hi);
2527 }
2528 #endif // _LP64
2529 }
2530 }
2531
2532
2533 // we assume that rax, and rdx can be overwritten
2534 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2535
2536 assert(left->is_single_cpu(), "left must be register");
2537 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2538 assert(result->is_single_cpu(), "result must be register");
2539
2540 // assert(left->destroys_register(), "check");
2541 // assert(right->destroys_register(), "check");
2542
2543 Register lreg = left->as_register();
2544 Register dreg = result->as_register();
2545
2546 if (right->is_constant()) {
2547 int divisor = right->as_constant_ptr()->as_jint();
2548 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2549 if (code == lir_idiv) {
2550 assert(lreg == rax, "must be rax,");
2551 assert(temp->as_register() == rdx, "tmp register must be rdx");
2552 __ cdql(); // sign extend into rdx:rax
2553 if (divisor == 2) {
2554 __ subl(lreg, rdx);
2555 } else {
2556 __ andl(rdx, divisor - 1);
2557 __ addl(lreg, rdx);
2558 }
2559 __ sarl(lreg, log2_intptr(divisor));
2560 move_regs(lreg, dreg);
2561 } else if (code == lir_irem) {
2562 Label done;
2563 __ mov(dreg, lreg);
2564 __ andl(dreg, 0x80000000 | (divisor - 1));
2565 __ jcc(Assembler::positive, done);
2566 __ decrement(dreg);
2567 __ orl(dreg, ~(divisor - 1));
2568 __ increment(dreg);
2569 __ bind(done);
2570 } else {
2571 ShouldNotReachHere();
2572 }
2573 } else {
2574 Register rreg = right->as_register();
2575 assert(lreg == rax, "left register must be rax,");
2576 assert(rreg != rdx, "right register must not be rdx");
2577 assert(temp->as_register() == rdx, "tmp register must be rdx");
2578
2579 move_regs(lreg, rax);
2580
2581 int idivl_offset = __ corrected_idivl(rreg);
2582 if (ImplicitDiv0Checks) {
2583 add_debug_info_for_div0(idivl_offset, info);
2584 }
2585 if (code == lir_irem) {
2586 move_regs(rdx, dreg); // result is in rdx
2587 } else {
2588 move_regs(rax, dreg);
2589 }
2590 }
2591 }
2592
2593
2594 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2595 if (opr1->is_single_cpu()) {
2596 Register reg1 = opr1->as_register();
2597 if (opr2->is_single_cpu()) {
2598 // cpu register - cpu register
2599 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2600 __ cmpoop(reg1, opr2->as_register());
2601 } else {
2602 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2603 __ cmpl(reg1, opr2->as_register());
2604 }
2605 } else if (opr2->is_stack()) {
2606 // cpu register - stack
2607 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2608 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2609 } else {
2610 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2611 }
2612 } else if (opr2->is_constant()) {
2613 // cpu register - constant
2614 LIR_Const* c = opr2->as_constant_ptr();
2615 if (c->type() == T_INT) {
2616 __ cmpl(reg1, c->as_jint());
2617 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2618 // In 64bit oops are single register
2619 jobject o = c->as_jobject();
2620 if (o == NULL) {
2621 __ cmpptr(reg1, (int32_t)NULL_WORD);
2622 } else {
2623 __ cmpoop(reg1, o);
2624 }
2625 } else {
2626 fatal("unexpected type: %s", basictype_to_str(c->type()));
2627 }
2628 // cpu register - address
2629 } else if (opr2->is_address()) {
2630 if (op->info() != NULL) {
2631 add_debug_info_for_null_check_here(op->info());
2632 }
2633 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2634 } else {
2635 ShouldNotReachHere();
2636 }
2637
2638 } else if(opr1->is_double_cpu()) {
2639 Register xlo = opr1->as_register_lo();
2640 Register xhi = opr1->as_register_hi();
2641 if (opr2->is_double_cpu()) {
2642 #ifdef _LP64
2643 __ cmpptr(xlo, opr2->as_register_lo());
2644 #else
2645 // cpu register - cpu register
2646 Register ylo = opr2->as_register_lo();
2647 Register yhi = opr2->as_register_hi();
2648 __ subl(xlo, ylo);
2649 __ sbbl(xhi, yhi);
2650 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2651 __ orl(xhi, xlo);
2652 }
2653 #endif // _LP64
2654 } else if (opr2->is_constant()) {
2655 // cpu register - constant 0
2656 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2657 #ifdef _LP64
2658 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2659 #else
2660 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2661 __ orl(xhi, xlo);
2662 #endif // _LP64
2663 } else {
2664 ShouldNotReachHere();
2665 }
2666
2667 } else if (opr1->is_single_xmm()) {
2668 XMMRegister reg1 = opr1->as_xmm_float_reg();
2669 if (opr2->is_single_xmm()) {
2670 // xmm register - xmm register
2671 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2672 } else if (opr2->is_stack()) {
2673 // xmm register - stack
2674 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2675 } else if (opr2->is_constant()) {
2676 // xmm register - constant
2677 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2678 } else if (opr2->is_address()) {
2679 // xmm register - address
2680 if (op->info() != NULL) {
2681 add_debug_info_for_null_check_here(op->info());
2682 }
2683 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2684 } else {
2685 ShouldNotReachHere();
2686 }
2687
2688 } else if (opr1->is_double_xmm()) {
2689 XMMRegister reg1 = opr1->as_xmm_double_reg();
2690 if (opr2->is_double_xmm()) {
2691 // xmm register - xmm register
2692 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2693 } else if (opr2->is_stack()) {
2694 // xmm register - stack
2695 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2696 } else if (opr2->is_constant()) {
2697 // xmm register - constant
2698 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2699 } else if (opr2->is_address()) {
2700 // xmm register - address
2701 if (op->info() != NULL) {
2702 add_debug_info_for_null_check_here(op->info());
2703 }
2704 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2705 } else {
2706 ShouldNotReachHere();
2707 }
2708
2709 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2710 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2711 assert(opr2->is_fpu_register(), "both must be registers");
2712 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2713
2714 } else if (opr1->is_address() && opr2->is_constant()) {
2715 LIR_Const* c = opr2->as_constant_ptr();
2716 #ifdef _LP64
2717 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2718 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2719 __ movoop(rscratch1, c->as_jobject());
2720 }
2721 #endif // LP64
2722 if (op->info() != NULL) {
2723 add_debug_info_for_null_check_here(op->info());
2724 }
2725 // special case: address - constant
2726 LIR_Address* addr = opr1->as_address_ptr();
2727 if (c->type() == T_INT) {
2728 __ cmpl(as_Address(addr), c->as_jint());
2729 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2730 #ifdef _LP64
2731 // %%% Make this explode if addr isn't reachable until we figure out a
2732 // better strategy by giving noreg as the temp for as_Address
2733 __ cmpoop(rscratch1, as_Address(addr, noreg));
2734 #else
2735 __ cmpoop(as_Address(addr), c->as_jobject());
2736 #endif // _LP64
2737 } else {
2738 ShouldNotReachHere();
2739 }
2740
2741 } else {
2742 ShouldNotReachHere();
2743 }
2744 }
2745
2746 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2747 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2748 if (left->is_single_xmm()) {
2749 assert(right->is_single_xmm(), "must match");
2750 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2751 } else if (left->is_double_xmm()) {
2752 assert(right->is_double_xmm(), "must match");
2753 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2754
2755 } else {
2756 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2757 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2758
2759 assert(left->fpu() == 0, "left must be on TOS");
2760 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2761 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2762 }
2763 } else {
2764 assert(code == lir_cmp_l2i, "check");
2765 #ifdef _LP64
2766 Label done;
2767 Register dest = dst->as_register();
2768 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2769 __ movl(dest, -1);
2770 __ jccb(Assembler::less, done);
2771 __ set_byte_if_not_zero(dest);
2772 __ movzbl(dest, dest);
2773 __ bind(done);
2774 #else
2775 __ lcmp2int(left->as_register_hi(),
2776 left->as_register_lo(),
2777 right->as_register_hi(),
2778 right->as_register_lo());
2779 move_regs(left->as_register_hi(), dst->as_register());
2780 #endif // _LP64
2781 }
2782 }
2783
2784
2785 void LIR_Assembler::align_call(LIR_Code code) {
2786 if (os::is_MP()) {
2787 // make sure that the displacement word of the call ends up word aligned
2788 int offset = __ offset();
2789 switch (code) {
2790 case lir_static_call:
2791 case lir_optvirtual_call:
2792 case lir_dynamic_call:
2793 offset += NativeCall::displacement_offset;
2794 break;
2795 case lir_icvirtual_call:
2796 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2797 break;
2798 case lir_virtual_call: // currently, sparc-specific for niagara
2799 default: ShouldNotReachHere();
2800 }
2801 __ align(BytesPerWord, offset);
2802 }
2803 }
2804
2805
2806 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2807 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2808 "must be aligned");
2809 __ call(AddressLiteral(op->addr(), rtype));
2810 add_call_info(code_offset(), op->info());
2811 }
2812
2813
2814 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2815 __ ic_call(op->addr());
2816 add_call_info(code_offset(), op->info());
2817 assert(!os::is_MP() ||
2818 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2819 "must be aligned");
2820 }
2821
2822
2823 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2824 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2825 ShouldNotReachHere();
2826 }
2827
2828
2829 void LIR_Assembler::emit_static_call_stub() {
2830 address call_pc = __ pc();
2831 address stub = __ start_a_stub(call_stub_size());
2832 if (stub == NULL) {
2833 bailout("static call stub overflow");
2834 return;
2835 }
2836
2837 int start = __ offset();
2838 if (os::is_MP()) {
2839 // make sure that the displacement word of the call ends up word aligned
2840 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2841 }
2842 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2843 __ mov_metadata(rbx, (Metadata*)NULL);
2844 // must be set to -1 at code generation time
2845 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2846 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2847 __ jump(RuntimeAddress(__ pc()));
2848
2849 if (UseAOT) {
2850 // Trampoline to aot code
2851 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2852 #ifdef _LP64
2853 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2854 #else
2855 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2856 #endif
2857 __ jmp(rax);
2858 }
2859 assert(__ offset() - start <= call_stub_size(), "stub too big");
2860 __ end_a_stub();
2861 }
2862
2863
2864 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2865 assert(exceptionOop->as_register() == rax, "must match");
2866 assert(exceptionPC->as_register() == rdx, "must match");
2867
2868 // exception object is not added to oop map by LinearScan
2869 // (LinearScan assumes that no oops are in fixed registers)
2870 info->add_register_oop(exceptionOop);
2871 Runtime1::StubID unwind_id;
2872
2873 // get current pc information
2874 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2875 int pc_for_athrow_offset = __ offset();
2876 InternalAddress pc_for_athrow(__ pc());
2877 __ lea(exceptionPC->as_register(), pc_for_athrow);
2878 add_call_info(pc_for_athrow_offset, info); // for exception handler
2879
2880 __ verify_not_null_oop(rax);
2881 // search an exception handler (rax: exception oop, rdx: throwing pc)
2882 if (compilation()->has_fpu_code()) {
2883 unwind_id = Runtime1::handle_exception_id;
2884 } else {
2885 unwind_id = Runtime1::handle_exception_nofpu_id;
2886 }
2887 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2888
2889 // enough room for two byte trap
2890 __ nop();
2891 }
2892
2893
2894 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2895 assert(exceptionOop->as_register() == rax, "must match");
2896
2897 __ jmp(_unwind_handler_entry);
2898 }
2899
2900
2901 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2902
2903 // optimized version for linear scan:
2904 // * count must be already in ECX (guaranteed by LinearScan)
2905 // * left and dest must be equal
2906 // * tmp must be unused
2907 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2908 assert(left == dest, "left and dest must be equal");
2909 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2910
2911 if (left->is_single_cpu()) {
2912 Register value = left->as_register();
2913 assert(value != SHIFT_count, "left cannot be ECX");
2914
2915 switch (code) {
2916 case lir_shl: __ shll(value); break;
2917 case lir_shr: __ sarl(value); break;
2918 case lir_ushr: __ shrl(value); break;
2919 default: ShouldNotReachHere();
2920 }
2921 } else if (left->is_double_cpu()) {
2922 Register lo = left->as_register_lo();
2923 Register hi = left->as_register_hi();
2924 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2925 #ifdef _LP64
2926 switch (code) {
2927 case lir_shl: __ shlptr(lo); break;
2928 case lir_shr: __ sarptr(lo); break;
2929 case lir_ushr: __ shrptr(lo); break;
2930 default: ShouldNotReachHere();
2931 }
2932 #else
2933
2934 switch (code) {
2935 case lir_shl: __ lshl(hi, lo); break;
2936 case lir_shr: __ lshr(hi, lo, true); break;
2937 case lir_ushr: __ lshr(hi, lo, false); break;
2938 default: ShouldNotReachHere();
2939 }
2940 #endif // LP64
2941 } else {
2942 ShouldNotReachHere();
2943 }
2944 }
2945
2946
2947 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2948 if (dest->is_single_cpu()) {
2949 // first move left into dest so that left is not destroyed by the shift
2950 Register value = dest->as_register();
2951 count = count & 0x1F; // Java spec
2952
2953 move_regs(left->as_register(), value);
2954 switch (code) {
2955 case lir_shl: __ shll(value, count); break;
2956 case lir_shr: __ sarl(value, count); break;
2957 case lir_ushr: __ shrl(value, count); break;
2958 default: ShouldNotReachHere();
2959 }
2960 } else if (dest->is_double_cpu()) {
2961 #ifndef _LP64
2962 Unimplemented();
2963 #else
2964 // first move left into dest so that left is not destroyed by the shift
2965 Register value = dest->as_register_lo();
2966 count = count & 0x1F; // Java spec
2967
2968 move_regs(left->as_register_lo(), value);
2969 switch (code) {
2970 case lir_shl: __ shlptr(value, count); break;
2971 case lir_shr: __ sarptr(value, count); break;
2972 case lir_ushr: __ shrptr(value, count); break;
2973 default: ShouldNotReachHere();
2974 }
2975 #endif // _LP64
2976 } else {
2977 ShouldNotReachHere();
2978 }
2979 }
2980
2981
2982 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2983 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2984 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2985 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2986 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2987 }
2988
2989
2990 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2991 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2992 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2993 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2994 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2995 }
2996
2997
2998 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2999 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3000 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3001 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3002 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3003 }
3004
3005
3006 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3007 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3008 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3009 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3010 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3011 }
3012
3013
3014 // This code replaces a call to arraycopy; no exception may
3015 // be thrown in this code, they must be thrown in the System.arraycopy
3016 // activation frame; we could save some checks if this would not be the case
3017 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3018 ciArrayKlass* default_type = op->expected_type();
3019 Register src = op->src()->as_register();
3020 Register dst = op->dst()->as_register();
3021 Register src_pos = op->src_pos()->as_register();
3022 Register dst_pos = op->dst_pos()->as_register();
3023 Register length = op->length()->as_register();
3024 Register tmp = op->tmp()->as_register();
3025
3026 CodeStub* stub = op->stub();
3027 int flags = op->flags();
3028 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3029 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3030
3031 // if we don't know anything, just go through the generic arraycopy
3032 if (default_type == NULL) {
3033 Label done;
3034 // save outgoing arguments on stack in case call to System.arraycopy is needed
3035 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3036 // for interpreter calling conventions. Now we have to do it in new style conventions.
3037 // For the moment until C1 gets the new register allocator I just force all the
3038 // args to the right place (except the register args) and then on the back side
3039 // reload the register args properly if we go slow path. Yuck
3040
3041 // These are proper for the calling convention
3042 store_parameter(length, 2);
3043 store_parameter(dst_pos, 1);
3044 store_parameter(dst, 0);
3045
3046 // these are just temporary placements until we need to reload
3047 store_parameter(src_pos, 3);
3048 store_parameter(src, 4);
3049 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3050
3051 address copyfunc_addr = StubRoutines::generic_arraycopy();
3052 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3053
3054 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3055 #ifdef _LP64
3056 // The arguments are in java calling convention so we can trivially shift them to C
3057 // convention
3058 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3059 __ mov(c_rarg0, j_rarg0);
3060 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3061 __ mov(c_rarg1, j_rarg1);
3062 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3063 __ mov(c_rarg2, j_rarg2);
3064 assert_different_registers(c_rarg3, j_rarg4);
3065 __ mov(c_rarg3, j_rarg3);
3066 #ifdef _WIN64
3067 // Allocate abi space for args but be sure to keep stack aligned
3068 __ subptr(rsp, 6*wordSize);
3069 store_parameter(j_rarg4, 4);
3070 #ifndef PRODUCT
3071 if (PrintC1Statistics) {
3072 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3073 }
3074 #endif
3075 __ call(RuntimeAddress(copyfunc_addr));
3076 __ addptr(rsp, 6*wordSize);
3077 #else
3078 __ mov(c_rarg4, j_rarg4);
3079 #ifndef PRODUCT
3080 if (PrintC1Statistics) {
3081 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3082 }
3083 #endif
3084 __ call(RuntimeAddress(copyfunc_addr));
3085 #endif // _WIN64
3086 #else
3087 __ push(length);
3088 __ push(dst_pos);
3089 __ push(dst);
3090 __ push(src_pos);
3091 __ push(src);
3092
3093 #ifndef PRODUCT
3094 if (PrintC1Statistics) {
3095 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3096 }
3097 #endif
3098 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3099
3100 #endif // _LP64
3101
3102 __ cmpl(rax, 0);
3103 __ jcc(Assembler::equal, *stub->continuation());
3104
3105 __ mov(tmp, rax);
3106 __ xorl(tmp, -1);
3107
3108 // Reload values from the stack so they are where the stub
3109 // expects them.
3110 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3111 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3112 __ movptr (length, Address(rsp, 2*BytesPerWord));
3113 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3114 __ movptr (src, Address(rsp, 4*BytesPerWord));
3115
3116 __ subl(length, tmp);
3117 __ addl(src_pos, tmp);
3118 __ addl(dst_pos, tmp);
3119 __ jmp(*stub->entry());
3120
3121 __ bind(*stub->continuation());
3122 return;
3123 }
3124
3125 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3126
3127 int elem_size = type2aelembytes(basic_type);
3128 Address::ScaleFactor scale;
3129
3130 switch (elem_size) {
3131 case 1 :
3132 scale = Address::times_1;
3133 break;
3134 case 2 :
3135 scale = Address::times_2;
3136 break;
3137 case 4 :
3138 scale = Address::times_4;
3139 break;
3140 case 8 :
3141 scale = Address::times_8;
3142 break;
3143 default:
3144 scale = Address::no_scale;
3145 ShouldNotReachHere();
3146 }
3147
3148 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3149 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3150 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3151 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3152
3153 // length and pos's are all sign extended at this point on 64bit
3154
3155 // test for NULL
3156 if (flags & LIR_OpArrayCopy::src_null_check) {
3157 __ testptr(src, src);
3158 __ jcc(Assembler::zero, *stub->entry());
3159 }
3160 if (flags & LIR_OpArrayCopy::dst_null_check) {
3161 __ testptr(dst, dst);
3162 __ jcc(Assembler::zero, *stub->entry());
3163 }
3164
3165 // If the compiler was not able to prove that exact type of the source or the destination
3166 // of the arraycopy is an array type, check at runtime if the source or the destination is
3167 // an instance type.
3168 if (flags & LIR_OpArrayCopy::type_check) {
3169 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3170 __ load_klass(tmp, dst);
3171 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3172 __ jcc(Assembler::greaterEqual, *stub->entry());
3173 }
3174
3175 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3176 __ load_klass(tmp, src);
3177 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3178 __ jcc(Assembler::greaterEqual, *stub->entry());
3179 }
3180 }
3181
3182 // check if negative
3183 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3184 __ testl(src_pos, src_pos);
3185 __ jcc(Assembler::less, *stub->entry());
3186 }
3187 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3188 __ testl(dst_pos, dst_pos);
3189 __ jcc(Assembler::less, *stub->entry());
3190 }
3191
3192 if (flags & LIR_OpArrayCopy::src_range_check) {
3193 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3194 __ cmpl(tmp, src_length_addr);
3195 __ jcc(Assembler::above, *stub->entry());
3196 }
3197 if (flags & LIR_OpArrayCopy::dst_range_check) {
3198 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3199 __ cmpl(tmp, dst_length_addr);
3200 __ jcc(Assembler::above, *stub->entry());
3201 }
3202
3203 if (flags & LIR_OpArrayCopy::length_positive_check) {
3204 __ testl(length, length);
3205 __ jcc(Assembler::less, *stub->entry());
3206 }
3207
3208 #ifdef _LP64
3209 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3210 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3211 #endif
3212
3213 if (flags & LIR_OpArrayCopy::type_check) {
3214 // We don't know the array types are compatible
3215 if (basic_type != T_OBJECT) {
3216 // Simple test for basic type arrays
3217 if (UseCompressedClassPointers) {
3218 __ movl(tmp, src_klass_addr);
3219 __ cmpl(tmp, dst_klass_addr);
3220 } else {
3221 __ movptr(tmp, src_klass_addr);
3222 __ cmpptr(tmp, dst_klass_addr);
3223 }
3224 __ jcc(Assembler::notEqual, *stub->entry());
3225 } else {
3226 // For object arrays, if src is a sub class of dst then we can
3227 // safely do the copy.
3228 Label cont, slow;
3229
3230 __ push(src);
3231 __ push(dst);
3232
3233 __ load_klass(src, src);
3234 __ load_klass(dst, dst);
3235
3236 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3237
3238 __ push(src);
3239 __ push(dst);
3240 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3241 __ pop(dst);
3242 __ pop(src);
3243
3244 __ cmpl(src, 0);
3245 __ jcc(Assembler::notEqual, cont);
3246
3247 __ bind(slow);
3248 __ pop(dst);
3249 __ pop(src);
3250
3251 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3252 if (copyfunc_addr != NULL) { // use stub if available
3253 // src is not a sub class of dst so we have to do a
3254 // per-element check.
3255
3256 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3257 if ((flags & mask) != mask) {
3258 // Check that at least both of them object arrays.
3259 assert(flags & mask, "one of the two should be known to be an object array");
3260
3261 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3262 __ load_klass(tmp, src);
3263 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3264 __ load_klass(tmp, dst);
3265 }
3266 int lh_offset = in_bytes(Klass::layout_helper_offset());
3267 Address klass_lh_addr(tmp, lh_offset);
3268 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3269 __ cmpl(klass_lh_addr, objArray_lh);
3270 __ jcc(Assembler::notEqual, *stub->entry());
3271 }
3272
3273 // Spill because stubs can use any register they like and it's
3274 // easier to restore just those that we care about.
3275 store_parameter(dst, 0);
3276 store_parameter(dst_pos, 1);
3277 store_parameter(length, 2);
3278 store_parameter(src_pos, 3);
3279 store_parameter(src, 4);
3280
3281 #ifndef _LP64
3282 __ movptr(tmp, dst_klass_addr);
3283 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3284 __ push(tmp);
3285 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3286 __ push(tmp);
3287 __ push(length);
3288 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3289 __ push(tmp);
3290 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3291 __ push(tmp);
3292
3293 __ call_VM_leaf(copyfunc_addr, 5);
3294 #else
3295 __ movl2ptr(length, length); //higher 32bits must be null
3296
3297 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3298 assert_different_registers(c_rarg0, dst, dst_pos, length);
3299 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3300 assert_different_registers(c_rarg1, dst, length);
3301
3302 __ mov(c_rarg2, length);
3303 assert_different_registers(c_rarg2, dst);
3304
3305 #ifdef _WIN64
3306 // Allocate abi space for args but be sure to keep stack aligned
3307 __ subptr(rsp, 6*wordSize);
3308 __ load_klass(c_rarg3, dst);
3309 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3310 store_parameter(c_rarg3, 4);
3311 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3312 __ call(RuntimeAddress(copyfunc_addr));
3313 __ addptr(rsp, 6*wordSize);
3314 #else
3315 __ load_klass(c_rarg4, dst);
3316 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3317 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3318 __ call(RuntimeAddress(copyfunc_addr));
3319 #endif
3320
3321 #endif
3322
3323 #ifndef PRODUCT
3324 if (PrintC1Statistics) {
3325 Label failed;
3326 __ testl(rax, rax);
3327 __ jcc(Assembler::notZero, failed);
3328 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3329 __ bind(failed);
3330 }
3331 #endif
3332
3333 __ testl(rax, rax);
3334 __ jcc(Assembler::zero, *stub->continuation());
3335
3336 #ifndef PRODUCT
3337 if (PrintC1Statistics) {
3338 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3339 }
3340 #endif
3341
3342 __ mov(tmp, rax);
3343
3344 __ xorl(tmp, -1);
3345
3346 // Restore previously spilled arguments
3347 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3348 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3349 __ movptr (length, Address(rsp, 2*BytesPerWord));
3350 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3351 __ movptr (src, Address(rsp, 4*BytesPerWord));
3352
3353
3354 __ subl(length, tmp);
3355 __ addl(src_pos, tmp);
3356 __ addl(dst_pos, tmp);
3357 }
3358
3359 __ jmp(*stub->entry());
3360
3361 __ bind(cont);
3362 __ pop(dst);
3363 __ pop(src);
3364 }
3365 }
3366
3367 #ifdef ASSERT
3368 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3369 // Sanity check the known type with the incoming class. For the
3370 // primitive case the types must match exactly with src.klass and
3371 // dst.klass each exactly matching the default type. For the
3372 // object array case, if no type check is needed then either the
3373 // dst type is exactly the expected type and the src type is a
3374 // subtype which we can't check or src is the same array as dst
3375 // but not necessarily exactly of type default_type.
3376 Label known_ok, halt;
3377 __ mov_metadata(tmp, default_type->constant_encoding());
3378 #ifdef _LP64
3379 if (UseCompressedClassPointers) {
3380 __ encode_klass_not_null(tmp);
3381 }
3382 #endif
3383
3384 if (basic_type != T_OBJECT) {
3385
3386 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3387 else __ cmpptr(tmp, dst_klass_addr);
3388 __ jcc(Assembler::notEqual, halt);
3389 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3390 else __ cmpptr(tmp, src_klass_addr);
3391 __ jcc(Assembler::equal, known_ok);
3392 } else {
3393 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3394 else __ cmpptr(tmp, dst_klass_addr);
3395 __ jcc(Assembler::equal, known_ok);
3396 __ cmpptr(src, dst);
3397 __ jcc(Assembler::equal, known_ok);
3398 }
3399 __ bind(halt);
3400 __ stop("incorrect type information in arraycopy");
3401 __ bind(known_ok);
3402 }
3403 #endif
3404
3405 #ifndef PRODUCT
3406 if (PrintC1Statistics) {
3407 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3408 }
3409 #endif
3410
3411 #ifdef _LP64
3412 assert_different_registers(c_rarg0, dst, dst_pos, length);
3413 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3414 assert_different_registers(c_rarg1, length);
3415 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3416 __ mov(c_rarg2, length);
3417
3418 #else
3419 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3420 store_parameter(tmp, 0);
3421 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3422 store_parameter(tmp, 1);
3423 store_parameter(length, 2);
3424 #endif // _LP64
3425
3426 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3427 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3428 const char *name;
3429 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3430 __ call_VM_leaf(entry, 0);
3431
3432 __ bind(*stub->continuation());
3433 }
3434
3435 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3436 assert(op->crc()->is_single_cpu(), "crc must be register");
3437 assert(op->val()->is_single_cpu(), "byte value must be register");
3438 assert(op->result_opr()->is_single_cpu(), "result must be register");
3439 Register crc = op->crc()->as_register();
3440 Register val = op->val()->as_register();
3441 Register res = op->result_opr()->as_register();
3442
3443 assert_different_registers(val, crc, res);
3444
3445 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3446 __ notl(crc); // ~crc
3447 __ update_byte_crc32(crc, val, res);
3448 __ notl(crc); // ~crc
3449 __ mov(res, crc);
3450 }
3451
3452 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3453 Register obj = op->obj_opr()->as_register(); // may not be an oop
3454 Register hdr = op->hdr_opr()->as_register();
3455 Register lock = op->lock_opr()->as_register();
3456 if (!UseFastLocking) {
3457 __ jmp(*op->stub()->entry());
3458 } else if (op->code() == lir_lock) {
3459 Register scratch = noreg;
3460 if (UseBiasedLocking) {
3461 scratch = op->scratch_opr()->as_register();
3462 }
3463 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3464 // add debug info for NullPointerException only if one is possible
3465 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3466 if (op->info() != NULL) {
3467 add_debug_info_for_null_check(null_check_offset, op->info());
3468 }
3469 // done
3470 } else if (op->code() == lir_unlock) {
3471 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3472 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3473 } else {
3474 Unimplemented();
3475 }
3476 __ bind(*op->stub()->continuation());
3477 }
3478
3479
3480 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3481 ciMethod* method = op->profiled_method();
3482 int bci = op->profiled_bci();
3483 ciMethod* callee = op->profiled_callee();
3484
3485 // Update counter for all call types
3486 ciMethodData* md = method->method_data_or_null();
3487 assert(md != NULL, "Sanity");
3488 ciProfileData* data = md->bci_to_data(bci);
3489 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3490 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3491 Register mdo = op->mdo()->as_register();
3492 __ mov_metadata(mdo, md->constant_encoding());
3493 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3494 // Perform additional virtual call profiling for invokevirtual and
3495 // invokeinterface bytecodes
3496 if (op->should_profile_receiver_type()) {
3497 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3498 Register recv = op->recv()->as_register();
3499 assert_different_registers(mdo, recv);
3500 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3501 ciKlass* known_klass = op->known_holder();
3502 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3503 // We know the type that will be seen at this call site; we can
3504 // statically update the MethodData* rather than needing to do
3505 // dynamic tests on the receiver type
3506
3507 // NOTE: we should probably put a lock around this search to
3508 // avoid collisions by concurrent compilations
3509 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3510 uint i;
3511 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3512 ciKlass* receiver = vc_data->receiver(i);
3513 if (known_klass->equals(receiver)) {
3514 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3515 __ addptr(data_addr, DataLayout::counter_increment);
3516 return;
3517 }
3518 }
3519
3520 // Receiver type not found in profile data; select an empty slot
3521
3522 // Note that this is less efficient than it should be because it
3523 // always does a write to the receiver part of the
3524 // VirtualCallData rather than just the first time
3525 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3526 ciKlass* receiver = vc_data->receiver(i);
3527 if (receiver == NULL) {
3528 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3529 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3530 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3531 __ addptr(data_addr, DataLayout::counter_increment);
3532 return;
3533 }
3534 }
3535 } else {
3536 __ load_klass(recv, recv);
3537 Label update_done;
3538 type_profile_helper(mdo, md, data, recv, &update_done);
3539 // Receiver did not match any saved receiver and there is no empty row for it.
3540 // Increment total counter to indicate polymorphic case.
3541 __ addptr(counter_addr, DataLayout::counter_increment);
3542
3543 __ bind(update_done);
3544 }
3545 } else {
3546 // Static call
3547 __ addptr(counter_addr, DataLayout::counter_increment);
3548 }
3549 }
3550
3551 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3552 Register obj = op->obj()->as_register();
3553 Register tmp = op->tmp()->as_pointer_register();
3554 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3555 ciKlass* exact_klass = op->exact_klass();
3556 intptr_t current_klass = op->current_klass();
3557 bool not_null = op->not_null();
3558 bool no_conflict = op->no_conflict();
3559
3560 Label update, next, none;
3561
3562 bool do_null = !not_null;
3563 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3564 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3565
3566 assert(do_null || do_update, "why are we here?");
3567 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3568
3569 __ verify_oop(obj);
3570
3571 if (tmp != obj) {
3572 __ mov(tmp, obj);
3573 }
3574 if (do_null) {
3575 __ testptr(tmp, tmp);
3576 __ jccb(Assembler::notZero, update);
3577 if (!TypeEntries::was_null_seen(current_klass)) {
3578 __ orptr(mdo_addr, TypeEntries::null_seen);
3579 }
3580 if (do_update) {
3581 #ifndef ASSERT
3582 __ jmpb(next);
3583 }
3584 #else
3585 __ jmp(next);
3586 }
3587 } else {
3588 __ testptr(tmp, tmp);
3589 __ jccb(Assembler::notZero, update);
3590 __ stop("unexpect null obj");
3591 #endif
3592 }
3593
3594 __ bind(update);
3595
3596 if (do_update) {
3597 #ifdef ASSERT
3598 if (exact_klass != NULL) {
3599 Label ok;
3600 __ load_klass(tmp, tmp);
3601 __ push(tmp);
3602 __ mov_metadata(tmp, exact_klass->constant_encoding());
3603 __ cmpptr(tmp, Address(rsp, 0));
3604 __ jccb(Assembler::equal, ok);
3605 __ stop("exact klass and actual klass differ");
3606 __ bind(ok);
3607 __ pop(tmp);
3608 }
3609 #endif
3610 if (!no_conflict) {
3611 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3612 if (exact_klass != NULL) {
3613 __ mov_metadata(tmp, exact_klass->constant_encoding());
3614 } else {
3615 __ load_klass(tmp, tmp);
3616 }
3617
3618 __ xorptr(tmp, mdo_addr);
3619 __ testptr(tmp, TypeEntries::type_klass_mask);
3620 // klass seen before, nothing to do. The unknown bit may have been
3621 // set already but no need to check.
3622 __ jccb(Assembler::zero, next);
3623
3624 __ testptr(tmp, TypeEntries::type_unknown);
3625 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3626
3627 if (TypeEntries::is_type_none(current_klass)) {
3628 __ cmpptr(mdo_addr, 0);
3629 __ jccb(Assembler::equal, none);
3630 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3631 __ jccb(Assembler::equal, none);
3632 // There is a chance that the checks above (re-reading profiling
3633 // data from memory) fail if another thread has just set the
3634 // profiling to this obj's klass
3635 __ xorptr(tmp, mdo_addr);
3636 __ testptr(tmp, TypeEntries::type_klass_mask);
3637 __ jccb(Assembler::zero, next);
3638 }
3639 } else {
3640 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3641 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3642
3643 __ movptr(tmp, mdo_addr);
3644 __ testptr(tmp, TypeEntries::type_unknown);
3645 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3646 }
3647
3648 // different than before. Cannot keep accurate profile.
3649 __ orptr(mdo_addr, TypeEntries::type_unknown);
3650
3651 if (TypeEntries::is_type_none(current_klass)) {
3652 __ jmpb(next);
3653
3654 __ bind(none);
3655 // first time here. Set profile type.
3656 __ movptr(mdo_addr, tmp);
3657 }
3658 } else {
3659 // There's a single possible klass at this profile point
3660 assert(exact_klass != NULL, "should be");
3661 if (TypeEntries::is_type_none(current_klass)) {
3662 __ mov_metadata(tmp, exact_klass->constant_encoding());
3663 __ xorptr(tmp, mdo_addr);
3664 __ testptr(tmp, TypeEntries::type_klass_mask);
3665 #ifdef ASSERT
3666 __ jcc(Assembler::zero, next);
3667
3668 {
3669 Label ok;
3670 __ push(tmp);
3671 __ cmpptr(mdo_addr, 0);
3672 __ jcc(Assembler::equal, ok);
3673 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3674 __ jcc(Assembler::equal, ok);
3675 // may have been set by another thread
3676 __ mov_metadata(tmp, exact_klass->constant_encoding());
3677 __ xorptr(tmp, mdo_addr);
3678 __ testptr(tmp, TypeEntries::type_mask);
3679 __ jcc(Assembler::zero, ok);
3680
3681 __ stop("unexpected profiling mismatch");
3682 __ bind(ok);
3683 __ pop(tmp);
3684 }
3685 #else
3686 __ jccb(Assembler::zero, next);
3687 #endif
3688 // first time here. Set profile type.
3689 __ movptr(mdo_addr, tmp);
3690 } else {
3691 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3692 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3693
3694 __ movptr(tmp, mdo_addr);
3695 __ testptr(tmp, TypeEntries::type_unknown);
3696 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3697
3698 __ orptr(mdo_addr, TypeEntries::type_unknown);
3699 }
3700 }
3701
3702 __ bind(next);
3703 }
3704 }
3705
3706 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3707 Unimplemented();
3708 }
3709
3710
3711 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3712 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3713 }
3714
3715
3716 void LIR_Assembler::align_backward_branch_target() {
3717 __ align(BytesPerWord);
3718 }
3719
3720
3721 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3722 if (left->is_single_cpu()) {
3723 __ negl(left->as_register());
3724 move_regs(left->as_register(), dest->as_register());
3725
3726 } else if (left->is_double_cpu()) {
3727 Register lo = left->as_register_lo();
3728 #ifdef _LP64
3729 Register dst = dest->as_register_lo();
3730 __ movptr(dst, lo);
3731 __ negptr(dst);
3732 #else
3733 Register hi = left->as_register_hi();
3734 __ lneg(hi, lo);
3735 if (dest->as_register_lo() == hi) {
3736 assert(dest->as_register_hi() != lo, "destroying register");
3737 move_regs(hi, dest->as_register_hi());
3738 move_regs(lo, dest->as_register_lo());
3739 } else {
3740 move_regs(lo, dest->as_register_lo());
3741 move_regs(hi, dest->as_register_hi());
3742 }
3743 #endif // _LP64
3744
3745 } else if (dest->is_single_xmm()) {
3746 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3747 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3748 }
3749 if (UseAVX > 0) {
3750 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3751 ExternalAddress((address)float_signflip_pool));
3752 } else {
3753 __ xorps(dest->as_xmm_float_reg(),
3754 ExternalAddress((address)float_signflip_pool));
3755 }
3756 } else if (dest->is_double_xmm()) {
3757 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3758 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3759 }
3760 if (UseAVX > 0) {
3761 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3762 ExternalAddress((address)double_signflip_pool));
3763 } else {
3764 __ xorpd(dest->as_xmm_double_reg(),
3765 ExternalAddress((address)double_signflip_pool));
3766 }
3767 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3768 assert(left->fpu() == 0, "arg must be on TOS");
3769 assert(dest->fpu() == 0, "dest must be TOS");
3770 __ fchs();
3771
3772 } else {
3773 ShouldNotReachHere();
3774 }
3775 }
3776
3777
3778 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3779 assert(src->is_address(), "must be an address");
3780 assert(dest->is_register(), "must be a register");
3781
3782 PatchingStub* patch = NULL;
3783 if (patch_code != lir_patch_none) {
3784 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3785 }
3786
3787 Register reg = dest->as_pointer_register();
3788 LIR_Address* addr = src->as_address_ptr();
3789 __ lea(reg, as_Address(addr));
3790
3791 if (patch != NULL) {
3792 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3793 }
3794 }
3795
3796
3797
3798 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3799 assert(!tmp->is_valid(), "don't need temporary");
3800 __ call(RuntimeAddress(dest));
3801 if (info != NULL) {
3802 add_call_info_here(info);
3803 }
3804 }
3805
3806
3807 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3808 assert(type == T_LONG, "only for volatile long fields");
3809
3810 if (info != NULL) {
3811 add_debug_info_for_null_check_here(info);
3812 }
3813
3814 if (src->is_double_xmm()) {
3815 if (dest->is_double_cpu()) {
3816 #ifdef _LP64
3817 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3818 #else
3819 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3820 __ psrlq(src->as_xmm_double_reg(), 32);
3821 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3822 #endif // _LP64
3823 } else if (dest->is_double_stack()) {
3824 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3825 } else if (dest->is_address()) {
3826 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3827 } else {
3828 ShouldNotReachHere();
3829 }
3830
3831 } else if (dest->is_double_xmm()) {
3832 if (src->is_double_stack()) {
3833 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3834 } else if (src->is_address()) {
3835 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3836 } else {
3837 ShouldNotReachHere();
3838 }
3839
3840 } else if (src->is_double_fpu()) {
3841 assert(src->fpu_regnrLo() == 0, "must be TOS");
3842 if (dest->is_double_stack()) {
3843 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3844 } else if (dest->is_address()) {
3845 __ fistp_d(as_Address(dest->as_address_ptr()));
3846 } else {
3847 ShouldNotReachHere();
3848 }
3849
3850 } else if (dest->is_double_fpu()) {
3851 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3852 if (src->is_double_stack()) {
3853 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3854 } else if (src->is_address()) {
3855 __ fild_d(as_Address(src->as_address_ptr()));
3856 } else {
3857 ShouldNotReachHere();
3858 }
3859 } else {
3860 ShouldNotReachHere();
3861 }
3862 }
3863
3864 #ifdef ASSERT
3865 // emit run-time assertion
3866 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3867 assert(op->code() == lir_assert, "must be");
3868
3869 if (op->in_opr1()->is_valid()) {
3870 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3871 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3872 } else {
3873 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3874 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3875 }
3876
3877 Label ok;
3878 if (op->condition() != lir_cond_always) {
3879 Assembler::Condition acond = Assembler::zero;
3880 switch (op->condition()) {
3881 case lir_cond_equal: acond = Assembler::equal; break;
3882 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3883 case lir_cond_less: acond = Assembler::less; break;
3884 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3885 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3886 case lir_cond_greater: acond = Assembler::greater; break;
3887 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3888 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3889 default: ShouldNotReachHere();
3890 }
3891 __ jcc(acond, ok);
3892 }
3893 if (op->halt()) {
3894 const char* str = __ code_string(op->msg());
3895 __ stop(str);
3896 } else {
3897 breakpoint();
3898 }
3899 __ bind(ok);
3900 }
3901 #endif
3902
3903 void LIR_Assembler::membar() {
3904 // QQQ sparc TSO uses this,
3905 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3906 }
3907
3908 void LIR_Assembler::membar_acquire() {
3909 // No x86 machines currently require load fences
3910 }
3911
3912 void LIR_Assembler::membar_release() {
3913 // No x86 machines currently require store fences
3914 }
3915
3916 void LIR_Assembler::membar_loadload() {
3917 // no-op
3918 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3919 }
3920
3921 void LIR_Assembler::membar_storestore() {
3922 // no-op
3923 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3924 }
3925
3926 void LIR_Assembler::membar_loadstore() {
3927 // no-op
3928 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3929 }
3930
3931 void LIR_Assembler::membar_storeload() {
3932 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3933 }
3934
3935 void LIR_Assembler::on_spin_wait() {
3936 __ pause ();
3937 }
3938
3939 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3940 assert(result_reg->is_register(), "check");
3941 #ifdef _LP64
3942 // __ get_thread(result_reg->as_register_lo());
3943 __ mov(result_reg->as_register(), r15_thread);
3944 #else
3945 __ get_thread(result_reg->as_register());
3946 #endif // _LP64
3947 }
3948
3949
3950 void LIR_Assembler::peephole(LIR_List*) {
3951 // do nothing for now
3952 }
3953
3954 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3955 assert(data == dest, "xchg/xadd uses only 2 operands");
3956
3957 if (data->type() == T_INT) {
3958 if (code == lir_xadd) {
3959 if (os::is_MP()) {
3960 __ lock();
3961 }
3962 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3963 } else {
3964 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3965 }
3966 } else if (data->is_oop()) {
3967 assert (code == lir_xchg, "xadd for oops");
3968 Register obj = data->as_register();
3969 assert (tmp->is_register(), "should be register");
3970 __ xchg_oop(obj, as_Address(src->as_address_ptr()), tmp->as_register());
3971 } else if (data->type() == T_LONG) {
3972 #ifdef _LP64
3973 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3974 if (code == lir_xadd) {
3975 if (os::is_MP()) {
3976 __ lock();
3977 }
3978 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3979 } else {
3980 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3981 }
3982 #else
3983 ShouldNotReachHere();
3984 #endif
3985 } else {
3986 ShouldNotReachHere();
3987 }
3988 }
3989
3990 #undef __