19 * or visit www.oracle.com if you need additional information or have any
20 * questions.
21 *
22 */
23
24 #include "precompiled.hpp"
25 #include "c1/c1_LIRAssembler.hpp"
26 #include "c1/c1_MacroAssembler.hpp"
27 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
30
31 #define __ masm->masm()->
32
33 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
34 Register addr = _addr->as_register_lo();
35 Register newval = _new_value->as_register();
36 Register cmpval = _cmp_value->as_register();
37 Register tmp1 = _tmp1->as_register();
38 Register tmp2 = _tmp2->as_register();
39 Register result = result_opr()->as_register();
40
41 ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, rscratch2);
42
43 if (UseCompressedOops) {
44 __ encode_heap_oop(tmp1, cmpval);
45 cmpval = tmp1;
46 __ encode_heap_oop(tmp2, newval);
47 newval = tmp2;
48 }
49
50 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, result);
51 }
52
53 #undef __
54
55 #ifdef ASSERT
56 #define __ gen->lir(__FILE__, __LINE__)->
57 #else
58 #define __ gen->lir()->
59 #endif
60
61 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
62 BasicType bt = access.type();
63 if (access.is_oop()) {
64 LIRGenerator *gen = access.gen();
65 if (ShenandoahSATBBarrier) {
66 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
67 LIR_OprFact::illegalOpr /* pre_val */);
68 }
69 if (ShenandoahCASBarrier) {
70 cmp_value.load_item();
71 new_value.load_item();
72
73 LIR_Opr t1 = gen->new_register(T_OBJECT);
74 LIR_Opr t2 = gen->new_register(T_OBJECT);
75 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
76 LIR_Opr result = gen->new_register(T_INT);
77
78 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
79 return result;
80 }
81 }
82 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
83 }
84
85 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
86 LIRGenerator* gen = access.gen();
87 BasicType type = access.type();
88
89 LIR_Opr result = gen->new_register(type);
90 value.load_item();
91 LIR_Opr value_opr = value.result();
92
93 if (access.is_oop()) {
94 value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
95 }
96
97 assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");
98 LIR_Opr tmp = gen->new_register(T_INT);
|
19 * or visit www.oracle.com if you need additional information or have any
20 * questions.
21 *
22 */
23
24 #include "precompiled.hpp"
25 #include "c1/c1_LIRAssembler.hpp"
26 #include "c1/c1_MacroAssembler.hpp"
27 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
30
31 #define __ masm->masm()->
32
33 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
34 Register addr = _addr->as_register_lo();
35 Register newval = _new_value->as_register();
36 Register cmpval = _cmp_value->as_register();
37 Register tmp1 = _tmp1->as_register();
38 Register tmp2 = _tmp2->as_register();
39 Register tmp3 = _tmp3->as_register();
40 Register result = result_opr()->as_register();
41
42 ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, rscratch2);
43
44 if (UseCompressedOops) {
45 __ encode_heap_oop(tmp1, cmpval);
46 cmpval = tmp1;
47 __ encode_heap_oop(tmp2, newval);
48 newval = tmp2;
49 }
50
51 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, tmp3, result);
52 }
53
54 #undef __
55
56 #ifdef ASSERT
57 #define __ gen->lir(__FILE__, __LINE__)->
58 #else
59 #define __ gen->lir()->
60 #endif
61
62 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
63 BasicType bt = access.type();
64 if (access.is_oop()) {
65 LIRGenerator *gen = access.gen();
66 if (ShenandoahSATBBarrier) {
67 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
68 LIR_OprFact::illegalOpr /* pre_val */);
69 }
70 if (ShenandoahCASBarrier) {
71 cmp_value.load_item();
72 new_value.load_item();
73
74 LIR_Opr t1 = gen->new_register(T_OBJECT);
75 LIR_Opr t2 = gen->new_register(T_OBJECT);
76 LIR_Opr t3 = gen->new_register(T_OBJECT);
77 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
78 LIR_Opr result = gen->new_register(T_INT);
79
80 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, t3, result));
81 return result;
82 }
83 }
84 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
85 }
86
87 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
88 LIRGenerator* gen = access.gen();
89 BasicType type = access.type();
90
91 LIR_Opr result = gen->new_register(type);
92 value.load_item();
93 LIR_Opr value_opr = value.result();
94
95 if (access.is_oop()) {
96 value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
97 }
98
99 assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");
100 LIR_Opr tmp = gen->new_register(T_INT);
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