1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "asm/assembler.hpp" 30 #include "asm/assembler.inline.hpp" 31 #include "gc/shared/cardTable.hpp" 32 #include "gc/shared/cardTableModRefBS.hpp" 33 #include "interpreter/interpreter.hpp" 34 #include "compiler/disassembler.hpp" 35 #include "memory/resourceArea.hpp" 36 #include "nativeInst_aarch64.hpp" 37 #include "oops/klass.inline.hpp" 38 #include "oops/oop.inline.hpp" 39 #include "opto/compile.hpp" 40 #include "opto/intrinsicnode.hpp" 41 #include "opto/node.hpp" 42 #include "prims/jvm.h" 43 #include "runtime/biasedLocking.hpp" 44 #include "runtime/icache.hpp" 45 #include "runtime/interfaceSupport.hpp" 46 #include "runtime/sharedRuntime.hpp" 47 #include "runtime/thread.hpp" 48 49 #if INCLUDE_ALL_GCS 50 #include "gc/g1/g1CardTable.hpp" 51 #include "gc/g1/g1CollectedHeap.inline.hpp" 52 #include "gc/g1/g1BarrierSet.hpp" 53 #include "gc/g1/heapRegion.hpp" 54 #endif 55 56 #ifdef PRODUCT 57 #define BLOCK_COMMENT(str) /* nothing */ 58 #define STOP(error) stop(error) 59 #else 60 #define BLOCK_COMMENT(str) block_comment(str) 61 #define STOP(error) block_comment(error); stop(error) 62 #endif 63 64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 65 66 // Patch any kind of instruction; there may be several instructions. 67 // Return the total length (in bytes) of the instructions. 68 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 69 int instructions = 1; 70 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); 71 long offset = (target - branch) >> 2; 72 unsigned insn = *(unsigned*)branch; 73 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 74 // Load register (literal) 75 Instruction_aarch64::spatch(branch, 23, 5, offset); 76 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 77 // Unconditional branch (immediate) 78 Instruction_aarch64::spatch(branch, 25, 0, offset); 79 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 80 // Conditional branch (immediate) 81 Instruction_aarch64::spatch(branch, 23, 5, offset); 82 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 83 // Compare & branch (immediate) 84 Instruction_aarch64::spatch(branch, 23, 5, offset); 85 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 86 // Test & branch (immediate) 87 Instruction_aarch64::spatch(branch, 18, 5, offset); 88 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 89 // PC-rel. addressing 90 offset = target-branch; 91 int shift = Instruction_aarch64::extract(insn, 31, 31); 92 if (shift) { 93 u_int64_t dest = (u_int64_t)target; 94 uint64_t pc_page = (uint64_t)branch >> 12; 95 uint64_t adr_page = (uint64_t)target >> 12; 96 unsigned offset_lo = dest & 0xfff; 97 offset = adr_page - pc_page; 98 99 // We handle 4 types of PC relative addressing 100 // 1 - adrp Rx, target_page 101 // ldr/str Ry, [Rx, #offset_in_page] 102 // 2 - adrp Rx, target_page 103 // add Ry, Rx, #offset_in_page 104 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 105 // movk Rx, #imm16<<32 106 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 107 // In the first 3 cases we must check that Rx is the same in the adrp and the 108 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 109 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 110 // to be followed by a random unrelated ldr/str, add or movk instruction. 111 // 112 unsigned insn2 = ((unsigned*)branch)[1]; 113 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 114 Instruction_aarch64::extract(insn, 4, 0) == 115 Instruction_aarch64::extract(insn2, 9, 5)) { 116 // Load/store register (unsigned immediate) 117 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 118 Instruction_aarch64::patch(branch + sizeof (unsigned), 119 21, 10, offset_lo >> size); 120 guarantee(((dest >> size) << size) == dest, "misaligned target"); 121 instructions = 2; 122 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 123 Instruction_aarch64::extract(insn, 4, 0) == 124 Instruction_aarch64::extract(insn2, 4, 0)) { 125 // add (immediate) 126 Instruction_aarch64::patch(branch + sizeof (unsigned), 127 21, 10, offset_lo); 128 instructions = 2; 129 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 130 Instruction_aarch64::extract(insn, 4, 0) == 131 Instruction_aarch64::extract(insn2, 4, 0)) { 132 // movk #imm16<<32 133 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 134 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); 135 long pc_page = (long)branch >> 12; 136 long adr_page = (long)dest >> 12; 137 offset = adr_page - pc_page; 138 instructions = 2; 139 } 140 } 141 int offset_lo = offset & 3; 142 offset >>= 2; 143 Instruction_aarch64::spatch(branch, 23, 5, offset); 144 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 145 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 146 u_int64_t dest = (u_int64_t)target; 147 // Move wide constant 148 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 149 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 150 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 151 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 152 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 153 assert(target_addr_for_insn(branch) == target, "should be"); 154 instructions = 3; 155 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 156 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 157 // nothing to do 158 assert(target == 0, "did not expect to relocate target for polling page load"); 159 } else { 160 ShouldNotReachHere(); 161 } 162 return instructions * NativeInstruction::instruction_size; 163 } 164 165 int MacroAssembler::patch_oop(address insn_addr, address o) { 166 int instructions; 167 unsigned insn = *(unsigned*)insn_addr; 168 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 169 170 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 171 // narrow OOPs by setting the upper 16 bits in the first 172 // instruction. 173 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 174 // Move narrow OOP 175 narrowOop n = oopDesc::encode_heap_oop((oop)o); 176 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 177 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 178 instructions = 2; 179 } else { 180 // Move wide OOP 181 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 182 uintptr_t dest = (uintptr_t)o; 183 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 184 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 185 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 186 instructions = 3; 187 } 188 return instructions * NativeInstruction::instruction_size; 189 } 190 191 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) { 192 // Metatdata pointers are either narrow (32 bits) or wide (48 bits). 193 // We encode narrow ones by setting the upper 16 bits in the first 194 // instruction. 195 NativeInstruction *insn = nativeInstruction_at(insn_addr); 196 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 && 197 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 198 199 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 200 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 201 return 2 * NativeInstruction::instruction_size; 202 } 203 204 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 205 long offset = 0; 206 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 207 // Load register (literal) 208 offset = Instruction_aarch64::sextract(insn, 23, 5); 209 return address(((uint64_t)insn_addr + (offset << 2))); 210 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 211 // Unconditional branch (immediate) 212 offset = Instruction_aarch64::sextract(insn, 25, 0); 213 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 214 // Conditional branch (immediate) 215 offset = Instruction_aarch64::sextract(insn, 23, 5); 216 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 217 // Compare & branch (immediate) 218 offset = Instruction_aarch64::sextract(insn, 23, 5); 219 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 220 // Test & branch (immediate) 221 offset = Instruction_aarch64::sextract(insn, 18, 5); 222 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 223 // PC-rel. addressing 224 offset = Instruction_aarch64::extract(insn, 30, 29); 225 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 226 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 227 if (shift) { 228 offset <<= shift; 229 uint64_t target_page = ((uint64_t)insn_addr) + offset; 230 target_page &= ((uint64_t)-1) << shift; 231 // Return the target address for the following sequences 232 // 1 - adrp Rx, target_page 233 // ldr/str Ry, [Rx, #offset_in_page] 234 // 2 - adrp Rx, target_page 235 // add Ry, Rx, #offset_in_page 236 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 237 // movk Rx, #imm12<<32 238 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 239 // 240 // In the first two cases we check that the register is the same and 241 // return the target_page + the offset within the page. 242 // Otherwise we assume it is a page aligned relocation and return 243 // the target page only. 244 // 245 unsigned insn2 = ((unsigned*)insn_addr)[1]; 246 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 247 Instruction_aarch64::extract(insn, 4, 0) == 248 Instruction_aarch64::extract(insn2, 9, 5)) { 249 // Load/store register (unsigned immediate) 250 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 251 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 252 return address(target_page + (byte_offset << size)); 253 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 254 Instruction_aarch64::extract(insn, 4, 0) == 255 Instruction_aarch64::extract(insn2, 4, 0)) { 256 // add (immediate) 257 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 258 return address(target_page + byte_offset); 259 } else { 260 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 261 Instruction_aarch64::extract(insn, 4, 0) == 262 Instruction_aarch64::extract(insn2, 4, 0)) { 263 target_page = (target_page & 0xffffffff) | 264 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 265 } 266 return (address)target_page; 267 } 268 } else { 269 ShouldNotReachHere(); 270 } 271 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 272 u_int32_t *insns = (u_int32_t *)insn_addr; 273 // Move wide constant: movz, movk, movk. See movptr(). 274 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 275 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 276 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 277 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 278 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 279 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 280 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 281 return 0; 282 } else { 283 ShouldNotReachHere(); 284 } 285 return address(((uint64_t)insn_addr + (offset << 2))); 286 } 287 288 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 289 dsb(Assembler::SY); 290 } 291 292 293 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 294 // we must set sp to zero to clear frame 295 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 296 297 // must clear fp, so that compiled frames are not confused; it is 298 // possible that we need it only for debugging 299 if (clear_fp) { 300 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 301 } 302 303 // Always clear the pc because it could have been set by make_walkable() 304 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 305 } 306 307 // Calls to C land 308 // 309 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 310 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 311 // has to be reset to 0. This is required to allow proper stack traversal. 312 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 313 Register last_java_fp, 314 Register last_java_pc, 315 Register scratch) { 316 317 if (last_java_pc->is_valid()) { 318 str(last_java_pc, Address(rthread, 319 JavaThread::frame_anchor_offset() 320 + JavaFrameAnchor::last_Java_pc_offset())); 321 } 322 323 // determine last_java_sp register 324 if (last_java_sp == sp) { 325 mov(scratch, sp); 326 last_java_sp = scratch; 327 } else if (!last_java_sp->is_valid()) { 328 last_java_sp = esp; 329 } 330 331 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 332 333 // last_java_fp is optional 334 if (last_java_fp->is_valid()) { 335 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 336 } 337 } 338 339 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 340 Register last_java_fp, 341 address last_java_pc, 342 Register scratch) { 343 if (last_java_pc != NULL) { 344 adr(scratch, last_java_pc); 345 } else { 346 // FIXME: This is almost never correct. We should delete all 347 // cases of set_last_Java_frame with last_java_pc=NULL and use the 348 // correct return address instead. 349 adr(scratch, pc()); 350 } 351 352 str(scratch, Address(rthread, 353 JavaThread::frame_anchor_offset() 354 + JavaFrameAnchor::last_Java_pc_offset())); 355 356 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 357 } 358 359 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 360 Register last_java_fp, 361 Label &L, 362 Register scratch) { 363 if (L.is_bound()) { 364 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 365 } else { 366 InstructionMark im(this); 367 L.add_patch_at(code(), locator()); 368 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); 369 } 370 } 371 372 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 373 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 374 assert(CodeCache::find_blob(entry.target()) != NULL, 375 "destination of far call not found in code cache"); 376 if (far_branches()) { 377 unsigned long offset; 378 // We can use ADRP here because we know that the total size of 379 // the code cache cannot exceed 2Gb. 380 adrp(tmp, entry, offset); 381 add(tmp, tmp, offset); 382 if (cbuf) cbuf->set_insts_mark(); 383 blr(tmp); 384 } else { 385 if (cbuf) cbuf->set_insts_mark(); 386 bl(entry); 387 } 388 } 389 390 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 391 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 392 assert(CodeCache::find_blob(entry.target()) != NULL, 393 "destination of far call not found in code cache"); 394 if (far_branches()) { 395 unsigned long offset; 396 // We can use ADRP here because we know that the total size of 397 // the code cache cannot exceed 2Gb. 398 adrp(tmp, entry, offset); 399 add(tmp, tmp, offset); 400 if (cbuf) cbuf->set_insts_mark(); 401 br(tmp); 402 } else { 403 if (cbuf) cbuf->set_insts_mark(); 404 b(entry); 405 } 406 } 407 408 void MacroAssembler::reserved_stack_check() { 409 // testing if reserved zone needs to be enabled 410 Label no_reserved_zone_enabling; 411 412 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); 413 cmp(sp, rscratch1); 414 br(Assembler::LO, no_reserved_zone_enabling); 415 416 enter(); // LR and FP are live. 417 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)); 418 mov(c_rarg0, rthread); 419 blr(rscratch1); 420 leave(); 421 422 // We have already removed our own frame. 423 // throw_delayed_StackOverflowError will think that it's been 424 // called by our caller. 425 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 426 br(rscratch1); 427 should_not_reach_here(); 428 429 bind(no_reserved_zone_enabling); 430 } 431 432 int MacroAssembler::biased_locking_enter(Register lock_reg, 433 Register obj_reg, 434 Register swap_reg, 435 Register tmp_reg, 436 bool swap_reg_contains_mark, 437 Label& done, 438 Label* slow_case, 439 BiasedLockingCounters* counters) { 440 assert(UseBiasedLocking, "why call this otherwise?"); 441 assert_different_registers(lock_reg, obj_reg, swap_reg); 442 443 if (PrintBiasedLockingStatistics && counters == NULL) 444 counters = BiasedLocking::counters(); 445 446 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 447 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 448 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 449 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 450 Address saved_mark_addr(lock_reg, 0); 451 452 // Biased locking 453 // See whether the lock is currently biased toward our thread and 454 // whether the epoch is still valid 455 // Note that the runtime guarantees sufficient alignment of JavaThread 456 // pointers to allow age to be placed into low bits 457 // First check to see whether biasing is even enabled for this object 458 Label cas_label; 459 int null_check_offset = -1; 460 if (!swap_reg_contains_mark) { 461 null_check_offset = offset(); 462 ldr(swap_reg, mark_addr); 463 } 464 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); 465 cmp(tmp_reg, markOopDesc::biased_lock_pattern); 466 br(Assembler::NE, cas_label); 467 // The bias pattern is present in the object's header. Need to check 468 // whether the bias owner and the epoch are both still current. 469 load_prototype_header(tmp_reg, obj_reg); 470 orr(tmp_reg, tmp_reg, rthread); 471 eor(tmp_reg, swap_reg, tmp_reg); 472 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 473 if (counters != NULL) { 474 Label around; 475 cbnz(tmp_reg, around); 476 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 477 b(done); 478 bind(around); 479 } else { 480 cbz(tmp_reg, done); 481 } 482 483 Label try_revoke_bias; 484 Label try_rebias; 485 486 // At this point we know that the header has the bias pattern and 487 // that we are not the bias owner in the current epoch. We need to 488 // figure out more details about the state of the header in order to 489 // know what operations can be legally performed on the object's 490 // header. 491 492 // If the low three bits in the xor result aren't clear, that means 493 // the prototype header is no longer biased and we have to revoke 494 // the bias on this object. 495 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); 496 cbnz(rscratch1, try_revoke_bias); 497 498 // Biasing is still enabled for this data type. See whether the 499 // epoch of the current bias is still valid, meaning that the epoch 500 // bits of the mark word are equal to the epoch bits of the 501 // prototype header. (Note that the prototype header's epoch bits 502 // only change at a safepoint.) If not, attempt to rebias the object 503 // toward the current thread. Note that we must be absolutely sure 504 // that the current epoch is invalid in order to do this because 505 // otherwise the manipulations it performs on the mark word are 506 // illegal. 507 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); 508 cbnz(rscratch1, try_rebias); 509 510 // The epoch of the current bias is still valid but we know nothing 511 // about the owner; it might be set or it might be clear. Try to 512 // acquire the bias of the object using an atomic operation. If this 513 // fails we will go in to the runtime to revoke the object's bias. 514 // Note that we first construct the presumed unbiased header so we 515 // don't accidentally blow away another thread's valid bias. 516 { 517 Label here; 518 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 519 andr(swap_reg, swap_reg, rscratch1); 520 orr(tmp_reg, swap_reg, rthread); 521 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 522 // If the biasing toward our thread failed, this means that 523 // another thread succeeded in biasing it toward itself and we 524 // need to revoke that bias. The revocation will occur in the 525 // interpreter runtime in the slow case. 526 bind(here); 527 if (counters != NULL) { 528 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 529 tmp_reg, rscratch1, rscratch2); 530 } 531 } 532 b(done); 533 534 bind(try_rebias); 535 // At this point we know the epoch has expired, meaning that the 536 // current "bias owner", if any, is actually invalid. Under these 537 // circumstances _only_, we are allowed to use the current header's 538 // value as the comparison value when doing the cas to acquire the 539 // bias in the current epoch. In other words, we allow transfer of 540 // the bias from one thread to another directly in this situation. 541 // 542 // FIXME: due to a lack of registers we currently blow away the age 543 // bits in this situation. Should attempt to preserve them. 544 { 545 Label here; 546 load_prototype_header(tmp_reg, obj_reg); 547 orr(tmp_reg, rthread, tmp_reg); 548 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 549 // If the biasing toward our thread failed, then another thread 550 // succeeded in biasing it toward itself and we need to revoke that 551 // bias. The revocation will occur in the runtime in the slow case. 552 bind(here); 553 if (counters != NULL) { 554 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 555 tmp_reg, rscratch1, rscratch2); 556 } 557 } 558 b(done); 559 560 bind(try_revoke_bias); 561 // The prototype mark in the klass doesn't have the bias bit set any 562 // more, indicating that objects of this data type are not supposed 563 // to be biased any more. We are going to try to reset the mark of 564 // this object to the prototype value and fall through to the 565 // CAS-based locking scheme. Note that if our CAS fails, it means 566 // that another thread raced us for the privilege of revoking the 567 // bias of this particular object, so it's okay to continue in the 568 // normal locking code. 569 // 570 // FIXME: due to a lack of registers we currently blow away the age 571 // bits in this situation. Should attempt to preserve them. 572 { 573 Label here, nope; 574 load_prototype_header(tmp_reg, obj_reg); 575 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 576 bind(here); 577 578 // Fall through to the normal CAS-based lock, because no matter what 579 // the result of the above CAS, some thread must have succeeded in 580 // removing the bias bit from the object's header. 581 if (counters != NULL) { 582 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 583 rscratch1, rscratch2); 584 } 585 bind(nope); 586 } 587 588 bind(cas_label); 589 590 return null_check_offset; 591 } 592 593 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 594 assert(UseBiasedLocking, "why call this otherwise?"); 595 596 // Check for biased locking unlock case, which is a no-op 597 // Note: we do not have to check the thread ID for two reasons. 598 // First, the interpreter checks for IllegalMonitorStateException at 599 // a higher level. Second, if the bias was revoked while we held the 600 // lock, the object could not be rebiased toward another thread, so 601 // the bias bit would be clear. 602 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 603 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); 604 cmp(temp_reg, markOopDesc::biased_lock_pattern); 605 br(Assembler::EQ, done); 606 } 607 608 static void pass_arg0(MacroAssembler* masm, Register arg) { 609 if (c_rarg0 != arg ) { 610 masm->mov(c_rarg0, arg); 611 } 612 } 613 614 static void pass_arg1(MacroAssembler* masm, Register arg) { 615 if (c_rarg1 != arg ) { 616 masm->mov(c_rarg1, arg); 617 } 618 } 619 620 static void pass_arg2(MacroAssembler* masm, Register arg) { 621 if (c_rarg2 != arg ) { 622 masm->mov(c_rarg2, arg); 623 } 624 } 625 626 static void pass_arg3(MacroAssembler* masm, Register arg) { 627 if (c_rarg3 != arg ) { 628 masm->mov(c_rarg3, arg); 629 } 630 } 631 632 void MacroAssembler::call_VM_base(Register oop_result, 633 Register java_thread, 634 Register last_java_sp, 635 address entry_point, 636 int number_of_arguments, 637 bool check_exceptions) { 638 // determine java_thread register 639 if (!java_thread->is_valid()) { 640 java_thread = rthread; 641 } 642 643 // determine last_java_sp register 644 if (!last_java_sp->is_valid()) { 645 last_java_sp = esp; 646 } 647 648 // debugging support 649 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 650 assert(java_thread == rthread, "unexpected register"); 651 #ifdef ASSERT 652 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 653 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 654 #endif // ASSERT 655 656 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 657 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 658 659 // push java thread (becomes first argument of C function) 660 661 mov(c_rarg0, java_thread); 662 663 // set last Java frame before call 664 assert(last_java_sp != rfp, "can't use rfp"); 665 666 Label l; 667 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 668 669 // do the call, remove parameters 670 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 671 672 // reset last Java frame 673 // Only interpreter should have to clear fp 674 reset_last_Java_frame(true); 675 676 // C++ interp handles this in the interpreter 677 check_and_handle_popframe(java_thread); 678 check_and_handle_earlyret(java_thread); 679 680 if (check_exceptions) { 681 // check for pending exceptions (java_thread is set upon return) 682 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 683 Label ok; 684 cbz(rscratch1, ok); 685 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 686 br(rscratch1); 687 bind(ok); 688 } 689 690 // get oop result if there is one and reset the value in the thread 691 if (oop_result->is_valid()) { 692 get_vm_result(oop_result, java_thread); 693 } 694 } 695 696 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 697 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 698 } 699 700 // Maybe emit a call via a trampoline. If the code cache is small 701 // trampolines won't be emitted. 702 703 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 704 assert(JavaThread::current()->is_Compiler_thread(), "just checking"); 705 assert(entry.rspec().type() == relocInfo::runtime_call_type 706 || entry.rspec().type() == relocInfo::opt_virtual_call_type 707 || entry.rspec().type() == relocInfo::static_call_type 708 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 709 710 unsigned int start_offset = offset(); 711 if (far_branches() && !Compile::current()->in_scratch_emit_size()) { 712 address stub = emit_trampoline_stub(start_offset, entry.target()); 713 if (stub == NULL) { 714 return NULL; // CodeCache is full 715 } 716 } 717 718 if (cbuf) cbuf->set_insts_mark(); 719 relocate(entry.rspec()); 720 if (!far_branches()) { 721 bl(entry.target()); 722 } else { 723 bl(pc()); 724 } 725 // just need to return a non-null address 726 return pc(); 727 } 728 729 730 // Emit a trampoline stub for a call to a target which is too far away. 731 // 732 // code sequences: 733 // 734 // call-site: 735 // branch-and-link to <destination> or <trampoline stub> 736 // 737 // Related trampoline stub for this call site in the stub section: 738 // load the call target from the constant pool 739 // branch (LR still points to the call site above) 740 741 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 742 address dest) { 743 address stub = start_a_stub(Compile::MAX_stubs_size/2); 744 if (stub == NULL) { 745 return NULL; // CodeBuffer::expand failed 746 } 747 748 // Create a trampoline stub relocation which relates this trampoline stub 749 // with the call instruction at insts_call_instruction_offset in the 750 // instructions code-section. 751 align(wordSize); 752 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 753 + insts_call_instruction_offset)); 754 const int stub_start_offset = offset(); 755 756 // Now, create the trampoline stub's code: 757 // - load the call 758 // - call 759 Label target; 760 ldr(rscratch1, target); 761 br(rscratch1); 762 bind(target); 763 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 764 "should be"); 765 emit_int64((int64_t)dest); 766 767 const address stub_start_addr = addr_at(stub_start_offset); 768 769 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 770 771 end_a_stub(); 772 return stub; 773 } 774 775 address MacroAssembler::ic_call(address entry, jint method_index) { 776 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 777 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 778 // unsigned long offset; 779 // ldr_constant(rscratch2, const_ptr); 780 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 781 return trampoline_call(Address(entry, rh)); 782 } 783 784 // Implementation of call_VM versions 785 786 void MacroAssembler::call_VM(Register oop_result, 787 address entry_point, 788 bool check_exceptions) { 789 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 790 } 791 792 void MacroAssembler::call_VM(Register oop_result, 793 address entry_point, 794 Register arg_1, 795 bool check_exceptions) { 796 pass_arg1(this, arg_1); 797 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 798 } 799 800 void MacroAssembler::call_VM(Register oop_result, 801 address entry_point, 802 Register arg_1, 803 Register arg_2, 804 bool check_exceptions) { 805 assert(arg_1 != c_rarg2, "smashed arg"); 806 pass_arg2(this, arg_2); 807 pass_arg1(this, arg_1); 808 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 809 } 810 811 void MacroAssembler::call_VM(Register oop_result, 812 address entry_point, 813 Register arg_1, 814 Register arg_2, 815 Register arg_3, 816 bool check_exceptions) { 817 assert(arg_1 != c_rarg3, "smashed arg"); 818 assert(arg_2 != c_rarg3, "smashed arg"); 819 pass_arg3(this, arg_3); 820 821 assert(arg_1 != c_rarg2, "smashed arg"); 822 pass_arg2(this, arg_2); 823 824 pass_arg1(this, arg_1); 825 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 826 } 827 828 void MacroAssembler::call_VM(Register oop_result, 829 Register last_java_sp, 830 address entry_point, 831 int number_of_arguments, 832 bool check_exceptions) { 833 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 834 } 835 836 void MacroAssembler::call_VM(Register oop_result, 837 Register last_java_sp, 838 address entry_point, 839 Register arg_1, 840 bool check_exceptions) { 841 pass_arg1(this, arg_1); 842 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 843 } 844 845 void MacroAssembler::call_VM(Register oop_result, 846 Register last_java_sp, 847 address entry_point, 848 Register arg_1, 849 Register arg_2, 850 bool check_exceptions) { 851 852 assert(arg_1 != c_rarg2, "smashed arg"); 853 pass_arg2(this, arg_2); 854 pass_arg1(this, arg_1); 855 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 856 } 857 858 void MacroAssembler::call_VM(Register oop_result, 859 Register last_java_sp, 860 address entry_point, 861 Register arg_1, 862 Register arg_2, 863 Register arg_3, 864 bool check_exceptions) { 865 assert(arg_1 != c_rarg3, "smashed arg"); 866 assert(arg_2 != c_rarg3, "smashed arg"); 867 pass_arg3(this, arg_3); 868 assert(arg_1 != c_rarg2, "smashed arg"); 869 pass_arg2(this, arg_2); 870 pass_arg1(this, arg_1); 871 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 872 } 873 874 875 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 876 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 877 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 878 verify_oop(oop_result, "broken oop in call_VM_base"); 879 } 880 881 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 882 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 883 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 884 } 885 886 void MacroAssembler::align(int modulus) { 887 while (offset() % modulus != 0) nop(); 888 } 889 890 // these are no-ops overridden by InterpreterMacroAssembler 891 892 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 893 894 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 895 896 897 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 898 Register tmp, 899 int offset) { 900 intptr_t value = *delayed_value_addr; 901 if (value != 0) 902 return RegisterOrConstant(value + offset); 903 904 // load indirectly to solve generation ordering problem 905 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 906 907 if (offset != 0) 908 add(tmp, tmp, offset); 909 910 return RegisterOrConstant(tmp); 911 } 912 913 914 void MacroAssembler:: notify(int type) { 915 if (type == bytecode_start) { 916 // set_last_Java_frame(esp, rfp, (address)NULL); 917 Assembler:: notify(type); 918 // reset_last_Java_frame(true); 919 } 920 else 921 Assembler:: notify(type); 922 } 923 924 // Look up the method for a megamorphic invokeinterface call. 925 // The target method is determined by <intf_klass, itable_index>. 926 // The receiver klass is in recv_klass. 927 // On success, the result will be in method_result, and execution falls through. 928 // On failure, execution transfers to the given label. 929 void MacroAssembler::lookup_interface_method(Register recv_klass, 930 Register intf_klass, 931 RegisterOrConstant itable_index, 932 Register method_result, 933 Register scan_temp, 934 Label& L_no_such_interface) { 935 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 936 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 937 "caller must use same register for non-constant itable index as for method"); 938 939 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 940 int vtable_base = in_bytes(Klass::vtable_start_offset()); 941 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 942 int scan_step = itableOffsetEntry::size() * wordSize; 943 int vte_size = vtableEntry::size_in_bytes(); 944 assert(vte_size == wordSize, "else adjust times_vte_scale"); 945 946 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 947 948 // %%% Could store the aligned, prescaled offset in the klassoop. 949 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 950 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 951 add(scan_temp, scan_temp, vtable_base); 952 953 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 954 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 955 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 956 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 957 if (itentry_off) 958 add(recv_klass, recv_klass, itentry_off); 959 960 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 961 // if (scan->interface() == intf) { 962 // result = (klass + scan->offset() + itable_index); 963 // } 964 // } 965 Label search, found_method; 966 967 for (int peel = 1; peel >= 0; peel--) { 968 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 969 cmp(intf_klass, method_result); 970 971 if (peel) { 972 br(Assembler::EQ, found_method); 973 } else { 974 br(Assembler::NE, search); 975 // (invert the test to fall through to found_method...) 976 } 977 978 if (!peel) break; 979 980 bind(search); 981 982 // Check that the previous entry is non-null. A null entry means that 983 // the receiver class doesn't implement the interface, and wasn't the 984 // same as when the caller was compiled. 985 cbz(method_result, L_no_such_interface); 986 add(scan_temp, scan_temp, scan_step); 987 } 988 989 bind(found_method); 990 991 // Got a hit. 992 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 993 ldr(method_result, Address(recv_klass, scan_temp)); 994 } 995 996 // virtual method calling 997 void MacroAssembler::lookup_virtual_method(Register recv_klass, 998 RegisterOrConstant vtable_index, 999 Register method_result) { 1000 const int base = in_bytes(Klass::vtable_start_offset()); 1001 assert(vtableEntry::size() * wordSize == 8, 1002 "adjust the scaling in the code below"); 1003 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 1004 1005 if (vtable_index.is_register()) { 1006 lea(method_result, Address(recv_klass, 1007 vtable_index.as_register(), 1008 Address::lsl(LogBytesPerWord))); 1009 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 1010 } else { 1011 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 1012 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes)); 1013 } 1014 } 1015 1016 void MacroAssembler::check_klass_subtype(Register sub_klass, 1017 Register super_klass, 1018 Register temp_reg, 1019 Label& L_success) { 1020 Label L_failure; 1021 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 1022 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 1023 bind(L_failure); 1024 } 1025 1026 1027 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 1028 Register super_klass, 1029 Register temp_reg, 1030 Label* L_success, 1031 Label* L_failure, 1032 Label* L_slow_path, 1033 RegisterOrConstant super_check_offset) { 1034 assert_different_registers(sub_klass, super_klass, temp_reg); 1035 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1036 if (super_check_offset.is_register()) { 1037 assert_different_registers(sub_klass, super_klass, 1038 super_check_offset.as_register()); 1039 } else if (must_load_sco) { 1040 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1041 } 1042 1043 Label L_fallthrough; 1044 int label_nulls = 0; 1045 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1046 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1047 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1048 assert(label_nulls <= 1, "at most one NULL in the batch"); 1049 1050 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1051 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1052 Address super_check_offset_addr(super_klass, sco_offset); 1053 1054 // Hacked jmp, which may only be used just before L_fallthrough. 1055 #define final_jmp(label) \ 1056 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1057 else b(label) /*omit semi*/ 1058 1059 // If the pointers are equal, we are done (e.g., String[] elements). 1060 // This self-check enables sharing of secondary supertype arrays among 1061 // non-primary types such as array-of-interface. Otherwise, each such 1062 // type would need its own customized SSA. 1063 // We move this check to the front of the fast path because many 1064 // type checks are in fact trivially successful in this manner, 1065 // so we get a nicely predicted branch right at the start of the check. 1066 cmp(sub_klass, super_klass); 1067 br(Assembler::EQ, *L_success); 1068 1069 // Check the supertype display: 1070 if (must_load_sco) { 1071 ldrw(temp_reg, super_check_offset_addr); 1072 super_check_offset = RegisterOrConstant(temp_reg); 1073 } 1074 Address super_check_addr(sub_klass, super_check_offset); 1075 ldr(rscratch1, super_check_addr); 1076 cmp(super_klass, rscratch1); // load displayed supertype 1077 1078 // This check has worked decisively for primary supers. 1079 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1080 // (Secondary supers are interfaces and very deeply nested subtypes.) 1081 // This works in the same check above because of a tricky aliasing 1082 // between the super_cache and the primary super display elements. 1083 // (The 'super_check_addr' can address either, as the case requires.) 1084 // Note that the cache is updated below if it does not help us find 1085 // what we need immediately. 1086 // So if it was a primary super, we can just fail immediately. 1087 // Otherwise, it's the slow path for us (no success at this point). 1088 1089 if (super_check_offset.is_register()) { 1090 br(Assembler::EQ, *L_success); 1091 cmp(super_check_offset.as_register(), sc_offset); 1092 if (L_failure == &L_fallthrough) { 1093 br(Assembler::EQ, *L_slow_path); 1094 } else { 1095 br(Assembler::NE, *L_failure); 1096 final_jmp(*L_slow_path); 1097 } 1098 } else if (super_check_offset.as_constant() == sc_offset) { 1099 // Need a slow path; fast failure is impossible. 1100 if (L_slow_path == &L_fallthrough) { 1101 br(Assembler::EQ, *L_success); 1102 } else { 1103 br(Assembler::NE, *L_slow_path); 1104 final_jmp(*L_success); 1105 } 1106 } else { 1107 // No slow path; it's a fast decision. 1108 if (L_failure == &L_fallthrough) { 1109 br(Assembler::EQ, *L_success); 1110 } else { 1111 br(Assembler::NE, *L_failure); 1112 final_jmp(*L_success); 1113 } 1114 } 1115 1116 bind(L_fallthrough); 1117 1118 #undef final_jmp 1119 } 1120 1121 // These two are taken from x86, but they look generally useful 1122 1123 // scans count pointer sized words at [addr] for occurence of value, 1124 // generic 1125 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1126 Register scratch) { 1127 Label Lloop, Lexit; 1128 cbz(count, Lexit); 1129 bind(Lloop); 1130 ldr(scratch, post(addr, wordSize)); 1131 cmp(value, scratch); 1132 br(EQ, Lexit); 1133 sub(count, count, 1); 1134 cbnz(count, Lloop); 1135 bind(Lexit); 1136 } 1137 1138 // scans count 4 byte words at [addr] for occurence of value, 1139 // generic 1140 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1141 Register scratch) { 1142 Label Lloop, Lexit; 1143 cbz(count, Lexit); 1144 bind(Lloop); 1145 ldrw(scratch, post(addr, wordSize)); 1146 cmpw(value, scratch); 1147 br(EQ, Lexit); 1148 sub(count, count, 1); 1149 cbnz(count, Lloop); 1150 bind(Lexit); 1151 } 1152 1153 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1154 Register super_klass, 1155 Register temp_reg, 1156 Register temp2_reg, 1157 Label* L_success, 1158 Label* L_failure, 1159 bool set_cond_codes) { 1160 assert_different_registers(sub_klass, super_klass, temp_reg); 1161 if (temp2_reg != noreg) 1162 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1163 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1164 1165 Label L_fallthrough; 1166 int label_nulls = 0; 1167 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1168 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1169 assert(label_nulls <= 1, "at most one NULL in the batch"); 1170 1171 // a couple of useful fields in sub_klass: 1172 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1173 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1174 Address secondary_supers_addr(sub_klass, ss_offset); 1175 Address super_cache_addr( sub_klass, sc_offset); 1176 1177 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1178 1179 // Do a linear scan of the secondary super-klass chain. 1180 // This code is rarely used, so simplicity is a virtue here. 1181 // The repne_scan instruction uses fixed registers, which we must spill. 1182 // Don't worry too much about pre-existing connections with the input regs. 1183 1184 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1185 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1186 1187 // Get super_klass value into r0 (even if it was in r5 or r2). 1188 RegSet pushed_registers; 1189 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1190 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1191 1192 if (super_klass != r0 || UseCompressedOops) { 1193 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1194 } 1195 1196 push(pushed_registers, sp); 1197 1198 #ifndef PRODUCT 1199 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1200 Address pst_counter_addr(rscratch2); 1201 ldr(rscratch1, pst_counter_addr); 1202 add(rscratch1, rscratch1, 1); 1203 str(rscratch1, pst_counter_addr); 1204 #endif //PRODUCT 1205 1206 // We will consult the secondary-super array. 1207 ldr(r5, secondary_supers_addr); 1208 // Load the array length. 1209 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1210 // Skip to start of data. 1211 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1212 1213 cmp(sp, zr); // Clear Z flag; SP is never zero 1214 // Scan R2 words at [R5] for an occurrence of R0. 1215 // Set NZ/Z based on last compare. 1216 repne_scan(r5, r0, r2, rscratch1); 1217 1218 // Unspill the temp. registers: 1219 pop(pushed_registers, sp); 1220 1221 br(Assembler::NE, *L_failure); 1222 1223 // Success. Cache the super we found and proceed in triumph. 1224 str(super_klass, super_cache_addr); 1225 1226 if (L_success != &L_fallthrough) { 1227 b(*L_success); 1228 } 1229 1230 #undef IS_A_TEMP 1231 1232 bind(L_fallthrough); 1233 } 1234 1235 1236 void MacroAssembler::verify_oop(Register reg, const char* s) { 1237 if (!VerifyOops) return; 1238 1239 // Pass register number to verify_oop_subroutine 1240 const char* b = NULL; 1241 { 1242 ResourceMark rm; 1243 stringStream ss; 1244 ss.print("verify_oop: %s: %s", reg->name(), s); 1245 b = code_string(ss.as_string()); 1246 } 1247 BLOCK_COMMENT("verify_oop {"); 1248 1249 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1250 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1251 1252 mov(r0, reg); 1253 mov(rscratch1, (address)b); 1254 1255 // call indirectly to solve generation ordering problem 1256 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1257 ldr(rscratch2, Address(rscratch2)); 1258 blr(rscratch2); 1259 1260 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1261 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1262 1263 BLOCK_COMMENT("} verify_oop"); 1264 } 1265 1266 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1267 if (!VerifyOops) return; 1268 1269 const char* b = NULL; 1270 { 1271 ResourceMark rm; 1272 stringStream ss; 1273 ss.print("verify_oop_addr: %s", s); 1274 b = code_string(ss.as_string()); 1275 } 1276 BLOCK_COMMENT("verify_oop_addr {"); 1277 1278 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1279 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1280 1281 // addr may contain sp so we will have to adjust it based on the 1282 // pushes that we just did. 1283 if (addr.uses(sp)) { 1284 lea(r0, addr); 1285 ldr(r0, Address(r0, 4 * wordSize)); 1286 } else { 1287 ldr(r0, addr); 1288 } 1289 mov(rscratch1, (address)b); 1290 1291 // call indirectly to solve generation ordering problem 1292 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1293 ldr(rscratch2, Address(rscratch2)); 1294 blr(rscratch2); 1295 1296 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1297 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1298 1299 BLOCK_COMMENT("} verify_oop_addr"); 1300 } 1301 1302 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1303 int extra_slot_offset) { 1304 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1305 int stackElementSize = Interpreter::stackElementSize; 1306 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1307 #ifdef ASSERT 1308 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1309 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1310 #endif 1311 if (arg_slot.is_constant()) { 1312 return Address(esp, arg_slot.as_constant() * stackElementSize 1313 + offset); 1314 } else { 1315 add(rscratch1, esp, arg_slot.as_register(), 1316 ext::uxtx, exact_log2(stackElementSize)); 1317 return Address(rscratch1, offset); 1318 } 1319 } 1320 1321 void MacroAssembler::call_VM_leaf_base(address entry_point, 1322 int number_of_arguments, 1323 Label *retaddr) { 1324 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); 1325 } 1326 1327 void MacroAssembler::call_VM_leaf_base1(address entry_point, 1328 int number_of_gp_arguments, 1329 int number_of_fp_arguments, 1330 ret_type type, 1331 Label *retaddr) { 1332 Label E, L; 1333 1334 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1335 1336 // We add 1 to number_of_arguments because the thread in arg0 is 1337 // not counted 1338 mov(rscratch1, entry_point); 1339 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); 1340 if (retaddr) 1341 bind(*retaddr); 1342 1343 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1344 maybe_isb(); 1345 } 1346 1347 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1348 call_VM_leaf_base(entry_point, number_of_arguments); 1349 } 1350 1351 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1352 pass_arg0(this, arg_0); 1353 call_VM_leaf_base(entry_point, 1); 1354 } 1355 1356 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1357 pass_arg0(this, arg_0); 1358 pass_arg1(this, arg_1); 1359 call_VM_leaf_base(entry_point, 2); 1360 } 1361 1362 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1363 Register arg_1, Register arg_2) { 1364 pass_arg0(this, arg_0); 1365 pass_arg1(this, arg_1); 1366 pass_arg2(this, arg_2); 1367 call_VM_leaf_base(entry_point, 3); 1368 } 1369 1370 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1371 pass_arg0(this, arg_0); 1372 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1373 } 1374 1375 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1376 1377 assert(arg_0 != c_rarg1, "smashed arg"); 1378 pass_arg1(this, arg_1); 1379 pass_arg0(this, arg_0); 1380 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1381 } 1382 1383 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1384 assert(arg_0 != c_rarg2, "smashed arg"); 1385 assert(arg_1 != c_rarg2, "smashed arg"); 1386 pass_arg2(this, arg_2); 1387 assert(arg_0 != c_rarg1, "smashed arg"); 1388 pass_arg1(this, arg_1); 1389 pass_arg0(this, arg_0); 1390 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1391 } 1392 1393 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1394 assert(arg_0 != c_rarg3, "smashed arg"); 1395 assert(arg_1 != c_rarg3, "smashed arg"); 1396 assert(arg_2 != c_rarg3, "smashed arg"); 1397 pass_arg3(this, arg_3); 1398 assert(arg_0 != c_rarg2, "smashed arg"); 1399 assert(arg_1 != c_rarg2, "smashed arg"); 1400 pass_arg2(this, arg_2); 1401 assert(arg_0 != c_rarg1, "smashed arg"); 1402 pass_arg1(this, arg_1); 1403 pass_arg0(this, arg_0); 1404 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1405 } 1406 1407 void MacroAssembler::null_check(Register reg, int offset) { 1408 if (needs_explicit_null_check(offset)) { 1409 // provoke OS NULL exception if reg = NULL by 1410 // accessing M[reg] w/o changing any registers 1411 // NOTE: this is plenty to provoke a segv 1412 ldr(zr, Address(reg)); 1413 } else { 1414 // nothing to do, (later) access of M[reg + offset] 1415 // will provoke OS NULL exception if reg = NULL 1416 } 1417 } 1418 1419 // MacroAssembler protected routines needed to implement 1420 // public methods 1421 1422 void MacroAssembler::mov(Register r, Address dest) { 1423 code_section()->relocate(pc(), dest.rspec()); 1424 u_int64_t imm64 = (u_int64_t)dest.target(); 1425 movptr(r, imm64); 1426 } 1427 1428 // Move a constant pointer into r. In AArch64 mode the virtual 1429 // address space is 48 bits in size, so we only need three 1430 // instructions to create a patchable instruction sequence that can 1431 // reach anywhere. 1432 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1433 #ifndef PRODUCT 1434 { 1435 char buffer[64]; 1436 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1437 block_comment(buffer); 1438 } 1439 #endif 1440 assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); 1441 movz(r, imm64 & 0xffff); 1442 imm64 >>= 16; 1443 movk(r, imm64 & 0xffff, 16); 1444 imm64 >>= 16; 1445 movk(r, imm64 & 0xffff, 32); 1446 } 1447 1448 // Macro to mov replicated immediate to vector register. 1449 // Vd will get the following values for different arrangements in T 1450 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1451 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1452 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1453 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1454 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1455 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1456 // T1D/T2D: invalid 1457 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 1458 assert(T != T1D && T != T2D, "invalid arrangement"); 1459 if (T == T8B || T == T16B) { 1460 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1461 movi(Vd, T, imm32 & 0xff, 0); 1462 return; 1463 } 1464 u_int32_t nimm32 = ~imm32; 1465 if (T == T4H || T == T8H) { 1466 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1467 imm32 &= 0xffff; 1468 nimm32 &= 0xffff; 1469 } 1470 u_int32_t x = imm32; 1471 int movi_cnt = 0; 1472 int movn_cnt = 0; 1473 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1474 x = nimm32; 1475 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1476 if (movn_cnt < movi_cnt) imm32 = nimm32; 1477 unsigned lsl = 0; 1478 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1479 if (movn_cnt < movi_cnt) 1480 mvni(Vd, T, imm32 & 0xff, lsl); 1481 else 1482 movi(Vd, T, imm32 & 0xff, lsl); 1483 imm32 >>= 8; lsl += 8; 1484 while (imm32) { 1485 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1486 if (movn_cnt < movi_cnt) 1487 bici(Vd, T, imm32 & 0xff, lsl); 1488 else 1489 orri(Vd, T, imm32 & 0xff, lsl); 1490 lsl += 8; imm32 >>= 8; 1491 } 1492 } 1493 1494 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) 1495 { 1496 #ifndef PRODUCT 1497 { 1498 char buffer[64]; 1499 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1500 block_comment(buffer); 1501 } 1502 #endif 1503 if (operand_valid_for_logical_immediate(false, imm64)) { 1504 orr(dst, zr, imm64); 1505 } else { 1506 // we can use a combination of MOVZ or MOVN with 1507 // MOVK to build up the constant 1508 u_int64_t imm_h[4]; 1509 int zero_count = 0; 1510 int neg_count = 0; 1511 int i; 1512 for (i = 0; i < 4; i++) { 1513 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1514 if (imm_h[i] == 0) { 1515 zero_count++; 1516 } else if (imm_h[i] == 0xffffL) { 1517 neg_count++; 1518 } 1519 } 1520 if (zero_count == 4) { 1521 // one MOVZ will do 1522 movz(dst, 0); 1523 } else if (neg_count == 4) { 1524 // one MOVN will do 1525 movn(dst, 0); 1526 } else if (zero_count == 3) { 1527 for (i = 0; i < 4; i++) { 1528 if (imm_h[i] != 0L) { 1529 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1530 break; 1531 } 1532 } 1533 } else if (neg_count == 3) { 1534 // one MOVN will do 1535 for (int i = 0; i < 4; i++) { 1536 if (imm_h[i] != 0xffffL) { 1537 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1538 break; 1539 } 1540 } 1541 } else if (zero_count == 2) { 1542 // one MOVZ and one MOVK will do 1543 for (i = 0; i < 3; i++) { 1544 if (imm_h[i] != 0L) { 1545 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1546 i++; 1547 break; 1548 } 1549 } 1550 for (;i < 4; i++) { 1551 if (imm_h[i] != 0L) { 1552 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1553 } 1554 } 1555 } else if (neg_count == 2) { 1556 // one MOVN and one MOVK will do 1557 for (i = 0; i < 4; i++) { 1558 if (imm_h[i] != 0xffffL) { 1559 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1560 i++; 1561 break; 1562 } 1563 } 1564 for (;i < 4; i++) { 1565 if (imm_h[i] != 0xffffL) { 1566 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1567 } 1568 } 1569 } else if (zero_count == 1) { 1570 // one MOVZ and two MOVKs will do 1571 for (i = 0; i < 4; i++) { 1572 if (imm_h[i] != 0L) { 1573 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1574 i++; 1575 break; 1576 } 1577 } 1578 for (;i < 4; i++) { 1579 if (imm_h[i] != 0x0L) { 1580 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1581 } 1582 } 1583 } else if (neg_count == 1) { 1584 // one MOVN and two MOVKs will do 1585 for (i = 0; i < 4; i++) { 1586 if (imm_h[i] != 0xffffL) { 1587 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1588 i++; 1589 break; 1590 } 1591 } 1592 for (;i < 4; i++) { 1593 if (imm_h[i] != 0xffffL) { 1594 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1595 } 1596 } 1597 } else { 1598 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1599 movz(dst, (u_int32_t)imm_h[0], 0); 1600 for (i = 1; i < 4; i++) { 1601 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1602 } 1603 } 1604 } 1605 } 1606 1607 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) 1608 { 1609 #ifndef PRODUCT 1610 { 1611 char buffer[64]; 1612 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); 1613 block_comment(buffer); 1614 } 1615 #endif 1616 if (operand_valid_for_logical_immediate(true, imm32)) { 1617 orrw(dst, zr, imm32); 1618 } else { 1619 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1620 // constant 1621 u_int32_t imm_h[2]; 1622 imm_h[0] = imm32 & 0xffff; 1623 imm_h[1] = ((imm32 >> 16) & 0xffff); 1624 if (imm_h[0] == 0) { 1625 movzw(dst, imm_h[1], 16); 1626 } else if (imm_h[0] == 0xffff) { 1627 movnw(dst, imm_h[1] ^ 0xffff, 16); 1628 } else if (imm_h[1] == 0) { 1629 movzw(dst, imm_h[0], 0); 1630 } else if (imm_h[1] == 0xffff) { 1631 movnw(dst, imm_h[0] ^ 0xffff, 0); 1632 } else { 1633 // use a MOVZ and MOVK (makes it easier to debug) 1634 movzw(dst, imm_h[0], 0); 1635 movkw(dst, imm_h[1], 16); 1636 } 1637 } 1638 } 1639 1640 // Form an address from base + offset in Rd. Rd may or may 1641 // not actually be used: you must use the Address that is returned. 1642 // It is up to you to ensure that the shift provided matches the size 1643 // of your data. 1644 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { 1645 if (Address::offset_ok_for_immed(byte_offset, shift)) 1646 // It fits; no need for any heroics 1647 return Address(base, byte_offset); 1648 1649 // Don't do anything clever with negative or misaligned offsets 1650 unsigned mask = (1 << shift) - 1; 1651 if (byte_offset < 0 || byte_offset & mask) { 1652 mov(Rd, byte_offset); 1653 add(Rd, base, Rd); 1654 return Address(Rd); 1655 } 1656 1657 // See if we can do this with two 12-bit offsets 1658 { 1659 unsigned long word_offset = byte_offset >> shift; 1660 unsigned long masked_offset = word_offset & 0xfff000; 1661 if (Address::offset_ok_for_immed(word_offset - masked_offset) 1662 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1663 add(Rd, base, masked_offset << shift); 1664 word_offset -= masked_offset; 1665 return Address(Rd, word_offset << shift); 1666 } 1667 } 1668 1669 // Do it the hard way 1670 mov(Rd, byte_offset); 1671 add(Rd, base, Rd); 1672 return Address(Rd); 1673 } 1674 1675 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1676 if (UseLSE) { 1677 mov(tmp, 1); 1678 ldadd(Assembler::word, tmp, zr, counter_addr); 1679 return; 1680 } 1681 Label retry_load; 1682 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 1683 prfm(Address(counter_addr), PSTL1STRM); 1684 bind(retry_load); 1685 // flush and load exclusive from the memory location 1686 ldxrw(tmp, counter_addr); 1687 addw(tmp, tmp, 1); 1688 // if we store+flush with no intervening write tmp wil be zero 1689 stxrw(tmp2, tmp, counter_addr); 1690 cbnzw(tmp2, retry_load); 1691 } 1692 1693 1694 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1695 bool want_remainder, Register scratch) 1696 { 1697 // Full implementation of Java idiv and irem. The function 1698 // returns the (pc) offset of the div instruction - may be needed 1699 // for implicit exceptions. 1700 // 1701 // constraint : ra/rb =/= scratch 1702 // normal case 1703 // 1704 // input : ra: dividend 1705 // rb: divisor 1706 // 1707 // result: either 1708 // quotient (= ra idiv rb) 1709 // remainder (= ra irem rb) 1710 1711 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1712 1713 int idivl_offset = offset(); 1714 if (! want_remainder) { 1715 sdivw(result, ra, rb); 1716 } else { 1717 sdivw(scratch, ra, rb); 1718 Assembler::msubw(result, scratch, rb, ra); 1719 } 1720 1721 return idivl_offset; 1722 } 1723 1724 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1725 bool want_remainder, Register scratch) 1726 { 1727 // Full implementation of Java ldiv and lrem. The function 1728 // returns the (pc) offset of the div instruction - may be needed 1729 // for implicit exceptions. 1730 // 1731 // constraint : ra/rb =/= scratch 1732 // normal case 1733 // 1734 // input : ra: dividend 1735 // rb: divisor 1736 // 1737 // result: either 1738 // quotient (= ra idiv rb) 1739 // remainder (= ra irem rb) 1740 1741 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1742 1743 int idivq_offset = offset(); 1744 if (! want_remainder) { 1745 sdiv(result, ra, rb); 1746 } else { 1747 sdiv(scratch, ra, rb); 1748 Assembler::msub(result, scratch, rb, ra); 1749 } 1750 1751 return idivq_offset; 1752 } 1753 1754 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1755 address prev = pc() - NativeMembar::instruction_size; 1756 if (prev == code()->last_membar()) { 1757 NativeMembar *bar = NativeMembar_at(prev); 1758 // We are merging two memory barrier instructions. On AArch64 we 1759 // can do this simply by ORing them together. 1760 bar->set_kind(bar->get_kind() | order_constraint); 1761 BLOCK_COMMENT("merged membar"); 1762 } else { 1763 code()->set_last_membar(pc()); 1764 dmb(Assembler::barrier(order_constraint)); 1765 } 1766 } 1767 1768 // MacroAssembler routines found actually to be needed 1769 1770 void MacroAssembler::push(Register src) 1771 { 1772 str(src, Address(pre(esp, -1 * wordSize))); 1773 } 1774 1775 void MacroAssembler::pop(Register dst) 1776 { 1777 ldr(dst, Address(post(esp, 1 * wordSize))); 1778 } 1779 1780 // Note: load_unsigned_short used to be called load_unsigned_word. 1781 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1782 int off = offset(); 1783 ldrh(dst, src); 1784 return off; 1785 } 1786 1787 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1788 int off = offset(); 1789 ldrb(dst, src); 1790 return off; 1791 } 1792 1793 int MacroAssembler::load_signed_short(Register dst, Address src) { 1794 int off = offset(); 1795 ldrsh(dst, src); 1796 return off; 1797 } 1798 1799 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1800 int off = offset(); 1801 ldrsb(dst, src); 1802 return off; 1803 } 1804 1805 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1806 int off = offset(); 1807 ldrshw(dst, src); 1808 return off; 1809 } 1810 1811 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1812 int off = offset(); 1813 ldrsbw(dst, src); 1814 return off; 1815 } 1816 1817 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1818 switch (size_in_bytes) { 1819 case 8: ldr(dst, src); break; 1820 case 4: ldrw(dst, src); break; 1821 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1822 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1823 default: ShouldNotReachHere(); 1824 } 1825 } 1826 1827 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1828 switch (size_in_bytes) { 1829 case 8: str(src, dst); break; 1830 case 4: strw(src, dst); break; 1831 case 2: strh(src, dst); break; 1832 case 1: strb(src, dst); break; 1833 default: ShouldNotReachHere(); 1834 } 1835 } 1836 1837 void MacroAssembler::decrementw(Register reg, int value) 1838 { 1839 if (value < 0) { incrementw(reg, -value); return; } 1840 if (value == 0) { return; } 1841 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1842 /* else */ { 1843 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1844 movw(rscratch2, (unsigned)value); 1845 subw(reg, reg, rscratch2); 1846 } 1847 } 1848 1849 void MacroAssembler::decrement(Register reg, int value) 1850 { 1851 if (value < 0) { increment(reg, -value); return; } 1852 if (value == 0) { return; } 1853 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1854 /* else */ { 1855 assert(reg != rscratch2, "invalid dst for register decrement"); 1856 mov(rscratch2, (unsigned long)value); 1857 sub(reg, reg, rscratch2); 1858 } 1859 } 1860 1861 void MacroAssembler::decrementw(Address dst, int value) 1862 { 1863 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1864 ldrw(rscratch1, dst); 1865 decrementw(rscratch1, value); 1866 strw(rscratch1, dst); 1867 } 1868 1869 void MacroAssembler::decrement(Address dst, int value) 1870 { 1871 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1872 ldr(rscratch1, dst); 1873 decrement(rscratch1, value); 1874 str(rscratch1, dst); 1875 } 1876 1877 void MacroAssembler::incrementw(Register reg, int value) 1878 { 1879 if (value < 0) { decrementw(reg, -value); return; } 1880 if (value == 0) { return; } 1881 if (value < (1 << 12)) { addw(reg, reg, value); return; } 1882 /* else */ { 1883 assert(reg != rscratch2, "invalid dst for register increment"); 1884 movw(rscratch2, (unsigned)value); 1885 addw(reg, reg, rscratch2); 1886 } 1887 } 1888 1889 void MacroAssembler::increment(Register reg, int value) 1890 { 1891 if (value < 0) { decrement(reg, -value); return; } 1892 if (value == 0) { return; } 1893 if (value < (1 << 12)) { add(reg, reg, value); return; } 1894 /* else */ { 1895 assert(reg != rscratch2, "invalid dst for register increment"); 1896 movw(rscratch2, (unsigned)value); 1897 add(reg, reg, rscratch2); 1898 } 1899 } 1900 1901 void MacroAssembler::incrementw(Address dst, int value) 1902 { 1903 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1904 ldrw(rscratch1, dst); 1905 incrementw(rscratch1, value); 1906 strw(rscratch1, dst); 1907 } 1908 1909 void MacroAssembler::increment(Address dst, int value) 1910 { 1911 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1912 ldr(rscratch1, dst); 1913 increment(rscratch1, value); 1914 str(rscratch1, dst); 1915 } 1916 1917 1918 void MacroAssembler::pusha() { 1919 push(0x7fffffff, sp); 1920 } 1921 1922 void MacroAssembler::popa() { 1923 pop(0x7fffffff, sp); 1924 } 1925 1926 // Push lots of registers in the bit set supplied. Don't push sp. 1927 // Return the number of words pushed 1928 int MacroAssembler::push(unsigned int bitset, Register stack) { 1929 int words_pushed = 0; 1930 1931 // Scan bitset to accumulate register pairs 1932 unsigned char regs[32]; 1933 int count = 0; 1934 for (int reg = 0; reg <= 30; reg++) { 1935 if (1 & bitset) 1936 regs[count++] = reg; 1937 bitset >>= 1; 1938 } 1939 regs[count++] = zr->encoding_nocheck(); 1940 count &= ~1; // Only push an even nuber of regs 1941 1942 if (count) { 1943 stp(as_Register(regs[0]), as_Register(regs[1]), 1944 Address(pre(stack, -count * wordSize))); 1945 words_pushed += 2; 1946 } 1947 for (int i = 2; i < count; i += 2) { 1948 stp(as_Register(regs[i]), as_Register(regs[i+1]), 1949 Address(stack, i * wordSize)); 1950 words_pushed += 2; 1951 } 1952 1953 assert(words_pushed == count, "oops, pushed != count"); 1954 1955 return count; 1956 } 1957 1958 int MacroAssembler::pop(unsigned int bitset, Register stack) { 1959 int words_pushed = 0; 1960 1961 // Scan bitset to accumulate register pairs 1962 unsigned char regs[32]; 1963 int count = 0; 1964 for (int reg = 0; reg <= 30; reg++) { 1965 if (1 & bitset) 1966 regs[count++] = reg; 1967 bitset >>= 1; 1968 } 1969 regs[count++] = zr->encoding_nocheck(); 1970 count &= ~1; 1971 1972 for (int i = 2; i < count; i += 2) { 1973 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 1974 Address(stack, i * wordSize)); 1975 words_pushed += 2; 1976 } 1977 if (count) { 1978 ldp(as_Register(regs[0]), as_Register(regs[1]), 1979 Address(post(stack, count * wordSize))); 1980 words_pushed += 2; 1981 } 1982 1983 assert(words_pushed == count, "oops, pushed != count"); 1984 1985 return count; 1986 } 1987 #ifdef ASSERT 1988 void MacroAssembler::verify_heapbase(const char* msg) { 1989 #if 0 1990 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 1991 assert (Universe::heap() != NULL, "java heap should be initialized"); 1992 if (CheckCompressedOops) { 1993 Label ok; 1994 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 1995 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 1996 br(Assembler::EQ, ok); 1997 stop(msg); 1998 bind(ok); 1999 pop(1 << rscratch1->encoding(), sp); 2000 } 2001 #endif 2002 } 2003 #endif 2004 2005 void MacroAssembler::stop(const char* msg) { 2006 address ip = pc(); 2007 pusha(); 2008 mov(c_rarg0, (address)msg); 2009 mov(c_rarg1, (address)ip); 2010 mov(c_rarg2, sp); 2011 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); 2012 // call(c_rarg3); 2013 blrt(c_rarg3, 3, 0, 1); 2014 hlt(0); 2015 } 2016 2017 void MacroAssembler::unimplemented(const char* what) { 2018 char* b = new char[1024]; 2019 jio_snprintf(b, 1024, "unimplemented: %s", what); 2020 stop(b); 2021 } 2022 2023 // If a constant does not fit in an immediate field, generate some 2024 // number of MOV instructions and then perform the operation. 2025 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 2026 add_sub_imm_insn insn1, 2027 add_sub_reg_insn insn2) { 2028 assert(Rd != zr, "Rd = zr and not setting flags?"); 2029 if (operand_valid_for_add_sub_immediate((int)imm)) { 2030 (this->*insn1)(Rd, Rn, imm); 2031 } else { 2032 if (uabs(imm) < (1 << 24)) { 2033 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 2034 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 2035 } else { 2036 assert_different_registers(Rd, Rn); 2037 mov(Rd, (uint64_t)imm); 2038 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2039 } 2040 } 2041 } 2042 2043 // Seperate vsn which sets the flags. Optimisations are more restricted 2044 // because we must set the flags correctly. 2045 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 2046 add_sub_imm_insn insn1, 2047 add_sub_reg_insn insn2) { 2048 if (operand_valid_for_add_sub_immediate((int)imm)) { 2049 (this->*insn1)(Rd, Rn, imm); 2050 } else { 2051 assert_different_registers(Rd, Rn); 2052 assert(Rd != zr, "overflow in immediate operand"); 2053 mov(Rd, (uint64_t)imm); 2054 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2055 } 2056 } 2057 2058 2059 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2060 if (increment.is_register()) { 2061 add(Rd, Rn, increment.as_register()); 2062 } else { 2063 add(Rd, Rn, increment.as_constant()); 2064 } 2065 } 2066 2067 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2068 if (increment.is_register()) { 2069 addw(Rd, Rn, increment.as_register()); 2070 } else { 2071 addw(Rd, Rn, increment.as_constant()); 2072 } 2073 } 2074 2075 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2076 if (decrement.is_register()) { 2077 sub(Rd, Rn, decrement.as_register()); 2078 } else { 2079 sub(Rd, Rn, decrement.as_constant()); 2080 } 2081 } 2082 2083 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2084 if (decrement.is_register()) { 2085 subw(Rd, Rn, decrement.as_register()); 2086 } else { 2087 subw(Rd, Rn, decrement.as_constant()); 2088 } 2089 } 2090 2091 void MacroAssembler::reinit_heapbase() 2092 { 2093 if (UseCompressedOops) { 2094 if (Universe::is_fully_initialized()) { 2095 mov(rheapbase, Universe::narrow_ptrs_base()); 2096 } else { 2097 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2098 ldr(rheapbase, Address(rheapbase)); 2099 } 2100 } 2101 } 2102 2103 // this simulates the behaviour of the x86 cmpxchg instruction using a 2104 // load linked/store conditional pair. we use the acquire/release 2105 // versions of these instructions so that we flush pending writes as 2106 // per Java semantics. 2107 2108 // n.b the x86 version assumes the old value to be compared against is 2109 // in rax and updates rax with the value located in memory if the 2110 // cmpxchg fails. we supply a register for the old value explicitly 2111 2112 // the aarch64 load linked/store conditional instructions do not 2113 // accept an offset. so, unlike x86, we must provide a plain register 2114 // to identify the memory word to be compared/exchanged rather than a 2115 // register+offset Address. 2116 2117 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2118 Label &succeed, Label *fail) { 2119 // oldv holds comparison value 2120 // newv holds value to write in exchange 2121 // addr identifies memory word to compare against/update 2122 if (UseLSE) { 2123 mov(tmp, oldv); 2124 casal(Assembler::xword, oldv, newv, addr); 2125 cmp(tmp, oldv); 2126 br(Assembler::EQ, succeed); 2127 membar(AnyAny); 2128 } else { 2129 Label retry_load, nope; 2130 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2131 prfm(Address(addr), PSTL1STRM); 2132 bind(retry_load); 2133 // flush and load exclusive from the memory location 2134 // and fail if it is not what we expect 2135 ldaxr(tmp, addr); 2136 cmp(tmp, oldv); 2137 br(Assembler::NE, nope); 2138 // if we store+flush with no intervening write tmp wil be zero 2139 stlxr(tmp, newv, addr); 2140 cbzw(tmp, succeed); 2141 // retry so we only ever return after a load fails to compare 2142 // ensures we don't return a stale value after a failed write. 2143 b(retry_load); 2144 // if the memory word differs we return it in oldv and signal a fail 2145 bind(nope); 2146 membar(AnyAny); 2147 mov(oldv, tmp); 2148 } 2149 if (fail) 2150 b(*fail); 2151 } 2152 2153 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 2154 Label &succeed, Label *fail) { 2155 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption"); 2156 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail); 2157 } 2158 2159 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2160 Label &succeed, Label *fail) { 2161 // oldv holds comparison value 2162 // newv holds value to write in exchange 2163 // addr identifies memory word to compare against/update 2164 // tmp returns 0/1 for success/failure 2165 if (UseLSE) { 2166 mov(tmp, oldv); 2167 casal(Assembler::word, oldv, newv, addr); 2168 cmp(tmp, oldv); 2169 br(Assembler::EQ, succeed); 2170 membar(AnyAny); 2171 } else { 2172 Label retry_load, nope; 2173 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2174 prfm(Address(addr), PSTL1STRM); 2175 bind(retry_load); 2176 // flush and load exclusive from the memory location 2177 // and fail if it is not what we expect 2178 ldaxrw(tmp, addr); 2179 cmp(tmp, oldv); 2180 br(Assembler::NE, nope); 2181 // if we store+flush with no intervening write tmp wil be zero 2182 stlxrw(tmp, newv, addr); 2183 cbzw(tmp, succeed); 2184 // retry so we only ever return after a load fails to compare 2185 // ensures we don't return a stale value after a failed write. 2186 b(retry_load); 2187 // if the memory word differs we return it in oldv and signal a fail 2188 bind(nope); 2189 membar(AnyAny); 2190 mov(oldv, tmp); 2191 } 2192 if (fail) 2193 b(*fail); 2194 } 2195 2196 // A generic CAS; success or failure is in the EQ flag. A weak CAS 2197 // doesn't retry and may fail spuriously. If the oldval is wanted, 2198 // Pass a register for the result, otherwise pass noreg. 2199 2200 // Clobbers rscratch1 2201 void MacroAssembler::cmpxchg(Register addr, Register expected, 2202 Register new_val, 2203 enum operand_size size, 2204 bool acquire, bool release, 2205 bool weak, 2206 Register result) { 2207 if (result == noreg) result = rscratch1; 2208 if (UseLSE) { 2209 mov(result, expected); 2210 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true); 2211 cmp(result, expected); 2212 } else { 2213 BLOCK_COMMENT("cmpxchg {"); 2214 Label retry_load, done; 2215 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2216 prfm(Address(addr), PSTL1STRM); 2217 bind(retry_load); 2218 load_exclusive(result, addr, size, acquire); 2219 if (size == xword) 2220 cmp(result, expected); 2221 else 2222 cmpw(result, expected); 2223 br(Assembler::NE, done); 2224 store_exclusive(rscratch1, new_val, addr, size, release); 2225 if (weak) { 2226 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller. 2227 } else { 2228 cbnzw(rscratch1, retry_load); 2229 } 2230 bind(done); 2231 BLOCK_COMMENT("} cmpxchg"); 2232 } 2233 } 2234 2235 static bool different(Register a, RegisterOrConstant b, Register c) { 2236 if (b.is_constant()) 2237 return a != c; 2238 else 2239 return a != b.as_register() && a != c && b.as_register() != c; 2240 } 2241 2242 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \ 2243 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \ 2244 if (UseLSE) { \ 2245 prev = prev->is_valid() ? prev : zr; \ 2246 if (incr.is_register()) { \ 2247 AOP(sz, incr.as_register(), prev, addr); \ 2248 } else { \ 2249 mov(rscratch2, incr.as_constant()); \ 2250 AOP(sz, rscratch2, prev, addr); \ 2251 } \ 2252 return; \ 2253 } \ 2254 Register result = rscratch2; \ 2255 if (prev->is_valid()) \ 2256 result = different(prev, incr, addr) ? prev : rscratch2; \ 2257 \ 2258 Label retry_load; \ 2259 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2260 prfm(Address(addr), PSTL1STRM); \ 2261 bind(retry_load); \ 2262 LDXR(result, addr); \ 2263 OP(rscratch1, result, incr); \ 2264 STXR(rscratch2, rscratch1, addr); \ 2265 cbnzw(rscratch2, retry_load); \ 2266 if (prev->is_valid() && prev != result) { \ 2267 IOP(prev, rscratch1, incr); \ 2268 } \ 2269 } 2270 2271 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword) 2272 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word) 2273 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword) 2274 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word) 2275 2276 #undef ATOMIC_OP 2277 2278 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \ 2279 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2280 if (UseLSE) { \ 2281 prev = prev->is_valid() ? prev : zr; \ 2282 AOP(sz, newv, prev, addr); \ 2283 return; \ 2284 } \ 2285 Register result = rscratch2; \ 2286 if (prev->is_valid()) \ 2287 result = different(prev, newv, addr) ? prev : rscratch2; \ 2288 \ 2289 Label retry_load; \ 2290 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2291 prfm(Address(addr), PSTL1STRM); \ 2292 bind(retry_load); \ 2293 LDXR(result, addr); \ 2294 STXR(rscratch1, newv, addr); \ 2295 cbnzw(rscratch1, retry_load); \ 2296 if (prev->is_valid() && prev != result) \ 2297 mov(prev, result); \ 2298 } 2299 2300 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) 2301 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) 2302 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) 2303 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) 2304 2305 #undef ATOMIC_XCHG 2306 2307 void MacroAssembler::incr_allocated_bytes(Register thread, 2308 Register var_size_in_bytes, 2309 int con_size_in_bytes, 2310 Register t1) { 2311 if (!thread->is_valid()) { 2312 thread = rthread; 2313 } 2314 assert(t1->is_valid(), "need temp reg"); 2315 2316 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2317 if (var_size_in_bytes->is_valid()) { 2318 add(t1, t1, var_size_in_bytes); 2319 } else { 2320 add(t1, t1, con_size_in_bytes); 2321 } 2322 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2323 } 2324 2325 #ifndef PRODUCT 2326 extern "C" void findpc(intptr_t x); 2327 #endif 2328 2329 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2330 { 2331 // In order to get locks to work, we need to fake a in_VM state 2332 if (ShowMessageBoxOnError ) { 2333 JavaThread* thread = JavaThread::current(); 2334 JavaThreadState saved_state = thread->thread_state(); 2335 thread->set_thread_state(_thread_in_vm); 2336 #ifndef PRODUCT 2337 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2338 ttyLocker ttyl; 2339 BytecodeCounter::print(); 2340 } 2341 #endif 2342 if (os::message_box(msg, "Execution stopped, print registers?")) { 2343 ttyLocker ttyl; 2344 tty->print_cr(" pc = 0x%016lx", pc); 2345 #ifndef PRODUCT 2346 tty->cr(); 2347 findpc(pc); 2348 tty->cr(); 2349 #endif 2350 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2351 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2352 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2353 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2354 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2355 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2356 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2357 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2358 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2359 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2360 tty->print_cr("r10 = 0x%016lx", regs[10]); 2361 tty->print_cr("r11 = 0x%016lx", regs[11]); 2362 tty->print_cr("r12 = 0x%016lx", regs[12]); 2363 tty->print_cr("r13 = 0x%016lx", regs[13]); 2364 tty->print_cr("r14 = 0x%016lx", regs[14]); 2365 tty->print_cr("r15 = 0x%016lx", regs[15]); 2366 tty->print_cr("r16 = 0x%016lx", regs[16]); 2367 tty->print_cr("r17 = 0x%016lx", regs[17]); 2368 tty->print_cr("r18 = 0x%016lx", regs[18]); 2369 tty->print_cr("r19 = 0x%016lx", regs[19]); 2370 tty->print_cr("r20 = 0x%016lx", regs[20]); 2371 tty->print_cr("r21 = 0x%016lx", regs[21]); 2372 tty->print_cr("r22 = 0x%016lx", regs[22]); 2373 tty->print_cr("r23 = 0x%016lx", regs[23]); 2374 tty->print_cr("r24 = 0x%016lx", regs[24]); 2375 tty->print_cr("r25 = 0x%016lx", regs[25]); 2376 tty->print_cr("r26 = 0x%016lx", regs[26]); 2377 tty->print_cr("r27 = 0x%016lx", regs[27]); 2378 tty->print_cr("r28 = 0x%016lx", regs[28]); 2379 tty->print_cr("r30 = 0x%016lx", regs[30]); 2380 tty->print_cr("r31 = 0x%016lx", regs[31]); 2381 BREAKPOINT; 2382 } 2383 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 2384 } else { 2385 ttyLocker ttyl; 2386 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 2387 msg); 2388 assert(false, "DEBUG MESSAGE: %s", msg); 2389 } 2390 } 2391 2392 #ifdef BUILTIN_SIM 2393 // routine to generate an x86 prolog for a stub function which 2394 // bootstraps into the generated ARM code which directly follows the 2395 // stub 2396 // 2397 // the argument encodes the number of general and fp registers 2398 // passed by the caller and the callng convention (currently just 2399 // the number of general registers and assumes C argument passing) 2400 2401 extern "C" { 2402 int aarch64_stub_prolog_size(); 2403 void aarch64_stub_prolog(); 2404 void aarch64_prolog(); 2405 } 2406 2407 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, 2408 address *prolog_ptr) 2409 { 2410 int calltype = (((ret_type & 0x3) << 8) | 2411 ((fp_arg_count & 0xf) << 4) | 2412 (gp_arg_count & 0xf)); 2413 2414 // the addresses for the x86 to ARM entry code we need to use 2415 address start = pc(); 2416 // printf("start = %lx\n", start); 2417 int byteCount = aarch64_stub_prolog_size(); 2418 // printf("byteCount = %x\n", byteCount); 2419 int instructionCount = (byteCount + 3)/ 4; 2420 // printf("instructionCount = %x\n", instructionCount); 2421 for (int i = 0; i < instructionCount; i++) { 2422 nop(); 2423 } 2424 2425 memcpy(start, (void*)aarch64_stub_prolog, byteCount); 2426 2427 // write the address of the setup routine and the call format at the 2428 // end of into the copied code 2429 u_int64_t *patch_end = (u_int64_t *)(start + byteCount); 2430 if (prolog_ptr) 2431 patch_end[-2] = (u_int64_t)prolog_ptr; 2432 patch_end[-1] = calltype; 2433 } 2434 #endif 2435 2436 void MacroAssembler::push_call_clobbered_registers() { 2437 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2438 2439 // Push v0-v7, v16-v31. 2440 for (int i = 30; i >= 0; i -= 2) { 2441 if (i <= v7->encoding() || i >= v16->encoding()) { 2442 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2443 Address(pre(sp, -2 * wordSize))); 2444 } 2445 } 2446 } 2447 2448 void MacroAssembler::pop_call_clobbered_registers() { 2449 2450 for (int i = 0; i < 32; i += 2) { 2451 if (i <= v7->encoding() || i >= v16->encoding()) { 2452 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2453 Address(post(sp, 2 * wordSize))); 2454 } 2455 } 2456 2457 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2458 } 2459 2460 void MacroAssembler::push_CPU_state(bool save_vectors) { 2461 push(0x3fffffff, sp); // integer registers except lr & sp 2462 2463 if (!save_vectors) { 2464 for (int i = 30; i >= 0; i -= 2) 2465 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2466 Address(pre(sp, -2 * wordSize))); 2467 } else { 2468 for (int i = 30; i >= 0; i -= 2) 2469 stpq(as_FloatRegister(i), as_FloatRegister(i+1), 2470 Address(pre(sp, -4 * wordSize))); 2471 } 2472 } 2473 2474 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2475 if (!restore_vectors) { 2476 for (int i = 0; i < 32; i += 2) 2477 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2478 Address(post(sp, 2 * wordSize))); 2479 } else { 2480 for (int i = 0; i < 32; i += 2) 2481 ldpq(as_FloatRegister(i), as_FloatRegister(i+1), 2482 Address(post(sp, 4 * wordSize))); 2483 } 2484 2485 pop(0x3fffffff, sp); // integer registers except lr & sp 2486 } 2487 2488 /** 2489 * Helpers for multiply_to_len(). 2490 */ 2491 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2492 Register src1, Register src2) { 2493 adds(dest_lo, dest_lo, src1); 2494 adc(dest_hi, dest_hi, zr); 2495 adds(dest_lo, dest_lo, src2); 2496 adc(final_dest_hi, dest_hi, zr); 2497 } 2498 2499 // Generate an address from (r + r1 extend offset). "size" is the 2500 // size of the operand. The result may be in rscratch2. 2501 Address MacroAssembler::offsetted_address(Register r, Register r1, 2502 Address::extend ext, int offset, int size) { 2503 if (offset || (ext.shift() % size != 0)) { 2504 lea(rscratch2, Address(r, r1, ext)); 2505 return Address(rscratch2, offset); 2506 } else { 2507 return Address(r, r1, ext); 2508 } 2509 } 2510 2511 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2512 { 2513 assert(offset >= 0, "spill to negative address?"); 2514 // Offset reachable ? 2515 // Not aligned - 9 bits signed offset 2516 // Aligned - 12 bits unsigned offset shifted 2517 Register base = sp; 2518 if ((offset & (size-1)) && offset >= (1<<8)) { 2519 add(tmp, base, offset & ((1<<12)-1)); 2520 base = tmp; 2521 offset &= -1<<12; 2522 } 2523 2524 if (offset >= (1<<12) * size) { 2525 add(tmp, base, offset & (((1<<12)-1)<<12)); 2526 base = tmp; 2527 offset &= ~(((1<<12)-1)<<12); 2528 } 2529 2530 return Address(base, offset); 2531 } 2532 2533 /** 2534 * Multiply 64 bit by 64 bit first loop. 2535 */ 2536 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2537 Register y, Register y_idx, Register z, 2538 Register carry, Register product, 2539 Register idx, Register kdx) { 2540 // 2541 // jlong carry, x[], y[], z[]; 2542 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2543 // huge_128 product = y[idx] * x[xstart] + carry; 2544 // z[kdx] = (jlong)product; 2545 // carry = (jlong)(product >>> 64); 2546 // } 2547 // z[xstart] = carry; 2548 // 2549 2550 Label L_first_loop, L_first_loop_exit; 2551 Label L_one_x, L_one_y, L_multiply; 2552 2553 subsw(xstart, xstart, 1); 2554 br(Assembler::MI, L_one_x); 2555 2556 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2557 ldr(x_xstart, Address(rscratch1)); 2558 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2559 2560 bind(L_first_loop); 2561 subsw(idx, idx, 1); 2562 br(Assembler::MI, L_first_loop_exit); 2563 subsw(idx, idx, 1); 2564 br(Assembler::MI, L_one_y); 2565 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2566 ldr(y_idx, Address(rscratch1)); 2567 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2568 bind(L_multiply); 2569 2570 // AArch64 has a multiply-accumulate instruction that we can't use 2571 // here because it has no way to process carries, so we have to use 2572 // separate add and adc instructions. Bah. 2573 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2574 mul(product, x_xstart, y_idx); 2575 adds(product, product, carry); 2576 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2577 2578 subw(kdx, kdx, 2); 2579 ror(product, product, 32); // back to big-endian 2580 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2581 2582 b(L_first_loop); 2583 2584 bind(L_one_y); 2585 ldrw(y_idx, Address(y, 0)); 2586 b(L_multiply); 2587 2588 bind(L_one_x); 2589 ldrw(x_xstart, Address(x, 0)); 2590 b(L_first_loop); 2591 2592 bind(L_first_loop_exit); 2593 } 2594 2595 /** 2596 * Multiply 128 bit by 128. Unrolled inner loop. 2597 * 2598 */ 2599 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2600 Register carry, Register carry2, 2601 Register idx, Register jdx, 2602 Register yz_idx1, Register yz_idx2, 2603 Register tmp, Register tmp3, Register tmp4, 2604 Register tmp6, Register product_hi) { 2605 2606 // jlong carry, x[], y[], z[]; 2607 // int kdx = ystart+1; 2608 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2609 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2610 // jlong carry2 = (jlong)(tmp3 >>> 64); 2611 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2612 // carry = (jlong)(tmp4 >>> 64); 2613 // z[kdx+idx+1] = (jlong)tmp3; 2614 // z[kdx+idx] = (jlong)tmp4; 2615 // } 2616 // idx += 2; 2617 // if (idx > 0) { 2618 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2619 // z[kdx+idx] = (jlong)yz_idx1; 2620 // carry = (jlong)(yz_idx1 >>> 64); 2621 // } 2622 // 2623 2624 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2625 2626 lsrw(jdx, idx, 2); 2627 2628 bind(L_third_loop); 2629 2630 subsw(jdx, jdx, 1); 2631 br(Assembler::MI, L_third_loop_exit); 2632 subw(idx, idx, 4); 2633 2634 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2635 2636 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2637 2638 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2639 2640 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2641 ror(yz_idx2, yz_idx2, 32); 2642 2643 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2644 2645 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2646 umulh(tmp4, product_hi, yz_idx1); 2647 2648 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2649 ror(rscratch2, rscratch2, 32); 2650 2651 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2652 umulh(carry2, product_hi, yz_idx2); 2653 2654 // propagate sum of both multiplications into carry:tmp4:tmp3 2655 adds(tmp3, tmp3, carry); 2656 adc(tmp4, tmp4, zr); 2657 adds(tmp3, tmp3, rscratch1); 2658 adcs(tmp4, tmp4, tmp); 2659 adc(carry, carry2, zr); 2660 adds(tmp4, tmp4, rscratch2); 2661 adc(carry, carry, zr); 2662 2663 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2664 ror(tmp4, tmp4, 32); 2665 stp(tmp4, tmp3, Address(tmp6, 0)); 2666 2667 b(L_third_loop); 2668 bind (L_third_loop_exit); 2669 2670 andw (idx, idx, 0x3); 2671 cbz(idx, L_post_third_loop_done); 2672 2673 Label L_check_1; 2674 subsw(idx, idx, 2); 2675 br(Assembler::MI, L_check_1); 2676 2677 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2678 ldr(yz_idx1, Address(rscratch1, 0)); 2679 ror(yz_idx1, yz_idx1, 32); 2680 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2681 umulh(tmp4, product_hi, yz_idx1); 2682 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2683 ldr(yz_idx2, Address(rscratch1, 0)); 2684 ror(yz_idx2, yz_idx2, 32); 2685 2686 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2687 2688 ror(tmp3, tmp3, 32); 2689 str(tmp3, Address(rscratch1, 0)); 2690 2691 bind (L_check_1); 2692 2693 andw (idx, idx, 0x1); 2694 subsw(idx, idx, 1); 2695 br(Assembler::MI, L_post_third_loop_done); 2696 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2697 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2698 umulh(carry2, tmp4, product_hi); 2699 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2700 2701 add2_with_carry(carry2, tmp3, tmp4, carry); 2702 2703 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2704 extr(carry, carry2, tmp3, 32); 2705 2706 bind(L_post_third_loop_done); 2707 } 2708 2709 /** 2710 * Code for BigInteger::multiplyToLen() instrinsic. 2711 * 2712 * r0: x 2713 * r1: xlen 2714 * r2: y 2715 * r3: ylen 2716 * r4: z 2717 * r5: zlen 2718 * r10: tmp1 2719 * r11: tmp2 2720 * r12: tmp3 2721 * r13: tmp4 2722 * r14: tmp5 2723 * r15: tmp6 2724 * r16: tmp7 2725 * 2726 */ 2727 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 2728 Register z, Register zlen, 2729 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 2730 Register tmp5, Register tmp6, Register product_hi) { 2731 2732 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 2733 2734 const Register idx = tmp1; 2735 const Register kdx = tmp2; 2736 const Register xstart = tmp3; 2737 2738 const Register y_idx = tmp4; 2739 const Register carry = tmp5; 2740 const Register product = xlen; 2741 const Register x_xstart = zlen; // reuse register 2742 2743 // First Loop. 2744 // 2745 // final static long LONG_MASK = 0xffffffffL; 2746 // int xstart = xlen - 1; 2747 // int ystart = ylen - 1; 2748 // long carry = 0; 2749 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2750 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 2751 // z[kdx] = (int)product; 2752 // carry = product >>> 32; 2753 // } 2754 // z[xstart] = (int)carry; 2755 // 2756 2757 movw(idx, ylen); // idx = ylen; 2758 movw(kdx, zlen); // kdx = xlen+ylen; 2759 mov(carry, zr); // carry = 0; 2760 2761 Label L_done; 2762 2763 movw(xstart, xlen); 2764 subsw(xstart, xstart, 1); 2765 br(Assembler::MI, L_done); 2766 2767 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 2768 2769 Label L_second_loop; 2770 cbzw(kdx, L_second_loop); 2771 2772 Label L_carry; 2773 subw(kdx, kdx, 1); 2774 cbzw(kdx, L_carry); 2775 2776 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2777 lsr(carry, carry, 32); 2778 subw(kdx, kdx, 1); 2779 2780 bind(L_carry); 2781 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2782 2783 // Second and third (nested) loops. 2784 // 2785 // for (int i = xstart-1; i >= 0; i--) { // Second loop 2786 // carry = 0; 2787 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 2788 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 2789 // (z[k] & LONG_MASK) + carry; 2790 // z[k] = (int)product; 2791 // carry = product >>> 32; 2792 // } 2793 // z[i] = (int)carry; 2794 // } 2795 // 2796 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 2797 2798 const Register jdx = tmp1; 2799 2800 bind(L_second_loop); 2801 mov(carry, zr); // carry = 0; 2802 movw(jdx, ylen); // j = ystart+1 2803 2804 subsw(xstart, xstart, 1); // i = xstart-1; 2805 br(Assembler::MI, L_done); 2806 2807 str(z, Address(pre(sp, -4 * wordSize))); 2808 2809 Label L_last_x; 2810 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 2811 subsw(xstart, xstart, 1); // i = xstart-1; 2812 br(Assembler::MI, L_last_x); 2813 2814 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 2815 ldr(product_hi, Address(rscratch1)); 2816 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 2817 2818 Label L_third_loop_prologue; 2819 bind(L_third_loop_prologue); 2820 2821 str(ylen, Address(sp, wordSize)); 2822 stp(x, xstart, Address(sp, 2 * wordSize)); 2823 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 2824 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 2825 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 2826 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 2827 2828 addw(tmp3, xlen, 1); 2829 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2830 subsw(tmp3, tmp3, 1); 2831 br(Assembler::MI, L_done); 2832 2833 lsr(carry, carry, 32); 2834 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2835 b(L_second_loop); 2836 2837 // Next infrequent code is moved outside loops. 2838 bind(L_last_x); 2839 ldrw(product_hi, Address(x, 0)); 2840 b(L_third_loop_prologue); 2841 2842 bind(L_done); 2843 } 2844 2845 /** 2846 * Emits code to update CRC-32 with a byte value according to constants in table 2847 * 2848 * @param [in,out]crc Register containing the crc. 2849 * @param [in]val Register containing the byte to fold into the CRC. 2850 * @param [in]table Register containing the table of crc constants. 2851 * 2852 * uint32_t crc; 2853 * val = crc_table[(val ^ crc) & 0xFF]; 2854 * crc = val ^ (crc >> 8); 2855 * 2856 */ 2857 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 2858 eor(val, val, crc); 2859 andr(val, val, 0xff); 2860 ldrw(val, Address(table, val, Address::lsl(2))); 2861 eor(crc, val, crc, Assembler::LSR, 8); 2862 } 2863 2864 /** 2865 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 2866 * 2867 * @param [in,out]crc Register containing the crc. 2868 * @param [in]v Register containing the 32-bit to fold into the CRC. 2869 * @param [in]table0 Register containing table 0 of crc constants. 2870 * @param [in]table1 Register containing table 1 of crc constants. 2871 * @param [in]table2 Register containing table 2 of crc constants. 2872 * @param [in]table3 Register containing table 3 of crc constants. 2873 * 2874 * uint32_t crc; 2875 * v = crc ^ v 2876 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 2877 * 2878 */ 2879 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 2880 Register table0, Register table1, Register table2, Register table3, 2881 bool upper) { 2882 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 2883 uxtb(tmp, v); 2884 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 2885 ubfx(tmp, v, 8, 8); 2886 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 2887 eor(crc, crc, tmp); 2888 ubfx(tmp, v, 16, 8); 2889 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 2890 eor(crc, crc, tmp); 2891 ubfx(tmp, v, 24, 8); 2892 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 2893 eor(crc, crc, tmp); 2894 } 2895 2896 /** 2897 * @param crc register containing existing CRC (32-bit) 2898 * @param buf register pointing to input byte buffer (byte*) 2899 * @param len register containing number of bytes 2900 * @param table register that will contain address of CRC table 2901 * @param tmp scratch register 2902 */ 2903 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 2904 Register table0, Register table1, Register table2, Register table3, 2905 Register tmp, Register tmp2, Register tmp3) { 2906 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 2907 unsigned long offset; 2908 2909 ornw(crc, zr, crc); 2910 2911 if (UseCRC32) { 2912 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 2913 2914 subs(len, len, 64); 2915 br(Assembler::GE, CRC_by64_loop); 2916 adds(len, len, 64-4); 2917 br(Assembler::GE, CRC_by4_loop); 2918 adds(len, len, 4); 2919 br(Assembler::GT, CRC_by1_loop); 2920 b(L_exit); 2921 2922 BIND(CRC_by4_loop); 2923 ldrw(tmp, Address(post(buf, 4))); 2924 subs(len, len, 4); 2925 crc32w(crc, crc, tmp); 2926 br(Assembler::GE, CRC_by4_loop); 2927 adds(len, len, 4); 2928 br(Assembler::LE, L_exit); 2929 BIND(CRC_by1_loop); 2930 ldrb(tmp, Address(post(buf, 1))); 2931 subs(len, len, 1); 2932 crc32b(crc, crc, tmp); 2933 br(Assembler::GT, CRC_by1_loop); 2934 b(L_exit); 2935 2936 align(CodeEntryAlignment); 2937 BIND(CRC_by64_loop); 2938 subs(len, len, 64); 2939 ldp(tmp, tmp3, Address(post(buf, 16))); 2940 crc32x(crc, crc, tmp); 2941 crc32x(crc, crc, tmp3); 2942 ldp(tmp, tmp3, Address(post(buf, 16))); 2943 crc32x(crc, crc, tmp); 2944 crc32x(crc, crc, tmp3); 2945 ldp(tmp, tmp3, Address(post(buf, 16))); 2946 crc32x(crc, crc, tmp); 2947 crc32x(crc, crc, tmp3); 2948 ldp(tmp, tmp3, Address(post(buf, 16))); 2949 crc32x(crc, crc, tmp); 2950 crc32x(crc, crc, tmp3); 2951 br(Assembler::GE, CRC_by64_loop); 2952 adds(len, len, 64-4); 2953 br(Assembler::GE, CRC_by4_loop); 2954 adds(len, len, 4); 2955 br(Assembler::GT, CRC_by1_loop); 2956 BIND(L_exit); 2957 ornw(crc, zr, crc); 2958 return; 2959 } 2960 2961 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2962 if (offset) add(table0, table0, offset); 2963 add(table1, table0, 1*256*sizeof(juint)); 2964 add(table2, table0, 2*256*sizeof(juint)); 2965 add(table3, table0, 3*256*sizeof(juint)); 2966 2967 if (UseNeon) { 2968 cmp(len, 64); 2969 br(Assembler::LT, L_by16); 2970 eor(v16, T16B, v16, v16); 2971 2972 Label L_fold; 2973 2974 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 2975 2976 ld1(v0, v1, T2D, post(buf, 32)); 2977 ld1r(v4, T2D, post(tmp, 8)); 2978 ld1r(v5, T2D, post(tmp, 8)); 2979 ld1r(v6, T2D, post(tmp, 8)); 2980 ld1r(v7, T2D, post(tmp, 8)); 2981 mov(v16, T4S, 0, crc); 2982 2983 eor(v0, T16B, v0, v16); 2984 sub(len, len, 64); 2985 2986 BIND(L_fold); 2987 pmull(v22, T8H, v0, v5, T8B); 2988 pmull(v20, T8H, v0, v7, T8B); 2989 pmull(v23, T8H, v0, v4, T8B); 2990 pmull(v21, T8H, v0, v6, T8B); 2991 2992 pmull2(v18, T8H, v0, v5, T16B); 2993 pmull2(v16, T8H, v0, v7, T16B); 2994 pmull2(v19, T8H, v0, v4, T16B); 2995 pmull2(v17, T8H, v0, v6, T16B); 2996 2997 uzp1(v24, v20, v22, T8H); 2998 uzp2(v25, v20, v22, T8H); 2999 eor(v20, T16B, v24, v25); 3000 3001 uzp1(v26, v16, v18, T8H); 3002 uzp2(v27, v16, v18, T8H); 3003 eor(v16, T16B, v26, v27); 3004 3005 ushll2(v22, T4S, v20, T8H, 8); 3006 ushll(v20, T4S, v20, T4H, 8); 3007 3008 ushll2(v18, T4S, v16, T8H, 8); 3009 ushll(v16, T4S, v16, T4H, 8); 3010 3011 eor(v22, T16B, v23, v22); 3012 eor(v18, T16B, v19, v18); 3013 eor(v20, T16B, v21, v20); 3014 eor(v16, T16B, v17, v16); 3015 3016 uzp1(v17, v16, v20, T2D); 3017 uzp2(v21, v16, v20, T2D); 3018 eor(v17, T16B, v17, v21); 3019 3020 ushll2(v20, T2D, v17, T4S, 16); 3021 ushll(v16, T2D, v17, T2S, 16); 3022 3023 eor(v20, T16B, v20, v22); 3024 eor(v16, T16B, v16, v18); 3025 3026 uzp1(v17, v20, v16, T2D); 3027 uzp2(v21, v20, v16, T2D); 3028 eor(v28, T16B, v17, v21); 3029 3030 pmull(v22, T8H, v1, v5, T8B); 3031 pmull(v20, T8H, v1, v7, T8B); 3032 pmull(v23, T8H, v1, v4, T8B); 3033 pmull(v21, T8H, v1, v6, T8B); 3034 3035 pmull2(v18, T8H, v1, v5, T16B); 3036 pmull2(v16, T8H, v1, v7, T16B); 3037 pmull2(v19, T8H, v1, v4, T16B); 3038 pmull2(v17, T8H, v1, v6, T16B); 3039 3040 ld1(v0, v1, T2D, post(buf, 32)); 3041 3042 uzp1(v24, v20, v22, T8H); 3043 uzp2(v25, v20, v22, T8H); 3044 eor(v20, T16B, v24, v25); 3045 3046 uzp1(v26, v16, v18, T8H); 3047 uzp2(v27, v16, v18, T8H); 3048 eor(v16, T16B, v26, v27); 3049 3050 ushll2(v22, T4S, v20, T8H, 8); 3051 ushll(v20, T4S, v20, T4H, 8); 3052 3053 ushll2(v18, T4S, v16, T8H, 8); 3054 ushll(v16, T4S, v16, T4H, 8); 3055 3056 eor(v22, T16B, v23, v22); 3057 eor(v18, T16B, v19, v18); 3058 eor(v20, T16B, v21, v20); 3059 eor(v16, T16B, v17, v16); 3060 3061 uzp1(v17, v16, v20, T2D); 3062 uzp2(v21, v16, v20, T2D); 3063 eor(v16, T16B, v17, v21); 3064 3065 ushll2(v20, T2D, v16, T4S, 16); 3066 ushll(v16, T2D, v16, T2S, 16); 3067 3068 eor(v20, T16B, v22, v20); 3069 eor(v16, T16B, v16, v18); 3070 3071 uzp1(v17, v20, v16, T2D); 3072 uzp2(v21, v20, v16, T2D); 3073 eor(v20, T16B, v17, v21); 3074 3075 shl(v16, T2D, v28, 1); 3076 shl(v17, T2D, v20, 1); 3077 3078 eor(v0, T16B, v0, v16); 3079 eor(v1, T16B, v1, v17); 3080 3081 subs(len, len, 32); 3082 br(Assembler::GE, L_fold); 3083 3084 mov(crc, 0); 3085 mov(tmp, v0, T1D, 0); 3086 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3087 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3088 mov(tmp, v0, T1D, 1); 3089 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3090 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3091 mov(tmp, v1, T1D, 0); 3092 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3093 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3094 mov(tmp, v1, T1D, 1); 3095 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3096 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3097 3098 add(len, len, 32); 3099 } 3100 3101 BIND(L_by16); 3102 subs(len, len, 16); 3103 br(Assembler::GE, L_by16_loop); 3104 adds(len, len, 16-4); 3105 br(Assembler::GE, L_by4_loop); 3106 adds(len, len, 4); 3107 br(Assembler::GT, L_by1_loop); 3108 b(L_exit); 3109 3110 BIND(L_by4_loop); 3111 ldrw(tmp, Address(post(buf, 4))); 3112 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 3113 subs(len, len, 4); 3114 br(Assembler::GE, L_by4_loop); 3115 adds(len, len, 4); 3116 br(Assembler::LE, L_exit); 3117 BIND(L_by1_loop); 3118 subs(len, len, 1); 3119 ldrb(tmp, Address(post(buf, 1))); 3120 update_byte_crc32(crc, tmp, table0); 3121 br(Assembler::GT, L_by1_loop); 3122 b(L_exit); 3123 3124 align(CodeEntryAlignment); 3125 BIND(L_by16_loop); 3126 subs(len, len, 16); 3127 ldp(tmp, tmp3, Address(post(buf, 16))); 3128 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3129 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3130 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 3131 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 3132 br(Assembler::GE, L_by16_loop); 3133 adds(len, len, 16-4); 3134 br(Assembler::GE, L_by4_loop); 3135 adds(len, len, 4); 3136 br(Assembler::GT, L_by1_loop); 3137 BIND(L_exit); 3138 ornw(crc, zr, crc); 3139 } 3140 3141 /** 3142 * @param crc register containing existing CRC (32-bit) 3143 * @param buf register pointing to input byte buffer (byte*) 3144 * @param len register containing number of bytes 3145 * @param table register that will contain address of CRC table 3146 * @param tmp scratch register 3147 */ 3148 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3149 Register table0, Register table1, Register table2, Register table3, 3150 Register tmp, Register tmp2, Register tmp3) { 3151 Label L_exit; 3152 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 3153 3154 subs(len, len, 64); 3155 br(Assembler::GE, CRC_by64_loop); 3156 adds(len, len, 64-4); 3157 br(Assembler::GE, CRC_by4_loop); 3158 adds(len, len, 4); 3159 br(Assembler::GT, CRC_by1_loop); 3160 b(L_exit); 3161 3162 BIND(CRC_by4_loop); 3163 ldrw(tmp, Address(post(buf, 4))); 3164 subs(len, len, 4); 3165 crc32cw(crc, crc, tmp); 3166 br(Assembler::GE, CRC_by4_loop); 3167 adds(len, len, 4); 3168 br(Assembler::LE, L_exit); 3169 BIND(CRC_by1_loop); 3170 ldrb(tmp, Address(post(buf, 1))); 3171 subs(len, len, 1); 3172 crc32cb(crc, crc, tmp); 3173 br(Assembler::GT, CRC_by1_loop); 3174 b(L_exit); 3175 3176 align(CodeEntryAlignment); 3177 BIND(CRC_by64_loop); 3178 subs(len, len, 64); 3179 ldp(tmp, tmp3, Address(post(buf, 16))); 3180 crc32cx(crc, crc, tmp); 3181 crc32cx(crc, crc, tmp3); 3182 ldp(tmp, tmp3, Address(post(buf, 16))); 3183 crc32cx(crc, crc, tmp); 3184 crc32cx(crc, crc, tmp3); 3185 ldp(tmp, tmp3, Address(post(buf, 16))); 3186 crc32cx(crc, crc, tmp); 3187 crc32cx(crc, crc, tmp3); 3188 ldp(tmp, tmp3, Address(post(buf, 16))); 3189 crc32cx(crc, crc, tmp); 3190 crc32cx(crc, crc, tmp3); 3191 br(Assembler::GE, CRC_by64_loop); 3192 adds(len, len, 64-4); 3193 br(Assembler::GE, CRC_by4_loop); 3194 adds(len, len, 4); 3195 br(Assembler::GT, CRC_by1_loop); 3196 BIND(L_exit); 3197 return; 3198 } 3199 3200 SkipIfEqual::SkipIfEqual( 3201 MacroAssembler* masm, const bool* flag_addr, bool value) { 3202 _masm = masm; 3203 unsigned long offset; 3204 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3205 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3206 _masm->cbzw(rscratch1, _label); 3207 } 3208 3209 SkipIfEqual::~SkipIfEqual() { 3210 _masm->bind(_label); 3211 } 3212 3213 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3214 Address adr; 3215 switch(dst.getMode()) { 3216 case Address::base_plus_offset: 3217 // This is the expected mode, although we allow all the other 3218 // forms below. 3219 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3220 break; 3221 default: 3222 lea(rscratch2, dst); 3223 adr = Address(rscratch2); 3224 break; 3225 } 3226 ldr(rscratch1, adr); 3227 add(rscratch1, rscratch1, src); 3228 str(rscratch1, adr); 3229 } 3230 3231 void MacroAssembler::cmpptr(Register src1, Address src2) { 3232 unsigned long offset; 3233 adrp(rscratch1, src2, offset); 3234 ldr(rscratch1, Address(rscratch1, offset)); 3235 cmp(src1, rscratch1); 3236 } 3237 3238 void MacroAssembler::store_check(Register obj, Address dst) { 3239 store_check(obj); 3240 } 3241 3242 void MacroAssembler::store_check(Register obj) { 3243 // Does a store check for the oop in register obj. The content of 3244 // register obj is destroyed afterwards. 3245 3246 BarrierSet* bs = Universe::heap()->barrier_set(); 3247 assert(bs->kind() == BarrierSet::CardTableModRef, 3248 "Wrong barrier set kind"); 3249 3250 CardTableModRefBS* ctbs = barrier_set_cast<CardTableModRefBS>(bs); 3251 CardTable* ct = ctbs->card_table(); 3252 assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "adjust this code"); 3253 3254 lsr(obj, obj, CardTable::card_shift); 3255 3256 assert(CardTable::dirty_card_val() == 0, "must be"); 3257 3258 load_byte_map_base(rscratch1); 3259 3260 if (UseCondCardMark) { 3261 Label L_already_dirty; 3262 membar(StoreLoad); 3263 ldrb(rscratch2, Address(obj, rscratch1)); 3264 cbz(rscratch2, L_already_dirty); 3265 strb(zr, Address(obj, rscratch1)); 3266 bind(L_already_dirty); 3267 } else { 3268 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) { 3269 membar(StoreStore); 3270 } 3271 strb(zr, Address(obj, rscratch1)); 3272 } 3273 } 3274 3275 void MacroAssembler::load_klass(Register dst, Register src) { 3276 if (UseCompressedClassPointers) { 3277 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3278 decode_klass_not_null(dst); 3279 } else { 3280 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3281 } 3282 } 3283 3284 // ((OopHandle)result).resolve(); 3285 void MacroAssembler::resolve_oop_handle(Register result) { 3286 // OopHandle::resolve is an indirection. 3287 ldr(result, Address(result, 0)); 3288 } 3289 3290 void MacroAssembler::load_mirror(Register dst, Register method) { 3291 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 3292 ldr(dst, Address(rmethod, Method::const_offset())); 3293 ldr(dst, Address(dst, ConstMethod::constants_offset())); 3294 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes())); 3295 ldr(dst, Address(dst, mirror_offset)); 3296 } 3297 3298 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3299 if (UseCompressedClassPointers) { 3300 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3301 if (Universe::narrow_klass_base() == NULL) { 3302 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); 3303 return; 3304 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3305 && Universe::narrow_klass_shift() == 0) { 3306 // Only the bottom 32 bits matter 3307 cmpw(trial_klass, tmp); 3308 return; 3309 } 3310 decode_klass_not_null(tmp); 3311 } else { 3312 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3313 } 3314 cmp(trial_klass, tmp); 3315 } 3316 3317 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3318 load_klass(dst, src); 3319 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3320 } 3321 3322 void MacroAssembler::store_klass(Register dst, Register src) { 3323 // FIXME: Should this be a store release? concurrent gcs assumes 3324 // klass length is valid if klass field is not null. 3325 if (UseCompressedClassPointers) { 3326 encode_klass_not_null(src); 3327 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3328 } else { 3329 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3330 } 3331 } 3332 3333 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3334 if (UseCompressedClassPointers) { 3335 // Store to klass gap in destination 3336 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3337 } 3338 } 3339 3340 // Algorithm must match oop.inline.hpp encode_heap_oop. 3341 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3342 #ifdef ASSERT 3343 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3344 #endif 3345 verify_oop(s, "broken oop in encode_heap_oop"); 3346 if (Universe::narrow_oop_base() == NULL) { 3347 if (Universe::narrow_oop_shift() != 0) { 3348 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3349 lsr(d, s, LogMinObjAlignmentInBytes); 3350 } else { 3351 mov(d, s); 3352 } 3353 } else { 3354 subs(d, s, rheapbase); 3355 csel(d, d, zr, Assembler::HS); 3356 lsr(d, d, LogMinObjAlignmentInBytes); 3357 3358 /* Old algorithm: is this any worse? 3359 Label nonnull; 3360 cbnz(r, nonnull); 3361 sub(r, r, rheapbase); 3362 bind(nonnull); 3363 lsr(r, r, LogMinObjAlignmentInBytes); 3364 */ 3365 } 3366 } 3367 3368 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3369 #ifdef ASSERT 3370 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3371 if (CheckCompressedOops) { 3372 Label ok; 3373 cbnz(r, ok); 3374 stop("null oop passed to encode_heap_oop_not_null"); 3375 bind(ok); 3376 } 3377 #endif 3378 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3379 if (Universe::narrow_oop_base() != NULL) { 3380 sub(r, r, rheapbase); 3381 } 3382 if (Universe::narrow_oop_shift() != 0) { 3383 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3384 lsr(r, r, LogMinObjAlignmentInBytes); 3385 } 3386 } 3387 3388 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3389 #ifdef ASSERT 3390 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3391 if (CheckCompressedOops) { 3392 Label ok; 3393 cbnz(src, ok); 3394 stop("null oop passed to encode_heap_oop_not_null2"); 3395 bind(ok); 3396 } 3397 #endif 3398 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3399 3400 Register data = src; 3401 if (Universe::narrow_oop_base() != NULL) { 3402 sub(dst, src, rheapbase); 3403 data = dst; 3404 } 3405 if (Universe::narrow_oop_shift() != 0) { 3406 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3407 lsr(dst, data, LogMinObjAlignmentInBytes); 3408 data = dst; 3409 } 3410 if (data == src) 3411 mov(dst, src); 3412 } 3413 3414 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3415 #ifdef ASSERT 3416 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3417 #endif 3418 if (Universe::narrow_oop_base() == NULL) { 3419 if (Universe::narrow_oop_shift() != 0 || d != s) { 3420 lsl(d, s, Universe::narrow_oop_shift()); 3421 } 3422 } else { 3423 Label done; 3424 if (d != s) 3425 mov(d, s); 3426 cbz(s, done); 3427 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3428 bind(done); 3429 } 3430 verify_oop(d, "broken oop in decode_heap_oop"); 3431 } 3432 3433 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3434 assert (UseCompressedOops, "should only be used for compressed headers"); 3435 assert (Universe::heap() != NULL, "java heap should be initialized"); 3436 // Cannot assert, unverified entry point counts instructions (see .ad file) 3437 // vtableStubs also counts instructions in pd_code_size_limit. 3438 // Also do not verify_oop as this is called by verify_oop. 3439 if (Universe::narrow_oop_shift() != 0) { 3440 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3441 if (Universe::narrow_oop_base() != NULL) { 3442 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3443 } else { 3444 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3445 } 3446 } else { 3447 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3448 } 3449 } 3450 3451 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3452 assert (UseCompressedOops, "should only be used for compressed headers"); 3453 assert (Universe::heap() != NULL, "java heap should be initialized"); 3454 // Cannot assert, unverified entry point counts instructions (see .ad file) 3455 // vtableStubs also counts instructions in pd_code_size_limit. 3456 // Also do not verify_oop as this is called by verify_oop. 3457 if (Universe::narrow_oop_shift() != 0) { 3458 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3459 if (Universe::narrow_oop_base() != NULL) { 3460 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3461 } else { 3462 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3463 } 3464 } else { 3465 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3466 if (dst != src) { 3467 mov(dst, src); 3468 } 3469 } 3470 } 3471 3472 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3473 if (Universe::narrow_klass_base() == NULL) { 3474 if (Universe::narrow_klass_shift() != 0) { 3475 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3476 lsr(dst, src, LogKlassAlignmentInBytes); 3477 } else { 3478 if (dst != src) mov(dst, src); 3479 } 3480 return; 3481 } 3482 3483 if (use_XOR_for_compressed_class_base) { 3484 if (Universe::narrow_klass_shift() != 0) { 3485 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3486 lsr(dst, dst, LogKlassAlignmentInBytes); 3487 } else { 3488 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3489 } 3490 return; 3491 } 3492 3493 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3494 && Universe::narrow_klass_shift() == 0) { 3495 movw(dst, src); 3496 return; 3497 } 3498 3499 #ifdef ASSERT 3500 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 3501 #endif 3502 3503 Register rbase = dst; 3504 if (dst == src) rbase = rheapbase; 3505 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3506 sub(dst, src, rbase); 3507 if (Universe::narrow_klass_shift() != 0) { 3508 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3509 lsr(dst, dst, LogKlassAlignmentInBytes); 3510 } 3511 if (dst == src) reinit_heapbase(); 3512 } 3513 3514 void MacroAssembler::encode_klass_not_null(Register r) { 3515 encode_klass_not_null(r, r); 3516 } 3517 3518 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3519 Register rbase = dst; 3520 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3521 3522 if (Universe::narrow_klass_base() == NULL) { 3523 if (Universe::narrow_klass_shift() != 0) { 3524 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3525 lsl(dst, src, LogKlassAlignmentInBytes); 3526 } else { 3527 if (dst != src) mov(dst, src); 3528 } 3529 return; 3530 } 3531 3532 if (use_XOR_for_compressed_class_base) { 3533 if (Universe::narrow_klass_shift() != 0) { 3534 lsl(dst, src, LogKlassAlignmentInBytes); 3535 eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); 3536 } else { 3537 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3538 } 3539 return; 3540 } 3541 3542 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3543 && Universe::narrow_klass_shift() == 0) { 3544 if (dst != src) 3545 movw(dst, src); 3546 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); 3547 return; 3548 } 3549 3550 // Cannot assert, unverified entry point counts instructions (see .ad file) 3551 // vtableStubs also counts instructions in pd_code_size_limit. 3552 // Also do not verify_oop as this is called by verify_oop. 3553 if (dst == src) rbase = rheapbase; 3554 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3555 if (Universe::narrow_klass_shift() != 0) { 3556 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3557 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 3558 } else { 3559 add(dst, rbase, src); 3560 } 3561 if (dst == src) reinit_heapbase(); 3562 } 3563 3564 void MacroAssembler::decode_klass_not_null(Register r) { 3565 decode_klass_not_null(r, r); 3566 } 3567 3568 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 3569 assert (UseCompressedOops, "should only be used for compressed oops"); 3570 assert (Universe::heap() != NULL, "java heap should be initialized"); 3571 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3572 3573 int oop_index = oop_recorder()->find_index(obj); 3574 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3575 3576 InstructionMark im(this); 3577 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3578 code_section()->relocate(inst_mark(), rspec); 3579 movz(dst, 0xDEAD, 16); 3580 movk(dst, 0xBEEF); 3581 } 3582 3583 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 3584 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3585 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3586 int index = oop_recorder()->find_index(k); 3587 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); 3588 3589 InstructionMark im(this); 3590 RelocationHolder rspec = metadata_Relocation::spec(index); 3591 code_section()->relocate(inst_mark(), rspec); 3592 narrowKlass nk = Klass::encode_klass(k); 3593 movz(dst, (nk >> 16), 16); 3594 movk(dst, nk & 0xffff); 3595 } 3596 3597 void MacroAssembler::load_heap_oop(Register dst, Address src) 3598 { 3599 if (UseCompressedOops) { 3600 ldrw(dst, src); 3601 decode_heap_oop(dst); 3602 } else { 3603 ldr(dst, src); 3604 } 3605 } 3606 3607 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) 3608 { 3609 if (UseCompressedOops) { 3610 ldrw(dst, src); 3611 decode_heap_oop_not_null(dst); 3612 } else { 3613 ldr(dst, src); 3614 } 3615 } 3616 3617 void MacroAssembler::store_heap_oop(Address dst, Register src) { 3618 if (UseCompressedOops) { 3619 assert(!dst.uses(src), "not enough registers"); 3620 encode_heap_oop(src); 3621 strw(src, dst); 3622 } else 3623 str(src, dst); 3624 } 3625 3626 // Used for storing NULLs. 3627 void MacroAssembler::store_heap_oop_null(Address dst) { 3628 if (UseCompressedOops) { 3629 strw(zr, dst); 3630 } else 3631 str(zr, dst); 3632 } 3633 3634 #if INCLUDE_ALL_GCS 3635 /* 3636 * g1_write_barrier_pre -- G1GC pre-write barrier for store of new_val at 3637 * store_addr. 3638 * 3639 * Allocates rscratch1 3640 */ 3641 void MacroAssembler::g1_write_barrier_pre(Register obj, 3642 Register pre_val, 3643 Register thread, 3644 Register tmp, 3645 bool tosca_live, 3646 bool expand_call) { 3647 // If expand_call is true then we expand the call_VM_leaf macro 3648 // directly to skip generating the check by 3649 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 3650 3651 assert(thread == rthread, "must be"); 3652 3653 Label done; 3654 Label runtime; 3655 3656 assert_different_registers(obj, pre_val, tmp, rscratch1); 3657 assert(pre_val != noreg && tmp != noreg, "expecting a register"); 3658 3659 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3660 SATBMarkQueue::byte_offset_of_active())); 3661 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3662 SATBMarkQueue::byte_offset_of_index())); 3663 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3664 SATBMarkQueue::byte_offset_of_buf())); 3665 3666 3667 // Is marking active? 3668 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3669 ldrw(tmp, in_progress); 3670 } else { 3671 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 3672 ldrb(tmp, in_progress); 3673 } 3674 cbzw(tmp, done); 3675 3676 // Do we need to load the previous value? 3677 if (obj != noreg) { 3678 load_heap_oop(pre_val, Address(obj, 0)); 3679 } 3680 3681 // Is the previous value null? 3682 cbz(pre_val, done); 3683 3684 // Can we store original value in the thread's buffer? 3685 // Is index == 0? 3686 // (The index field is typed as size_t.) 3687 3688 ldr(tmp, index); // tmp := *index_adr 3689 cbz(tmp, runtime); // tmp == 0? 3690 // If yes, goto runtime 3691 3692 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize 3693 str(tmp, index); // *index_adr := tmp 3694 ldr(rscratch1, buffer); 3695 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr 3696 3697 // Record the previous value 3698 str(pre_val, Address(tmp, 0)); 3699 b(done); 3700 3701 bind(runtime); 3702 // save the live input values 3703 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3704 3705 // Calling the runtime using the regular call_VM_leaf mechanism generates 3706 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 3707 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. 3708 // 3709 // If we care generating the pre-barrier without a frame (e.g. in the 3710 // intrinsified Reference.get() routine) then ebp might be pointing to 3711 // the caller frame and so this check will most likely fail at runtime. 3712 // 3713 // Expanding the call directly bypasses the generation of the check. 3714 // So when we do not have have a full interpreter frame on the stack 3715 // expand_call should be passed true. 3716 3717 if (expand_call) { 3718 assert(pre_val != c_rarg1, "smashed arg"); 3719 pass_arg1(this, thread); 3720 pass_arg0(this, pre_val); 3721 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 3722 } else { 3723 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 3724 } 3725 3726 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3727 3728 bind(done); 3729 } 3730 3731 /* 3732 * g1_write_barrier_post -- G1GC post-write barrier for store of new_val at 3733 * store_addr 3734 * 3735 * Allocates rscratch1 3736 */ 3737 void MacroAssembler::g1_write_barrier_post(Register store_addr, 3738 Register new_val, 3739 Register thread, 3740 Register tmp, 3741 Register tmp2) { 3742 assert(thread == rthread, "must be"); 3743 assert_different_registers(store_addr, new_val, thread, tmp, tmp2, 3744 rscratch1); 3745 assert(store_addr != noreg && new_val != noreg && tmp != noreg 3746 && tmp2 != noreg, "expecting a register"); 3747 3748 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3749 DirtyCardQueue::byte_offset_of_index())); 3750 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3751 DirtyCardQueue::byte_offset_of_buf())); 3752 3753 BarrierSet* bs = Universe::heap()->barrier_set(); 3754 CardTableModRefBS* ctbs = barrier_set_cast<CardTableModRefBS>(bs); 3755 CardTable* ct = ctbs->card_table(); 3756 assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "adjust this code"); 3757 3758 Label done; 3759 Label runtime; 3760 3761 // Does store cross heap regions? 3762 3763 eor(tmp, store_addr, new_val); 3764 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes); 3765 cbz(tmp, done); 3766 3767 // crosses regions, storing NULL? 3768 3769 cbz(new_val, done); 3770 3771 // storing region crossing non-NULL, is card already dirty? 3772 3773 ExternalAddress cardtable((address) ct->byte_map_base()); 3774 assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "adjust this code"); 3775 const Register card_addr = tmp; 3776 3777 lsr(card_addr, store_addr, CardTable::card_shift); 3778 3779 // get the address of the card 3780 load_byte_map_base(tmp2); 3781 add(card_addr, card_addr, tmp2); 3782 ldrb(tmp2, Address(card_addr)); 3783 cmpw(tmp2, (int)G1CardTable::g1_young_card_val()); 3784 br(Assembler::EQ, done); 3785 3786 assert((int)CardTable::dirty_card_val() == 0, "must be 0"); 3787 3788 membar(Assembler::StoreLoad); 3789 3790 ldrb(tmp2, Address(card_addr)); 3791 cbzw(tmp2, done); 3792 3793 // storing a region crossing, non-NULL oop, card is clean. 3794 // dirty card and log. 3795 3796 strb(zr, Address(card_addr)); 3797 3798 ldr(rscratch1, queue_index); 3799 cbz(rscratch1, runtime); 3800 sub(rscratch1, rscratch1, wordSize); 3801 str(rscratch1, queue_index); 3802 3803 ldr(tmp2, buffer); 3804 str(card_addr, Address(tmp2, rscratch1)); 3805 b(done); 3806 3807 bind(runtime); 3808 // save the live input values 3809 push(store_addr->bit(true) | new_val->bit(true), sp); 3810 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 3811 pop(store_addr->bit(true) | new_val->bit(true), sp); 3812 3813 bind(done); 3814 } 3815 3816 #endif // INCLUDE_ALL_GCS 3817 3818 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 3819 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 3820 int index = oop_recorder()->allocate_metadata_index(obj); 3821 RelocationHolder rspec = metadata_Relocation::spec(index); 3822 return Address((address)obj, rspec); 3823 } 3824 3825 // Move an oop into a register. immediate is true if we want 3826 // immediate instrcutions, i.e. we are not going to patch this 3827 // instruction while the code is being executed by another thread. In 3828 // that case we can use move immediates rather than the constant pool. 3829 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 3830 int oop_index; 3831 if (obj == NULL) { 3832 oop_index = oop_recorder()->allocate_oop_index(obj); 3833 } else { 3834 oop_index = oop_recorder()->find_index(obj); 3835 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3836 } 3837 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3838 if (! immediate) { 3839 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 3840 ldr_constant(dst, Address(dummy, rspec)); 3841 } else 3842 mov(dst, Address((address)obj, rspec)); 3843 } 3844 3845 // Move a metadata address into a register. 3846 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 3847 int oop_index; 3848 if (obj == NULL) { 3849 oop_index = oop_recorder()->allocate_metadata_index(obj); 3850 } else { 3851 oop_index = oop_recorder()->find_index(obj); 3852 } 3853 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 3854 mov(dst, Address((address)obj, rspec)); 3855 } 3856 3857 Address MacroAssembler::constant_oop_address(jobject obj) { 3858 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3859 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 3860 int oop_index = oop_recorder()->find_index(obj); 3861 return Address((address)obj, oop_Relocation::spec(oop_index)); 3862 } 3863 3864 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3865 void MacroAssembler::tlab_allocate(Register obj, 3866 Register var_size_in_bytes, 3867 int con_size_in_bytes, 3868 Register t1, 3869 Register t2, 3870 Label& slow_case) { 3871 assert_different_registers(obj, t2); 3872 assert_different_registers(obj, var_size_in_bytes); 3873 Register end = t2; 3874 3875 // verify_tlab(); 3876 3877 ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); 3878 if (var_size_in_bytes == noreg) { 3879 lea(end, Address(obj, con_size_in_bytes)); 3880 } else { 3881 lea(end, Address(obj, var_size_in_bytes)); 3882 } 3883 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); 3884 cmp(end, rscratch1); 3885 br(Assembler::HI, slow_case); 3886 3887 // update the tlab top pointer 3888 str(end, Address(rthread, JavaThread::tlab_top_offset())); 3889 3890 // recover var_size_in_bytes if necessary 3891 if (var_size_in_bytes == end) { 3892 sub(var_size_in_bytes, var_size_in_bytes, obj); 3893 } 3894 // verify_tlab(); 3895 } 3896 3897 // Preserves r19, and r3. 3898 Register MacroAssembler::tlab_refill(Label& retry, 3899 Label& try_eden, 3900 Label& slow_case) { 3901 Register top = r0; 3902 Register t1 = r2; 3903 Register t2 = r4; 3904 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3); 3905 Label do_refill, discard_tlab; 3906 3907 if (!Universe::heap()->supports_inline_contig_alloc()) { 3908 // No allocation in the shared eden. 3909 b(slow_case); 3910 } 3911 3912 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3913 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3914 3915 // calculate amount of free space 3916 sub(t1, t1, top); 3917 lsr(t1, t1, LogHeapWordSize); 3918 3919 // Retain tlab and allocate object in shared space if 3920 // the amount free in the tlab is too large to discard. 3921 3922 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3923 cmp(t1, rscratch1); 3924 br(Assembler::LE, discard_tlab); 3925 3926 // Retain 3927 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3928 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 3929 add(rscratch1, rscratch1, t2); 3930 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3931 3932 if (TLABStats) { 3933 // increment number of slow_allocations 3934 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), 3935 1, rscratch1); 3936 } 3937 b(try_eden); 3938 3939 bind(discard_tlab); 3940 if (TLABStats) { 3941 // increment number of refills 3942 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, 3943 rscratch1); 3944 // accumulate wastage -- t1 is amount free in tlab 3945 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, 3946 rscratch1); 3947 } 3948 3949 // if tlab is currently allocated (top or end != null) then 3950 // fill [top, end + alignment_reserve) with array object 3951 cbz(top, do_refill); 3952 3953 // set up the mark word 3954 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 3955 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes())); 3956 // set the length to the remaining space 3957 sub(t1, t1, typeArrayOopDesc::header_size(T_INT)); 3958 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 3959 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); 3960 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes())); 3961 // set klass to intArrayKlass 3962 { 3963 unsigned long offset; 3964 // dubious reloc why not an oop reloc? 3965 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), 3966 offset); 3967 ldr(t1, Address(rscratch1, offset)); 3968 } 3969 // store klass last. concurrent gcs assumes klass length is valid if 3970 // klass field is not null. 3971 store_klass(top, t1); 3972 3973 mov(t1, top); 3974 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3975 sub(t1, t1, rscratch1); 3976 incr_allocated_bytes(rthread, t1, 0, rscratch1); 3977 3978 // refill the tlab with an eden allocation 3979 bind(do_refill); 3980 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3981 lsl(t1, t1, LogHeapWordSize); 3982 // allocate new tlab, address returned in top 3983 eden_allocate(top, t1, 0, t2, slow_case); 3984 3985 // Check that t1 was preserved in eden_allocate. 3986 #ifdef ASSERT 3987 if (UseTLAB) { 3988 Label ok; 3989 Register tsize = r4; 3990 assert_different_registers(tsize, rthread, t1); 3991 str(tsize, Address(pre(sp, -16))); 3992 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3993 lsl(tsize, tsize, LogHeapWordSize); 3994 cmp(t1, tsize); 3995 br(Assembler::EQ, ok); 3996 STOP("assert(t1 != tlab size)"); 3997 should_not_reach_here(); 3998 3999 bind(ok); 4000 ldr(tsize, Address(post(sp, 16))); 4001 } 4002 #endif 4003 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4004 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4005 add(top, top, t1); 4006 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 4007 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4008 4009 if (ZeroTLAB) { 4010 // This is a fast TLAB refill, therefore the GC is not notified of it. 4011 // So compiled code must fill the new TLAB with zeroes. 4012 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4013 zero_memory(top,t1,t2); 4014 } 4015 4016 verify_tlab(); 4017 b(retry); 4018 4019 return rthread; // for use by caller 4020 } 4021 4022 // Zero words; len is in bytes 4023 // Destroys all registers except addr 4024 // len must be a nonzero multiple of wordSize 4025 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) { 4026 assert_different_registers(addr, len, t1, rscratch1, rscratch2); 4027 4028 #ifdef ASSERT 4029 { Label L; 4030 tst(len, BytesPerWord - 1); 4031 br(Assembler::EQ, L); 4032 stop("len is not a multiple of BytesPerWord"); 4033 bind(L); 4034 } 4035 #endif 4036 4037 #ifndef PRODUCT 4038 block_comment("zero memory"); 4039 #endif 4040 4041 Label loop; 4042 Label entry; 4043 4044 // Algorithm: 4045 // 4046 // scratch1 = cnt & 7; 4047 // cnt -= scratch1; 4048 // p += scratch1; 4049 // switch (scratch1) { 4050 // do { 4051 // cnt -= 8; 4052 // p[-8] = 0; 4053 // case 7: 4054 // p[-7] = 0; 4055 // case 6: 4056 // p[-6] = 0; 4057 // // ... 4058 // case 1: 4059 // p[-1] = 0; 4060 // case 0: 4061 // p += 8; 4062 // } while (cnt); 4063 // } 4064 4065 const int unroll = 8; // Number of str(zr) instructions we'll unroll 4066 4067 lsr(len, len, LogBytesPerWord); 4068 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll 4069 sub(len, len, rscratch1); // cnt -= unroll 4070 // t1 always points to the end of the region we're about to zero 4071 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord); 4072 adr(rscratch2, entry); 4073 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2); 4074 br(rscratch2); 4075 bind(loop); 4076 sub(len, len, unroll); 4077 for (int i = -unroll; i < 0; i++) 4078 str(zr, Address(t1, i * wordSize)); 4079 bind(entry); 4080 add(t1, t1, unroll * wordSize); 4081 cbnz(len, loop); 4082 } 4083 4084 // Defines obj, preserves var_size_in_bytes 4085 void MacroAssembler::eden_allocate(Register obj, 4086 Register var_size_in_bytes, 4087 int con_size_in_bytes, 4088 Register t1, 4089 Label& slow_case) { 4090 assert_different_registers(obj, var_size_in_bytes, t1); 4091 if (!Universe::heap()->supports_inline_contig_alloc()) { 4092 b(slow_case); 4093 } else { 4094 Register end = t1; 4095 Register heap_end = rscratch2; 4096 Label retry; 4097 bind(retry); 4098 { 4099 unsigned long offset; 4100 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); 4101 ldr(heap_end, Address(rscratch1, offset)); 4102 } 4103 4104 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 4105 4106 // Get the current top of the heap 4107 { 4108 unsigned long offset; 4109 adrp(rscratch1, heap_top, offset); 4110 // Use add() here after ARDP, rather than lea(). 4111 // lea() does not generate anything if its offset is zero. 4112 // However, relocs expect to find either an ADD or a load/store 4113 // insn after an ADRP. add() always generates an ADD insn, even 4114 // for add(Rn, Rn, 0). 4115 add(rscratch1, rscratch1, offset); 4116 ldaxr(obj, rscratch1); 4117 } 4118 4119 // Adjust it my the size of our new object 4120 if (var_size_in_bytes == noreg) { 4121 lea(end, Address(obj, con_size_in_bytes)); 4122 } else { 4123 lea(end, Address(obj, var_size_in_bytes)); 4124 } 4125 4126 // if end < obj then we wrapped around high memory 4127 cmp(end, obj); 4128 br(Assembler::LO, slow_case); 4129 4130 cmp(end, heap_end); 4131 br(Assembler::HI, slow_case); 4132 4133 // If heap_top hasn't been changed by some other thread, update it. 4134 stlxr(rscratch2, end, rscratch1); 4135 cbnzw(rscratch2, retry); 4136 } 4137 } 4138 4139 void MacroAssembler::verify_tlab() { 4140 #ifdef ASSERT 4141 if (UseTLAB && VerifyOops) { 4142 Label next, ok; 4143 4144 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 4145 4146 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4147 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4148 cmp(rscratch2, rscratch1); 4149 br(Assembler::HS, next); 4150 STOP("assert(top >= start)"); 4151 should_not_reach_here(); 4152 4153 bind(next); 4154 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4155 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4156 cmp(rscratch2, rscratch1); 4157 br(Assembler::HS, ok); 4158 STOP("assert(top <= end)"); 4159 should_not_reach_here(); 4160 4161 bind(ok); 4162 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 4163 } 4164 #endif 4165 } 4166 4167 // Writes to stack successive pages until offset reached to check for 4168 // stack overflow + shadow pages. This clobbers tmp. 4169 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 4170 assert_different_registers(tmp, size, rscratch1); 4171 mov(tmp, sp); 4172 // Bang stack for total size given plus shadow page size. 4173 // Bang one page at a time because large size can bang beyond yellow and 4174 // red zones. 4175 Label loop; 4176 mov(rscratch1, os::vm_page_size()); 4177 bind(loop); 4178 lea(tmp, Address(tmp, -os::vm_page_size())); 4179 subsw(size, size, rscratch1); 4180 str(size, Address(tmp)); 4181 br(Assembler::GT, loop); 4182 4183 // Bang down shadow pages too. 4184 // At this point, (tmp-0) is the last address touched, so don't 4185 // touch it again. (It was touched as (tmp-pagesize) but then tmp 4186 // was post-decremented.) Skip this address by starting at i=1, and 4187 // touch a few more pages below. N.B. It is important to touch all 4188 // the way down to and including i=StackShadowPages. 4189 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { 4190 // this could be any sized move but this is can be a debugging crumb 4191 // so the bigger the better. 4192 lea(tmp, Address(tmp, -os::vm_page_size())); 4193 str(size, Address(tmp)); 4194 } 4195 } 4196 4197 4198 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { 4199 unsigned long off; 4200 adrp(r, Address(page, rtype), off); 4201 InstructionMark im(this); 4202 code_section()->relocate(inst_mark(), rtype); 4203 ldrw(zr, Address(r, off)); 4204 return inst_mark(); 4205 } 4206 4207 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 4208 InstructionMark im(this); 4209 code_section()->relocate(inst_mark(), rtype); 4210 ldrw(zr, Address(r, 0)); 4211 return inst_mark(); 4212 } 4213 4214 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { 4215 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 4216 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; 4217 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; 4218 unsigned long dest_page = (unsigned long)dest.target() >> 12; 4219 long offset_low = dest_page - low_page; 4220 long offset_high = dest_page - high_page; 4221 4222 assert(is_valid_AArch64_address(dest.target()), "bad address"); 4223 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 4224 4225 InstructionMark im(this); 4226 code_section()->relocate(inst_mark(), dest.rspec()); 4227 // 8143067: Ensure that the adrp can reach the dest from anywhere within 4228 // the code cache so that if it is relocated we know it will still reach 4229 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 4230 _adrp(reg1, dest.target()); 4231 } else { 4232 unsigned long target = (unsigned long)dest.target(); 4233 unsigned long adrp_target 4234 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); 4235 4236 _adrp(reg1, (address)adrp_target); 4237 movk(reg1, target >> 32, 32); 4238 } 4239 byte_offset = (unsigned long)dest.target() & 0xfff; 4240 } 4241 4242 void MacroAssembler::load_byte_map_base(Register reg) { 4243 jbyte *byte_map_base = 4244 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base; 4245 4246 if (is_valid_AArch64_address((address)byte_map_base)) { 4247 // Strictly speaking the byte_map_base isn't an address at all, 4248 // and it might even be negative. 4249 unsigned long offset; 4250 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4251 // We expect offset to be zero with most collectors. 4252 if (offset != 0) { 4253 add(reg, reg, offset); 4254 } 4255 } else { 4256 mov(reg, (uint64_t)byte_map_base); 4257 } 4258 } 4259 4260 void MacroAssembler::build_frame(int framesize) { 4261 assert(framesize > 0, "framesize must be > 0"); 4262 if (framesize < ((1 << 9) + 2 * wordSize)) { 4263 sub(sp, sp, framesize); 4264 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4265 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4266 } else { 4267 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4268 if (PreserveFramePointer) mov(rfp, sp); 4269 if (framesize < ((1 << 12) + 2 * wordSize)) 4270 sub(sp, sp, framesize - 2 * wordSize); 4271 else { 4272 mov(rscratch1, framesize - 2 * wordSize); 4273 sub(sp, sp, rscratch1); 4274 } 4275 } 4276 } 4277 4278 void MacroAssembler::remove_frame(int framesize) { 4279 assert(framesize > 0, "framesize must be > 0"); 4280 if (framesize < ((1 << 9) + 2 * wordSize)) { 4281 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4282 add(sp, sp, framesize); 4283 } else { 4284 if (framesize < ((1 << 12) + 2 * wordSize)) 4285 add(sp, sp, framesize - 2 * wordSize); 4286 else { 4287 mov(rscratch1, framesize - 2 * wordSize); 4288 add(sp, sp, rscratch1); 4289 } 4290 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4291 } 4292 } 4293 4294 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); 4295 4296 // Search for str1 in str2 and return index or -1 4297 void MacroAssembler::string_indexof(Register str2, Register str1, 4298 Register cnt2, Register cnt1, 4299 Register tmp1, Register tmp2, 4300 Register tmp3, Register tmp4, 4301 int icnt1, Register result, int ae) { 4302 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; 4303 4304 Register ch1 = rscratch1; 4305 Register ch2 = rscratch2; 4306 Register cnt1tmp = tmp1; 4307 Register cnt2tmp = tmp2; 4308 Register cnt1_neg = cnt1; 4309 Register cnt2_neg = cnt2; 4310 Register result_tmp = tmp4; 4311 4312 bool isL = ae == StrIntrinsicNode::LL; 4313 4314 bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL; 4315 bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU; 4316 int str1_chr_shift = str1_isL ? 0:1; 4317 int str2_chr_shift = str2_isL ? 0:1; 4318 int str1_chr_size = str1_isL ? 1:2; 4319 int str2_chr_size = str2_isL ? 1:2; 4320 chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : 4321 (chr_insn)&MacroAssembler::ldrh; 4322 chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : 4323 (chr_insn)&MacroAssembler::ldrh; 4324 chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw; 4325 chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr; 4326 4327 // Note, inline_string_indexOf() generates checks: 4328 // if (substr.count > string.count) return -1; 4329 // if (substr.count == 0) return 0; 4330 4331 // We have two strings, a source string in str2, cnt2 and a pattern string 4332 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1. 4333 4334 // For larger pattern and source we use a simplified Boyer Moore algorithm. 4335 // With a small pattern and source we use linear scan. 4336 4337 if (icnt1 == -1) { 4338 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 4339 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use 4340 br(LO, LINEARSEARCH); // a byte array. 4341 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM 4342 br(HS, LINEARSEARCH); 4343 } 4344 4345 // The Boyer Moore alogorithm is based on the description here:- 4346 // 4347 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm 4348 // 4349 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule 4350 // and the 'Good Suffix' rule. 4351 // 4352 // These rules are essentially heuristics for how far we can shift the 4353 // pattern along the search string. 4354 // 4355 // The implementation here uses the 'Bad Character' rule only because of the 4356 // complexity of initialisation for the 'Good Suffix' rule. 4357 // 4358 // This is also known as the Boyer-Moore-Horspool algorithm:- 4359 // 4360 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm 4361 // 4362 // #define ASIZE 128 4363 // 4364 // int bm(unsigned char *x, int m, unsigned char *y, int n) { 4365 // int i, j; 4366 // unsigned c; 4367 // unsigned char bc[ASIZE]; 4368 // 4369 // /* Preprocessing */ 4370 // for (i = 0; i < ASIZE; ++i) 4371 // bc[i] = 0; 4372 // for (i = 0; i < m - 1; ) { 4373 // c = x[i]; 4374 // ++i; 4375 // if (c < ASIZE) bc[c] = i; 4376 // } 4377 // 4378 // /* Searching */ 4379 // j = 0; 4380 // while (j <= n - m) { 4381 // c = y[i+j]; 4382 // if (x[m-1] == c) 4383 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); 4384 // if (i < 0) return j; 4385 // if (c < ASIZE) 4386 // j = j - bc[y[j+m-1]] + m; 4387 // else 4388 // j += 1; // Advance by 1 only if char >= ASIZE 4389 // } 4390 // } 4391 4392 if (icnt1 == -1) { 4393 BIND(BM); 4394 4395 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; 4396 Label BMADV, BMMATCH, BMCHECKEND; 4397 4398 Register cnt1end = tmp2; 4399 Register str2end = cnt2; 4400 Register skipch = tmp2; 4401 4402 // Restrict ASIZE to 128 to reduce stack space/initialisation. 4403 // The presence of chars >= ASIZE in the target string does not affect 4404 // performance, but we must be careful not to initialise them in the stack 4405 // array. 4406 // The presence of chars >= ASIZE in the source string may adversely affect 4407 // performance since we can only advance by one when we encounter one. 4408 4409 stp(zr, zr, pre(sp, -128)); 4410 for (int i = 1; i < 8; i++) 4411 stp(zr, zr, Address(sp, i*16)); 4412 4413 mov(cnt1tmp, 0); 4414 sub(cnt1end, cnt1, 1); 4415 BIND(BCLOOP); 4416 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4417 cmp(ch1, 128); 4418 add(cnt1tmp, cnt1tmp, 1); 4419 br(HS, BCSKIP); 4420 strb(cnt1tmp, Address(sp, ch1)); 4421 BIND(BCSKIP); 4422 cmp(cnt1tmp, cnt1end); 4423 br(LT, BCLOOP); 4424 4425 mov(result_tmp, str2); 4426 4427 sub(cnt2, cnt2, cnt1); 4428 add(str2end, str2, cnt2, LSL, str2_chr_shift); 4429 BIND(BMLOOPSTR2); 4430 sub(cnt1tmp, cnt1, 1); 4431 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4432 (this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); 4433 cmp(ch1, skipch); 4434 br(NE, BMSKIP); 4435 subs(cnt1tmp, cnt1tmp, 1); 4436 br(LT, BMMATCH); 4437 BIND(BMLOOPSTR1); 4438 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4439 (this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); 4440 cmp(ch1, ch2); 4441 br(NE, BMSKIP); 4442 subs(cnt1tmp, cnt1tmp, 1); 4443 br(GE, BMLOOPSTR1); 4444 BIND(BMMATCH); 4445 sub(result, str2, result_tmp); 4446 if (!str2_isL) lsr(result, result, 1); 4447 add(sp, sp, 128); 4448 b(DONE); 4449 BIND(BMADV); 4450 add(str2, str2, str2_chr_size); 4451 b(BMCHECKEND); 4452 BIND(BMSKIP); 4453 cmp(skipch, 128); 4454 br(HS, BMADV); 4455 ldrb(ch2, Address(sp, skipch)); 4456 add(str2, str2, cnt1, LSL, str2_chr_shift); 4457 sub(str2, str2, ch2, LSL, str2_chr_shift); 4458 BIND(BMCHECKEND); 4459 cmp(str2, str2end); 4460 br(LE, BMLOOPSTR2); 4461 add(sp, sp, 128); 4462 b(NOMATCH); 4463 } 4464 4465 BIND(LINEARSEARCH); 4466 { 4467 Label DO1, DO2, DO3; 4468 4469 Register str2tmp = tmp2; 4470 Register first = tmp3; 4471 4472 if (icnt1 == -1) 4473 { 4474 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT; 4475 4476 cmp(cnt1, str1_isL == str2_isL ? 4 : 2); 4477 br(LT, DOSHORT); 4478 4479 sub(cnt2, cnt2, cnt1); 4480 mov(result_tmp, cnt2); 4481 4482 lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift))); 4483 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4484 sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift); 4485 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4486 (this->*str1_load_1chr)(first, Address(str1, cnt1_neg)); 4487 4488 BIND(FIRST_LOOP); 4489 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); 4490 cmp(first, ch2); 4491 br(EQ, STR1_LOOP); 4492 BIND(STR2_NEXT); 4493 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4494 br(LE, FIRST_LOOP); 4495 b(NOMATCH); 4496 4497 BIND(STR1_LOOP); 4498 adds(cnt1tmp, cnt1_neg, str1_chr_size); 4499 add(cnt2tmp, cnt2_neg, str2_chr_size); 4500 br(GE, MATCH); 4501 4502 BIND(STR1_NEXT); 4503 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp)); 4504 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); 4505 cmp(ch1, ch2); 4506 br(NE, STR2_NEXT); 4507 adds(cnt1tmp, cnt1tmp, str1_chr_size); 4508 add(cnt2tmp, cnt2tmp, str2_chr_size); 4509 br(LT, STR1_NEXT); 4510 b(MATCH); 4511 4512 BIND(DOSHORT); 4513 if (str1_isL == str2_isL) { 4514 cmp(cnt1, 2); 4515 br(LT, DO1); 4516 br(GT, DO3); 4517 } 4518 } 4519 4520 if (icnt1 == 4) { 4521 Label CH1_LOOP; 4522 4523 (this->*load_4chr)(ch1, str1); 4524 sub(cnt2, cnt2, 4); 4525 mov(result_tmp, cnt2); 4526 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4527 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4528 4529 BIND(CH1_LOOP); 4530 (this->*load_4chr)(ch2, Address(str2, cnt2_neg)); 4531 cmp(ch1, ch2); 4532 br(EQ, MATCH); 4533 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4534 br(LE, CH1_LOOP); 4535 b(NOMATCH); 4536 } 4537 4538 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) { 4539 Label CH1_LOOP; 4540 4541 BIND(DO2); 4542 (this->*load_2chr)(ch1, str1); 4543 sub(cnt2, cnt2, 2); 4544 mov(result_tmp, cnt2); 4545 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4546 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4547 4548 BIND(CH1_LOOP); 4549 (this->*load_2chr)(ch2, Address(str2, cnt2_neg)); 4550 cmp(ch1, ch2); 4551 br(EQ, MATCH); 4552 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4553 br(LE, CH1_LOOP); 4554 b(NOMATCH); 4555 } 4556 4557 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) { 4558 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; 4559 4560 BIND(DO3); 4561 (this->*load_2chr)(first, str1); 4562 (this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size)); 4563 4564 sub(cnt2, cnt2, 3); 4565 mov(result_tmp, cnt2); 4566 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4567 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4568 4569 BIND(FIRST_LOOP); 4570 (this->*load_2chr)(ch2, Address(str2, cnt2_neg)); 4571 cmpw(first, ch2); 4572 br(EQ, STR1_LOOP); 4573 BIND(STR2_NEXT); 4574 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4575 br(LE, FIRST_LOOP); 4576 b(NOMATCH); 4577 4578 BIND(STR1_LOOP); 4579 add(cnt2tmp, cnt2_neg, 2*str2_chr_size); 4580 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); 4581 cmp(ch1, ch2); 4582 br(NE, STR2_NEXT); 4583 b(MATCH); 4584 } 4585 4586 if (icnt1 == -1 || icnt1 == 1) { 4587 Label CH1_LOOP, HAS_ZERO; 4588 Label DO1_SHORT, DO1_LOOP; 4589 4590 BIND(DO1); 4591 (this->*str1_load_1chr)(ch1, str1); 4592 cmp(cnt2, 8); 4593 br(LT, DO1_SHORT); 4594 4595 if (str2_isL) { 4596 if (!str1_isL) { 4597 tst(ch1, 0xff00); 4598 br(NE, NOMATCH); 4599 } 4600 orr(ch1, ch1, ch1, LSL, 8); 4601 } 4602 orr(ch1, ch1, ch1, LSL, 16); 4603 orr(ch1, ch1, ch1, LSL, 32); 4604 4605 sub(cnt2, cnt2, 8/str2_chr_size); 4606 mov(result_tmp, cnt2); 4607 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4608 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4609 4610 mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001); 4611 BIND(CH1_LOOP); 4612 ldr(ch2, Address(str2, cnt2_neg)); 4613 eor(ch2, ch1, ch2); 4614 sub(tmp1, ch2, tmp3); 4615 orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); 4616 bics(tmp1, tmp1, tmp2); 4617 br(NE, HAS_ZERO); 4618 adds(cnt2_neg, cnt2_neg, 8); 4619 br(LT, CH1_LOOP); 4620 4621 cmp(cnt2_neg, 8); 4622 mov(cnt2_neg, 0); 4623 br(LT, CH1_LOOP); 4624 b(NOMATCH); 4625 4626 BIND(HAS_ZERO); 4627 rev(tmp1, tmp1); 4628 clz(tmp1, tmp1); 4629 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); 4630 b(MATCH); 4631 4632 BIND(DO1_SHORT); 4633 mov(result_tmp, cnt2); 4634 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4635 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4636 BIND(DO1_LOOP); 4637 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); 4638 cmpw(ch1, ch2); 4639 br(EQ, MATCH); 4640 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4641 br(LT, DO1_LOOP); 4642 } 4643 } 4644 BIND(NOMATCH); 4645 mov(result, -1); 4646 b(DONE); 4647 BIND(MATCH); 4648 add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift); 4649 BIND(DONE); 4650 } 4651 4652 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); 4653 typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn); 4654 4655 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, 4656 Register ch, Register result, 4657 Register tmp1, Register tmp2, Register tmp3) 4658 { 4659 Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE; 4660 Register cnt1_neg = cnt1; 4661 Register ch1 = rscratch1; 4662 Register result_tmp = rscratch2; 4663 4664 cmp(cnt1, 4); 4665 br(LT, DO1_SHORT); 4666 4667 orr(ch, ch, ch, LSL, 16); 4668 orr(ch, ch, ch, LSL, 32); 4669 4670 sub(cnt1, cnt1, 4); 4671 mov(result_tmp, cnt1); 4672 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4673 sub(cnt1_neg, zr, cnt1, LSL, 1); 4674 4675 mov(tmp3, 0x0001000100010001); 4676 4677 BIND(CH1_LOOP); 4678 ldr(ch1, Address(str1, cnt1_neg)); 4679 eor(ch1, ch, ch1); 4680 sub(tmp1, ch1, tmp3); 4681 orr(tmp2, ch1, 0x7fff7fff7fff7fff); 4682 bics(tmp1, tmp1, tmp2); 4683 br(NE, HAS_ZERO); 4684 adds(cnt1_neg, cnt1_neg, 8); 4685 br(LT, CH1_LOOP); 4686 4687 cmp(cnt1_neg, 8); 4688 mov(cnt1_neg, 0); 4689 br(LT, CH1_LOOP); 4690 b(NOMATCH); 4691 4692 BIND(HAS_ZERO); 4693 rev(tmp1, tmp1); 4694 clz(tmp1, tmp1); 4695 add(cnt1_neg, cnt1_neg, tmp1, LSR, 3); 4696 b(MATCH); 4697 4698 BIND(DO1_SHORT); 4699 mov(result_tmp, cnt1); 4700 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4701 sub(cnt1_neg, zr, cnt1, LSL, 1); 4702 BIND(DO1_LOOP); 4703 ldrh(ch1, Address(str1, cnt1_neg)); 4704 cmpw(ch, ch1); 4705 br(EQ, MATCH); 4706 adds(cnt1_neg, cnt1_neg, 2); 4707 br(LT, DO1_LOOP); 4708 BIND(NOMATCH); 4709 mov(result, -1); 4710 b(DONE); 4711 BIND(MATCH); 4712 add(result, result_tmp, cnt1_neg, ASR, 1); 4713 BIND(DONE); 4714 } 4715 4716 // Compare strings. 4717 void MacroAssembler::string_compare(Register str1, Register str2, 4718 Register cnt1, Register cnt2, Register result, 4719 Register tmp1, 4720 FloatRegister vtmp, FloatRegister vtmpZ, int ae) { 4721 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, 4722 NEXT_WORD, DIFFERENCE; 4723 4724 bool isLL = ae == StrIntrinsicNode::LL; 4725 bool isLU = ae == StrIntrinsicNode::LU; 4726 bool isUL = ae == StrIntrinsicNode::UL; 4727 4728 bool str1_isL = isLL || isLU; 4729 bool str2_isL = isLL || isUL; 4730 4731 int str1_chr_shift = str1_isL ? 0 : 1; 4732 int str2_chr_shift = str2_isL ? 0 : 1; 4733 int str1_chr_size = str1_isL ? 1 : 2; 4734 int str2_chr_size = str2_isL ? 1 : 2; 4735 4736 chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : 4737 (chr_insn)&MacroAssembler::ldrh; 4738 chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : 4739 (chr_insn)&MacroAssembler::ldrh; 4740 uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw : 4741 (uxt_insn)&MacroAssembler::uxthw; 4742 4743 BLOCK_COMMENT("string_compare {"); 4744 4745 // Bizzarely, the counts are passed in bytes, regardless of whether they 4746 // are L or U strings, however the result is always in characters. 4747 if (!str1_isL) asrw(cnt1, cnt1, 1); 4748 if (!str2_isL) asrw(cnt2, cnt2, 1); 4749 4750 // Compute the minimum of the string lengths and save the difference. 4751 subsw(tmp1, cnt1, cnt2); 4752 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min 4753 4754 // A very short string 4755 cmpw(cnt2, isLL ? 8:4); 4756 br(Assembler::LT, SHORT_STRING); 4757 4758 // Check if the strings start at the same location. 4759 cmp(str1, str2); 4760 br(Assembler::EQ, LENGTH_DIFF); 4761 4762 // Compare longwords 4763 { 4764 subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case 4765 4766 // Move both string pointers to the last longword of their 4767 // strings, negate the remaining count, and convert it to bytes. 4768 lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift))); 4769 lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift))); 4770 if (isLU || isUL) { 4771 sub(cnt1, zr, cnt2, LSL, str1_chr_shift); 4772 eor(vtmpZ, T16B, vtmpZ, vtmpZ); 4773 } 4774 sub(cnt2, zr, cnt2, LSL, str2_chr_shift); 4775 4776 // Loop, loading longwords and comparing them into rscratch2. 4777 bind(NEXT_WORD); 4778 if (isLU) { 4779 ldrs(vtmp, Address(str1, cnt1)); 4780 zip1(vtmp, T8B, vtmp, vtmpZ); 4781 umov(result, vtmp, D, 0); 4782 } else { 4783 ldr(result, Address(str1, isUL ? cnt1:cnt2)); 4784 } 4785 if (isUL) { 4786 ldrs(vtmp, Address(str2, cnt2)); 4787 zip1(vtmp, T8B, vtmp, vtmpZ); 4788 umov(rscratch1, vtmp, D, 0); 4789 } else { 4790 ldr(rscratch1, Address(str2, cnt2)); 4791 } 4792 adds(cnt2, cnt2, isUL ? 4:8); 4793 if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8); 4794 eor(rscratch2, result, rscratch1); 4795 cbnz(rscratch2, DIFFERENCE); 4796 br(Assembler::LT, NEXT_WORD); 4797 4798 // Last longword. In the case where length == 4 we compare the 4799 // same longword twice, but that's still faster than another 4800 // conditional branch. 4801 4802 if (isLU) { 4803 ldrs(vtmp, Address(str1)); 4804 zip1(vtmp, T8B, vtmp, vtmpZ); 4805 umov(result, vtmp, D, 0); 4806 } else { 4807 ldr(result, Address(str1)); 4808 } 4809 if (isUL) { 4810 ldrs(vtmp, Address(str2)); 4811 zip1(vtmp, T8B, vtmp, vtmpZ); 4812 umov(rscratch1, vtmp, D, 0); 4813 } else { 4814 ldr(rscratch1, Address(str2)); 4815 } 4816 eor(rscratch2, result, rscratch1); 4817 cbz(rscratch2, LENGTH_DIFF); 4818 4819 // Find the first different characters in the longwords and 4820 // compute their difference. 4821 bind(DIFFERENCE); 4822 rev(rscratch2, rscratch2); 4823 clz(rscratch2, rscratch2); 4824 andr(rscratch2, rscratch2, isLL ? -8 : -16); 4825 lsrv(result, result, rscratch2); 4826 (this->*ext_chr)(result, result); 4827 lsrv(rscratch1, rscratch1, rscratch2); 4828 (this->*ext_chr)(rscratch1, rscratch1); 4829 subw(result, result, rscratch1); 4830 b(DONE); 4831 } 4832 4833 bind(SHORT_STRING); 4834 // Is the minimum length zero? 4835 cbz(cnt2, LENGTH_DIFF); 4836 4837 bind(SHORT_LOOP); 4838 (this->*str1_load_chr)(result, Address(post(str1, str1_chr_size))); 4839 (this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size))); 4840 subw(result, result, cnt1); 4841 cbnz(result, DONE); 4842 sub(cnt2, cnt2, 1); 4843 cbnz(cnt2, SHORT_LOOP); 4844 4845 // Strings are equal up to min length. Return the length difference. 4846 bind(LENGTH_DIFF); 4847 mov(result, tmp1); 4848 4849 // That's it 4850 bind(DONE); 4851 4852 BLOCK_COMMENT("} string_compare"); 4853 } 4854 4855 // This method checks if provided byte array contains byte with highest bit set. 4856 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) { 4857 // Simple and most common case of aligned small array which is not at the 4858 // end of memory page is placed here. All other cases are in stub. 4859 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; 4860 const uint64_t UPPER_BIT_MASK=0x8080808080808080; 4861 assert_different_registers(ary1, len, result); 4862 4863 cmpw(len, 0); 4864 br(LE, SET_RESULT); 4865 cmpw(len, 4 * wordSize); 4866 br(GE, STUB_LONG); // size > 32 then go to stub 4867 4868 int shift = 64 - exact_log2(os::vm_page_size()); 4869 lsl(rscratch1, ary1, shift); 4870 mov(rscratch2, (size_t)(4 * wordSize) << shift); 4871 adds(rscratch2, rscratch1, rscratch2); // At end of page? 4872 br(CS, STUB); // at the end of page then go to stub 4873 subs(len, len, wordSize); 4874 br(LT, END); 4875 4876 BIND(LOOP); 4877 ldr(rscratch1, Address(post(ary1, wordSize))); 4878 tst(rscratch1, UPPER_BIT_MASK); 4879 br(NE, SET_RESULT); 4880 subs(len, len, wordSize); 4881 br(GE, LOOP); 4882 cmpw(len, -wordSize); 4883 br(EQ, SET_RESULT); 4884 4885 BIND(END); 4886 ldr(result, Address(ary1)); 4887 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes 4888 lslv(result, result, len); 4889 tst(result, UPPER_BIT_MASK); 4890 b(SET_RESULT); 4891 4892 BIND(STUB); 4893 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); 4894 assert(has_neg.target() != NULL, "has_negatives stub has not been generated"); 4895 trampoline_call(has_neg); 4896 b(DONE); 4897 4898 BIND(STUB_LONG); 4899 RuntimeAddress has_neg_long = RuntimeAddress( 4900 StubRoutines::aarch64::has_negatives_long()); 4901 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated"); 4902 trampoline_call(has_neg_long); 4903 b(DONE); 4904 4905 BIND(SET_RESULT); 4906 cset(result, NE); // set true or false 4907 4908 BIND(DONE); 4909 } 4910 4911 // Compare Strings or char/byte arrays. 4912 4913 // is_string is true iff this is a string comparison. 4914 4915 // For Strings we're passed the address of the first characters in a1 4916 // and a2 and the length in cnt1. 4917 4918 // For byte and char arrays we're passed the arrays themselves and we 4919 // have to extract length fields and do null checks here. 4920 4921 // elem_size is the element size in bytes: either 1 or 2. 4922 4923 // There are two implementations. For arrays >= 8 bytes, all 4924 // comparisons (including the final one, which may overlap) are 4925 // performed 8 bytes at a time. For arrays < 8 bytes, we compare a 4926 // halfword, then a short, and then a byte. 4927 4928 void MacroAssembler::arrays_equals(Register a1, Register a2, 4929 Register result, Register cnt1, 4930 int elem_size, bool is_string) 4931 { 4932 Label SAME, DONE, SHORT, NEXT_WORD, ONE; 4933 Register tmp1 = rscratch1; 4934 Register tmp2 = rscratch2; 4935 Register cnt2 = tmp2; // cnt2 only used in array length compare 4936 int elem_per_word = wordSize/elem_size; 4937 int log_elem_size = exact_log2(elem_size); 4938 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4939 int base_offset 4940 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); 4941 4942 assert(elem_size == 1 || elem_size == 2, "must be char or byte"); 4943 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 4944 4945 #ifndef PRODUCT 4946 { 4947 const char kind = (elem_size == 2) ? 'U' : 'L'; 4948 char comment[64]; 4949 snprintf(comment, sizeof comment, "%s%c%s {", 4950 is_string ? "string_equals" : "array_equals", 4951 kind, "{"); 4952 BLOCK_COMMENT(comment); 4953 } 4954 #endif 4955 4956 mov(result, false); 4957 4958 if (!is_string) { 4959 // if (a==a2) 4960 // return true; 4961 eor(rscratch1, a1, a2); 4962 cbz(rscratch1, SAME); 4963 // if (a==null || a2==null) 4964 // return false; 4965 cbz(a1, DONE); 4966 cbz(a2, DONE); 4967 // if (a1.length != a2.length) 4968 // return false; 4969 ldrw(cnt1, Address(a1, length_offset)); 4970 ldrw(cnt2, Address(a2, length_offset)); 4971 eorw(tmp1, cnt1, cnt2); 4972 cbnzw(tmp1, DONE); 4973 4974 lea(a1, Address(a1, base_offset)); 4975 lea(a2, Address(a2, base_offset)); 4976 } 4977 4978 // Check for short strings, i.e. smaller than wordSize. 4979 subs(cnt1, cnt1, elem_per_word); 4980 br(Assembler::LT, SHORT); 4981 // Main 8 byte comparison loop. 4982 bind(NEXT_WORD); { 4983 ldr(tmp1, Address(post(a1, wordSize))); 4984 ldr(tmp2, Address(post(a2, wordSize))); 4985 subs(cnt1, cnt1, elem_per_word); 4986 eor(tmp1, tmp1, tmp2); 4987 cbnz(tmp1, DONE); 4988 } br(GT, NEXT_WORD); 4989 // Last longword. In the case where length == 4 we compare the 4990 // same longword twice, but that's still faster than another 4991 // conditional branch. 4992 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 4993 // length == 4. 4994 if (log_elem_size > 0) 4995 lsl(cnt1, cnt1, log_elem_size); 4996 ldr(tmp1, Address(a1, cnt1)); 4997 ldr(tmp2, Address(a2, cnt1)); 4998 eor(tmp1, tmp1, tmp2); 4999 cbnz(tmp1, DONE); 5000 b(SAME); 5001 5002 bind(SHORT); 5003 Label TAIL03, TAIL01; 5004 5005 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. 5006 { 5007 ldrw(tmp1, Address(post(a1, 4))); 5008 ldrw(tmp2, Address(post(a2, 4))); 5009 eorw(tmp1, tmp1, tmp2); 5010 cbnzw(tmp1, DONE); 5011 } 5012 bind(TAIL03); 5013 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. 5014 { 5015 ldrh(tmp1, Address(post(a1, 2))); 5016 ldrh(tmp2, Address(post(a2, 2))); 5017 eorw(tmp1, tmp1, tmp2); 5018 cbnzw(tmp1, DONE); 5019 } 5020 bind(TAIL01); 5021 if (elem_size == 1) { // Only needed when comparing byte arrays. 5022 tbz(cnt1, 0, SAME); // 0-1 bytes left. 5023 { 5024 ldrb(tmp1, a1); 5025 ldrb(tmp2, a2); 5026 eorw(tmp1, tmp1, tmp2); 5027 cbnzw(tmp1, DONE); 5028 } 5029 } 5030 // Arrays are equal. 5031 bind(SAME); 5032 mov(result, true); 5033 5034 // That's it. 5035 bind(DONE); 5036 BLOCK_COMMENT(is_string ? "} string_equals" : "} array_equals"); 5037 } 5038 5039 5040 // The size of the blocks erased by the zero_blocks stub. We must 5041 // handle anything smaller than this ourselves in zero_words(). 5042 const int MacroAssembler::zero_words_block_size = 8; 5043 5044 // zero_words() is used by C2 ClearArray patterns. It is as small as 5045 // possible, handling small word counts locally and delegating 5046 // anything larger to the zero_blocks stub. It is expanded many times 5047 // in compiled code, so it is important to keep it short. 5048 5049 // ptr: Address of a buffer to be zeroed. 5050 // cnt: Count in HeapWords. 5051 // 5052 // ptr, cnt, rscratch1, and rscratch2 are clobbered. 5053 void MacroAssembler::zero_words(Register ptr, Register cnt) 5054 { 5055 assert(is_power_of_2(zero_words_block_size), "adjust this"); 5056 assert(ptr == r10 && cnt == r11, "mismatch in register usage"); 5057 5058 BLOCK_COMMENT("zero_words {"); 5059 cmp(cnt, zero_words_block_size); 5060 Label around, done, done16; 5061 br(LO, around); 5062 { 5063 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); 5064 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated"); 5065 if (StubRoutines::aarch64::complete()) { 5066 trampoline_call(zero_blocks); 5067 } else { 5068 bl(zero_blocks); 5069 } 5070 } 5071 bind(around); 5072 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) { 5073 Label l; 5074 tbz(cnt, exact_log2(i), l); 5075 for (int j = 0; j < i; j += 2) { 5076 stp(zr, zr, post(ptr, 16)); 5077 } 5078 bind(l); 5079 } 5080 { 5081 Label l; 5082 tbz(cnt, 0, l); 5083 str(zr, Address(ptr)); 5084 bind(l); 5085 } 5086 BLOCK_COMMENT("} zero_words"); 5087 } 5088 5089 // base: Address of a buffer to be zeroed, 8 bytes aligned. 5090 // cnt: Immediate count in HeapWords. 5091 #define SmallArraySize (18 * BytesPerLong) 5092 void MacroAssembler::zero_words(Register base, u_int64_t cnt) 5093 { 5094 BLOCK_COMMENT("zero_words {"); 5095 int i = cnt & 1; // store any odd word to start 5096 if (i) str(zr, Address(base)); 5097 5098 if (cnt <= SmallArraySize / BytesPerLong) { 5099 for (; i < (int)cnt; i += 2) 5100 stp(zr, zr, Address(base, i * wordSize)); 5101 } else { 5102 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll 5103 int remainder = cnt % (2 * unroll); 5104 for (; i < remainder; i += 2) 5105 stp(zr, zr, Address(base, i * wordSize)); 5106 5107 Label loop; 5108 Register cnt_reg = rscratch1; 5109 Register loop_base = rscratch2; 5110 cnt = cnt - remainder; 5111 mov(cnt_reg, cnt); 5112 // adjust base and prebias by -2 * wordSize so we can pre-increment 5113 add(loop_base, base, (remainder - 2) * wordSize); 5114 bind(loop); 5115 sub(cnt_reg, cnt_reg, 2 * unroll); 5116 for (i = 1; i < unroll; i++) 5117 stp(zr, zr, Address(loop_base, 2 * i * wordSize)); 5118 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize))); 5119 cbnz(cnt_reg, loop); 5120 } 5121 BLOCK_COMMENT("} zero_words"); 5122 } 5123 5124 // Zero blocks of memory by using DC ZVA. 5125 // 5126 // Aligns the base address first sufficently for DC ZVA, then uses 5127 // DC ZVA repeatedly for every full block. cnt is the size to be 5128 // zeroed in HeapWords. Returns the count of words left to be zeroed 5129 // in cnt. 5130 // 5131 // NOTE: This is intended to be used in the zero_blocks() stub. If 5132 // you want to use it elsewhere, note that cnt must be >= 2*zva_length. 5133 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) { 5134 Register tmp = rscratch1; 5135 Register tmp2 = rscratch2; 5136 int zva_length = VM_Version::zva_length(); 5137 Label initial_table_end, loop_zva; 5138 Label fini; 5139 5140 // Base must be 16 byte aligned. If not just return and let caller handle it 5141 tst(base, 0x0f); 5142 br(Assembler::NE, fini); 5143 // Align base with ZVA length. 5144 neg(tmp, base); 5145 andr(tmp, tmp, zva_length - 1); 5146 5147 // tmp: the number of bytes to be filled to align the base with ZVA length. 5148 add(base, base, tmp); 5149 sub(cnt, cnt, tmp, Assembler::ASR, 3); 5150 adr(tmp2, initial_table_end); 5151 sub(tmp2, tmp2, tmp, Assembler::LSR, 2); 5152 br(tmp2); 5153 5154 for (int i = -zva_length + 16; i < 0; i += 16) 5155 stp(zr, zr, Address(base, i)); 5156 bind(initial_table_end); 5157 5158 sub(cnt, cnt, zva_length >> 3); 5159 bind(loop_zva); 5160 dc(Assembler::ZVA, base); 5161 subs(cnt, cnt, zva_length >> 3); 5162 add(base, base, zva_length); 5163 br(Assembler::GE, loop_zva); 5164 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA 5165 bind(fini); 5166 } 5167 5168 // base: Address of a buffer to be filled, 8 bytes aligned. 5169 // cnt: Count in 8-byte unit. 5170 // value: Value to be filled with. 5171 // base will point to the end of the buffer after filling. 5172 void MacroAssembler::fill_words(Register base, Register cnt, Register value) 5173 { 5174 // Algorithm: 5175 // 5176 // scratch1 = cnt & 7; 5177 // cnt -= scratch1; 5178 // p += scratch1; 5179 // switch (scratch1) { 5180 // do { 5181 // cnt -= 8; 5182 // p[-8] = v; 5183 // case 7: 5184 // p[-7] = v; 5185 // case 6: 5186 // p[-6] = v; 5187 // // ... 5188 // case 1: 5189 // p[-1] = v; 5190 // case 0: 5191 // p += 8; 5192 // } while (cnt); 5193 // } 5194 5195 assert_different_registers(base, cnt, value, rscratch1, rscratch2); 5196 5197 Label fini, skip, entry, loop; 5198 const int unroll = 8; // Number of stp instructions we'll unroll 5199 5200 cbz(cnt, fini); 5201 tbz(base, 3, skip); 5202 str(value, Address(post(base, 8))); 5203 sub(cnt, cnt, 1); 5204 bind(skip); 5205 5206 andr(rscratch1, cnt, (unroll-1) * 2); 5207 sub(cnt, cnt, rscratch1); 5208 add(base, base, rscratch1, Assembler::LSL, 3); 5209 adr(rscratch2, entry); 5210 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1); 5211 br(rscratch2); 5212 5213 bind(loop); 5214 add(base, base, unroll * 16); 5215 for (int i = -unroll; i < 0; i++) 5216 stp(value, value, Address(base, i * 16)); 5217 bind(entry); 5218 subs(cnt, cnt, unroll * 2); 5219 br(Assembler::GE, loop); 5220 5221 tbz(cnt, 0, fini); 5222 str(value, Address(post(base, 8))); 5223 bind(fini); 5224 } 5225 5226 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and 5227 // java/lang/StringUTF16.compress. 5228 void MacroAssembler::encode_iso_array(Register src, Register dst, 5229 Register len, Register result, 5230 FloatRegister Vtmp1, FloatRegister Vtmp2, 5231 FloatRegister Vtmp3, FloatRegister Vtmp4) 5232 { 5233 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; 5234 Register tmp1 = rscratch1; 5235 5236 mov(result, len); // Save initial len 5237 5238 #ifndef BUILTIN_SIM 5239 subs(len, len, 32); 5240 br(LT, LOOP_8); 5241 5242 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions 5243 // to convert chars to bytes. These set the 'QC' bit in the FPSR if 5244 // any char could not fit in a byte, so clear the FPSR so we can test it. 5245 clear_fpsr(); 5246 5247 BIND(NEXT_32); 5248 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 5249 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half 5250 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half 5251 uqxtn(Vtmp2, T8B, Vtmp3, T8H); 5252 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 5253 get_fpsr(tmp1); 5254 cbnzw(tmp1, LOOP_8); 5255 st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); 5256 subs(len, len, 32); 5257 add(src, src, 64); 5258 br(GE, NEXT_32); 5259 5260 BIND(LOOP_8); 5261 adds(len, len, 32-8); 5262 br(LT, LOOP_1); 5263 clear_fpsr(); // QC may be set from loop above, clear again 5264 BIND(NEXT_8); 5265 ld1(Vtmp1, T8H, src); 5266 uqxtn(Vtmp1, T8B, Vtmp1, T8H); 5267 get_fpsr(tmp1); 5268 cbnzw(tmp1, LOOP_1); 5269 st1(Vtmp1, T8B, post(dst, 8)); 5270 subs(len, len, 8); 5271 add(src, src, 16); 5272 br(GE, NEXT_8); 5273 5274 BIND(LOOP_1); 5275 adds(len, len, 8); 5276 br(LE, DONE); 5277 #else 5278 cbz(len, DONE); 5279 #endif 5280 BIND(NEXT_1); 5281 ldrh(tmp1, Address(post(src, 2))); 5282 tst(tmp1, 0xff00); 5283 br(NE, DONE); 5284 strb(tmp1, Address(post(dst, 1))); 5285 subs(len, len, 1); 5286 br(GT, NEXT_1); 5287 5288 BIND(DONE); 5289 sub(result, result, len); // Return index where we stopped 5290 // Return len == 0 if we processed all 5291 // characters 5292 } 5293 5294 5295 // Inflate byte[] array to char[]. 5296 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 5297 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, 5298 Register tmp4) { 5299 Label big, done; 5300 5301 assert_different_registers(src, dst, len, tmp4, rscratch1); 5302 5303 fmovd(vtmp1 , zr); 5304 lsrw(rscratch1, len, 3); 5305 5306 cbnzw(rscratch1, big); 5307 5308 // Short string: less than 8 bytes. 5309 { 5310 Label loop, around, tiny; 5311 5312 subsw(len, len, 4); 5313 andw(len, len, 3); 5314 br(LO, tiny); 5315 5316 // Use SIMD to do 4 bytes. 5317 ldrs(vtmp2, post(src, 4)); 5318 zip1(vtmp3, T8B, vtmp2, vtmp1); 5319 strd(vtmp3, post(dst, 8)); 5320 5321 cbzw(len, done); 5322 5323 // Do the remaining bytes by steam. 5324 bind(loop); 5325 ldrb(tmp4, post(src, 1)); 5326 strh(tmp4, post(dst, 2)); 5327 subw(len, len, 1); 5328 5329 bind(tiny); 5330 cbnz(len, loop); 5331 5332 bind(around); 5333 b(done); 5334 } 5335 5336 // Unpack the bytes 8 at a time. 5337 bind(big); 5338 andw(len, len, 7); 5339 5340 { 5341 Label loop, around; 5342 5343 bind(loop); 5344 ldrd(vtmp2, post(src, 8)); 5345 sub(rscratch1, rscratch1, 1); 5346 zip1(vtmp3, T16B, vtmp2, vtmp1); 5347 st1(vtmp3, T8H, post(dst, 16)); 5348 cbnz(rscratch1, loop); 5349 5350 bind(around); 5351 } 5352 5353 // Do the tail of up to 8 bytes. 5354 sub(src, src, 8); 5355 add(src, src, len, ext::uxtw, 0); 5356 ldrd(vtmp2, Address(src)); 5357 sub(dst, dst, 16); 5358 add(dst, dst, len, ext::uxtw, 1); 5359 zip1(vtmp3, T16B, vtmp2, vtmp1); 5360 st1(vtmp3, T8H, Address(dst)); 5361 5362 bind(done); 5363 } 5364 5365 // Compress char[] array to byte[]. 5366 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 5367 FloatRegister tmp1Reg, FloatRegister tmp2Reg, 5368 FloatRegister tmp3Reg, FloatRegister tmp4Reg, 5369 Register result) { 5370 encode_iso_array(src, dst, len, result, 5371 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg); 5372 cmp(len, zr); 5373 csel(result, result, zr, EQ); 5374 } 5375 5376 // get_thread() can be called anywhere inside generated code so we 5377 // need to save whatever non-callee save context might get clobbered 5378 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 5379 // the call setup code. 5380 // 5381 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 5382 // 5383 void MacroAssembler::get_thread(Register dst) { 5384 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 5385 push(saved_regs, sp); 5386 5387 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 5388 blrt(lr, 1, 0, 1); 5389 if (dst != c_rarg0) { 5390 mov(dst, c_rarg0); 5391 } 5392 5393 pop(saved_regs, sp); 5394 }