1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "memory/allocation.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "opto/ad.hpp" 29 #include "opto/addnode.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/idealGraphPrinter.hpp" 32 #include "opto/matcher.hpp" 33 #include "opto/memnode.hpp" 34 #include "opto/movenode.hpp" 35 #include "opto/opcodes.hpp" 36 #include "opto/regmask.hpp" 37 #include "opto/rootnode.hpp" 38 #include "opto/runtime.hpp" 39 #include "opto/type.hpp" 40 #include "opto/vectornode.hpp" 41 #include "runtime/os.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 #include "utilities/align.hpp" 44 #if INCLUDE_ZGC 45 #include "gc/z/zBarrierSetRuntime.hpp" 46 #endif // INCLUDE_ZGC 47 #if INCLUDE_SHENANDOAHGC 48 #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" 49 #endif 50 51 OptoReg::Name OptoReg::c_frame_pointer; 52 53 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 54 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 55 RegMask Matcher::STACK_ONLY_mask; 56 RegMask Matcher::c_frame_ptr_mask; 57 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 58 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 59 60 //---------------------------Matcher------------------------------------------- 61 Matcher::Matcher() 62 : PhaseTransform( Phase::Ins_Select ), 63 #ifdef ASSERT 64 _old2new_map(C->comp_arena()), 65 _new2old_map(C->comp_arena()), 66 #endif 67 _shared_nodes(C->comp_arena()), 68 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 69 _swallowed(swallowed), 70 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 71 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 72 _must_clone(must_clone), 73 _register_save_policy(register_save_policy), 74 _c_reg_save_policy(c_reg_save_policy), 75 _register_save_type(register_save_type), 76 _ruleName(ruleName), 77 _allocation_started(false), 78 _states_arena(Chunk::medium_size, mtCompiler), 79 _visited(&_states_arena), 80 _shared(&_states_arena), 81 _dontcare(&_states_arena) { 82 C->set_matcher(this); 83 84 idealreg2spillmask [Op_RegI] = NULL; 85 idealreg2spillmask [Op_RegN] = NULL; 86 idealreg2spillmask [Op_RegL] = NULL; 87 idealreg2spillmask [Op_RegF] = NULL; 88 idealreg2spillmask [Op_RegD] = NULL; 89 idealreg2spillmask [Op_RegP] = NULL; 90 idealreg2spillmask [Op_VecS] = NULL; 91 idealreg2spillmask [Op_VecD] = NULL; 92 idealreg2spillmask [Op_VecX] = NULL; 93 idealreg2spillmask [Op_VecY] = NULL; 94 idealreg2spillmask [Op_VecZ] = NULL; 95 idealreg2spillmask [Op_RegFlags] = NULL; 96 97 idealreg2debugmask [Op_RegI] = NULL; 98 idealreg2debugmask [Op_RegN] = NULL; 99 idealreg2debugmask [Op_RegL] = NULL; 100 idealreg2debugmask [Op_RegF] = NULL; 101 idealreg2debugmask [Op_RegD] = NULL; 102 idealreg2debugmask [Op_RegP] = NULL; 103 idealreg2debugmask [Op_VecS] = NULL; 104 idealreg2debugmask [Op_VecD] = NULL; 105 idealreg2debugmask [Op_VecX] = NULL; 106 idealreg2debugmask [Op_VecY] = NULL; 107 idealreg2debugmask [Op_VecZ] = NULL; 108 idealreg2debugmask [Op_RegFlags] = NULL; 109 110 idealreg2mhdebugmask[Op_RegI] = NULL; 111 idealreg2mhdebugmask[Op_RegN] = NULL; 112 idealreg2mhdebugmask[Op_RegL] = NULL; 113 idealreg2mhdebugmask[Op_RegF] = NULL; 114 idealreg2mhdebugmask[Op_RegD] = NULL; 115 idealreg2mhdebugmask[Op_RegP] = NULL; 116 idealreg2mhdebugmask[Op_VecS] = NULL; 117 idealreg2mhdebugmask[Op_VecD] = NULL; 118 idealreg2mhdebugmask[Op_VecX] = NULL; 119 idealreg2mhdebugmask[Op_VecY] = NULL; 120 idealreg2mhdebugmask[Op_VecZ] = NULL; 121 idealreg2mhdebugmask[Op_RegFlags] = NULL; 122 123 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 124 } 125 126 //------------------------------warp_incoming_stk_arg------------------------ 127 // This warps a VMReg into an OptoReg::Name 128 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 129 OptoReg::Name warped; 130 if( reg->is_stack() ) { // Stack slot argument? 131 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 132 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 133 if( warped >= _in_arg_limit ) 134 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 135 if (!RegMask::can_represent_arg(warped)) { 136 // the compiler cannot represent this method's calling sequence 137 C->record_method_not_compilable("unsupported incoming calling sequence"); 138 return OptoReg::Bad; 139 } 140 return warped; 141 } 142 return OptoReg::as_OptoReg(reg); 143 } 144 145 //---------------------------compute_old_SP------------------------------------ 146 OptoReg::Name Compile::compute_old_SP() { 147 int fixed = fixed_slots(); 148 int preserve = in_preserve_stack_slots(); 149 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots())); 150 } 151 152 153 154 #ifdef ASSERT 155 void Matcher::verify_new_nodes_only(Node* xroot) { 156 // Make sure that the new graph only references new nodes 157 ResourceMark rm; 158 Unique_Node_List worklist; 159 VectorSet visited(Thread::current()->resource_area()); 160 worklist.push(xroot); 161 while (worklist.size() > 0) { 162 Node* n = worklist.pop(); 163 visited <<= n->_idx; 164 assert(C->node_arena()->contains(n), "dead node"); 165 for (uint j = 0; j < n->req(); j++) { 166 Node* in = n->in(j); 167 if (in != NULL) { 168 assert(C->node_arena()->contains(in), "dead node"); 169 if (!visited.test(in->_idx)) { 170 worklist.push(in); 171 } 172 } 173 } 174 } 175 } 176 #endif 177 178 179 //---------------------------match--------------------------------------------- 180 void Matcher::match( ) { 181 if( MaxLabelRootDepth < 100 ) { // Too small? 182 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 183 MaxLabelRootDepth = 100; 184 } 185 // One-time initialization of some register masks. 186 init_spill_mask( C->root()->in(1) ); 187 _return_addr_mask = return_addr(); 188 #ifdef _LP64 189 // Pointers take 2 slots in 64-bit land 190 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 191 #endif 192 193 // Map a Java-signature return type into return register-value 194 // machine registers for 0, 1 and 2 returned values. 195 const TypeTuple *range = C->tf()->range(); 196 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 197 // Get ideal-register return type 198 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 199 // Get machine return register 200 uint sop = C->start()->Opcode(); 201 OptoRegPair regs = return_value(ireg, false); 202 203 // And mask for same 204 _return_value_mask = RegMask(regs.first()); 205 if( OptoReg::is_valid(regs.second()) ) 206 _return_value_mask.Insert(regs.second()); 207 } 208 209 // --------------- 210 // Frame Layout 211 212 // Need the method signature to determine the incoming argument types, 213 // because the types determine which registers the incoming arguments are 214 // in, and this affects the matched code. 215 const TypeTuple *domain = C->tf()->domain(); 216 uint argcnt = domain->cnt() - TypeFunc::Parms; 217 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 218 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 219 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 220 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 221 uint i; 222 for( i = 0; i<argcnt; i++ ) { 223 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 224 } 225 226 // Pass array of ideal registers and length to USER code (from the AD file) 227 // that will convert this to an array of register numbers. 228 const StartNode *start = C->start(); 229 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 230 #ifdef ASSERT 231 // Sanity check users' calling convention. Real handy while trying to 232 // get the initial port correct. 233 { for (uint i = 0; i<argcnt; i++) { 234 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 235 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 236 _parm_regs[i].set_bad(); 237 continue; 238 } 239 VMReg parm_reg = vm_parm_regs[i].first(); 240 assert(parm_reg->is_valid(), "invalid arg?"); 241 if (parm_reg->is_reg()) { 242 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 243 assert(can_be_java_arg(opto_parm_reg) || 244 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 245 opto_parm_reg == inline_cache_reg(), 246 "parameters in register must be preserved by runtime stubs"); 247 } 248 for (uint j = 0; j < i; j++) { 249 assert(parm_reg != vm_parm_regs[j].first(), 250 "calling conv. must produce distinct regs"); 251 } 252 } 253 } 254 #endif 255 256 // Do some initial frame layout. 257 258 // Compute the old incoming SP (may be called FP) as 259 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 260 _old_SP = C->compute_old_SP(); 261 assert( is_even(_old_SP), "must be even" ); 262 263 // Compute highest incoming stack argument as 264 // _old_SP + out_preserve_stack_slots + incoming argument size. 265 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 266 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 267 for( i = 0; i < argcnt; i++ ) { 268 // Permit args to have no register 269 _calling_convention_mask[i].Clear(); 270 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 271 continue; 272 } 273 // calling_convention returns stack arguments as a count of 274 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 275 // the allocators point of view, taking into account all the 276 // preserve area, locks & pad2. 277 278 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 279 if( OptoReg::is_valid(reg1)) 280 _calling_convention_mask[i].Insert(reg1); 281 282 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 283 if( OptoReg::is_valid(reg2)) 284 _calling_convention_mask[i].Insert(reg2); 285 286 // Saved biased stack-slot register number 287 _parm_regs[i].set_pair(reg2, reg1); 288 } 289 290 // Finally, make sure the incoming arguments take up an even number of 291 // words, in case the arguments or locals need to contain doubleword stack 292 // slots. The rest of the system assumes that stack slot pairs (in 293 // particular, in the spill area) which look aligned will in fact be 294 // aligned relative to the stack pointer in the target machine. Double 295 // stack slots will always be allocated aligned. 296 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong)); 297 298 // Compute highest outgoing stack argument as 299 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 300 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 301 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 302 303 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 304 // the compiler cannot represent this method's calling sequence 305 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 306 } 307 308 if (C->failing()) return; // bailed out on incoming arg failure 309 310 // --------------- 311 // Collect roots of matcher trees. Every node for which 312 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 313 // can be a valid interior of some tree. 314 find_shared( C->root() ); 315 find_shared( C->top() ); 316 317 C->print_method(PHASE_BEFORE_MATCHING); 318 319 // Create new ideal node ConP #NULL even if it does exist in old space 320 // to avoid false sharing if the corresponding mach node is not used. 321 // The corresponding mach node is only used in rare cases for derived 322 // pointers. 323 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 324 325 // Swap out to old-space; emptying new-space 326 Arena *old = C->node_arena()->move_contents(C->old_arena()); 327 328 // Save debug and profile information for nodes in old space: 329 _old_node_note_array = C->node_note_array(); 330 if (_old_node_note_array != NULL) { 331 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 332 (C->comp_arena(), _old_node_note_array->length(), 333 0, NULL)); 334 } 335 336 // Pre-size the new_node table to avoid the need for range checks. 337 grow_new_node_array(C->unique()); 338 339 // Reset node counter so MachNodes start with _idx at 0 340 int live_nodes = C->live_nodes(); 341 C->set_unique(0); 342 C->reset_dead_node_list(); 343 344 // Recursively match trees from old space into new space. 345 // Correct leaves of new-space Nodes; they point to old-space. 346 _visited.Clear(); // Clear visit bits for xform call 347 C->set_cached_top_node(xform( C->top(), live_nodes )); 348 if (!C->failing()) { 349 Node* xroot = xform( C->root(), 1 ); 350 if (xroot == NULL) { 351 Matcher::soft_match_failure(); // recursive matching process failed 352 C->record_method_not_compilable("instruction match failed"); 353 } else { 354 // During matching shared constants were attached to C->root() 355 // because xroot wasn't available yet, so transfer the uses to 356 // the xroot. 357 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 358 Node* n = C->root()->fast_out(j); 359 if (C->node_arena()->contains(n)) { 360 assert(n->in(0) == C->root(), "should be control user"); 361 n->set_req(0, xroot); 362 --j; 363 --jmax; 364 } 365 } 366 367 // Generate new mach node for ConP #NULL 368 assert(new_ideal_null != NULL, "sanity"); 369 _mach_null = match_tree(new_ideal_null); 370 // Don't set control, it will confuse GCM since there are no uses. 371 // The control will be set when this node is used first time 372 // in find_base_for_derived(). 373 assert(_mach_null != NULL, ""); 374 375 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 376 377 #ifdef ASSERT 378 verify_new_nodes_only(xroot); 379 #endif 380 } 381 } 382 if (C->top() == NULL || C->root() == NULL) { 383 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 384 } 385 if (C->failing()) { 386 // delete old; 387 old->destruct_contents(); 388 return; 389 } 390 assert( C->top(), "" ); 391 assert( C->root(), "" ); 392 validate_null_checks(); 393 394 // Now smoke old-space 395 NOT_DEBUG( old->destruct_contents() ); 396 397 // ------------------------ 398 // Set up save-on-entry registers 399 Fixup_Save_On_Entry( ); 400 } 401 402 403 //------------------------------Fixup_Save_On_Entry---------------------------- 404 // The stated purpose of this routine is to take care of save-on-entry 405 // registers. However, the overall goal of the Match phase is to convert into 406 // machine-specific instructions which have RegMasks to guide allocation. 407 // So what this procedure really does is put a valid RegMask on each input 408 // to the machine-specific variations of all Return, TailCall and Halt 409 // instructions. It also adds edgs to define the save-on-entry values (and of 410 // course gives them a mask). 411 412 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 413 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 414 // Do all the pre-defined register masks 415 rms[TypeFunc::Control ] = RegMask::Empty; 416 rms[TypeFunc::I_O ] = RegMask::Empty; 417 rms[TypeFunc::Memory ] = RegMask::Empty; 418 rms[TypeFunc::ReturnAdr] = ret_adr; 419 rms[TypeFunc::FramePtr ] = fp; 420 return rms; 421 } 422 423 //---------------------------init_first_stack_mask----------------------------- 424 // Create the initial stack mask used by values spilling to the stack. 425 // Disallow any debug info in outgoing argument areas by setting the 426 // initial mask accordingly. 427 void Matcher::init_first_stack_mask() { 428 429 // Allocate storage for spill masks as masks for the appropriate load type. 430 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); 431 432 idealreg2spillmask [Op_RegN] = &rms[0]; 433 idealreg2spillmask [Op_RegI] = &rms[1]; 434 idealreg2spillmask [Op_RegL] = &rms[2]; 435 idealreg2spillmask [Op_RegF] = &rms[3]; 436 idealreg2spillmask [Op_RegD] = &rms[4]; 437 idealreg2spillmask [Op_RegP] = &rms[5]; 438 439 idealreg2debugmask [Op_RegN] = &rms[6]; 440 idealreg2debugmask [Op_RegI] = &rms[7]; 441 idealreg2debugmask [Op_RegL] = &rms[8]; 442 idealreg2debugmask [Op_RegF] = &rms[9]; 443 idealreg2debugmask [Op_RegD] = &rms[10]; 444 idealreg2debugmask [Op_RegP] = &rms[11]; 445 446 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 447 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 448 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 449 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 450 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 451 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 452 453 idealreg2spillmask [Op_VecS] = &rms[18]; 454 idealreg2spillmask [Op_VecD] = &rms[19]; 455 idealreg2spillmask [Op_VecX] = &rms[20]; 456 idealreg2spillmask [Op_VecY] = &rms[21]; 457 idealreg2spillmask [Op_VecZ] = &rms[22]; 458 459 OptoReg::Name i; 460 461 // At first, start with the empty mask 462 C->FIRST_STACK_mask().Clear(); 463 464 // Add in the incoming argument area 465 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 466 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 467 C->FIRST_STACK_mask().Insert(i); 468 } 469 // Add in all bits past the outgoing argument area 470 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 471 "must be able to represent all call arguments in reg mask"); 472 OptoReg::Name init = _out_arg_limit; 473 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 474 C->FIRST_STACK_mask().Insert(i); 475 } 476 // Finally, set the "infinite stack" bit. 477 C->FIRST_STACK_mask().set_AllStack(); 478 479 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 480 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 481 // Keep spill masks aligned. 482 aligned_stack_mask.clear_to_pairs(); 483 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 484 485 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 486 #ifdef _LP64 487 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 488 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 489 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 490 #else 491 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 492 #endif 493 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 494 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 495 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 496 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 497 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 498 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 499 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 500 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 501 502 if (Matcher::vector_size_supported(T_BYTE,4)) { 503 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 504 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 505 } 506 if (Matcher::vector_size_supported(T_FLOAT,2)) { 507 // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 508 // RA guarantees such alignment since it is needed for Double and Long values. 509 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 510 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 511 } 512 if (Matcher::vector_size_supported(T_FLOAT,4)) { 513 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 514 // 515 // RA can use input arguments stack slots for spills but until RA 516 // we don't know frame size and offset of input arg stack slots. 517 // 518 // Exclude last input arg stack slots to avoid spilling vectors there 519 // otherwise vector spills could stomp over stack slots in caller frame. 520 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 521 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 522 aligned_stack_mask.Remove(in); 523 in = OptoReg::add(in, -1); 524 } 525 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 526 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 527 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 528 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 529 } 530 if (Matcher::vector_size_supported(T_FLOAT,8)) { 531 // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 532 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 533 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 534 aligned_stack_mask.Remove(in); 535 in = OptoReg::add(in, -1); 536 } 537 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 538 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 539 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 540 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 541 } 542 if (Matcher::vector_size_supported(T_FLOAT,16)) { 543 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 544 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 545 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 546 aligned_stack_mask.Remove(in); 547 in = OptoReg::add(in, -1); 548 } 549 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 550 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 551 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 552 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 553 } 554 if (UseFPUForSpilling) { 555 // This mask logic assumes that the spill operations are 556 // symmetric and that the registers involved are the same size. 557 // On sparc for instance we may have to use 64 bit moves will 558 // kill 2 registers when used with F0-F31. 559 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 560 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 561 #ifdef _LP64 562 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 563 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 564 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 565 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 566 #else 567 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 568 #ifdef ARM 569 // ARM has support for moving 64bit values between a pair of 570 // integer registers and a double register 571 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 572 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 573 #endif 574 #endif 575 } 576 577 // Make up debug masks. Any spill slot plus callee-save registers. 578 // Caller-save registers are assumed to be trashable by the various 579 // inline-cache fixup routines. 580 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 581 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 582 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 583 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 584 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 585 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 586 587 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 588 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 589 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 590 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 591 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 592 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 593 594 // Prevent stub compilations from attempting to reference 595 // callee-saved registers from debug info 596 bool exclude_soe = !Compile::current()->is_method_compilation(); 597 598 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 599 // registers the caller has to save do not work 600 if( _register_save_policy[i] == 'C' || 601 _register_save_policy[i] == 'A' || 602 (_register_save_policy[i] == 'E' && exclude_soe) ) { 603 idealreg2debugmask [Op_RegN]->Remove(i); 604 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 605 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 606 idealreg2debugmask [Op_RegF]->Remove(i); // masks 607 idealreg2debugmask [Op_RegD]->Remove(i); 608 idealreg2debugmask [Op_RegP]->Remove(i); 609 610 idealreg2mhdebugmask[Op_RegN]->Remove(i); 611 idealreg2mhdebugmask[Op_RegI]->Remove(i); 612 idealreg2mhdebugmask[Op_RegL]->Remove(i); 613 idealreg2mhdebugmask[Op_RegF]->Remove(i); 614 idealreg2mhdebugmask[Op_RegD]->Remove(i); 615 idealreg2mhdebugmask[Op_RegP]->Remove(i); 616 } 617 } 618 619 // Subtract the register we use to save the SP for MethodHandle 620 // invokes to from the debug mask. 621 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 622 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 623 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 624 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 625 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 626 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 627 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 628 } 629 630 //---------------------------is_save_on_entry---------------------------------- 631 bool Matcher::is_save_on_entry( int reg ) { 632 return 633 _register_save_policy[reg] == 'E' || 634 _register_save_policy[reg] == 'A' || // Save-on-entry register? 635 // Also save argument registers in the trampolining stubs 636 (C->save_argument_registers() && is_spillable_arg(reg)); 637 } 638 639 //---------------------------Fixup_Save_On_Entry------------------------------- 640 void Matcher::Fixup_Save_On_Entry( ) { 641 init_first_stack_mask(); 642 643 Node *root = C->root(); // Short name for root 644 // Count number of save-on-entry registers. 645 uint soe_cnt = number_of_saved_registers(); 646 uint i; 647 648 // Find the procedure Start Node 649 StartNode *start = C->start(); 650 assert( start, "Expect a start node" ); 651 652 // Save argument registers in the trampolining stubs 653 if( C->save_argument_registers() ) 654 for( i = 0; i < _last_Mach_Reg; i++ ) 655 if( is_spillable_arg(i) ) 656 soe_cnt++; 657 658 // Input RegMask array shared by all Returns. 659 // The type for doubles and longs has a count of 2, but 660 // there is only 1 returned value 661 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 662 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 663 // Returns have 0 or 1 returned values depending on call signature. 664 // Return register is specified by return_value in the AD file. 665 if (ret_edge_cnt > TypeFunc::Parms) 666 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 667 668 // Input RegMask array shared by all Rethrows. 669 uint reth_edge_cnt = TypeFunc::Parms+1; 670 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 671 // Rethrow takes exception oop only, but in the argument 0 slot. 672 OptoReg::Name reg = find_receiver(false); 673 if (reg >= 0) { 674 reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 675 #ifdef _LP64 676 // Need two slots for ptrs in 64-bit land 677 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 678 #endif 679 } 680 681 // Input RegMask array shared by all TailCalls 682 uint tail_call_edge_cnt = TypeFunc::Parms+2; 683 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 684 685 // Input RegMask array shared by all TailJumps 686 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 687 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 688 689 // TailCalls have 2 returned values (target & moop), whose masks come 690 // from the usual MachNode/MachOper mechanism. Find a sample 691 // TailCall to extract these masks and put the correct masks into 692 // the tail_call_rms array. 693 for( i=1; i < root->req(); i++ ) { 694 MachReturnNode *m = root->in(i)->as_MachReturn(); 695 if( m->ideal_Opcode() == Op_TailCall ) { 696 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 697 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 698 break; 699 } 700 } 701 702 // TailJumps have 2 returned values (target & ex_oop), whose masks come 703 // from the usual MachNode/MachOper mechanism. Find a sample 704 // TailJump to extract these masks and put the correct masks into 705 // the tail_jump_rms array. 706 for( i=1; i < root->req(); i++ ) { 707 MachReturnNode *m = root->in(i)->as_MachReturn(); 708 if( m->ideal_Opcode() == Op_TailJump ) { 709 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 710 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 711 break; 712 } 713 } 714 715 // Input RegMask array shared by all Halts 716 uint halt_edge_cnt = TypeFunc::Parms; 717 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 718 719 // Capture the return input masks into each exit flavor 720 for( i=1; i < root->req(); i++ ) { 721 MachReturnNode *exit = root->in(i)->as_MachReturn(); 722 switch( exit->ideal_Opcode() ) { 723 case Op_Return : exit->_in_rms = ret_rms; break; 724 case Op_Rethrow : exit->_in_rms = reth_rms; break; 725 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 726 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 727 case Op_Halt : exit->_in_rms = halt_rms; break; 728 default : ShouldNotReachHere(); 729 } 730 } 731 732 // Next unused projection number from Start. 733 int proj_cnt = C->tf()->domain()->cnt(); 734 735 // Do all the save-on-entry registers. Make projections from Start for 736 // them, and give them a use at the exit points. To the allocator, they 737 // look like incoming register arguments. 738 for( i = 0; i < _last_Mach_Reg; i++ ) { 739 if( is_save_on_entry(i) ) { 740 741 // Add the save-on-entry to the mask array 742 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 743 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 744 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 745 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 746 // Halts need the SOE registers, but only in the stack as debug info. 747 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 748 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 749 750 Node *mproj; 751 752 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 753 // into a single RegD. 754 if( (i&1) == 0 && 755 _register_save_type[i ] == Op_RegF && 756 _register_save_type[i+1] == Op_RegF && 757 is_save_on_entry(i+1) ) { 758 // Add other bit for double 759 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 760 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 761 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 762 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 763 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 764 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 765 proj_cnt += 2; // Skip 2 for doubles 766 } 767 else if( (i&1) == 1 && // Else check for high half of double 768 _register_save_type[i-1] == Op_RegF && 769 _register_save_type[i ] == Op_RegF && 770 is_save_on_entry(i-1) ) { 771 ret_rms [ ret_edge_cnt] = RegMask::Empty; 772 reth_rms [ reth_edge_cnt] = RegMask::Empty; 773 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 774 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 775 halt_rms [ halt_edge_cnt] = RegMask::Empty; 776 mproj = C->top(); 777 } 778 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 779 // into a single RegL. 780 else if( (i&1) == 0 && 781 _register_save_type[i ] == Op_RegI && 782 _register_save_type[i+1] == Op_RegI && 783 is_save_on_entry(i+1) ) { 784 // Add other bit for long 785 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 786 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 787 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 788 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 789 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 790 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 791 proj_cnt += 2; // Skip 2 for longs 792 } 793 else if( (i&1) == 1 && // Else check for high half of long 794 _register_save_type[i-1] == Op_RegI && 795 _register_save_type[i ] == Op_RegI && 796 is_save_on_entry(i-1) ) { 797 ret_rms [ ret_edge_cnt] = RegMask::Empty; 798 reth_rms [ reth_edge_cnt] = RegMask::Empty; 799 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 800 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 801 halt_rms [ halt_edge_cnt] = RegMask::Empty; 802 mproj = C->top(); 803 } else { 804 // Make a projection for it off the Start 805 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 806 } 807 808 ret_edge_cnt ++; 809 reth_edge_cnt ++; 810 tail_call_edge_cnt ++; 811 tail_jump_edge_cnt ++; 812 halt_edge_cnt ++; 813 814 // Add a use of the SOE register to all exit paths 815 for( uint j=1; j < root->req(); j++ ) 816 root->in(j)->add_req(mproj); 817 } // End of if a save-on-entry register 818 } // End of for all machine registers 819 } 820 821 //------------------------------init_spill_mask-------------------------------- 822 void Matcher::init_spill_mask( Node *ret ) { 823 if( idealreg2regmask[Op_RegI] ) return; // One time only init 824 825 OptoReg::c_frame_pointer = c_frame_pointer(); 826 c_frame_ptr_mask = c_frame_pointer(); 827 #ifdef _LP64 828 // pointers are twice as big 829 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 830 #endif 831 832 // Start at OptoReg::stack0() 833 STACK_ONLY_mask.Clear(); 834 OptoReg::Name init = OptoReg::stack2reg(0); 835 // STACK_ONLY_mask is all stack bits 836 OptoReg::Name i; 837 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 838 STACK_ONLY_mask.Insert(i); 839 // Also set the "infinite stack" bit. 840 STACK_ONLY_mask.set_AllStack(); 841 842 // Copy the register names over into the shared world 843 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 844 // SharedInfo::regName[i] = regName[i]; 845 // Handy RegMasks per machine register 846 mreg2regmask[i].Insert(i); 847 } 848 849 // Grab the Frame Pointer 850 Node *fp = ret->in(TypeFunc::FramePtr); 851 Node *mem = ret->in(TypeFunc::Memory); 852 const TypePtr* atp = TypePtr::BOTTOM; 853 // Share frame pointer while making spill ops 854 set_shared(fp); 855 856 // Compute generic short-offset Loads 857 #ifdef _LP64 858 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 859 #endif 860 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered)); 861 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false)); 862 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered)); 863 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered)); 864 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 865 assert(spillI != NULL && spillL != NULL && spillF != NULL && 866 spillD != NULL && spillP != NULL, ""); 867 // Get the ADLC notion of the right regmask, for each basic type. 868 #ifdef _LP64 869 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 870 #endif 871 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 872 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 873 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 874 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 875 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 876 877 // Vector regmasks. 878 if (Matcher::vector_size_supported(T_BYTE,4)) { 879 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 880 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 881 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 882 } 883 if (Matcher::vector_size_supported(T_FLOAT,2)) { 884 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 885 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 886 } 887 if (Matcher::vector_size_supported(T_FLOAT,4)) { 888 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 889 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 890 } 891 if (Matcher::vector_size_supported(T_FLOAT,8)) { 892 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 893 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 894 } 895 if (Matcher::vector_size_supported(T_FLOAT,16)) { 896 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ)); 897 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask(); 898 } 899 } 900 901 #ifdef ASSERT 902 static void match_alias_type(Compile* C, Node* n, Node* m) { 903 if (!VerifyAliases) return; // do not go looking for trouble by default 904 const TypePtr* nat = n->adr_type(); 905 const TypePtr* mat = m->adr_type(); 906 int nidx = C->get_alias_index(nat); 907 int midx = C->get_alias_index(mat); 908 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 909 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 910 for (uint i = 1; i < n->req(); i++) { 911 Node* n1 = n->in(i); 912 const TypePtr* n1at = n1->adr_type(); 913 if (n1at != NULL) { 914 nat = n1at; 915 nidx = C->get_alias_index(n1at); 916 } 917 } 918 } 919 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 920 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 921 switch (n->Opcode()) { 922 case Op_PrefetchAllocation: 923 nidx = Compile::AliasIdxRaw; 924 nat = TypeRawPtr::BOTTOM; 925 break; 926 } 927 } 928 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 929 switch (n->Opcode()) { 930 case Op_ClearArray: 931 midx = Compile::AliasIdxRaw; 932 mat = TypeRawPtr::BOTTOM; 933 break; 934 } 935 } 936 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 937 switch (n->Opcode()) { 938 case Op_Return: 939 case Op_Rethrow: 940 case Op_Halt: 941 case Op_TailCall: 942 case Op_TailJump: 943 nidx = Compile::AliasIdxBot; 944 nat = TypePtr::BOTTOM; 945 break; 946 } 947 } 948 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 949 switch (n->Opcode()) { 950 case Op_StrComp: 951 case Op_StrEquals: 952 case Op_StrIndexOf: 953 case Op_StrIndexOfChar: 954 case Op_AryEq: 955 case Op_HasNegatives: 956 case Op_MemBarVolatile: 957 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 958 case Op_StrInflatedCopy: 959 case Op_StrCompressedCopy: 960 case Op_OnSpinWait: 961 case Op_EncodeISOArray: 962 nidx = Compile::AliasIdxTop; 963 nat = NULL; 964 break; 965 } 966 } 967 if (nidx != midx) { 968 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 969 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 970 n->dump(); 971 m->dump(); 972 } 973 assert(C->subsume_loads() && C->must_alias(nat, midx), 974 "must not lose alias info when matching"); 975 } 976 } 977 #endif 978 979 //------------------------------xform------------------------------------------ 980 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine 981 // Node in new-space. Given a new-space Node, recursively walk his children. 982 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 983 Node *Matcher::xform( Node *n, int max_stack ) { 984 // Use one stack to keep both: child's node/state and parent's node/index 985 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 986 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 987 while (mstack.is_nonempty()) { 988 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 989 if (C->failing()) return NULL; 990 n = mstack.node(); // Leave node on stack 991 Node_State nstate = mstack.state(); 992 if (nstate == Visit) { 993 mstack.set_state(Post_Visit); 994 Node *oldn = n; 995 // Old-space or new-space check 996 if (!C->node_arena()->contains(n)) { 997 // Old space! 998 Node* m; 999 if (has_new_node(n)) { // Not yet Label/Reduced 1000 m = new_node(n); 1001 } else { 1002 if (!is_dontcare(n)) { // Matcher can match this guy 1003 // Calls match special. They match alone with no children. 1004 // Their children, the incoming arguments, match normally. 1005 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1006 if (C->failing()) return NULL; 1007 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1008 } else { // Nothing the matcher cares about 1009 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections? 1010 // Convert to machine-dependent projection 1011 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1012 #ifdef ASSERT 1013 _new2old_map.map(m->_idx, n); 1014 #endif 1015 if (m->in(0) != NULL) // m might be top 1016 collect_null_checks(m, n); 1017 } else { // Else just a regular 'ol guy 1018 m = n->clone(); // So just clone into new-space 1019 #ifdef ASSERT 1020 _new2old_map.map(m->_idx, n); 1021 #endif 1022 // Def-Use edges will be added incrementally as Uses 1023 // of this node are matched. 1024 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1025 } 1026 } 1027 1028 set_new_node(n, m); // Map old to new 1029 if (_old_node_note_array != NULL) { 1030 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1031 n->_idx); 1032 C->set_node_notes_at(m->_idx, nn); 1033 } 1034 debug_only(match_alias_type(C, n, m)); 1035 } 1036 n = m; // n is now a new-space node 1037 mstack.set_node(n); 1038 } 1039 1040 // New space! 1041 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1042 1043 int i; 1044 // Put precedence edges on stack first (match them last). 1045 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1046 Node *m = oldn->in(i); 1047 if (m == NULL) break; 1048 // set -1 to call add_prec() instead of set_req() during Step1 1049 mstack.push(m, Visit, n, -1); 1050 } 1051 1052 // Handle precedence edges for interior nodes 1053 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1054 Node *m = n->in(i); 1055 if (m == NULL || C->node_arena()->contains(m)) continue; 1056 n->rm_prec(i); 1057 // set -1 to call add_prec() instead of set_req() during Step1 1058 mstack.push(m, Visit, n, -1); 1059 } 1060 1061 // For constant debug info, I'd rather have unmatched constants. 1062 int cnt = n->req(); 1063 JVMState* jvms = n->jvms(); 1064 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1065 1066 // Now do only debug info. Clone constants rather than matching. 1067 // Constants are represented directly in the debug info without 1068 // the need for executable machine instructions. 1069 // Monitor boxes are also represented directly. 1070 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1071 Node *m = n->in(i); // Get input 1072 int op = m->Opcode(); 1073 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1074 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1075 op == Op_ConF || op == Op_ConD || op == Op_ConL 1076 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1077 ) { 1078 m = m->clone(); 1079 #ifdef ASSERT 1080 _new2old_map.map(m->_idx, n); 1081 #endif 1082 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1083 mstack.push(m->in(0), Visit, m, 0); 1084 } else { 1085 mstack.push(m, Visit, n, i); 1086 } 1087 } 1088 1089 // And now walk his children, and convert his inputs to new-space. 1090 for( ; i >= 0; --i ) { // For all normal inputs do 1091 Node *m = n->in(i); // Get input 1092 if(m != NULL) 1093 mstack.push(m, Visit, n, i); 1094 } 1095 1096 } 1097 else if (nstate == Post_Visit) { 1098 // Set xformed input 1099 Node *p = mstack.parent(); 1100 if (p != NULL) { // root doesn't have parent 1101 int i = (int)mstack.index(); 1102 if (i >= 0) 1103 p->set_req(i, n); // required input 1104 else if (i == -1) 1105 p->add_prec(n); // precedence input 1106 else 1107 ShouldNotReachHere(); 1108 } 1109 mstack.pop(); // remove processed node from stack 1110 } 1111 else { 1112 ShouldNotReachHere(); 1113 } 1114 } // while (mstack.is_nonempty()) 1115 return n; // Return new-space Node 1116 } 1117 1118 //------------------------------warp_outgoing_stk_arg------------------------ 1119 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1120 // Convert outgoing argument location to a pre-biased stack offset 1121 if (reg->is_stack()) { 1122 OptoReg::Name warped = reg->reg2stack(); 1123 // Adjust the stack slot offset to be the register number used 1124 // by the allocator. 1125 warped = OptoReg::add(begin_out_arg_area, warped); 1126 // Keep track of the largest numbered stack slot used for an arg. 1127 // Largest used slot per call-site indicates the amount of stack 1128 // that is killed by the call. 1129 if( warped >= out_arg_limit_per_call ) 1130 out_arg_limit_per_call = OptoReg::add(warped,1); 1131 if (!RegMask::can_represent_arg(warped)) { 1132 C->record_method_not_compilable("unsupported calling sequence"); 1133 return OptoReg::Bad; 1134 } 1135 return warped; 1136 } 1137 return OptoReg::as_OptoReg(reg); 1138 } 1139 1140 1141 //------------------------------match_sfpt------------------------------------- 1142 // Helper function to match call instructions. Calls match special. 1143 // They match alone with no children. Their children, the incoming 1144 // arguments, match normally. 1145 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1146 MachSafePointNode *msfpt = NULL; 1147 MachCallNode *mcall = NULL; 1148 uint cnt; 1149 // Split out case for SafePoint vs Call 1150 CallNode *call; 1151 const TypeTuple *domain; 1152 ciMethod* method = NULL; 1153 bool is_method_handle_invoke = false; // for special kill effects 1154 if( sfpt->is_Call() ) { 1155 call = sfpt->as_Call(); 1156 domain = call->tf()->domain(); 1157 cnt = domain->cnt(); 1158 1159 // Match just the call, nothing else 1160 MachNode *m = match_tree(call); 1161 if (C->failing()) return NULL; 1162 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1163 1164 // Copy data from the Ideal SafePoint to the machine version 1165 mcall = m->as_MachCall(); 1166 1167 mcall->set_tf( call->tf()); 1168 mcall->set_entry_point(call->entry_point()); 1169 mcall->set_cnt( call->cnt()); 1170 1171 if( mcall->is_MachCallJava() ) { 1172 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1173 const CallJavaNode *call_java = call->as_CallJava(); 1174 method = call_java->method(); 1175 mcall_java->_method = method; 1176 mcall_java->_bci = call_java->_bci; 1177 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1178 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1179 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1180 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1181 if (is_method_handle_invoke) { 1182 C->set_has_method_handle_invokes(true); 1183 } 1184 if( mcall_java->is_MachCallStaticJava() ) 1185 mcall_java->as_MachCallStaticJava()->_name = 1186 call_java->as_CallStaticJava()->_name; 1187 if( mcall_java->is_MachCallDynamicJava() ) 1188 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1189 call_java->as_CallDynamicJava()->_vtable_index; 1190 } 1191 else if( mcall->is_MachCallRuntime() ) { 1192 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1193 } 1194 msfpt = mcall; 1195 } 1196 // This is a non-call safepoint 1197 else { 1198 call = NULL; 1199 domain = NULL; 1200 MachNode *mn = match_tree(sfpt); 1201 if (C->failing()) return NULL; 1202 msfpt = mn->as_MachSafePoint(); 1203 cnt = TypeFunc::Parms; 1204 } 1205 1206 // Advertise the correct memory effects (for anti-dependence computation). 1207 msfpt->set_adr_type(sfpt->adr_type()); 1208 1209 // Allocate a private array of RegMasks. These RegMasks are not shared. 1210 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1211 // Empty them all. 1212 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); 1213 1214 // Do all the pre-defined non-Empty register masks 1215 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1216 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1217 1218 // Place first outgoing argument can possibly be put. 1219 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1220 assert( is_even(begin_out_arg_area), "" ); 1221 // Compute max outgoing register number per call site. 1222 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1223 // Calls to C may hammer extra stack slots above and beyond any arguments. 1224 // These are usually backing store for register arguments for varargs. 1225 if( call != NULL && call->is_CallRuntime() ) 1226 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1227 1228 1229 // Do the normal argument list (parameters) register masks 1230 int argcnt = cnt - TypeFunc::Parms; 1231 if( argcnt > 0 ) { // Skip it all if we have no args 1232 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1233 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1234 int i; 1235 for( i = 0; i < argcnt; i++ ) { 1236 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1237 } 1238 // V-call to pick proper calling convention 1239 call->calling_convention( sig_bt, parm_regs, argcnt ); 1240 1241 #ifdef ASSERT 1242 // Sanity check users' calling convention. Really handy during 1243 // the initial porting effort. Fairly expensive otherwise. 1244 { for (int i = 0; i<argcnt; i++) { 1245 if( !parm_regs[i].first()->is_valid() && 1246 !parm_regs[i].second()->is_valid() ) continue; 1247 VMReg reg1 = parm_regs[i].first(); 1248 VMReg reg2 = parm_regs[i].second(); 1249 for (int j = 0; j < i; j++) { 1250 if( !parm_regs[j].first()->is_valid() && 1251 !parm_regs[j].second()->is_valid() ) continue; 1252 VMReg reg3 = parm_regs[j].first(); 1253 VMReg reg4 = parm_regs[j].second(); 1254 if( !reg1->is_valid() ) { 1255 assert( !reg2->is_valid(), "valid halvsies" ); 1256 } else if( !reg3->is_valid() ) { 1257 assert( !reg4->is_valid(), "valid halvsies" ); 1258 } else { 1259 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1260 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1261 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1262 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1263 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1264 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1265 } 1266 } 1267 } 1268 } 1269 #endif 1270 1271 // Visit each argument. Compute its outgoing register mask. 1272 // Return results now can have 2 bits returned. 1273 // Compute max over all outgoing arguments both per call-site 1274 // and over the entire method. 1275 for( i = 0; i < argcnt; i++ ) { 1276 // Address of incoming argument mask to fill in 1277 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1278 if( !parm_regs[i].first()->is_valid() && 1279 !parm_regs[i].second()->is_valid() ) { 1280 continue; // Avoid Halves 1281 } 1282 // Grab first register, adjust stack slots and insert in mask. 1283 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1284 if (OptoReg::is_valid(reg1)) 1285 rm->Insert( reg1 ); 1286 // Grab second register (if any), adjust stack slots and insert in mask. 1287 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1288 if (OptoReg::is_valid(reg2)) 1289 rm->Insert( reg2 ); 1290 } // End of for all arguments 1291 1292 // Compute number of stack slots needed to restore stack in case of 1293 // Pascal-style argument popping. 1294 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1295 } 1296 1297 // Compute the max stack slot killed by any call. These will not be 1298 // available for debug info, and will be used to adjust FIRST_STACK_mask 1299 // after all call sites have been visited. 1300 if( _out_arg_limit < out_arg_limit_per_call) 1301 _out_arg_limit = out_arg_limit_per_call; 1302 1303 if (mcall) { 1304 // Kill the outgoing argument area, including any non-argument holes and 1305 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1306 // Since the max-per-method covers the max-per-call-site and debug info 1307 // is excluded on the max-per-method basis, debug info cannot land in 1308 // this killed area. 1309 uint r_cnt = mcall->tf()->range()->cnt(); 1310 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1311 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1312 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1313 } else { 1314 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1315 proj->_rout.Insert(OptoReg::Name(i)); 1316 } 1317 if (proj->_rout.is_NotEmpty()) { 1318 push_projection(proj); 1319 } 1320 } 1321 // Transfer the safepoint information from the call to the mcall 1322 // Move the JVMState list 1323 msfpt->set_jvms(sfpt->jvms()); 1324 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1325 jvms->set_map(sfpt); 1326 } 1327 1328 // Debug inputs begin just after the last incoming parameter 1329 assert((mcall == NULL) || (mcall->jvms() == NULL) || 1330 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), ""); 1331 1332 // Move the OopMap 1333 msfpt->_oop_map = sfpt->_oop_map; 1334 1335 // Add additional edges. 1336 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1337 // For these calls we can not add MachConstantBase in expand(), as the 1338 // ins are not complete then. 1339 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1340 if (msfpt->jvms() && 1341 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1342 // We added an edge before jvms, so we must adapt the position of the ins. 1343 msfpt->jvms()->adapt_position(+1); 1344 } 1345 } 1346 1347 // Registers killed by the call are set in the local scheduling pass 1348 // of Global Code Motion. 1349 return msfpt; 1350 } 1351 1352 //---------------------------match_tree---------------------------------------- 1353 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1354 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1355 // making GotoNodes while building the CFG and in init_spill_mask() to identify 1356 // a Load's result RegMask for memoization in idealreg2regmask[] 1357 MachNode *Matcher::match_tree( const Node *n ) { 1358 assert( n->Opcode() != Op_Phi, "cannot match" ); 1359 assert( !n->is_block_start(), "cannot match" ); 1360 // Set the mark for all locally allocated State objects. 1361 // When this call returns, the _states_arena arena will be reset 1362 // freeing all State objects. 1363 ResourceMark rm( &_states_arena ); 1364 1365 LabelRootDepth = 0; 1366 1367 // StoreNodes require their Memory input to match any LoadNodes 1368 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1369 #ifdef ASSERT 1370 Node* save_mem_node = _mem_node; 1371 _mem_node = n->is_Store() ? (Node*)n : NULL; 1372 #endif 1373 // State object for root node of match tree 1374 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1375 State *s = new (&_states_arena) State; 1376 s->_kids[0] = NULL; 1377 s->_kids[1] = NULL; 1378 s->_leaf = (Node*)n; 1379 // Label the input tree, allocating labels from top-level arena 1380 Label_Root( n, s, n->in(0), mem ); 1381 if (C->failing()) return NULL; 1382 1383 // The minimum cost match for the whole tree is found at the root State 1384 uint mincost = max_juint; 1385 uint cost = max_juint; 1386 uint i; 1387 for( i = 0; i < NUM_OPERANDS; i++ ) { 1388 if( s->valid(i) && // valid entry and 1389 s->_cost[i] < cost && // low cost and 1390 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1391 cost = s->_cost[mincost=i]; 1392 } 1393 if (mincost == max_juint) { 1394 #ifndef PRODUCT 1395 tty->print("No matching rule for:"); 1396 s->dump(); 1397 #endif 1398 Matcher::soft_match_failure(); 1399 return NULL; 1400 } 1401 // Reduce input tree based upon the state labels to machine Nodes 1402 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1403 #ifdef ASSERT 1404 _old2new_map.map(n->_idx, m); 1405 _new2old_map.map(m->_idx, (Node*)n); 1406 #endif 1407 1408 // Add any Matcher-ignored edges 1409 uint cnt = n->req(); 1410 uint start = 1; 1411 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1412 if( n->is_AddP() ) { 1413 assert( mem == (Node*)1, "" ); 1414 start = AddPNode::Base+1; 1415 } 1416 for( i = start; i < cnt; i++ ) { 1417 if( !n->match_edge(i) ) { 1418 if( i < m->req() ) 1419 m->ins_req( i, n->in(i) ); 1420 else 1421 m->add_req( n->in(i) ); 1422 } 1423 } 1424 1425 debug_only( _mem_node = save_mem_node; ) 1426 return m; 1427 } 1428 1429 1430 //------------------------------match_into_reg--------------------------------- 1431 // Choose to either match this Node in a register or part of the current 1432 // match tree. Return true for requiring a register and false for matching 1433 // as part of the current match tree. 1434 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1435 1436 const Type *t = m->bottom_type(); 1437 1438 if (t->singleton()) { 1439 // Never force constants into registers. Allow them to match as 1440 // constants or registers. Copies of the same value will share 1441 // the same register. See find_shared_node. 1442 return false; 1443 } else { // Not a constant 1444 // Stop recursion if they have different Controls. 1445 Node* m_control = m->in(0); 1446 // Control of load's memory can post-dominates load's control. 1447 // So use it since load can't float above its memory. 1448 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1449 if (control && m_control && control != m_control && control != mem_control) { 1450 1451 // Actually, we can live with the most conservative control we 1452 // find, if it post-dominates the others. This allows us to 1453 // pick up load/op/store trees where the load can float a little 1454 // above the store. 1455 Node *x = control; 1456 const uint max_scan = 6; // Arbitrary scan cutoff 1457 uint j; 1458 for (j=0; j<max_scan; j++) { 1459 if (x->is_Region()) // Bail out at merge points 1460 return true; 1461 x = x->in(0); 1462 if (x == m_control) // Does 'control' post-dominate 1463 break; // m->in(0)? If so, we can use it 1464 if (x == mem_control) // Does 'control' post-dominate 1465 break; // mem_control? If so, we can use it 1466 } 1467 if (j == max_scan) // No post-domination before scan end? 1468 return true; // Then break the match tree up 1469 } 1470 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1471 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1472 // These are commonly used in address expressions and can 1473 // efficiently fold into them on X64 in some cases. 1474 return false; 1475 } 1476 } 1477 1478 // Not forceable cloning. If shared, put it into a register. 1479 return shared; 1480 } 1481 1482 1483 //------------------------------Instruction Selection-------------------------- 1484 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1485 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1486 // things the Matcher does not match (e.g., Memory), and things with different 1487 // Controls (hence forced into different blocks). We pass in the Control 1488 // selected for this entire State tree. 1489 1490 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1491 // Store and the Load must have identical Memories (as well as identical 1492 // pointers). Since the Matcher does not have anything for Memory (and 1493 // does not handle DAGs), I have to match the Memory input myself. If the 1494 // Tree root is a Store, I require all Loads to have the identical memory. 1495 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1496 // Since Label_Root is a recursive function, its possible that we might run 1497 // out of stack space. See bugs 6272980 & 6227033 for more info. 1498 LabelRootDepth++; 1499 if (LabelRootDepth > MaxLabelRootDepth) { 1500 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1501 return NULL; 1502 } 1503 uint care = 0; // Edges matcher cares about 1504 uint cnt = n->req(); 1505 uint i = 0; 1506 1507 // Examine children for memory state 1508 // Can only subsume a child into your match-tree if that child's memory state 1509 // is not modified along the path to another input. 1510 // It is unsafe even if the other inputs are separate roots. 1511 Node *input_mem = NULL; 1512 for( i = 1; i < cnt; i++ ) { 1513 if( !n->match_edge(i) ) continue; 1514 Node *m = n->in(i); // Get ith input 1515 assert( m, "expect non-null children" ); 1516 if( m->is_Load() ) { 1517 if( input_mem == NULL ) { 1518 input_mem = m->in(MemNode::Memory); 1519 } else if( input_mem != m->in(MemNode::Memory) ) { 1520 input_mem = NodeSentinel; 1521 } 1522 } 1523 } 1524 1525 for( i = 1; i < cnt; i++ ){// For my children 1526 if( !n->match_edge(i) ) continue; 1527 Node *m = n->in(i); // Get ith input 1528 // Allocate states out of a private arena 1529 State *s = new (&_states_arena) State; 1530 svec->_kids[care++] = s; 1531 assert( care <= 2, "binary only for now" ); 1532 1533 // Recursively label the State tree. 1534 s->_kids[0] = NULL; 1535 s->_kids[1] = NULL; 1536 s->_leaf = m; 1537 1538 // Check for leaves of the State Tree; things that cannot be a part of 1539 // the current tree. If it finds any, that value is matched as a 1540 // register operand. If not, then the normal matching is used. 1541 if( match_into_reg(n, m, control, i, is_shared(m)) || 1542 // 1543 // Stop recursion if this is LoadNode and the root of this tree is a 1544 // StoreNode and the load & store have different memories. 1545 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1546 // Can NOT include the match of a subtree when its memory state 1547 // is used by any of the other subtrees 1548 (input_mem == NodeSentinel) ) { 1549 // Print when we exclude matching due to different memory states at input-loads 1550 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1551 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1552 tty->print_cr("invalid input_mem"); 1553 } 1554 // Switch to a register-only opcode; this value must be in a register 1555 // and cannot be subsumed as part of a larger instruction. 1556 s->DFA( m->ideal_reg(), m ); 1557 1558 } else { 1559 // If match tree has no control and we do, adopt it for entire tree 1560 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1561 control = m->in(0); // Pick up control 1562 // Else match as a normal part of the match tree. 1563 control = Label_Root(m,s,control,mem); 1564 if (C->failing()) return NULL; 1565 } 1566 } 1567 1568 1569 // Call DFA to match this node, and return 1570 svec->DFA( n->Opcode(), n ); 1571 1572 #ifdef ASSERT 1573 uint x; 1574 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1575 if( svec->valid(x) ) 1576 break; 1577 1578 if (x >= _LAST_MACH_OPER) { 1579 n->dump(); 1580 svec->dump(); 1581 assert( false, "bad AD file" ); 1582 } 1583 #endif 1584 return control; 1585 } 1586 1587 1588 // Con nodes reduced using the same rule can share their MachNode 1589 // which reduces the number of copies of a constant in the final 1590 // program. The register allocator is free to split uses later to 1591 // split live ranges. 1592 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1593 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1594 1595 // See if this Con has already been reduced using this rule. 1596 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1597 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1598 if (last != NULL && rule == last->rule()) { 1599 // Don't expect control change for DecodeN 1600 if (leaf->is_DecodeNarrowPtr()) 1601 return last; 1602 // Get the new space root. 1603 Node* xroot = new_node(C->root()); 1604 if (xroot == NULL) { 1605 // This shouldn't happen give the order of matching. 1606 return NULL; 1607 } 1608 1609 // Shared constants need to have their control be root so they 1610 // can be scheduled properly. 1611 Node* control = last->in(0); 1612 if (control != xroot) { 1613 if (control == NULL || control == C->root()) { 1614 last->set_req(0, xroot); 1615 } else { 1616 assert(false, "unexpected control"); 1617 return NULL; 1618 } 1619 } 1620 return last; 1621 } 1622 return NULL; 1623 } 1624 1625 1626 //------------------------------ReduceInst------------------------------------- 1627 // Reduce a State tree (with given Control) into a tree of MachNodes. 1628 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1629 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1630 // Each MachNode has a number of complicated MachOper operands; each 1631 // MachOper also covers a further tree of Ideal Nodes. 1632 1633 // The root of the Ideal match tree is always an instruction, so we enter 1634 // the recursion here. After building the MachNode, we need to recurse 1635 // the tree checking for these cases: 1636 // (1) Child is an instruction - 1637 // Build the instruction (recursively), add it as an edge. 1638 // Build a simple operand (register) to hold the result of the instruction. 1639 // (2) Child is an interior part of an instruction - 1640 // Skip over it (do nothing) 1641 // (3) Child is the start of a operand - 1642 // Build the operand, place it inside the instruction 1643 // Call ReduceOper. 1644 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1645 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1646 1647 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1648 if (shared_node != NULL) { 1649 return shared_node; 1650 } 1651 1652 // Build the object to represent this state & prepare for recursive calls 1653 MachNode *mach = s->MachNodeGenerator(rule); 1654 guarantee(mach != NULL, "Missing MachNode"); 1655 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1656 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1657 Node *leaf = s->_leaf; 1658 // Check for instruction or instruction chain rule 1659 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1660 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1661 "duplicating node that's already been matched"); 1662 // Instruction 1663 mach->add_req( leaf->in(0) ); // Set initial control 1664 // Reduce interior of complex instruction 1665 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1666 } else { 1667 // Instruction chain rules are data-dependent on their inputs 1668 mach->add_req(0); // Set initial control to none 1669 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1670 } 1671 1672 // If a Memory was used, insert a Memory edge 1673 if( mem != (Node*)1 ) { 1674 mach->ins_req(MemNode::Memory,mem); 1675 #ifdef ASSERT 1676 // Verify adr type after matching memory operation 1677 const MachOper* oper = mach->memory_operand(); 1678 if (oper != NULL && oper != (MachOper*)-1) { 1679 // It has a unique memory operand. Find corresponding ideal mem node. 1680 Node* m = NULL; 1681 if (leaf->is_Mem()) { 1682 m = leaf; 1683 } else { 1684 m = _mem_node; 1685 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1686 } 1687 const Type* mach_at = mach->adr_type(); 1688 // DecodeN node consumed by an address may have different type 1689 // than its input. Don't compare types for such case. 1690 if (m->adr_type() != mach_at && 1691 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1692 (m->in(MemNode::Address)->is_AddP() && 1693 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) || 1694 (m->in(MemNode::Address)->is_AddP() && 1695 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1696 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) { 1697 mach_at = m->adr_type(); 1698 } 1699 if (m->adr_type() != mach_at) { 1700 m->dump(); 1701 tty->print_cr("mach:"); 1702 mach->dump(1); 1703 } 1704 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1705 } 1706 #endif 1707 } 1708 1709 // If the _leaf is an AddP, insert the base edge 1710 if (leaf->is_AddP()) { 1711 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1712 } 1713 1714 uint number_of_projections_prior = number_of_projections(); 1715 1716 // Perform any 1-to-many expansions required 1717 MachNode *ex = mach->Expand(s, _projection_list, mem); 1718 if (ex != mach) { 1719 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1720 if( ex->in(1)->is_Con() ) 1721 ex->in(1)->set_req(0, C->root()); 1722 // Remove old node from the graph 1723 for( uint i=0; i<mach->req(); i++ ) { 1724 mach->set_req(i,NULL); 1725 } 1726 #ifdef ASSERT 1727 _new2old_map.map(ex->_idx, s->_leaf); 1728 #endif 1729 } 1730 1731 // PhaseChaitin::fixup_spills will sometimes generate spill code 1732 // via the matcher. By the time, nodes have been wired into the CFG, 1733 // and any further nodes generated by expand rules will be left hanging 1734 // in space, and will not get emitted as output code. Catch this. 1735 // Also, catch any new register allocation constraints ("projections") 1736 // generated belatedly during spill code generation. 1737 if (_allocation_started) { 1738 guarantee(ex == mach, "no expand rules during spill generation"); 1739 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1740 } 1741 1742 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1743 // Record the con for sharing 1744 _shared_nodes.map(leaf->_idx, ex); 1745 } 1746 1747 return ex; 1748 } 1749 1750 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1751 for (uint i = n->req(); i < n->len(); i++) { 1752 if (n->in(i) != NULL) { 1753 mach->add_prec(n->in(i)); 1754 } 1755 } 1756 } 1757 1758 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1759 // 'op' is what I am expecting to receive 1760 int op = _leftOp[rule]; 1761 // Operand type to catch childs result 1762 // This is what my child will give me. 1763 int opnd_class_instance = s->_rule[op]; 1764 // Choose between operand class or not. 1765 // This is what I will receive. 1766 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1767 // New rule for child. Chase operand classes to get the actual rule. 1768 int newrule = s->_rule[catch_op]; 1769 1770 if( newrule < NUM_OPERANDS ) { 1771 // Chain from operand or operand class, may be output of shared node 1772 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1773 "Bad AD file: Instruction chain rule must chain from operand"); 1774 // Insert operand into array of operands for this instruction 1775 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1776 1777 ReduceOper( s, newrule, mem, mach ); 1778 } else { 1779 // Chain from the result of an instruction 1780 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1781 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1782 Node *mem1 = (Node*)1; 1783 debug_only(Node *save_mem_node = _mem_node;) 1784 mach->add_req( ReduceInst(s, newrule, mem1) ); 1785 debug_only(_mem_node = save_mem_node;) 1786 } 1787 return; 1788 } 1789 1790 1791 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1792 handle_precedence_edges(s->_leaf, mach); 1793 1794 if( s->_leaf->is_Load() ) { 1795 Node *mem2 = s->_leaf->in(MemNode::Memory); 1796 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1797 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1798 mem = mem2; 1799 } 1800 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1801 if( mach->in(0) == NULL ) 1802 mach->set_req(0, s->_leaf->in(0)); 1803 } 1804 1805 // Now recursively walk the state tree & add operand list. 1806 for( uint i=0; i<2; i++ ) { // binary tree 1807 State *newstate = s->_kids[i]; 1808 if( newstate == NULL ) break; // Might only have 1 child 1809 // 'op' is what I am expecting to receive 1810 int op; 1811 if( i == 0 ) { 1812 op = _leftOp[rule]; 1813 } else { 1814 op = _rightOp[rule]; 1815 } 1816 // Operand type to catch childs result 1817 // This is what my child will give me. 1818 int opnd_class_instance = newstate->_rule[op]; 1819 // Choose between operand class or not. 1820 // This is what I will receive. 1821 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1822 // New rule for child. Chase operand classes to get the actual rule. 1823 int newrule = newstate->_rule[catch_op]; 1824 1825 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1826 // Operand/operandClass 1827 // Insert operand into array of operands for this instruction 1828 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 1829 ReduceOper( newstate, newrule, mem, mach ); 1830 1831 } else { // Child is internal operand or new instruction 1832 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1833 // internal operand --> call ReduceInst_Interior 1834 // Interior of complex instruction. Do nothing but recurse. 1835 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1836 } else { 1837 // instruction --> call build operand( ) to catch result 1838 // --> ReduceInst( newrule ) 1839 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 1840 Node *mem1 = (Node*)1; 1841 debug_only(Node *save_mem_node = _mem_node;) 1842 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1843 debug_only(_mem_node = save_mem_node;) 1844 } 1845 } 1846 assert( mach->_opnds[num_opnds-1], "" ); 1847 } 1848 return num_opnds; 1849 } 1850 1851 // This routine walks the interior of possible complex operands. 1852 // At each point we check our children in the match tree: 1853 // (1) No children - 1854 // We are a leaf; add _leaf field as an input to the MachNode 1855 // (2) Child is an internal operand - 1856 // Skip over it ( do nothing ) 1857 // (3) Child is an instruction - 1858 // Call ReduceInst recursively and 1859 // and instruction as an input to the MachNode 1860 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1861 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1862 State *kid = s->_kids[0]; 1863 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1864 1865 // Leaf? And not subsumed? 1866 if( kid == NULL && !_swallowed[rule] ) { 1867 mach->add_req( s->_leaf ); // Add leaf pointer 1868 return; // Bail out 1869 } 1870 1871 if( s->_leaf->is_Load() ) { 1872 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1873 mem = s->_leaf->in(MemNode::Memory); 1874 debug_only(_mem_node = s->_leaf;) 1875 } 1876 1877 handle_precedence_edges(s->_leaf, mach); 1878 1879 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1880 if( !mach->in(0) ) 1881 mach->set_req(0,s->_leaf->in(0)); 1882 else { 1883 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1884 } 1885 } 1886 1887 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1888 int newrule; 1889 if( i == 0) 1890 newrule = kid->_rule[_leftOp[rule]]; 1891 else 1892 newrule = kid->_rule[_rightOp[rule]]; 1893 1894 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1895 // Internal operand; recurse but do nothing else 1896 ReduceOper( kid, newrule, mem, mach ); 1897 1898 } else { // Child is a new instruction 1899 // Reduce the instruction, and add a direct pointer from this 1900 // machine instruction to the newly reduced one. 1901 Node *mem1 = (Node*)1; 1902 debug_only(Node *save_mem_node = _mem_node;) 1903 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1904 debug_only(_mem_node = save_mem_node;) 1905 } 1906 } 1907 } 1908 1909 1910 // ------------------------------------------------------------------------- 1911 // Java-Java calling convention 1912 // (what you use when Java calls Java) 1913 1914 //------------------------------find_receiver---------------------------------- 1915 // For a given signature, return the OptoReg for parameter 0. 1916 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1917 VMRegPair regs; 1918 BasicType sig_bt = T_OBJECT; 1919 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1920 // Return argument 0 register. In the LP64 build pointers 1921 // take 2 registers, but the VM wants only the 'main' name. 1922 return OptoReg::as_OptoReg(regs.first()); 1923 } 1924 1925 // This function identifies sub-graphs in which a 'load' node is 1926 // input to two different nodes, and such that it can be matched 1927 // with BMI instructions like blsi, blsr, etc. 1928 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32. 1929 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL* 1930 // refers to the same node. 1931 #ifdef X86 1932 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop) 1933 // This is a temporary solution until we make DAGs expressible in ADL. 1934 template<typename ConType> 1935 class FusedPatternMatcher { 1936 Node* _op1_node; 1937 Node* _mop_node; 1938 int _con_op; 1939 1940 static int match_next(Node* n, int next_op, int next_op_idx) { 1941 if (n->in(1) == NULL || n->in(2) == NULL) { 1942 return -1; 1943 } 1944 1945 if (next_op_idx == -1) { // n is commutative, try rotations 1946 if (n->in(1)->Opcode() == next_op) { 1947 return 1; 1948 } else if (n->in(2)->Opcode() == next_op) { 1949 return 2; 1950 } 1951 } else { 1952 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index"); 1953 if (n->in(next_op_idx)->Opcode() == next_op) { 1954 return next_op_idx; 1955 } 1956 } 1957 return -1; 1958 } 1959 public: 1960 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) : 1961 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { } 1962 1963 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative 1964 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative 1965 typename ConType::NativeType con_value) { 1966 if (_op1_node->Opcode() != op1) { 1967 return false; 1968 } 1969 if (_mop_node->outcnt() > 2) { 1970 return false; 1971 } 1972 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx); 1973 if (op1_op2_idx == -1) { 1974 return false; 1975 } 1976 // Memory operation must be the other edge 1977 int op1_mop_idx = (op1_op2_idx & 1) + 1; 1978 1979 // Check that the mop node is really what we want 1980 if (_op1_node->in(op1_mop_idx) == _mop_node) { 1981 Node *op2_node = _op1_node->in(op1_op2_idx); 1982 if (op2_node->outcnt() > 1) { 1983 return false; 1984 } 1985 assert(op2_node->Opcode() == op2, "Should be"); 1986 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx); 1987 if (op2_con_idx == -1) { 1988 return false; 1989 } 1990 // Memory operation must be the other edge 1991 int op2_mop_idx = (op2_con_idx & 1) + 1; 1992 // Check that the memory operation is the same node 1993 if (op2_node->in(op2_mop_idx) == _mop_node) { 1994 // Now check the constant 1995 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type(); 1996 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) { 1997 return true; 1998 } 1999 } 2000 } 2001 return false; 2002 } 2003 }; 2004 2005 2006 bool Matcher::is_bmi_pattern(Node *n, Node *m) { 2007 if (n != NULL && m != NULL) { 2008 if (m->Opcode() == Op_LoadI) { 2009 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI); 2010 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) || 2011 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) || 2012 bmii.match(Op_XorI, -1, Op_AddI, -1, -1); 2013 } else if (m->Opcode() == Op_LoadL) { 2014 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL); 2015 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) || 2016 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) || 2017 bmil.match(Op_XorL, -1, Op_AddL, -1, -1); 2018 } 2019 } 2020 return false; 2021 } 2022 #endif // X86 2023 2024 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2025 Node *off = m->in(AddPNode::Offset); 2026 if (off->is_Con()) { 2027 address_visited.test_set(m->_idx); // Flag as address_visited 2028 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2029 // Clone X+offset as it also folds into most addressing expressions 2030 mstack.push(off, Visit); 2031 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2032 return true; 2033 } 2034 return false; 2035 } 2036 2037 // A method-klass-holder may be passed in the inline_cache_reg 2038 // and then expanded into the inline_cache_reg and a method_oop register 2039 // defined in ad_<arch>.cpp 2040 2041 //------------------------------find_shared------------------------------------ 2042 // Set bits if Node is shared or otherwise a root 2043 void Matcher::find_shared( Node *n ) { 2044 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2045 MStack mstack(C->live_nodes() * 2); 2046 // Mark nodes as address_visited if they are inputs to an address expression 2047 VectorSet address_visited(Thread::current()->resource_area()); 2048 mstack.push(n, Visit); // Don't need to pre-visit root node 2049 while (mstack.is_nonempty()) { 2050 n = mstack.node(); // Leave node on stack 2051 Node_State nstate = mstack.state(); 2052 uint nop = n->Opcode(); 2053 if (nstate == Pre_Visit) { 2054 if (address_visited.test(n->_idx)) { // Visited in address already? 2055 // Flag as visited and shared now. 2056 set_visited(n); 2057 } 2058 if (is_visited(n)) { // Visited already? 2059 // Node is shared and has no reason to clone. Flag it as shared. 2060 // This causes it to match into a register for the sharing. 2061 set_shared(n); // Flag as shared and 2062 mstack.pop(); // remove node from stack 2063 continue; 2064 } 2065 nstate = Visit; // Not already visited; so visit now 2066 } 2067 if (nstate == Visit) { 2068 mstack.set_state(Post_Visit); 2069 set_visited(n); // Flag as visited now 2070 bool mem_op = false; 2071 int mem_addr_idx = MemNode::Address; 2072 2073 switch( nop ) { // Handle some opcodes special 2074 case Op_Phi: // Treat Phis as shared roots 2075 case Op_Parm: 2076 case Op_Proj: // All handled specially during matching 2077 case Op_SafePointScalarObject: 2078 set_shared(n); 2079 set_dontcare(n); 2080 break; 2081 case Op_If: 2082 case Op_CountedLoopEnd: 2083 mstack.set_state(Alt_Post_Visit); // Alternative way 2084 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2085 // with matching cmp/branch in 1 instruction. The Matcher needs the 2086 // Bool and CmpX side-by-side, because it can only get at constants 2087 // that are at the leaves of Match trees, and the Bool's condition acts 2088 // as a constant here. 2089 mstack.push(n->in(1), Visit); // Clone the Bool 2090 mstack.push(n->in(0), Pre_Visit); // Visit control input 2091 continue; // while (mstack.is_nonempty()) 2092 case Op_ConvI2D: // These forms efficiently match with a prior 2093 case Op_ConvI2F: // Load but not a following Store 2094 if( n->in(1)->is_Load() && // Prior load 2095 n->outcnt() == 1 && // Not already shared 2096 n->unique_out()->is_Store() ) // Following store 2097 set_shared(n); // Force it to be a root 2098 break; 2099 case Op_ReverseBytesI: 2100 case Op_ReverseBytesL: 2101 if( n->in(1)->is_Load() && // Prior load 2102 n->outcnt() == 1 ) // Not already shared 2103 set_shared(n); // Force it to be a root 2104 break; 2105 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 2106 case Op_IfFalse: 2107 case Op_IfTrue: 2108 case Op_MachProj: 2109 case Op_MergeMem: 2110 case Op_Catch: 2111 case Op_CatchProj: 2112 case Op_CProj: 2113 case Op_JumpProj: 2114 case Op_JProj: 2115 case Op_NeverBranch: 2116 set_dontcare(n); 2117 break; 2118 case Op_Jump: 2119 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2120 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2121 continue; // while (mstack.is_nonempty()) 2122 case Op_StrComp: 2123 case Op_StrEquals: 2124 case Op_StrIndexOf: 2125 case Op_StrIndexOfChar: 2126 case Op_AryEq: 2127 case Op_HasNegatives: 2128 case Op_StrInflatedCopy: 2129 case Op_StrCompressedCopy: 2130 case Op_EncodeISOArray: 2131 case Op_FmaD: 2132 case Op_FmaF: 2133 case Op_FmaVD: 2134 case Op_FmaVF: 2135 set_shared(n); // Force result into register (it will be anyways) 2136 break; 2137 case Op_ConP: { // Convert pointers above the centerline to NUL 2138 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2139 const TypePtr* tp = tn->type()->is_ptr(); 2140 if (tp->_ptr == TypePtr::AnyNull) { 2141 tn->set_type(TypePtr::NULL_PTR); 2142 } 2143 break; 2144 } 2145 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2146 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2147 const TypePtr* tp = tn->type()->make_ptr(); 2148 if (tp && tp->_ptr == TypePtr::AnyNull) { 2149 tn->set_type(TypeNarrowOop::NULL_PTR); 2150 } 2151 break; 2152 } 2153 case Op_Binary: // These are introduced in the Post_Visit state. 2154 ShouldNotReachHere(); 2155 break; 2156 case Op_ClearArray: 2157 case Op_SafePoint: 2158 mem_op = true; 2159 break; 2160 #if INCLUDE_SHENANDOAHGC 2161 case Op_ShenandoahReadBarrier: 2162 if (n->in(ShenandoahBarrierNode::ValueIn)->is_DecodeNarrowPtr()) { 2163 set_shared(n->in(ShenandoahBarrierNode::ValueIn)->in(1)); 2164 } 2165 mem_op = true; 2166 set_shared(n); 2167 break; 2168 #endif 2169 #if INCLUDE_ZGC 2170 case Op_CallLeaf: 2171 if (UseZGC) { 2172 if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() || 2173 n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) { 2174 mem_op = true; 2175 mem_addr_idx = TypeFunc::Parms+1; 2176 } 2177 break; 2178 } 2179 #endif 2180 default: 2181 if( n->is_Store() ) { 2182 // Do match stores, despite no ideal reg 2183 mem_op = true; 2184 break; 2185 } 2186 if( n->is_Mem() ) { // Loads and LoadStores 2187 mem_op = true; 2188 // Loads must be root of match tree due to prior load conflict 2189 if( C->subsume_loads() == false ) 2190 set_shared(n); 2191 } 2192 // Fall into default case 2193 if( !n->ideal_reg() ) 2194 set_dontcare(n); // Unmatchable Nodes 2195 } // end_switch 2196 2197 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2198 Node *m = n->in(i); // Get ith input 2199 if (m == NULL) continue; // Ignore NULLs 2200 uint mop = m->Opcode(); 2201 2202 // Must clone all producers of flags, or we will not match correctly. 2203 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2204 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2205 // are also there, so we may match a float-branch to int-flags and 2206 // expect the allocator to haul the flags from the int-side to the 2207 // fp-side. No can do. 2208 if( _must_clone[mop] ) { 2209 mstack.push(m, Visit); 2210 continue; // for(int i = ...) 2211 } 2212 2213 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { 2214 // Bases used in addresses must be shared but since 2215 // they are shared through a DecodeN they may appear 2216 // to have a single use so force sharing here. 2217 set_shared(m->in(AddPNode::Base)->in(1)); 2218 } 2219 2220 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node. 2221 #ifdef X86 2222 if (UseBMI1Instructions && is_bmi_pattern(n, m)) { 2223 mstack.push(m, Visit); 2224 continue; 2225 } 2226 #endif 2227 2228 // Clone addressing expressions as they are "free" in memory access instructions 2229 if (mem_op && i == mem_addr_idx && mop == Op_AddP && 2230 // When there are other uses besides address expressions 2231 // put it on stack and mark as shared. 2232 !is_visited(m)) { 2233 // Some inputs for address expression are not put on stack 2234 // to avoid marking them as shared and forcing them into register 2235 // if they are used only in address expressions. 2236 // But they should be marked as shared if there are other uses 2237 // besides address expressions. 2238 2239 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2240 continue; 2241 } 2242 } // if( mem_op && 2243 mstack.push(m, Pre_Visit); 2244 } // for(int i = ...) 2245 } 2246 else if (nstate == Alt_Post_Visit) { 2247 mstack.pop(); // Remove node from stack 2248 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2249 // shared and all users of the Bool need to move the Cmp in parallel. 2250 // This leaves both the Bool and the If pointing at the Cmp. To 2251 // prevent the Matcher from trying to Match the Cmp along both paths 2252 // BoolNode::match_edge always returns a zero. 2253 2254 // We reorder the Op_If in a pre-order manner, so we can visit without 2255 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2256 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2257 } 2258 else if (nstate == Post_Visit) { 2259 mstack.pop(); // Remove node from stack 2260 2261 // Now hack a few special opcodes 2262 switch( n->Opcode() ) { // Handle some opcodes special 2263 case Op_StorePConditional: 2264 case Op_StoreIConditional: 2265 case Op_StoreLConditional: 2266 #if INCLUDE_SHENANDOAHGC 2267 case Op_ShenandoahCompareAndExchangeP: 2268 case Op_ShenandoahCompareAndExchangeN: 2269 case Op_ShenandoahWeakCompareAndSwapP: 2270 case Op_ShenandoahWeakCompareAndSwapN: 2271 case Op_ShenandoahCompareAndSwapP: 2272 case Op_ShenandoahCompareAndSwapN: 2273 #endif 2274 case Op_CompareAndExchangeB: 2275 case Op_CompareAndExchangeS: 2276 case Op_CompareAndExchangeI: 2277 case Op_CompareAndExchangeL: 2278 case Op_CompareAndExchangeP: 2279 case Op_CompareAndExchangeN: 2280 case Op_WeakCompareAndSwapB: 2281 case Op_WeakCompareAndSwapS: 2282 case Op_WeakCompareAndSwapI: 2283 case Op_WeakCompareAndSwapL: 2284 case Op_WeakCompareAndSwapP: 2285 case Op_WeakCompareAndSwapN: 2286 case Op_CompareAndSwapB: 2287 case Op_CompareAndSwapS: 2288 case Op_CompareAndSwapI: 2289 case Op_CompareAndSwapL: 2290 case Op_CompareAndSwapP: 2291 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2292 Node *newval = n->in(MemNode::ValueIn ); 2293 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2294 Node *pair = new BinaryNode( oldval, newval ); 2295 n->set_req(MemNode::ValueIn,pair); 2296 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2297 break; 2298 } 2299 case Op_CMoveD: // Convert trinary to binary-tree 2300 case Op_CMoveF: 2301 case Op_CMoveI: 2302 case Op_CMoveL: 2303 case Op_CMoveN: 2304 case Op_CMoveP: 2305 case Op_CMoveVF: 2306 case Op_CMoveVD: { 2307 // Restructure into a binary tree for Matching. It's possible that 2308 // we could move this code up next to the graph reshaping for IfNodes 2309 // or vice-versa, but I do not want to debug this for Ladybird. 2310 // 10/2/2000 CNC. 2311 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1)); 2312 n->set_req(1,pair1); 2313 Node *pair2 = new BinaryNode(n->in(2),n->in(3)); 2314 n->set_req(2,pair2); 2315 n->del_req(3); 2316 break; 2317 } 2318 case Op_LoopLimit: { 2319 Node *pair1 = new BinaryNode(n->in(1),n->in(2)); 2320 n->set_req(1,pair1); 2321 n->set_req(2,n->in(3)); 2322 n->del_req(3); 2323 break; 2324 } 2325 case Op_StrEquals: 2326 case Op_StrIndexOfChar: { 2327 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2328 n->set_req(2,pair1); 2329 n->set_req(3,n->in(4)); 2330 n->del_req(4); 2331 break; 2332 } 2333 case Op_StrComp: 2334 case Op_StrIndexOf: { 2335 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2336 n->set_req(2,pair1); 2337 Node *pair2 = new BinaryNode(n->in(4),n->in(5)); 2338 n->set_req(3,pair2); 2339 n->del_req(5); 2340 n->del_req(4); 2341 break; 2342 } 2343 case Op_StrCompressedCopy: 2344 case Op_StrInflatedCopy: 2345 case Op_EncodeISOArray: { 2346 // Restructure into a binary tree for Matching. 2347 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2348 n->set_req(3, pair); 2349 n->del_req(4); 2350 break; 2351 } 2352 case Op_FmaD: 2353 case Op_FmaF: 2354 case Op_FmaVD: 2355 case Op_FmaVF: { 2356 // Restructure into a binary tree for Matching. 2357 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2358 n->set_req(2, pair); 2359 n->set_req(1, n->in(3)); 2360 n->del_req(3); 2361 break; 2362 } 2363 default: 2364 break; 2365 } 2366 } 2367 else { 2368 ShouldNotReachHere(); 2369 } 2370 } // end of while (mstack.is_nonempty()) 2371 } 2372 2373 #ifdef ASSERT 2374 // machine-independent root to machine-dependent root 2375 void Matcher::dump_old2new_map() { 2376 _old2new_map.dump(); 2377 } 2378 #endif 2379 2380 //---------------------------collect_null_checks------------------------------- 2381 // Find null checks in the ideal graph; write a machine-specific node for 2382 // it. Used by later implicit-null-check handling. Actually collects 2383 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2384 // value being tested. 2385 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2386 Node *iff = proj->in(0); 2387 if( iff->Opcode() == Op_If ) { 2388 // During matching If's have Bool & Cmp side-by-side 2389 BoolNode *b = iff->in(1)->as_Bool(); 2390 Node *cmp = iff->in(2); 2391 int opc = cmp->Opcode(); 2392 if (opc != Op_CmpP && opc != Op_CmpN) return; 2393 2394 const Type* ct = cmp->in(2)->bottom_type(); 2395 if (ct == TypePtr::NULL_PTR || 2396 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2397 2398 bool push_it = false; 2399 if( proj->Opcode() == Op_IfTrue ) { 2400 #ifndef PRODUCT 2401 extern int all_null_checks_found; 2402 all_null_checks_found++; 2403 #endif 2404 if( b->_test._test == BoolTest::ne ) { 2405 push_it = true; 2406 } 2407 } else { 2408 assert( proj->Opcode() == Op_IfFalse, "" ); 2409 if( b->_test._test == BoolTest::eq ) { 2410 push_it = true; 2411 } 2412 } 2413 if( push_it ) { 2414 _null_check_tests.push(proj); 2415 Node* val = cmp->in(1); 2416 #ifdef _LP64 2417 if (val->bottom_type()->isa_narrowoop() && 2418 !Matcher::narrow_oop_use_complex_address()) { 2419 // 2420 // Look for DecodeN node which should be pinned to orig_proj. 2421 // On platforms (Sparc) which can not handle 2 adds 2422 // in addressing mode we have to keep a DecodeN node and 2423 // use it to do implicit NULL check in address. 2424 // 2425 // DecodeN node was pinned to non-null path (orig_proj) during 2426 // CastPP transformation in final_graph_reshaping_impl(). 2427 // 2428 uint cnt = orig_proj->outcnt(); 2429 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2430 Node* d = orig_proj->raw_out(i); 2431 if (d->is_DecodeN() && d->in(1) == val) { 2432 val = d; 2433 val->set_req(0, NULL); // Unpin now. 2434 // Mark this as special case to distinguish from 2435 // a regular case: CmpP(DecodeN, NULL). 2436 val = (Node*)(((intptr_t)val) | 1); 2437 break; 2438 } 2439 } 2440 } 2441 #endif 2442 _null_check_tests.push(val); 2443 } 2444 } 2445 } 2446 } 2447 2448 //---------------------------validate_null_checks------------------------------ 2449 // Its possible that the value being NULL checked is not the root of a match 2450 // tree. If so, I cannot use the value in an implicit null check. 2451 void Matcher::validate_null_checks( ) { 2452 uint cnt = _null_check_tests.size(); 2453 for( uint i=0; i < cnt; i+=2 ) { 2454 Node *test = _null_check_tests[i]; 2455 Node *val = _null_check_tests[i+1]; 2456 bool is_decoden = ((intptr_t)val) & 1; 2457 val = (Node*)(((intptr_t)val) & ~1); 2458 if (has_new_node(val)) { 2459 Node* new_val = new_node(val); 2460 if (is_decoden) { 2461 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2462 // Note: new_val may have a control edge if 2463 // the original ideal node DecodeN was matched before 2464 // it was unpinned in Matcher::collect_null_checks(). 2465 // Unpin the mach node and mark it. 2466 new_val->set_req(0, NULL); 2467 new_val = (Node*)(((intptr_t)new_val) | 1); 2468 } 2469 // Is a match-tree root, so replace with the matched value 2470 _null_check_tests.map(i+1, new_val); 2471 } else { 2472 // Yank from candidate list 2473 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2474 _null_check_tests.map(i,_null_check_tests[--cnt]); 2475 _null_check_tests.pop(); 2476 _null_check_tests.pop(); 2477 i-=2; 2478 } 2479 } 2480 } 2481 2482 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2483 // atomic instruction acting as a store_load barrier without any 2484 // intervening volatile load, and thus we don't need a barrier here. 2485 // We retain the Node to act as a compiler ordering barrier. 2486 bool Matcher::post_store_load_barrier(const Node* vmb) { 2487 Compile* C = Compile::current(); 2488 assert(vmb->is_MemBar(), ""); 2489 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2490 const MemBarNode* membar = vmb->as_MemBar(); 2491 2492 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2493 Node* ctrl = NULL; 2494 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2495 Node* p = membar->fast_out(i); 2496 assert(p->is_Proj(), "only projections here"); 2497 if ((p->as_Proj()->_con == TypeFunc::Control) && 2498 !C->node_arena()->contains(p)) { // Unmatched old-space only 2499 ctrl = p; 2500 break; 2501 } 2502 } 2503 assert((ctrl != NULL), "missing control projection"); 2504 2505 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2506 Node *x = ctrl->fast_out(j); 2507 int xop = x->Opcode(); 2508 2509 // We don't need current barrier if we see another or a lock 2510 // before seeing volatile load. 2511 // 2512 // Op_Fastunlock previously appeared in the Op_* list below. 2513 // With the advent of 1-0 lock operations we're no longer guaranteed 2514 // that a monitor exit operation contains a serializing instruction. 2515 2516 if (xop == Op_MemBarVolatile || 2517 #if INCLUDE_SHENANDOAHGC 2518 xop == Op_ShenandoahCompareAndExchangeP || 2519 xop == Op_ShenandoahCompareAndExchangeN || 2520 xop == Op_ShenandoahWeakCompareAndSwapP || 2521 xop == Op_ShenandoahWeakCompareAndSwapN || 2522 xop == Op_ShenandoahCompareAndSwapN || 2523 xop == Op_ShenandoahCompareAndSwapP || 2524 #endif 2525 xop == Op_CompareAndExchangeB || 2526 xop == Op_CompareAndExchangeS || 2527 xop == Op_CompareAndExchangeI || 2528 xop == Op_CompareAndExchangeL || 2529 xop == Op_CompareAndExchangeP || 2530 xop == Op_CompareAndExchangeN || 2531 xop == Op_WeakCompareAndSwapB || 2532 xop == Op_WeakCompareAndSwapS || 2533 xop == Op_WeakCompareAndSwapL || 2534 xop == Op_WeakCompareAndSwapP || 2535 xop == Op_WeakCompareAndSwapN || 2536 xop == Op_WeakCompareAndSwapI || 2537 xop == Op_CompareAndSwapB || 2538 xop == Op_CompareAndSwapS || 2539 xop == Op_CompareAndSwapL || 2540 xop == Op_CompareAndSwapP || 2541 xop == Op_CompareAndSwapN || 2542 xop == Op_CompareAndSwapI) { 2543 return true; 2544 } 2545 2546 // Op_FastLock previously appeared in the Op_* list above. 2547 // With biased locking we're no longer guaranteed that a monitor 2548 // enter operation contains a serializing instruction. 2549 if ((xop == Op_FastLock) && !UseBiasedLocking) { 2550 return true; 2551 } 2552 2553 if (x->is_MemBar()) { 2554 // We must retain this membar if there is an upcoming volatile 2555 // load, which will be followed by acquire membar. 2556 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2557 return false; 2558 } else { 2559 // For other kinds of barriers, check by pretending we 2560 // are them, and seeing if we can be removed. 2561 return post_store_load_barrier(x->as_MemBar()); 2562 } 2563 } 2564 2565 // probably not necessary to check for these 2566 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2567 return false; 2568 } 2569 } 2570 return false; 2571 } 2572 2573 // Check whether node n is a branch to an uncommon trap that we could 2574 // optimize as test with very high branch costs in case of going to 2575 // the uncommon trap. The code must be able to be recompiled to use 2576 // a cheaper test. 2577 bool Matcher::branches_to_uncommon_trap(const Node *n) { 2578 // Don't do it for natives, adapters, or runtime stubs 2579 Compile *C = Compile::current(); 2580 if (!C->is_method_compilation()) return false; 2581 2582 assert(n->is_If(), "You should only call this on if nodes."); 2583 IfNode *ifn = n->as_If(); 2584 2585 Node *ifFalse = NULL; 2586 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2587 if (ifn->fast_out(i)->is_IfFalse()) { 2588 ifFalse = ifn->fast_out(i); 2589 break; 2590 } 2591 } 2592 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2593 2594 Node *reg = ifFalse; 2595 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2596 // Alternatively use visited set? Seems too expensive. 2597 while (reg != NULL && cnt > 0) { 2598 CallNode *call = NULL; 2599 RegionNode *nxt_reg = NULL; 2600 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2601 Node *o = reg->fast_out(i); 2602 if (o->is_Call()) { 2603 call = o->as_Call(); 2604 } 2605 if (o->is_Region()) { 2606 nxt_reg = o->as_Region(); 2607 } 2608 } 2609 2610 if (call && 2611 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2612 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2613 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2614 jint tr_con = trtype->is_int()->get_con(); 2615 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2616 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2617 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2618 2619 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 2620 && action != Deoptimization::Action_none) { 2621 // This uncommon trap is sure to recompile, eventually. 2622 // When that happens, C->too_many_traps will prevent 2623 // this transformation from happening again. 2624 return true; 2625 } 2626 } 2627 } 2628 2629 reg = nxt_reg; 2630 cnt--; 2631 } 2632 2633 return false; 2634 } 2635 2636 //============================================================================= 2637 //---------------------------State--------------------------------------------- 2638 State::State(void) { 2639 #ifdef ASSERT 2640 _id = 0; 2641 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2642 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2643 //memset(_cost, -1, sizeof(_cost)); 2644 //memset(_rule, -1, sizeof(_rule)); 2645 #endif 2646 memset(_valid, 0, sizeof(_valid)); 2647 } 2648 2649 #ifdef ASSERT 2650 State::~State() { 2651 _id = 99; 2652 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2653 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2654 memset(_cost, -3, sizeof(_cost)); 2655 memset(_rule, -3, sizeof(_rule)); 2656 } 2657 #endif 2658 2659 #ifndef PRODUCT 2660 //---------------------------dump---------------------------------------------- 2661 void State::dump() { 2662 tty->print("\n"); 2663 dump(0); 2664 } 2665 2666 void State::dump(int depth) { 2667 for( int j = 0; j < depth; j++ ) 2668 tty->print(" "); 2669 tty->print("--N: "); 2670 _leaf->dump(); 2671 uint i; 2672 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2673 // Check for valid entry 2674 if( valid(i) ) { 2675 for( int j = 0; j < depth; j++ ) 2676 tty->print(" "); 2677 assert(_cost[i] != max_juint, "cost must be a valid value"); 2678 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2679 tty->print_cr("%s %d %s", 2680 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2681 } 2682 tty->cr(); 2683 2684 for( i=0; i<2; i++ ) 2685 if( _kids[i] ) 2686 _kids[i]->dump(depth+1); 2687 } 2688 #endif