1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #include "gc_implementation/shenandoah/shenandoahHeap.inline.hpp"
47 #include "gc_implementation/shenandoah/shenandoahHeapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49
50 #ifdef PRODUCT
51 #define BLOCK_COMMENT(str) /* nothing */
52 #define STOP(error) stop(error)
53 #else
54 #define BLOCK_COMMENT(str) block_comment(str)
55 #define STOP(error) block_comment(error); stop(error)
56 #endif
57
58 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
59
60 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
61
62 #ifdef ASSERT
63 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
64 #endif
65
66 static Assembler::Condition reverse[] = {
67 Assembler::noOverflow /* overflow = 0x0 */ ,
68 Assembler::overflow /* noOverflow = 0x1 */ ,
69 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
70 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
71 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
72 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
73 Assembler::above /* belowEqual = 0x6 */ ,
74 Assembler::belowEqual /* above = 0x7 */ ,
75 Assembler::positive /* negative = 0x8 */ ,
76 Assembler::negative /* positive = 0x9 */ ,
77 Assembler::noParity /* parity = 0xa */ ,
78 Assembler::parity /* noParity = 0xb */ ,
79 Assembler::greaterEqual /* less = 0xc */ ,
80 Assembler::less /* greaterEqual = 0xd */ ,
81 Assembler::greater /* lessEqual = 0xe */ ,
82 Assembler::lessEqual /* greater = 0xf, */
83
84 };
85
86
87 // Implementation of MacroAssembler
88
89 // First all the versions that have distinct versions depending on 32/64 bit
90 // Unless the difference is trivial (1 line or so).
91
92 #ifndef _LP64
93
94 // 32bit versions
95
96 Address MacroAssembler::as_Address(AddressLiteral adr) {
97 return Address(adr.target(), adr.rspec());
98 }
99
100 Address MacroAssembler::as_Address(ArrayAddress adr) {
101 return Address::make_array(adr);
102 }
103
104 void MacroAssembler::call_VM_leaf_base(address entry_point,
105 int number_of_arguments) {
106 call(RuntimeAddress(entry_point));
107 increment(rsp, number_of_arguments * wordSize);
108 }
109
110 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
111 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
112 }
113
114 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118 void MacroAssembler::cmpoop(Address src1, jobject obj) {
119 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
120 }
121
122 void MacroAssembler::cmpoop(Register src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
126 void MacroAssembler::extend_sign(Register hi, Register lo) {
127 // According to Intel Doc. AP-526, "Integer Divide", p.18.
128 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
129 cdql();
130 } else {
131 movl(hi, lo);
132 sarl(hi, 31);
133 }
134 }
135
136 void MacroAssembler::jC2(Register tmp, Label& L) {
137 // set parity bit if FPU flag C2 is set (via rax)
138 save_rax(tmp);
139 fwait(); fnstsw_ax();
140 sahf();
141 restore_rax(tmp);
142 // branch
143 jcc(Assembler::parity, L);
144 }
145
146 void MacroAssembler::jnC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::noParity, L);
154 }
155
156 // 32bit can do a case table jump in one instruction but we no longer allow the base
157 // to be installed in the Address class
158 void MacroAssembler::jump(ArrayAddress entry) {
159 jmp(as_Address(entry));
160 }
161
162 // Note: y_lo will be destroyed
163 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
164 // Long compare for Java (semantics as described in JVM spec.)
165 Label high, low, done;
166
167 cmpl(x_hi, y_hi);
168 jcc(Assembler::less, low);
169 jcc(Assembler::greater, high);
170 // x_hi is the return register
171 xorl(x_hi, x_hi);
172 cmpl(x_lo, y_lo);
173 jcc(Assembler::below, low);
174 jcc(Assembler::equal, done);
175
176 bind(high);
177 xorl(x_hi, x_hi);
178 increment(x_hi);
179 jmp(done);
180
181 bind(low);
182 xorl(x_hi, x_hi);
183 decrementl(x_hi);
184
185 bind(done);
186 }
187
188 void MacroAssembler::lea(Register dst, AddressLiteral src) {
189 mov_literal32(dst, (int32_t)src.target(), src.rspec());
190 }
191
192 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
193 // leal(dst, as_Address(adr));
194 // see note in movl as to why we must use a move
195 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
196 }
197
198 void MacroAssembler::leave() {
199 mov(rsp, rbp);
200 pop(rbp);
201 }
202
203 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
204 // Multiplication of two Java long values stored on the stack
205 // as illustrated below. Result is in rdx:rax.
206 //
207 // rsp ---> [ ?? ] \ \
208 // .... | y_rsp_offset |
209 // [ y_lo ] / (in bytes) | x_rsp_offset
210 // [ y_hi ] | (in bytes)
211 // .... |
212 // [ x_lo ] /
213 // [ x_hi ]
214 // ....
215 //
216 // Basic idea: lo(result) = lo(x_lo * y_lo)
217 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
218 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
219 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
220 Label quick;
221 // load x_hi, y_hi and check if quick
222 // multiplication is possible
223 movl(rbx, x_hi);
224 movl(rcx, y_hi);
225 movl(rax, rbx);
226 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
227 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
228 // do full multiplication
229 // 1st step
230 mull(y_lo); // x_hi * y_lo
231 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
232 // 2nd step
233 movl(rax, x_lo);
234 mull(rcx); // x_lo * y_hi
235 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
236 // 3rd step
237 bind(quick); // note: rbx, = 0 if quick multiply!
238 movl(rax, x_lo);
239 mull(y_lo); // x_lo * y_lo
240 addl(rdx, rbx); // correct hi(x_lo * y_lo)
241 }
242
243 void MacroAssembler::lneg(Register hi, Register lo) {
244 negl(lo);
245 adcl(hi, 0);
246 negl(hi);
247 }
248
249 void MacroAssembler::lshl(Register hi, Register lo) {
250 // Java shift left long support (semantics as described in JVM spec., p.305)
251 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
252 // shift value is in rcx !
253 assert(hi != rcx, "must not use rcx");
254 assert(lo != rcx, "must not use rcx");
255 const Register s = rcx; // shift count
256 const int n = BitsPerWord;
257 Label L;
258 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
259 cmpl(s, n); // if (s < n)
260 jcc(Assembler::less, L); // else (s >= n)
261 movl(hi, lo); // x := x << n
262 xorl(lo, lo);
263 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
264 bind(L); // s (mod n) < n
265 shldl(hi, lo); // x := x << s
266 shll(lo);
267 }
268
269
270 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
271 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
272 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
273 assert(hi != rcx, "must not use rcx");
274 assert(lo != rcx, "must not use rcx");
275 const Register s = rcx; // shift count
276 const int n = BitsPerWord;
277 Label L;
278 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
279 cmpl(s, n); // if (s < n)
280 jcc(Assembler::less, L); // else (s >= n)
281 movl(lo, hi); // x := x >> n
282 if (sign_extension) sarl(hi, 31);
283 else xorl(hi, hi);
284 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
285 bind(L); // s (mod n) < n
286 shrdl(lo, hi); // x := x >> s
287 if (sign_extension) sarl(hi);
288 else shrl(hi);
289 }
290
291 void MacroAssembler::movoop(Register dst, jobject obj) {
292 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
293 }
294
295 void MacroAssembler::movoop(Address dst, jobject obj) {
296 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
297 }
298
299 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
300 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
301 }
302
303 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
304 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
305 }
306
307 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
308 // scratch register is not used,
309 // it is defined to match parameters of 64-bit version of this method.
310 if (src.is_lval()) {
311 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
312 } else {
313 movl(dst, as_Address(src));
314 }
315 }
316
317 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
318 movl(as_Address(dst), src);
319 }
320
321 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
322 movl(dst, as_Address(src));
323 }
324
325 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
326 void MacroAssembler::movptr(Address dst, intptr_t src) {
327 movl(dst, src);
328 }
329
330
331 void MacroAssembler::pop_callee_saved_registers() {
332 pop(rcx);
333 pop(rdx);
334 pop(rdi);
335 pop(rsi);
336 }
337
338 void MacroAssembler::pop_fTOS() {
339 fld_d(Address(rsp, 0));
340 addl(rsp, 2 * wordSize);
341 }
342
343 void MacroAssembler::push_callee_saved_registers() {
344 push(rsi);
345 push(rdi);
346 push(rdx);
347 push(rcx);
348 }
349
350 void MacroAssembler::push_fTOS() {
351 subl(rsp, 2 * wordSize);
352 fstp_d(Address(rsp, 0));
353 }
354
355
356 void MacroAssembler::pushoop(jobject obj) {
357 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
358 }
359
360 void MacroAssembler::pushklass(Metadata* obj) {
361 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
362 }
363
364 void MacroAssembler::pushptr(AddressLiteral src) {
365 if (src.is_lval()) {
366 push_literal32((int32_t)src.target(), src.rspec());
367 } else {
368 pushl(as_Address(src));
369 }
370 }
371
372 void MacroAssembler::set_word_if_not_zero(Register dst) {
373 xorl(dst, dst);
374 set_byte_if_not_zero(dst);
375 }
376
377 static void pass_arg0(MacroAssembler* masm, Register arg) {
378 masm->push(arg);
379 }
380
381 static void pass_arg1(MacroAssembler* masm, Register arg) {
382 masm->push(arg);
383 }
384
385 static void pass_arg2(MacroAssembler* masm, Register arg) {
386 masm->push(arg);
387 }
388
389 static void pass_arg3(MacroAssembler* masm, Register arg) {
390 masm->push(arg);
391 }
392
393 #ifndef PRODUCT
394 extern "C" void findpc(intptr_t x);
395 #endif
396
397 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
398 // In order to get locks to work, we need to fake a in_VM state
399 JavaThread* thread = JavaThread::current();
400 JavaThreadState saved_state = thread->thread_state();
401 thread->set_thread_state(_thread_in_vm);
402 if (ShowMessageBoxOnError) {
403 JavaThread* thread = JavaThread::current();
404 JavaThreadState saved_state = thread->thread_state();
405 thread->set_thread_state(_thread_in_vm);
406 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
407 ttyLocker ttyl;
408 BytecodeCounter::print();
409 }
410 // To see where a verify_oop failed, get $ebx+40/X for this frame.
411 // This is the value of eip which points to where verify_oop will return.
412 if (os::message_box(msg, "Execution stopped, print registers?")) {
413 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
414 BREAKPOINT;
415 }
416 } else {
417 ttyLocker ttyl;
418 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
419 }
420 // Don't assert holding the ttyLock
421 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
422 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
423 }
424
425 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
426 ttyLocker ttyl;
427 FlagSetting fs(Debugging, true);
428 tty->print_cr("eip = 0x%08x", eip);
429 #ifndef PRODUCT
430 if ((WizardMode || Verbose) && PrintMiscellaneous) {
431 tty->cr();
432 findpc(eip);
433 tty->cr();
434 }
435 #endif
436 #define PRINT_REG(rax) \
437 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
438 PRINT_REG(rax);
439 PRINT_REG(rbx);
440 PRINT_REG(rcx);
441 PRINT_REG(rdx);
442 PRINT_REG(rdi);
443 PRINT_REG(rsi);
444 PRINT_REG(rbp);
445 PRINT_REG(rsp);
446 #undef PRINT_REG
447 // Print some words near top of staack.
448 int* dump_sp = (int*) rsp;
449 for (int col1 = 0; col1 < 8; col1++) {
450 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
451 os::print_location(tty, *dump_sp++);
452 }
453 for (int row = 0; row < 16; row++) {
454 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
455 for (int col = 0; col < 8; col++) {
456 tty->print(" 0x%08x", *dump_sp++);
457 }
458 tty->cr();
459 }
460 // Print some instructions around pc:
461 Disassembler::decode((address)eip-64, (address)eip);
462 tty->print_cr("--------");
463 Disassembler::decode((address)eip, (address)eip+32);
464 }
465
466 void MacroAssembler::stop(const char* msg) {
467 ExternalAddress message((address)msg);
468 // push address of message
469 pushptr(message.addr());
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
473 hlt();
474 }
475
476 void MacroAssembler::warn(const char* msg) {
477 push_CPU_state();
478
479 ExternalAddress message((address) msg);
480 // push address of message
481 pushptr(message.addr());
482
483 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
484 addl(rsp, wordSize); // discard argument
485 pop_CPU_state();
486 }
487
488 void MacroAssembler::print_state() {
489 { Label L; call(L, relocInfo::none); bind(L); } // push eip
490 pusha(); // push registers
491
492 push_CPU_state();
493 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
494 pop_CPU_state();
495
496 popa();
497 addl(rsp, wordSize);
498 }
499
500 #else // _LP64
501
502 // 64 bit versions
503
504 Address MacroAssembler::as_Address(AddressLiteral adr) {
505 // amd64 always does this as a pc-rel
506 // we can be absolute or disp based on the instruction type
507 // jmp/call are displacements others are absolute
508 assert(!adr.is_lval(), "must be rval");
509 assert(reachable(adr), "must be");
510 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
511
512 }
513
514 Address MacroAssembler::as_Address(ArrayAddress adr) {
515 AddressLiteral base = adr.base();
516 lea(rscratch1, base);
517 Address index = adr.index();
518 assert(index._disp == 0, "must not have disp"); // maybe it can?
519 Address array(rscratch1, index._index, index._scale, index._disp);
520 return array;
521 }
522
523 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
524 Label L, E;
525
526 #ifdef _WIN64
527 // Windows always allocates space for it's register args
528 assert(num_args <= 4, "only register arguments supported");
529 subq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531
532 // Align stack if necessary
533 testl(rsp, 15);
534 jcc(Assembler::zero, L);
535
536 subq(rsp, 8);
537 {
538 call(RuntimeAddress(entry_point));
539 }
540 addq(rsp, 8);
541 jmp(E);
542
543 bind(L);
544 {
545 call(RuntimeAddress(entry_point));
546 }
547
548 bind(E);
549
550 #ifdef _WIN64
551 // restore stack pointer
552 addq(rsp, frame::arg_reg_save_area_bytes);
553 #endif
554
555 }
556
557 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
558 assert(!src2.is_lval(), "should use cmpptr");
559
560 if (reachable(src2)) {
561 cmpq(src1, as_Address(src2));
562 } else {
563 lea(rscratch1, src2);
564 Assembler::cmpq(src1, Address(rscratch1, 0));
565 }
566 }
567
568 int MacroAssembler::corrected_idivq(Register reg) {
569 // Full implementation of Java ldiv and lrem; checks for special
570 // case as described in JVM spec., p.243 & p.271. The function
571 // returns the (pc) offset of the idivl instruction - may be needed
572 // for implicit exceptions.
573 //
574 // normal case special case
575 //
576 // input : rax: dividend min_long
577 // reg: divisor (may not be eax/edx) -1
578 //
579 // output: rax: quotient (= rax idiv reg) min_long
580 // rdx: remainder (= rax irem reg) 0
581 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
582 static const int64_t min_long = 0x8000000000000000;
583 Label normal_case, special_case;
584
585 // check for special case
586 cmp64(rax, ExternalAddress((address) &min_long));
587 jcc(Assembler::notEqual, normal_case);
588 xorl(rdx, rdx); // prepare rdx for possible special case (where
589 // remainder = 0)
590 cmpq(reg, -1);
591 jcc(Assembler::equal, special_case);
592
593 // handle normal case
594 bind(normal_case);
595 cdqq();
596 int idivq_offset = offset();
597 idivq(reg);
598
599 // normal and special case exit
600 bind(special_case);
601
602 return idivq_offset;
603 }
604
605 void MacroAssembler::decrementq(Register reg, int value) {
606 if (value == min_jint) { subq(reg, value); return; }
607 if (value < 0) { incrementq(reg, -value); return; }
608 if (value == 0) { ; return; }
609 if (value == 1 && UseIncDec) { decq(reg) ; return; }
610 /* else */ { subq(reg, value) ; return; }
611 }
612
613 void MacroAssembler::decrementq(Address dst, int value) {
614 if (value == min_jint) { subq(dst, value); return; }
615 if (value < 0) { incrementq(dst, -value); return; }
616 if (value == 0) { ; return; }
617 if (value == 1 && UseIncDec) { decq(dst) ; return; }
618 /* else */ { subq(dst, value) ; return; }
619 }
620
621 void MacroAssembler::incrementq(AddressLiteral dst) {
622 if (reachable(dst)) {
623 incrementq(as_Address(dst));
624 } else {
625 lea(rscratch1, dst);
626 incrementq(Address(rscratch1, 0));
627 }
628 }
629
630 void MacroAssembler::incrementq(Register reg, int value) {
631 if (value == min_jint) { addq(reg, value); return; }
632 if (value < 0) { decrementq(reg, -value); return; }
633 if (value == 0) { ; return; }
634 if (value == 1 && UseIncDec) { incq(reg) ; return; }
635 /* else */ { addq(reg, value) ; return; }
636 }
637
638 void MacroAssembler::incrementq(Address dst, int value) {
639 if (value == min_jint) { addq(dst, value); return; }
640 if (value < 0) { decrementq(dst, -value); return; }
641 if (value == 0) { ; return; }
642 if (value == 1 && UseIncDec) { incq(dst) ; return; }
643 /* else */ { addq(dst, value) ; return; }
644 }
645
646 // 32bit can do a case table jump in one instruction but we no longer allow the base
647 // to be installed in the Address class
648 void MacroAssembler::jump(ArrayAddress entry) {
649 lea(rscratch1, entry.base());
650 Address dispatch = entry.index();
651 assert(dispatch._base == noreg, "must be");
652 dispatch._base = rscratch1;
653 jmp(dispatch);
654 }
655
656 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
657 ShouldNotReachHere(); // 64bit doesn't use two regs
658 cmpq(x_lo, y_lo);
659 }
660
661 void MacroAssembler::lea(Register dst, AddressLiteral src) {
662 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
663 }
664
665 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
666 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
667 movptr(dst, rscratch1);
668 }
669
670 void MacroAssembler::leave() {
671 // %%% is this really better? Why not on 32bit too?
672 emit_int8((unsigned char)0xC9); // LEAVE
673 }
674
675 void MacroAssembler::lneg(Register hi, Register lo) {
676 ShouldNotReachHere(); // 64bit doesn't use two regs
677 negq(lo);
678 }
679
680 void MacroAssembler::movoop(Register dst, jobject obj) {
681 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
682 }
683
684 void MacroAssembler::movoop(Address dst, jobject obj) {
685 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
686 movq(dst, rscratch1);
687 }
688
689 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
690 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
691 }
692
693 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
694 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
695 movq(dst, rscratch1);
696 }
697
698 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
699 if (src.is_lval()) {
700 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
701 } else {
702 if (reachable(src)) {
703 movq(dst, as_Address(src));
704 } else {
705 lea(scratch, src);
706 movq(dst, Address(scratch, 0));
707 }
708 }
709 }
710
711 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
712 movq(as_Address(dst), src);
713 }
714
715 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
716 movq(dst, as_Address(src));
717 }
718
719 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
720 void MacroAssembler::movptr(Address dst, intptr_t src) {
721 mov64(rscratch1, src);
722 movq(dst, rscratch1);
723 }
724
725 // These are mostly for initializing NULL
726 void MacroAssembler::movptr(Address dst, int32_t src) {
727 movslq(dst, src);
728 }
729
730 void MacroAssembler::movptr(Register dst, int32_t src) {
731 mov64(dst, (intptr_t)src);
732 }
733
734 void MacroAssembler::pushoop(jobject obj) {
735 movoop(rscratch1, obj);
736 push(rscratch1);
737 }
738
739 void MacroAssembler::pushklass(Metadata* obj) {
740 mov_metadata(rscratch1, obj);
741 push(rscratch1);
742 }
743
744 void MacroAssembler::pushptr(AddressLiteral src) {
745 lea(rscratch1, src);
746 if (src.is_lval()) {
747 push(rscratch1);
748 } else {
749 pushq(Address(rscratch1, 0));
750 }
751 }
752
753 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
754 // we must set sp to zero to clear frame
755 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
756 // must clear fp, so that compiled frames are not confused; it is
757 // possible that we need it only for debugging
758 if (clear_fp) {
759 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
760 }
761
762 // Always clear the pc because it could have been set by make_walkable()
763 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
764 }
765
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
773
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
779
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
787
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
790
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
796
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
802
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
808
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
814
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
825
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
837
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
845
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
849
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
855
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
859
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
888
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
936
937 #endif // _LP64
938
939 // Now versions that are common to 32/64 bit
940
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
944
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
948
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
961
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
970
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
976
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
998
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1002
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1008
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1017
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1024
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1034
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1048
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1061
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1073 bool need_tmp_reg = false;
1074 if (tmp_reg == noreg) {
1075 need_tmp_reg = true;
1076 tmp_reg = lock_reg;
1077 assert_different_registers(lock_reg, obj_reg, swap_reg);
1078 } else {
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 }
1081 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1082 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1083 Address saved_mark_addr(lock_reg, 0);
1084
1085 if (PrintBiasedLockingStatistics && counters == NULL) {
1086 counters = BiasedLocking::counters();
1087 }
1088 // Biased locking
1089 // See whether the lock is currently biased toward our thread and
1090 // whether the epoch is still valid
1091 // Note that the runtime guarantees sufficient alignment of JavaThread
1092 // pointers to allow age to be placed into low bits
1093 // First check to see whether biasing is even enabled for this object
1094 Label cas_label;
1095 int null_check_offset = -1;
1096 if (!swap_reg_contains_mark) {
1097 null_check_offset = offset();
1098 movptr(swap_reg, mark_addr);
1099 }
1100 if (need_tmp_reg) {
1101 push(tmp_reg);
1102 }
1103 movptr(tmp_reg, swap_reg);
1104 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1105 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1106 if (need_tmp_reg) {
1107 pop(tmp_reg);
1108 }
1109 jcc(Assembler::notEqual, cas_label);
1110 // The bias pattern is present in the object's header. Need to check
1111 // whether the bias owner and the epoch are both still current.
1112 #ifndef _LP64
1113 // Note that because there is no current thread register on x86_32 we
1114 // need to store off the mark word we read out of the object to
1115 // avoid reloading it and needing to recheck invariants below. This
1116 // store is unfortunate but it makes the overall code shorter and
1117 // simpler.
1118 movptr(saved_mark_addr, swap_reg);
1119 #endif
1120 if (need_tmp_reg) {
1121 push(tmp_reg);
1122 }
1123 if (swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 }
1126 load_prototype_header(tmp_reg, obj_reg);
1127 #ifdef _LP64
1128 orptr(tmp_reg, r15_thread);
1129 xorptr(tmp_reg, swap_reg);
1130 Register header_reg = tmp_reg;
1131 #else
1132 xorptr(tmp_reg, swap_reg);
1133 get_thread(swap_reg);
1134 xorptr(swap_reg, tmp_reg);
1135 Register header_reg = swap_reg;
1136 #endif
1137 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1138 if (need_tmp_reg) {
1139 pop(tmp_reg);
1140 }
1141 if (counters != NULL) {
1142 cond_inc32(Assembler::zero,
1143 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1144 }
1145 jcc(Assembler::equal, done);
1146
1147 Label try_revoke_bias;
1148 Label try_rebias;
1149
1150 // At this point we know that the header has the bias pattern and
1151 // that we are not the bias owner in the current epoch. We need to
1152 // figure out more details about the state of the header in order to
1153 // know what operations can be legally performed on the object's
1154 // header.
1155
1156 // If the low three bits in the xor result aren't clear, that means
1157 // the prototype header is no longer biased and we have to revoke
1158 // the bias on this object.
1159 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1160 jccb_if_possible(Assembler::notZero, try_revoke_bias);
1161
1162 // Biasing is still enabled for this data type. See whether the
1163 // epoch of the current bias is still valid, meaning that the epoch
1164 // bits of the mark word are equal to the epoch bits of the
1165 // prototype header. (Note that the prototype header's epoch bits
1166 // only change at a safepoint.) If not, attempt to rebias the object
1167 // toward the current thread. Note that we must be absolutely sure
1168 // that the current epoch is invalid in order to do this because
1169 // otherwise the manipulations it performs on the mark word are
1170 // illegal.
1171 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1172 jccb_if_possible(Assembler::notZero, try_rebias);
1173
1174 // The epoch of the current bias is still valid but we know nothing
1175 // about the owner; it might be set or it might be clear. Try to
1176 // acquire the bias of the object using an atomic operation. If this
1177 // fails we will go in to the runtime to revoke the object's bias.
1178 // Note that we first construct the presumed unbiased header so we
1179 // don't accidentally blow away another thread's valid bias.
1180 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1181 andptr(swap_reg,
1182 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1183 if (need_tmp_reg) {
1184 push(tmp_reg);
1185 }
1186 #ifdef _LP64
1187 movptr(tmp_reg, swap_reg);
1188 orptr(tmp_reg, r15_thread);
1189 #else
1190 get_thread(tmp_reg);
1191 orptr(tmp_reg, swap_reg);
1192 #endif
1193 if (os::is_MP()) {
1194 lock();
1195 }
1196 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1197 if (need_tmp_reg) {
1198 pop(tmp_reg);
1199 }
1200 // If the biasing toward our thread failed, this means that
1201 // another thread succeeded in biasing it toward itself and we
1202 // need to revoke that bias. The revocation will occur in the
1203 // interpreter runtime in the slow case.
1204 if (counters != NULL) {
1205 cond_inc32(Assembler::zero,
1206 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1207 }
1208 if (slow_case != NULL) {
1209 jcc(Assembler::notZero, *slow_case);
1210 }
1211 jmp(done);
1212
1213 bind(try_rebias);
1214 // At this point we know the epoch has expired, meaning that the
1215 // current "bias owner", if any, is actually invalid. Under these
1216 // circumstances _only_, we are allowed to use the current header's
1217 // value as the comparison value when doing the cas to acquire the
1218 // bias in the current epoch. In other words, we allow transfer of
1219 // the bias from one thread to another directly in this situation.
1220 //
1221 // FIXME: due to a lack of registers we currently blow away the age
1222 // bits in this situation. Should attempt to preserve them.
1223 if (need_tmp_reg) {
1224 push(tmp_reg);
1225 }
1226 load_prototype_header(tmp_reg, obj_reg);
1227 #ifdef _LP64
1228 orptr(tmp_reg, r15_thread);
1229 #else
1230 get_thread(swap_reg);
1231 orptr(tmp_reg, swap_reg);
1232 movptr(swap_reg, saved_mark_addr);
1233 #endif
1234 if (os::is_MP()) {
1235 lock();
1236 }
1237 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1238 if (need_tmp_reg) {
1239 pop(tmp_reg);
1240 }
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 if (need_tmp_reg) {
1267 push(tmp_reg);
1268 }
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 if (need_tmp_reg) {
1275 pop(tmp_reg);
1276 }
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1284
1285 bind(cas_label);
1286
1287 return null_check_offset;
1288 }
1289
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1292
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1304
1305 #ifdef COMPILER2
1306
1307 #if INCLUDE_RTM_OPT
1308
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1326
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1336
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1361
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 if (os::is_MP()) {
1372 lock();
1373 }
1374 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1375 }
1376 jmpb(L_done);
1377 bind(L_check_always_rtm1);
1378 // Reload RTMLockingCounters* address
1379 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1380 bind(L_check_always_rtm2);
1381 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1382 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1383 jccb(Assembler::below, L_done);
1384 if (method_data != NULL) {
1385 // set rtm_state to "always rtm" in MDO
1386 mov_metadata(tmpReg, method_data);
1387 if (os::is_MP()) {
1388 lock();
1389 }
1390 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1391 }
1392 bind(L_done);
1393 }
1394
1395 // Update counters and perform abort ratio calculation
1396 // input: abort_status_Reg
1397 // rtm_counters_Reg, flags are killed
1398 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1399 Register rtm_counters_Reg,
1400 RTMLockingCounters* rtm_counters,
1401 Metadata* method_data,
1402 bool profile_rtm) {
1403
1404 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1405 // update rtm counters based on rax value at abort
1406 // reads abort_status_Reg, updates flags
1407 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1408 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1409 if (profile_rtm) {
1410 // Save abort status because abort_status_Reg is used by following code.
1411 if (RTMRetryCount > 0) {
1412 push(abort_status_Reg);
1413 }
1414 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1415 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1416 // restore abort status
1417 if (RTMRetryCount > 0) {
1418 pop(abort_status_Reg);
1419 }
1420 }
1421 }
1422
1423 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1424 // inputs: retry_count_Reg
1425 // : abort_status_Reg
1426 // output: retry_count_Reg decremented by 1
1427 // flags are killed
1428 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1429 Label doneRetry;
1430 assert(abort_status_Reg == rax, "");
1431 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1432 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1433 // if reason is in 0x6 and retry count != 0 then retry
1434 andptr(abort_status_Reg, 0x6);
1435 jccb(Assembler::zero, doneRetry);
1436 testl(retry_count_Reg, retry_count_Reg);
1437 jccb(Assembler::zero, doneRetry);
1438 pause();
1439 decrementl(retry_count_Reg);
1440 jmp(retryLabel);
1441 bind(doneRetry);
1442 }
1443
1444 // Spin and retry if lock is busy,
1445 // inputs: box_Reg (monitor address)
1446 // : retry_count_Reg
1447 // output: retry_count_Reg decremented by 1
1448 // : clear z flag if retry count exceeded
1449 // tmp_Reg, scr_Reg, flags are killed
1450 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1451 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1452 Label SpinLoop, SpinExit, doneRetry;
1453 // Clean monitor_value bit to get valid pointer
1454 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1455
1456 testl(retry_count_Reg, retry_count_Reg);
1457 jccb(Assembler::zero, doneRetry);
1458 decrementl(retry_count_Reg);
1459 movptr(scr_Reg, RTMSpinLoopCount);
1460
1461 bind(SpinLoop);
1462 pause();
1463 decrementl(scr_Reg);
1464 jccb(Assembler::lessEqual, SpinExit);
1465 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1466 testptr(tmp_Reg, tmp_Reg);
1467 jccb(Assembler::notZero, SpinLoop);
1468
1469 bind(SpinExit);
1470 jmp(retryLabel);
1471 bind(doneRetry);
1472 incrementl(retry_count_Reg); // clear z flag
1473 }
1474
1475 // Use RTM for normal stack locks
1476 // Input: objReg (object to lock)
1477 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1478 Register retry_on_abort_count_Reg,
1479 RTMLockingCounters* stack_rtm_counters,
1480 Metadata* method_data, bool profile_rtm,
1481 Label& DONE_LABEL, Label& IsInflated) {
1482 assert(UseRTMForStackLocks, "why call this otherwise?");
1483 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1484 assert(tmpReg == rax, "");
1485 assert(scrReg == rdx, "");
1486 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1487
1488 if (RTMRetryCount > 0) {
1489 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1490 bind(L_rtm_retry);
1491 }
1492 movptr(tmpReg, Address(objReg, 0));
1493 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1494 jcc(Assembler::notZero, IsInflated);
1495
1496 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1497 Label L_noincrement;
1498 if (RTMTotalCountIncrRate > 1) {
1499 // tmpReg, scrReg and flags are killed
1500 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1501 }
1502 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1503 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1504 bind(L_noincrement);
1505 }
1506 xbegin(L_on_abort);
1507 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1508 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1509 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1510 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1511
1512 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1513 if (UseRTMXendForLockBusy) {
1514 xend();
1515 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1516 jmp(L_decrement_retry);
1517 }
1518 else {
1519 xabort(0);
1520 }
1521 bind(L_on_abort);
1522 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1523 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1524 }
1525 bind(L_decrement_retry);
1526 if (RTMRetryCount > 0) {
1527 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1528 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1529 }
1530 }
1531
1532 // Use RTM for inflating locks
1533 // inputs: objReg (object to lock)
1534 // boxReg (on-stack box address (displaced header location) - KILLED)
1535 // tmpReg (ObjectMonitor address + 2(monitor_value))
1536 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1537 Register scrReg, Register retry_on_busy_count_Reg,
1538 Register retry_on_abort_count_Reg,
1539 RTMLockingCounters* rtm_counters,
1540 Metadata* method_data, bool profile_rtm,
1541 Label& DONE_LABEL) {
1542 assert(UseRTMLocking, "why call this otherwise?");
1543 assert(tmpReg == rax, "");
1544 assert(scrReg == rdx, "");
1545 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1546 // Clean monitor_value bit to get valid pointer
1547 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1548
1549 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1550 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1551 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1552
1553 if (RTMRetryCount > 0) {
1554 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1555 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1556 bind(L_rtm_retry);
1557 }
1558 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1559 Label L_noincrement;
1560 if (RTMTotalCountIncrRate > 1) {
1561 // tmpReg, scrReg and flags are killed
1562 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1563 }
1564 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1565 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1566 bind(L_noincrement);
1567 }
1568 xbegin(L_on_abort);
1569 movptr(tmpReg, Address(objReg, 0));
1570 movptr(tmpReg, Address(tmpReg, owner_offset));
1571 testptr(tmpReg, tmpReg);
1572 jcc(Assembler::zero, DONE_LABEL);
1573 if (UseRTMXendForLockBusy) {
1574 xend();
1575 jmp(L_decrement_retry);
1576 }
1577 else {
1578 xabort(0);
1579 }
1580 bind(L_on_abort);
1581 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1582 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1583 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1584 }
1585 if (RTMRetryCount > 0) {
1586 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1587 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1588 }
1589
1590 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1591 testptr(tmpReg, tmpReg) ;
1592 jccb(Assembler::notZero, L_decrement_retry) ;
1593
1594 // Appears unlocked - try to swing _owner from null to non-null.
1595 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1596 #ifdef _LP64
1597 Register threadReg = r15_thread;
1598 #else
1599 get_thread(scrReg);
1600 Register threadReg = scrReg;
1601 #endif
1602 if (os::is_MP()) {
1603 lock();
1604 }
1605 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1606
1607 if (RTMRetryCount > 0) {
1608 // success done else retry
1609 jccb(Assembler::equal, DONE_LABEL) ;
1610 bind(L_decrement_retry);
1611 // Spin and retry if lock is busy.
1612 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1613 }
1614 else {
1615 bind(L_decrement_retry);
1616 }
1617 }
1618
1619 #endif // INCLUDE_RTM_OPT
1620
1621 // Fast_Lock and Fast_Unlock used by C2
1622
1623 // Because the transitions from emitted code to the runtime
1624 // monitorenter/exit helper stubs are so slow it's critical that
1625 // we inline both the stack-locking fast-path and the inflated fast path.
1626 //
1627 // See also: cmpFastLock and cmpFastUnlock.
1628 //
1629 // What follows is a specialized inline transliteration of the code
1630 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1631 // another option would be to emit TrySlowEnter and TrySlowExit methods
1632 // at startup-time. These methods would accept arguments as
1633 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1634 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1635 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1636 // In practice, however, the # of lock sites is bounded and is usually small.
1637 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1638 // if the processor uses simple bimodal branch predictors keyed by EIP
1639 // Since the helper routines would be called from multiple synchronization
1640 // sites.
1641 //
1642 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1643 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1644 // to those specialized methods. That'd give us a mostly platform-independent
1645 // implementation that the JITs could optimize and inline at their pleasure.
1646 // Done correctly, the only time we'd need to cross to native could would be
1647 // to park() or unpark() threads. We'd also need a few more unsafe operators
1648 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1649 // (b) explicit barriers or fence operations.
1650 //
1651 // TODO:
1652 //
1653 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1654 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1655 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1656 // the lock operators would typically be faster than reifying Self.
1657 //
1658 // * Ideally I'd define the primitives as:
1659 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1660 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1661 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1662 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1663 // Furthermore the register assignments are overconstrained, possibly resulting in
1664 // sub-optimal code near the synchronization site.
1665 //
1666 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1667 // Alternately, use a better sp-proximity test.
1668 //
1669 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1670 // Either one is sufficient to uniquely identify a thread.
1671 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1672 //
1673 // * Intrinsify notify() and notifyAll() for the common cases where the
1674 // object is locked by the calling thread but the waitlist is empty.
1675 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1676 //
1677 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1678 // But beware of excessive branch density on AMD Opterons.
1679 //
1680 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1681 // or failure of the fast-path. If the fast-path fails then we pass
1682 // control to the slow-path, typically in C. In Fast_Lock and
1683 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1684 // will emit a conditional branch immediately after the node.
1685 // So we have branches to branches and lots of ICC.ZF games.
1686 // Instead, it might be better to have C2 pass a "FailureLabel"
1687 // into Fast_Lock and Fast_Unlock. In the case of success, control
1688 // will drop through the node. ICC.ZF is undefined at exit.
1689 // In the case of failure, the node will branch directly to the
1690 // FailureLabel
1691
1692
1693 // obj: object to lock
1694 // box: on-stack box address (displaced header location) - KILLED
1695 // rax,: tmp -- KILLED
1696 // scr: tmp -- KILLED
1697 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1698 Register scrReg, Register cx1Reg, Register cx2Reg,
1699 BiasedLockingCounters* counters,
1700 RTMLockingCounters* rtm_counters,
1701 RTMLockingCounters* stack_rtm_counters,
1702 Metadata* method_data,
1703 bool use_rtm, bool profile_rtm) {
1704 // Ensure the register assignents are disjoint
1705 assert(tmpReg == rax, "");
1706
1707 if (use_rtm) {
1708 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1709 } else {
1710 assert(cx1Reg == noreg, "");
1711 assert(cx2Reg == noreg, "");
1712 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1713 }
1714
1715 if (counters != NULL) {
1716 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1717 }
1718 if (EmitSync & 1) {
1719 // set box->dhw = unused_mark (3)
1720 // Force all sync thru slow-path: slow_enter() and slow_exit()
1721 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1722 cmpptr (rsp, (int32_t)NULL_WORD);
1723 } else
1724 if (EmitSync & 2) {
1725 Label DONE_LABEL ;
1726 if (UseBiasedLocking) {
1727 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1728 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1729 }
1730
1731 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1732 orptr (tmpReg, 0x1);
1733 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1734 if (os::is_MP()) {
1735 lock();
1736 }
1737 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1738 jccb(Assembler::equal, DONE_LABEL);
1739 // Recursive locking
1740 subptr(tmpReg, rsp);
1741 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1742 movptr(Address(boxReg, 0), tmpReg);
1743 bind(DONE_LABEL);
1744 } else {
1745 // Possible cases that we'll encounter in fast_lock
1746 // ------------------------------------------------
1747 // * Inflated
1748 // -- unlocked
1749 // -- Locked
1750 // = by self
1751 // = by other
1752 // * biased
1753 // -- by Self
1754 // -- by other
1755 // * neutral
1756 // * stack-locked
1757 // -- by self
1758 // = sp-proximity test hits
1759 // = sp-proximity test generates false-negative
1760 // -- by other
1761 //
1762
1763 Label IsInflated, DONE_LABEL;
1764
1765 // it's stack-locked, biased or neutral
1766 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1767 // order to reduce the number of conditional branches in the most common cases.
1768 // Beware -- there's a subtle invariant that fetch of the markword
1769 // at [FETCH], below, will never observe a biased encoding (*101b).
1770 // If this invariant is not held we risk exclusion (safety) failure.
1771 if (UseBiasedLocking && !UseOptoBiasInlining) {
1772 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1773 }
1774
1775 #if INCLUDE_RTM_OPT
1776 if (UseRTMForStackLocks && use_rtm) {
1777 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1778 stack_rtm_counters, method_data, profile_rtm,
1779 DONE_LABEL, IsInflated);
1780 }
1781 #endif // INCLUDE_RTM_OPT
1782
1783 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1784 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1785 jccb_if_possible(Assembler::notZero, IsInflated);
1786
1787 // Attempt stack-locking ...
1788 orptr (tmpReg, markOopDesc::unlocked_value);
1789 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1790 if (os::is_MP()) {
1791 lock();
1792 }
1793 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1794 if (counters != NULL) {
1795 cond_inc32(Assembler::equal,
1796 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1797 }
1798 jcc(Assembler::equal, DONE_LABEL); // Success
1799
1800 // Recursive locking.
1801 // The object is stack-locked: markword contains stack pointer to BasicLock.
1802 // Locked by current thread if difference with current SP is less than one page.
1803 subptr(tmpReg, rsp);
1804 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1805 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1806 movptr(Address(boxReg, 0), tmpReg);
1807 if (counters != NULL) {
1808 cond_inc32(Assembler::equal,
1809 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1810 }
1811 jmp(DONE_LABEL);
1812
1813 bind(IsInflated);
1814 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value)
1815
1816 #if INCLUDE_RTM_OPT
1817 // Use the same RTM locking code in 32- and 64-bit VM.
1818 if (use_rtm) {
1819 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1820 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1821 } else {
1822 #endif // INCLUDE_RTM_OPT
1823
1824 #ifndef _LP64
1825 // The object is inflated.
1826 //
1827 // TODO-FIXME: eliminate the ugly use of manifest constants:
1828 // Use markOopDesc::monitor_value instead of "2".
1829 // use markOop::unused_mark() instead of "3".
1830 // The tmpReg value is an objectMonitor reference ORed with
1831 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
1832 // objectmonitor pointer by masking off the "2" bit or we can just
1833 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
1834 // field offsets with "-2" to compensate for and annul the low-order tag bit.
1835 //
1836 // I use the latter as it avoids AGI stalls.
1837 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
1838 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
1839 //
1840 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
1841
1842 // boxReg refers to the on-stack BasicLock in the current frame.
1843 // We'd like to write:
1844 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
1845 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1846 // additional latency as we have another ST in the store buffer that must drain.
1847
1848 if (EmitSync & 8192) {
1849 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1850 get_thread (scrReg);
1851 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1852 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1853 if (os::is_MP()) {
1854 lock();
1855 }
1856 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1857 } else
1858 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1859 movptr(scrReg, boxReg);
1860 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1861
1862 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1863 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1864 // prefetchw [eax + Offset(_owner)-2]
1865 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1866 }
1867
1868 if ((EmitSync & 64) == 0) {
1869 // Optimistic form: consider XORL tmpReg,tmpReg
1870 movptr(tmpReg, NULL_WORD);
1871 } else {
1872 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1873 // Test-And-CAS instead of CAS
1874 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1875 testptr(tmpReg, tmpReg); // Locked ?
1876 jccb_if_possible(Assembler::notZero, DONE_LABEL);
1877 }
1878
1879 // Appears unlocked - try to swing _owner from null to non-null.
1880 // Ideally, I'd manifest "Self" with get_thread and then attempt
1881 // to CAS the register containing Self into m->Owner.
1882 // But we don't have enough registers, so instead we can either try to CAS
1883 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1884 // we later store "Self" into m->Owner. Transiently storing a stack address
1885 // (rsp or the address of the box) into m->owner is harmless.
1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1887 if (os::is_MP()) {
1888 lock();
1889 }
1890 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1891 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1892 jccb_if_possible(Assembler::notZero, DONE_LABEL);
1893 get_thread (scrReg); // beware: clobbers ICCs
1894 movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg);
1895 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1896
1897 // If the CAS fails we can either retry or pass control to the slow-path.
1898 // We use the latter tactic.
1899 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1900 // If the CAS was successful ...
1901 // Self has acquired the lock
1902 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1903 // Intentional fall-through into DONE_LABEL ...
1904 } else {
1905 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1906 movptr(boxReg, tmpReg);
1907
1908 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1909 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1910 // prefetchw [eax + Offset(_owner)-2]
1911 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1912 }
1913
1914 if ((EmitSync & 64) == 0) {
1915 // Optimistic form
1916 xorptr (tmpReg, tmpReg);
1917 } else {
1918 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1919 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1920 testptr(tmpReg, tmpReg); // Locked ?
1921 jccb_if_possible(Assembler::notZero, DONE_LABEL);
1922 }
1923
1924 // Appears unlocked - try to swing _owner from null to non-null.
1925 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1926 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1927 get_thread (scrReg);
1928 if (os::is_MP()) {
1929 lock();
1930 }
1931 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1932
1933 // If the CAS fails we can either retry or pass control to the slow-path.
1934 // We use the latter tactic.
1935 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1936 // If the CAS was successful ...
1937 // Self has acquired the lock
1938 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1939 // Intentional fall-through into DONE_LABEL ...
1940 }
1941 #else // _LP64
1942 // It's inflated
1943
1944 // TODO: someday avoid the ST-before-CAS penalty by
1945 // relocating (deferring) the following ST.
1946 // We should also think about trying a CAS without having
1947 // fetched _owner. If the CAS is successful we may
1948 // avoid an RTO->RTS upgrade on the $line.
1949
1950 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1951 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1952
1953 movptr (boxReg, tmpReg);
1954 movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1955 testptr(tmpReg, tmpReg);
1956 jccb_if_possible(Assembler::notZero, DONE_LABEL);
1957
1958 // It's inflated and appears unlocked
1959 if (os::is_MP()) {
1960 lock();
1961 }
1962 cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1963 // Intentional fall-through into DONE_LABEL ...
1964 #endif // _LP64
1965
1966 #if INCLUDE_RTM_OPT
1967 } // use_rtm()
1968 #endif
1969 // DONE_LABEL is a hot target - we'd really like to place it at the
1970 // start of cache line by padding with NOPs.
1971 // See the AMD and Intel software optimization manuals for the
1972 // most efficient "long" NOP encodings.
1973 // Unfortunately none of our alignment mechanisms suffice.
1974 bind(DONE_LABEL);
1975
1976 // At DONE_LABEL the icc ZFlag is set as follows ...
1977 // Fast_Unlock uses the same protocol.
1978 // ZFlag == 1 -> Success
1979 // ZFlag == 0 -> Failure - force control through the slow-path
1980 }
1981 }
1982
1983 // obj: object to unlock
1984 // box: box address (displaced header location), killed. Must be EAX.
1985 // tmp: killed, cannot be obj nor box.
1986 //
1987 // Some commentary on balanced locking:
1988 //
1989 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1990 // Methods that don't have provably balanced locking are forced to run in the
1991 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1992 // The interpreter provides two properties:
1993 // I1: At return-time the interpreter automatically and quietly unlocks any
1994 // objects acquired the current activation (frame). Recall that the
1995 // interpreter maintains an on-stack list of locks currently held by
1996 // a frame.
1997 // I2: If a method attempts to unlock an object that is not held by the
1998 // the frame the interpreter throws IMSX.
1999 //
2000 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
2001 // B() doesn't have provably balanced locking so it runs in the interpreter.
2002 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
2003 // is still locked by A().
2004 //
2005 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
2006 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
2007 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
2008 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
2009
2010 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
2011 assert(boxReg == rax, "");
2012 assert_different_registers(objReg, boxReg, tmpReg);
2013
2014 if (EmitSync & 4) {
2015 // Disable - inhibit all inlining. Force control through the slow-path
2016 cmpptr (rsp, 0);
2017 } else
2018 if (EmitSync & 8) {
2019 Label DONE_LABEL;
2020 if (UseBiasedLocking) {
2021 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2022 }
2023 // Classic stack-locking code ...
2024 // Check whether the displaced header is 0
2025 //(=> recursive unlock)
2026 movptr(tmpReg, Address(boxReg, 0));
2027 testptr(tmpReg, tmpReg);
2028 jccb(Assembler::zero, DONE_LABEL);
2029 // If not recursive lock, reset the header to displaced header
2030 if (os::is_MP()) {
2031 lock();
2032 }
2033 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2034 bind(DONE_LABEL);
2035 } else {
2036 Label DONE_LABEL, Stacked, CheckSucc;
2037
2038 // Critically, the biased locking test must have precedence over
2039 // and appear before the (box->dhw == 0) recursive stack-lock test.
2040 if (UseBiasedLocking && !UseOptoBiasInlining) {
2041 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2042 }
2043
2044 #if INCLUDE_RTM_OPT
2045 if (UseRTMForStackLocks && use_rtm) {
2046 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2047 Label L_regular_unlock;
2048 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2049 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2050 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2051 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2052 xend(); // otherwise end...
2053 jmp(DONE_LABEL); // ... and we're done
2054 bind(L_regular_unlock);
2055 }
2056 #endif
2057
2058 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2059 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2060 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2061 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2062 jccb (Assembler::zero, Stacked);
2063
2064 // It's inflated.
2065 #if INCLUDE_RTM_OPT
2066 if (use_rtm) {
2067 Label L_regular_inflated_unlock;
2068 // Clean monitor_value bit to get valid pointer
2069 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2070 movptr(boxReg, Address(tmpReg, owner_offset));
2071 testptr(boxReg, boxReg);
2072 jccb(Assembler::notZero, L_regular_inflated_unlock);
2073 xend();
2074 jmpb_if_possible(DONE_LABEL);
2075 bind(L_regular_inflated_unlock);
2076 }
2077 #endif
2078
2079 // Despite our balanced locking property we still check that m->_owner == Self
2080 // as java routines or native JNI code called by this thread might
2081 // have released the lock.
2082 // Refer to the comments in synchronizer.cpp for how we might encode extra
2083 // state in _succ so we can avoid fetching EntryList|cxq.
2084 //
2085 // I'd like to add more cases in fast_lock() and fast_unlock() --
2086 // such as recursive enter and exit -- but we have to be wary of
2087 // I$ bloat, T$ effects and BP$ effects.
2088 //
2089 // If there's no contention try a 1-0 exit. That is, exit without
2090 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2091 // we detect and recover from the race that the 1-0 exit admits.
2092 //
2093 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2094 // before it STs null into _owner, releasing the lock. Updates
2095 // to data protected by the critical section must be visible before
2096 // we drop the lock (and thus before any other thread could acquire
2097 // the lock and observe the fields protected by the lock).
2098 // IA32's memory-model is SPO, so STs are ordered with respect to
2099 // each other and there's no need for an explicit barrier (fence).
2100 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2101 #ifndef _LP64
2102 get_thread (boxReg);
2103 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2104 // prefetchw [ebx + Offset(_owner)-2]
2105 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2106 }
2107
2108 // Note that we could employ various encoding schemes to reduce
2109 // the number of loads below (currently 4) to just 2 or 3.
2110 // Refer to the comments in synchronizer.cpp.
2111 // In practice the chain of fetches doesn't seem to impact performance, however.
2112 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2113 // Attempt to reduce branch density - AMD's branch predictor.
2114 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2115 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2116 orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2117 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2118 jccb_if_possible(Assembler::notZero, DONE_LABEL);
2119 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2120 jmpb_if_possible(DONE_LABEL);
2121 } else {
2122 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2123 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2124 jccb_if_possible(Assembler::notZero, DONE_LABEL);
2125 movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2126 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2127 jccb_if_possible(Assembler::notZero, CheckSucc);
2128 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2129 jmpb_if_possible(DONE_LABEL);
2130 }
2131
2132 // The Following code fragment (EmitSync & 65536) improves the performance of
2133 // contended applications and contended synchronization microbenchmarks.
2134 // Unfortunately the emission of the code - even though not executed - causes regressions
2135 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2136 // with an equal number of never-executed NOPs results in the same regression.
2137 // We leave it off by default.
2138
2139 if ((EmitSync & 65536) != 0) {
2140 Label LSuccess, LGoSlowPath ;
2141
2142 bind (CheckSucc);
2143
2144 // Optional pre-test ... it's safe to elide this
2145 if ((EmitSync & 16) == 0) {
2146 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2147 jccb (Assembler::zero, LGoSlowPath);
2148 }
2149
2150 // We have a classic Dekker-style idiom:
2151 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2152 // There are a number of ways to implement the barrier:
2153 // (1) lock:andl &m->_owner, 0
2154 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2155 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2156 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2157 // (2) If supported, an explicit MFENCE is appealing.
2158 // In older IA32 processors MFENCE is slower than lock:add or xchg
2159 // particularly if the write-buffer is full as might be the case if
2160 // if stores closely precede the fence or fence-equivalent instruction.
2161 // In more modern implementations MFENCE appears faster, however.
2162 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2163 // The $lines underlying the top-of-stack should be in M-state.
2164 // The locked add instruction is serializing, of course.
2165 // (4) Use xchg, which is serializing
2166 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2167 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2168 // The integer condition codes will tell us if succ was 0.
2169 // Since _succ and _owner should reside in the same $line and
2170 // we just stored into _owner, it's likely that the $line
2171 // remains in M-state for the lock:orl.
2172 //
2173 // We currently use (3), although it's likely that switching to (2)
2174 // is correct for the future.
2175
2176 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2177 if (os::is_MP()) {
2178 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2179 mfence();
2180 } else {
2181 lock (); addptr(Address(rsp, 0), 0);
2182 }
2183 }
2184 // Ratify _succ remains non-null
2185 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0);
2186 jccb (Assembler::notZero, LSuccess);
2187
2188 xorptr(boxReg, boxReg); // box is really EAX
2189 if (os::is_MP()) { lock(); }
2190 cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2191 jccb (Assembler::notEqual, LSuccess);
2192 // Since we're low on registers we installed rsp as a placeholding in _owner.
2193 // Now install Self over rsp. This is safe as we're transitioning from
2194 // non-null to non=null
2195 get_thread (boxReg);
2196 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg);
2197 // Intentional fall-through into LGoSlowPath ...
2198
2199 bind (LGoSlowPath);
2200 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2201 jmpb_if_possible(DONE_LABEL);
2202
2203 bind (LSuccess);
2204 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2205 jmpb_if_possible(DONE_LABEL);
2206 }
2207
2208 bind (Stacked);
2209 // It's not inflated and it's not recursively stack-locked and it's not biased.
2210 // It must be stack-locked.
2211 // Try to reset the header to displaced header.
2212 // The "box" value on the stack is stable, so we can reload
2213 // and be assured we observe the same value as above.
2214 movptr(tmpReg, Address(boxReg, 0));
2215 if (os::is_MP()) {
2216 lock();
2217 }
2218 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2219 // Intention fall-thru into DONE_LABEL
2220
2221 // DONE_LABEL is a hot target - we'd really like to place it at the
2222 // start of cache line by padding with NOPs.
2223 // See the AMD and Intel software optimization manuals for the
2224 // most efficient "long" NOP encodings.
2225 // Unfortunately none of our alignment mechanisms suffice.
2226 if ((EmitSync & 65536) == 0) {
2227 bind (CheckSucc);
2228 }
2229 #else // _LP64
2230 // It's inflated
2231 movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2232 xorptr(boxReg, r15_thread);
2233 orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2234 jccb_if_possible(Assembler::notZero, DONE_LABEL);
2235 movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2236 orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2237 jccb (Assembler::notZero, CheckSucc);
2238 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2239 jmpb_if_possible(DONE_LABEL);
2240
2241 if ((EmitSync & 65536) == 0) {
2242 Label LSuccess, LGoSlowPath ;
2243 bind (CheckSucc);
2244 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2245 jccb (Assembler::zero, LGoSlowPath);
2246
2247 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2248 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2249 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2250 // are all faster when the write buffer is populated.
2251 movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2252 if (os::is_MP()) {
2253 lock (); addl (Address(rsp, 0), 0);
2254 }
2255 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2256 jccb (Assembler::notZero, LSuccess);
2257
2258 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2259 if (os::is_MP()) { lock(); }
2260 cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2261 jccb (Assembler::notEqual, LSuccess);
2262 // Intentional fall-through into slow-path
2263
2264 bind (LGoSlowPath);
2265 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2266 jmpb_if_possible(DONE_LABEL);
2267
2268 bind (LSuccess);
2269 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2270 jmpb_if_possible(DONE_LABEL);
2271 }
2272
2273 bind (Stacked);
2274 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2275 if (os::is_MP()) { lock(); }
2276 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2277
2278 if (EmitSync & 65536) {
2279 bind (CheckSucc);
2280 }
2281 #endif
2282 bind(DONE_LABEL);
2283 // Avoid branch to branch on AMD processors
2284 if (EmitSync & 32768) {
2285 nop();
2286 }
2287 }
2288 }
2289 #endif // COMPILER2
2290
2291 void MacroAssembler::c2bool(Register x) {
2292 // implements x == 0 ? 0 : 1
2293 // note: must only look at least-significant byte of x
2294 // since C-style booleans are stored in one byte
2295 // only! (was bug)
2296 andl(x, 0xFF);
2297 setb(Assembler::notZero, x);
2298 }
2299
2300 // Wouldn't need if AddressLiteral version had new name
2301 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2302 Assembler::call(L, rtype);
2303 }
2304
2305 void MacroAssembler::call(Register entry) {
2306 Assembler::call(entry);
2307 }
2308
2309 void MacroAssembler::call(AddressLiteral entry) {
2310 if (reachable(entry)) {
2311 Assembler::call_literal(entry.target(), entry.rspec());
2312 } else {
2313 lea(rscratch1, entry);
2314 Assembler::call(rscratch1);
2315 }
2316 }
2317
2318 void MacroAssembler::ic_call(address entry) {
2319 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2320 movptr(rax, (intptr_t)Universe::non_oop_word());
2321 call(AddressLiteral(entry, rh));
2322 }
2323
2324 // Implementation of call_VM versions
2325
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 bool check_exceptions) {
2329 Label C, E;
2330 call(C, relocInfo::none);
2331 jmp(E);
2332
2333 bind(C);
2334 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2335 ret(0);
2336
2337 bind(E);
2338 }
2339
2340 void MacroAssembler::call_VM(Register oop_result,
2341 address entry_point,
2342 Register arg_1,
2343 bool check_exceptions) {
2344 Label C, E;
2345 call(C, relocInfo::none);
2346 jmp(E);
2347
2348 bind(C);
2349 pass_arg1(this, arg_1);
2350 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2351 ret(0);
2352
2353 bind(E);
2354 }
2355
2356 void MacroAssembler::call_VM(Register oop_result,
2357 address entry_point,
2358 Register arg_1,
2359 Register arg_2,
2360 bool check_exceptions) {
2361 Label C, E;
2362 call(C, relocInfo::none);
2363 jmp(E);
2364
2365 bind(C);
2366
2367 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2368
2369 pass_arg2(this, arg_2);
2370 pass_arg1(this, arg_1);
2371 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2372 ret(0);
2373
2374 bind(E);
2375 }
2376
2377 void MacroAssembler::call_VM(Register oop_result,
2378 address entry_point,
2379 Register arg_1,
2380 Register arg_2,
2381 Register arg_3,
2382 bool check_exceptions) {
2383 Label C, E;
2384 call(C, relocInfo::none);
2385 jmp(E);
2386
2387 bind(C);
2388
2389 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2390 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2391 pass_arg3(this, arg_3);
2392
2393 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2394 pass_arg2(this, arg_2);
2395
2396 pass_arg1(this, arg_1);
2397 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2398 ret(0);
2399
2400 bind(E);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 int number_of_arguments,
2407 bool check_exceptions) {
2408 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2409 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2410 }
2411
2412 void MacroAssembler::call_VM(Register oop_result,
2413 Register last_java_sp,
2414 address entry_point,
2415 Register arg_1,
2416 bool check_exceptions) {
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2419 }
2420
2421 void MacroAssembler::call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 Register arg_1,
2425 Register arg_2,
2426 bool check_exceptions) {
2427
2428 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2429 pass_arg2(this, arg_2);
2430 pass_arg1(this, arg_1);
2431 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2432 }
2433
2434 void MacroAssembler::call_VM(Register oop_result,
2435 Register last_java_sp,
2436 address entry_point,
2437 Register arg_1,
2438 Register arg_2,
2439 Register arg_3,
2440 bool check_exceptions) {
2441 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2442 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2443 pass_arg3(this, arg_3);
2444 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2445 pass_arg2(this, arg_2);
2446 pass_arg1(this, arg_1);
2447 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 int number_of_arguments,
2454 bool check_exceptions) {
2455 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2456 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2457 }
2458
2459 void MacroAssembler::super_call_VM(Register oop_result,
2460 Register last_java_sp,
2461 address entry_point,
2462 Register arg_1,
2463 bool check_exceptions) {
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2466 }
2467
2468 void MacroAssembler::super_call_VM(Register oop_result,
2469 Register last_java_sp,
2470 address entry_point,
2471 Register arg_1,
2472 Register arg_2,
2473 bool check_exceptions) {
2474
2475 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2476 pass_arg2(this, arg_2);
2477 pass_arg1(this, arg_1);
2478 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2479 }
2480
2481 void MacroAssembler::super_call_VM(Register oop_result,
2482 Register last_java_sp,
2483 address entry_point,
2484 Register arg_1,
2485 Register arg_2,
2486 Register arg_3,
2487 bool check_exceptions) {
2488 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2489 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2490 pass_arg3(this, arg_3);
2491 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2492 pass_arg2(this, arg_2);
2493 pass_arg1(this, arg_1);
2494 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2495 }
2496
2497 void MacroAssembler::call_VM_base(Register oop_result,
2498 Register java_thread,
2499 Register last_java_sp,
2500 address entry_point,
2501 int number_of_arguments,
2502 bool check_exceptions) {
2503 // determine java_thread register
2504 if (!java_thread->is_valid()) {
2505 #ifdef _LP64
2506 java_thread = r15_thread;
2507 #else
2508 java_thread = rdi;
2509 get_thread(java_thread);
2510 #endif // LP64
2511 }
2512 // determine last_java_sp register
2513 if (!last_java_sp->is_valid()) {
2514 last_java_sp = rsp;
2515 }
2516 // debugging support
2517 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2518 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2519 #ifdef ASSERT
2520 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2521 // r12 is the heapbase.
2522 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2523 #endif // ASSERT
2524
2525 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2526 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2527
2528 // push java thread (becomes first argument of C function)
2529
2530 NOT_LP64(push(java_thread); number_of_arguments++);
2531 LP64_ONLY(mov(c_rarg0, r15_thread));
2532
2533 // set last Java frame before call
2534 assert(last_java_sp != rbp, "can't use ebp/rbp");
2535
2536 // Only interpreter should have to set fp
2537 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2538
2539 // do the call, remove parameters
2540 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2541
2542 // restore the thread (cannot use the pushed argument since arguments
2543 // may be overwritten by C code generated by an optimizing compiler);
2544 // however can use the register value directly if it is callee saved.
2545 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2546 // rdi & rsi (also r15) are callee saved -> nothing to do
2547 #ifdef ASSERT
2548 guarantee(java_thread != rax, "change this code");
2549 push(rax);
2550 { Label L;
2551 get_thread(rax);
2552 cmpptr(java_thread, rax);
2553 jcc(Assembler::equal, L);
2554 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2555 bind(L);
2556 }
2557 pop(rax);
2558 #endif
2559 } else {
2560 get_thread(java_thread);
2561 }
2562 // reset last Java frame
2563 // Only interpreter should have to clear fp
2564 reset_last_Java_frame(java_thread, true);
2565
2566 #ifndef CC_INTERP
2567 // C++ interp handles this in the interpreter
2568 check_and_handle_popframe(java_thread);
2569 check_and_handle_earlyret(java_thread);
2570 #endif /* CC_INTERP */
2571
2572 if (check_exceptions) {
2573 // check for pending exceptions (java_thread is set upon return)
2574 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2575 #ifndef _LP64
2576 jump_cc(Assembler::notEqual,
2577 RuntimeAddress(StubRoutines::forward_exception_entry()));
2578 #else
2579 // This used to conditionally jump to forward_exception however it is
2580 // possible if we relocate that the branch will not reach. So we must jump
2581 // around so we can always reach
2582
2583 Label ok;
2584 jcc(Assembler::equal, ok);
2585 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2586 bind(ok);
2587 #endif // LP64
2588 }
2589
2590 // get oop result if there is one and reset the value in the thread
2591 if (oop_result->is_valid()) {
2592 get_vm_result(oop_result, java_thread);
2593 }
2594 }
2595
2596 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2597
2598 // Calculate the value for last_Java_sp
2599 // somewhat subtle. call_VM does an intermediate call
2600 // which places a return address on the stack just under the
2601 // stack pointer as the user finsihed with it. This allows
2602 // use to retrieve last_Java_pc from last_Java_sp[-1].
2603 // On 32bit we then have to push additional args on the stack to accomplish
2604 // the actual requested call. On 64bit call_VM only can use register args
2605 // so the only extra space is the return address that call_VM created.
2606 // This hopefully explains the calculations here.
2607
2608 #ifdef _LP64
2609 // We've pushed one address, correct last_Java_sp
2610 lea(rax, Address(rsp, wordSize));
2611 #else
2612 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2613 #endif // LP64
2614
2615 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2616
2617 }
2618
2619 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2620 call_VM_leaf_base(entry_point, number_of_arguments);
2621 }
2622
2623 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2624 pass_arg0(this, arg_0);
2625 call_VM_leaf(entry_point, 1);
2626 }
2627
2628 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2629
2630 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2631 pass_arg1(this, arg_1);
2632 pass_arg0(this, arg_0);
2633 call_VM_leaf(entry_point, 2);
2634 }
2635
2636 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2637 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2638 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2639 pass_arg2(this, arg_2);
2640 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2641 pass_arg1(this, arg_1);
2642 pass_arg0(this, arg_0);
2643 call_VM_leaf(entry_point, 3);
2644 }
2645
2646 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2649 }
2650
2651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2652
2653 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2654 pass_arg1(this, arg_1);
2655 pass_arg0(this, arg_0);
2656 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2657 }
2658
2659 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2660 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2661 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2662 pass_arg2(this, arg_2);
2663 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2664 pass_arg1(this, arg_1);
2665 pass_arg0(this, arg_0);
2666 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2667 }
2668
2669 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2670 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2671 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2672 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2673 pass_arg3(this, arg_3);
2674 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2675 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2676 pass_arg2(this, arg_2);
2677 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2678 pass_arg1(this, arg_1);
2679 pass_arg0(this, arg_0);
2680 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2681 }
2682
2683 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2684 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2685 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2686 verify_oop(oop_result, "broken oop in call_VM_base");
2687 }
2688
2689 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2690 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2691 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2692 }
2693
2694 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2695 }
2696
2697 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2698 }
2699
2700 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2701 if (reachable(src1)) {
2702 cmpl(as_Address(src1), imm);
2703 } else {
2704 lea(rscratch1, src1);
2705 cmpl(Address(rscratch1, 0), imm);
2706 }
2707 }
2708
2709 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2710 assert(!src2.is_lval(), "use cmpptr");
2711 if (reachable(src2)) {
2712 cmpl(src1, as_Address(src2));
2713 } else {
2714 lea(rscratch1, src2);
2715 cmpl(src1, Address(rscratch1, 0));
2716 }
2717 }
2718
2719 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2720 Assembler::cmpl(src1, imm);
2721 }
2722
2723 void MacroAssembler::cmp32(Register src1, Address src2) {
2724 Assembler::cmpl(src1, src2);
2725 }
2726
2727 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2728 ucomisd(opr1, opr2);
2729
2730 Label L;
2731 if (unordered_is_less) {
2732 movl(dst, -1);
2733 jcc(Assembler::parity, L);
2734 jcc(Assembler::below , L);
2735 movl(dst, 0);
2736 jcc(Assembler::equal , L);
2737 increment(dst);
2738 } else { // unordered is greater
2739 movl(dst, 1);
2740 jcc(Assembler::parity, L);
2741 jcc(Assembler::above , L);
2742 movl(dst, 0);
2743 jcc(Assembler::equal , L);
2744 decrementl(dst);
2745 }
2746 bind(L);
2747 }
2748
2749 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2750 ucomiss(opr1, opr2);
2751
2752 Label L;
2753 if (unordered_is_less) {
2754 movl(dst, -1);
2755 jcc(Assembler::parity, L);
2756 jcc(Assembler::below , L);
2757 movl(dst, 0);
2758 jcc(Assembler::equal , L);
2759 increment(dst);
2760 } else { // unordered is greater
2761 movl(dst, 1);
2762 jcc(Assembler::parity, L);
2763 jcc(Assembler::above , L);
2764 movl(dst, 0);
2765 jcc(Assembler::equal , L);
2766 decrementl(dst);
2767 }
2768 bind(L);
2769 }
2770
2771
2772 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2773 if (reachable(src1)) {
2774 cmpb(as_Address(src1), imm);
2775 } else {
2776 lea(rscratch1, src1);
2777 cmpb(Address(rscratch1, 0), imm);
2778 }
2779 }
2780
2781 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2782 #ifdef _LP64
2783 if (src2.is_lval()) {
2784 movptr(rscratch1, src2);
2785 Assembler::cmpq(src1, rscratch1);
2786 } else if (reachable(src2)) {
2787 cmpq(src1, as_Address(src2));
2788 } else {
2789 lea(rscratch1, src2);
2790 Assembler::cmpq(src1, Address(rscratch1, 0));
2791 }
2792 #else
2793 if (src2.is_lval()) {
2794 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2795 } else {
2796 cmpl(src1, as_Address(src2));
2797 }
2798 #endif // _LP64
2799 }
2800
2801 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2802 assert(src2.is_lval(), "not a mem-mem compare");
2803 #ifdef _LP64
2804 // moves src2's literal address
2805 movptr(rscratch1, src2);
2806 Assembler::cmpq(src1, rscratch1);
2807 #else
2808 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2809 #endif // _LP64
2810 }
2811
2812 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2813 if (reachable(adr)) {
2814 if (os::is_MP())
2815 lock();
2816 cmpxchgptr(reg, as_Address(adr));
2817 } else {
2818 lea(rscratch1, adr);
2819 if (os::is_MP())
2820 lock();
2821 cmpxchgptr(reg, Address(rscratch1, 0));
2822 }
2823 }
2824
2825 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2826 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2827 }
2828
2829 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2830 if (reachable(src)) {
2831 Assembler::comisd(dst, as_Address(src));
2832 } else {
2833 lea(rscratch1, src);
2834 Assembler::comisd(dst, Address(rscratch1, 0));
2835 }
2836 }
2837
2838 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2839 if (reachable(src)) {
2840 Assembler::comiss(dst, as_Address(src));
2841 } else {
2842 lea(rscratch1, src);
2843 Assembler::comiss(dst, Address(rscratch1, 0));
2844 }
2845 }
2846
2847
2848 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2849 Condition negated_cond = negate_condition(cond);
2850 Label L;
2851 jcc(negated_cond, L);
2852 pushf(); // Preserve flags
2853 atomic_incl(counter_addr);
2854 popf();
2855 bind(L);
2856 }
2857
2858 int MacroAssembler::corrected_idivl(Register reg) {
2859 // Full implementation of Java idiv and irem; checks for
2860 // special case as described in JVM spec., p.243 & p.271.
2861 // The function returns the (pc) offset of the idivl
2862 // instruction - may be needed for implicit exceptions.
2863 //
2864 // normal case special case
2865 //
2866 // input : rax,: dividend min_int
2867 // reg: divisor (may not be rax,/rdx) -1
2868 //
2869 // output: rax,: quotient (= rax, idiv reg) min_int
2870 // rdx: remainder (= rax, irem reg) 0
2871 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2872 const int min_int = 0x80000000;
2873 Label normal_case, special_case;
2874
2875 // check for special case
2876 cmpl(rax, min_int);
2877 jcc(Assembler::notEqual, normal_case);
2878 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2879 cmpl(reg, -1);
2880 jcc(Assembler::equal, special_case);
2881
2882 // handle normal case
2883 bind(normal_case);
2884 cdql();
2885 int idivl_offset = offset();
2886 idivl(reg);
2887
2888 // normal and special case exit
2889 bind(special_case);
2890
2891 return idivl_offset;
2892 }
2893
2894
2895
2896 void MacroAssembler::decrementl(Register reg, int value) {
2897 if (value == min_jint) {subl(reg, value) ; return; }
2898 if (value < 0) { incrementl(reg, -value); return; }
2899 if (value == 0) { ; return; }
2900 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2901 /* else */ { subl(reg, value) ; return; }
2902 }
2903
2904 void MacroAssembler::decrementl(Address dst, int value) {
2905 if (value == min_jint) {subl(dst, value) ; return; }
2906 if (value < 0) { incrementl(dst, -value); return; }
2907 if (value == 0) { ; return; }
2908 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2909 /* else */ { subl(dst, value) ; return; }
2910 }
2911
2912 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2913 assert (shift_value > 0, "illegal shift value");
2914 Label _is_positive;
2915 testl (reg, reg);
2916 jcc (Assembler::positive, _is_positive);
2917 int offset = (1 << shift_value) - 1 ;
2918
2919 if (offset == 1) {
2920 incrementl(reg);
2921 } else {
2922 addl(reg, offset);
2923 }
2924
2925 bind (_is_positive);
2926 sarl(reg, shift_value);
2927 }
2928
2929 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2930 if (reachable(src)) {
2931 Assembler::divsd(dst, as_Address(src));
2932 } else {
2933 lea(rscratch1, src);
2934 Assembler::divsd(dst, Address(rscratch1, 0));
2935 }
2936 }
2937
2938 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2939 if (reachable(src)) {
2940 Assembler::divss(dst, as_Address(src));
2941 } else {
2942 lea(rscratch1, src);
2943 Assembler::divss(dst, Address(rscratch1, 0));
2944 }
2945 }
2946
2947 // !defined(COMPILER2) is because of stupid core builds
2948 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2949 void MacroAssembler::empty_FPU_stack() {
2950 if (VM_Version::supports_mmx()) {
2951 emms();
2952 } else {
2953 for (int i = 8; i-- > 0; ) ffree(i);
2954 }
2955 }
2956 #endif // !LP64 || C1 || !C2
2957
2958
2959 // Defines obj, preserves var_size_in_bytes
2960 void MacroAssembler::eden_allocate(Register obj,
2961 Register var_size_in_bytes,
2962 int con_size_in_bytes,
2963 Register t1,
2964 Label& slow_case) {
2965 assert(obj == rax, "obj must be in rax, for cmpxchg");
2966 assert_different_registers(obj, var_size_in_bytes, t1);
2967 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2968 jmp(slow_case);
2969 } else {
2970 Register end = t1;
2971 Label retry;
2972 bind(retry);
2973 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2974 movptr(obj, heap_top);
2975 if (var_size_in_bytes == noreg) {
2976 lea(end, Address(obj, con_size_in_bytes));
2977 } else {
2978 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2979 }
2980 // if end < obj then we wrapped around => object too long => slow case
2981 cmpptr(end, obj);
2982 jcc(Assembler::below, slow_case);
2983 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2984 jcc(Assembler::above, slow_case);
2985 // Compare obj with the top addr, and if still equal, store the new top addr in
2986 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2987 // it otherwise. Use lock prefix for atomicity on MPs.
2988 locked_cmpxchgptr(end, heap_top);
2989 jcc(Assembler::notEqual, retry);
2990 }
2991 }
2992
2993 void MacroAssembler::enter() {
2994 push(rbp);
2995 mov(rbp, rsp);
2996 }
2997
2998 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2999 void MacroAssembler::fat_nop() {
3000 if (UseAddressNop) {
3001 addr_nop_5();
3002 } else {
3003 emit_int8(0x26); // es:
3004 emit_int8(0x2e); // cs:
3005 emit_int8(0x64); // fs:
3006 emit_int8(0x65); // gs:
3007 emit_int8((unsigned char)0x90);
3008 }
3009 }
3010
3011 void MacroAssembler::fcmp(Register tmp) {
3012 fcmp(tmp, 1, true, true);
3013 }
3014
3015 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3016 assert(!pop_right || pop_left, "usage error");
3017 if (VM_Version::supports_cmov()) {
3018 assert(tmp == noreg, "unneeded temp");
3019 if (pop_left) {
3020 fucomip(index);
3021 } else {
3022 fucomi(index);
3023 }
3024 if (pop_right) {
3025 fpop();
3026 }
3027 } else {
3028 assert(tmp != noreg, "need temp");
3029 if (pop_left) {
3030 if (pop_right) {
3031 fcompp();
3032 } else {
3033 fcomp(index);
3034 }
3035 } else {
3036 fcom(index);
3037 }
3038 // convert FPU condition into eflags condition via rax,
3039 save_rax(tmp);
3040 fwait(); fnstsw_ax();
3041 sahf();
3042 restore_rax(tmp);
3043 }
3044 // condition codes set as follows:
3045 //
3046 // CF (corresponds to C0) if x < y
3047 // PF (corresponds to C2) if unordered
3048 // ZF (corresponds to C3) if x = y
3049 }
3050
3051 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3052 fcmp2int(dst, unordered_is_less, 1, true, true);
3053 }
3054
3055 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3056 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3057 Label L;
3058 if (unordered_is_less) {
3059 movl(dst, -1);
3060 jcc(Assembler::parity, L);
3061 jcc(Assembler::below , L);
3062 movl(dst, 0);
3063 jcc(Assembler::equal , L);
3064 increment(dst);
3065 } else { // unordered is greater
3066 movl(dst, 1);
3067 jcc(Assembler::parity, L);
3068 jcc(Assembler::above , L);
3069 movl(dst, 0);
3070 jcc(Assembler::equal , L);
3071 decrementl(dst);
3072 }
3073 bind(L);
3074 }
3075
3076 void MacroAssembler::fld_d(AddressLiteral src) {
3077 fld_d(as_Address(src));
3078 }
3079
3080 void MacroAssembler::fld_s(AddressLiteral src) {
3081 fld_s(as_Address(src));
3082 }
3083
3084 void MacroAssembler::fld_x(AddressLiteral src) {
3085 Assembler::fld_x(as_Address(src));
3086 }
3087
3088 void MacroAssembler::fldcw(AddressLiteral src) {
3089 Assembler::fldcw(as_Address(src));
3090 }
3091
3092 void MacroAssembler::pow_exp_core_encoding() {
3093 // kills rax, rcx, rdx
3094 subptr(rsp,sizeof(jdouble));
3095 // computes 2^X. Stack: X ...
3096 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3097 // keep it on the thread's stack to compute 2^int(X) later
3098 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3099 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3100 fld_s(0); // Stack: X X ...
3101 frndint(); // Stack: int(X) X ...
3102 fsuba(1); // Stack: int(X) X-int(X) ...
3103 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3104 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3105 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3106 faddp(1); // Stack: 2^(X-int(X))
3107 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3108 // shift int(X)+1023 to exponent position.
3109 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3110 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3111 // values so detect them and set result to NaN.
3112 movl(rax,Address(rsp,0));
3113 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3114 addl(rax, 1023);
3115 movl(rdx,rax);
3116 shll(rax,20);
3117 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3118 addl(rdx,1);
3119 // Check that 1 < int(X)+1023+1 < 2048
3120 // in 3 steps:
3121 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3122 // 2- (int(X)+1023+1)&-2048 != 0
3123 // 3- (int(X)+1023+1)&-2048 != 1
3124 // Do 2- first because addl just updated the flags.
3125 cmov32(Assembler::equal,rax,rcx);
3126 cmpl(rdx,1);
3127 cmov32(Assembler::equal,rax,rcx);
3128 testl(rdx,rcx);
3129 cmov32(Assembler::notEqual,rax,rcx);
3130 movl(Address(rsp,4),rax);
3131 movl(Address(rsp,0),0);
3132 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3133 addptr(rsp,sizeof(jdouble));
3134 }
3135
3136 void MacroAssembler::increase_precision() {
3137 subptr(rsp, BytesPerWord);
3138 fnstcw(Address(rsp, 0));
3139 movl(rax, Address(rsp, 0));
3140 orl(rax, 0x300);
3141 push(rax);
3142 fldcw(Address(rsp, 0));
3143 pop(rax);
3144 }
3145
3146 void MacroAssembler::restore_precision() {
3147 fldcw(Address(rsp, 0));
3148 addptr(rsp, BytesPerWord);
3149 }
3150
3151 void MacroAssembler::fast_pow() {
3152 // computes X^Y = 2^(Y * log2(X))
3153 // if fast computation is not possible, result is NaN. Requires
3154 // fallback from user of this macro.
3155 // increase precision for intermediate steps of the computation
3156 BLOCK_COMMENT("fast_pow {");
3157 increase_precision();
3158 fyl2x(); // Stack: (Y*log2(X)) ...
3159 pow_exp_core_encoding(); // Stack: exp(X) ...
3160 restore_precision();
3161 BLOCK_COMMENT("} fast_pow");
3162 }
3163
3164 void MacroAssembler::fast_exp() {
3165 // computes exp(X) = 2^(X * log2(e))
3166 // if fast computation is not possible, result is NaN. Requires
3167 // fallback from user of this macro.
3168 // increase precision for intermediate steps of the computation
3169 increase_precision();
3170 fldl2e(); // Stack: log2(e) X ...
3171 fmulp(1); // Stack: (X*log2(e)) ...
3172 pow_exp_core_encoding(); // Stack: exp(X) ...
3173 restore_precision();
3174 }
3175
3176 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3177 // kills rax, rcx, rdx
3178 // pow and exp needs 2 extra registers on the fpu stack.
3179 Label slow_case, done;
3180 Register tmp = noreg;
3181 if (!VM_Version::supports_cmov()) {
3182 // fcmp needs a temporary so preserve rdx,
3183 tmp = rdx;
3184 }
3185 Register tmp2 = rax;
3186 Register tmp3 = rcx;
3187
3188 if (is_exp) {
3189 // Stack: X
3190 fld_s(0); // duplicate argument for runtime call. Stack: X X
3191 fast_exp(); // Stack: exp(X) X
3192 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3193 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3194 jcc(Assembler::parity, slow_case);
3195 // get rid of duplicate argument. Stack: exp(X)
3196 if (num_fpu_regs_in_use > 0) {
3197 fxch();
3198 fpop();
3199 } else {
3200 ffree(1);
3201 }
3202 jmp(done);
3203 } else {
3204 // Stack: X Y
3205 Label x_negative, y_not_2;
3206
3207 static double two = 2.0;
3208 ExternalAddress two_addr((address)&two);
3209
3210 // constant maybe too far on 64 bit
3211 lea(tmp2, two_addr);
3212 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3213 fcmp(tmp, 2, true, false); // Stack: X Y
3214 jcc(Assembler::parity, y_not_2);
3215 jcc(Assembler::notEqual, y_not_2);
3216
3217 fxch(); fpop(); // Stack: X
3218 fmul(0); // Stack: X*X
3219
3220 jmp(done);
3221
3222 bind(y_not_2);
3223
3224 fldz(); // Stack: 0 X Y
3225 fcmp(tmp, 1, true, false); // Stack: X Y
3226 jcc(Assembler::above, x_negative);
3227
3228 // X >= 0
3229
3230 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3231 fld_s(1); // Stack: X Y X Y
3232 fast_pow(); // Stack: X^Y X Y
3233 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3234 // X^Y not equal to itself: X^Y is NaN go to slow case.
3235 jcc(Assembler::parity, slow_case);
3236 // get rid of duplicate arguments. Stack: X^Y
3237 if (num_fpu_regs_in_use > 0) {
3238 fxch(); fpop();
3239 fxch(); fpop();
3240 } else {
3241 ffree(2);
3242 ffree(1);
3243 }
3244 jmp(done);
3245
3246 // X <= 0
3247 bind(x_negative);
3248
3249 fld_s(1); // Stack: Y X Y
3250 frndint(); // Stack: int(Y) X Y
3251 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3252 jcc(Assembler::notEqual, slow_case);
3253
3254 subptr(rsp, 8);
3255
3256 // For X^Y, when X < 0, Y has to be an integer and the final
3257 // result depends on whether it's odd or even. We just checked
3258 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3259 // integer to test its parity. If int(Y) is huge and doesn't fit
3260 // in the 64 bit integer range, the integer indefinite value will
3261 // end up in the gp registers. Huge numbers are all even, the
3262 // integer indefinite number is even so it's fine.
3263
3264 #ifdef ASSERT
3265 // Let's check we don't end up with an integer indefinite number
3266 // when not expected. First test for huge numbers: check whether
3267 // int(Y)+1 == int(Y) which is true for very large numbers and
3268 // those are all even. A 64 bit integer is guaranteed to not
3269 // overflow for numbers where y+1 != y (when precision is set to
3270 // double precision).
3271 Label y_not_huge;
3272
3273 fld1(); // Stack: 1 int(Y) X Y
3274 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3275
3276 #ifdef _LP64
3277 // trip to memory to force the precision down from double extended
3278 // precision
3279 fstp_d(Address(rsp, 0));
3280 fld_d(Address(rsp, 0));
3281 #endif
3282
3283 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3284 #endif
3285
3286 // move int(Y) as 64 bit integer to thread's stack
3287 fistp_d(Address(rsp,0)); // Stack: X Y
3288
3289 #ifdef ASSERT
3290 jcc(Assembler::notEqual, y_not_huge);
3291
3292 // Y is huge so we know it's even. It may not fit in a 64 bit
3293 // integer and we don't want the debug code below to see the
3294 // integer indefinite value so overwrite int(Y) on the thread's
3295 // stack with 0.
3296 movl(Address(rsp, 0), 0);
3297 movl(Address(rsp, 4), 0);
3298
3299 bind(y_not_huge);
3300 #endif
3301
3302 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3303 fld_s(1); // Stack: X Y X Y
3304 fabs(); // Stack: abs(X) Y X Y
3305 fast_pow(); // Stack: abs(X)^Y X Y
3306 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3307 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3308
3309 pop(tmp2);
3310 NOT_LP64(pop(tmp3));
3311 jcc(Assembler::parity, slow_case);
3312
3313 #ifdef ASSERT
3314 // Check that int(Y) is not integer indefinite value (int
3315 // overflow). Shouldn't happen because for values that would
3316 // overflow, 1+int(Y)==Y which was tested earlier.
3317 #ifndef _LP64
3318 {
3319 Label integer;
3320 testl(tmp2, tmp2);
3321 jcc(Assembler::notZero, integer);
3322 cmpl(tmp3, 0x80000000);
3323 jcc(Assembler::notZero, integer);
3324 STOP("integer indefinite value shouldn't be seen here");
3325 bind(integer);
3326 }
3327 #else
3328 {
3329 Label integer;
3330 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3331 shlq(tmp3, 1);
3332 jcc(Assembler::carryClear, integer);
3333 jcc(Assembler::notZero, integer);
3334 STOP("integer indefinite value shouldn't be seen here");
3335 bind(integer);
3336 }
3337 #endif
3338 #endif
3339
3340 // get rid of duplicate arguments. Stack: X^Y
3341 if (num_fpu_regs_in_use > 0) {
3342 fxch(); fpop();
3343 fxch(); fpop();
3344 } else {
3345 ffree(2);
3346 ffree(1);
3347 }
3348
3349 testl(tmp2, 1);
3350 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3351 // X <= 0, Y even: X^Y = -abs(X)^Y
3352
3353 fchs(); // Stack: -abs(X)^Y Y
3354 jmp(done);
3355 }
3356
3357 // slow case: runtime call
3358 bind(slow_case);
3359
3360 fpop(); // pop incorrect result or int(Y)
3361
3362 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3363 is_exp ? 1 : 2, num_fpu_regs_in_use);
3364
3365 // Come here with result in F-TOS
3366 bind(done);
3367 }
3368
3369 void MacroAssembler::fpop() {
3370 ffree();
3371 fincstp();
3372 }
3373
3374 void MacroAssembler::fremr(Register tmp) {
3375 save_rax(tmp);
3376 { Label L;
3377 bind(L);
3378 fprem();
3379 fwait(); fnstsw_ax();
3380 #ifdef _LP64
3381 testl(rax, 0x400);
3382 jcc(Assembler::notEqual, L);
3383 #else
3384 sahf();
3385 jcc(Assembler::parity, L);
3386 #endif // _LP64
3387 }
3388 restore_rax(tmp);
3389 // Result is in ST0.
3390 // Note: fxch & fpop to get rid of ST1
3391 // (otherwise FPU stack could overflow eventually)
3392 fxch(1);
3393 fpop();
3394 }
3395
3396
3397 void MacroAssembler::incrementl(AddressLiteral dst) {
3398 if (reachable(dst)) {
3399 incrementl(as_Address(dst));
3400 } else {
3401 lea(rscratch1, dst);
3402 incrementl(Address(rscratch1, 0));
3403 }
3404 }
3405
3406 void MacroAssembler::incrementl(ArrayAddress dst) {
3407 incrementl(as_Address(dst));
3408 }
3409
3410 void MacroAssembler::incrementl(Register reg, int value) {
3411 if (value == min_jint) {addl(reg, value) ; return; }
3412 if (value < 0) { decrementl(reg, -value); return; }
3413 if (value == 0) { ; return; }
3414 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3415 /* else */ { addl(reg, value) ; return; }
3416 }
3417
3418 void MacroAssembler::incrementl(Address dst, int value) {
3419 if (value == min_jint) {addl(dst, value) ; return; }
3420 if (value < 0) { decrementl(dst, -value); return; }
3421 if (value == 0) { ; return; }
3422 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3423 /* else */ { addl(dst, value) ; return; }
3424 }
3425
3426 void MacroAssembler::jump(AddressLiteral dst) {
3427 if (reachable(dst)) {
3428 jmp_literal(dst.target(), dst.rspec());
3429 } else {
3430 lea(rscratch1, dst);
3431 jmp(rscratch1);
3432 }
3433 }
3434
3435 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3436 if (reachable(dst)) {
3437 InstructionMark im(this);
3438 relocate(dst.reloc());
3439 const int short_size = 2;
3440 const int long_size = 6;
3441 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3442 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3443 // 0111 tttn #8-bit disp
3444 emit_int8(0x70 | cc);
3445 emit_int8((offs - short_size) & 0xFF);
3446 } else {
3447 // 0000 1111 1000 tttn #32-bit disp
3448 emit_int8(0x0F);
3449 emit_int8((unsigned char)(0x80 | cc));
3450 emit_int32(offs - long_size);
3451 }
3452 } else {
3453 #ifdef ASSERT
3454 warning("reversing conditional branch");
3455 #endif /* ASSERT */
3456 Label skip;
3457 jccb(reverse[cc], skip);
3458 lea(rscratch1, dst);
3459 Assembler::jmp(rscratch1);
3460 bind(skip);
3461 }
3462 }
3463
3464 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3465 if (reachable(src)) {
3466 Assembler::ldmxcsr(as_Address(src));
3467 } else {
3468 lea(rscratch1, src);
3469 Assembler::ldmxcsr(Address(rscratch1, 0));
3470 }
3471 }
3472
3473 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3474 int off;
3475 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3476 off = offset();
3477 movsbl(dst, src); // movsxb
3478 } else {
3479 off = load_unsigned_byte(dst, src);
3480 shll(dst, 24);
3481 sarl(dst, 24);
3482 }
3483 return off;
3484 }
3485
3486 // Note: load_signed_short used to be called load_signed_word.
3487 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3488 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3489 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3490 int MacroAssembler::load_signed_short(Register dst, Address src) {
3491 int off;
3492 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3493 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3494 // version but this is what 64bit has always done. This seems to imply
3495 // that users are only using 32bits worth.
3496 off = offset();
3497 movswl(dst, src); // movsxw
3498 } else {
3499 off = load_unsigned_short(dst, src);
3500 shll(dst, 16);
3501 sarl(dst, 16);
3502 }
3503 return off;
3504 }
3505
3506 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3507 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3508 // and "3.9 Partial Register Penalties", p. 22).
3509 int off;
3510 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3511 off = offset();
3512 movzbl(dst, src); // movzxb
3513 } else {
3514 xorl(dst, dst);
3515 off = offset();
3516 movb(dst, src);
3517 }
3518 return off;
3519 }
3520
3521 // Note: load_unsigned_short used to be called load_unsigned_word.
3522 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3523 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3524 // and "3.9 Partial Register Penalties", p. 22).
3525 int off;
3526 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3527 off = offset();
3528 movzwl(dst, src); // movzxw
3529 } else {
3530 xorl(dst, dst);
3531 off = offset();
3532 movw(dst, src);
3533 }
3534 return off;
3535 }
3536
3537 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3538 switch (size_in_bytes) {
3539 #ifndef _LP64
3540 case 8:
3541 assert(dst2 != noreg, "second dest register required");
3542 movl(dst, src);
3543 movl(dst2, src.plus_disp(BytesPerInt));
3544 break;
3545 #else
3546 case 8: movq(dst, src); break;
3547 #endif
3548 case 4: movl(dst, src); break;
3549 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3550 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3551 default: ShouldNotReachHere();
3552 }
3553 }
3554
3555 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3556 switch (size_in_bytes) {
3557 #ifndef _LP64
3558 case 8:
3559 assert(src2 != noreg, "second source register required");
3560 movl(dst, src);
3561 movl(dst.plus_disp(BytesPerInt), src2);
3562 break;
3563 #else
3564 case 8: movq(dst, src); break;
3565 #endif
3566 case 4: movl(dst, src); break;
3567 case 2: movw(dst, src); break;
3568 case 1: movb(dst, src); break;
3569 default: ShouldNotReachHere();
3570 }
3571 }
3572
3573 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3574 if (reachable(dst)) {
3575 movl(as_Address(dst), src);
3576 } else {
3577 lea(rscratch1, dst);
3578 movl(Address(rscratch1, 0), src);
3579 }
3580 }
3581
3582 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3583 if (reachable(src)) {
3584 movl(dst, as_Address(src));
3585 } else {
3586 lea(rscratch1, src);
3587 movl(dst, Address(rscratch1, 0));
3588 }
3589 }
3590
3591 // C++ bool manipulation
3592
3593 void MacroAssembler::movbool(Register dst, Address src) {
3594 if(sizeof(bool) == 1)
3595 movb(dst, src);
3596 else if(sizeof(bool) == 2)
3597 movw(dst, src);
3598 else if(sizeof(bool) == 4)
3599 movl(dst, src);
3600 else
3601 // unsupported
3602 ShouldNotReachHere();
3603 }
3604
3605 void MacroAssembler::movbool(Address dst, bool boolconst) {
3606 if(sizeof(bool) == 1)
3607 movb(dst, (int) boolconst);
3608 else if(sizeof(bool) == 2)
3609 movw(dst, (int) boolconst);
3610 else if(sizeof(bool) == 4)
3611 movl(dst, (int) boolconst);
3612 else
3613 // unsupported
3614 ShouldNotReachHere();
3615 }
3616
3617 void MacroAssembler::movbool(Address dst, Register src) {
3618 if(sizeof(bool) == 1)
3619 movb(dst, src);
3620 else if(sizeof(bool) == 2)
3621 movw(dst, src);
3622 else if(sizeof(bool) == 4)
3623 movl(dst, src);
3624 else
3625 // unsupported
3626 ShouldNotReachHere();
3627 }
3628
3629 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3630 movb(as_Address(dst), src);
3631 }
3632
3633 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3634 if (reachable(src)) {
3635 movdl(dst, as_Address(src));
3636 } else {
3637 lea(rscratch1, src);
3638 movdl(dst, Address(rscratch1, 0));
3639 }
3640 }
3641
3642 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3643 if (reachable(src)) {
3644 movq(dst, as_Address(src));
3645 } else {
3646 lea(rscratch1, src);
3647 movq(dst, Address(rscratch1, 0));
3648 }
3649 }
3650
3651 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3652 if (reachable(src)) {
3653 if (UseXmmLoadAndClearUpper) {
3654 movsd (dst, as_Address(src));
3655 } else {
3656 movlpd(dst, as_Address(src));
3657 }
3658 } else {
3659 lea(rscratch1, src);
3660 if (UseXmmLoadAndClearUpper) {
3661 movsd (dst, Address(rscratch1, 0));
3662 } else {
3663 movlpd(dst, Address(rscratch1, 0));
3664 }
3665 }
3666 }
3667
3668 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3669 if (reachable(src)) {
3670 movss(dst, as_Address(src));
3671 } else {
3672 lea(rscratch1, src);
3673 movss(dst, Address(rscratch1, 0));
3674 }
3675 }
3676
3677 void MacroAssembler::movptr(Register dst, Register src) {
3678 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3679 }
3680
3681 void MacroAssembler::movptr(Register dst, Address src) {
3682 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3683 }
3684
3685 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3686 void MacroAssembler::movptr(Register dst, intptr_t src) {
3687 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3688 }
3689
3690 void MacroAssembler::movptr(Address dst, Register src) {
3691 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3692 }
3693
3694 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3695 if (reachable(src)) {
3696 Assembler::movdqu(dst, as_Address(src));
3697 } else {
3698 lea(rscratch1, src);
3699 Assembler::movdqu(dst, Address(rscratch1, 0));
3700 }
3701 }
3702
3703 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3704 if (reachable(src)) {
3705 Assembler::movdqa(dst, as_Address(src));
3706 } else {
3707 lea(rscratch1, src);
3708 Assembler::movdqa(dst, Address(rscratch1, 0));
3709 }
3710 }
3711
3712 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3713 if (reachable(src)) {
3714 Assembler::movsd(dst, as_Address(src));
3715 } else {
3716 lea(rscratch1, src);
3717 Assembler::movsd(dst, Address(rscratch1, 0));
3718 }
3719 }
3720
3721 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3722 if (reachable(src)) {
3723 Assembler::movss(dst, as_Address(src));
3724 } else {
3725 lea(rscratch1, src);
3726 Assembler::movss(dst, Address(rscratch1, 0));
3727 }
3728 }
3729
3730 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3731 if (reachable(src)) {
3732 Assembler::mulsd(dst, as_Address(src));
3733 } else {
3734 lea(rscratch1, src);
3735 Assembler::mulsd(dst, Address(rscratch1, 0));
3736 }
3737 }
3738
3739 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3740 if (reachable(src)) {
3741 Assembler::mulss(dst, as_Address(src));
3742 } else {
3743 lea(rscratch1, src);
3744 Assembler::mulss(dst, Address(rscratch1, 0));
3745 }
3746 }
3747
3748 void MacroAssembler::null_check(Register reg, int offset) {
3749 if (needs_explicit_null_check(offset)) {
3750 // provoke OS NULL exception if reg = NULL by
3751 // accessing M[reg] w/o changing any (non-CC) registers
3752 // NOTE: cmpl is plenty here to provoke a segv
3753 cmpptr(rax, Address(reg, 0));
3754 // Note: should probably use testl(rax, Address(reg, 0));
3755 // may be shorter code (however, this version of
3756 // testl needs to be implemented first)
3757 } else {
3758 // nothing to do, (later) access of M[reg + offset]
3759 // will provoke OS NULL exception if reg = NULL
3760 }
3761 }
3762
3763 void MacroAssembler::os_breakpoint() {
3764 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3765 // (e.g., MSVC can't call ps() otherwise)
3766 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3767 }
3768
3769 void MacroAssembler::pop_CPU_state() {
3770 pop_FPU_state();
3771 pop_IU_state();
3772 }
3773
3774 void MacroAssembler::pop_FPU_state() {
3775 NOT_LP64(frstor(Address(rsp, 0));)
3776 LP64_ONLY(fxrstor(Address(rsp, 0));)
3777 addptr(rsp, FPUStateSizeInWords * wordSize);
3778 }
3779
3780 void MacroAssembler::pop_IU_state() {
3781 popa();
3782 LP64_ONLY(addq(rsp, 8));
3783 popf();
3784 }
3785
3786 // Save Integer and Float state
3787 // Warning: Stack must be 16 byte aligned (64bit)
3788 void MacroAssembler::push_CPU_state() {
3789 push_IU_state();
3790 push_FPU_state();
3791 }
3792
3793 void MacroAssembler::push_FPU_state() {
3794 subptr(rsp, FPUStateSizeInWords * wordSize);
3795 #ifndef _LP64
3796 fnsave(Address(rsp, 0));
3797 fwait();
3798 #else
3799 fxsave(Address(rsp, 0));
3800 #endif // LP64
3801 }
3802
3803 void MacroAssembler::push_IU_state() {
3804 // Push flags first because pusha kills them
3805 pushf();
3806 // Make sure rsp stays 16-byte aligned
3807 LP64_ONLY(subq(rsp, 8));
3808 pusha();
3809 }
3810
3811 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) {
3812 // determine java_thread register
3813 if (!java_thread->is_valid()) {
3814 java_thread = rdi;
3815 get_thread(java_thread);
3816 }
3817 // we must set sp to zero to clear frame
3818 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3819 if (clear_fp) {
3820 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3821 }
3822
3823 // Always clear the pc because it could have been set by make_walkable()
3824 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3825
3826 }
3827
3828 void MacroAssembler::restore_rax(Register tmp) {
3829 if (tmp == noreg) pop(rax);
3830 else if (tmp != rax) mov(rax, tmp);
3831 }
3832
3833 void MacroAssembler::round_to(Register reg, int modulus) {
3834 addptr(reg, modulus - 1);
3835 andptr(reg, -modulus);
3836 }
3837
3838 void MacroAssembler::save_rax(Register tmp) {
3839 if (tmp == noreg) push(rax);
3840 else if (tmp != rax) mov(tmp, rax);
3841 }
3842
3843 // Write serialization page so VM thread can do a pseudo remote membar.
3844 // We use the current thread pointer to calculate a thread specific
3845 // offset to write to within the page. This minimizes bus traffic
3846 // due to cache line collision.
3847 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3848 movl(tmp, thread);
3849 shrl(tmp, os::get_serialize_page_shift_count());
3850 andl(tmp, (os::vm_page_size() - sizeof(int)));
3851
3852 Address index(noreg, tmp, Address::times_1);
3853 ExternalAddress page(os::get_memory_serialize_page());
3854
3855 // Size of store must match masking code above
3856 movl(as_Address(ArrayAddress(page, index)), tmp);
3857 }
3858
3859 // Special Shenandoah CAS implementation that handles false negatives
3860 // due to concurrent evacuation.
3861 #if INCLUDE_ALL_GCS
3862 #ifndef _LP64
3863 void MacroAssembler::cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
3864 bool exchange,
3865 Register tmp1, Register tmp2) {
3866 // Shenandoah has no 32-bit version for this.
3867 Unimplemented();
3868 }
3869 #else
3870 void MacroAssembler::cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
3871 bool exchange,
3872 Register tmp1, Register tmp2) {
3873 assert (UseShenandoahGC && ShenandoahCASBarrier, "Should only be used with Shenandoah");
3874 assert(oldval == rax, "must be in rax for implicit use in cmpxchg");
3875
3876 Label retry, done;
3877
3878 // Remember oldval for retry logic below
3879 if (UseCompressedOops) {
3880 movl(tmp1, oldval);
3881 } else {
3882 movptr(tmp1, oldval);
3883 }
3884
3885 // Step 1. Try to CAS with given arguments. If successful, then we are done,
3886 // and can safely return.
3887 if (os::is_MP()) lock();
3888 if (UseCompressedOops) {
3889 cmpxchgl(newval, addr);
3890 } else {
3891 cmpxchgptr(newval, addr);
3892 }
3893 jcc(Assembler::equal, done, true);
3894
3895 // Step 2. CAS had failed. This may be a false negative.
3896 //
3897 // The trouble comes when we compare the to-space pointer with the from-space
3898 // pointer to the same object. To resolve this, it will suffice to read both
3899 // oldval and the value from memory through the read barriers -- this will give
3900 // both to-space pointers. If they mismatch, then it was a legitimate failure.
3901 //
3902 if (UseCompressedOops) {
3903 decode_heap_oop(tmp1);
3904 }
3905 oopDesc::bs()->interpreter_read_barrier(this, tmp1);
3906
3907 if (UseCompressedOops) {
3908 movl(tmp2, oldval);
3909 decode_heap_oop(tmp2);
3910 } else {
3911 movptr(tmp2, oldval);
3912 }
3913 oopDesc::bs()->interpreter_read_barrier(this, tmp2);
3914
3915 cmpptr(tmp1, tmp2);
3916 jcc(Assembler::notEqual, done, true);
3917
3918 // Step 3. Try to CAS again with resolved to-space pointers.
3919 //
3920 // Corner case: it may happen that somebody stored the from-space pointer
3921 // to memory while we were preparing for retry. Therefore, we can fail again
3922 // on retry, and so need to do this in loop, always re-reading the failure
3923 // witness through the read barrier.
3924 bind(retry);
3925 if (os::is_MP()) lock();
3926 if (UseCompressedOops) {
3927 cmpxchgl(newval, addr);
3928 } else {
3929 cmpxchgptr(newval, addr);
3930 }
3931 jcc(Assembler::equal, done, true);
3932
3933 if (UseCompressedOops) {
3934 movl(tmp2, oldval);
3935 decode_heap_oop(tmp2);
3936 } else {
3937 movptr(tmp2, oldval);
3938 }
3939 oopDesc::bs()->interpreter_read_barrier(this, tmp2);
3940
3941 cmpptr(tmp1, tmp2);
3942 jcc(Assembler::equal, retry, true);
3943
3944 // Step 4. If we need a boolean result out of CAS, check the flag again,
3945 // and promote the result. Note that we handle the flag from both the CAS
3946 // itself and from the retry loop.
3947 bind(done);
3948 if (!exchange) {
3949 setb(Assembler::equal, res);
3950 movzbl(res, res);
3951 }
3952 }
3953 #endif // INCLUDE_ALL_GCS
3954 #endif // LP64
3955
3956 // Calls to C land
3957 //
3958 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3959 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3960 // has to be reset to 0. This is required to allow proper stack traversal.
3961 void MacroAssembler::set_last_Java_frame(Register java_thread,
3962 Register last_java_sp,
3963 Register last_java_fp,
3964 address last_java_pc) {
3965 // determine java_thread register
3966 if (!java_thread->is_valid()) {
3967 java_thread = rdi;
3968 get_thread(java_thread);
3969 }
3970 // determine last_java_sp register
3971 if (!last_java_sp->is_valid()) {
3972 last_java_sp = rsp;
3973 }
3974
3975 // last_java_fp is optional
3976
3977 if (last_java_fp->is_valid()) {
3978 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3979 }
3980
3981 // last_java_pc is optional
3982
3983 if (last_java_pc != NULL) {
3984 lea(Address(java_thread,
3985 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3986 InternalAddress(last_java_pc));
3987
3988 }
3989 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3990 }
3991
3992 void MacroAssembler::shlptr(Register dst, int imm8) {
3993 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3994 }
3995
3996 void MacroAssembler::shrptr(Register dst, int imm8) {
3997 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3998 }
3999
4000 void MacroAssembler::sign_extend_byte(Register reg) {
4001 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
4002 movsbl(reg, reg); // movsxb
4003 } else {
4004 shll(reg, 24);
4005 sarl(reg, 24);
4006 }
4007 }
4008
4009 void MacroAssembler::sign_extend_short(Register reg) {
4010 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
4011 movswl(reg, reg); // movsxw
4012 } else {
4013 shll(reg, 16);
4014 sarl(reg, 16);
4015 }
4016 }
4017
4018 void MacroAssembler::testl(Register dst, AddressLiteral src) {
4019 assert(reachable(src), "Address should be reachable");
4020 testl(dst, as_Address(src));
4021 }
4022
4023 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4024 if (reachable(src)) {
4025 Assembler::sqrtsd(dst, as_Address(src));
4026 } else {
4027 lea(rscratch1, src);
4028 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4029 }
4030 }
4031
4032 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4033 if (reachable(src)) {
4034 Assembler::sqrtss(dst, as_Address(src));
4035 } else {
4036 lea(rscratch1, src);
4037 Assembler::sqrtss(dst, Address(rscratch1, 0));
4038 }
4039 }
4040
4041 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4042 if (reachable(src)) {
4043 Assembler::subsd(dst, as_Address(src));
4044 } else {
4045 lea(rscratch1, src);
4046 Assembler::subsd(dst, Address(rscratch1, 0));
4047 }
4048 }
4049
4050 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4051 if (reachable(src)) {
4052 Assembler::subss(dst, as_Address(src));
4053 } else {
4054 lea(rscratch1, src);
4055 Assembler::subss(dst, Address(rscratch1, 0));
4056 }
4057 }
4058
4059 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4060 if (reachable(src)) {
4061 Assembler::ucomisd(dst, as_Address(src));
4062 } else {
4063 lea(rscratch1, src);
4064 Assembler::ucomisd(dst, Address(rscratch1, 0));
4065 }
4066 }
4067
4068 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4069 if (reachable(src)) {
4070 Assembler::ucomiss(dst, as_Address(src));
4071 } else {
4072 lea(rscratch1, src);
4073 Assembler::ucomiss(dst, Address(rscratch1, 0));
4074 }
4075 }
4076
4077 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4078 // Used in sign-bit flipping with aligned address.
4079 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4080 if (reachable(src)) {
4081 Assembler::xorpd(dst, as_Address(src));
4082 } else {
4083 lea(rscratch1, src);
4084 Assembler::xorpd(dst, Address(rscratch1, 0));
4085 }
4086 }
4087
4088 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4089 // Used in sign-bit flipping with aligned address.
4090 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4091 if (reachable(src)) {
4092 Assembler::xorps(dst, as_Address(src));
4093 } else {
4094 lea(rscratch1, src);
4095 Assembler::xorps(dst, Address(rscratch1, 0));
4096 }
4097 }
4098
4099 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4100 // Used in sign-bit flipping with aligned address.
4101 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4102 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4103 if (reachable(src)) {
4104 Assembler::pshufb(dst, as_Address(src));
4105 } else {
4106 lea(rscratch1, src);
4107 Assembler::pshufb(dst, Address(rscratch1, 0));
4108 }
4109 }
4110
4111 // AVX 3-operands instructions
4112
4113 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4114 if (reachable(src)) {
4115 vaddsd(dst, nds, as_Address(src));
4116 } else {
4117 lea(rscratch1, src);
4118 vaddsd(dst, nds, Address(rscratch1, 0));
4119 }
4120 }
4121
4122 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4123 if (reachable(src)) {
4124 vaddss(dst, nds, as_Address(src));
4125 } else {
4126 lea(rscratch1, src);
4127 vaddss(dst, nds, Address(rscratch1, 0));
4128 }
4129 }
4130
4131 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4132 if (reachable(src)) {
4133 vandpd(dst, nds, as_Address(src), vector256);
4134 } else {
4135 lea(rscratch1, src);
4136 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4137 }
4138 }
4139
4140 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4141 if (reachable(src)) {
4142 vandps(dst, nds, as_Address(src), vector256);
4143 } else {
4144 lea(rscratch1, src);
4145 vandps(dst, nds, Address(rscratch1, 0), vector256);
4146 }
4147 }
4148
4149 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4150 if (reachable(src)) {
4151 vdivsd(dst, nds, as_Address(src));
4152 } else {
4153 lea(rscratch1, src);
4154 vdivsd(dst, nds, Address(rscratch1, 0));
4155 }
4156 }
4157
4158 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4159 if (reachable(src)) {
4160 vdivss(dst, nds, as_Address(src));
4161 } else {
4162 lea(rscratch1, src);
4163 vdivss(dst, nds, Address(rscratch1, 0));
4164 }
4165 }
4166
4167 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4168 if (reachable(src)) {
4169 vmulsd(dst, nds, as_Address(src));
4170 } else {
4171 lea(rscratch1, src);
4172 vmulsd(dst, nds, Address(rscratch1, 0));
4173 }
4174 }
4175
4176 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4177 if (reachable(src)) {
4178 vmulss(dst, nds, as_Address(src));
4179 } else {
4180 lea(rscratch1, src);
4181 vmulss(dst, nds, Address(rscratch1, 0));
4182 }
4183 }
4184
4185 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4186 if (reachable(src)) {
4187 vsubsd(dst, nds, as_Address(src));
4188 } else {
4189 lea(rscratch1, src);
4190 vsubsd(dst, nds, Address(rscratch1, 0));
4191 }
4192 }
4193
4194 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4195 if (reachable(src)) {
4196 vsubss(dst, nds, as_Address(src));
4197 } else {
4198 lea(rscratch1, src);
4199 vsubss(dst, nds, Address(rscratch1, 0));
4200 }
4201 }
4202
4203 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4204 if (reachable(src)) {
4205 vxorpd(dst, nds, as_Address(src), vector256);
4206 } else {
4207 lea(rscratch1, src);
4208 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4209 }
4210 }
4211
4212 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4213 if (reachable(src)) {
4214 vxorps(dst, nds, as_Address(src), vector256);
4215 } else {
4216 lea(rscratch1, src);
4217 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4218 }
4219 }
4220
4221
4222 //////////////////////////////////////////////////////////////////////////////////
4223 #if INCLUDE_ALL_GCS
4224
4225 void MacroAssembler::g1_write_barrier_pre(Register obj,
4226 Register pre_val,
4227 Register thread,
4228 Register tmp,
4229 bool tosca_live,
4230 bool expand_call) {
4231
4232 // If expand_call is true then we expand the call_VM_leaf macro
4233 // directly to skip generating the check by
4234 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4235
4236 #ifdef _LP64
4237 assert(thread == r15_thread, "must be");
4238 #endif // _LP64
4239
4240 Label done;
4241 Label runtime;
4242
4243 assert(pre_val != noreg, "check this code");
4244
4245 if (obj != noreg) {
4246 assert_different_registers(obj, pre_val, tmp);
4247 assert(pre_val != rax, "check this code");
4248 }
4249
4250 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4251 PtrQueue::byte_offset_of_active()));
4252 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4253 PtrQueue::byte_offset_of_index()));
4254 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4255 PtrQueue::byte_offset_of_buf()));
4256
4257 if (UseShenandoahGC) {
4258 Address gc_state(thread, in_bytes(JavaThread::gc_state_offset()));
4259 testb(gc_state, ShenandoahHeap::MARKING);
4260 jcc(Assembler::zero, done);
4261 } else {
4262 assert(UseG1GC, "Should be");
4263 // Is marking active?
4264 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4265 cmpl(in_progress, 0);
4266 } else {
4267 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4268 cmpb(in_progress, 0);
4269 }
4270 jcc(Assembler::equal, done);
4271 }
4272
4273 // Do we need to load the previous value?
4274 if (obj != noreg) {
4275 load_heap_oop(pre_val, Address(obj, 0));
4276 }
4277
4278 // Is the previous value null?
4279 cmpptr(pre_val, (int32_t) NULL_WORD);
4280 jcc(Assembler::equal, done);
4281
4282 // Can we store original value in the thread's buffer?
4283 // Is index == 0?
4284 // (The index field is typed as size_t.)
4285
4286 movptr(tmp, index); // tmp := *index_adr
4287 cmpptr(tmp, 0); // tmp == 0?
4288 jcc(Assembler::equal, runtime); // If yes, goto runtime
4289
4290 subptr(tmp, wordSize); // tmp := tmp - wordSize
4291 movptr(index, tmp); // *index_adr := tmp
4292 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4293
4294 // Record the previous value
4295 movptr(Address(tmp, 0), pre_val);
4296 jmp(done);
4297
4298 bind(runtime);
4299 // save the live input values
4300 if(tosca_live) push(rax);
4301
4302 if (obj != noreg && obj != rax)
4303 push(obj);
4304
4305 if (pre_val != rax)
4306 push(pre_val);
4307
4308 // Calling the runtime using the regular call_VM_leaf mechanism generates
4309 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4310 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4311 //
4312 // If we care generating the pre-barrier without a frame (e.g. in the
4313 // intrinsified Reference.get() routine) then ebp might be pointing to
4314 // the caller frame and so this check will most likely fail at runtime.
4315 //
4316 // Expanding the call directly bypasses the generation of the check.
4317 // So when we do not have have a full interpreter frame on the stack
4318 // expand_call should be passed true.
4319
4320 NOT_LP64( push(thread); )
4321
4322 if (expand_call) {
4323 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4324 pass_arg1(this, thread);
4325 pass_arg0(this, pre_val);
4326 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4327 } else {
4328 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4329 }
4330
4331 NOT_LP64( pop(thread); )
4332
4333 // save the live input values
4334 if (pre_val != rax)
4335 pop(pre_val);
4336
4337 if (obj != noreg && obj != rax)
4338 pop(obj);
4339
4340 if(tosca_live) pop(rax);
4341
4342 bind(done);
4343 }
4344
4345 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4346 Register new_val,
4347 Register thread,
4348 Register tmp,
4349 Register tmp2) {
4350 #ifdef _LP64
4351 assert(thread == r15_thread, "must be");
4352 #endif // _LP64
4353
4354 if (UseShenandoahGC) {
4355 // No need for this in Shenandoah.
4356 return;
4357 }
4358
4359 assert(UseG1GC, "expect G1 GC");
4360
4361 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4362 PtrQueue::byte_offset_of_index()));
4363 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4364 PtrQueue::byte_offset_of_buf()));
4365
4366 BarrierSet* bs = Universe::heap()->barrier_set();
4367 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4368 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4369
4370 Label done;
4371 Label runtime;
4372
4373 // Does store cross heap regions?
4374
4375 movptr(tmp, store_addr);
4376 xorptr(tmp, new_val);
4377 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4378 jcc(Assembler::equal, done);
4379
4380 // crosses regions, storing NULL?
4381
4382 cmpptr(new_val, (int32_t) NULL_WORD);
4383 jcc(Assembler::equal, done);
4384
4385 // storing region crossing non-NULL, is card already dirty?
4386
4387 const Register card_addr = tmp;
4388 const Register cardtable = tmp2;
4389
4390 movptr(card_addr, store_addr);
4391 shrptr(card_addr, CardTableModRefBS::card_shift);
4392 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4393 // a valid address and therefore is not properly handled by the relocation code.
4394 movptr(cardtable, (intptr_t)ct->byte_map_base);
4395 addptr(card_addr, cardtable);
4396
4397 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4398 jcc(Assembler::equal, done);
4399
4400 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4401 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4402 jcc(Assembler::equal, done);
4403
4404
4405 // storing a region crossing, non-NULL oop, card is clean.
4406 // dirty card and log.
4407
4408 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4409
4410 cmpl(queue_index, 0);
4411 jcc(Assembler::equal, runtime);
4412 subl(queue_index, wordSize);
4413 movptr(tmp2, buffer);
4414 #ifdef _LP64
4415 movslq(rscratch1, queue_index);
4416 addq(tmp2, rscratch1);
4417 movq(Address(tmp2, 0), card_addr);
4418 #else
4419 addl(tmp2, queue_index);
4420 movl(Address(tmp2, 0), card_addr);
4421 #endif
4422 jmp(done);
4423
4424 bind(runtime);
4425 // save the live input values
4426 push(store_addr);
4427 push(new_val);
4428 #ifdef _LP64
4429 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4430 #else
4431 push(thread);
4432 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4433 pop(thread);
4434 #endif
4435 pop(new_val);
4436 pop(store_addr);
4437
4438 bind(done);
4439 }
4440
4441 #ifndef _LP64
4442 void MacroAssembler::shenandoah_write_barrier(Register dst) {
4443 Unimplemented();
4444 }
4445 #else
4446 void MacroAssembler::shenandoah_write_barrier(Register dst) {
4447 assert(UseShenandoahGC && ShenandoahWriteBarrier, "Should be enabled");
4448
4449 Label done;
4450
4451 Address gc_state(r15_thread, in_bytes(JavaThread::gc_state_offset()));
4452
4453 // Check for heap stability
4454 testb(gc_state, ShenandoahHeap::HAS_FORWARDED | ShenandoahHeap::EVACUATION);
4455 jccb(Assembler::zero, done);
4456
4457 // Heap is unstable, need to perform the read-barrier even if WB is inactive
4458 if (ShenandoahWriteBarrierRB) {
4459 movptr(dst, Address(dst, BrooksPointer::byte_offset()));
4460 }
4461
4462 // Check for evacuation-in-progress and jump to WB slow-path if needed
4463 testb(gc_state, ShenandoahHeap::EVACUATION);
4464 jccb(Assembler::zero, done);
4465
4466 if (dst != rax) {
4467 xchgptr(dst, rax); // Move obj into rax and save rax into obj.
4468 }
4469
4470 assert(StubRoutines::x86::shenandoah_wb() != NULL, "need write barrier stub");
4471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::shenandoah_wb())));
4472
4473 if (dst != rax) {
4474 xchgptr(rax, dst); // Swap back obj with rax.
4475 }
4476
4477 bind(done);
4478 }
4479 #endif // _LP64
4480
4481 #endif // INCLUDE_ALL_GCS
4482 //////////////////////////////////////////////////////////////////////////////////
4483
4484
4485 void MacroAssembler::store_check(Register obj) {
4486 // Does a store check for the oop in register obj. The content of
4487 // register obj is destroyed afterwards.
4488 store_check_part_1(obj);
4489 store_check_part_2(obj);
4490 }
4491
4492 void MacroAssembler::store_check(Register obj, Address dst) {
4493 store_check(obj);
4494 }
4495
4496
4497 // split the store check operation so that other instructions can be scheduled inbetween
4498 void MacroAssembler::store_check_part_1(Register obj) {
4499 BarrierSet* bs = Universe::heap()->barrier_set();
4500 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4501 shrptr(obj, CardTableModRefBS::card_shift);
4502 }
4503
4504 void MacroAssembler::store_check_part_2(Register obj) {
4505 BarrierSet* bs = Universe::heap()->barrier_set();
4506 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4507 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4508 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4509
4510 // The calculation for byte_map_base is as follows:
4511 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4512 // So this essentially converts an address to a displacement and it will
4513 // never need to be relocated. On 64bit however the value may be too
4514 // large for a 32bit displacement.
4515 intptr_t disp = (intptr_t) ct->byte_map_base;
4516 if (is_simm32(disp)) {
4517 Address cardtable(noreg, obj, Address::times_1, disp);
4518 movb(cardtable, 0);
4519 } else {
4520 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4521 // displacement and done in a single instruction given favorable mapping and a
4522 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4523 // entry and that entry is not properly handled by the relocation code.
4524 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4525 Address index(noreg, obj, Address::times_1);
4526 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4527 }
4528 }
4529
4530 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4531 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4532 }
4533
4534 // Force generation of a 4 byte immediate value even if it fits into 8bit
4535 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4536 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4537 }
4538
4539 void MacroAssembler::subptr(Register dst, Register src) {
4540 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4541 }
4542
4543 // C++ bool manipulation
4544 void MacroAssembler::testbool(Register dst) {
4545 if(sizeof(bool) == 1)
4546 testb(dst, 0xff);
4547 else if(sizeof(bool) == 2) {
4548 // testw implementation needed for two byte bools
4549 ShouldNotReachHere();
4550 } else if(sizeof(bool) == 4)
4551 testl(dst, dst);
4552 else
4553 // unsupported
4554 ShouldNotReachHere();
4555 }
4556
4557 void MacroAssembler::testptr(Register dst, Register src) {
4558 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4559 }
4560
4561 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4562 void MacroAssembler::tlab_allocate(Register obj,
4563 Register var_size_in_bytes,
4564 int con_size_in_bytes,
4565 Register t1,
4566 Register t2,
4567 Label& slow_case) {
4568 assert_different_registers(obj, t1, t2);
4569 assert_different_registers(obj, var_size_in_bytes, t1);
4570 Register end = t2;
4571 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4572
4573 verify_tlab();
4574
4575 NOT_LP64(get_thread(thread));
4576
4577 uint oop_extra_words = Universe::heap()->oop_extra_words();
4578
4579 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4580 if (var_size_in_bytes == noreg) {
4581 lea(end, Address(obj, con_size_in_bytes + oop_extra_words * HeapWordSize));
4582 } else {
4583 if (oop_extra_words > 0) {
4584 addptr(var_size_in_bytes, oop_extra_words * HeapWordSize);
4585 }
4586 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4587 }
4588 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4589 jcc(Assembler::above, slow_case);
4590
4591 // update the tlab top pointer
4592 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4593
4594 Universe::heap()->compile_prepare_oop(this, obj);
4595
4596 // recover var_size_in_bytes if necessary
4597 if (var_size_in_bytes == end) {
4598 subptr(var_size_in_bytes, obj);
4599 }
4600 verify_tlab();
4601 }
4602
4603 // Preserves rbx, and rdx.
4604 Register MacroAssembler::tlab_refill(Label& retry,
4605 Label& try_eden,
4606 Label& slow_case) {
4607 Register top = rax;
4608 Register t1 = rcx;
4609 Register t2 = rsi;
4610 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4611 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4612 Label do_refill, discard_tlab;
4613
4614 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4615 // No allocation in the shared eden.
4616 jmp(slow_case);
4617 }
4618
4619 NOT_LP64(get_thread(thread_reg));
4620
4621 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4622 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4623
4624 // calculate amount of free space
4625 subptr(t1, top);
4626 shrptr(t1, LogHeapWordSize);
4627
4628 // Retain tlab and allocate object in shared space if
4629 // the amount free in the tlab is too large to discard.
4630 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4631 jcc(Assembler::lessEqual, discard_tlab);
4632
4633 // Retain
4634 // %%% yuck as movptr...
4635 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4636 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4637 if (TLABStats) {
4638 // increment number of slow_allocations
4639 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4640 }
4641 jmp(try_eden);
4642
4643 bind(discard_tlab);
4644 if (TLABStats) {
4645 // increment number of refills
4646 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4647 // accumulate wastage -- t1 is amount free in tlab
4648 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4649 }
4650
4651 // if tlab is currently allocated (top or end != null) then
4652 // fill [top, end + alignment_reserve) with array object
4653 testptr(top, top);
4654 jcc(Assembler::zero, do_refill);
4655
4656 // set up the mark word
4657 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4658 // set the length to the remaining space
4659 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4660 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4661 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4662 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4663 // set klass to intArrayKlass
4664 // dubious reloc why not an oop reloc?
4665 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4666 // store klass last. concurrent gcs assumes klass length is valid if
4667 // klass field is not null.
4668 store_klass(top, t1);
4669
4670 movptr(t1, top);
4671 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4672 incr_allocated_bytes(thread_reg, t1, 0);
4673
4674 // refill the tlab with an eden allocation
4675 bind(do_refill);
4676 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4677 shlptr(t1, LogHeapWordSize);
4678 // allocate new tlab, address returned in top
4679 eden_allocate(top, t1, 0, t2, slow_case);
4680
4681 // Check that t1 was preserved in eden_allocate.
4682 #ifdef ASSERT
4683 if (UseTLAB) {
4684 Label ok;
4685 Register tsize = rsi;
4686 assert_different_registers(tsize, thread_reg, t1);
4687 push(tsize);
4688 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4689 shlptr(tsize, LogHeapWordSize);
4690 cmpptr(t1, tsize);
4691 jcc(Assembler::equal, ok);
4692 STOP("assert(t1 != tlab size)");
4693 should_not_reach_here();
4694
4695 bind(ok);
4696 pop(tsize);
4697 }
4698 #endif
4699 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4700 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4701 addptr(top, t1);
4702 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4703 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4704 verify_tlab();
4705 jmp(retry);
4706
4707 return thread_reg; // for use by caller
4708 }
4709
4710 void MacroAssembler::incr_allocated_bytes(Register thread,
4711 Register var_size_in_bytes,
4712 int con_size_in_bytes,
4713 Register t1) {
4714 if (!thread->is_valid()) {
4715 #ifdef _LP64
4716 thread = r15_thread;
4717 #else
4718 assert(t1->is_valid(), "need temp reg");
4719 thread = t1;
4720 get_thread(thread);
4721 #endif
4722 }
4723
4724 #ifdef _LP64
4725 if (var_size_in_bytes->is_valid()) {
4726 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4727 } else {
4728 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4729 }
4730 #else
4731 if (var_size_in_bytes->is_valid()) {
4732 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4733 } else {
4734 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4735 }
4736 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4737 #endif
4738 }
4739
4740 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4741 pusha();
4742
4743 save_vector_registers();
4744
4745 // if we are coming from c1, xmm registers may be live
4746
4747 // Preserve registers across runtime call
4748 int incoming_argument_and_return_value_offset = -1;
4749 if (num_fpu_regs_in_use > 1) {
4750 // Must preserve all other FPU regs (could alternatively convert
4751 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4752 // FPU state, but can not trust C compiler)
4753 NEEDS_CLEANUP;
4754 // NOTE that in this case we also push the incoming argument(s) to
4755 // the stack and restore it later; we also use this stack slot to
4756 // hold the return value from dsin, dcos etc.
4757 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4758 subptr(rsp, sizeof(jdouble));
4759 fstp_d(Address(rsp, 0));
4760 }
4761 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4762 for (int i = nb_args-1; i >= 0; i--) {
4763 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4764 }
4765 }
4766
4767 subptr(rsp, nb_args*sizeof(jdouble));
4768 for (int i = 0; i < nb_args; i++) {
4769 fstp_d(Address(rsp, i*sizeof(jdouble)));
4770 }
4771
4772 #ifdef _LP64
4773 if (nb_args > 0) {
4774 movdbl(xmm0, Address(rsp, 0));
4775 }
4776 if (nb_args > 1) {
4777 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4778 }
4779 assert(nb_args <= 2, "unsupported number of args");
4780 #endif // _LP64
4781
4782 // NOTE: we must not use call_VM_leaf here because that requires a
4783 // complete interpreter frame in debug mode -- same bug as 4387334
4784 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4785 // do proper 64bit abi
4786
4787 NEEDS_CLEANUP;
4788 // Need to add stack banging before this runtime call if it needs to
4789 // be taken; however, there is no generic stack banging routine at
4790 // the MacroAssembler level
4791
4792 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4793
4794 #ifdef _LP64
4795 movsd(Address(rsp, 0), xmm0);
4796 fld_d(Address(rsp, 0));
4797 #endif // _LP64
4798 addptr(rsp, sizeof(jdouble) * nb_args);
4799 if (num_fpu_regs_in_use > 1) {
4800 // Must save return value to stack and then restore entire FPU
4801 // stack except incoming arguments
4802 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4803 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4804 fld_d(Address(rsp, 0));
4805 addptr(rsp, sizeof(jdouble));
4806 }
4807 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4808 addptr(rsp, sizeof(jdouble) * nb_args);
4809 }
4810
4811 restore_vector_registers();
4812 popa();
4813 }
4814
4815 void MacroAssembler::save_vector_registers() {
4816 int off = 0;
4817 if (UseSSE == 1) {
4818 subptr(rsp, sizeof(jdouble)*8);
4819 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4820 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4821 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4822 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4823 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4824 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4825 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4826 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4827 } else if (UseSSE >= 2) {
4828 #ifdef COMPILER2
4829 if (MaxVectorSize > 16) {
4830 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4831 // Save upper half of YMM registes
4832 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4833 vextractf128h(Address(rsp, 0),xmm0);
4834 vextractf128h(Address(rsp, 16),xmm1);
4835 vextractf128h(Address(rsp, 32),xmm2);
4836 vextractf128h(Address(rsp, 48),xmm3);
4837 vextractf128h(Address(rsp, 64),xmm4);
4838 vextractf128h(Address(rsp, 80),xmm5);
4839 vextractf128h(Address(rsp, 96),xmm6);
4840 vextractf128h(Address(rsp,112),xmm7);
4841 #ifdef _LP64
4842 vextractf128h(Address(rsp,128),xmm8);
4843 vextractf128h(Address(rsp,144),xmm9);
4844 vextractf128h(Address(rsp,160),xmm10);
4845 vextractf128h(Address(rsp,176),xmm11);
4846 vextractf128h(Address(rsp,192),xmm12);
4847 vextractf128h(Address(rsp,208),xmm13);
4848 vextractf128h(Address(rsp,224),xmm14);
4849 vextractf128h(Address(rsp,240),xmm15);
4850 #endif
4851 }
4852 #endif
4853 // Save whole 128bit (16 bytes) XMM regiters
4854 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4855 movdqu(Address(rsp,off++*16),xmm0);
4856 movdqu(Address(rsp,off++*16),xmm1);
4857 movdqu(Address(rsp,off++*16),xmm2);
4858 movdqu(Address(rsp,off++*16),xmm3);
4859 movdqu(Address(rsp,off++*16),xmm4);
4860 movdqu(Address(rsp,off++*16),xmm5);
4861 movdqu(Address(rsp,off++*16),xmm6);
4862 movdqu(Address(rsp,off++*16),xmm7);
4863 #ifdef _LP64
4864 movdqu(Address(rsp,off++*16),xmm8);
4865 movdqu(Address(rsp,off++*16),xmm9);
4866 movdqu(Address(rsp,off++*16),xmm10);
4867 movdqu(Address(rsp,off++*16),xmm11);
4868 movdqu(Address(rsp,off++*16),xmm12);
4869 movdqu(Address(rsp,off++*16),xmm13);
4870 movdqu(Address(rsp,off++*16),xmm14);
4871 movdqu(Address(rsp,off++*16),xmm15);
4872 #endif
4873 }
4874 }
4875
4876 void MacroAssembler::restore_vector_registers() {
4877 int off = 0;
4878 if (UseSSE == 1) {
4879 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4880 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4881 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4882 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4883 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4884 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4885 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4886 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4887 addptr(rsp, sizeof(jdouble)*8);
4888 } else if (UseSSE >= 2) {
4889 // Restore whole 128bit (16 bytes) XMM regiters
4890 movdqu(xmm0, Address(rsp,off++*16));
4891 movdqu(xmm1, Address(rsp,off++*16));
4892 movdqu(xmm2, Address(rsp,off++*16));
4893 movdqu(xmm3, Address(rsp,off++*16));
4894 movdqu(xmm4, Address(rsp,off++*16));
4895 movdqu(xmm5, Address(rsp,off++*16));
4896 movdqu(xmm6, Address(rsp,off++*16));
4897 movdqu(xmm7, Address(rsp,off++*16));
4898 #ifdef _LP64
4899 movdqu(xmm8, Address(rsp,off++*16));
4900 movdqu(xmm9, Address(rsp,off++*16));
4901 movdqu(xmm10, Address(rsp,off++*16));
4902 movdqu(xmm11, Address(rsp,off++*16));
4903 movdqu(xmm12, Address(rsp,off++*16));
4904 movdqu(xmm13, Address(rsp,off++*16));
4905 movdqu(xmm14, Address(rsp,off++*16));
4906 movdqu(xmm15, Address(rsp,off++*16));
4907 #endif
4908 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4909 #ifdef COMPILER2
4910 if (MaxVectorSize > 16) {
4911 // Restore upper half of YMM registes.
4912 vinsertf128h(xmm0, Address(rsp, 0));
4913 vinsertf128h(xmm1, Address(rsp, 16));
4914 vinsertf128h(xmm2, Address(rsp, 32));
4915 vinsertf128h(xmm3, Address(rsp, 48));
4916 vinsertf128h(xmm4, Address(rsp, 64));
4917 vinsertf128h(xmm5, Address(rsp, 80));
4918 vinsertf128h(xmm6, Address(rsp, 96));
4919 vinsertf128h(xmm7, Address(rsp,112));
4920 #ifdef _LP64
4921 vinsertf128h(xmm8, Address(rsp,128));
4922 vinsertf128h(xmm9, Address(rsp,144));
4923 vinsertf128h(xmm10, Address(rsp,160));
4924 vinsertf128h(xmm11, Address(rsp,176));
4925 vinsertf128h(xmm12, Address(rsp,192));
4926 vinsertf128h(xmm13, Address(rsp,208));
4927 vinsertf128h(xmm14, Address(rsp,224));
4928 vinsertf128h(xmm15, Address(rsp,240));
4929 #endif
4930 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4931 }
4932 #endif
4933 }
4934 }
4935
4936 static const double pi_4 = 0.7853981633974483;
4937
4938 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4939 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4940 // was attempted in this code; unfortunately it appears that the
4941 // switch to 80-bit precision and back causes this to be
4942 // unprofitable compared with simply performing a runtime call if
4943 // the argument is out of the (-pi/4, pi/4) range.
4944
4945 Register tmp = noreg;
4946 if (!VM_Version::supports_cmov()) {
4947 // fcmp needs a temporary so preserve rbx,
4948 tmp = rbx;
4949 push(tmp);
4950 }
4951
4952 Label slow_case, done;
4953
4954 ExternalAddress pi4_adr = (address)&pi_4;
4955 if (reachable(pi4_adr)) {
4956 // x ?<= pi/4
4957 fld_d(pi4_adr);
4958 fld_s(1); // Stack: X PI/4 X
4959 fabs(); // Stack: |X| PI/4 X
4960 fcmp(tmp);
4961 jcc(Assembler::above, slow_case);
4962
4963 // fastest case: -pi/4 <= x <= pi/4
4964 switch(trig) {
4965 case 's':
4966 fsin();
4967 break;
4968 case 'c':
4969 fcos();
4970 break;
4971 case 't':
4972 ftan();
4973 break;
4974 default:
4975 assert(false, "bad intrinsic");
4976 break;
4977 }
4978 jmp(done);
4979 }
4980
4981 // slow case: runtime call
4982 bind(slow_case);
4983
4984 switch(trig) {
4985 case 's':
4986 {
4987 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4988 }
4989 break;
4990 case 'c':
4991 {
4992 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4993 }
4994 break;
4995 case 't':
4996 {
4997 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4998 }
4999 break;
5000 default:
5001 assert(false, "bad intrinsic");
5002 break;
5003 }
5004
5005 // Come here with result in F-TOS
5006 bind(done);
5007
5008 if (tmp != noreg) {
5009 pop(tmp);
5010 }
5011 }
5012
5013
5014 // Look up the method for a megamorphic invokeinterface call.
5015 // The target method is determined by <intf_klass, itable_index>.
5016 // The receiver klass is in recv_klass.
5017 // On success, the result will be in method_result, and execution falls through.
5018 // On failure, execution transfers to the given label.
5019 void MacroAssembler::lookup_interface_method(Register recv_klass,
5020 Register intf_klass,
5021 RegisterOrConstant itable_index,
5022 Register method_result,
5023 Register scan_temp,
5024 Label& L_no_such_interface,
5025 bool return_method) {
5026 assert_different_registers(recv_klass, intf_klass, scan_temp);
5027 assert_different_registers(method_result, intf_klass, scan_temp);
5028 assert(recv_klass != method_result || !return_method,
5029 "recv_klass can be destroyed when method isn't needed");
5030
5031 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5032 "caller must use same register for non-constant itable index as for method");
5033
5034 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5035 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
5036 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5037 int scan_step = itableOffsetEntry::size() * wordSize;
5038 int vte_size = vtableEntry::size() * wordSize;
5039 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5040 assert(vte_size == wordSize, "else adjust times_vte_scale");
5041
5042 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
5043
5044 // %%% Could store the aligned, prescaled offset in the klassoop.
5045 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5046 if (HeapWordsPerLong > 1) {
5047 // Round up to align_object_offset boundary
5048 // see code for InstanceKlass::start_of_itable!
5049 round_to(scan_temp, BytesPerLong);
5050 }
5051
5052 if (return_method) {
5053 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5054 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5055 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5056 }
5057
5058 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5059 // if (scan->interface() == intf) {
5060 // result = (klass + scan->offset() + itable_index);
5061 // }
5062 // }
5063 Label search, found_method;
5064
5065 for (int peel = 1; peel >= 0; peel--) {
5066 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5067 cmpptr(intf_klass, method_result);
5068
5069 if (peel) {
5070 jccb(Assembler::equal, found_method);
5071 } else {
5072 jccb(Assembler::notEqual, search);
5073 // (invert the test to fall through to found_method...)
5074 }
5075
5076 if (!peel) break;
5077
5078 bind(search);
5079
5080 // Check that the previous entry is non-null. A null entry means that
5081 // the receiver class doesn't implement the interface, and wasn't the
5082 // same as when the caller was compiled.
5083 testptr(method_result, method_result);
5084 jcc(Assembler::zero, L_no_such_interface);
5085 addptr(scan_temp, scan_step);
5086 }
5087
5088 bind(found_method);
5089
5090 if (return_method) {
5091 // Got a hit.
5092 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5093 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5094 }
5095 }
5096
5097
5098 // virtual method calling
5099 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5100 RegisterOrConstant vtable_index,
5101 Register method_result) {
5102 const int base = InstanceKlass::vtable_start_offset() * wordSize;
5103 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5104 Address vtable_entry_addr(recv_klass,
5105 vtable_index, Address::times_ptr,
5106 base + vtableEntry::method_offset_in_bytes());
5107 movptr(method_result, vtable_entry_addr);
5108 }
5109
5110
5111 void MacroAssembler::check_klass_subtype(Register sub_klass,
5112 Register super_klass,
5113 Register temp_reg,
5114 Label& L_success) {
5115 Label L_failure;
5116 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5117 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5118 bind(L_failure);
5119 }
5120
5121
5122 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5123 Register super_klass,
5124 Register temp_reg,
5125 Label* L_success,
5126 Label* L_failure,
5127 Label* L_slow_path,
5128 RegisterOrConstant super_check_offset) {
5129 assert_different_registers(sub_klass, super_klass, temp_reg);
5130 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5131 if (super_check_offset.is_register()) {
5132 assert_different_registers(sub_klass, super_klass,
5133 super_check_offset.as_register());
5134 } else if (must_load_sco) {
5135 assert(temp_reg != noreg, "supply either a temp or a register offset");
5136 }
5137
5138 Label L_fallthrough;
5139 int label_nulls = 0;
5140 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5141 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5142 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5143 assert(label_nulls <= 1, "at most one NULL in the batch");
5144
5145 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5146 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5147 Address super_check_offset_addr(super_klass, sco_offset);
5148
5149 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5150 // range of a jccb. If this routine grows larger, reconsider at
5151 // least some of these.
5152 #define local_jcc(assembler_cond, label) \
5153 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5154 else jcc( assembler_cond, label) /*omit semi*/
5155
5156 // Hacked jmp, which may only be used just before L_fallthrough.
5157 #define final_jmp(label) \
5158 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5159 else jmp(label) /*omit semi*/
5160
5161 // If the pointers are equal, we are done (e.g., String[] elements).
5162 // This self-check enables sharing of secondary supertype arrays among
5163 // non-primary types such as array-of-interface. Otherwise, each such
5164 // type would need its own customized SSA.
5165 // We move this check to the front of the fast path because many
5166 // type checks are in fact trivially successful in this manner,
5167 // so we get a nicely predicted branch right at the start of the check.
5168 cmpptr(sub_klass, super_klass);
5169 local_jcc(Assembler::equal, *L_success);
5170
5171 // Check the supertype display:
5172 if (must_load_sco) {
5173 // Positive movl does right thing on LP64.
5174 movl(temp_reg, super_check_offset_addr);
5175 super_check_offset = RegisterOrConstant(temp_reg);
5176 }
5177 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5178 cmpptr(super_klass, super_check_addr); // load displayed supertype
5179
5180 // This check has worked decisively for primary supers.
5181 // Secondary supers are sought in the super_cache ('super_cache_addr').
5182 // (Secondary supers are interfaces and very deeply nested subtypes.)
5183 // This works in the same check above because of a tricky aliasing
5184 // between the super_cache and the primary super display elements.
5185 // (The 'super_check_addr' can address either, as the case requires.)
5186 // Note that the cache is updated below if it does not help us find
5187 // what we need immediately.
5188 // So if it was a primary super, we can just fail immediately.
5189 // Otherwise, it's the slow path for us (no success at this point).
5190
5191 if (super_check_offset.is_register()) {
5192 local_jcc(Assembler::equal, *L_success);
5193 cmpl(super_check_offset.as_register(), sc_offset);
5194 if (L_failure == &L_fallthrough) {
5195 local_jcc(Assembler::equal, *L_slow_path);
5196 } else {
5197 local_jcc(Assembler::notEqual, *L_failure);
5198 final_jmp(*L_slow_path);
5199 }
5200 } else if (super_check_offset.as_constant() == sc_offset) {
5201 // Need a slow path; fast failure is impossible.
5202 if (L_slow_path == &L_fallthrough) {
5203 local_jcc(Assembler::equal, *L_success);
5204 } else {
5205 local_jcc(Assembler::notEqual, *L_slow_path);
5206 final_jmp(*L_success);
5207 }
5208 } else {
5209 // No slow path; it's a fast decision.
5210 if (L_failure == &L_fallthrough) {
5211 local_jcc(Assembler::equal, *L_success);
5212 } else {
5213 local_jcc(Assembler::notEqual, *L_failure);
5214 final_jmp(*L_success);
5215 }
5216 }
5217
5218 bind(L_fallthrough);
5219
5220 #undef local_jcc
5221 #undef final_jmp
5222 }
5223
5224
5225 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5226 Register super_klass,
5227 Register temp_reg,
5228 Register temp2_reg,
5229 Label* L_success,
5230 Label* L_failure,
5231 bool set_cond_codes) {
5232 assert_different_registers(sub_klass, super_klass, temp_reg);
5233 if (temp2_reg != noreg)
5234 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5235 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5236
5237 Label L_fallthrough;
5238 int label_nulls = 0;
5239 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5240 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5241 assert(label_nulls <= 1, "at most one NULL in the batch");
5242
5243 // a couple of useful fields in sub_klass:
5244 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5245 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5246 Address secondary_supers_addr(sub_klass, ss_offset);
5247 Address super_cache_addr( sub_klass, sc_offset);
5248
5249 // Do a linear scan of the secondary super-klass chain.
5250 // This code is rarely used, so simplicity is a virtue here.
5251 // The repne_scan instruction uses fixed registers, which we must spill.
5252 // Don't worry too much about pre-existing connections with the input regs.
5253
5254 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5255 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5256
5257 // Get super_klass value into rax (even if it was in rdi or rcx).
5258 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5259 if (super_klass != rax || UseCompressedOops) {
5260 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5261 mov(rax, super_klass);
5262 }
5263 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5264 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5265
5266 #ifndef PRODUCT
5267 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5268 ExternalAddress pst_counter_addr((address) pst_counter);
5269 NOT_LP64( incrementl(pst_counter_addr) );
5270 LP64_ONLY( lea(rcx, pst_counter_addr) );
5271 LP64_ONLY( incrementl(Address(rcx, 0)) );
5272 #endif //PRODUCT
5273
5274 // We will consult the secondary-super array.
5275 movptr(rdi, secondary_supers_addr);
5276 // Load the array length. (Positive movl does right thing on LP64.)
5277 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5278 // Skip to start of data.
5279 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5280
5281 // Scan RCX words at [RDI] for an occurrence of RAX.
5282 // Set NZ/Z based on last compare.
5283 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5284 // not change flags (only scas instruction which is repeated sets flags).
5285 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5286
5287 testptr(rax,rax); // Set Z = 0
5288 repne_scan();
5289
5290 // Unspill the temp. registers:
5291 if (pushed_rdi) pop(rdi);
5292 if (pushed_rcx) pop(rcx);
5293 if (pushed_rax) pop(rax);
5294
5295 if (set_cond_codes) {
5296 // Special hack for the AD files: rdi is guaranteed non-zero.
5297 assert(!pushed_rdi, "rdi must be left non-NULL");
5298 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5299 }
5300
5301 if (L_failure == &L_fallthrough)
5302 jccb(Assembler::notEqual, *L_failure);
5303 else jcc(Assembler::notEqual, *L_failure);
5304
5305 // Success. Cache the super we found and proceed in triumph.
5306 movptr(super_cache_addr, super_klass);
5307
5308 if (L_success != &L_fallthrough) {
5309 jmp(*L_success);
5310 }
5311
5312 #undef IS_A_TEMP
5313
5314 bind(L_fallthrough);
5315 }
5316
5317
5318 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5319 if (VM_Version::supports_cmov()) {
5320 cmovl(cc, dst, src);
5321 } else {
5322 Label L;
5323 jccb(negate_condition(cc), L);
5324 movl(dst, src);
5325 bind(L);
5326 }
5327 }
5328
5329 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5330 if (VM_Version::supports_cmov()) {
5331 cmovl(cc, dst, src);
5332 } else {
5333 Label L;
5334 jccb(negate_condition(cc), L);
5335 movl(dst, src);
5336 bind(L);
5337 }
5338 }
5339
5340 void MacroAssembler::verify_oop(Register reg, const char* s) {
5341 if (!VerifyOops) return;
5342
5343 // Pass register number to verify_oop_subroutine
5344 const char* b = NULL;
5345 {
5346 ResourceMark rm;
5347 stringStream ss;
5348 ss.print("verify_oop: %s: %s", reg->name(), s);
5349 b = code_string(ss.as_string());
5350 }
5351 BLOCK_COMMENT("verify_oop {");
5352 #ifdef _LP64
5353 push(rscratch1); // save r10, trashed by movptr()
5354 #endif
5355 push(rax); // save rax,
5356 push(reg); // pass register argument
5357 ExternalAddress buffer((address) b);
5358 // avoid using pushptr, as it modifies scratch registers
5359 // and our contract is not to modify anything
5360 movptr(rax, buffer.addr());
5361 push(rax);
5362 // call indirectly to solve generation ordering problem
5363 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5364 call(rax);
5365 // Caller pops the arguments (oop, message) and restores rax, r10
5366 BLOCK_COMMENT("} verify_oop");
5367 }
5368
5369 #if INCLUDE_ALL_GCS
5370 void MacroAssembler::in_heap_check(Register raddr, Register tmp, Label& done) {
5371 ShenandoahHeap *h = (ShenandoahHeap *)Universe::heap();
5372
5373 HeapWord* heap_base = (HeapWord*) h->base();
5374 HeapWord* last_region_end = heap_base + (ShenandoahHeapRegion::region_size_bytes() / HeapWordSize) * h->num_regions();
5375 guarantee(heap_base < last_region_end, err_msg("sanity: %p < %p", heap_base, last_region_end));
5376 movptr(tmp, (intptr_t) heap_base);
5377 cmpptr(raddr, tmp);
5378 jcc(Assembler::below, done);
5379 movptr(tmp, (intptr_t) last_region_end);
5380 cmpptr(raddr, tmp);
5381 jcc(Assembler::aboveEqual, done);
5382
5383 }
5384 #endif
5385
5386 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5387 Register tmp,
5388 int offset) {
5389 intptr_t value = *delayed_value_addr;
5390 if (value != 0)
5391 return RegisterOrConstant(value + offset);
5392
5393 // load indirectly to solve generation ordering problem
5394 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5395
5396 #ifdef ASSERT
5397 { Label L;
5398 testptr(tmp, tmp);
5399 if (WizardMode) {
5400 const char* buf = NULL;
5401 {
5402 ResourceMark rm;
5403 stringStream ss;
5404 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5405 buf = code_string(ss.as_string());
5406 }
5407 jcc(Assembler::notZero, L);
5408 STOP(buf);
5409 } else {
5410 jccb(Assembler::notZero, L);
5411 hlt();
5412 }
5413 bind(L);
5414 }
5415 #endif
5416
5417 if (offset != 0)
5418 addptr(tmp, offset);
5419
5420 return RegisterOrConstant(tmp);
5421 }
5422
5423
5424 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5425 int extra_slot_offset) {
5426 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5427 int stackElementSize = Interpreter::stackElementSize;
5428 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5429 #ifdef ASSERT
5430 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5431 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5432 #endif
5433 Register scale_reg = noreg;
5434 Address::ScaleFactor scale_factor = Address::no_scale;
5435 if (arg_slot.is_constant()) {
5436 offset += arg_slot.as_constant() * stackElementSize;
5437 } else {
5438 scale_reg = arg_slot.as_register();
5439 scale_factor = Address::times(stackElementSize);
5440 }
5441 offset += wordSize; // return PC is on stack
5442 return Address(rsp, scale_reg, scale_factor, offset);
5443 }
5444
5445
5446 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5447 if (!VerifyOops) return;
5448
5449 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5450 // Pass register number to verify_oop_subroutine
5451 const char* b = NULL;
5452 {
5453 ResourceMark rm;
5454 stringStream ss;
5455 ss.print("verify_oop_addr: %s", s);
5456 b = code_string(ss.as_string());
5457 }
5458 #ifdef _LP64
5459 push(rscratch1); // save r10, trashed by movptr()
5460 #endif
5461 push(rax); // save rax,
5462 // addr may contain rsp so we will have to adjust it based on the push
5463 // we just did (and on 64 bit we do two pushes)
5464 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5465 // stores rax into addr which is backwards of what was intended.
5466 if (addr.uses(rsp)) {
5467 lea(rax, addr);
5468 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5469 } else {
5470 pushptr(addr);
5471 }
5472
5473 ExternalAddress buffer((address) b);
5474 // pass msg argument
5475 // avoid using pushptr, as it modifies scratch registers
5476 // and our contract is not to modify anything
5477 movptr(rax, buffer.addr());
5478 push(rax);
5479
5480 // call indirectly to solve generation ordering problem
5481 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5482 call(rax);
5483 // Caller pops the arguments (addr, message) and restores rax, r10.
5484 }
5485
5486 void MacroAssembler::verify_tlab() {
5487 #ifdef ASSERT
5488 if (UseTLAB && VerifyOops) {
5489 Label next, ok;
5490 Register t1 = rsi;
5491 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5492
5493 push(t1);
5494 NOT_LP64(push(thread_reg));
5495 NOT_LP64(get_thread(thread_reg));
5496
5497 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5498 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5499 jcc(Assembler::aboveEqual, next);
5500 STOP("assert(top >= start)");
5501 should_not_reach_here();
5502
5503 bind(next);
5504 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5505 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5506 jcc(Assembler::aboveEqual, ok);
5507 STOP("assert(top <= end)");
5508 should_not_reach_here();
5509
5510 bind(ok);
5511 NOT_LP64(pop(thread_reg));
5512 pop(t1);
5513 }
5514 #endif
5515 }
5516
5517 class ControlWord {
5518 public:
5519 int32_t _value;
5520
5521 int rounding_control() const { return (_value >> 10) & 3 ; }
5522 int precision_control() const { return (_value >> 8) & 3 ; }
5523 bool precision() const { return ((_value >> 5) & 1) != 0; }
5524 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5525 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5526 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5527 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5528 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5529
5530 void print() const {
5531 // rounding control
5532 const char* rc;
5533 switch (rounding_control()) {
5534 case 0: rc = "round near"; break;
5535 case 1: rc = "round down"; break;
5536 case 2: rc = "round up "; break;
5537 case 3: rc = "chop "; break;
5538 };
5539 // precision control
5540 const char* pc;
5541 switch (precision_control()) {
5542 case 0: pc = "24 bits "; break;
5543 case 1: pc = "reserved"; break;
5544 case 2: pc = "53 bits "; break;
5545 case 3: pc = "64 bits "; break;
5546 };
5547 // flags
5548 char f[9];
5549 f[0] = ' ';
5550 f[1] = ' ';
5551 f[2] = (precision ()) ? 'P' : 'p';
5552 f[3] = (underflow ()) ? 'U' : 'u';
5553 f[4] = (overflow ()) ? 'O' : 'o';
5554 f[5] = (zero_divide ()) ? 'Z' : 'z';
5555 f[6] = (denormalized()) ? 'D' : 'd';
5556 f[7] = (invalid ()) ? 'I' : 'i';
5557 f[8] = '\x0';
5558 // output
5559 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5560 }
5561
5562 };
5563
5564 class StatusWord {
5565 public:
5566 int32_t _value;
5567
5568 bool busy() const { return ((_value >> 15) & 1) != 0; }
5569 bool C3() const { return ((_value >> 14) & 1) != 0; }
5570 bool C2() const { return ((_value >> 10) & 1) != 0; }
5571 bool C1() const { return ((_value >> 9) & 1) != 0; }
5572 bool C0() const { return ((_value >> 8) & 1) != 0; }
5573 int top() const { return (_value >> 11) & 7 ; }
5574 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5575 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5576 bool precision() const { return ((_value >> 5) & 1) != 0; }
5577 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5578 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5579 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5580 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5581 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5582
5583 void print() const {
5584 // condition codes
5585 char c[5];
5586 c[0] = (C3()) ? '3' : '-';
5587 c[1] = (C2()) ? '2' : '-';
5588 c[2] = (C1()) ? '1' : '-';
5589 c[3] = (C0()) ? '0' : '-';
5590 c[4] = '\x0';
5591 // flags
5592 char f[9];
5593 f[0] = (error_status()) ? 'E' : '-';
5594 f[1] = (stack_fault ()) ? 'S' : '-';
5595 f[2] = (precision ()) ? 'P' : '-';
5596 f[3] = (underflow ()) ? 'U' : '-';
5597 f[4] = (overflow ()) ? 'O' : '-';
5598 f[5] = (zero_divide ()) ? 'Z' : '-';
5599 f[6] = (denormalized()) ? 'D' : '-';
5600 f[7] = (invalid ()) ? 'I' : '-';
5601 f[8] = '\x0';
5602 // output
5603 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5604 }
5605
5606 };
5607
5608 class TagWord {
5609 public:
5610 int32_t _value;
5611
5612 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5613
5614 void print() const {
5615 printf("%04x", _value & 0xFFFF);
5616 }
5617
5618 };
5619
5620 class FPU_Register {
5621 public:
5622 int32_t _m0;
5623 int32_t _m1;
5624 int16_t _ex;
5625
5626 bool is_indefinite() const {
5627 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5628 }
5629
5630 void print() const {
5631 char sign = (_ex < 0) ? '-' : '+';
5632 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5633 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5634 };
5635
5636 };
5637
5638 class FPU_State {
5639 public:
5640 enum {
5641 register_size = 10,
5642 number_of_registers = 8,
5643 register_mask = 7
5644 };
5645
5646 ControlWord _control_word;
5647 StatusWord _status_word;
5648 TagWord _tag_word;
5649 int32_t _error_offset;
5650 int32_t _error_selector;
5651 int32_t _data_offset;
5652 int32_t _data_selector;
5653 int8_t _register[register_size * number_of_registers];
5654
5655 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5656 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5657
5658 const char* tag_as_string(int tag) const {
5659 switch (tag) {
5660 case 0: return "valid";
5661 case 1: return "zero";
5662 case 2: return "special";
5663 case 3: return "empty";
5664 }
5665 ShouldNotReachHere();
5666 return NULL;
5667 }
5668
5669 void print() const {
5670 // print computation registers
5671 { int t = _status_word.top();
5672 for (int i = 0; i < number_of_registers; i++) {
5673 int j = (i - t) & register_mask;
5674 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5675 st(j)->print();
5676 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5677 }
5678 }
5679 printf("\n");
5680 // print control registers
5681 printf("ctrl = "); _control_word.print(); printf("\n");
5682 printf("stat = "); _status_word .print(); printf("\n");
5683 printf("tags = "); _tag_word .print(); printf("\n");
5684 }
5685
5686 };
5687
5688 class Flag_Register {
5689 public:
5690 int32_t _value;
5691
5692 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5693 bool direction() const { return ((_value >> 10) & 1) != 0; }
5694 bool sign() const { return ((_value >> 7) & 1) != 0; }
5695 bool zero() const { return ((_value >> 6) & 1) != 0; }
5696 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5697 bool parity() const { return ((_value >> 2) & 1) != 0; }
5698 bool carry() const { return ((_value >> 0) & 1) != 0; }
5699
5700 void print() const {
5701 // flags
5702 char f[8];
5703 f[0] = (overflow ()) ? 'O' : '-';
5704 f[1] = (direction ()) ? 'D' : '-';
5705 f[2] = (sign ()) ? 'S' : '-';
5706 f[3] = (zero ()) ? 'Z' : '-';
5707 f[4] = (auxiliary_carry()) ? 'A' : '-';
5708 f[5] = (parity ()) ? 'P' : '-';
5709 f[6] = (carry ()) ? 'C' : '-';
5710 f[7] = '\x0';
5711 // output
5712 printf("%08x flags = %s", _value, f);
5713 }
5714
5715 };
5716
5717 class IU_Register {
5718 public:
5719 int32_t _value;
5720
5721 void print() const {
5722 printf("%08x %11d", _value, _value);
5723 }
5724
5725 };
5726
5727 class IU_State {
5728 public:
5729 Flag_Register _eflags;
5730 IU_Register _rdi;
5731 IU_Register _rsi;
5732 IU_Register _rbp;
5733 IU_Register _rsp;
5734 IU_Register _rbx;
5735 IU_Register _rdx;
5736 IU_Register _rcx;
5737 IU_Register _rax;
5738
5739 void print() const {
5740 // computation registers
5741 printf("rax, = "); _rax.print(); printf("\n");
5742 printf("rbx, = "); _rbx.print(); printf("\n");
5743 printf("rcx = "); _rcx.print(); printf("\n");
5744 printf("rdx = "); _rdx.print(); printf("\n");
5745 printf("rdi = "); _rdi.print(); printf("\n");
5746 printf("rsi = "); _rsi.print(); printf("\n");
5747 printf("rbp, = "); _rbp.print(); printf("\n");
5748 printf("rsp = "); _rsp.print(); printf("\n");
5749 printf("\n");
5750 // control registers
5751 printf("flgs = "); _eflags.print(); printf("\n");
5752 }
5753 };
5754
5755
5756 class CPU_State {
5757 public:
5758 FPU_State _fpu_state;
5759 IU_State _iu_state;
5760
5761 void print() const {
5762 printf("--------------------------------------------------\n");
5763 _iu_state .print();
5764 printf("\n");
5765 _fpu_state.print();
5766 printf("--------------------------------------------------\n");
5767 }
5768
5769 };
5770
5771
5772 static void _print_CPU_state(CPU_State* state) {
5773 state->print();
5774 };
5775
5776
5777 void MacroAssembler::print_CPU_state() {
5778 push_CPU_state();
5779 push(rsp); // pass CPU state
5780 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5781 addptr(rsp, wordSize); // discard argument
5782 pop_CPU_state();
5783 }
5784
5785
5786 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5787 static int counter = 0;
5788 FPU_State* fs = &state->_fpu_state;
5789 counter++;
5790 // For leaf calls, only verify that the top few elements remain empty.
5791 // We only need 1 empty at the top for C2 code.
5792 if( stack_depth < 0 ) {
5793 if( fs->tag_for_st(7) != 3 ) {
5794 printf("FPR7 not empty\n");
5795 state->print();
5796 assert(false, "error");
5797 return false;
5798 }
5799 return true; // All other stack states do not matter
5800 }
5801
5802 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5803 "bad FPU control word");
5804
5805 // compute stack depth
5806 int i = 0;
5807 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5808 int d = i;
5809 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5810 // verify findings
5811 if (i != FPU_State::number_of_registers) {
5812 // stack not contiguous
5813 printf("%s: stack not contiguous at ST%d\n", s, i);
5814 state->print();
5815 assert(false, "error");
5816 return false;
5817 }
5818 // check if computed stack depth corresponds to expected stack depth
5819 if (stack_depth < 0) {
5820 // expected stack depth is -stack_depth or less
5821 if (d > -stack_depth) {
5822 // too many elements on the stack
5823 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5824 state->print();
5825 assert(false, "error");
5826 return false;
5827 }
5828 } else {
5829 // expected stack depth is stack_depth
5830 if (d != stack_depth) {
5831 // wrong stack depth
5832 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5833 state->print();
5834 assert(false, "error");
5835 return false;
5836 }
5837 }
5838 // everything is cool
5839 return true;
5840 }
5841
5842
5843 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5844 if (!VerifyFPU) return;
5845 push_CPU_state();
5846 push(rsp); // pass CPU state
5847 ExternalAddress msg((address) s);
5848 // pass message string s
5849 pushptr(msg.addr());
5850 push(stack_depth); // pass stack depth
5851 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5852 addptr(rsp, 3 * wordSize); // discard arguments
5853 // check for error
5854 { Label L;
5855 testl(rax, rax);
5856 jcc(Assembler::notZero, L);
5857 int3(); // break if error condition
5858 bind(L);
5859 }
5860 pop_CPU_state();
5861 }
5862
5863 void MacroAssembler::restore_cpu_control_state_after_jni() {
5864 // Either restore the MXCSR register after returning from the JNI Call
5865 // or verify that it wasn't changed (with -Xcheck:jni flag).
5866 if (VM_Version::supports_sse()) {
5867 if (RestoreMXCSROnJNICalls) {
5868 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5869 } else if (CheckJNICalls) {
5870 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5871 }
5872 }
5873 if (VM_Version::supports_avx()) {
5874 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5875 vzeroupper();
5876 }
5877
5878 #ifndef _LP64
5879 // Either restore the x87 floating pointer control word after returning
5880 // from the JNI call or verify that it wasn't changed.
5881 if (CheckJNICalls) {
5882 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5883 }
5884 #endif // _LP64
5885 }
5886
5887
5888 void MacroAssembler::load_klass(Register dst, Register src) {
5889 #ifdef _LP64
5890 if (UseCompressedClassPointers) {
5891 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5892 decode_klass_not_null(dst);
5893 } else
5894 #endif
5895 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5896 }
5897
5898 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5899 load_klass(dst, src);
5900 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5901 }
5902
5903 void MacroAssembler::store_klass(Register dst, Register src) {
5904 #ifdef _LP64
5905 if (UseCompressedClassPointers) {
5906 encode_klass_not_null(src);
5907 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5908 } else
5909 #endif
5910 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5911 }
5912
5913 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5914 #ifdef _LP64
5915 // FIXME: Must change all places where we try to load the klass.
5916 if (UseCompressedOops) {
5917 movl(dst, src);
5918 decode_heap_oop(dst);
5919 } else
5920 #endif
5921 movptr(dst, src);
5922 }
5923
5924 // Doesn't do verfication, generates fixed size code
5925 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5926 #ifdef _LP64
5927 if (UseCompressedOops) {
5928 movl(dst, src);
5929 decode_heap_oop_not_null(dst);
5930 } else
5931 #endif
5932 movptr(dst, src);
5933 }
5934
5935 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5936 #ifdef _LP64
5937 if (UseCompressedOops) {
5938 assert(!dst.uses(src), "not enough registers");
5939 encode_heap_oop(src);
5940 movl(dst, src);
5941 } else
5942 #endif
5943 movptr(dst, src);
5944 }
5945
5946 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5947 assert_different_registers(src1, tmp);
5948 #ifdef _LP64
5949 if (UseCompressedOops) {
5950 bool did_push = false;
5951 if (tmp == noreg) {
5952 tmp = rax;
5953 push(tmp);
5954 did_push = true;
5955 assert(!src2.uses(rsp), "can't push");
5956 }
5957 load_heap_oop(tmp, src2);
5958 cmpptr(src1, tmp);
5959 if (did_push) pop(tmp);
5960 } else
5961 #endif
5962 cmpptr(src1, src2);
5963 }
5964
5965 // Used for storing NULLs.
5966 void MacroAssembler::store_heap_oop_null(Address dst) {
5967 #ifdef _LP64
5968 if (UseCompressedOops) {
5969 movl(dst, (int32_t)NULL_WORD);
5970 } else {
5971 movslq(dst, (int32_t)NULL_WORD);
5972 }
5973 #else
5974 movl(dst, (int32_t)NULL_WORD);
5975 #endif
5976 }
5977
5978 #ifdef _LP64
5979 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5980 if (UseCompressedClassPointers) {
5981 // Store to klass gap in destination
5982 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5983 }
5984 }
5985
5986 #ifdef ASSERT
5987 void MacroAssembler::verify_heapbase(const char* msg) {
5988 assert (UseCompressedOops, "should be compressed");
5989 assert (Universe::heap() != NULL, "java heap should be initialized");
5990 if (CheckCompressedOops) {
5991 Label ok;
5992 push(rscratch1); // cmpptr trashes rscratch1
5993 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5994 jcc(Assembler::equal, ok);
5995 STOP(msg);
5996 bind(ok);
5997 pop(rscratch1);
5998 }
5999 }
6000 #endif
6001
6002 // Algorithm must match oop.inline.hpp encode_heap_oop.
6003 void MacroAssembler::encode_heap_oop(Register r) {
6004 #ifdef ASSERT
6005 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6006 #endif
6007 verify_oop(r, "broken oop in encode_heap_oop");
6008 if (Universe::narrow_oop_base() == NULL) {
6009 if (Universe::narrow_oop_shift() != 0) {
6010 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6011 shrq(r, LogMinObjAlignmentInBytes);
6012 }
6013 return;
6014 }
6015 testq(r, r);
6016 cmovq(Assembler::equal, r, r12_heapbase);
6017 subq(r, r12_heapbase);
6018 shrq(r, LogMinObjAlignmentInBytes);
6019 }
6020
6021 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6022 #ifdef ASSERT
6023 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6024 if (CheckCompressedOops) {
6025 Label ok;
6026 testq(r, r);
6027 jcc(Assembler::notEqual, ok);
6028 STOP("null oop passed to encode_heap_oop_not_null");
6029 bind(ok);
6030 }
6031 #endif
6032 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6033 if (Universe::narrow_oop_base() != NULL) {
6034 subq(r, r12_heapbase);
6035 }
6036 if (Universe::narrow_oop_shift() != 0) {
6037 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6038 shrq(r, LogMinObjAlignmentInBytes);
6039 }
6040 }
6041
6042 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6043 #ifdef ASSERT
6044 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6045 if (CheckCompressedOops) {
6046 Label ok;
6047 testq(src, src);
6048 jcc(Assembler::notEqual, ok);
6049 STOP("null oop passed to encode_heap_oop_not_null2");
6050 bind(ok);
6051 }
6052 #endif
6053 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6054 if (dst != src) {
6055 movq(dst, src);
6056 }
6057 if (Universe::narrow_oop_base() != NULL) {
6058 subq(dst, r12_heapbase);
6059 }
6060 if (Universe::narrow_oop_shift() != 0) {
6061 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6062 shrq(dst, LogMinObjAlignmentInBytes);
6063 }
6064 }
6065
6066 void MacroAssembler::decode_heap_oop(Register r) {
6067 #ifdef ASSERT
6068 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6069 #endif
6070 if (Universe::narrow_oop_base() == NULL) {
6071 if (Universe::narrow_oop_shift() != 0) {
6072 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6073 shlq(r, LogMinObjAlignmentInBytes);
6074 }
6075 } else {
6076 Label done;
6077 shlq(r, LogMinObjAlignmentInBytes);
6078 jccb(Assembler::equal, done);
6079 addq(r, r12_heapbase);
6080 bind(done);
6081 }
6082 verify_oop(r, "broken oop in decode_heap_oop");
6083 }
6084
6085 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6086 // Note: it will change flags
6087 assert (UseCompressedOops, "should only be used for compressed headers");
6088 assert (Universe::heap() != NULL, "java heap should be initialized");
6089 // Cannot assert, unverified entry point counts instructions (see .ad file)
6090 // vtableStubs also counts instructions in pd_code_size_limit.
6091 // Also do not verify_oop as this is called by verify_oop.
6092 if (Universe::narrow_oop_shift() != 0) {
6093 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6094 shlq(r, LogMinObjAlignmentInBytes);
6095 if (Universe::narrow_oop_base() != NULL) {
6096 addq(r, r12_heapbase);
6097 }
6098 } else {
6099 assert (Universe::narrow_oop_base() == NULL, "sanity");
6100 }
6101 }
6102
6103 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6104 // Note: it will change flags
6105 assert (UseCompressedOops, "should only be used for compressed headers");
6106 assert (Universe::heap() != NULL, "java heap should be initialized");
6107 // Cannot assert, unverified entry point counts instructions (see .ad file)
6108 // vtableStubs also counts instructions in pd_code_size_limit.
6109 // Also do not verify_oop as this is called by verify_oop.
6110 if (Universe::narrow_oop_shift() != 0) {
6111 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6112 if (LogMinObjAlignmentInBytes == Address::times_8) {
6113 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6114 } else {
6115 if (dst != src) {
6116 movq(dst, src);
6117 }
6118 shlq(dst, LogMinObjAlignmentInBytes);
6119 if (Universe::narrow_oop_base() != NULL) {
6120 addq(dst, r12_heapbase);
6121 }
6122 }
6123 } else {
6124 assert (Universe::narrow_oop_base() == NULL, "sanity");
6125 if (dst != src) {
6126 movq(dst, src);
6127 }
6128 }
6129 }
6130
6131 void MacroAssembler::encode_klass_not_null(Register r) {
6132 if (Universe::narrow_klass_base() != NULL) {
6133 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6134 assert(r != r12_heapbase, "Encoding a klass in r12");
6135 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6136 subq(r, r12_heapbase);
6137 }
6138 if (Universe::narrow_klass_shift() != 0) {
6139 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6140 shrq(r, LogKlassAlignmentInBytes);
6141 }
6142 if (Universe::narrow_klass_base() != NULL) {
6143 reinit_heapbase();
6144 }
6145 }
6146
6147 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6148 if (dst == src) {
6149 encode_klass_not_null(src);
6150 } else {
6151 if (Universe::narrow_klass_base() != NULL) {
6152 mov64(dst, (int64_t)Universe::narrow_klass_base());
6153 negq(dst);
6154 addq(dst, src);
6155 } else {
6156 movptr(dst, src);
6157 }
6158 if (Universe::narrow_klass_shift() != 0) {
6159 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6160 shrq(dst, LogKlassAlignmentInBytes);
6161 }
6162 }
6163 }
6164
6165 // Function instr_size_for_decode_klass_not_null() counts the instructions
6166 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6167 // when (Universe::heap() != NULL). Hence, if the instructions they
6168 // generate change, then this method needs to be updated.
6169 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6170 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6171 if (Universe::narrow_klass_base() != NULL) {
6172 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6173 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6174 } else {
6175 // longest load decode klass function, mov64, leaq
6176 return 16;
6177 }
6178 }
6179
6180 // !!! If the instructions that get generated here change then function
6181 // instr_size_for_decode_klass_not_null() needs to get updated.
6182 void MacroAssembler::decode_klass_not_null(Register r) {
6183 // Note: it will change flags
6184 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6185 assert(r != r12_heapbase, "Decoding a klass in r12");
6186 // Cannot assert, unverified entry point counts instructions (see .ad file)
6187 // vtableStubs also counts instructions in pd_code_size_limit.
6188 // Also do not verify_oop as this is called by verify_oop.
6189 if (Universe::narrow_klass_shift() != 0) {
6190 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6191 shlq(r, LogKlassAlignmentInBytes);
6192 }
6193 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6194 if (Universe::narrow_klass_base() != NULL) {
6195 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6196 addq(r, r12_heapbase);
6197 reinit_heapbase();
6198 }
6199 }
6200
6201 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6202 // Note: it will change flags
6203 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6204 if (dst == src) {
6205 decode_klass_not_null(dst);
6206 } else {
6207 // Cannot assert, unverified entry point counts instructions (see .ad file)
6208 // vtableStubs also counts instructions in pd_code_size_limit.
6209 // Also do not verify_oop as this is called by verify_oop.
6210 mov64(dst, (int64_t)Universe::narrow_klass_base());
6211 if (Universe::narrow_klass_shift() != 0) {
6212 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6213 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6214 leaq(dst, Address(dst, src, Address::times_8, 0));
6215 } else {
6216 addq(dst, src);
6217 }
6218 }
6219 }
6220
6221 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6222 assert (UseCompressedOops, "should only be used for compressed headers");
6223 assert (Universe::heap() != NULL, "java heap should be initialized");
6224 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6225 int oop_index = oop_recorder()->find_index(obj);
6226 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6227 mov_narrow_oop(dst, oop_index, rspec);
6228 }
6229
6230 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6231 assert (UseCompressedOops, "should only be used for compressed headers");
6232 assert (Universe::heap() != NULL, "java heap should be initialized");
6233 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6234 int oop_index = oop_recorder()->find_index(obj);
6235 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6236 mov_narrow_oop(dst, oop_index, rspec);
6237 }
6238
6239 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6240 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6241 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6242 int klass_index = oop_recorder()->find_index(k);
6243 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6244 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6245 }
6246
6247 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6248 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6249 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6250 int klass_index = oop_recorder()->find_index(k);
6251 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6252 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6253 }
6254
6255 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6256 assert (UseCompressedOops, "should only be used for compressed headers");
6257 assert (Universe::heap() != NULL, "java heap should be initialized");
6258 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6259 int oop_index = oop_recorder()->find_index(obj);
6260 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6261 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6262 }
6263
6264 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6265 assert (UseCompressedOops, "should only be used for compressed headers");
6266 assert (Universe::heap() != NULL, "java heap should be initialized");
6267 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6268 int oop_index = oop_recorder()->find_index(obj);
6269 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6270 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6271 }
6272
6273 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6274 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6275 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6276 int klass_index = oop_recorder()->find_index(k);
6277 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6278 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6279 }
6280
6281 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6282 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6283 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6284 int klass_index = oop_recorder()->find_index(k);
6285 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6286 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6287 }
6288
6289 void MacroAssembler::reinit_heapbase() {
6290 if (UseCompressedOops || UseCompressedClassPointers) {
6291 if (Universe::heap() != NULL) {
6292 if (Universe::narrow_oop_base() == NULL) {
6293 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6294 } else {
6295 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6296 }
6297 } else {
6298 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6299 }
6300 }
6301 }
6302
6303 #endif // _LP64
6304
6305
6306 // C2 compiled method's prolog code.
6307 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6308
6309 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6310 // NativeJump::patch_verified_entry will be able to patch out the entry
6311 // code safely. The push to verify stack depth is ok at 5 bytes,
6312 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6313 // stack bang then we must use the 6 byte frame allocation even if
6314 // we have no frame. :-(
6315 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6316
6317 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6318 // Remove word for return addr
6319 framesize -= wordSize;
6320 stack_bang_size -= wordSize;
6321
6322 // Calls to C2R adapters often do not accept exceptional returns.
6323 // We require that their callers must bang for them. But be careful, because
6324 // some VM calls (such as call site linkage) can use several kilobytes of
6325 // stack. But the stack safety zone should account for that.
6326 // See bugs 4446381, 4468289, 4497237.
6327 if (stack_bang_size > 0) {
6328 generate_stack_overflow_check(stack_bang_size);
6329
6330 // We always push rbp, so that on return to interpreter rbp, will be
6331 // restored correctly and we can correct the stack.
6332 push(rbp);
6333 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6334 if (PreserveFramePointer) {
6335 mov(rbp, rsp);
6336 }
6337 // Remove word for ebp
6338 framesize -= wordSize;
6339
6340 // Create frame
6341 if (framesize) {
6342 subptr(rsp, framesize);
6343 }
6344 } else {
6345 // Create frame (force generation of a 4 byte immediate value)
6346 subptr_imm32(rsp, framesize);
6347
6348 // Save RBP register now.
6349 framesize -= wordSize;
6350 movptr(Address(rsp, framesize), rbp);
6351 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6352 if (PreserveFramePointer) {
6353 movptr(rbp, rsp);
6354 if (framesize > 0) {
6355 addptr(rbp, framesize);
6356 }
6357 }
6358 }
6359
6360 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6361 framesize -= wordSize;
6362 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6363 }
6364
6365 #ifndef _LP64
6366 // If method sets FPU control word do it now
6367 if (fp_mode_24b) {
6368 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6369 }
6370 if (UseSSE >= 2 && VerifyFPU) {
6371 verify_FPU(0, "FPU stack must be clean on entry");
6372 }
6373 #endif
6374
6375 #ifdef ASSERT
6376 if (VerifyStackAtCalls) {
6377 Label L;
6378 push(rax);
6379 mov(rax, rsp);
6380 andptr(rax, StackAlignmentInBytes-1);
6381 cmpptr(rax, StackAlignmentInBytes-wordSize);
6382 pop(rax);
6383 jcc(Assembler::equal, L);
6384 STOP("Stack is not properly aligned!");
6385 bind(L);
6386 }
6387 #endif
6388
6389 }
6390
6391 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6392 // cnt - number of qwords (8-byte words).
6393 // base - start address, qword aligned.
6394 assert(base==rdi, "base register must be edi for rep stos");
6395 assert(tmp==rax, "tmp register must be eax for rep stos");
6396 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6397
6398 xorptr(tmp, tmp);
6399 if (UseFastStosb) {
6400 shlptr(cnt,3); // convert to number of bytes
6401 rep_stosb();
6402 } else {
6403 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6404 rep_stos();
6405 }
6406 }
6407
6408 // IndexOf for constant substrings with size >= 8 chars
6409 // which don't need to be loaded through stack.
6410 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6411 Register cnt1, Register cnt2,
6412 int int_cnt2, Register result,
6413 XMMRegister vec, Register tmp) {
6414 ShortBranchVerifier sbv(this);
6415 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6416
6417 // This method uses pcmpestri inxtruction with bound registers
6418 // inputs:
6419 // xmm - substring
6420 // rax - substring length (elements count)
6421 // mem - scanned string
6422 // rdx - string length (elements count)
6423 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6424 // outputs:
6425 // rcx - matched index in string
6426 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6427
6428 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6429 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6430 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6431
6432 // Note, inline_string_indexOf() generates checks:
6433 // if (substr.count > string.count) return -1;
6434 // if (substr.count == 0) return 0;
6435 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6436
6437 // Load substring.
6438 movdqu(vec, Address(str2, 0));
6439 movl(cnt2, int_cnt2);
6440 movptr(result, str1); // string addr
6441
6442 if (int_cnt2 > 8) {
6443 jmpb(SCAN_TO_SUBSTR);
6444
6445 // Reload substr for rescan, this code
6446 // is executed only for large substrings (> 8 chars)
6447 bind(RELOAD_SUBSTR);
6448 movdqu(vec, Address(str2, 0));
6449 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6450
6451 bind(RELOAD_STR);
6452 // We came here after the beginning of the substring was
6453 // matched but the rest of it was not so we need to search
6454 // again. Start from the next element after the previous match.
6455
6456 // cnt2 is number of substring reminding elements and
6457 // cnt1 is number of string reminding elements when cmp failed.
6458 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6459 subl(cnt1, cnt2);
6460 addl(cnt1, int_cnt2);
6461 movl(cnt2, int_cnt2); // Now restore cnt2
6462
6463 decrementl(cnt1); // Shift to next element
6464 cmpl(cnt1, cnt2);
6465 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6466
6467 addptr(result, 2);
6468
6469 } // (int_cnt2 > 8)
6470
6471 // Scan string for start of substr in 16-byte vectors
6472 bind(SCAN_TO_SUBSTR);
6473 pcmpestri(vec, Address(result, 0), 0x0d);
6474 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6475 subl(cnt1, 8);
6476 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6477 cmpl(cnt1, cnt2);
6478 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6479 addptr(result, 16);
6480 jmpb(SCAN_TO_SUBSTR);
6481
6482 // Found a potential substr
6483 bind(FOUND_CANDIDATE);
6484 // Matched whole vector if first element matched (tmp(rcx) == 0).
6485 if (int_cnt2 == 8) {
6486 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6487 } else { // int_cnt2 > 8
6488 jccb(Assembler::overflow, FOUND_SUBSTR);
6489 }
6490 // After pcmpestri tmp(rcx) contains matched element index
6491 // Compute start addr of substr
6492 lea(result, Address(result, tmp, Address::times_2));
6493
6494 // Make sure string is still long enough
6495 subl(cnt1, tmp);
6496 cmpl(cnt1, cnt2);
6497 if (int_cnt2 == 8) {
6498 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6499 } else { // int_cnt2 > 8
6500 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6501 }
6502 // Left less then substring.
6503
6504 bind(RET_NOT_FOUND);
6505 movl(result, -1);
6506 jmpb(EXIT);
6507
6508 if (int_cnt2 > 8) {
6509 // This code is optimized for the case when whole substring
6510 // is matched if its head is matched.
6511 bind(MATCH_SUBSTR_HEAD);
6512 pcmpestri(vec, Address(result, 0), 0x0d);
6513 // Reload only string if does not match
6514 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6515
6516 Label CONT_SCAN_SUBSTR;
6517 // Compare the rest of substring (> 8 chars).
6518 bind(FOUND_SUBSTR);
6519 // First 8 chars are already matched.
6520 negptr(cnt2);
6521 addptr(cnt2, 8);
6522
6523 bind(SCAN_SUBSTR);
6524 subl(cnt1, 8);
6525 cmpl(cnt2, -8); // Do not read beyond substring
6526 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6527 // Back-up strings to avoid reading beyond substring:
6528 // cnt1 = cnt1 - cnt2 + 8
6529 addl(cnt1, cnt2); // cnt2 is negative
6530 addl(cnt1, 8);
6531 movl(cnt2, 8); negptr(cnt2);
6532 bind(CONT_SCAN_SUBSTR);
6533 if (int_cnt2 < (int)G) {
6534 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6535 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6536 } else {
6537 // calculate index in register to avoid integer overflow (int_cnt2*2)
6538 movl(tmp, int_cnt2);
6539 addptr(tmp, cnt2);
6540 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6541 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6542 }
6543 // Need to reload strings pointers if not matched whole vector
6544 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6545 addptr(cnt2, 8);
6546 jcc(Assembler::negative, SCAN_SUBSTR);
6547 // Fall through if found full substring
6548
6549 } // (int_cnt2 > 8)
6550
6551 bind(RET_FOUND);
6552 // Found result if we matched full small substring.
6553 // Compute substr offset
6554 subptr(result, str1);
6555 shrl(result, 1); // index
6556 bind(EXIT);
6557
6558 } // string_indexofC8
6559
6560 // Small strings are loaded through stack if they cross page boundary.
6561 void MacroAssembler::string_indexof(Register str1, Register str2,
6562 Register cnt1, Register cnt2,
6563 int int_cnt2, Register result,
6564 XMMRegister vec, Register tmp) {
6565 ShortBranchVerifier sbv(this);
6566 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6567 //
6568 // int_cnt2 is length of small (< 8 chars) constant substring
6569 // or (-1) for non constant substring in which case its length
6570 // is in cnt2 register.
6571 //
6572 // Note, inline_string_indexOf() generates checks:
6573 // if (substr.count > string.count) return -1;
6574 // if (substr.count == 0) return 0;
6575 //
6576 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6577
6578 // This method uses pcmpestri inxtruction with bound registers
6579 // inputs:
6580 // xmm - substring
6581 // rax - substring length (elements count)
6582 // mem - scanned string
6583 // rdx - string length (elements count)
6584 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6585 // outputs:
6586 // rcx - matched index in string
6587 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6588
6589 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6590 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6591 FOUND_CANDIDATE;
6592
6593 { //========================================================
6594 // We don't know where these strings are located
6595 // and we can't read beyond them. Load them through stack.
6596 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6597
6598 movptr(tmp, rsp); // save old SP
6599
6600 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6601 if (int_cnt2 == 1) { // One char
6602 load_unsigned_short(result, Address(str2, 0));
6603 movdl(vec, result); // move 32 bits
6604 } else if (int_cnt2 == 2) { // Two chars
6605 movdl(vec, Address(str2, 0)); // move 32 bits
6606 } else if (int_cnt2 == 4) { // Four chars
6607 movq(vec, Address(str2, 0)); // move 64 bits
6608 } else { // cnt2 = { 3, 5, 6, 7 }
6609 // Array header size is 12 bytes in 32-bit VM
6610 // + 6 bytes for 3 chars == 18 bytes,
6611 // enough space to load vec and shift.
6612 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6613 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6614 psrldq(vec, 16-(int_cnt2*2));
6615 }
6616 } else { // not constant substring
6617 cmpl(cnt2, 8);
6618 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6619
6620 // We can read beyond string if srt+16 does not cross page boundary
6621 // since heaps are aligned and mapped by pages.
6622 assert(os::vm_page_size() < (int)G, "default page should be small");
6623 movl(result, str2); // We need only low 32 bits
6624 andl(result, (os::vm_page_size()-1));
6625 cmpl(result, (os::vm_page_size()-16));
6626 jccb(Assembler::belowEqual, CHECK_STR);
6627
6628 // Move small strings to stack to allow load 16 bytes into vec.
6629 subptr(rsp, 16);
6630 int stk_offset = wordSize-2;
6631 push(cnt2);
6632
6633 bind(COPY_SUBSTR);
6634 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6635 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6636 decrement(cnt2);
6637 jccb(Assembler::notZero, COPY_SUBSTR);
6638
6639 pop(cnt2);
6640 movptr(str2, rsp); // New substring address
6641 } // non constant
6642
6643 bind(CHECK_STR);
6644 cmpl(cnt1, 8);
6645 jccb(Assembler::aboveEqual, BIG_STRINGS);
6646
6647 // Check cross page boundary.
6648 movl(result, str1); // We need only low 32 bits
6649 andl(result, (os::vm_page_size()-1));
6650 cmpl(result, (os::vm_page_size()-16));
6651 jccb(Assembler::belowEqual, BIG_STRINGS);
6652
6653 subptr(rsp, 16);
6654 int stk_offset = -2;
6655 if (int_cnt2 < 0) { // not constant
6656 push(cnt2);
6657 stk_offset += wordSize;
6658 }
6659 movl(cnt2, cnt1);
6660
6661 bind(COPY_STR);
6662 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6663 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6664 decrement(cnt2);
6665 jccb(Assembler::notZero, COPY_STR);
6666
6667 if (int_cnt2 < 0) { // not constant
6668 pop(cnt2);
6669 }
6670 movptr(str1, rsp); // New string address
6671
6672 bind(BIG_STRINGS);
6673 // Load substring.
6674 if (int_cnt2 < 0) { // -1
6675 movdqu(vec, Address(str2, 0));
6676 push(cnt2); // substr count
6677 push(str2); // substr addr
6678 push(str1); // string addr
6679 } else {
6680 // Small (< 8 chars) constant substrings are loaded already.
6681 movl(cnt2, int_cnt2);
6682 }
6683 push(tmp); // original SP
6684
6685 } // Finished loading
6686
6687 //========================================================
6688 // Start search
6689 //
6690
6691 movptr(result, str1); // string addr
6692
6693 if (int_cnt2 < 0) { // Only for non constant substring
6694 jmpb(SCAN_TO_SUBSTR);
6695
6696 // SP saved at sp+0
6697 // String saved at sp+1*wordSize
6698 // Substr saved at sp+2*wordSize
6699 // Substr count saved at sp+3*wordSize
6700
6701 // Reload substr for rescan, this code
6702 // is executed only for large substrings (> 8 chars)
6703 bind(RELOAD_SUBSTR);
6704 movptr(str2, Address(rsp, 2*wordSize));
6705 movl(cnt2, Address(rsp, 3*wordSize));
6706 movdqu(vec, Address(str2, 0));
6707 // We came here after the beginning of the substring was
6708 // matched but the rest of it was not so we need to search
6709 // again. Start from the next element after the previous match.
6710 subptr(str1, result); // Restore counter
6711 shrl(str1, 1);
6712 addl(cnt1, str1);
6713 decrementl(cnt1); // Shift to next element
6714 cmpl(cnt1, cnt2);
6715 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6716
6717 addptr(result, 2);
6718 } // non constant
6719
6720 // Scan string for start of substr in 16-byte vectors
6721 bind(SCAN_TO_SUBSTR);
6722 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6723 pcmpestri(vec, Address(result, 0), 0x0d);
6724 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6725 subl(cnt1, 8);
6726 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6727 cmpl(cnt1, cnt2);
6728 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6729 addptr(result, 16);
6730
6731 bind(ADJUST_STR);
6732 cmpl(cnt1, 8); // Do not read beyond string
6733 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6734 // Back-up string to avoid reading beyond string.
6735 lea(result, Address(result, cnt1, Address::times_2, -16));
6736 movl(cnt1, 8);
6737 jmpb(SCAN_TO_SUBSTR);
6738
6739 // Found a potential substr
6740 bind(FOUND_CANDIDATE);
6741 // After pcmpestri tmp(rcx) contains matched element index
6742
6743 // Make sure string is still long enough
6744 subl(cnt1, tmp);
6745 cmpl(cnt1, cnt2);
6746 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6747 // Left less then substring.
6748
6749 bind(RET_NOT_FOUND);
6750 movl(result, -1);
6751 jmpb(CLEANUP);
6752
6753 bind(FOUND_SUBSTR);
6754 // Compute start addr of substr
6755 lea(result, Address(result, tmp, Address::times_2));
6756
6757 if (int_cnt2 > 0) { // Constant substring
6758 // Repeat search for small substring (< 8 chars)
6759 // from new point without reloading substring.
6760 // Have to check that we don't read beyond string.
6761 cmpl(tmp, 8-int_cnt2);
6762 jccb(Assembler::greater, ADJUST_STR);
6763 // Fall through if matched whole substring.
6764 } else { // non constant
6765 assert(int_cnt2 == -1, "should be != 0");
6766
6767 addl(tmp, cnt2);
6768 // Found result if we matched whole substring.
6769 cmpl(tmp, 8);
6770 jccb(Assembler::lessEqual, RET_FOUND);
6771
6772 // Repeat search for small substring (<= 8 chars)
6773 // from new point 'str1' without reloading substring.
6774 cmpl(cnt2, 8);
6775 // Have to check that we don't read beyond string.
6776 jccb(Assembler::lessEqual, ADJUST_STR);
6777
6778 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6779 // Compare the rest of substring (> 8 chars).
6780 movptr(str1, result);
6781
6782 cmpl(tmp, cnt2);
6783 // First 8 chars are already matched.
6784 jccb(Assembler::equal, CHECK_NEXT);
6785
6786 bind(SCAN_SUBSTR);
6787 pcmpestri(vec, Address(str1, 0), 0x0d);
6788 // Need to reload strings pointers if not matched whole vector
6789 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6790
6791 bind(CHECK_NEXT);
6792 subl(cnt2, 8);
6793 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6794 addptr(str1, 16);
6795 addptr(str2, 16);
6796 subl(cnt1, 8);
6797 cmpl(cnt2, 8); // Do not read beyond substring
6798 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6799 // Back-up strings to avoid reading beyond substring.
6800 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6801 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6802 subl(cnt1, cnt2);
6803 movl(cnt2, 8);
6804 addl(cnt1, 8);
6805 bind(CONT_SCAN_SUBSTR);
6806 movdqu(vec, Address(str2, 0));
6807 jmpb(SCAN_SUBSTR);
6808
6809 bind(RET_FOUND_LONG);
6810 movptr(str1, Address(rsp, wordSize));
6811 } // non constant
6812
6813 bind(RET_FOUND);
6814 // Compute substr offset
6815 subptr(result, str1);
6816 shrl(result, 1); // index
6817
6818 bind(CLEANUP);
6819 pop(rsp); // restore SP
6820
6821 } // string_indexof
6822
6823 // Compare strings.
6824 void MacroAssembler::string_compare(Register str1, Register str2,
6825 Register cnt1, Register cnt2, Register result,
6826 XMMRegister vec1) {
6827 ShortBranchVerifier sbv(this);
6828 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6829
6830 // Compute the minimum of the string lengths and the
6831 // difference of the string lengths (stack).
6832 // Do the conditional move stuff
6833 movl(result, cnt1);
6834 subl(cnt1, cnt2);
6835 push(cnt1);
6836 cmov32(Assembler::lessEqual, cnt2, result);
6837
6838 // Is the minimum length zero?
6839 testl(cnt2, cnt2);
6840 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6841
6842 // Compare first characters
6843 load_unsigned_short(result, Address(str1, 0));
6844 load_unsigned_short(cnt1, Address(str2, 0));
6845 subl(result, cnt1);
6846 jcc(Assembler::notZero, POP_LABEL);
6847 cmpl(cnt2, 1);
6848 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6849
6850 // Check if the strings start at the same location.
6851 cmpptr(str1, str2);
6852 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6853
6854 Address::ScaleFactor scale = Address::times_2;
6855 int stride = 8;
6856
6857 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6858 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6859 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6860 Label COMPARE_TAIL_LONG;
6861 int pcmpmask = 0x19;
6862
6863 // Setup to compare 16-chars (32-bytes) vectors,
6864 // start from first character again because it has aligned address.
6865 int stride2 = 16;
6866 int adr_stride = stride << scale;
6867 int adr_stride2 = stride2 << scale;
6868
6869 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6870 // rax and rdx are used by pcmpestri as elements counters
6871 movl(result, cnt2);
6872 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6873 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6874
6875 // fast path : compare first 2 8-char vectors.
6876 bind(COMPARE_16_CHARS);
6877 movdqu(vec1, Address(str1, 0));
6878 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6879 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6880
6881 movdqu(vec1, Address(str1, adr_stride));
6882 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6883 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6884 addl(cnt1, stride);
6885
6886 // Compare the characters at index in cnt1
6887 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6888 load_unsigned_short(result, Address(str1, cnt1, scale));
6889 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6890 subl(result, cnt2);
6891 jmp(POP_LABEL);
6892
6893 // Setup the registers to start vector comparison loop
6894 bind(COMPARE_WIDE_VECTORS);
6895 lea(str1, Address(str1, result, scale));
6896 lea(str2, Address(str2, result, scale));
6897 subl(result, stride2);
6898 subl(cnt2, stride2);
6899 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6900 negptr(result);
6901
6902 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6903 bind(COMPARE_WIDE_VECTORS_LOOP);
6904 vmovdqu(vec1, Address(str1, result, scale));
6905 vpxor(vec1, Address(str2, result, scale));
6906 vptest(vec1, vec1);
6907 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6908 addptr(result, stride2);
6909 subl(cnt2, stride2);
6910 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6911 // clean upper bits of YMM registers
6912 vpxor(vec1, vec1);
6913
6914 // compare wide vectors tail
6915 bind(COMPARE_WIDE_TAIL);
6916 testptr(result, result);
6917 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6918
6919 movl(result, stride2);
6920 movl(cnt2, result);
6921 negptr(result);
6922 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6923
6924 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6925 bind(VECTOR_NOT_EQUAL);
6926 // clean upper bits of YMM registers
6927 vpxor(vec1, vec1);
6928 lea(str1, Address(str1, result, scale));
6929 lea(str2, Address(str2, result, scale));
6930 jmp(COMPARE_16_CHARS);
6931
6932 // Compare tail chars, length between 1 to 15 chars
6933 bind(COMPARE_TAIL_LONG);
6934 movl(cnt2, result);
6935 cmpl(cnt2, stride);
6936 jccb(Assembler::less, COMPARE_SMALL_STR);
6937
6938 movdqu(vec1, Address(str1, 0));
6939 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6940 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6941 subptr(cnt2, stride);
6942 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6943 lea(str1, Address(str1, result, scale));
6944 lea(str2, Address(str2, result, scale));
6945 negptr(cnt2);
6946 jmpb(WHILE_HEAD_LABEL);
6947
6948 bind(COMPARE_SMALL_STR);
6949 } else if (UseSSE42Intrinsics) {
6950 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6951 int pcmpmask = 0x19;
6952 // Setup to compare 8-char (16-byte) vectors,
6953 // start from first character again because it has aligned address.
6954 movl(result, cnt2);
6955 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6956 jccb(Assembler::zero, COMPARE_TAIL);
6957
6958 lea(str1, Address(str1, result, scale));
6959 lea(str2, Address(str2, result, scale));
6960 negptr(result);
6961
6962 // pcmpestri
6963 // inputs:
6964 // vec1- substring
6965 // rax - negative string length (elements count)
6966 // mem - scaned string
6967 // rdx - string length (elements count)
6968 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6969 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6970 // outputs:
6971 // rcx - first mismatched element index
6972 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6973
6974 bind(COMPARE_WIDE_VECTORS);
6975 movdqu(vec1, Address(str1, result, scale));
6976 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6977 // After pcmpestri cnt1(rcx) contains mismatched element index
6978
6979 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6980 addptr(result, stride);
6981 subptr(cnt2, stride);
6982 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6983
6984 // compare wide vectors tail
6985 testptr(result, result);
6986 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6987
6988 movl(cnt2, stride);
6989 movl(result, stride);
6990 negptr(result);
6991 movdqu(vec1, Address(str1, result, scale));
6992 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6993 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6994
6995 // Mismatched characters in the vectors
6996 bind(VECTOR_NOT_EQUAL);
6997 addptr(cnt1, result);
6998 load_unsigned_short(result, Address(str1, cnt1, scale));
6999 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
7000 subl(result, cnt2);
7001 jmpb(POP_LABEL);
7002
7003 bind(COMPARE_TAIL); // limit is zero
7004 movl(cnt2, result);
7005 // Fallthru to tail compare
7006 }
7007 // Shift str2 and str1 to the end of the arrays, negate min
7008 lea(str1, Address(str1, cnt2, scale));
7009 lea(str2, Address(str2, cnt2, scale));
7010 decrementl(cnt2); // first character was compared already
7011 negptr(cnt2);
7012
7013 // Compare the rest of the elements
7014 bind(WHILE_HEAD_LABEL);
7015 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
7016 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
7017 subl(result, cnt1);
7018 jccb(Assembler::notZero, POP_LABEL);
7019 increment(cnt2);
7020 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7021
7022 // Strings are equal up to min length. Return the length difference.
7023 bind(LENGTH_DIFF_LABEL);
7024 pop(result);
7025 jmpb(DONE_LABEL);
7026
7027 // Discard the stored length difference
7028 bind(POP_LABEL);
7029 pop(cnt1);
7030
7031 // That's it
7032 bind(DONE_LABEL);
7033 }
7034
7035 // Compare char[] arrays aligned to 4 bytes or substrings.
7036 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7037 Register limit, Register result, Register chr,
7038 XMMRegister vec1, XMMRegister vec2) {
7039 ShortBranchVerifier sbv(this);
7040 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
7041
7042 int length_offset = arrayOopDesc::length_offset_in_bytes();
7043 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
7044
7045 // Check the input args
7046 if (is_array_equ) {
7047 cmpoops(ary1, ary2);
7048 } else {
7049 cmpptr(ary1, ary2);
7050 }
7051 jcc(Assembler::equal, TRUE_LABEL);
7052
7053 if (is_array_equ) {
7054 // Need additional checks for arrays_equals.
7055 testptr(ary1, ary1);
7056 jcc(Assembler::zero, FALSE_LABEL);
7057 testptr(ary2, ary2);
7058 jcc(Assembler::zero, FALSE_LABEL);
7059
7060 // Check the lengths
7061 movl(limit, Address(ary1, length_offset));
7062 cmpl(limit, Address(ary2, length_offset));
7063 jcc(Assembler::notEqual, FALSE_LABEL);
7064 }
7065
7066 // count == 0
7067 testl(limit, limit);
7068 jcc(Assembler::zero, TRUE_LABEL);
7069
7070 if (is_array_equ) {
7071 // Load array address
7072 lea(ary1, Address(ary1, base_offset));
7073 lea(ary2, Address(ary2, base_offset));
7074 }
7075
7076 shll(limit, 1); // byte count != 0
7077 movl(result, limit); // copy
7078
7079 if (UseAVX >= 2) {
7080 // With AVX2, use 32-byte vector compare
7081 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7082
7083 // Compare 32-byte vectors
7084 andl(result, 0x0000001e); // tail count (in bytes)
7085 andl(limit, 0xffffffe0); // vector count (in bytes)
7086 jccb(Assembler::zero, COMPARE_TAIL);
7087
7088 lea(ary1, Address(ary1, limit, Address::times_1));
7089 lea(ary2, Address(ary2, limit, Address::times_1));
7090 negptr(limit);
7091
7092 bind(COMPARE_WIDE_VECTORS);
7093 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7094 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7095 vpxor(vec1, vec2);
7096
7097 vptest(vec1, vec1);
7098 jccb(Assembler::notZero, FALSE_LABEL);
7099 addptr(limit, 32);
7100 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7101
7102 testl(result, result);
7103 jccb(Assembler::zero, TRUE_LABEL);
7104
7105 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7106 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7107 vpxor(vec1, vec2);
7108
7109 vptest(vec1, vec1);
7110 jccb(Assembler::notZero, FALSE_LABEL);
7111 jmpb(TRUE_LABEL);
7112
7113 bind(COMPARE_TAIL); // limit is zero
7114 movl(limit, result);
7115 // Fallthru to tail compare
7116 } else if (UseSSE42Intrinsics) {
7117 // With SSE4.2, use double quad vector compare
7118 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7119
7120 // Compare 16-byte vectors
7121 andl(result, 0x0000000e); // tail count (in bytes)
7122 andl(limit, 0xfffffff0); // vector count (in bytes)
7123 jccb(Assembler::zero, COMPARE_TAIL);
7124
7125 lea(ary1, Address(ary1, limit, Address::times_1));
7126 lea(ary2, Address(ary2, limit, Address::times_1));
7127 negptr(limit);
7128
7129 bind(COMPARE_WIDE_VECTORS);
7130 movdqu(vec1, Address(ary1, limit, Address::times_1));
7131 movdqu(vec2, Address(ary2, limit, Address::times_1));
7132 pxor(vec1, vec2);
7133
7134 ptest(vec1, vec1);
7135 jccb(Assembler::notZero, FALSE_LABEL);
7136 addptr(limit, 16);
7137 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7138
7139 testl(result, result);
7140 jccb(Assembler::zero, TRUE_LABEL);
7141
7142 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7143 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7144 pxor(vec1, vec2);
7145
7146 ptest(vec1, vec1);
7147 jccb(Assembler::notZero, FALSE_LABEL);
7148 jmpb(TRUE_LABEL);
7149
7150 bind(COMPARE_TAIL); // limit is zero
7151 movl(limit, result);
7152 // Fallthru to tail compare
7153 }
7154
7155 // Compare 4-byte vectors
7156 andl(limit, 0xfffffffc); // vector count (in bytes)
7157 jccb(Assembler::zero, COMPARE_CHAR);
7158
7159 lea(ary1, Address(ary1, limit, Address::times_1));
7160 lea(ary2, Address(ary2, limit, Address::times_1));
7161 negptr(limit);
7162
7163 bind(COMPARE_VECTORS);
7164 movl(chr, Address(ary1, limit, Address::times_1));
7165 cmpl(chr, Address(ary2, limit, Address::times_1));
7166 jccb(Assembler::notEqual, FALSE_LABEL);
7167 addptr(limit, 4);
7168 jcc(Assembler::notZero, COMPARE_VECTORS);
7169
7170 // Compare trailing char (final 2 bytes), if any
7171 bind(COMPARE_CHAR);
7172 testl(result, 0x2); // tail char
7173 jccb(Assembler::zero, TRUE_LABEL);
7174 load_unsigned_short(chr, Address(ary1, 0));
7175 load_unsigned_short(limit, Address(ary2, 0));
7176 cmpl(chr, limit);
7177 jccb(Assembler::notEqual, FALSE_LABEL);
7178
7179 bind(TRUE_LABEL);
7180 movl(result, 1); // return true
7181 jmpb(DONE);
7182
7183 bind(FALSE_LABEL);
7184 xorl(result, result); // return false
7185
7186 // That's it
7187 bind(DONE);
7188 if (UseAVX >= 2) {
7189 // clean upper bits of YMM registers
7190 vpxor(vec1, vec1);
7191 vpxor(vec2, vec2);
7192 }
7193 }
7194
7195 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7196 Register to, Register value, Register count,
7197 Register rtmp, XMMRegister xtmp) {
7198 ShortBranchVerifier sbv(this);
7199 assert_different_registers(to, value, count, rtmp);
7200 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7201 Label L_fill_2_bytes, L_fill_4_bytes;
7202
7203 int shift = -1;
7204 switch (t) {
7205 case T_BYTE:
7206 shift = 2;
7207 break;
7208 case T_SHORT:
7209 shift = 1;
7210 break;
7211 case T_INT:
7212 shift = 0;
7213 break;
7214 default: ShouldNotReachHere();
7215 }
7216
7217 if (t == T_BYTE) {
7218 andl(value, 0xff);
7219 movl(rtmp, value);
7220 shll(rtmp, 8);
7221 orl(value, rtmp);
7222 }
7223 if (t == T_SHORT) {
7224 andl(value, 0xffff);
7225 }
7226 if (t == T_BYTE || t == T_SHORT) {
7227 movl(rtmp, value);
7228 shll(rtmp, 16);
7229 orl(value, rtmp);
7230 }
7231
7232 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7233 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7234 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7235 // align source address at 4 bytes address boundary
7236 if (t == T_BYTE) {
7237 // One byte misalignment happens only for byte arrays
7238 testptr(to, 1);
7239 jccb(Assembler::zero, L_skip_align1);
7240 movb(Address(to, 0), value);
7241 increment(to);
7242 decrement(count);
7243 BIND(L_skip_align1);
7244 }
7245 // Two bytes misalignment happens only for byte and short (char) arrays
7246 testptr(to, 2);
7247 jccb(Assembler::zero, L_skip_align2);
7248 movw(Address(to, 0), value);
7249 addptr(to, 2);
7250 subl(count, 1<<(shift-1));
7251 BIND(L_skip_align2);
7252 }
7253 if (UseSSE < 2) {
7254 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7255 // Fill 32-byte chunks
7256 subl(count, 8 << shift);
7257 jcc(Assembler::less, L_check_fill_8_bytes);
7258 align(16);
7259
7260 BIND(L_fill_32_bytes_loop);
7261
7262 for (int i = 0; i < 32; i += 4) {
7263 movl(Address(to, i), value);
7264 }
7265
7266 addptr(to, 32);
7267 subl(count, 8 << shift);
7268 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7269 BIND(L_check_fill_8_bytes);
7270 addl(count, 8 << shift);
7271 jccb(Assembler::zero, L_exit);
7272 jmpb(L_fill_8_bytes);
7273
7274 //
7275 // length is too short, just fill qwords
7276 //
7277 BIND(L_fill_8_bytes_loop);
7278 movl(Address(to, 0), value);
7279 movl(Address(to, 4), value);
7280 addptr(to, 8);
7281 BIND(L_fill_8_bytes);
7282 subl(count, 1 << (shift + 1));
7283 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7284 // fall through to fill 4 bytes
7285 } else {
7286 Label L_fill_32_bytes;
7287 if (!UseUnalignedLoadStores) {
7288 // align to 8 bytes, we know we are 4 byte aligned to start
7289 testptr(to, 4);
7290 jccb(Assembler::zero, L_fill_32_bytes);
7291 movl(Address(to, 0), value);
7292 addptr(to, 4);
7293 subl(count, 1<<shift);
7294 }
7295 BIND(L_fill_32_bytes);
7296 {
7297 assert( UseSSE >= 2, "supported cpu only" );
7298 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7299 movdl(xtmp, value);
7300 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7301 // Fill 64-byte chunks
7302 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7303 vpbroadcastd(xtmp, xtmp);
7304
7305 subl(count, 16 << shift);
7306 jcc(Assembler::less, L_check_fill_32_bytes);
7307 align(16);
7308
7309 BIND(L_fill_64_bytes_loop);
7310 vmovdqu(Address(to, 0), xtmp);
7311 vmovdqu(Address(to, 32), xtmp);
7312 addptr(to, 64);
7313 subl(count, 16 << shift);
7314 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7315
7316 BIND(L_check_fill_32_bytes);
7317 addl(count, 8 << shift);
7318 jccb(Assembler::less, L_check_fill_8_bytes);
7319 vmovdqu(Address(to, 0), xtmp);
7320 addptr(to, 32);
7321 subl(count, 8 << shift);
7322
7323 BIND(L_check_fill_8_bytes);
7324 // clean upper bits of YMM registers
7325 movdl(xtmp, value);
7326 pshufd(xtmp, xtmp, 0);
7327 } else {
7328 // Fill 32-byte chunks
7329 pshufd(xtmp, xtmp, 0);
7330
7331 subl(count, 8 << shift);
7332 jcc(Assembler::less, L_check_fill_8_bytes);
7333 align(16);
7334
7335 BIND(L_fill_32_bytes_loop);
7336
7337 if (UseUnalignedLoadStores) {
7338 movdqu(Address(to, 0), xtmp);
7339 movdqu(Address(to, 16), xtmp);
7340 } else {
7341 movq(Address(to, 0), xtmp);
7342 movq(Address(to, 8), xtmp);
7343 movq(Address(to, 16), xtmp);
7344 movq(Address(to, 24), xtmp);
7345 }
7346
7347 addptr(to, 32);
7348 subl(count, 8 << shift);
7349 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7350
7351 BIND(L_check_fill_8_bytes);
7352 }
7353 addl(count, 8 << shift);
7354 jccb(Assembler::zero, L_exit);
7355 jmpb(L_fill_8_bytes);
7356
7357 //
7358 // length is too short, just fill qwords
7359 //
7360 BIND(L_fill_8_bytes_loop);
7361 movq(Address(to, 0), xtmp);
7362 addptr(to, 8);
7363 BIND(L_fill_8_bytes);
7364 subl(count, 1 << (shift + 1));
7365 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7366 }
7367 }
7368 // fill trailing 4 bytes
7369 BIND(L_fill_4_bytes);
7370 testl(count, 1<<shift);
7371 jccb(Assembler::zero, L_fill_2_bytes);
7372 movl(Address(to, 0), value);
7373 if (t == T_BYTE || t == T_SHORT) {
7374 addptr(to, 4);
7375 BIND(L_fill_2_bytes);
7376 // fill trailing 2 bytes
7377 testl(count, 1<<(shift-1));
7378 jccb(Assembler::zero, L_fill_byte);
7379 movw(Address(to, 0), value);
7380 if (t == T_BYTE) {
7381 addptr(to, 2);
7382 BIND(L_fill_byte);
7383 // fill trailing byte
7384 testl(count, 1);
7385 jccb(Assembler::zero, L_exit);
7386 movb(Address(to, 0), value);
7387 } else {
7388 BIND(L_fill_byte);
7389 }
7390 } else {
7391 BIND(L_fill_2_bytes);
7392 }
7393 BIND(L_exit);
7394 }
7395
7396 // encode char[] to byte[] in ISO_8859_1
7397 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7398 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7399 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7400 Register tmp5, Register result) {
7401 // rsi: src
7402 // rdi: dst
7403 // rdx: len
7404 // rcx: tmp5
7405 // rax: result
7406 ShortBranchVerifier sbv(this);
7407 assert_different_registers(src, dst, len, tmp5, result);
7408 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7409
7410 // set result
7411 xorl(result, result);
7412 // check for zero length
7413 testl(len, len);
7414 jcc(Assembler::zero, L_done);
7415 movl(result, len);
7416
7417 // Setup pointers
7418 lea(src, Address(src, len, Address::times_2)); // char[]
7419 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7420 negptr(len);
7421
7422 if (UseSSE42Intrinsics || UseAVX >= 2) {
7423 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7424 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7425
7426 if (UseAVX >= 2) {
7427 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7428 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7429 movdl(tmp1Reg, tmp5);
7430 vpbroadcastd(tmp1Reg, tmp1Reg);
7431 jmpb(L_chars_32_check);
7432
7433 bind(L_copy_32_chars);
7434 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7435 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7436 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7437 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7438 jccb(Assembler::notZero, L_copy_32_chars_exit);
7439 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7440 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7441 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7442
7443 bind(L_chars_32_check);
7444 addptr(len, 32);
7445 jccb(Assembler::lessEqual, L_copy_32_chars);
7446
7447 bind(L_copy_32_chars_exit);
7448 subptr(len, 16);
7449 jccb(Assembler::greater, L_copy_16_chars_exit);
7450
7451 } else if (UseSSE42Intrinsics) {
7452 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7453 movdl(tmp1Reg, tmp5);
7454 pshufd(tmp1Reg, tmp1Reg, 0);
7455 jmpb(L_chars_16_check);
7456 }
7457
7458 bind(L_copy_16_chars);
7459 if (UseAVX >= 2) {
7460 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7461 vptest(tmp2Reg, tmp1Reg);
7462 jccb(Assembler::notZero, L_copy_16_chars_exit);
7463 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7464 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7465 } else {
7466 if (UseAVX > 0) {
7467 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7468 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7469 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7470 } else {
7471 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7472 por(tmp2Reg, tmp3Reg);
7473 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7474 por(tmp2Reg, tmp4Reg);
7475 }
7476 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7477 jccb(Assembler::notZero, L_copy_16_chars_exit);
7478 packuswb(tmp3Reg, tmp4Reg);
7479 }
7480 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7481
7482 bind(L_chars_16_check);
7483 addptr(len, 16);
7484 jccb(Assembler::lessEqual, L_copy_16_chars);
7485
7486 bind(L_copy_16_chars_exit);
7487 if (UseAVX >= 2) {
7488 // clean upper bits of YMM registers
7489 vpxor(tmp2Reg, tmp2Reg);
7490 vpxor(tmp3Reg, tmp3Reg);
7491 vpxor(tmp4Reg, tmp4Reg);
7492 movdl(tmp1Reg, tmp5);
7493 pshufd(tmp1Reg, tmp1Reg, 0);
7494 }
7495 subptr(len, 8);
7496 jccb(Assembler::greater, L_copy_8_chars_exit);
7497
7498 bind(L_copy_8_chars);
7499 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7500 ptest(tmp3Reg, tmp1Reg);
7501 jccb(Assembler::notZero, L_copy_8_chars_exit);
7502 packuswb(tmp3Reg, tmp1Reg);
7503 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7504 addptr(len, 8);
7505 jccb(Assembler::lessEqual, L_copy_8_chars);
7506
7507 bind(L_copy_8_chars_exit);
7508 subptr(len, 8);
7509 jccb(Assembler::zero, L_done);
7510 }
7511
7512 bind(L_copy_1_char);
7513 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7514 testl(tmp5, 0xff00); // check if Unicode char
7515 jccb(Assembler::notZero, L_copy_1_char_exit);
7516 movb(Address(dst, len, Address::times_1, 0), tmp5);
7517 addptr(len, 1);
7518 jccb(Assembler::less, L_copy_1_char);
7519
7520 bind(L_copy_1_char_exit);
7521 addptr(result, len); // len is negative count of not processed elements
7522 bind(L_done);
7523 }
7524
7525 #ifdef _LP64
7526 /**
7527 * Helper for multiply_to_len().
7528 */
7529 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7530 addq(dest_lo, src1);
7531 adcq(dest_hi, 0);
7532 addq(dest_lo, src2);
7533 adcq(dest_hi, 0);
7534 }
7535
7536 /**
7537 * Multiply 64 bit by 64 bit first loop.
7538 */
7539 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7540 Register y, Register y_idx, Register z,
7541 Register carry, Register product,
7542 Register idx, Register kdx) {
7543 //
7544 // jlong carry, x[], y[], z[];
7545 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7546 // huge_128 product = y[idx] * x[xstart] + carry;
7547 // z[kdx] = (jlong)product;
7548 // carry = (jlong)(product >>> 64);
7549 // }
7550 // z[xstart] = carry;
7551 //
7552
7553 Label L_first_loop, L_first_loop_exit;
7554 Label L_one_x, L_one_y, L_multiply;
7555
7556 decrementl(xstart);
7557 jcc(Assembler::negative, L_one_x);
7558
7559 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7560 rorq(x_xstart, 32); // convert big-endian to little-endian
7561
7562 bind(L_first_loop);
7563 decrementl(idx);
7564 jcc(Assembler::negative, L_first_loop_exit);
7565 decrementl(idx);
7566 jcc(Assembler::negative, L_one_y);
7567 movq(y_idx, Address(y, idx, Address::times_4, 0));
7568 rorq(y_idx, 32); // convert big-endian to little-endian
7569 bind(L_multiply);
7570 movq(product, x_xstart);
7571 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7572 addq(product, carry);
7573 adcq(rdx, 0);
7574 subl(kdx, 2);
7575 movl(Address(z, kdx, Address::times_4, 4), product);
7576 shrq(product, 32);
7577 movl(Address(z, kdx, Address::times_4, 0), product);
7578 movq(carry, rdx);
7579 jmp(L_first_loop);
7580
7581 bind(L_one_y);
7582 movl(y_idx, Address(y, 0));
7583 jmp(L_multiply);
7584
7585 bind(L_one_x);
7586 movl(x_xstart, Address(x, 0));
7587 jmp(L_first_loop);
7588
7589 bind(L_first_loop_exit);
7590 }
7591
7592 /**
7593 * Multiply 64 bit by 64 bit and add 128 bit.
7594 */
7595 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7596 Register yz_idx, Register idx,
7597 Register carry, Register product, int offset) {
7598 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7599 // z[kdx] = (jlong)product;
7600
7601 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7602 rorq(yz_idx, 32); // convert big-endian to little-endian
7603 movq(product, x_xstart);
7604 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7605 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7606 rorq(yz_idx, 32); // convert big-endian to little-endian
7607
7608 add2_with_carry(rdx, product, carry, yz_idx);
7609
7610 movl(Address(z, idx, Address::times_4, offset+4), product);
7611 shrq(product, 32);
7612 movl(Address(z, idx, Address::times_4, offset), product);
7613
7614 }
7615
7616 /**
7617 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7618 */
7619 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7620 Register yz_idx, Register idx, Register jdx,
7621 Register carry, Register product,
7622 Register carry2) {
7623 // jlong carry, x[], y[], z[];
7624 // int kdx = ystart+1;
7625 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7626 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7627 // z[kdx+idx+1] = (jlong)product;
7628 // jlong carry2 = (jlong)(product >>> 64);
7629 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7630 // z[kdx+idx] = (jlong)product;
7631 // carry = (jlong)(product >>> 64);
7632 // }
7633 // idx += 2;
7634 // if (idx > 0) {
7635 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7636 // z[kdx+idx] = (jlong)product;
7637 // carry = (jlong)(product >>> 64);
7638 // }
7639 //
7640
7641 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7642
7643 movl(jdx, idx);
7644 andl(jdx, 0xFFFFFFFC);
7645 shrl(jdx, 2);
7646
7647 bind(L_third_loop);
7648 subl(jdx, 1);
7649 jcc(Assembler::negative, L_third_loop_exit);
7650 subl(idx, 4);
7651
7652 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7653 movq(carry2, rdx);
7654
7655 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7656 movq(carry, rdx);
7657 jmp(L_third_loop);
7658
7659 bind (L_third_loop_exit);
7660
7661 andl (idx, 0x3);
7662 jcc(Assembler::zero, L_post_third_loop_done);
7663
7664 Label L_check_1;
7665 subl(idx, 2);
7666 jcc(Assembler::negative, L_check_1);
7667
7668 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7669 movq(carry, rdx);
7670
7671 bind (L_check_1);
7672 addl (idx, 0x2);
7673 andl (idx, 0x1);
7674 subl(idx, 1);
7675 jcc(Assembler::negative, L_post_third_loop_done);
7676
7677 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7678 movq(product, x_xstart);
7679 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7680 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7681
7682 add2_with_carry(rdx, product, yz_idx, carry);
7683
7684 movl(Address(z, idx, Address::times_4, 0), product);
7685 shrq(product, 32);
7686
7687 shlq(rdx, 32);
7688 orq(product, rdx);
7689 movq(carry, product);
7690
7691 bind(L_post_third_loop_done);
7692 }
7693
7694 /**
7695 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7696 *
7697 */
7698 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7699 Register carry, Register carry2,
7700 Register idx, Register jdx,
7701 Register yz_idx1, Register yz_idx2,
7702 Register tmp, Register tmp3, Register tmp4) {
7703 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7704
7705 // jlong carry, x[], y[], z[];
7706 // int kdx = ystart+1;
7707 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7708 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7709 // jlong carry2 = (jlong)(tmp3 >>> 64);
7710 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7711 // carry = (jlong)(tmp4 >>> 64);
7712 // z[kdx+idx+1] = (jlong)tmp3;
7713 // z[kdx+idx] = (jlong)tmp4;
7714 // }
7715 // idx += 2;
7716 // if (idx > 0) {
7717 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7718 // z[kdx+idx] = (jlong)yz_idx1;
7719 // carry = (jlong)(yz_idx1 >>> 64);
7720 // }
7721 //
7722
7723 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7724
7725 movl(jdx, idx);
7726 andl(jdx, 0xFFFFFFFC);
7727 shrl(jdx, 2);
7728
7729 bind(L_third_loop);
7730 subl(jdx, 1);
7731 jcc(Assembler::negative, L_third_loop_exit);
7732 subl(idx, 4);
7733
7734 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7735 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7736 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7737 rorxq(yz_idx2, yz_idx2, 32);
7738
7739 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7740 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7741
7742 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7743 rorxq(yz_idx1, yz_idx1, 32);
7744 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7745 rorxq(yz_idx2, yz_idx2, 32);
7746
7747 if (VM_Version::supports_adx()) {
7748 adcxq(tmp3, carry);
7749 adoxq(tmp3, yz_idx1);
7750
7751 adcxq(tmp4, tmp);
7752 adoxq(tmp4, yz_idx2);
7753
7754 movl(carry, 0); // does not affect flags
7755 adcxq(carry2, carry);
7756 adoxq(carry2, carry);
7757 } else {
7758 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7759 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7760 }
7761 movq(carry, carry2);
7762
7763 movl(Address(z, idx, Address::times_4, 12), tmp3);
7764 shrq(tmp3, 32);
7765 movl(Address(z, idx, Address::times_4, 8), tmp3);
7766
7767 movl(Address(z, idx, Address::times_4, 4), tmp4);
7768 shrq(tmp4, 32);
7769 movl(Address(z, idx, Address::times_4, 0), tmp4);
7770
7771 jmp(L_third_loop);
7772
7773 bind (L_third_loop_exit);
7774
7775 andl (idx, 0x3);
7776 jcc(Assembler::zero, L_post_third_loop_done);
7777
7778 Label L_check_1;
7779 subl(idx, 2);
7780 jcc(Assembler::negative, L_check_1);
7781
7782 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7783 rorxq(yz_idx1, yz_idx1, 32);
7784 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7785 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7786 rorxq(yz_idx2, yz_idx2, 32);
7787
7788 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7789
7790 movl(Address(z, idx, Address::times_4, 4), tmp3);
7791 shrq(tmp3, 32);
7792 movl(Address(z, idx, Address::times_4, 0), tmp3);
7793 movq(carry, tmp4);
7794
7795 bind (L_check_1);
7796 addl (idx, 0x2);
7797 andl (idx, 0x1);
7798 subl(idx, 1);
7799 jcc(Assembler::negative, L_post_third_loop_done);
7800 movl(tmp4, Address(y, idx, Address::times_4, 0));
7801 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7802 movl(tmp4, Address(z, idx, Address::times_4, 0));
7803
7804 add2_with_carry(carry2, tmp3, tmp4, carry);
7805
7806 movl(Address(z, idx, Address::times_4, 0), tmp3);
7807 shrq(tmp3, 32);
7808
7809 shlq(carry2, 32);
7810 orq(tmp3, carry2);
7811 movq(carry, tmp3);
7812
7813 bind(L_post_third_loop_done);
7814 }
7815
7816 /**
7817 * Code for BigInteger::multiplyToLen() instrinsic.
7818 *
7819 * rdi: x
7820 * rax: xlen
7821 * rsi: y
7822 * rcx: ylen
7823 * r8: z
7824 * r11: zlen
7825 * r12: tmp1
7826 * r13: tmp2
7827 * r14: tmp3
7828 * r15: tmp4
7829 * rbx: tmp5
7830 *
7831 */
7832 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7833 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7834 ShortBranchVerifier sbv(this);
7835 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7836
7837 push(tmp1);
7838 push(tmp2);
7839 push(tmp3);
7840 push(tmp4);
7841 push(tmp5);
7842
7843 push(xlen);
7844 push(zlen);
7845
7846 const Register idx = tmp1;
7847 const Register kdx = tmp2;
7848 const Register xstart = tmp3;
7849
7850 const Register y_idx = tmp4;
7851 const Register carry = tmp5;
7852 const Register product = xlen;
7853 const Register x_xstart = zlen; // reuse register
7854
7855 // First Loop.
7856 //
7857 // final static long LONG_MASK = 0xffffffffL;
7858 // int xstart = xlen - 1;
7859 // int ystart = ylen - 1;
7860 // long carry = 0;
7861 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7862 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7863 // z[kdx] = (int)product;
7864 // carry = product >>> 32;
7865 // }
7866 // z[xstart] = (int)carry;
7867 //
7868
7869 movl(idx, ylen); // idx = ylen;
7870 movl(kdx, zlen); // kdx = xlen+ylen;
7871 xorq(carry, carry); // carry = 0;
7872
7873 Label L_done;
7874
7875 movl(xstart, xlen);
7876 decrementl(xstart);
7877 jcc(Assembler::negative, L_done);
7878
7879 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7880
7881 Label L_second_loop;
7882 testl(kdx, kdx);
7883 jcc(Assembler::zero, L_second_loop);
7884
7885 Label L_carry;
7886 subl(kdx, 1);
7887 jcc(Assembler::zero, L_carry);
7888
7889 movl(Address(z, kdx, Address::times_4, 0), carry);
7890 shrq(carry, 32);
7891 subl(kdx, 1);
7892
7893 bind(L_carry);
7894 movl(Address(z, kdx, Address::times_4, 0), carry);
7895
7896 // Second and third (nested) loops.
7897 //
7898 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7899 // carry = 0;
7900 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7901 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7902 // (z[k] & LONG_MASK) + carry;
7903 // z[k] = (int)product;
7904 // carry = product >>> 32;
7905 // }
7906 // z[i] = (int)carry;
7907 // }
7908 //
7909 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7910
7911 const Register jdx = tmp1;
7912
7913 bind(L_second_loop);
7914 xorl(carry, carry); // carry = 0;
7915 movl(jdx, ylen); // j = ystart+1
7916
7917 subl(xstart, 1); // i = xstart-1;
7918 jcc(Assembler::negative, L_done);
7919
7920 push (z);
7921
7922 Label L_last_x;
7923 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7924 subl(xstart, 1); // i = xstart-1;
7925 jcc(Assembler::negative, L_last_x);
7926
7927 if (UseBMI2Instructions) {
7928 movq(rdx, Address(x, xstart, Address::times_4, 0));
7929 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7930 } else {
7931 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7932 rorq(x_xstart, 32); // convert big-endian to little-endian
7933 }
7934
7935 Label L_third_loop_prologue;
7936 bind(L_third_loop_prologue);
7937
7938 push (x);
7939 push (xstart);
7940 push (ylen);
7941
7942
7943 if (UseBMI2Instructions) {
7944 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7945 } else { // !UseBMI2Instructions
7946 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7947 }
7948
7949 pop(ylen);
7950 pop(xlen);
7951 pop(x);
7952 pop(z);
7953
7954 movl(tmp3, xlen);
7955 addl(tmp3, 1);
7956 movl(Address(z, tmp3, Address::times_4, 0), carry);
7957 subl(tmp3, 1);
7958 jccb(Assembler::negative, L_done);
7959
7960 shrq(carry, 32);
7961 movl(Address(z, tmp3, Address::times_4, 0), carry);
7962 jmp(L_second_loop);
7963
7964 // Next infrequent code is moved outside loops.
7965 bind(L_last_x);
7966 if (UseBMI2Instructions) {
7967 movl(rdx, Address(x, 0));
7968 } else {
7969 movl(x_xstart, Address(x, 0));
7970 }
7971 jmp(L_third_loop_prologue);
7972
7973 bind(L_done);
7974
7975 pop(zlen);
7976 pop(xlen);
7977
7978 pop(tmp5);
7979 pop(tmp4);
7980 pop(tmp3);
7981 pop(tmp2);
7982 pop(tmp1);
7983 }
7984
7985 //Helper functions for square_to_len()
7986
7987 /**
7988 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7989 * Preserves x and z and modifies rest of the registers.
7990 */
7991
7992 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7993 // Perform square and right shift by 1
7994 // Handle odd xlen case first, then for even xlen do the following
7995 // jlong carry = 0;
7996 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7997 // huge_128 product = x[j:j+1] * x[j:j+1];
7998 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7999 // z[i+2:i+3] = (jlong)(product >>> 1);
8000 // carry = (jlong)product;
8001 // }
8002
8003 xorq(tmp5, tmp5); // carry
8004 xorq(rdxReg, rdxReg);
8005 xorl(tmp1, tmp1); // index for x
8006 xorl(tmp4, tmp4); // index for z
8007
8008 Label L_first_loop, L_first_loop_exit;
8009
8010 testl(xlen, 1);
8011 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8012
8013 // Square and right shift by 1 the odd element using 32 bit multiply
8014 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8015 imulq(raxReg, raxReg);
8016 shrq(raxReg, 1);
8017 adcq(tmp5, 0);
8018 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8019 incrementl(tmp1);
8020 addl(tmp4, 2);
8021
8022 // Square and right shift by 1 the rest using 64 bit multiply
8023 bind(L_first_loop);
8024 cmpptr(tmp1, xlen);
8025 jccb(Assembler::equal, L_first_loop_exit);
8026
8027 // Square
8028 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8029 rorq(raxReg, 32); // convert big-endian to little-endian
8030 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8031
8032 // Right shift by 1 and save carry
8033 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8034 rcrq(rdxReg, 1);
8035 rcrq(raxReg, 1);
8036 adcq(tmp5, 0);
8037
8038 // Store result in z
8039 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8040 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8041
8042 // Update indices for x and z
8043 addl(tmp1, 2);
8044 addl(tmp4, 4);
8045 jmp(L_first_loop);
8046
8047 bind(L_first_loop_exit);
8048 }
8049
8050
8051 /**
8052 * Perform the following multiply add operation using BMI2 instructions
8053 * carry:sum = sum + op1*op2 + carry
8054 * op2 should be in rdx
8055 * op2 is preserved, all other registers are modified
8056 */
8057 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8058 // assert op2 is rdx
8059 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8060 addq(sum, carry);
8061 adcq(tmp2, 0);
8062 addq(sum, op1);
8063 adcq(tmp2, 0);
8064 movq(carry, tmp2);
8065 }
8066
8067 /**
8068 * Perform the following multiply add operation:
8069 * carry:sum = sum + op1*op2 + carry
8070 * Preserves op1, op2 and modifies rest of registers
8071 */
8072 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8073 // rdx:rax = op1 * op2
8074 movq(raxReg, op2);
8075 mulq(op1);
8076
8077 // rdx:rax = sum + carry + rdx:rax
8078 addq(sum, carry);
8079 adcq(rdxReg, 0);
8080 addq(sum, raxReg);
8081 adcq(rdxReg, 0);
8082
8083 // carry:sum = rdx:sum
8084 movq(carry, rdxReg);
8085 }
8086
8087 /**
8088 * Add 64 bit long carry into z[] with carry propogation.
8089 * Preserves z and carry register values and modifies rest of registers.
8090 *
8091 */
8092 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8093 Label L_fourth_loop, L_fourth_loop_exit;
8094
8095 movl(tmp1, 1);
8096 subl(zlen, 2);
8097 addq(Address(z, zlen, Address::times_4, 0), carry);
8098
8099 bind(L_fourth_loop);
8100 jccb(Assembler::carryClear, L_fourth_loop_exit);
8101 subl(zlen, 2);
8102 jccb(Assembler::negative, L_fourth_loop_exit);
8103 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8104 jmp(L_fourth_loop);
8105 bind(L_fourth_loop_exit);
8106 }
8107
8108 /**
8109 * Shift z[] left by 1 bit.
8110 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8111 *
8112 */
8113 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8114
8115 Label L_fifth_loop, L_fifth_loop_exit;
8116
8117 // Fifth loop
8118 // Perform primitiveLeftShift(z, zlen, 1)
8119
8120 const Register prev_carry = tmp1;
8121 const Register new_carry = tmp4;
8122 const Register value = tmp2;
8123 const Register zidx = tmp3;
8124
8125 // int zidx, carry;
8126 // long value;
8127 // carry = 0;
8128 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8129 // (carry:value) = (z[i] << 1) | carry ;
8130 // z[i] = value;
8131 // }
8132
8133 movl(zidx, zlen);
8134 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8135
8136 bind(L_fifth_loop);
8137 decl(zidx); // Use decl to preserve carry flag
8138 decl(zidx);
8139 jccb(Assembler::negative, L_fifth_loop_exit);
8140
8141 if (UseBMI2Instructions) {
8142 movq(value, Address(z, zidx, Address::times_4, 0));
8143 rclq(value, 1);
8144 rorxq(value, value, 32);
8145 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8146 }
8147 else {
8148 // clear new_carry
8149 xorl(new_carry, new_carry);
8150
8151 // Shift z[i] by 1, or in previous carry and save new carry
8152 movq(value, Address(z, zidx, Address::times_4, 0));
8153 shlq(value, 1);
8154 adcl(new_carry, 0);
8155
8156 orq(value, prev_carry);
8157 rorq(value, 0x20);
8158 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8159
8160 // Set previous carry = new carry
8161 movl(prev_carry, new_carry);
8162 }
8163 jmp(L_fifth_loop);
8164
8165 bind(L_fifth_loop_exit);
8166 }
8167
8168
8169 /**
8170 * Code for BigInteger::squareToLen() intrinsic
8171 *
8172 * rdi: x
8173 * rsi: len
8174 * r8: z
8175 * rcx: zlen
8176 * r12: tmp1
8177 * r13: tmp2
8178 * r14: tmp3
8179 * r15: tmp4
8180 * rbx: tmp5
8181 *
8182 */
8183 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8184
8185 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
8186 push(tmp1);
8187 push(tmp2);
8188 push(tmp3);
8189 push(tmp4);
8190 push(tmp5);
8191
8192 // First loop
8193 // Store the squares, right shifted one bit (i.e., divided by 2).
8194 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8195
8196 // Add in off-diagonal sums.
8197 //
8198 // Second, third (nested) and fourth loops.
8199 // zlen +=2;
8200 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8201 // carry = 0;
8202 // long op2 = x[xidx:xidx+1];
8203 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8204 // k -= 2;
8205 // long op1 = x[j:j+1];
8206 // long sum = z[k:k+1];
8207 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8208 // z[k:k+1] = sum;
8209 // }
8210 // add_one_64(z, k, carry, tmp_regs);
8211 // }
8212
8213 const Register carry = tmp5;
8214 const Register sum = tmp3;
8215 const Register op1 = tmp4;
8216 Register op2 = tmp2;
8217
8218 push(zlen);
8219 push(len);
8220 addl(zlen,2);
8221 bind(L_second_loop);
8222 xorq(carry, carry);
8223 subl(zlen, 4);
8224 subl(len, 2);
8225 push(zlen);
8226 push(len);
8227 cmpl(len, 0);
8228 jccb(Assembler::lessEqual, L_second_loop_exit);
8229
8230 // Multiply an array by one 64 bit long.
8231 if (UseBMI2Instructions) {
8232 op2 = rdxReg;
8233 movq(op2, Address(x, len, Address::times_4, 0));
8234 rorxq(op2, op2, 32);
8235 }
8236 else {
8237 movq(op2, Address(x, len, Address::times_4, 0));
8238 rorq(op2, 32);
8239 }
8240
8241 bind(L_third_loop);
8242 decrementl(len);
8243 jccb(Assembler::negative, L_third_loop_exit);
8244 decrementl(len);
8245 jccb(Assembler::negative, L_last_x);
8246
8247 movq(op1, Address(x, len, Address::times_4, 0));
8248 rorq(op1, 32);
8249
8250 bind(L_multiply);
8251 subl(zlen, 2);
8252 movq(sum, Address(z, zlen, Address::times_4, 0));
8253
8254 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8255 if (UseBMI2Instructions) {
8256 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8257 }
8258 else {
8259 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8260 }
8261
8262 movq(Address(z, zlen, Address::times_4, 0), sum);
8263
8264 jmp(L_third_loop);
8265 bind(L_third_loop_exit);
8266
8267 // Fourth loop
8268 // Add 64 bit long carry into z with carry propogation.
8269 // Uses offsetted zlen.
8270 add_one_64(z, zlen, carry, tmp1);
8271
8272 pop(len);
8273 pop(zlen);
8274 jmp(L_second_loop);
8275
8276 // Next infrequent code is moved outside loops.
8277 bind(L_last_x);
8278 movl(op1, Address(x, 0));
8279 jmp(L_multiply);
8280
8281 bind(L_second_loop_exit);
8282 pop(len);
8283 pop(zlen);
8284 pop(len);
8285 pop(zlen);
8286
8287 // Fifth loop
8288 // Shift z left 1 bit.
8289 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8290
8291 // z[zlen-1] |= x[len-1] & 1;
8292 movl(tmp3, Address(x, len, Address::times_4, -4));
8293 andl(tmp3, 1);
8294 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8295
8296 pop(tmp5);
8297 pop(tmp4);
8298 pop(tmp3);
8299 pop(tmp2);
8300 pop(tmp1);
8301 }
8302
8303 /**
8304 * Helper function for mul_add()
8305 * Multiply the in[] by int k and add to out[] starting at offset offs using
8306 * 128 bit by 32 bit multiply and return the carry in tmp5.
8307 * Only quad int aligned length of in[] is operated on in this function.
8308 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8309 * This function preserves out, in and k registers.
8310 * len and offset point to the appropriate index in "in" & "out" correspondingly
8311 * tmp5 has the carry.
8312 * other registers are temporary and are modified.
8313 *
8314 */
8315 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8316 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8317 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8318
8319 Label L_first_loop, L_first_loop_exit;
8320
8321 movl(tmp1, len);
8322 shrl(tmp1, 2);
8323
8324 bind(L_first_loop);
8325 subl(tmp1, 1);
8326 jccb(Assembler::negative, L_first_loop_exit);
8327
8328 subl(len, 4);
8329 subl(offset, 4);
8330
8331 Register op2 = tmp2;
8332 const Register sum = tmp3;
8333 const Register op1 = tmp4;
8334 const Register carry = tmp5;
8335
8336 if (UseBMI2Instructions) {
8337 op2 = rdxReg;
8338 }
8339
8340 movq(op1, Address(in, len, Address::times_4, 8));
8341 rorq(op1, 32);
8342 movq(sum, Address(out, offset, Address::times_4, 8));
8343 rorq(sum, 32);
8344 if (UseBMI2Instructions) {
8345 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8346 }
8347 else {
8348 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8349 }
8350 // Store back in big endian from little endian
8351 rorq(sum, 0x20);
8352 movq(Address(out, offset, Address::times_4, 8), sum);
8353
8354 movq(op1, Address(in, len, Address::times_4, 0));
8355 rorq(op1, 32);
8356 movq(sum, Address(out, offset, Address::times_4, 0));
8357 rorq(sum, 32);
8358 if (UseBMI2Instructions) {
8359 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8360 }
8361 else {
8362 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8363 }
8364 // Store back in big endian from little endian
8365 rorq(sum, 0x20);
8366 movq(Address(out, offset, Address::times_4, 0), sum);
8367
8368 jmp(L_first_loop);
8369 bind(L_first_loop_exit);
8370 }
8371
8372 /**
8373 * Code for BigInteger::mulAdd() intrinsic
8374 *
8375 * rdi: out
8376 * rsi: in
8377 * r11: offs (out.length - offset)
8378 * rcx: len
8379 * r8: k
8380 * r12: tmp1
8381 * r13: tmp2
8382 * r14: tmp3
8383 * r15: tmp4
8384 * rbx: tmp5
8385 * Multiply the in[] by word k and add to out[], return the carry in rax
8386 */
8387 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8388 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8389 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8390
8391 Label L_carry, L_last_in, L_done;
8392
8393 // carry = 0;
8394 // for (int j=len-1; j >= 0; j--) {
8395 // long product = (in[j] & LONG_MASK) * kLong +
8396 // (out[offs] & LONG_MASK) + carry;
8397 // out[offs--] = (int)product;
8398 // carry = product >>> 32;
8399 // }
8400 //
8401 push(tmp1);
8402 push(tmp2);
8403 push(tmp3);
8404 push(tmp4);
8405 push(tmp5);
8406
8407 Register op2 = tmp2;
8408 const Register sum = tmp3;
8409 const Register op1 = tmp4;
8410 const Register carry = tmp5;
8411
8412 if (UseBMI2Instructions) {
8413 op2 = rdxReg;
8414 movl(op2, k);
8415 }
8416 else {
8417 movl(op2, k);
8418 }
8419
8420 xorq(carry, carry);
8421
8422 //First loop
8423
8424 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8425 //The carry is in tmp5
8426 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8427
8428 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8429 decrementl(len);
8430 jccb(Assembler::negative, L_carry);
8431 decrementl(len);
8432 jccb(Assembler::negative, L_last_in);
8433
8434 movq(op1, Address(in, len, Address::times_4, 0));
8435 rorq(op1, 32);
8436
8437 subl(offs, 2);
8438 movq(sum, Address(out, offs, Address::times_4, 0));
8439 rorq(sum, 32);
8440
8441 if (UseBMI2Instructions) {
8442 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8443 }
8444 else {
8445 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8446 }
8447
8448 // Store back in big endian from little endian
8449 rorq(sum, 0x20);
8450 movq(Address(out, offs, Address::times_4, 0), sum);
8451
8452 testl(len, len);
8453 jccb(Assembler::zero, L_carry);
8454
8455 //Multiply the last in[] entry, if any
8456 bind(L_last_in);
8457 movl(op1, Address(in, 0));
8458 movl(sum, Address(out, offs, Address::times_4, -4));
8459
8460 movl(raxReg, k);
8461 mull(op1); //tmp4 * eax -> edx:eax
8462 addl(sum, carry);
8463 adcl(rdxReg, 0);
8464 addl(sum, raxReg);
8465 adcl(rdxReg, 0);
8466 movl(carry, rdxReg);
8467
8468 movl(Address(out, offs, Address::times_4, -4), sum);
8469
8470 bind(L_carry);
8471 //return tmp5/carry as carry in rax
8472 movl(rax, carry);
8473
8474 bind(L_done);
8475 pop(tmp5);
8476 pop(tmp4);
8477 pop(tmp3);
8478 pop(tmp2);
8479 pop(tmp1);
8480 }
8481 #endif
8482
8483 /**
8484 * Emits code to update CRC-32 with a byte value according to constants in table
8485 *
8486 * @param [in,out]crc Register containing the crc.
8487 * @param [in]val Register containing the byte to fold into the CRC.
8488 * @param [in]table Register containing the table of crc constants.
8489 *
8490 * uint32_t crc;
8491 * val = crc_table[(val ^ crc) & 0xFF];
8492 * crc = val ^ (crc >> 8);
8493 *
8494 */
8495 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8496 xorl(val, crc);
8497 andl(val, 0xFF);
8498 shrl(crc, 8); // unsigned shift
8499 xorl(crc, Address(table, val, Address::times_4, 0));
8500 }
8501
8502 /**
8503 * Fold 128-bit data chunk
8504 */
8505 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8506 if (UseAVX > 0) {
8507 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8508 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8509 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
8510 pxor(xcrc, xtmp);
8511 } else {
8512 movdqa(xtmp, xcrc);
8513 pclmulhdq(xtmp, xK); // [123:64]
8514 pclmulldq(xcrc, xK); // [63:0]
8515 pxor(xcrc, xtmp);
8516 movdqu(xtmp, Address(buf, offset));
8517 pxor(xcrc, xtmp);
8518 }
8519 }
8520
8521 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8522 if (UseAVX > 0) {
8523 vpclmulhdq(xtmp, xK, xcrc);
8524 vpclmulldq(xcrc, xK, xcrc);
8525 pxor(xcrc, xbuf);
8526 pxor(xcrc, xtmp);
8527 } else {
8528 movdqa(xtmp, xcrc);
8529 pclmulhdq(xtmp, xK);
8530 pclmulldq(xcrc, xK);
8531 pxor(xcrc, xbuf);
8532 pxor(xcrc, xtmp);
8533 }
8534 }
8535
8536 /**
8537 * 8-bit folds to compute 32-bit CRC
8538 *
8539 * uint64_t xcrc;
8540 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8541 */
8542 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8543 movdl(tmp, xcrc);
8544 andl(tmp, 0xFF);
8545 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8546 psrldq(xcrc, 1); // unsigned shift one byte
8547 pxor(xcrc, xtmp);
8548 }
8549
8550 /**
8551 * uint32_t crc;
8552 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8553 */
8554 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8555 movl(tmp, crc);
8556 andl(tmp, 0xFF);
8557 shrl(crc, 8);
8558 xorl(crc, Address(table, tmp, Address::times_4, 0));
8559 }
8560
8561 /**
8562 * @param crc register containing existing CRC (32-bit)
8563 * @param buf register pointing to input byte buffer (byte*)
8564 * @param len register containing number of bytes
8565 * @param table register that will contain address of CRC table
8566 * @param tmp scratch register
8567 */
8568 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8569 assert_different_registers(crc, buf, len, table, tmp, rax);
8570
8571 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8572 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8573
8574 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8575 notl(crc); // ~crc
8576 cmpl(len, 16);
8577 jcc(Assembler::less, L_tail);
8578
8579 // Align buffer to 16 bytes
8580 movl(tmp, buf);
8581 andl(tmp, 0xF);
8582 jccb(Assembler::zero, L_aligned);
8583 subl(tmp, 16);
8584 addl(len, tmp);
8585
8586 align(4);
8587 BIND(L_align_loop);
8588 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8589 update_byte_crc32(crc, rax, table);
8590 increment(buf);
8591 incrementl(tmp);
8592 jccb(Assembler::less, L_align_loop);
8593
8594 BIND(L_aligned);
8595 movl(tmp, len); // save
8596 shrl(len, 4);
8597 jcc(Assembler::zero, L_tail_restore);
8598
8599 // Fold crc into first bytes of vector
8600 movdqa(xmm1, Address(buf, 0));
8601 movdl(rax, xmm1);
8602 xorl(crc, rax);
8603 pinsrd(xmm1, crc, 0);
8604 addptr(buf, 16);
8605 subl(len, 4); // len > 0
8606 jcc(Assembler::less, L_fold_tail);
8607
8608 movdqa(xmm2, Address(buf, 0));
8609 movdqa(xmm3, Address(buf, 16));
8610 movdqa(xmm4, Address(buf, 32));
8611 addptr(buf, 48);
8612 subl(len, 3);
8613 jcc(Assembler::lessEqual, L_fold_512b);
8614
8615 // Fold total 512 bits of polynomial on each iteration,
8616 // 128 bits per each of 4 parallel streams.
8617 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8618
8619 align(32);
8620 BIND(L_fold_512b_loop);
8621 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8622 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8623 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8624 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8625 addptr(buf, 64);
8626 subl(len, 4);
8627 jcc(Assembler::greater, L_fold_512b_loop);
8628
8629 // Fold 512 bits to 128 bits.
8630 BIND(L_fold_512b);
8631 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8632 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8633 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8634 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8635
8636 // Fold the rest of 128 bits data chunks
8637 BIND(L_fold_tail);
8638 addl(len, 3);
8639 jccb(Assembler::lessEqual, L_fold_128b);
8640 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8641
8642 BIND(L_fold_tail_loop);
8643 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8644 addptr(buf, 16);
8645 decrementl(len);
8646 jccb(Assembler::greater, L_fold_tail_loop);
8647
8648 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8649 BIND(L_fold_128b);
8650 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8651 if (UseAVX > 0) {
8652 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8653 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
8654 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8655 } else {
8656 movdqa(xmm2, xmm0);
8657 pclmulqdq(xmm2, xmm1, 0x1);
8658 movdqa(xmm3, xmm0);
8659 pand(xmm3, xmm2);
8660 pclmulqdq(xmm0, xmm3, 0x1);
8661 }
8662 psrldq(xmm1, 8);
8663 psrldq(xmm2, 4);
8664 pxor(xmm0, xmm1);
8665 pxor(xmm0, xmm2);
8666
8667 // 8 8-bit folds to compute 32-bit CRC.
8668 for (int j = 0; j < 4; j++) {
8669 fold_8bit_crc32(xmm0, table, xmm1, rax);
8670 }
8671 movdl(crc, xmm0); // mov 32 bits to general register
8672 for (int j = 0; j < 4; j++) {
8673 fold_8bit_crc32(crc, table, rax);
8674 }
8675
8676 BIND(L_tail_restore);
8677 movl(len, tmp); // restore
8678 BIND(L_tail);
8679 andl(len, 0xf);
8680 jccb(Assembler::zero, L_exit);
8681
8682 // Fold the rest of bytes
8683 align(4);
8684 BIND(L_tail_loop);
8685 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8686 update_byte_crc32(crc, rax, table);
8687 increment(buf);
8688 decrementl(len);
8689 jccb(Assembler::greater, L_tail_loop);
8690
8691 BIND(L_exit);
8692 notl(crc); // ~c
8693 }
8694
8695 #undef BIND
8696 #undef BLOCK_COMMENT
8697
8698
8699 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8700 switch (cond) {
8701 // Note some conditions are synonyms for others
8702 case Assembler::zero: return Assembler::notZero;
8703 case Assembler::notZero: return Assembler::zero;
8704 case Assembler::less: return Assembler::greaterEqual;
8705 case Assembler::lessEqual: return Assembler::greater;
8706 case Assembler::greater: return Assembler::lessEqual;
8707 case Assembler::greaterEqual: return Assembler::less;
8708 case Assembler::below: return Assembler::aboveEqual;
8709 case Assembler::belowEqual: return Assembler::above;
8710 case Assembler::above: return Assembler::belowEqual;
8711 case Assembler::aboveEqual: return Assembler::below;
8712 case Assembler::overflow: return Assembler::noOverflow;
8713 case Assembler::noOverflow: return Assembler::overflow;
8714 case Assembler::negative: return Assembler::positive;
8715 case Assembler::positive: return Assembler::negative;
8716 case Assembler::parity: return Assembler::noParity;
8717 case Assembler::noParity: return Assembler::parity;
8718 }
8719 ShouldNotReachHere(); return Assembler::overflow;
8720 }
8721
8722 SkipIfEqual::SkipIfEqual(
8723 MacroAssembler* masm, const bool* flag_addr, bool value) {
8724 _masm = masm;
8725 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8726 _masm->jcc(Assembler::equal, _label);
8727 }
8728
8729 SkipIfEqual::~SkipIfEqual() {
8730 _masm->bind(_label);
8731 }
8732
8733 void MacroAssembler::cmpoops(Register src1, Register src2) {
8734 cmpptr(src1, src2);
8735 oopDesc::bs()->asm_acmp_barrier(this, src1, src2);
8736 }
8737
8738 void MacroAssembler::cmpoops(Register src1, Address src2) {
8739 cmpptr(src1, src2);
8740 #if INCLUDE_ALL_GCS
8741 if (UseShenandoahGC && ShenandoahAcmpBarrier) {
8742 Label done;
8743 jccb(Assembler::equal, done);
8744 movptr(rscratch2, src2);
8745 oopDesc::bs()->interpreter_read_barrier(this, src1);
8746 oopDesc::bs()->interpreter_read_barrier(this, rscratch2);
8747 cmpptr(src1, rscratch2);
8748 bind(done);
8749 }
8750 #endif
8751 }