1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/shenandoahSupport.hpp"
38 #include "opto/type.hpp"
39 #include "opto/vectornode.hpp"
40 #include "runtime/atomic.hpp"
41 #include "runtime/os.hpp"
42 #if defined AD_MD_HPP
43 # include AD_MD_HPP
44 #elif defined TARGET_ARCH_MODEL_x86_32
45 # include "adfiles/ad_x86_32.hpp"
46 #elif defined TARGET_ARCH_MODEL_x86_64
47 # include "adfiles/ad_x86_64.hpp"
48 #elif defined TARGET_ARCH_MODEL_aarch64
49 # include "adfiles/ad_aarch64.hpp"
50 #elif defined TARGET_ARCH_MODEL_sparc
51 # include "adfiles/ad_sparc.hpp"
52 #elif defined TARGET_ARCH_MODEL_zero
53 # include "adfiles/ad_zero.hpp"
54 #elif defined TARGET_ARCH_MODEL_ppc_64
55 # include "adfiles/ad_ppc_64.hpp"
56 #endif
57
58 OptoReg::Name OptoReg::c_frame_pointer;
59
60 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
61 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
62 RegMask Matcher::STACK_ONLY_mask;
63 RegMask Matcher::c_frame_ptr_mask;
64 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
65 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
66
67 //---------------------------Matcher-------------------------------------------
68 Matcher::Matcher()
69 : PhaseTransform( Phase::Ins_Select ),
70 #ifdef ASSERT
71 _old2new_map(C->comp_arena()),
72 _new2old_map(C->comp_arena()),
73 #endif
74 _shared_nodes(C->comp_arena()),
75 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
76 _swallowed(swallowed),
77 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
78 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
79 _must_clone(must_clone),
80 _register_save_policy(register_save_policy),
81 _c_reg_save_policy(c_reg_save_policy),
82 _register_save_type(register_save_type),
83 _ruleName(ruleName),
84 _allocation_started(false),
85 _states_arena(Chunk::medium_size, mtCompiler),
86 _visited(&_states_arena),
87 _shared(&_states_arena),
88 _dontcare(&_states_arena) {
89 C->set_matcher(this);
90
91 idealreg2spillmask [Op_RegI] = NULL;
92 idealreg2spillmask [Op_RegN] = NULL;
93 idealreg2spillmask [Op_RegL] = NULL;
94 idealreg2spillmask [Op_RegF] = NULL;
95 idealreg2spillmask [Op_RegD] = NULL;
96 idealreg2spillmask [Op_RegP] = NULL;
97 idealreg2spillmask [Op_VecS] = NULL;
98 idealreg2spillmask [Op_VecD] = NULL;
99 idealreg2spillmask [Op_VecX] = NULL;
100 idealreg2spillmask [Op_VecY] = NULL;
101
102 idealreg2debugmask [Op_RegI] = NULL;
103 idealreg2debugmask [Op_RegN] = NULL;
104 idealreg2debugmask [Op_RegL] = NULL;
105 idealreg2debugmask [Op_RegF] = NULL;
106 idealreg2debugmask [Op_RegD] = NULL;
107 idealreg2debugmask [Op_RegP] = NULL;
108 idealreg2debugmask [Op_VecS] = NULL;
109 idealreg2debugmask [Op_VecD] = NULL;
110 idealreg2debugmask [Op_VecX] = NULL;
111 idealreg2debugmask [Op_VecY] = NULL;
112
113 idealreg2mhdebugmask[Op_RegI] = NULL;
114 idealreg2mhdebugmask[Op_RegN] = NULL;
115 idealreg2mhdebugmask[Op_RegL] = NULL;
116 idealreg2mhdebugmask[Op_RegF] = NULL;
117 idealreg2mhdebugmask[Op_RegD] = NULL;
118 idealreg2mhdebugmask[Op_RegP] = NULL;
119 idealreg2mhdebugmask[Op_VecS] = NULL;
120 idealreg2mhdebugmask[Op_VecD] = NULL;
121 idealreg2mhdebugmask[Op_VecX] = NULL;
122 idealreg2mhdebugmask[Op_VecY] = NULL;
123
124 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
125 }
126
127 //------------------------------warp_incoming_stk_arg------------------------
128 // This warps a VMReg into an OptoReg::Name
129 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
130 OptoReg::Name warped;
131 if( reg->is_stack() ) { // Stack slot argument?
132 warped = OptoReg::add(_old_SP, reg->reg2stack() );
133 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
134 if( warped >= _in_arg_limit )
135 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
136 if (!RegMask::can_represent_arg(warped)) {
137 // the compiler cannot represent this method's calling sequence
138 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
139 return OptoReg::Bad;
140 }
141 return warped;
142 }
143 return OptoReg::as_OptoReg(reg);
144 }
145
146 //---------------------------compute_old_SP------------------------------------
147 OptoReg::Name Compile::compute_old_SP() {
148 int fixed = fixed_slots();
149 int preserve = in_preserve_stack_slots();
150 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
151 }
152
153
154
155 #ifdef ASSERT
156 void Matcher::verify_new_nodes_only(Node* xroot) {
157 // Make sure that the new graph only references new nodes
158 ResourceMark rm;
159 Unique_Node_List worklist;
160 VectorSet visited(Thread::current()->resource_area());
161 worklist.push(xroot);
162 while (worklist.size() > 0) {
163 Node* n = worklist.pop();
164 visited <<= n->_idx;
165 assert(C->node_arena()->contains(n), "dead node");
166 for (uint j = 0; j < n->req(); j++) {
167 Node* in = n->in(j);
168 if (in != NULL) {
169 assert(C->node_arena()->contains(in), "dead node");
170 if (!visited.test(in->_idx)) {
171 worklist.push(in);
172 }
173 }
174 }
175 }
176 }
177 #endif
178
179
180 //---------------------------match---------------------------------------------
181 void Matcher::match( ) {
182 if( MaxLabelRootDepth < 100 ) { // Too small?
183 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
184 MaxLabelRootDepth = 100;
185 }
186 // One-time initialization of some register masks.
187 init_spill_mask( C->root()->in(1) );
188 _return_addr_mask = return_addr();
189 #ifdef _LP64
190 // Pointers take 2 slots in 64-bit land
191 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
192 #endif
193
194 // Map a Java-signature return type into return register-value
195 // machine registers for 0, 1 and 2 returned values.
196 const TypeTuple *range = C->tf()->range();
197 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
198 // Get ideal-register return type
199 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
200 // Get machine return register
201 uint sop = C->start()->Opcode();
202 OptoRegPair regs = return_value(ireg, false);
203
204 // And mask for same
205 _return_value_mask = RegMask(regs.first());
206 if( OptoReg::is_valid(regs.second()) )
207 _return_value_mask.Insert(regs.second());
208 }
209
210 // ---------------
211 // Frame Layout
212
213 // Need the method signature to determine the incoming argument types,
214 // because the types determine which registers the incoming arguments are
215 // in, and this affects the matched code.
216 const TypeTuple *domain = C->tf()->domain();
217 uint argcnt = domain->cnt() - TypeFunc::Parms;
218 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
219 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
220 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
221 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
222 uint i;
223 for( i = 0; i<argcnt; i++ ) {
224 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
225 }
226
227 // Pass array of ideal registers and length to USER code (from the AD file)
228 // that will convert this to an array of register numbers.
229 const StartNode *start = C->start();
230 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
231 #ifdef ASSERT
232 // Sanity check users' calling convention. Real handy while trying to
233 // get the initial port correct.
234 { for (uint i = 0; i<argcnt; i++) {
235 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
236 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
237 _parm_regs[i].set_bad();
238 continue;
239 }
240 VMReg parm_reg = vm_parm_regs[i].first();
241 assert(parm_reg->is_valid(), "invalid arg?");
242 if (parm_reg->is_reg()) {
243 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
244 assert(can_be_java_arg(opto_parm_reg) ||
245 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
246 opto_parm_reg == inline_cache_reg(),
247 "parameters in register must be preserved by runtime stubs");
248 }
249 for (uint j = 0; j < i; j++) {
250 assert(parm_reg != vm_parm_regs[j].first(),
251 "calling conv. must produce distinct regs");
252 }
253 }
254 }
255 #endif
256
257 // Do some initial frame layout.
258
259 // Compute the old incoming SP (may be called FP) as
260 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
261 _old_SP = C->compute_old_SP();
262 assert( is_even(_old_SP), "must be even" );
263
264 // Compute highest incoming stack argument as
265 // _old_SP + out_preserve_stack_slots + incoming argument size.
266 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
267 assert( is_even(_in_arg_limit), "out_preserve must be even" );
268 for( i = 0; i < argcnt; i++ ) {
269 // Permit args to have no register
270 _calling_convention_mask[i].Clear();
271 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
272 continue;
273 }
274 // calling_convention returns stack arguments as a count of
275 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
276 // the allocators point of view, taking into account all the
277 // preserve area, locks & pad2.
278
279 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
280 if( OptoReg::is_valid(reg1))
281 _calling_convention_mask[i].Insert(reg1);
282
283 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
284 if( OptoReg::is_valid(reg2))
285 _calling_convention_mask[i].Insert(reg2);
286
287 // Saved biased stack-slot register number
288 _parm_regs[i].set_pair(reg2, reg1);
289 }
290
291 // Finally, make sure the incoming arguments take up an even number of
292 // words, in case the arguments or locals need to contain doubleword stack
293 // slots. The rest of the system assumes that stack slot pairs (in
294 // particular, in the spill area) which look aligned will in fact be
295 // aligned relative to the stack pointer in the target machine. Double
296 // stack slots will always be allocated aligned.
297 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
298
299 // Compute highest outgoing stack argument as
300 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
301 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
302 assert( is_even(_out_arg_limit), "out_preserve must be even" );
303
304 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
305 // the compiler cannot represent this method's calling sequence
306 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
307 }
308
309 if (C->failing()) return; // bailed out on incoming arg failure
310
311 // ---------------
312 // Collect roots of matcher trees. Every node for which
313 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
314 // can be a valid interior of some tree.
315 find_shared( C->root() );
316 find_shared( C->top() );
317
318 C->print_method(PHASE_BEFORE_MATCHING);
319
320 // Create new ideal node ConP #NULL even if it does exist in old space
321 // to avoid false sharing if the corresponding mach node is not used.
322 // The corresponding mach node is only used in rare cases for derived
323 // pointers.
324 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
325
326 // Swap out to old-space; emptying new-space
327 Arena *old = C->node_arena()->move_contents(C->old_arena());
328
329 // Save debug and profile information for nodes in old space:
330 _old_node_note_array = C->node_note_array();
331 if (_old_node_note_array != NULL) {
332 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
333 (C->comp_arena(), _old_node_note_array->length(),
334 0, NULL));
335 }
336
337 // Pre-size the new_node table to avoid the need for range checks.
338 grow_new_node_array(C->unique());
339
340 // Reset node counter so MachNodes start with _idx at 0
341 int live_nodes = C->live_nodes();
342 C->set_unique(0);
343 C->reset_dead_node_list();
344
345 // Recursively match trees from old space into new space.
346 // Correct leaves of new-space Nodes; they point to old-space.
347 _visited.Clear(); // Clear visit bits for xform call
348 C->set_cached_top_node(xform( C->top(), live_nodes));
349 if (!C->failing()) {
350 Node* xroot = xform( C->root(), 1 );
351 if (xroot == NULL) {
352 Matcher::soft_match_failure(); // recursive matching process failed
353 C->record_method_not_compilable("instruction match failed");
354 } else {
355 // During matching shared constants were attached to C->root()
356 // because xroot wasn't available yet, so transfer the uses to
357 // the xroot.
358 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
359 Node* n = C->root()->fast_out(j);
360 if (C->node_arena()->contains(n)) {
361 assert(n->in(0) == C->root(), "should be control user");
362 n->set_req(0, xroot);
363 --j;
364 --jmax;
365 }
366 }
367
368 // Generate new mach node for ConP #NULL
369 assert(new_ideal_null != NULL, "sanity");
370 _mach_null = match_tree(new_ideal_null);
371 // Don't set control, it will confuse GCM since there are no uses.
372 // The control will be set when this node is used first time
373 // in find_base_for_derived().
374 assert(_mach_null != NULL, "");
375
376 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
377
378 #ifdef ASSERT
379 verify_new_nodes_only(xroot);
380 #endif
381 }
382 }
383 if (C->top() == NULL || C->root() == NULL) {
384 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
385 }
386 if (C->failing()) {
387 // delete old;
388 old->destruct_contents();
389 return;
390 }
391 assert( C->top(), "" );
392 assert( C->root(), "" );
393 validate_null_checks();
394
395 // Now smoke old-space
396 NOT_DEBUG( old->destruct_contents() );
397
398 // ------------------------
399 // Set up save-on-entry registers
400 Fixup_Save_On_Entry( );
401 }
402
403
404 //------------------------------Fixup_Save_On_Entry----------------------------
405 // The stated purpose of this routine is to take care of save-on-entry
406 // registers. However, the overall goal of the Match phase is to convert into
407 // machine-specific instructions which have RegMasks to guide allocation.
408 // So what this procedure really does is put a valid RegMask on each input
409 // to the machine-specific variations of all Return, TailCall and Halt
410 // instructions. It also adds edgs to define the save-on-entry values (and of
411 // course gives them a mask).
412
413 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
414 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
415 // Do all the pre-defined register masks
416 rms[TypeFunc::Control ] = RegMask::Empty;
417 rms[TypeFunc::I_O ] = RegMask::Empty;
418 rms[TypeFunc::Memory ] = RegMask::Empty;
419 rms[TypeFunc::ReturnAdr] = ret_adr;
420 rms[TypeFunc::FramePtr ] = fp;
421 return rms;
422 }
423
424 //---------------------------init_first_stack_mask-----------------------------
425 // Create the initial stack mask used by values spilling to the stack.
426 // Disallow any debug info in outgoing argument areas by setting the
427 // initial mask accordingly.
428 void Matcher::init_first_stack_mask() {
429
430 // Allocate storage for spill masks as masks for the appropriate load type.
431 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
432
433 idealreg2spillmask [Op_RegN] = &rms[0];
434 idealreg2spillmask [Op_RegI] = &rms[1];
435 idealreg2spillmask [Op_RegL] = &rms[2];
436 idealreg2spillmask [Op_RegF] = &rms[3];
437 idealreg2spillmask [Op_RegD] = &rms[4];
438 idealreg2spillmask [Op_RegP] = &rms[5];
439
440 idealreg2debugmask [Op_RegN] = &rms[6];
441 idealreg2debugmask [Op_RegI] = &rms[7];
442 idealreg2debugmask [Op_RegL] = &rms[8];
443 idealreg2debugmask [Op_RegF] = &rms[9];
444 idealreg2debugmask [Op_RegD] = &rms[10];
445 idealreg2debugmask [Op_RegP] = &rms[11];
446
447 idealreg2mhdebugmask[Op_RegN] = &rms[12];
448 idealreg2mhdebugmask[Op_RegI] = &rms[13];
449 idealreg2mhdebugmask[Op_RegL] = &rms[14];
450 idealreg2mhdebugmask[Op_RegF] = &rms[15];
451 idealreg2mhdebugmask[Op_RegD] = &rms[16];
452 idealreg2mhdebugmask[Op_RegP] = &rms[17];
453
454 idealreg2spillmask [Op_VecS] = &rms[18];
455 idealreg2spillmask [Op_VecD] = &rms[19];
456 idealreg2spillmask [Op_VecX] = &rms[20];
457 idealreg2spillmask [Op_VecY] = &rms[21];
458
459 OptoReg::Name i;
460
461 // At first, start with the empty mask
462 C->FIRST_STACK_mask().Clear();
463
464 // Add in the incoming argument area
465 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
466 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
467 C->FIRST_STACK_mask().Insert(i);
468 }
469 // Add in all bits past the outgoing argument area
470 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
471 "must be able to represent all call arguments in reg mask");
472 OptoReg::Name init = _out_arg_limit;
473 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
474 C->FIRST_STACK_mask().Insert(i);
475 }
476 // Finally, set the "infinite stack" bit.
477 C->FIRST_STACK_mask().set_AllStack();
478
479 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
480 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
481 // Keep spill masks aligned.
482 aligned_stack_mask.clear_to_pairs();
483 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
484
485 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
486 #ifdef _LP64
487 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
488 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
489 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
490 #else
491 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
492 #endif
493 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
494 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
495 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
496 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
497 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
498 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
499 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
500 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
501
502 if (Matcher::vector_size_supported(T_BYTE,4)) {
503 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
504 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
505 }
506 if (Matcher::vector_size_supported(T_FLOAT,2)) {
507 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
508 // RA guarantees such alignment since it is needed for Double and Long values.
509 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
510 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
511 }
512 if (Matcher::vector_size_supported(T_FLOAT,4)) {
513 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
514 //
515 // RA can use input arguments stack slots for spills but until RA
516 // we don't know frame size and offset of input arg stack slots.
517 //
518 // Exclude last input arg stack slots to avoid spilling vectors there
519 // otherwise vector spills could stomp over stack slots in caller frame.
520 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
521 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
522 aligned_stack_mask.Remove(in);
523 in = OptoReg::add(in, -1);
524 }
525 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
526 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
527 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
528 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
529 }
530 if (Matcher::vector_size_supported(T_FLOAT,8)) {
531 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
532 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
533 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
534 aligned_stack_mask.Remove(in);
535 in = OptoReg::add(in, -1);
536 }
537 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
538 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
539 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
540 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
541 }
542 if (UseFPUForSpilling) {
543 // This mask logic assumes that the spill operations are
544 // symmetric and that the registers involved are the same size.
545 // On sparc for instance we may have to use 64 bit moves will
546 // kill 2 registers when used with F0-F31.
547 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
548 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
549 #ifdef _LP64
550 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
551 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
552 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
553 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
554 #else
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
556 #ifdef ARM
557 // ARM has support for moving 64bit values between a pair of
558 // integer registers and a double register
559 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
560 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
561 #endif
562 #endif
563 }
564
565 // Make up debug masks. Any spill slot plus callee-save registers.
566 // Caller-save registers are assumed to be trashable by the various
567 // inline-cache fixup routines.
568 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
569 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
570 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
571 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
572 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
573 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
574
575 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
576 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
577 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
578 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
579 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
580 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
581
582 // Prevent stub compilations from attempting to reference
583 // callee-saved registers from debug info
584 bool exclude_soe = !Compile::current()->is_method_compilation();
585
586 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
587 // registers the caller has to save do not work
588 if( _register_save_policy[i] == 'C' ||
589 _register_save_policy[i] == 'A' ||
590 (_register_save_policy[i] == 'E' && exclude_soe) ) {
591 idealreg2debugmask [Op_RegN]->Remove(i);
592 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
593 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
594 idealreg2debugmask [Op_RegF]->Remove(i); // masks
595 idealreg2debugmask [Op_RegD]->Remove(i);
596 idealreg2debugmask [Op_RegP]->Remove(i);
597
598 idealreg2mhdebugmask[Op_RegN]->Remove(i);
599 idealreg2mhdebugmask[Op_RegI]->Remove(i);
600 idealreg2mhdebugmask[Op_RegL]->Remove(i);
601 idealreg2mhdebugmask[Op_RegF]->Remove(i);
602 idealreg2mhdebugmask[Op_RegD]->Remove(i);
603 idealreg2mhdebugmask[Op_RegP]->Remove(i);
604 }
605 }
606
607 // Subtract the register we use to save the SP for MethodHandle
608 // invokes to from the debug mask.
609 const RegMask save_mask = method_handle_invoke_SP_save_mask();
610 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
611 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
612 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
616 }
617
618 //---------------------------is_save_on_entry----------------------------------
619 bool Matcher::is_save_on_entry( int reg ) {
620 return
621 _register_save_policy[reg] == 'E' ||
622 _register_save_policy[reg] == 'A' || // Save-on-entry register?
623 // Also save argument registers in the trampolining stubs
624 (C->save_argument_registers() && is_spillable_arg(reg));
625 }
626
627 //---------------------------Fixup_Save_On_Entry-------------------------------
628 void Matcher::Fixup_Save_On_Entry( ) {
629 init_first_stack_mask();
630
631 Node *root = C->root(); // Short name for root
632 // Count number of save-on-entry registers.
633 uint soe_cnt = number_of_saved_registers();
634 uint i;
635
636 // Find the procedure Start Node
637 StartNode *start = C->start();
638 assert( start, "Expect a start node" );
639
640 // Save argument registers in the trampolining stubs
641 if( C->save_argument_registers() )
642 for( i = 0; i < _last_Mach_Reg; i++ )
643 if( is_spillable_arg(i) )
644 soe_cnt++;
645
646 // Input RegMask array shared by all Returns.
647 // The type for doubles and longs has a count of 2, but
648 // there is only 1 returned value
649 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
650 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
651 // Returns have 0 or 1 returned values depending on call signature.
652 // Return register is specified by return_value in the AD file.
653 if (ret_edge_cnt > TypeFunc::Parms)
654 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
655
656 // Input RegMask array shared by all Rethrows.
657 uint reth_edge_cnt = TypeFunc::Parms+1;
658 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
659 // Rethrow takes exception oop only, but in the argument 0 slot.
660 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
661 #ifdef _LP64
662 // Need two slots for ptrs in 64-bit land
663 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
664 #endif
665
666 // Input RegMask array shared by all TailCalls
667 uint tail_call_edge_cnt = TypeFunc::Parms+2;
668 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
669
670 // Input RegMask array shared by all TailJumps
671 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
672 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
673
674 // TailCalls have 2 returned values (target & moop), whose masks come
675 // from the usual MachNode/MachOper mechanism. Find a sample
676 // TailCall to extract these masks and put the correct masks into
677 // the tail_call_rms array.
678 for( i=1; i < root->req(); i++ ) {
679 MachReturnNode *m = root->in(i)->as_MachReturn();
680 if( m->ideal_Opcode() == Op_TailCall ) {
681 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
682 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
683 break;
684 }
685 }
686
687 // TailJumps have 2 returned values (target & ex_oop), whose masks come
688 // from the usual MachNode/MachOper mechanism. Find a sample
689 // TailJump to extract these masks and put the correct masks into
690 // the tail_jump_rms array.
691 for( i=1; i < root->req(); i++ ) {
692 MachReturnNode *m = root->in(i)->as_MachReturn();
693 if( m->ideal_Opcode() == Op_TailJump ) {
694 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
695 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
696 break;
697 }
698 }
699
700 // Input RegMask array shared by all Halts
701 uint halt_edge_cnt = TypeFunc::Parms;
702 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
703
704 // Capture the return input masks into each exit flavor
705 for( i=1; i < root->req(); i++ ) {
706 MachReturnNode *exit = root->in(i)->as_MachReturn();
707 switch( exit->ideal_Opcode() ) {
708 case Op_Return : exit->_in_rms = ret_rms; break;
709 case Op_Rethrow : exit->_in_rms = reth_rms; break;
710 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
711 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
712 case Op_Halt : exit->_in_rms = halt_rms; break;
713 default : ShouldNotReachHere();
714 }
715 }
716
717 // Next unused projection number from Start.
718 int proj_cnt = C->tf()->domain()->cnt();
719
720 // Do all the save-on-entry registers. Make projections from Start for
721 // them, and give them a use at the exit points. To the allocator, they
722 // look like incoming register arguments.
723 for( i = 0; i < _last_Mach_Reg; i++ ) {
724 if( is_save_on_entry(i) ) {
725
726 // Add the save-on-entry to the mask array
727 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
728 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
729 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
730 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
731 // Halts need the SOE registers, but only in the stack as debug info.
732 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
733 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
734
735 Node *mproj;
736
737 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
738 // into a single RegD.
739 if( (i&1) == 0 &&
740 _register_save_type[i ] == Op_RegF &&
741 _register_save_type[i+1] == Op_RegF &&
742 is_save_on_entry(i+1) ) {
743 // Add other bit for double
744 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
745 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
746 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
747 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
748 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
749 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
750 proj_cnt += 2; // Skip 2 for doubles
751 }
752 else if( (i&1) == 1 && // Else check for high half of double
753 _register_save_type[i-1] == Op_RegF &&
754 _register_save_type[i ] == Op_RegF &&
755 is_save_on_entry(i-1) ) {
756 ret_rms [ ret_edge_cnt] = RegMask::Empty;
757 reth_rms [ reth_edge_cnt] = RegMask::Empty;
758 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
759 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
760 halt_rms [ halt_edge_cnt] = RegMask::Empty;
761 mproj = C->top();
762 }
763 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
764 // into a single RegL.
765 else if( (i&1) == 0 &&
766 _register_save_type[i ] == Op_RegI &&
767 _register_save_type[i+1] == Op_RegI &&
768 is_save_on_entry(i+1) ) {
769 // Add other bit for long
770 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
771 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
772 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
773 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
774 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
775 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
776 proj_cnt += 2; // Skip 2 for longs
777 }
778 else if( (i&1) == 1 && // Else check for high half of long
779 _register_save_type[i-1] == Op_RegI &&
780 _register_save_type[i ] == Op_RegI &&
781 is_save_on_entry(i-1) ) {
782 ret_rms [ ret_edge_cnt] = RegMask::Empty;
783 reth_rms [ reth_edge_cnt] = RegMask::Empty;
784 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
785 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
786 halt_rms [ halt_edge_cnt] = RegMask::Empty;
787 mproj = C->top();
788 } else {
789 // Make a projection for it off the Start
790 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
791 }
792
793 ret_edge_cnt ++;
794 reth_edge_cnt ++;
795 tail_call_edge_cnt ++;
796 tail_jump_edge_cnt ++;
797 halt_edge_cnt ++;
798
799 // Add a use of the SOE register to all exit paths
800 for( uint j=1; j < root->req(); j++ )
801 root->in(j)->add_req(mproj);
802 } // End of if a save-on-entry register
803 } // End of for all machine registers
804 }
805
806 //------------------------------init_spill_mask--------------------------------
807 void Matcher::init_spill_mask( Node *ret ) {
808 if( idealreg2regmask[Op_RegI] ) return; // One time only init
809
810 OptoReg::c_frame_pointer = c_frame_pointer();
811 c_frame_ptr_mask = c_frame_pointer();
812 #ifdef _LP64
813 // pointers are twice as big
814 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
815 #endif
816
817 // Start at OptoReg::stack0()
818 STACK_ONLY_mask.Clear();
819 OptoReg::Name init = OptoReg::stack2reg(0);
820 // STACK_ONLY_mask is all stack bits
821 OptoReg::Name i;
822 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
823 STACK_ONLY_mask.Insert(i);
824 // Also set the "infinite stack" bit.
825 STACK_ONLY_mask.set_AllStack();
826
827 // Copy the register names over into the shared world
828 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
829 // SharedInfo::regName[i] = regName[i];
830 // Handy RegMasks per machine register
831 mreg2regmask[i].Insert(i);
832 }
833
834 // Grab the Frame Pointer
835 Node *fp = ret->in(TypeFunc::FramePtr);
836 Node *mem = ret->in(TypeFunc::Memory);
837 const TypePtr* atp = TypePtr::BOTTOM;
838 // Share frame pointer while making spill ops
839 set_shared(fp);
840
841 // Compute generic short-offset Loads
842 #ifdef _LP64
843 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
844 #endif
845 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
846 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest,false));
847 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
848 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
849 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
850 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
851 spillD != NULL && spillP != NULL, "");
852 // Get the ADLC notion of the right regmask, for each basic type.
853 #ifdef _LP64
854 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
855 #endif
856 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
857 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
858 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
859 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
860 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
861
862 // Vector regmasks.
863 if (Matcher::vector_size_supported(T_BYTE,4)) {
864 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
865 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
866 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
867 }
868 if (Matcher::vector_size_supported(T_FLOAT,2)) {
869 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
870 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
871 }
872 if (Matcher::vector_size_supported(T_FLOAT,4)) {
873 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
874 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
875 }
876 if (Matcher::vector_size_supported(T_FLOAT,8)) {
877 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
878 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
879 }
880 }
881
882 #ifdef ASSERT
883 static void match_alias_type(Compile* C, Node* n, Node* m) {
884 if (!VerifyAliases) return; // do not go looking for trouble by default
885 const TypePtr* nat = n->adr_type();
886 const TypePtr* mat = m->adr_type();
887 int nidx = C->get_alias_index(nat);
888 int midx = C->get_alias_index(mat);
889 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
890 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
891 for (uint i = 1; i < n->req(); i++) {
892 Node* n1 = n->in(i);
893 const TypePtr* n1at = n1->adr_type();
894 if (n1at != NULL) {
895 nat = n1at;
896 nidx = C->get_alias_index(n1at);
897 }
898 }
899 }
900 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
901 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
902 switch (n->Opcode()) {
903 case Op_PrefetchRead:
904 case Op_PrefetchWrite:
905 case Op_PrefetchAllocation:
906 nidx = Compile::AliasIdxRaw;
907 nat = TypeRawPtr::BOTTOM;
908 break;
909 }
910 }
911 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
912 switch (n->Opcode()) {
913 case Op_ClearArray:
914 midx = Compile::AliasIdxRaw;
915 mat = TypeRawPtr::BOTTOM;
916 break;
917 }
918 }
919 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
920 switch (n->Opcode()) {
921 case Op_Return:
922 case Op_Rethrow:
923 case Op_Halt:
924 case Op_TailCall:
925 case Op_TailJump:
926 nidx = Compile::AliasIdxBot;
927 nat = TypePtr::BOTTOM;
928 break;
929 }
930 }
931 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
932 switch (n->Opcode()) {
933 case Op_StrComp:
934 case Op_StrEquals:
935 case Op_StrIndexOf:
936 case Op_AryEq:
937 case Op_MemBarVolatile:
938 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
939 case Op_EncodeISOArray:
940 nidx = Compile::AliasIdxTop;
941 nat = NULL;
942 break;
943 }
944 }
945 if (nidx != midx) {
946 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
947 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
948 n->dump();
949 m->dump();
950 }
951 assert(C->subsume_loads() && C->must_alias(nat, midx),
952 "must not lose alias info when matching");
953 }
954 }
955 #endif
956
957
958 //------------------------------MStack-----------------------------------------
959 // State and MStack class used in xform() and find_shared() iterative methods.
960 enum Node_State { Pre_Visit, // node has to be pre-visited
961 Visit, // visit node
962 Post_Visit, // post-visit node
963 Alt_Post_Visit // alternative post-visit path
964 };
965
966 class MStack: public Node_Stack {
967 public:
968 MStack(int size) : Node_Stack(size) { }
969
970 void push(Node *n, Node_State ns) {
971 Node_Stack::push(n, (uint)ns);
972 }
973 void push(Node *n, Node_State ns, Node *parent, int indx) {
974 ++_inode_top;
975 if ((_inode_top + 1) >= _inode_max) grow();
976 _inode_top->node = parent;
977 _inode_top->indx = (uint)indx;
978 ++_inode_top;
979 _inode_top->node = n;
980 _inode_top->indx = (uint)ns;
981 }
982 Node *parent() {
983 pop();
984 return node();
985 }
986 Node_State state() const {
987 return (Node_State)index();
988 }
989 void set_state(Node_State ns) {
990 set_index((uint)ns);
991 }
992 };
993
994
995 //------------------------------xform------------------------------------------
996 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
997 // Node in new-space. Given a new-space Node, recursively walk his children.
998 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
999 Node *Matcher::xform( Node *n, int max_stack ) {
1000 // Use one stack to keep both: child's node/state and parent's node/index
1001 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1002 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1003
1004 while (mstack.is_nonempty()) {
1005 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1006 if (C->failing()) return NULL;
1007 n = mstack.node(); // Leave node on stack
1008 Node_State nstate = mstack.state();
1009 if (nstate == Visit) {
1010 mstack.set_state(Post_Visit);
1011 Node *oldn = n;
1012 // Old-space or new-space check
1013 if (!C->node_arena()->contains(n)) {
1014 // Old space!
1015 Node* m;
1016 if (has_new_node(n)) { // Not yet Label/Reduced
1017 m = new_node(n);
1018 } else {
1019 if (!is_dontcare(n)) { // Matcher can match this guy
1020 // Calls match special. They match alone with no children.
1021 // Their children, the incoming arguments, match normally.
1022 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1023 if (C->failing()) return NULL;
1024 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1025 if (n->is_MemBar() && UseShenandoahGC) {
1026 m->as_MachMemBar()->set_adr_type(n->adr_type());
1027 }
1028 } else { // Nothing the matcher cares about
1029 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1030 // Convert to machine-dependent projection
1031 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1032 #ifdef ASSERT
1033 _new2old_map.map(m->_idx, n);
1034 #endif
1035 if (m->in(0) != NULL) // m might be top
1036 collect_null_checks(m, n);
1037 } else { // Else just a regular 'ol guy
1038 m = n->clone(); // So just clone into new-space
1039 #ifdef ASSERT
1040 _new2old_map.map(m->_idx, n);
1041 #endif
1042 // Def-Use edges will be added incrementally as Uses
1043 // of this node are matched.
1044 assert(m->outcnt() == 0, "no Uses of this clone yet");
1045 }
1046 }
1047
1048 set_new_node(n, m); // Map old to new
1049 if (_old_node_note_array != NULL) {
1050 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1051 n->_idx);
1052 C->set_node_notes_at(m->_idx, nn);
1053 }
1054 debug_only(match_alias_type(C, n, m));
1055 }
1056 n = m; // n is now a new-space node
1057 mstack.set_node(n);
1058 }
1059
1060 // New space!
1061 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1062
1063 int i;
1064 // Put precedence edges on stack first (match them last).
1065 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1066 Node *m = oldn->in(i);
1067 if (m == NULL) break;
1068 // set -1 to call add_prec() instead of set_req() during Step1
1069 mstack.push(m, Visit, n, -1);
1070 }
1071
1072 // Handle precedence edges for interior nodes
1073 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1074 Node *m = n->in(i);
1075 if (m == NULL || C->node_arena()->contains(m)) continue;
1076 n->rm_prec(i);
1077 // set -1 to call add_prec() instead of set_req() during Step1
1078 mstack.push(m, Visit, n, -1);
1079 }
1080
1081 // For constant debug info, I'd rather have unmatched constants.
1082 int cnt = n->req();
1083 JVMState* jvms = n->jvms();
1084 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1085
1086 // Now do only debug info. Clone constants rather than matching.
1087 // Constants are represented directly in the debug info without
1088 // the need for executable machine instructions.
1089 // Monitor boxes are also represented directly.
1090 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1091 Node *m = n->in(i); // Get input
1092 int op = m->Opcode();
1093 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1094 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1095 op == Op_ConF || op == Op_ConD || op == Op_ConL
1096 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1097 ) {
1098 m = m->clone();
1099 #ifdef ASSERT
1100 _new2old_map.map(m->_idx, n);
1101 #endif
1102 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1103 mstack.push(m->in(0), Visit, m, 0);
1104 } else {
1105 mstack.push(m, Visit, n, i);
1106 }
1107 }
1108
1109 // And now walk his children, and convert his inputs to new-space.
1110 for( ; i >= 0; --i ) { // For all normal inputs do
1111 Node *m = n->in(i); // Get input
1112 if(m != NULL)
1113 mstack.push(m, Visit, n, i);
1114 }
1115
1116 }
1117 else if (nstate == Post_Visit) {
1118 // Set xformed input
1119 Node *p = mstack.parent();
1120 if (p != NULL) { // root doesn't have parent
1121 int i = (int)mstack.index();
1122 if (i >= 0)
1123 p->set_req(i, n); // required input
1124 else if (i == -1)
1125 p->add_prec(n); // precedence input
1126 else
1127 ShouldNotReachHere();
1128 }
1129 mstack.pop(); // remove processed node from stack
1130 }
1131 else {
1132 ShouldNotReachHere();
1133 }
1134 } // while (mstack.is_nonempty())
1135 return n; // Return new-space Node
1136 }
1137
1138 //------------------------------warp_outgoing_stk_arg------------------------
1139 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1140 // Convert outgoing argument location to a pre-biased stack offset
1141 if (reg->is_stack()) {
1142 OptoReg::Name warped = reg->reg2stack();
1143 // Adjust the stack slot offset to be the register number used
1144 // by the allocator.
1145 warped = OptoReg::add(begin_out_arg_area, warped);
1146 // Keep track of the largest numbered stack slot used for an arg.
1147 // Largest used slot per call-site indicates the amount of stack
1148 // that is killed by the call.
1149 if( warped >= out_arg_limit_per_call )
1150 out_arg_limit_per_call = OptoReg::add(warped,1);
1151 if (!RegMask::can_represent_arg(warped)) {
1152 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1153 return OptoReg::Bad;
1154 }
1155 return warped;
1156 }
1157 return OptoReg::as_OptoReg(reg);
1158 }
1159
1160
1161 //------------------------------match_sfpt-------------------------------------
1162 // Helper function to match call instructions. Calls match special.
1163 // They match alone with no children. Their children, the incoming
1164 // arguments, match normally.
1165 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1166 MachSafePointNode *msfpt = NULL;
1167 MachCallNode *mcall = NULL;
1168 uint cnt;
1169 // Split out case for SafePoint vs Call
1170 CallNode *call;
1171 const TypeTuple *domain;
1172 ciMethod* method = NULL;
1173 bool is_method_handle_invoke = false; // for special kill effects
1174 if( sfpt->is_Call() ) {
1175 call = sfpt->as_Call();
1176 domain = call->tf()->domain();
1177 cnt = domain->cnt();
1178
1179 // Match just the call, nothing else
1180 MachNode *m = match_tree(call);
1181 if (C->failing()) return NULL;
1182 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1183
1184 // Copy data from the Ideal SafePoint to the machine version
1185 mcall = m->as_MachCall();
1186
1187 mcall->set_tf( call->tf());
1188 mcall->set_entry_point(call->entry_point());
1189 mcall->set_cnt( call->cnt());
1190
1191 if( mcall->is_MachCallJava() ) {
1192 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1193 const CallJavaNode *call_java = call->as_CallJava();
1194 method = call_java->method();
1195 mcall_java->_method = method;
1196 mcall_java->_bci = call_java->_bci;
1197 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1198 is_method_handle_invoke = call_java->is_method_handle_invoke();
1199 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1200 if (is_method_handle_invoke) {
1201 C->set_has_method_handle_invokes(true);
1202 }
1203 if( mcall_java->is_MachCallStaticJava() )
1204 mcall_java->as_MachCallStaticJava()->_name =
1205 call_java->as_CallStaticJava()->_name;
1206 if( mcall_java->is_MachCallDynamicJava() )
1207 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1208 call_java->as_CallDynamicJava()->_vtable_index;
1209 }
1210 else if( mcall->is_MachCallRuntime() ) {
1211 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1212 }
1213 msfpt = mcall;
1214 }
1215 // This is a non-call safepoint
1216 else {
1217 call = NULL;
1218 domain = NULL;
1219 MachNode *mn = match_tree(sfpt);
1220 if (C->failing()) return NULL;
1221 msfpt = mn->as_MachSafePoint();
1222 cnt = TypeFunc::Parms;
1223 }
1224
1225 // Advertise the correct memory effects (for anti-dependence computation).
1226 msfpt->set_adr_type(sfpt->adr_type());
1227
1228 // Allocate a private array of RegMasks. These RegMasks are not shared.
1229 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1230 // Empty them all.
1231 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1232
1233 // Do all the pre-defined non-Empty register masks
1234 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1235 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1236
1237 // Place first outgoing argument can possibly be put.
1238 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1239 assert( is_even(begin_out_arg_area), "" );
1240 // Compute max outgoing register number per call site.
1241 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1242 // Calls to C may hammer extra stack slots above and beyond any arguments.
1243 // These are usually backing store for register arguments for varargs.
1244 if( call != NULL && call->is_CallRuntime() )
1245 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1246
1247
1248 // Do the normal argument list (parameters) register masks
1249 int argcnt = cnt - TypeFunc::Parms;
1250 if( argcnt > 0 ) { // Skip it all if we have no args
1251 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1252 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1253 int i;
1254 for( i = 0; i < argcnt; i++ ) {
1255 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1256 }
1257 // V-call to pick proper calling convention
1258 call->calling_convention( sig_bt, parm_regs, argcnt );
1259
1260 #ifdef ASSERT
1261 // Sanity check users' calling convention. Really handy during
1262 // the initial porting effort. Fairly expensive otherwise.
1263 { for (int i = 0; i<argcnt; i++) {
1264 if( !parm_regs[i].first()->is_valid() &&
1265 !parm_regs[i].second()->is_valid() ) continue;
1266 VMReg reg1 = parm_regs[i].first();
1267 VMReg reg2 = parm_regs[i].second();
1268 for (int j = 0; j < i; j++) {
1269 if( !parm_regs[j].first()->is_valid() &&
1270 !parm_regs[j].second()->is_valid() ) continue;
1271 VMReg reg3 = parm_regs[j].first();
1272 VMReg reg4 = parm_regs[j].second();
1273 if( !reg1->is_valid() ) {
1274 assert( !reg2->is_valid(), "valid halvsies" );
1275 } else if( !reg3->is_valid() ) {
1276 assert( !reg4->is_valid(), "valid halvsies" );
1277 } else {
1278 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1279 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1280 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1281 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1282 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1283 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1284 }
1285 }
1286 }
1287 }
1288 #endif
1289
1290 // Visit each argument. Compute its outgoing register mask.
1291 // Return results now can have 2 bits returned.
1292 // Compute max over all outgoing arguments both per call-site
1293 // and over the entire method.
1294 for( i = 0; i < argcnt; i++ ) {
1295 // Address of incoming argument mask to fill in
1296 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1297 if( !parm_regs[i].first()->is_valid() &&
1298 !parm_regs[i].second()->is_valid() ) {
1299 continue; // Avoid Halves
1300 }
1301 // Grab first register, adjust stack slots and insert in mask.
1302 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1303 if (OptoReg::is_valid(reg1))
1304 rm->Insert( reg1 );
1305 // Grab second register (if any), adjust stack slots and insert in mask.
1306 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1307 if (OptoReg::is_valid(reg2))
1308 rm->Insert( reg2 );
1309 } // End of for all arguments
1310
1311 // Compute number of stack slots needed to restore stack in case of
1312 // Pascal-style argument popping.
1313 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1314 }
1315
1316 // Compute the max stack slot killed by any call. These will not be
1317 // available for debug info, and will be used to adjust FIRST_STACK_mask
1318 // after all call sites have been visited.
1319 if( _out_arg_limit < out_arg_limit_per_call)
1320 _out_arg_limit = out_arg_limit_per_call;
1321
1322 if (mcall) {
1323 // Kill the outgoing argument area, including any non-argument holes and
1324 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1325 // Since the max-per-method covers the max-per-call-site and debug info
1326 // is excluded on the max-per-method basis, debug info cannot land in
1327 // this killed area.
1328 uint r_cnt = mcall->tf()->range()->cnt();
1329 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1330 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1331 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1332 } else {
1333 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1334 proj->_rout.Insert(OptoReg::Name(i));
1335 }
1336 if (proj->_rout.is_NotEmpty()) {
1337 push_projection(proj);
1338 }
1339 }
1340 // Transfer the safepoint information from the call to the mcall
1341 // Move the JVMState list
1342 msfpt->set_jvms(sfpt->jvms());
1343 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1344 jvms->set_map(sfpt);
1345 }
1346
1347 // Debug inputs begin just after the last incoming parameter
1348 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1349 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1350
1351 // Move the OopMap
1352 msfpt->_oop_map = sfpt->_oop_map;
1353
1354 // Add additional edges.
1355 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1356 // For these calls we can not add MachConstantBase in expand(), as the
1357 // ins are not complete then.
1358 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1359 if (msfpt->jvms() &&
1360 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1361 // We added an edge before jvms, so we must adapt the position of the ins.
1362 msfpt->jvms()->adapt_position(+1);
1363 }
1364 }
1365
1366 // Registers killed by the call are set in the local scheduling pass
1367 // of Global Code Motion.
1368 return msfpt;
1369 }
1370
1371 //---------------------------match_tree----------------------------------------
1372 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1373 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1374 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1375 // a Load's result RegMask for memoization in idealreg2regmask[]
1376 MachNode *Matcher::match_tree( const Node *n ) {
1377 assert( n->Opcode() != Op_Phi, "cannot match" );
1378 assert( !n->is_block_start(), "cannot match" );
1379 // Set the mark for all locally allocated State objects.
1380 // When this call returns, the _states_arena arena will be reset
1381 // freeing all State objects.
1382 ResourceMark rm( &_states_arena );
1383
1384 LabelRootDepth = 0;
1385
1386 // StoreNodes require their Memory input to match any LoadNodes
1387 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1388 #ifdef ASSERT
1389 Node* save_mem_node = _mem_node;
1390 _mem_node = n->is_Store() ? (Node*)n : NULL;
1391 #endif
1392 // State object for root node of match tree
1393 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1394 State *s = new (&_states_arena) State;
1395 s->_kids[0] = NULL;
1396 s->_kids[1] = NULL;
1397 s->_leaf = (Node*)n;
1398 // Label the input tree, allocating labels from top-level arena
1399 Label_Root( n, s, n->in(0), mem );
1400 if (C->failing()) return NULL;
1401
1402 // The minimum cost match for the whole tree is found at the root State
1403 uint mincost = max_juint;
1404 uint cost = max_juint;
1405 uint i;
1406 for( i = 0; i < NUM_OPERANDS; i++ ) {
1407 if( s->valid(i) && // valid entry and
1408 s->_cost[i] < cost && // low cost and
1409 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1410 cost = s->_cost[mincost=i];
1411 }
1412 if (mincost == max_juint) {
1413 #ifndef PRODUCT
1414 tty->print("No matching rule for:");
1415 s->dump();
1416 #endif
1417 Matcher::soft_match_failure();
1418 return NULL;
1419 }
1420 // Reduce input tree based upon the state labels to machine Nodes
1421 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1422 #ifdef ASSERT
1423 _old2new_map.map(n->_idx, m);
1424 _new2old_map.map(m->_idx, (Node*)n);
1425 #endif
1426
1427 // Add any Matcher-ignored edges
1428 uint cnt = n->req();
1429 uint start = 1;
1430 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1431 if( n->is_AddP() ) {
1432 assert( mem == (Node*)1, "" );
1433 start = AddPNode::Base+1;
1434 }
1435 for( i = start; i < cnt; i++ ) {
1436 if( !n->match_edge(i) ) {
1437 if( i < m->req() )
1438 m->ins_req( i, n->in(i) );
1439 else
1440 m->add_req( n->in(i) );
1441 }
1442 }
1443
1444 debug_only( _mem_node = save_mem_node; )
1445 return m;
1446 }
1447
1448
1449 //------------------------------match_into_reg---------------------------------
1450 // Choose to either match this Node in a register or part of the current
1451 // match tree. Return true for requiring a register and false for matching
1452 // as part of the current match tree.
1453 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1454
1455 const Type *t = m->bottom_type();
1456
1457 if (t->singleton()) {
1458 // Never force constants into registers. Allow them to match as
1459 // constants or registers. Copies of the same value will share
1460 // the same register. See find_shared_node.
1461 return false;
1462 } else { // Not a constant
1463 // Stop recursion if they have different Controls.
1464 Node* m_control = m->in(0);
1465 // Control of load's memory can post-dominates load's control.
1466 // So use it since load can't float above its memory.
1467 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1468 if (control && m_control && control != m_control && control != mem_control) {
1469
1470 // Actually, we can live with the most conservative control we
1471 // find, if it post-dominates the others. This allows us to
1472 // pick up load/op/store trees where the load can float a little
1473 // above the store.
1474 Node *x = control;
1475 const uint max_scan = 6; // Arbitrary scan cutoff
1476 uint j;
1477 for (j=0; j<max_scan; j++) {
1478 if (x->is_Region()) // Bail out at merge points
1479 return true;
1480 x = x->in(0);
1481 if (x == m_control) // Does 'control' post-dominate
1482 break; // m->in(0)? If so, we can use it
1483 if (x == mem_control) // Does 'control' post-dominate
1484 break; // mem_control? If so, we can use it
1485 }
1486 if (j == max_scan) // No post-domination before scan end?
1487 return true; // Then break the match tree up
1488 }
1489 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1490 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1491 // These are commonly used in address expressions and can
1492 // efficiently fold into them on X64 in some cases.
1493 return false;
1494 }
1495 }
1496
1497 // Not forceable cloning. If shared, put it into a register.
1498 return shared;
1499 }
1500
1501
1502 //------------------------------Instruction Selection--------------------------
1503 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1504 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1505 // things the Matcher does not match (e.g., Memory), and things with different
1506 // Controls (hence forced into different blocks). We pass in the Control
1507 // selected for this entire State tree.
1508
1509 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1510 // Store and the Load must have identical Memories (as well as identical
1511 // pointers). Since the Matcher does not have anything for Memory (and
1512 // does not handle DAGs), I have to match the Memory input myself. If the
1513 // Tree root is a Store, I require all Loads to have the identical memory.
1514 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1515 // Since Label_Root is a recursive function, its possible that we might run
1516 // out of stack space. See bugs 6272980 & 6227033 for more info.
1517 LabelRootDepth++;
1518 if (LabelRootDepth > MaxLabelRootDepth) {
1519 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1520 return NULL;
1521 }
1522 uint care = 0; // Edges matcher cares about
1523 uint cnt = n->req();
1524 uint i = 0;
1525
1526 // Examine children for memory state
1527 // Can only subsume a child into your match-tree if that child's memory state
1528 // is not modified along the path to another input.
1529 // It is unsafe even if the other inputs are separate roots.
1530 Node *input_mem = NULL;
1531 for( i = 1; i < cnt; i++ ) {
1532 if( !n->match_edge(i) ) continue;
1533 Node *m = n->in(i); // Get ith input
1534 assert( m, "expect non-null children" );
1535 if( m->is_Load() ) {
1536 if( input_mem == NULL ) {
1537 input_mem = m->in(MemNode::Memory);
1538 } else if( input_mem != m->in(MemNode::Memory) ) {
1539 input_mem = NodeSentinel;
1540 }
1541 }
1542 }
1543
1544 for( i = 1; i < cnt; i++ ){// For my children
1545 if( !n->match_edge(i) ) continue;
1546 Node *m = n->in(i); // Get ith input
1547 // Allocate states out of a private arena
1548 State *s = new (&_states_arena) State;
1549 svec->_kids[care++] = s;
1550 assert( care <= 2, "binary only for now" );
1551
1552 // Recursively label the State tree.
1553 s->_kids[0] = NULL;
1554 s->_kids[1] = NULL;
1555 s->_leaf = m;
1556
1557 // Check for leaves of the State Tree; things that cannot be a part of
1558 // the current tree. If it finds any, that value is matched as a
1559 // register operand. If not, then the normal matching is used.
1560 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1561 //
1562 // Stop recursion if this is LoadNode and the root of this tree is a
1563 // StoreNode and the load & store have different memories.
1564 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1565 // Can NOT include the match of a subtree when its memory state
1566 // is used by any of the other subtrees
1567 (input_mem == NodeSentinel) ) {
1568 #ifndef PRODUCT
1569 // Print when we exclude matching due to different memory states at input-loads
1570 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1571 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1572 tty->print_cr("invalid input_mem");
1573 }
1574 #endif
1575 // Switch to a register-only opcode; this value must be in a register
1576 // and cannot be subsumed as part of a larger instruction.
1577 s->DFA( m->ideal_reg(), m );
1578
1579 } else {
1580 // If match tree has no control and we do, adopt it for entire tree
1581 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1582 control = m->in(0); // Pick up control
1583 // Else match as a normal part of the match tree.
1584 control = Label_Root(m,s,control,mem);
1585 if (C->failing()) return NULL;
1586 }
1587 }
1588
1589
1590 // Call DFA to match this node, and return
1591 svec->DFA( n->Opcode(), n );
1592
1593 #ifdef ASSERT
1594 uint x;
1595 for( x = 0; x < _LAST_MACH_OPER; x++ )
1596 if( svec->valid(x) )
1597 break;
1598
1599 if (x >= _LAST_MACH_OPER) {
1600 n->dump();
1601 svec->dump();
1602 assert( false, "bad AD file" );
1603 }
1604 #endif
1605 return control;
1606 }
1607
1608
1609 // Con nodes reduced using the same rule can share their MachNode
1610 // which reduces the number of copies of a constant in the final
1611 // program. The register allocator is free to split uses later to
1612 // split live ranges.
1613 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1614 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1615
1616 // See if this Con has already been reduced using this rule.
1617 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1618 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1619 if (last != NULL && rule == last->rule()) {
1620 // Don't expect control change for DecodeN
1621 if (leaf->is_DecodeNarrowPtr())
1622 return last;
1623 // Get the new space root.
1624 Node* xroot = new_node(C->root());
1625 if (xroot == NULL) {
1626 // This shouldn't happen give the order of matching.
1627 return NULL;
1628 }
1629
1630 // Shared constants need to have their control be root so they
1631 // can be scheduled properly.
1632 Node* control = last->in(0);
1633 if (control != xroot) {
1634 if (control == NULL || control == C->root()) {
1635 last->set_req(0, xroot);
1636 } else {
1637 assert(false, "unexpected control");
1638 return NULL;
1639 }
1640 }
1641 return last;
1642 }
1643 return NULL;
1644 }
1645
1646
1647 //------------------------------ReduceInst-------------------------------------
1648 // Reduce a State tree (with given Control) into a tree of MachNodes.
1649 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1650 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1651 // Each MachNode has a number of complicated MachOper operands; each
1652 // MachOper also covers a further tree of Ideal Nodes.
1653
1654 // The root of the Ideal match tree is always an instruction, so we enter
1655 // the recursion here. After building the MachNode, we need to recurse
1656 // the tree checking for these cases:
1657 // (1) Child is an instruction -
1658 // Build the instruction (recursively), add it as an edge.
1659 // Build a simple operand (register) to hold the result of the instruction.
1660 // (2) Child is an interior part of an instruction -
1661 // Skip over it (do nothing)
1662 // (3) Child is the start of a operand -
1663 // Build the operand, place it inside the instruction
1664 // Call ReduceOper.
1665 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1666 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1667
1668 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1669 if (shared_node != NULL) {
1670 return shared_node;
1671 }
1672
1673 // Build the object to represent this state & prepare for recursive calls
1674 MachNode *mach = s->MachNodeGenerator( rule, C );
1675 guarantee(mach != NULL, "Missing MachNode");
1676 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1677 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1678 Node *leaf = s->_leaf;
1679 // Check for instruction or instruction chain rule
1680 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1681 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1682 "duplicating node that's already been matched");
1683 // Instruction
1684 mach->add_req( leaf->in(0) ); // Set initial control
1685 // Reduce interior of complex instruction
1686 ReduceInst_Interior( s, rule, mem, mach, 1 );
1687 } else {
1688 // Instruction chain rules are data-dependent on their inputs
1689 mach->add_req(0); // Set initial control to none
1690 ReduceInst_Chain_Rule( s, rule, mem, mach );
1691 }
1692
1693 // If a Memory was used, insert a Memory edge
1694 if( mem != (Node*)1 ) {
1695 mach->ins_req(MemNode::Memory,mem);
1696 #ifdef ASSERT
1697 // Verify adr type after matching memory operation
1698 const MachOper* oper = mach->memory_operand();
1699 if (oper != NULL && oper != (MachOper*)-1) {
1700 // It has a unique memory operand. Find corresponding ideal mem node.
1701 Node* m = NULL;
1702 if (leaf->is_Mem()) {
1703 m = leaf;
1704 } else {
1705 m = _mem_node;
1706 assert(m != NULL && m->is_Mem(), "expecting memory node");
1707 }
1708 const Type* mach_at = mach->adr_type();
1709 // DecodeN node consumed by an address may have different type
1710 // then its input. Don't compare types for such case.
1711 if (m->adr_type() != mach_at &&
1712 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1713 m->in(MemNode::Address)->is_AddP() &&
1714 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1715 m->in(MemNode::Address)->is_AddP() &&
1716 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1717 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1718 mach_at = m->adr_type();
1719 }
1720 if (m->adr_type() != mach_at) {
1721 m->dump();
1722 tty->print_cr("mach:");
1723 mach->dump(1);
1724 }
1725 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1726 }
1727 #endif
1728 }
1729
1730 // If the _leaf is an AddP, insert the base edge
1731 if (leaf->is_AddP()) {
1732 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1733 }
1734
1735 uint number_of_projections_prior = number_of_projections();
1736
1737 // Perform any 1-to-many expansions required
1738 MachNode *ex = mach->Expand(s, _projection_list, mem);
1739 if (ex != mach) {
1740 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1741 if( ex->in(1)->is_Con() )
1742 ex->in(1)->set_req(0, C->root());
1743 // Remove old node from the graph
1744 for( uint i=0; i<mach->req(); i++ ) {
1745 mach->set_req(i,NULL);
1746 }
1747 #ifdef ASSERT
1748 _new2old_map.map(ex->_idx, s->_leaf);
1749 #endif
1750 }
1751
1752 // PhaseChaitin::fixup_spills will sometimes generate spill code
1753 // via the matcher. By the time, nodes have been wired into the CFG,
1754 // and any further nodes generated by expand rules will be left hanging
1755 // in space, and will not get emitted as output code. Catch this.
1756 // Also, catch any new register allocation constraints ("projections")
1757 // generated belatedly during spill code generation.
1758 if (_allocation_started) {
1759 guarantee(ex == mach, "no expand rules during spill generation");
1760 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1761 }
1762
1763 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1764 // Record the con for sharing
1765 _shared_nodes.map(leaf->_idx, ex);
1766 }
1767
1768 return ex;
1769 }
1770
1771 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1772 for (uint i = n->req(); i < n->len(); i++) {
1773 if (n->in(i) != NULL) {
1774 mach->add_prec(n->in(i));
1775 }
1776 }
1777 }
1778
1779 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1780 // 'op' is what I am expecting to receive
1781 int op = _leftOp[rule];
1782 // Operand type to catch childs result
1783 // This is what my child will give me.
1784 int opnd_class_instance = s->_rule[op];
1785 // Choose between operand class or not.
1786 // This is what I will receive.
1787 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1788 // New rule for child. Chase operand classes to get the actual rule.
1789 int newrule = s->_rule[catch_op];
1790
1791 if( newrule < NUM_OPERANDS ) {
1792 // Chain from operand or operand class, may be output of shared node
1793 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1794 "Bad AD file: Instruction chain rule must chain from operand");
1795 // Insert operand into array of operands for this instruction
1796 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1797
1798 ReduceOper( s, newrule, mem, mach );
1799 } else {
1800 // Chain from the result of an instruction
1801 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1802 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1803 Node *mem1 = (Node*)1;
1804 debug_only(Node *save_mem_node = _mem_node;)
1805 mach->add_req( ReduceInst(s, newrule, mem1) );
1806 debug_only(_mem_node = save_mem_node;)
1807 }
1808 return;
1809 }
1810
1811
1812 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1813 handle_precedence_edges(s->_leaf, mach);
1814
1815 if( s->_leaf->is_Load() ) {
1816 Node *mem2 = s->_leaf->in(MemNode::Memory);
1817 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1818 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1819 mem = mem2;
1820 }
1821 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1822 if( mach->in(0) == NULL )
1823 mach->set_req(0, s->_leaf->in(0));
1824 }
1825
1826 // Now recursively walk the state tree & add operand list.
1827 for( uint i=0; i<2; i++ ) { // binary tree
1828 State *newstate = s->_kids[i];
1829 if( newstate == NULL ) break; // Might only have 1 child
1830 // 'op' is what I am expecting to receive
1831 int op;
1832 if( i == 0 ) {
1833 op = _leftOp[rule];
1834 } else {
1835 op = _rightOp[rule];
1836 }
1837 // Operand type to catch childs result
1838 // This is what my child will give me.
1839 int opnd_class_instance = newstate->_rule[op];
1840 // Choose between operand class or not.
1841 // This is what I will receive.
1842 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1843 // New rule for child. Chase operand classes to get the actual rule.
1844 int newrule = newstate->_rule[catch_op];
1845
1846 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1847 // Operand/operandClass
1848 // Insert operand into array of operands for this instruction
1849 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1850 ReduceOper( newstate, newrule, mem, mach );
1851
1852 } else { // Child is internal operand or new instruction
1853 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1854 // internal operand --> call ReduceInst_Interior
1855 // Interior of complex instruction. Do nothing but recurse.
1856 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1857 } else {
1858 // instruction --> call build operand( ) to catch result
1859 // --> ReduceInst( newrule )
1860 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1861 Node *mem1 = (Node*)1;
1862 debug_only(Node *save_mem_node = _mem_node;)
1863 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1864 debug_only(_mem_node = save_mem_node;)
1865 }
1866 }
1867 assert( mach->_opnds[num_opnds-1], "" );
1868 }
1869 return num_opnds;
1870 }
1871
1872 // This routine walks the interior of possible complex operands.
1873 // At each point we check our children in the match tree:
1874 // (1) No children -
1875 // We are a leaf; add _leaf field as an input to the MachNode
1876 // (2) Child is an internal operand -
1877 // Skip over it ( do nothing )
1878 // (3) Child is an instruction -
1879 // Call ReduceInst recursively and
1880 // and instruction as an input to the MachNode
1881 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1882 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1883 State *kid = s->_kids[0];
1884 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1885
1886 // Leaf? And not subsumed?
1887 if( kid == NULL && !_swallowed[rule] ) {
1888 mach->add_req( s->_leaf ); // Add leaf pointer
1889 return; // Bail out
1890 }
1891
1892 if( s->_leaf->is_Load() ) {
1893 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1894 mem = s->_leaf->in(MemNode::Memory);
1895 debug_only(_mem_node = s->_leaf;)
1896 }
1897
1898 handle_precedence_edges(s->_leaf, mach);
1899
1900 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1901 if( !mach->in(0) )
1902 mach->set_req(0,s->_leaf->in(0));
1903 else {
1904 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1905 }
1906 }
1907
1908 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1909 int newrule;
1910 if( i == 0)
1911 newrule = kid->_rule[_leftOp[rule]];
1912 else
1913 newrule = kid->_rule[_rightOp[rule]];
1914
1915 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1916 // Internal operand; recurse but do nothing else
1917 ReduceOper( kid, newrule, mem, mach );
1918
1919 } else { // Child is a new instruction
1920 // Reduce the instruction, and add a direct pointer from this
1921 // machine instruction to the newly reduced one.
1922 Node *mem1 = (Node*)1;
1923 debug_only(Node *save_mem_node = _mem_node;)
1924 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1925 debug_only(_mem_node = save_mem_node;)
1926 }
1927 }
1928 }
1929
1930
1931 // -------------------------------------------------------------------------
1932 // Java-Java calling convention
1933 // (what you use when Java calls Java)
1934
1935 //------------------------------find_receiver----------------------------------
1936 // For a given signature, return the OptoReg for parameter 0.
1937 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1938 VMRegPair regs;
1939 BasicType sig_bt = T_OBJECT;
1940 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1941 // Return argument 0 register. In the LP64 build pointers
1942 // take 2 registers, but the VM wants only the 'main' name.
1943 return OptoReg::as_OptoReg(regs.first());
1944 }
1945
1946 // This function identifies sub-graphs in which a 'load' node is
1947 // input to two different nodes, and such that it can be matched
1948 // with BMI instructions like blsi, blsr, etc.
1949 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1950 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1951 // refers to the same node.
1952 #ifdef X86
1953 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1954 // This is a temporary solution until we make DAGs expressible in ADL.
1955 template<typename ConType>
1956 class FusedPatternMatcher {
1957 Node* _op1_node;
1958 Node* _mop_node;
1959 int _con_op;
1960
1961 static int match_next(Node* n, int next_op, int next_op_idx) {
1962 if (n->in(1) == NULL || n->in(2) == NULL) {
1963 return -1;
1964 }
1965
1966 if (next_op_idx == -1) { // n is commutative, try rotations
1967 if (n->in(1)->Opcode() == next_op) {
1968 return 1;
1969 } else if (n->in(2)->Opcode() == next_op) {
1970 return 2;
1971 }
1972 } else {
1973 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1974 if (n->in(next_op_idx)->Opcode() == next_op) {
1975 return next_op_idx;
1976 }
1977 }
1978 return -1;
1979 }
1980 public:
1981 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1982 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1983
1984 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1985 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1986 typename ConType::NativeType con_value) {
1987 if (_op1_node->Opcode() != op1) {
1988 return false;
1989 }
1990 if (_mop_node->outcnt() > 2) {
1991 return false;
1992 }
1993 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1994 if (op1_op2_idx == -1) {
1995 return false;
1996 }
1997 // Memory operation must be the other edge
1998 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1999
2000 // Check that the mop node is really what we want
2001 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2002 Node *op2_node = _op1_node->in(op1_op2_idx);
2003 if (op2_node->outcnt() > 1) {
2004 return false;
2005 }
2006 assert(op2_node->Opcode() == op2, "Should be");
2007 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2008 if (op2_con_idx == -1) {
2009 return false;
2010 }
2011 // Memory operation must be the other edge
2012 int op2_mop_idx = (op2_con_idx & 1) + 1;
2013 // Check that the memory operation is the same node
2014 if (op2_node->in(op2_mop_idx) == _mop_node) {
2015 // Now check the constant
2016 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2017 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2018 return true;
2019 }
2020 }
2021 }
2022 return false;
2023 }
2024 };
2025
2026
2027 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2028 if (n != NULL && m != NULL) {
2029 if (m->Opcode() == Op_LoadI) {
2030 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2031 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2032 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2033 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2034 } else if (m->Opcode() == Op_LoadL) {
2035 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2036 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2037 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2038 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2039 }
2040 }
2041 return false;
2042 }
2043 #endif // X86
2044
2045 // A method-klass-holder may be passed in the inline_cache_reg
2046 // and then expanded into the inline_cache_reg and a method_oop register
2047 // defined in ad_<arch>.cpp
2048
2049
2050 //------------------------------find_shared------------------------------------
2051 // Set bits if Node is shared or otherwise a root
2052 void Matcher::find_shared( Node *n ) {
2053 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2054 MStack mstack(C->live_nodes() * 2);
2055 // Mark nodes as address_visited if they are inputs to an address expression
2056 VectorSet address_visited(Thread::current()->resource_area());
2057 mstack.push(n, Visit); // Don't need to pre-visit root node
2058 while (mstack.is_nonempty()) {
2059 n = mstack.node(); // Leave node on stack
2060 Node_State nstate = mstack.state();
2061 uint nop = n->Opcode();
2062 if (nstate == Pre_Visit) {
2063 if (address_visited.test(n->_idx)) { // Visited in address already?
2064 // Flag as visited and shared now.
2065 set_visited(n);
2066 }
2067 if (is_visited(n)) { // Visited already?
2068 // Node is shared and has no reason to clone. Flag it as shared.
2069 // This causes it to match into a register for the sharing.
2070 set_shared(n); // Flag as shared and
2071 mstack.pop(); // remove node from stack
2072 continue;
2073 }
2074 nstate = Visit; // Not already visited; so visit now
2075 }
2076 if (nstate == Visit) {
2077 mstack.set_state(Post_Visit);
2078 set_visited(n); // Flag as visited now
2079 bool mem_op = false;
2080
2081 switch( nop ) { // Handle some opcodes special
2082 case Op_Phi: // Treat Phis as shared roots
2083 case Op_Parm:
2084 case Op_Proj: // All handled specially during matching
2085 case Op_SafePointScalarObject:
2086 set_shared(n);
2087 set_dontcare(n);
2088 break;
2089 case Op_If:
2090 case Op_CountedLoopEnd:
2091 mstack.set_state(Alt_Post_Visit); // Alternative way
2092 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2093 // with matching cmp/branch in 1 instruction. The Matcher needs the
2094 // Bool and CmpX side-by-side, because it can only get at constants
2095 // that are at the leaves of Match trees, and the Bool's condition acts
2096 // as a constant here.
2097 mstack.push(n->in(1), Visit); // Clone the Bool
2098 mstack.push(n->in(0), Pre_Visit); // Visit control input
2099 continue; // while (mstack.is_nonempty())
2100 case Op_ConvI2D: // These forms efficiently match with a prior
2101 case Op_ConvI2F: // Load but not a following Store
2102 if( n->in(1)->is_Load() && // Prior load
2103 n->outcnt() == 1 && // Not already shared
2104 n->unique_out()->is_Store() ) // Following store
2105 set_shared(n); // Force it to be a root
2106 break;
2107 case Op_ReverseBytesI:
2108 case Op_ReverseBytesL:
2109 if( n->in(1)->is_Load() && // Prior load
2110 n->outcnt() == 1 ) // Not already shared
2111 set_shared(n); // Force it to be a root
2112 break;
2113 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2114 case Op_IfFalse:
2115 case Op_IfTrue:
2116 case Op_MachProj:
2117 case Op_MergeMem:
2118 case Op_Catch:
2119 case Op_CatchProj:
2120 case Op_CProj:
2121 case Op_JumpProj:
2122 case Op_JProj:
2123 case Op_NeverBranch:
2124 set_dontcare(n);
2125 break;
2126 case Op_Jump:
2127 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2128 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2129 continue; // while (mstack.is_nonempty())
2130 case Op_StrComp:
2131 case Op_StrEquals:
2132 case Op_StrIndexOf:
2133 case Op_AryEq:
2134 case Op_EncodeISOArray:
2135 set_shared(n); // Force result into register (it will be anyways)
2136 break;
2137 case Op_ConP: { // Convert pointers above the centerline to NUL
2138 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2139 const TypePtr* tp = tn->type()->is_ptr();
2140 if (tp->_ptr == TypePtr::AnyNull) {
2141 tn->set_type(TypePtr::NULL_PTR);
2142 }
2143 break;
2144 }
2145 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2146 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2147 const TypePtr* tp = tn->type()->make_ptr();
2148 if (tp && tp->_ptr == TypePtr::AnyNull) {
2149 tn->set_type(TypeNarrowOop::NULL_PTR);
2150 }
2151 break;
2152 }
2153 case Op_Binary: // These are introduced in the Post_Visit state.
2154 ShouldNotReachHere();
2155 break;
2156 case Op_ClearArray:
2157 case Op_SafePoint:
2158 mem_op = true;
2159 break;
2160 case Op_ShenandoahReadBarrier:
2161 if (n->in(ShenandoahBarrierNode::ValueIn)->is_DecodeNarrowPtr()) {
2162 set_shared(n->in(ShenandoahBarrierNode::ValueIn)->in(1));
2163 }
2164 mem_op = true;
2165 set_shared(n);
2166 break;
2167 default:
2168 if( n->is_Store() ) {
2169 // Do match stores, despite no ideal reg
2170 mem_op = true;
2171 break;
2172 }
2173 if( n->is_Mem() ) { // Loads and LoadStores
2174 mem_op = true;
2175 // Loads must be root of match tree due to prior load conflict
2176 if( C->subsume_loads() == false )
2177 set_shared(n);
2178 }
2179 // Fall into default case
2180 if( !n->ideal_reg() )
2181 set_dontcare(n); // Unmatchable Nodes
2182 } // end_switch
2183
2184 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2185 Node *m = n->in(i); // Get ith input
2186 if (m == NULL) continue; // Ignore NULLs
2187 uint mop = m->Opcode();
2188
2189 // Must clone all producers of flags, or we will not match correctly.
2190 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2191 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2192 // are also there, so we may match a float-branch to int-flags and
2193 // expect the allocator to haul the flags from the int-side to the
2194 // fp-side. No can do.
2195 if( _must_clone[mop] ) {
2196 mstack.push(m, Visit);
2197 continue; // for(int i = ...)
2198 }
2199
2200 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2201 // Bases used in addresses must be shared but since
2202 // they are shared through a DecodeN they may appear
2203 // to have a single use so force sharing here.
2204 set_shared(m->in(AddPNode::Base)->in(1));
2205 }
2206
2207 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2208 #ifdef X86
2209 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2210 mstack.push(m, Visit);
2211 continue;
2212 }
2213 #endif
2214
2215 // Clone addressing expressions as they are "free" in memory access instructions
2216 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2217 // Some inputs for address expression are not put on stack
2218 // to avoid marking them as shared and forcing them into register
2219 // if they are used only in address expressions.
2220 // But they should be marked as shared if there are other uses
2221 // besides address expressions.
2222
2223 Node *off = m->in(AddPNode::Offset);
2224 if( off->is_Con() &&
2225 // When there are other uses besides address expressions
2226 // put it on stack and mark as shared.
2227 !is_visited(m) ) {
2228 address_visited.test_set(m->_idx); // Flag as address_visited
2229 Node *adr = m->in(AddPNode::Address);
2230
2231 // Intel, ARM and friends can handle 2 adds in addressing mode
2232 if( clone_shift_expressions && adr->is_AddP() &&
2233 // AtomicAdd is not an addressing expression.
2234 // Cheap to find it by looking for screwy base.
2235 !adr->in(AddPNode::Base)->is_top() &&
2236 // Are there other uses besides address expressions?
2237 !is_visited(adr) ) {
2238 address_visited.set(adr->_idx); // Flag as address_visited
2239 Node *shift = adr->in(AddPNode::Offset);
2240 // Check for shift by small constant as well
2241 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2242 shift->in(2)->get_int() <= 3 &&
2243 // Are there other uses besides address expressions?
2244 !is_visited(shift) ) {
2245 address_visited.set(shift->_idx); // Flag as address_visited
2246 mstack.push(shift->in(2), Visit);
2247 Node *conv = shift->in(1);
2248 #ifdef _LP64
2249 // Allow Matcher to match the rule which bypass
2250 // ConvI2L operation for an array index on LP64
2251 // if the index value is positive.
2252 if( conv->Opcode() == Op_ConvI2L &&
2253 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2254 // Are there other uses besides address expressions?
2255 !is_visited(conv) ) {
2256 address_visited.set(conv->_idx); // Flag as address_visited
2257 mstack.push(conv->in(1), Pre_Visit);
2258 } else
2259 #endif
2260 mstack.push(conv, Pre_Visit);
2261 } else {
2262 mstack.push(shift, Pre_Visit);
2263 }
2264 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2265 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2266 } else { // Sparc, Alpha, PPC and friends
2267 mstack.push(adr, Pre_Visit);
2268 }
2269
2270 // Clone X+offset as it also folds into most addressing expressions
2271 mstack.push(off, Visit);
2272 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2273 continue; // for(int i = ...)
2274 } // if( off->is_Con() )
2275 } // if( mem_op &&
2276 mstack.push(m, Pre_Visit);
2277 } // for(int i = ...)
2278 }
2279 else if (nstate == Alt_Post_Visit) {
2280 mstack.pop(); // Remove node from stack
2281 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2282 // shared and all users of the Bool need to move the Cmp in parallel.
2283 // This leaves both the Bool and the If pointing at the Cmp. To
2284 // prevent the Matcher from trying to Match the Cmp along both paths
2285 // BoolNode::match_edge always returns a zero.
2286
2287 // We reorder the Op_If in a pre-order manner, so we can visit without
2288 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2289 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2290 }
2291 else if (nstate == Post_Visit) {
2292 mstack.pop(); // Remove node from stack
2293
2294 // Now hack a few special opcodes
2295 switch( n->Opcode() ) { // Handle some opcodes special
2296 case Op_StorePConditional:
2297 case Op_StoreIConditional:
2298 case Op_StoreLConditional:
2299 case Op_CompareAndSwapI:
2300 case Op_CompareAndSwapL:
2301 case Op_CompareAndSwapP:
2302 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2303 Node *newval = n->in(MemNode::ValueIn );
2304 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2305 Node *pair = new (C) BinaryNode( oldval, newval );
2306 n->set_req(MemNode::ValueIn,pair);
2307 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2308 break;
2309 }
2310 case Op_CMoveD: // Convert trinary to binary-tree
2311 case Op_CMoveF:
2312 case Op_CMoveI:
2313 case Op_CMoveL:
2314 case Op_CMoveN:
2315 case Op_CMoveP: {
2316 // Restructure into a binary tree for Matching. It's possible that
2317 // we could move this code up next to the graph reshaping for IfNodes
2318 // or vice-versa, but I do not want to debug this for Ladybird.
2319 // 10/2/2000 CNC.
2320 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2321 n->set_req(1,pair1);
2322 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2323 n->set_req(2,pair2);
2324 n->del_req(3);
2325 break;
2326 }
2327 case Op_LoopLimit: {
2328 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2329 n->set_req(1,pair1);
2330 n->set_req(2,n->in(3));
2331 n->del_req(3);
2332 break;
2333 }
2334 case Op_StrEquals: {
2335 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2336 n->set_req(2,pair1);
2337 n->set_req(3,n->in(4));
2338 n->del_req(4);
2339 break;
2340 }
2341 case Op_StrComp:
2342 case Op_StrIndexOf: {
2343 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2344 n->set_req(2,pair1);
2345 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2346 n->set_req(3,pair2);
2347 n->del_req(5);
2348 n->del_req(4);
2349 break;
2350 }
2351 case Op_EncodeISOArray: {
2352 // Restructure into a binary tree for Matching.
2353 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2354 n->set_req(3, pair);
2355 n->del_req(4);
2356 break;
2357 }
2358 default:
2359 break;
2360 }
2361 }
2362 else {
2363 ShouldNotReachHere();
2364 }
2365 } // end of while (mstack.is_nonempty())
2366 }
2367
2368 #ifdef ASSERT
2369 // machine-independent root to machine-dependent root
2370 void Matcher::dump_old2new_map() {
2371 _old2new_map.dump();
2372 }
2373 #endif
2374
2375 //---------------------------collect_null_checks-------------------------------
2376 // Find null checks in the ideal graph; write a machine-specific node for
2377 // it. Used by later implicit-null-check handling. Actually collects
2378 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2379 // value being tested.
2380 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2381 Node *iff = proj->in(0);
2382 if( iff->Opcode() == Op_If ) {
2383 // During matching If's have Bool & Cmp side-by-side
2384 BoolNode *b = iff->in(1)->as_Bool();
2385 Node *cmp = iff->in(2);
2386 int opc = cmp->Opcode();
2387 if (opc != Op_CmpP && opc != Op_CmpN) return;
2388
2389 const Type* ct = cmp->in(2)->bottom_type();
2390 if (ct == TypePtr::NULL_PTR ||
2391 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2392
2393 bool push_it = false;
2394 if( proj->Opcode() == Op_IfTrue ) {
2395 extern int all_null_checks_found;
2396 all_null_checks_found++;
2397 if( b->_test._test == BoolTest::ne ) {
2398 push_it = true;
2399 }
2400 } else {
2401 assert( proj->Opcode() == Op_IfFalse, "" );
2402 if( b->_test._test == BoolTest::eq ) {
2403 push_it = true;
2404 }
2405 }
2406 if( push_it ) {
2407 _null_check_tests.push(proj);
2408 Node* val = cmp->in(1);
2409 #ifdef _LP64
2410 if (val->bottom_type()->isa_narrowoop() &&
2411 !Matcher::narrow_oop_use_complex_address()) {
2412 //
2413 // Look for DecodeN node which should be pinned to orig_proj.
2414 // On platforms (Sparc) which can not handle 2 adds
2415 // in addressing mode we have to keep a DecodeN node and
2416 // use it to do implicit NULL check in address.
2417 //
2418 // DecodeN node was pinned to non-null path (orig_proj) during
2419 // CastPP transformation in final_graph_reshaping_impl().
2420 //
2421 uint cnt = orig_proj->outcnt();
2422 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2423 Node* d = orig_proj->raw_out(i);
2424 if (d->is_DecodeN() && d->in(1) == val) {
2425 val = d;
2426 val->set_req(0, NULL); // Unpin now.
2427 // Mark this as special case to distinguish from
2428 // a regular case: CmpP(DecodeN, NULL).
2429 val = (Node*)(((intptr_t)val) | 1);
2430 break;
2431 }
2432 }
2433 }
2434 #endif
2435 _null_check_tests.push(val);
2436 }
2437 }
2438 }
2439 }
2440
2441 //---------------------------validate_null_checks------------------------------
2442 // Its possible that the value being NULL checked is not the root of a match
2443 // tree. If so, I cannot use the value in an implicit null check.
2444 void Matcher::validate_null_checks( ) {
2445 uint cnt = _null_check_tests.size();
2446 for( uint i=0; i < cnt; i+=2 ) {
2447 Node *test = _null_check_tests[i];
2448 Node *val = _null_check_tests[i+1];
2449 bool is_decoden = ((intptr_t)val) & 1;
2450 val = (Node*)(((intptr_t)val) & ~1);
2451 if (has_new_node(val)) {
2452 Node* new_val = new_node(val);
2453 if (is_decoden) {
2454 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2455 // Note: new_val may have a control edge if
2456 // the original ideal node DecodeN was matched before
2457 // it was unpinned in Matcher::collect_null_checks().
2458 // Unpin the mach node and mark it.
2459 new_val->set_req(0, NULL);
2460 new_val = (Node*)(((intptr_t)new_val) | 1);
2461 }
2462 // Is a match-tree root, so replace with the matched value
2463 _null_check_tests.map(i+1, new_val);
2464 } else {
2465 // Yank from candidate list
2466 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2467 _null_check_tests.map(i,_null_check_tests[--cnt]);
2468 _null_check_tests.pop();
2469 _null_check_tests.pop();
2470 i-=2;
2471 }
2472 }
2473 }
2474
2475 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2476 // atomic instruction acting as a store_load barrier without any
2477 // intervening volatile load, and thus we don't need a barrier here.
2478 // We retain the Node to act as a compiler ordering barrier.
2479 bool Matcher::post_store_load_barrier(const Node* vmb) {
2480 Compile* C = Compile::current();
2481 assert(vmb->is_MemBar(), "");
2482 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2483 const MemBarNode* membar = vmb->as_MemBar();
2484
2485 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2486 Node* ctrl = NULL;
2487 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2488 Node* p = membar->fast_out(i);
2489 assert(p->is_Proj(), "only projections here");
2490 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2491 !C->node_arena()->contains(p)) { // Unmatched old-space only
2492 ctrl = p;
2493 break;
2494 }
2495 }
2496 assert((ctrl != NULL), "missing control projection");
2497
2498 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2499 Node *x = ctrl->fast_out(j);
2500 int xop = x->Opcode();
2501
2502 // We don't need current barrier if we see another or a lock
2503 // before seeing volatile load.
2504 //
2505 // Op_Fastunlock previously appeared in the Op_* list below.
2506 // With the advent of 1-0 lock operations we're no longer guaranteed
2507 // that a monitor exit operation contains a serializing instruction.
2508
2509 if (xop == Op_MemBarVolatile ||
2510 xop == Op_CompareAndSwapL ||
2511 xop == Op_CompareAndSwapP ||
2512 xop == Op_CompareAndSwapN ||
2513 xop == Op_CompareAndSwapI) {
2514 return true;
2515 }
2516
2517 // Op_FastLock previously appeared in the Op_* list above.
2518 // With biased locking we're no longer guaranteed that a monitor
2519 // enter operation contains a serializing instruction.
2520 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2521 return true;
2522 }
2523
2524 if (x->is_MemBar()) {
2525 // We must retain this membar if there is an upcoming volatile
2526 // load, which will be followed by acquire membar.
2527 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2528 return false;
2529 } else {
2530 // For other kinds of barriers, check by pretending we
2531 // are them, and seeing if we can be removed.
2532 return post_store_load_barrier(x->as_MemBar());
2533 }
2534 }
2535
2536 // probably not necessary to check for these
2537 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2538 return false;
2539 }
2540 }
2541 return false;
2542 }
2543
2544 // Check whether node n is a branch to an uncommon trap that we could
2545 // optimize as test with very high branch costs in case of going to
2546 // the uncommon trap. The code must be able to be recompiled to use
2547 // a cheaper test.
2548 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2549 // Don't do it for natives, adapters, or runtime stubs
2550 Compile *C = Compile::current();
2551 if (!C->is_method_compilation()) return false;
2552
2553 assert(n->is_If(), "You should only call this on if nodes.");
2554 IfNode *ifn = n->as_If();
2555
2556 Node *ifFalse = NULL;
2557 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2558 if (ifn->fast_out(i)->is_IfFalse()) {
2559 ifFalse = ifn->fast_out(i);
2560 break;
2561 }
2562 }
2563 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2564
2565 Node *reg = ifFalse;
2566 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2567 // Alternatively use visited set? Seems too expensive.
2568 while (reg != NULL && cnt > 0) {
2569 CallNode *call = NULL;
2570 RegionNode *nxt_reg = NULL;
2571 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2572 Node *o = reg->fast_out(i);
2573 if (o->is_Call()) {
2574 call = o->as_Call();
2575 }
2576 if (o->is_Region()) {
2577 nxt_reg = o->as_Region();
2578 }
2579 }
2580
2581 if (call &&
2582 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2583 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2584 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2585 jint tr_con = trtype->is_int()->get_con();
2586 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2587 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2588 assert((int)reason < (int)BitsPerInt, "recode bit map");
2589
2590 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2591 && action != Deoptimization::Action_none) {
2592 // This uncommon trap is sure to recompile, eventually.
2593 // When that happens, C->too_many_traps will prevent
2594 // this transformation from happening again.
2595 return true;
2596 }
2597 }
2598 }
2599
2600 reg = nxt_reg;
2601 cnt--;
2602 }
2603
2604 return false;
2605 }
2606
2607 //=============================================================================
2608 //---------------------------State---------------------------------------------
2609 State::State(void) {
2610 #ifdef ASSERT
2611 _id = 0;
2612 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2613 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2614 //memset(_cost, -1, sizeof(_cost));
2615 //memset(_rule, -1, sizeof(_rule));
2616 #endif
2617 memset(_valid, 0, sizeof(_valid));
2618 }
2619
2620 #ifdef ASSERT
2621 State::~State() {
2622 _id = 99;
2623 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2624 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2625 memset(_cost, -3, sizeof(_cost));
2626 memset(_rule, -3, sizeof(_rule));
2627 }
2628 #endif
2629
2630 #ifndef PRODUCT
2631 //---------------------------dump----------------------------------------------
2632 void State::dump() {
2633 tty->print("\n");
2634 dump(0);
2635 }
2636
2637 void State::dump(int depth) {
2638 for( int j = 0; j < depth; j++ )
2639 tty->print(" ");
2640 tty->print("--N: ");
2641 _leaf->dump();
2642 uint i;
2643 for( i = 0; i < _LAST_MACH_OPER; i++ )
2644 // Check for valid entry
2645 if( valid(i) ) {
2646 for( int j = 0; j < depth; j++ )
2647 tty->print(" ");
2648 assert(_cost[i] != max_juint, "cost must be a valid value");
2649 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2650 tty->print_cr("%s %d %s",
2651 ruleName[i], _cost[i], ruleName[_rule[i]] );
2652 }
2653 tty->cr();
2654
2655 for( i=0; i<2; i++ )
2656 if( _kids[i] )
2657 _kids[i]->dump(depth+1);
2658 }
2659 #endif