1 /*
2 * Copyright (c) 2013, Red Hat Inc.
3 * Copyright (c) 1997, 2012, Oracle and/or its affiliates.
4 * All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
29
30 #include "asm/assembler.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 public:
41 using Assembler::mov;
42 using Assembler::movi;
43
44 protected:
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 #ifdef CC_INTERP
52 // c++ interpreter never wants to use interp_masm version of call_VM
53 #define VIRTUAL
54 #else
55 #define VIRTUAL virtual
56 #endif
57
58 VIRTUAL void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments, // the number of arguments to pop after the call
61 Label *retaddr = NULL
62 );
63
64 VIRTUAL void call_VM_leaf_base(
65 address entry_point, // the entry point
66 int number_of_arguments, // the number of arguments to pop after the call
67 Label &retaddr) {
68 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
69 }
70
71 // This is the base routine called by the different versions of call_VM. The interpreter
72 // may customize this version by overriding it for its purposes (e.g., to save/restore
73 // additional registers when doing a VM call).
74 //
75 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
76 // returns the register which contains the thread upon return. If a thread register has been
77 // specified, the return value will correspond to that register. If no last_java_sp is specified
78 // (noreg) than rsp will be used instead.
79 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
80 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
81 Register java_thread, // the thread if computed before ; use noreg otherwise
82 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
83 address entry_point, // the entry point
84 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
85 bool check_exceptions // whether to check for pending exceptions after return
86 );
87
88 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
89 // The implementation is only non-empty for the InterpreterMacroAssembler,
90 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
91 virtual void check_and_handle_popframe(Register java_thread);
92 virtual void check_and_handle_earlyret(Register java_thread);
93
94 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
95
96 // Maximum size of class area in Metaspace when compressed
97 uint64_t use_XOR_for_compressed_class_base;
98
99 public:
100 MacroAssembler(CodeBuffer* code) : Assembler(code) {
101 use_XOR_for_compressed_class_base
102 = (operand_valid_for_logical_immediate(false /*is32*/,
103 (uint64_t)Universe::narrow_klass_base())
104 && ((uint64_t)Universe::narrow_klass_base()
105 > (1u << log2_intptr(CompressedClassSpaceSize))));
106 }
107
108 // Biased locking support
109 // lock_reg and obj_reg must be loaded up with the appropriate values.
110 // swap_reg is killed.
111 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
112 // Optional slow case is for implementations (interpreter and C1) which branch to
113 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
114 // Returns offset of first potentially-faulting instruction for null
115 // check info (currently consumed only by C1). If
116 // swap_reg_contains_mark is true then returns -1 as it is assumed
117 // the calling code has already passed any potential faults.
118 int biased_locking_enter(Register lock_reg, Register obj_reg,
119 Register swap_reg, Register tmp_reg,
120 bool swap_reg_contains_mark,
121 Label& done, Label* slow_case = NULL,
122 BiasedLockingCounters* counters = NULL);
123 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
124
125
126 // Helper functions for statistics gathering.
127 // Unconditional atomic increment.
128 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
129 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
130 lea(tmp1, counter_addr);
131 atomic_incw(tmp1, tmp2, tmp3);
132 }
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 code_section()->relocate(inst_mark(), a.rspec());
137 a.lea(this, r);
138 }
139
140 void addmw(Address a, Register incr, Register scratch) {
141 ldrw(scratch, a);
142 addw(scratch, scratch, incr);
143 strw(scratch, a);
144 }
145
146 // Add constant to memory word
147 void addmw(Address a, int imm, Register scratch) {
148 ldrw(scratch, a);
149 if (imm > 0)
150 addw(scratch, scratch, (unsigned)imm);
151 else
152 subw(scratch, scratch, (unsigned)-imm);
153 strw(scratch, a);
154 }
155
156 // Frame creation and destruction shared between JITs.
157 void build_frame(int framesize);
158 void remove_frame(int framesize);
159
160 virtual void _call_Unimplemented(address call_site) {
161 mov(rscratch2, call_site);
162 haltsim();
163 }
164
165 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
166
167 virtual void notify(int type);
168
169 // aliases defined in AARCH64 spec
170
171 template<class T>
172 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
173 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
174
175 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
176 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
177
178 void cset(Register Rd, Assembler::Condition cond) {
179 csinc(Rd, zr, zr, ~cond);
180 }
181 void csetw(Register Rd, Assembler::Condition cond) {
182 csincw(Rd, zr, zr, ~cond);
183 }
184
185 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
186 csneg(Rd, Rn, Rn, ~cond);
187 }
188 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
189 csnegw(Rd, Rn, Rn, ~cond);
190 }
191
192 inline void movw(Register Rd, Register Rn) {
193 if (Rd == sp || Rn == sp) {
194 addw(Rd, Rn, 0U);
195 } else {
196 orrw(Rd, zr, Rn);
197 }
198 }
199 inline void mov(Register Rd, Register Rn) {
200 assert(Rd != r31_sp && Rn != r31_sp, "should be");
201 if (Rd == Rn) {
202 } else if (Rd == sp || Rn == sp) {
203 add(Rd, Rn, 0U);
204 } else {
205 orr(Rd, zr, Rn);
206 }
207 }
208
209 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
210 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
211
212 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
213 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
214
215 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
216 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
217
218 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
219 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
220 }
221 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
222 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
223 }
224
225 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
226 bfmw(Rd, Rn, lsb, (lsb + width - 1));
227 }
228 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 bfm(Rd, Rn, lsb , (lsb + width - 1));
230 }
231
232 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
233 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
234 }
235 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
237 }
238
239 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
240 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
241 }
242 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 sbfm(Rd, Rn, lsb , (lsb + width - 1));
244 }
245
246 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
247 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
248 }
249 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
251 }
252
253 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
254 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
255 }
256 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
257 ubfm(Rd, Rn, lsb , (lsb + width - 1));
258 }
259
260 inline void asrw(Register Rd, Register Rn, unsigned imm) {
261 sbfmw(Rd, Rn, imm, 31);
262 }
263
264 inline void asr(Register Rd, Register Rn, unsigned imm) {
265 sbfm(Rd, Rn, imm, 63);
266 }
267
268 inline void lslw(Register Rd, Register Rn, unsigned imm) {
269 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
270 }
271
272 inline void lsl(Register Rd, Register Rn, unsigned imm) {
273 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
274 }
275
276 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
277 ubfmw(Rd, Rn, imm, 31);
278 }
279
280 inline void lsr(Register Rd, Register Rn, unsigned imm) {
281 ubfm(Rd, Rn, imm, 63);
282 }
283
284 inline void rorw(Register Rd, Register Rn, unsigned imm) {
285 extrw(Rd, Rn, Rn, imm);
286 }
287
288 inline void ror(Register Rd, Register Rn, unsigned imm) {
289 extr(Rd, Rn, Rn, imm);
290 }
291
292 inline void sxtbw(Register Rd, Register Rn) {
293 sbfmw(Rd, Rn, 0, 7);
294 }
295 inline void sxthw(Register Rd, Register Rn) {
296 sbfmw(Rd, Rn, 0, 15);
297 }
298 inline void sxtb(Register Rd, Register Rn) {
299 sbfm(Rd, Rn, 0, 7);
300 }
301 inline void sxth(Register Rd, Register Rn) {
302 sbfm(Rd, Rn, 0, 15);
303 }
304 inline void sxtw(Register Rd, Register Rn) {
305 sbfm(Rd, Rn, 0, 31);
306 }
307
308 inline void uxtbw(Register Rd, Register Rn) {
309 ubfmw(Rd, Rn, 0, 7);
310 }
311 inline void uxthw(Register Rd, Register Rn) {
312 ubfmw(Rd, Rn, 0, 15);
313 }
314 inline void uxtb(Register Rd, Register Rn) {
315 ubfm(Rd, Rn, 0, 7);
316 }
317 inline void uxth(Register Rd, Register Rn) {
318 ubfm(Rd, Rn, 0, 15);
319 }
320 inline void uxtw(Register Rd, Register Rn) {
321 ubfm(Rd, Rn, 0, 31);
322 }
323
324 inline void cmnw(Register Rn, Register Rm) {
325 addsw(zr, Rn, Rm);
326 }
327 inline void cmn(Register Rn, Register Rm) {
328 adds(zr, Rn, Rm);
329 }
330
331 inline void cmpw(Register Rn, Register Rm) {
332 subsw(zr, Rn, Rm);
333 }
334 inline void cmp(Register Rn, Register Rm) {
335 subs(zr, Rn, Rm);
336 }
337
338 inline void negw(Register Rd, Register Rn) {
339 subw(Rd, zr, Rn);
340 }
341
342 inline void neg(Register Rd, Register Rn) {
343 sub(Rd, zr, Rn);
344 }
345
346 inline void negsw(Register Rd, Register Rn) {
347 subsw(Rd, zr, Rn);
348 }
349
350 inline void negs(Register Rd, Register Rn) {
351 subs(Rd, zr, Rn);
352 }
353
354 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
355 addsw(zr, Rn, Rm, kind, shift);
356 }
357 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
358 adds(zr, Rn, Rm, kind, shift);
359 }
360
361 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
362 subsw(zr, Rn, Rm, kind, shift);
363 }
364 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
365 subs(zr, Rn, Rm, kind, shift);
366 }
367
368 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
369 subw(Rd, zr, Rn, kind, shift);
370 }
371
372 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
373 sub(Rd, zr, Rn, kind, shift);
374 }
375
376 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
377 subsw(Rd, zr, Rn, kind, shift);
378 }
379
380 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
381 subs(Rd, zr, Rn, kind, shift);
382 }
383
384 inline void mnegw(Register Rd, Register Rn, Register Rm) {
385 msubw(Rd, Rn, Rm, zr);
386 }
387 inline void mneg(Register Rd, Register Rn, Register Rm) {
388 msub(Rd, Rn, Rm, zr);
389 }
390
391 inline void mulw(Register Rd, Register Rn, Register Rm) {
392 maddw(Rd, Rn, Rm, zr);
393 }
394 inline void mul(Register Rd, Register Rn, Register Rm) {
395 madd(Rd, Rn, Rm, zr);
396 }
397
398 inline void smnegl(Register Rd, Register Rn, Register Rm) {
399 smsubl(Rd, Rn, Rm, zr);
400 }
401 inline void smull(Register Rd, Register Rn, Register Rm) {
402 smaddl(Rd, Rn, Rm, zr);
403 }
404
405 inline void umnegl(Register Rd, Register Rn, Register Rm) {
406 umsubl(Rd, Rn, Rm, zr);
407 }
408 inline void umull(Register Rd, Register Rn, Register Rm) {
409 umaddl(Rd, Rn, Rm, zr);
410 }
411
412 #define WRAP(INSN) \
413 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
414 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
415 nop(); \
416 Assembler::INSN(Rd, Rn, Rm, Ra); \
417 }
418
419 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
420 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
421 #undef WRAP
422
423 // macro assembly operations needed for aarch64
424
425 // first two private routines for loading 32 bit or 64 bit constants
426 private:
427
428 void mov_immediate64(Register dst, u_int64_t imm64);
429 void mov_immediate32(Register dst, u_int32_t imm32);
430
431 int push(unsigned int bitset, Register stack);
432 int pop(unsigned int bitset, Register stack);
433
434 void mov(Register dst, Address a);
435
436 public:
437 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
438 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
439
440 // Push and pop everything that might be clobbered by a native
441 // runtime call except rscratch1 and rscratch2. (They are always
442 // scratch, so we don't have to protect them.) Only save the lower
443 // 64 bits of each vector register.
444 void push_call_clobbered_registers();
445 void pop_call_clobbered_registers();
446 void push_call_clobbered_fp_registers();
447 void pop_call_clobbered_fp_registers();
448
449 // now mov instructions for loading absolute addresses and 32 or
450 // 64 bit integers
451
452 void mov(Register dst, address addr);
453
454 inline void mov(Register dst, u_int64_t imm64)
455 {
456 mov_immediate64(dst, imm64);
457 }
458
459 inline void movw(Register dst, u_int32_t imm32)
460 {
461 mov_immediate32(dst, imm32);
462 }
463
464 inline void mov(Register dst, long l)
465 {
466 mov(dst, (u_int64_t)l);
467 }
468
469 inline void mov(Register dst, int i)
470 {
471 mov(dst, (long)i);
472 }
473
474 void mov(Register dst, RegisterOrConstant src) {
475 if (src.is_register())
476 mov(dst, src.as_register());
477 else
478 mov(dst, src.as_constant());
479 }
480
481 void movptr(Register r, uintptr_t imm64);
482
483 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
484
485 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
486 orr(Vd, T, Vn, Vn);
487 }
488
489 public:
490
491 // Generalized Test Bit And Branch, including a "far" variety which
492 // spans more than 32KiB.
493 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
494 assert(cond == EQ || cond == NE, "must be");
495
496 if (far)
497 cond = ~cond;
498
499 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
500 if (cond == Assembler::EQ)
501 branch = &Assembler::tbz;
502 else
503 branch = &Assembler::tbnz;
504
505 if (far) {
506 Label L;
507 (this->*branch)(Rt, bitpos, L);
508 b(dest);
509 bind(L);
510 } else {
511 (this->*branch)(Rt, bitpos, dest);
512 }
513 }
514
515 // macro instructions for accessing and updating floating point
516 // status register
517 //
518 // FPSR : op1 == 011
519 // CRn == 0100
520 // CRm == 0100
521 // op2 == 001
522
523 inline void get_fpsr(Register reg)
524 {
525 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
526 }
527
528 inline void set_fpsr(Register reg)
529 {
530 msr(0b011, 0b0100, 0b0100, 0b001, reg);
531 }
532
533 inline void clear_fpsr()
534 {
535 msr(0b011, 0b0100, 0b0100, 0b001, zr);
536 }
537
538 // Macro instructions for accessing and updating the condition flags
539 inline void get_nzcv(Register reg)
540 {
541 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
542 }
543
544 inline void set_nzcv(Register reg)
545 {
546 msr(0b011, 0b0100, 0b0010, 0b000, reg);
547 }
548
549 // DCZID_EL0: op1 == 011
550 // CRn == 0000
551 // CRm == 0000
552 // op2 == 111
553 inline void get_dczid_el0(Register reg)
554 {
555 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
556 }
557
558 // CTR_EL0: op1 == 011
559 // CRn == 0000
560 // CRm == 0000
561 // op2 == 001
562 inline void get_ctr_el0(Register reg)
563 {
564 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
565 }
566
567 // idiv variant which deals with MINLONG as dividend and -1 as divisor
568 int corrected_idivl(Register result, Register ra, Register rb,
569 bool want_remainder, Register tmp = rscratch1);
570 int corrected_idivq(Register result, Register ra, Register rb,
571 bool want_remainder, Register tmp = rscratch1);
572
573 // Support for NULL-checks
574 //
575 // Generates code that causes a NULL OS exception if the content of reg is NULL.
576 // If the accessed location is M[reg + offset] and the offset is known, provide the
577 // offset. No explicit code generation is needed if the offset is within a certain
578 // range (0 <= offset <= page_size).
579
580 virtual void null_check(Register reg, int offset = -1);
581 static bool needs_explicit_null_check(intptr_t offset);
582
583 static address target_addr_for_insn(address insn_addr, unsigned insn);
584 static address target_addr_for_insn(address insn_addr) {
585 unsigned insn = *(unsigned*)insn_addr;
586 return target_addr_for_insn(insn_addr, insn);
587 }
588
589 // Required platform-specific helpers for Label::patch_instructions.
590 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
591 static int pd_patch_instruction_size(address branch, address target);
592 static void pd_patch_instruction(address branch, address target) {
593 pd_patch_instruction_size(branch, target);
594 }
595 static address pd_call_destination(address branch) {
596 return target_addr_for_insn(branch);
597 }
598 #ifndef PRODUCT
599 static void pd_print_patched_instruction(address branch);
600 #endif
601
602 static int patch_oop(address insn_addr, address o);
603
604 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
605
606 // The following 4 methods return the offset of the appropriate move instruction
607
608 // Support for fast byte/short loading with zero extension (depending on particular CPU)
609 int load_unsigned_byte(Register dst, Address src);
610 int load_unsigned_short(Register dst, Address src);
611
612 // Support for fast byte/short loading with sign extension (depending on particular CPU)
613 int load_signed_byte(Register dst, Address src);
614 int load_signed_short(Register dst, Address src);
615
616 int load_signed_byte32(Register dst, Address src);
617 int load_signed_short32(Register dst, Address src);
618
619 // Support for sign-extension (hi:lo = extend_sign(lo))
620 void extend_sign(Register hi, Register lo);
621
622 // Load and store values by size and signed-ness
623 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
624 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
625
626 // Support for inc/dec with optimal instruction selection depending on value
627
628 // x86_64 aliases an unqualified register/address increment and
629 // decrement to call incrementq and decrementq but also supports
630 // explicitly sized calls to incrementq/decrementq or
631 // incrementl/decrementl
632
633 // for aarch64 the proper convention would be to use
634 // increment/decrement for 64 bit operatons and
635 // incrementw/decrementw for 32 bit operations. so when porting
636 // x86_64 code we can leave calls to increment/decrement as is,
637 // replace incrementq/decrementq with increment/decrement and
638 // replace incrementl/decrementl with incrementw/decrementw.
639
640 // n.b. increment/decrement calls with an Address destination will
641 // need to use a scratch register to load the value to be
642 // incremented. increment/decrement calls which add or subtract a
643 // constant value greater than 2^12 will need to use a 2nd scratch
644 // register to hold the constant. so, a register increment/decrement
645 // may trash rscratch2 and an address increment/decrement trash
646 // rscratch and rscratch2
647
648 void decrementw(Address dst, int value = 1);
649 void decrementw(Register reg, int value = 1);
650
651 void decrement(Register reg, int value = 1);
652 void decrement(Address dst, int value = 1);
653
654 void incrementw(Address dst, int value = 1);
655 void incrementw(Register reg, int value = 1);
656
657 void increment(Register reg, int value = 1);
658 void increment(Address dst, int value = 1);
659
660
661 // Alignment
662 void align(int modulus);
663
664 // Stack frame creation/removal
665 void enter()
666 {
667 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
668 mov(rfp, sp);
669 }
670 void leave()
671 {
672 mov(sp, rfp);
673 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
674 }
675
676 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
677 // The pointer will be loaded into the thread register.
678 void get_thread(Register thread);
679
680
681 // Support for VM calls
682 //
683 // It is imperative that all calls into the VM are handled via the call_VM macros.
684 // They make sure that the stack linkage is setup correctly. call_VM's correspond
685 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
686
687
688 void call_VM(Register oop_result,
689 address entry_point,
690 bool check_exceptions = true);
691 void call_VM(Register oop_result,
692 address entry_point,
693 Register arg_1,
694 bool check_exceptions = true);
695 void call_VM(Register oop_result,
696 address entry_point,
697 Register arg_1, Register arg_2,
698 bool check_exceptions = true);
699 void call_VM(Register oop_result,
700 address entry_point,
701 Register arg_1, Register arg_2, Register arg_3,
702 bool check_exceptions = true);
703
704 // Overloadings with last_Java_sp
705 void call_VM(Register oop_result,
706 Register last_java_sp,
707 address entry_point,
708 int number_of_arguments = 0,
709 bool check_exceptions = true);
710 void call_VM(Register oop_result,
711 Register last_java_sp,
712 address entry_point,
713 Register arg_1, bool
714 check_exceptions = true);
715 void call_VM(Register oop_result,
716 Register last_java_sp,
717 address entry_point,
718 Register arg_1, Register arg_2,
719 bool check_exceptions = true);
720 void call_VM(Register oop_result,
721 Register last_java_sp,
722 address entry_point,
723 Register arg_1, Register arg_2, Register arg_3,
724 bool check_exceptions = true);
725
726 void get_vm_result (Register oop_result, Register thread);
727 void get_vm_result_2(Register metadata_result, Register thread);
728
729 // These always tightly bind to MacroAssembler::call_VM_base
730 // bypassing the virtual implementation
731 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
732 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
733 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
734 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
735 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
736
737 void call_VM_leaf(address entry_point,
738 int number_of_arguments = 0);
739 void call_VM_leaf(address entry_point,
740 Register arg_1);
741 void call_VM_leaf(address entry_point,
742 Register arg_1, Register arg_2);
743 void call_VM_leaf(address entry_point,
744 Register arg_1, Register arg_2, Register arg_3);
745
746 // These always tightly bind to MacroAssembler::call_VM_leaf_base
747 // bypassing the virtual implementation
748 void super_call_VM_leaf(address entry_point);
749 void super_call_VM_leaf(address entry_point, Register arg_1);
750 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
751 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
752 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
753
754 // last Java Frame (fills frame anchor)
755 void set_last_Java_frame(Register last_java_sp,
756 Register last_java_fp,
757 address last_java_pc,
758 Register scratch);
759
760 void set_last_Java_frame(Register last_java_sp,
761 Register last_java_fp,
762 Label &last_java_pc,
763 Register scratch);
764
765 void set_last_Java_frame(Register last_java_sp,
766 Register last_java_fp,
767 Register last_java_pc,
768 Register scratch);
769
770 void reset_last_Java_frame(Register thread);
771
772 // thread in the default location (rthread)
773 void reset_last_Java_frame(bool clear_fp);
774
775 // Stores
776 void store_check(Register obj); // store check for obj - register is destroyed afterwards
777 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
778
779 #if INCLUDE_ALL_GCS
780
781 void g1_write_barrier_pre(Register obj,
782 Register pre_val,
783 Register thread,
784 Register tmp,
785 bool tosca_live,
786 bool expand_call);
787
788 void g1_write_barrier_post(Register store_addr,
789 Register new_val,
790 Register thread,
791 Register tmp,
792 Register tmp2);
793
794 void shenandoah_write_barrier(Register dst);
795
796 #endif // INCLUDE_ALL_GCS
797
798 // split store_check(Register obj) to enhance instruction interleaving
799 void store_check_part_1(Register obj);
800 void store_check_part_2(Register obj);
801
802 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
803 void c2bool(Register x);
804
805 // oop manipulations
806 void load_klass(Register dst, Register src);
807 void store_klass(Register dst, Register src);
808 void cmp_klass(Register oop, Register trial_klass, Register tmp);
809
810 void load_heap_oop(Register dst, Address src);
811
812 void load_heap_oop_not_null(Register dst, Address src);
813 void store_heap_oop(Address dst, Register src);
814
815 // currently unimplemented
816 // Used for storing NULL. All other oop constants should be
817 // stored using routines that take a jobject.
818 void store_heap_oop_null(Address dst);
819
820 void load_prototype_header(Register dst, Register src);
821
822 void store_klass_gap(Register dst, Register src);
823
824 // This dummy is to prevent a call to store_heap_oop from
825 // converting a zero (like NULL) into a Register by giving
826 // the compiler two choices it can't resolve
827
828 void store_heap_oop(Address dst, void* dummy);
829
830 void encode_heap_oop(Register d, Register s);
831 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
832 void decode_heap_oop(Register d, Register s);
833 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
834 void encode_heap_oop_not_null(Register r);
835 void decode_heap_oop_not_null(Register r);
836 void encode_heap_oop_not_null(Register dst, Register src);
837 void decode_heap_oop_not_null(Register dst, Register src);
838
839 void set_narrow_oop(Register dst, jobject obj);
840
841 void encode_klass_not_null(Register r);
842 void decode_klass_not_null(Register r);
843 void encode_klass_not_null(Register dst, Register src);
844 void decode_klass_not_null(Register dst, Register src);
845
846 void set_narrow_klass(Register dst, Klass* k);
847
848 // if heap base register is used - reinit it with the correct value
849 void reinit_heapbase();
850
851 DEBUG_ONLY(void verify_heapbase(const char* msg);)
852
853 void push_CPU_state(bool save_vectors = false);
854 void pop_CPU_state(bool restore_vectors = false) ;
855
856 // Round up to a power of two
857 void round_to(Register reg, int modulus);
858
859 // allocation
860 void eden_allocate(
861 Register obj, // result: pointer to object after successful allocation
862 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
863 int con_size_in_bytes, // object size in bytes if known at compile time
864 Register t1, // temp register
865 Label& slow_case // continuation point if fast allocation fails
866 );
867 void tlab_allocate(
868 Register obj, // result: pointer to object after successful allocation
869 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
870 int con_size_in_bytes, // object size in bytes if known at compile time
871 Register t1, // temp register
872 Register t2, // temp register
873 Label& slow_case // continuation point if fast allocation fails
874 );
875 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
876 void verify_tlab();
877
878 void incr_allocated_bytes(Register thread,
879 Register var_size_in_bytes, int con_size_in_bytes,
880 Register t1 = noreg);
881
882 // interface method calling
883 void lookup_interface_method(Register recv_klass,
884 Register intf_klass,
885 RegisterOrConstant itable_index,
886 Register method_result,
887 Register scan_temp,
888 Label& no_such_interface,
889 bool return_method = true);
890
891 // virtual method calling
892 // n.b. x86 allows RegisterOrConstant for vtable_index
893 void lookup_virtual_method(Register recv_klass,
894 RegisterOrConstant vtable_index,
895 Register method_result);
896
897 // Test sub_klass against super_klass, with fast and slow paths.
898
899 // The fast path produces a tri-state answer: yes / no / maybe-slow.
900 // One of the three labels can be NULL, meaning take the fall-through.
901 // If super_check_offset is -1, the value is loaded up from super_klass.
902 // No registers are killed, except temp_reg.
903 void check_klass_subtype_fast_path(Register sub_klass,
904 Register super_klass,
905 Register temp_reg,
906 Label* L_success,
907 Label* L_failure,
908 Label* L_slow_path,
909 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
910
911 // The rest of the type check; must be wired to a corresponding fast path.
912 // It does not repeat the fast path logic, so don't use it standalone.
913 // The temp_reg and temp2_reg can be noreg, if no temps are available.
914 // Updates the sub's secondary super cache as necessary.
915 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
916 void check_klass_subtype_slow_path(Register sub_klass,
917 Register super_klass,
918 Register temp_reg,
919 Register temp2_reg,
920 Label* L_success,
921 Label* L_failure,
922 bool set_cond_codes = false);
923
924 // Simplified, combined version, good for typical uses.
925 // Falls through on failure.
926 void check_klass_subtype(Register sub_klass,
927 Register super_klass,
928 Register temp_reg,
929 Label& L_success);
930
931 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
932
933
934 // Debugging
935
936 // only if +VerifyOops
937 void verify_oop(Register reg, const char* s = "broken oop");
938 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
939
940 // TODO: verify method and klass metadata (compare against vptr?)
941 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
942 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
943
944 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
945 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
946
947 // only if +VerifyFPU
948 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
949
950 // prints msg, dumps registers and stops execution
951 void stop(const char* msg, Label *l = NULL);
952
953 // prints msg and continues
954 void warn(const char* msg);
955
956 static void debug64(char* msg, int64_t pc, int64_t regs[]);
957
958 void untested() { stop("untested"); }
959
960 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
961
962 void should_not_reach_here() { stop("should not reach here"); }
963
964 // Stack overflow checking
965 void bang_stack_with_offset(int offset) {
966 // stack grows down, caller passes positive offset
967 assert(offset > 0, "must bang with negative offset");
968 mov(rscratch2, -offset);
969 str(zr, Address(sp, rscratch2));
970 }
971
972 // Writes to stack successive pages until offset reached to check for
973 // stack overflow + shadow pages. Also, clobbers tmp
974 void bang_stack_size(Register size, Register tmp);
975
976 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
977 Register tmp,
978 int offset);
979
980 // Support for serializing memory accesses between threads
981 void serialize_memory(Register thread, Register tmp);
982
983 // Arithmetics
984
985 void addptr(const Address &dst, int32_t src);
986 void cmpptr(Register src1, Address src2);
987
988 void cmpoops(Register src1, Register src2);
989
990 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
991 Label &suceed, Label *fail);
992
993 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
994 Label &suceed, Label *fail);
995
996 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
997 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
998
999 void atomic_xchg(Register prev, Register newv, Register addr);
1000 void atomic_xchgw(Register prev, Register newv, Register addr);
1001
1002 void orptr(Address adr, RegisterOrConstant src) {
1003 ldr(rscratch2, adr);
1004 if (src.is_register())
1005 orr(rscratch2, rscratch2, src.as_register());
1006 else
1007 orr(rscratch2, rscratch2, src.as_constant());
1008 str(rscratch2, adr);
1009 }
1010
1011 // A generic CAS; success or failure is in the EQ flag.
1012 void cmpxchg(Register addr, Register expected, Register new_val,
1013 enum operand_size size,
1014 bool acquire, bool release,
1015 Register tmp = rscratch1);
1016
1017 void cmpxchg_oop_shenandoah(Register addr, Register expected, Register new_val,
1018 enum operand_size size,
1019 bool acquire, bool release, bool weak,
1020 Register result = noreg, Register tmp2 = rscratch2);
1021 // Calls
1022
1023 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1024
1025 static bool far_branches() {
1026 return ReservedCodeCacheSize > branch_range;
1027 }
1028
1029 // Jumps that can reach anywhere in the code cache.
1030 // Trashes tmp.
1031 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1032 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1033
1034 static int far_branch_size() {
1035 if (far_branches()) {
1036 return 3 * 4; // adrp, add, br
1037 } else {
1038 return 4;
1039 }
1040 }
1041
1042 // Emit the CompiledIC call idiom
1043 address ic_call(address entry);
1044
1045 public:
1046
1047 // Data
1048
1049 void mov_metadata(Register dst, Metadata* obj);
1050 Address allocate_metadata_address(Metadata* obj);
1051 Address constant_oop_address(jobject obj);
1052
1053 void movoop(Register dst, jobject obj, bool immediate = false);
1054
1055 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1056 void kernel_crc32(Register crc, Register buf, Register len,
1057 Register table0, Register table1, Register table2, Register table3,
1058 Register tmp, Register tmp2, Register tmp3);
1059
1060 #undef VIRTUAL
1061
1062 // Stack push and pop individual 64 bit registers
1063 void push(Register src);
1064 void pop(Register dst);
1065
1066 // push all registers onto the stack
1067 void pusha();
1068 void popa();
1069
1070 void repne_scan(Register addr, Register value, Register count,
1071 Register scratch);
1072 void repne_scanw(Register addr, Register value, Register count,
1073 Register scratch);
1074
1075 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1076 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1077
1078 // If a constant does not fit in an immediate field, generate some
1079 // number of MOV instructions and then perform the operation
1080 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1081 add_sub_imm_insn insn1,
1082 add_sub_reg_insn insn2);
1083 // Seperate vsn which sets the flags
1084 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1085 add_sub_imm_insn insn1,
1086 add_sub_reg_insn insn2);
1087
1088 #define WRAP(INSN) \
1089 void INSN(Register Rd, Register Rn, unsigned imm) { \
1090 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1091 } \
1092 \
1093 void INSN(Register Rd, Register Rn, Register Rm, \
1094 enum shift_kind kind, unsigned shift = 0) { \
1095 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1096 } \
1097 \
1098 void INSN(Register Rd, Register Rn, Register Rm) { \
1099 Assembler::INSN(Rd, Rn, Rm); \
1100 } \
1101 \
1102 void INSN(Register Rd, Register Rn, Register Rm, \
1103 ext::operation option, int amount = 0) { \
1104 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1105 }
1106
1107 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1108
1109 #undef WRAP
1110 #define WRAP(INSN) \
1111 void INSN(Register Rd, Register Rn, unsigned imm) { \
1112 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1113 } \
1114 \
1115 void INSN(Register Rd, Register Rn, Register Rm, \
1116 enum shift_kind kind, unsigned shift = 0) { \
1117 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1118 } \
1119 \
1120 void INSN(Register Rd, Register Rn, Register Rm) { \
1121 Assembler::INSN(Rd, Rn, Rm); \
1122 } \
1123 \
1124 void INSN(Register Rd, Register Rn, Register Rm, \
1125 ext::operation option, int amount = 0) { \
1126 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1127 }
1128
1129 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1130
1131 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1132 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1133 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1134 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1135
1136 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1137
1138 void tableswitch(Register index, jint lowbound, jint highbound,
1139 Label &jumptable, Label &jumptable_end, int stride = 1) {
1140 adr(rscratch1, jumptable);
1141 subsw(rscratch2, index, lowbound);
1142 subsw(zr, rscratch2, highbound - lowbound);
1143 br(Assembler::HS, jumptable_end);
1144 add(rscratch1, rscratch1, rscratch2,
1145 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1146 br(rscratch1);
1147 }
1148
1149 // Form an address from base + offset in Rd. Rd may or may not
1150 // actually be used: you must use the Address that is returned. It
1151 // is up to you to ensure that the shift provided matches the size
1152 // of your data.
1153 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1154
1155 // Return true iff an address is within the 48-bit AArch64 address
1156 // space.
1157 bool is_valid_AArch64_address(address a) {
1158 return ((uint64_t)a >> 48) == 0;
1159 }
1160
1161 // Load the base of the cardtable byte map into reg.
1162 void load_byte_map_base(Register reg);
1163
1164 // Prolog generator routines to support switch between x86 code and
1165 // generated ARM code
1166
1167 // routine to generate an x86 prolog for a stub function which
1168 // bootstraps into the generated ARM code which directly follows the
1169 // stub
1170 //
1171
1172 public:
1173 // enum used for aarch64--x86 linkage to define return type of x86 function
1174 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1175
1176 #ifdef BUILTIN_SIM
1177 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1178 #else
1179 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1180 #endif
1181
1182 // special version of call_VM_leaf_base needed for aarch64 simulator
1183 // where we need to specify both the gp and fp arg counts and the
1184 // return type so that the linkage routine from aarch64 to x86 and
1185 // back knows which aarch64 registers to copy to x86 registers and
1186 // which x86 result register to copy back to an aarch64 register
1187
1188 void call_VM_leaf_base1(
1189 address entry_point, // the entry point
1190 int number_of_gp_arguments, // the number of gp reg arguments to pass
1191 int number_of_fp_arguments, // the number of fp reg arguments to pass
1192 ret_type type, // the return type for the call
1193 Label* retaddr = NULL
1194 );
1195
1196 void ldr_constant(Register dest, const Address &const_addr) {
1197 if (NearCpool) {
1198 ldr(dest, const_addr);
1199 } else {
1200 unsigned long offset;
1201 adrp(dest, InternalAddress(const_addr.target()), offset);
1202 ldr(dest, Address(dest, offset));
1203 }
1204 }
1205
1206 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1207 address read_polling_page(Register r, relocInfo::relocType rtype);
1208
1209 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1210 void update_byte_crc32(Register crc, Register val, Register table);
1211 void update_word_crc32(Register crc, Register v, Register tmp,
1212 Register table0, Register table1, Register table2, Register table3,
1213 bool upper = false);
1214
1215 void string_compare(Register str1, Register str2,
1216 Register cnt1, Register cnt2, Register result,
1217 Register tmp1);
1218 void string_equals(Register str1, Register str2,
1219 Register cnt, Register result,
1220 Register tmp1);
1221 void char_arrays_equals(Register ary1, Register ary2,
1222 Register result, Register tmp1);
1223 void fill_words(Register base, Register cnt, Register value);
1224 void zero_words(Register base, u_int64_t cnt);
1225 void zero_words(Register base, Register cnt);
1226 void block_zero(Register base, Register cnt, bool is_large = false);
1227
1228 void encode_iso_array(Register src, Register dst,
1229 Register len, Register result,
1230 FloatRegister Vtmp1, FloatRegister Vtmp2,
1231 FloatRegister Vtmp3, FloatRegister Vtmp4);
1232 void string_indexof(Register str1, Register str2,
1233 Register cnt1, Register cnt2,
1234 Register tmp1, Register tmp2,
1235 Register tmp3, Register tmp4,
1236 int int_cnt1, Register result);
1237 private:
1238 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1239 Register src1, Register src2);
1240 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1241 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1242 }
1243 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1244 Register y, Register y_idx, Register z,
1245 Register carry, Register product,
1246 Register idx, Register kdx);
1247 void multiply_128_x_128_loop(Register y, Register z,
1248 Register carry, Register carry2,
1249 Register idx, Register jdx,
1250 Register yz_idx1, Register yz_idx2,
1251 Register tmp, Register tmp3, Register tmp4,
1252 Register tmp7, Register product_hi);
1253 public:
1254 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1255 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1256 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1257 // ISB may be needed because of a safepoint
1258 void maybe_isb() { isb(); }
1259
1260 private:
1261 // Return the effective address r + (r1 << ext) + offset.
1262 // Uses rscratch2.
1263 Address offsetted_address(Register r, Register r1, Address::extend ext,
1264 int offset, int size);
1265
1266 private:
1267 // Returns an address on the stack which is reachable with a ldr/str of size
1268 // Uses rscratch2 if the address is not directly reachable
1269 Address spill_address(int size, int offset, Register tmp=rscratch2);
1270
1271 public:
1272 void spill(Register Rx, bool is64, int offset) {
1273 if (is64) {
1274 str(Rx, spill_address(8, offset));
1275 } else {
1276 strw(Rx, spill_address(4, offset));
1277 }
1278 }
1279 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1280 str(Vx, T, spill_address(1 << (int)T, offset));
1281 }
1282 void unspill(Register Rx, bool is64, int offset) {
1283 if (is64) {
1284 ldr(Rx, spill_address(8, offset));
1285 } else {
1286 ldrw(Rx, spill_address(4, offset));
1287 }
1288 }
1289 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1290 ldr(Vx, T, spill_address(1 << (int)T, offset));
1291 }
1292 void spill_copy128(int src_offset, int dst_offset,
1293 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1294 if (src_offset < 512 && (src_offset & 7) == 0 &&
1295 dst_offset < 512 && (dst_offset & 7) == 0) {
1296 ldp(tmp1, tmp2, Address(sp, src_offset));
1297 stp(tmp1, tmp2, Address(sp, dst_offset));
1298 } else {
1299 unspill(tmp1, true, src_offset);
1300 spill(tmp1, true, dst_offset);
1301 unspill(tmp1, true, src_offset+8);
1302 spill(tmp1, true, dst_offset+8);
1303 }
1304 }
1305 };
1306
1307 #ifdef ASSERT
1308 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1309 #endif
1310
1311 /**
1312 * class SkipIfEqual:
1313 *
1314 * Instantiating this class will result in assembly code being output that will
1315 * jump around any code emitted between the creation of the instance and it's
1316 * automatic destruction at the end of a scope block, depending on the value of
1317 * the flag passed to the constructor, which will be checked at run-time.
1318 */
1319 class SkipIfEqual {
1320 private:
1321 MacroAssembler* _masm;
1322 Label _label;
1323
1324 public:
1325 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1326 ~SkipIfEqual();
1327 };
1328
1329 struct tableswitch {
1330 Register _reg;
1331 int _insn_index; jint _first_key; jint _last_key;
1332 Label _after;
1333 Label _branches;
1334 };
1335
1336 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP