230 int oper_idx = num_opnds();
231 while (--oper_idx >= 0) {
232 if (_opnds[oper_idx] == oper) break;
233 }
234 int oper_pos = operand_index(oper_idx);
235 int base_pos = oper->base_position();
236 if (base_pos >= 0) {
237 base = _in[oper_pos+base_pos];
238 }
239 int index_pos = oper->index_position();
240 if (index_pos >= 0) {
241 index = _in[oper_pos+index_pos];
242 }
243 }
244 }
245
246 return oper;
247 }
248
249 //-----------------------------get_base_and_disp----------------------------
250 Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
251
252 // Find the memory inputs using our helper function
253 Node* base;
254 Node* index;
255 const MachOper* oper = memory_inputs(base, index);
256
257 if (oper == NULL) {
258 // Base has been set to NULL
259 offset = 0;
260 } else if (oper == (MachOper*)-1) {
261 // Base has been set to NodeSentinel
262 // There is not a unique memory use here. We will fall to AliasIdxBot.
263 offset = Type::OffsetBot;
264 } else {
265 // Base may be NULL, even if offset turns out to be != 0
266
267 intptr_t disp = oper->constant_disp();
268 int scale = oper->scale();
269 // Now we have collected every part of the ADLC MEMORY_INTER.
270 // See if it adds up to a base + offset.
309 }
310 adr_type = t_disp->add_offset(offset);
311 } else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) {
312 // Use ideal type if it is oop ptr.
313 const TypePtr *tp = oper->type()->isa_ptr();
314 if( tp != NULL) {
315 adr_type = tp;
316 }
317 }
318 }
319
320 }
321 return base;
322 }
323
324
325 //---------------------------------adr_type---------------------------------
326 const class TypePtr *MachNode::adr_type() const {
327 intptr_t offset = 0;
328 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
329 Node *base = get_base_and_disp(offset, adr_type);
330
331 if( adr_type != TYPE_PTR_SENTINAL ) {
332 return adr_type; // get_base_and_disp has the answer
333 }
334
335 // Direct addressing modes have no base node, simply an indirect
336 // offset, which is always to raw memory.
337 // %%%%% Someday we'd like to allow constant oop offsets which
338 // would let Intel load from static globals in 1 instruction.
339 // Currently Intel requires 2 instructions and a register temp.
340 if (base == NULL) {
341 // NULL base, zero offset means no memory at all (a null pointer!)
342 if (offset == 0) {
343 return NULL;
344 }
345 // NULL base, any offset means any pointer whatever
346 if (offset == Type::OffsetBot) {
347 return TypePtr::BOTTOM;
348 }
349 // %%% make offset be intptr_t
350 assert(!Universe::heap()->is_in_reserved(cast_to_oop(offset)), "must be a raw ptr");
774 void MachCallRuntimeNode::dump_spec(outputStream *st) const {
775 st->print("%s ",_name);
776 MachCallNode::dump_spec(st);
777 }
778 #endif
779 //=============================================================================
780 // A shared JVMState for all HaltNodes. Indicates the start of debug info
781 // is at TypeFunc::Parms. Only required for SOE register spill handling -
782 // to indicate where the stack-slot-only debug info inputs begin.
783 // There is no other JVM state needed here.
784 JVMState jvms_for_throw(0);
785 JVMState *MachHaltNode::jvms() const {
786 return &jvms_for_throw;
787 }
788
789 uint MachMemBarNode::size_of() const { return sizeof(*this); }
790
791 const TypePtr *MachMemBarNode::adr_type() const {
792 return _adr_type;
793 }
794
795
796 //=============================================================================
797 #ifndef PRODUCT
798 void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
799 st->print("B%d", _block_num);
800 }
801 #endif // PRODUCT
802
803 //=============================================================================
804 #ifndef PRODUCT
805 void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
806 st->print(INTPTR_FORMAT, _method);
807 }
808 #endif // PRODUCT
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230 int oper_idx = num_opnds();
231 while (--oper_idx >= 0) {
232 if (_opnds[oper_idx] == oper) break;
233 }
234 int oper_pos = operand_index(oper_idx);
235 int base_pos = oper->base_position();
236 if (base_pos >= 0) {
237 base = _in[oper_pos+base_pos];
238 }
239 int index_pos = oper->index_position();
240 if (index_pos >= 0) {
241 index = _in[oper_pos+index_pos];
242 }
243 }
244 }
245
246 return oper;
247 }
248
249 //-----------------------------get_base_and_disp----------------------------
250 const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
251
252 // Find the memory inputs using our helper function
253 Node* base;
254 Node* index;
255 const MachOper* oper = memory_inputs(base, index);
256
257 if (oper == NULL) {
258 // Base has been set to NULL
259 offset = 0;
260 } else if (oper == (MachOper*)-1) {
261 // Base has been set to NodeSentinel
262 // There is not a unique memory use here. We will fall to AliasIdxBot.
263 offset = Type::OffsetBot;
264 } else {
265 // Base may be NULL, even if offset turns out to be != 0
266
267 intptr_t disp = oper->constant_disp();
268 int scale = oper->scale();
269 // Now we have collected every part of the ADLC MEMORY_INTER.
270 // See if it adds up to a base + offset.
309 }
310 adr_type = t_disp->add_offset(offset);
311 } else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) {
312 // Use ideal type if it is oop ptr.
313 const TypePtr *tp = oper->type()->isa_ptr();
314 if( tp != NULL) {
315 adr_type = tp;
316 }
317 }
318 }
319
320 }
321 return base;
322 }
323
324
325 //---------------------------------adr_type---------------------------------
326 const class TypePtr *MachNode::adr_type() const {
327 intptr_t offset = 0;
328 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
329 const Node *base = get_base_and_disp(offset, adr_type);
330 if( adr_type != TYPE_PTR_SENTINAL ) {
331 return adr_type; // get_base_and_disp has the answer
332 }
333
334 // Direct addressing modes have no base node, simply an indirect
335 // offset, which is always to raw memory.
336 // %%%%% Someday we'd like to allow constant oop offsets which
337 // would let Intel load from static globals in 1 instruction.
338 // Currently Intel requires 2 instructions and a register temp.
339 if (base == NULL) {
340 // NULL base, zero offset means no memory at all (a null pointer!)
341 if (offset == 0) {
342 return NULL;
343 }
344 // NULL base, any offset means any pointer whatever
345 if (offset == Type::OffsetBot) {
346 return TypePtr::BOTTOM;
347 }
348 // %%% make offset be intptr_t
349 assert(!Universe::heap()->is_in_reserved(cast_to_oop(offset)), "must be a raw ptr");
773 void MachCallRuntimeNode::dump_spec(outputStream *st) const {
774 st->print("%s ",_name);
775 MachCallNode::dump_spec(st);
776 }
777 #endif
778 //=============================================================================
779 // A shared JVMState for all HaltNodes. Indicates the start of debug info
780 // is at TypeFunc::Parms. Only required for SOE register spill handling -
781 // to indicate where the stack-slot-only debug info inputs begin.
782 // There is no other JVM state needed here.
783 JVMState jvms_for_throw(0);
784 JVMState *MachHaltNode::jvms() const {
785 return &jvms_for_throw;
786 }
787
788 uint MachMemBarNode::size_of() const { return sizeof(*this); }
789
790 const TypePtr *MachMemBarNode::adr_type() const {
791 return _adr_type;
792 }
793
794 //=============================================================================
795 #ifndef PRODUCT
796 void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
797 st->print("B%d", _block_num);
798 }
799 #endif // PRODUCT
800
801 //=============================================================================
802 #ifndef PRODUCT
803 void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
804 st->print(INTPTR_FORMAT, _method);
805 }
806 #endif // PRODUCT
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