1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // Stores
297 void store_check(Register obj); // store check for obj - register is destroyed afterwards
298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
299
300 void resolve_jobject(Register value, Register thread, Register tmp);
301 void clear_jweak_tag(Register possibly_jweak);
302
303 #if INCLUDE_ALL_GCS
304
305 void g1_write_barrier_pre(Register obj,
306 Register pre_val,
307 Register thread,
308 Register tmp,
309 bool tosca_live,
310 bool expand_call);
311
312 void g1_write_barrier_post(Register store_addr,
313 Register new_val,
314 Register thread,
315 Register tmp,
316 Register tmp2);
317
318 void keep_alive_barrier(Register val,
319 Register thread,
320 Register tmp);
321
322 void shenandoah_write_barrier_post(Register store_addr,
323 Register new_val,
324 Register thread,
325 Register tmp,
326 Register tmp2);
327
328 void shenandoah_write_barrier(Register dst);
329
330 #endif // INCLUDE_ALL_GCS
331
332 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
333 void c2bool(Register x);
334
335 // C++ bool manipulation
336
337 void movbool(Register dst, Address src);
338 void movbool(Address dst, bool boolconst);
339 void movbool(Address dst, Register src);
340 void testbool(Register dst);
341
342 void load_mirror(Register mirror, Register method);
343
344 // oop manipulations
345 void load_klass(Register dst, Register src);
346 void store_klass(Register dst, Register src);
347
348 void load_heap_oop(Register dst, Address src);
349 void load_heap_oop_not_null(Register dst, Address src);
350 void store_heap_oop(Address dst, Register src);
351 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
352
353 // Used for storing NULL. All other oop constants should be
354 // stored using routines that take a jobject.
355 void store_heap_oop_null(Address dst);
356
357 void load_prototype_header(Register dst, Register src);
358
359 #ifdef _LP64
360 void store_klass_gap(Register dst, Register src);
361
362 // This dummy is to prevent a call to store_heap_oop from
363 // converting a zero (like NULL) into a Register by giving
364 // the compiler two choices it can't resolve
365
366 void store_heap_oop(Address dst, void* dummy);
367
368 void encode_heap_oop(Register r);
369 void decode_heap_oop(Register r);
370 void encode_heap_oop_not_null(Register r);
371 void decode_heap_oop_not_null(Register r);
372 void encode_heap_oop_not_null(Register dst, Register src);
373 void decode_heap_oop_not_null(Register dst, Register src);
374
375 void set_narrow_oop(Register dst, jobject obj);
376 void set_narrow_oop(Address dst, jobject obj);
377 void cmp_narrow_oop(Register dst, jobject obj);
378 void cmp_narrow_oop(Address dst, jobject obj);
379
380 void encode_klass_not_null(Register r);
381 void decode_klass_not_null(Register r);
382 void encode_klass_not_null(Register dst, Register src);
383 void decode_klass_not_null(Register dst, Register src);
384 void set_narrow_klass(Register dst, Klass* k);
385 void set_narrow_klass(Address dst, Klass* k);
386 void cmp_narrow_klass(Register dst, Klass* k);
387 void cmp_narrow_klass(Address dst, Klass* k);
388
389 // Returns the byte size of the instructions generated by decode_klass_not_null()
390 // when compressed klass pointers are being used.
391 static int instr_size_for_decode_klass_not_null();
392
393 // if heap base register is used - reinit it with the correct value
394 void reinit_heapbase();
395
396 DEBUG_ONLY(void verify_heapbase(const char* msg);)
397
398 #endif // _LP64
399
400 // Int division/remainder for Java
401 // (as idivl, but checks for special case as described in JVM spec.)
402 // returns idivl instruction offset for implicit exception handling
403 int corrected_idivl(Register reg);
404
405 // Long division/remainder for Java
406 // (as idivq, but checks for special case as described in JVM spec.)
407 // returns idivq instruction offset for implicit exception handling
408 int corrected_idivq(Register reg);
409
410 void int3();
411
412 // Long operation macros for a 32bit cpu
413 // Long negation for Java
414 void lneg(Register hi, Register lo);
415
416 // Long multiplication for Java
417 // (destroys contents of eax, ebx, ecx and edx)
418 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
419
420 // Long shifts for Java
421 // (semantics as described in JVM spec.)
422 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
423 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
424
425 // Long compare for Java
426 // (semantics as described in JVM spec.)
427 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
428
429
430 // misc
431
432 // Sign extension
433 void sign_extend_short(Register reg);
434 void sign_extend_byte(Register reg);
435
436 // Division by power of 2, rounding towards 0
437 void division_with_shift(Register reg, int shift_value);
438
439 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
440 //
441 // CF (corresponds to C0) if x < y
442 // PF (corresponds to C2) if unordered
443 // ZF (corresponds to C3) if x = y
444 //
445 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
446 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
447 void fcmp(Register tmp);
448 // Variant of the above which allows y to be further down the stack
449 // and which only pops x and y if specified. If pop_right is
450 // specified then pop_left must also be specified.
451 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
452
453 // Floating-point comparison for Java
454 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
455 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
456 // (semantics as described in JVM spec.)
457 void fcmp2int(Register dst, bool unordered_is_less);
458 // Variant of the above which allows y to be further down the stack
459 // and which only pops x and y if specified. If pop_right is
460 // specified then pop_left must also be specified.
461 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
462
463 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
464 // tmp is a temporary register, if none is available use noreg
465 void fremr(Register tmp);
466
467 // dst = c = a * b + c
468 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
469 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
470
471 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
472 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
473 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
474 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
475
476
477 // same as fcmp2int, but using SSE2
478 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
479 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
480
481 // branch to L if FPU flag C2 is set/not set
482 // tmp is a temporary register, if none is available use noreg
483 void jC2 (Register tmp, Label& L);
484 void jnC2(Register tmp, Label& L);
485
486 // Pop ST (ffree & fincstp combined)
487 void fpop();
488
489 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
490 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
491 void load_float(Address src);
492
493 // Store float value to 'address'. If UseSSE >= 1, the value is stored
494 // from register xmm0. Otherwise, the value is stored from the FPU stack.
495 void store_float(Address dst);
496
497 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
498 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
499 void load_double(Address src);
500
501 // Store double value to 'address'. If UseSSE >= 2, the value is stored
502 // from register xmm0. Otherwise, the value is stored from the FPU stack.
503 void store_double(Address dst);
504
505 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
506 void push_fTOS();
507
508 // pops double TOS element from CPU stack and pushes on FPU stack
509 void pop_fTOS();
510
511 void empty_FPU_stack();
512
513 void push_IU_state();
514 void pop_IU_state();
515
516 void push_FPU_state();
517 void pop_FPU_state();
518
519 void push_CPU_state();
520 void pop_CPU_state();
521
522 // Round up to a power of two
523 void round_to(Register reg, int modulus);
524
525 // Callee saved registers handling
526 void push_callee_saved_registers();
527 void pop_callee_saved_registers();
528
529 // allocation
530 void eden_allocate(
531 Register obj, // result: pointer to object after successful allocation
532 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
533 int con_size_in_bytes, // object size in bytes if known at compile time
534 Register t1, // temp register
535 Label& slow_case // continuation point if fast allocation fails
536 );
537 void tlab_allocate(
538 Register obj, // result: pointer to object after successful allocation
539 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
540 int con_size_in_bytes, // object size in bytes if known at compile time
541 Register t1, // temp register
542 Register t2, // temp register
543 Label& slow_case // continuation point if fast allocation fails
544 );
545 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
546 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
547
548 void incr_allocated_bytes(Register thread,
549 Register var_size_in_bytes, int con_size_in_bytes,
550 Register t1 = noreg);
551
552 // interface method calling
553 void lookup_interface_method(Register recv_klass,
554 Register intf_klass,
555 RegisterOrConstant itable_index,
556 Register method_result,
557 Register scan_temp,
558 Label& no_such_interface);
559
560 // virtual method calling
561 void lookup_virtual_method(Register recv_klass,
562 RegisterOrConstant vtable_index,
563 Register method_result);
564
565 // Test sub_klass against super_klass, with fast and slow paths.
566
567 // The fast path produces a tri-state answer: yes / no / maybe-slow.
568 // One of the three labels can be NULL, meaning take the fall-through.
569 // If super_check_offset is -1, the value is loaded up from super_klass.
570 // No registers are killed, except temp_reg.
571 void check_klass_subtype_fast_path(Register sub_klass,
572 Register super_klass,
573 Register temp_reg,
574 Label* L_success,
575 Label* L_failure,
576 Label* L_slow_path,
577 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
578
579 // The rest of the type check; must be wired to a corresponding fast path.
580 // It does not repeat the fast path logic, so don't use it standalone.
581 // The temp_reg and temp2_reg can be noreg, if no temps are available.
582 // Updates the sub's secondary super cache as necessary.
583 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
584 void check_klass_subtype_slow_path(Register sub_klass,
585 Register super_klass,
586 Register temp_reg,
587 Register temp2_reg,
588 Label* L_success,
589 Label* L_failure,
590 bool set_cond_codes = false);
591
592 // Simplified, combined version, good for typical uses.
593 // Falls through on failure.
594 void check_klass_subtype(Register sub_klass,
595 Register super_klass,
596 Register temp_reg,
597 Label& L_success);
598
599 // method handles (JSR 292)
600 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
601
602 //----
603 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
604
605 // Debugging
606
607 // only if +VerifyOops
608 // TODO: Make these macros with file and line like sparc version!
609 void verify_oop(Register reg, const char* s = "broken oop");
610 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
611
612 void shenandoah_in_heap_check(Register dst, Register tmp, Label& done);
613 void shenandoah_cset_check(Register dst, Register tmp, Label& done);
614
615 void shenandoah_store_addr_check(Register dst);
616 void shenandoah_store_addr_check(Address dst);
617
618 void shenandoah_store_val_check(Register dst, Register value);
619 void shenandoah_store_val_check(Address dst, Register value);
620
621 void shenandoah_lock_check(Register dst);
622
623 // TODO: verify method and klass metadata (compare against vptr?)
624 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
625 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
626
627 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
628 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
629
630 // only if +VerifyFPU
631 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
632
633 // Verify or restore cpu control state after JNI call
634 void restore_cpu_control_state_after_jni();
635
636 // prints msg, dumps registers and stops execution
637 void stop(const char* msg);
638
639 // prints msg and continues
640 void warn(const char* msg);
641
642 // dumps registers and other state
643 void print_state();
644
645 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
646 static void debug64(char* msg, int64_t pc, int64_t regs[]);
647 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
648 static void print_state64(int64_t pc, int64_t regs[]);
649
650 void os_breakpoint();
651
652 void untested() { stop("untested"); }
653
654 void unimplemented(const char* what = "");
655
656 void should_not_reach_here() { stop("should not reach here"); }
657
658 void print_CPU_state();
659
660 // Stack overflow checking
661 void bang_stack_with_offset(int offset) {
662 // stack grows down, caller passes positive offset
663 assert(offset > 0, "must bang with negative offset");
664 movl(Address(rsp, (-offset)), rax);
665 }
666
667 // Writes to stack successive pages until offset reached to check for
668 // stack overflow + shadow pages. Also, clobbers tmp
669 void bang_stack_size(Register size, Register tmp);
670
671 // Check for reserved stack access in method being exited (for JIT)
672 void reserved_stack_check();
673
674 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
675 Register tmp,
676 int offset);
677
678 // Support for serializing memory accesses between threads
679 void serialize_memory(Register thread, Register tmp);
680
681 void verify_tlab();
682
683 // Biased locking support
684 // lock_reg and obj_reg must be loaded up with the appropriate values.
685 // swap_reg must be rax, and is killed.
686 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
687 // be killed; if not supplied, push/pop will be used internally to
688 // allocate a temporary (inefficient, avoid if possible).
689 // Optional slow case is for implementations (interpreter and C1) which branch to
690 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
691 // Returns offset of first potentially-faulting instruction for null
692 // check info (currently consumed only by C1). If
693 // swap_reg_contains_mark is true then returns -1 as it is assumed
694 // the calling code has already passed any potential faults.
695 int biased_locking_enter(Register lock_reg, Register obj_reg,
696 Register swap_reg, Register tmp_reg,
697 bool swap_reg_contains_mark,
698 Label& done, Label* slow_case = NULL,
699 BiasedLockingCounters* counters = NULL);
700 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
701 #ifdef COMPILER2
702 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
703 // See full desription in macroAssembler_x86.cpp.
704 void fast_lock(Register obj, Register box, Register tmp,
705 Register scr, Register cx1, Register cx2,
706 BiasedLockingCounters* counters,
707 RTMLockingCounters* rtm_counters,
708 RTMLockingCounters* stack_rtm_counters,
709 Metadata* method_data,
710 bool use_rtm, bool profile_rtm);
711 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
712 #if INCLUDE_RTM_OPT
713 void rtm_counters_update(Register abort_status, Register rtm_counters);
714 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
715 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
716 RTMLockingCounters* rtm_counters,
717 Metadata* method_data);
718 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
719 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
720 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
721 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
722 void rtm_stack_locking(Register obj, Register tmp, Register scr,
723 Register retry_on_abort_count,
724 RTMLockingCounters* stack_rtm_counters,
725 Metadata* method_data, bool profile_rtm,
726 Label& DONE_LABEL, Label& IsInflated);
727 void rtm_inflated_locking(Register obj, Register box, Register tmp,
728 Register scr, Register retry_on_busy_count,
729 Register retry_on_abort_count,
730 RTMLockingCounters* rtm_counters,
731 Metadata* method_data, bool profile_rtm,
732 Label& DONE_LABEL);
733 #endif
734 #endif
735
736 Condition negate_condition(Condition cond);
737
738 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
739 // operands. In general the names are modified to avoid hiding the instruction in Assembler
740 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
741 // here in MacroAssembler. The major exception to this rule is call
742
743 // Arithmetics
744
745
746 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
747 void addptr(Address dst, Register src);
748
749 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
750 void addptr(Register dst, int32_t src);
751 void addptr(Register dst, Register src);
752 void addptr(Register dst, RegisterOrConstant src) {
753 if (src.is_constant()) addptr(dst, (int) src.as_constant());
754 else addptr(dst, src.as_register());
755 }
756
757 void andptr(Register dst, int32_t src);
758 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
759
760 void cmp8(AddressLiteral src1, int imm);
761
762 // renamed to drag out the casting of address to int32_t/intptr_t
763 void cmp32(Register src1, int32_t imm);
764
765 void cmp32(AddressLiteral src1, int32_t imm);
766 // compare reg - mem, or reg - &mem
767 void cmp32(Register src1, AddressLiteral src2);
768
769 void cmp32(Register src1, Address src2);
770
771 #ifndef _LP64
772 void cmpklass(Address dst, Metadata* obj);
773 void cmpklass(Register dst, Metadata* obj);
774 void cmpoop(Address dst, jobject obj);
775 void cmpoop(Register dst, jobject obj);
776 #endif // _LP64
777
778 // NOTE src2 must be the lval. This is NOT an mem-mem compare
779 void cmpptr(Address src1, AddressLiteral src2);
780
781 void cmpptr(Register src1, AddressLiteral src2);
782
783 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
784 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
785 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
786
787 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
788 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
789
790 // cmp64 to avoild hiding cmpq
791 void cmp64(Register src1, AddressLiteral src);
792
793 // Special cmp for heap objects, possibly inserting required barriers.
794 void cmpoops(Register src1, Register src2);
795 void cmpoops(Register src1, Address src2);
796
797 void cmpxchgptr(Register reg, Address adr);
798
799 // Special Shenandoah CAS implementation that handles false negatives
800 // due to concurrent evacuation.
801 void cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
802 bool exchange,
803 Register tmp1, Register tmp2);
804
805 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
806
807
808 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
809 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
810
811
812 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
813
814 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
815
816 void shlptr(Register dst, int32_t shift);
817 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
818
819 void shrptr(Register dst, int32_t shift);
820 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
821
822 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
823 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
824
825 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
826
827 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
828 void subptr(Register dst, int32_t src);
829 // Force generation of a 4 byte immediate value even if it fits into 8bit
830 void subptr_imm32(Register dst, int32_t src);
831 void subptr(Register dst, Register src);
832 void subptr(Register dst, RegisterOrConstant src) {
833 if (src.is_constant()) subptr(dst, (int) src.as_constant());
834 else subptr(dst, src.as_register());
835 }
836
837 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
838 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
839
840 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
841 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
842
843 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
844
845
846
847 // Helper functions for statistics gathering.
848 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
849 void cond_inc32(Condition cond, AddressLiteral counter_addr);
850 // Unconditional atomic increment.
851 void atomic_incl(Address counter_addr);
852 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
853 #ifdef _LP64
854 void atomic_incq(Address counter_addr);
855 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
856 #endif
857 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
858 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
859
860 void lea(Register dst, AddressLiteral adr);
861 void lea(Address dst, AddressLiteral adr);
862 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
863
864 void leal32(Register dst, Address src) { leal(dst, src); }
865
866 // Import other testl() methods from the parent class or else
867 // they will be hidden by the following overriding declaration.
868 using Assembler::testl;
869 void testl(Register dst, AddressLiteral src);
870
871 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
872 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
873 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
874 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
875
876 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
877 void testptr(Register src1, Register src2);
878
879 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
880 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
881
882 // Calls
883
884 void call(Label& L, relocInfo::relocType rtype);
885 void call(Register entry);
886
887 // NOTE: this call transfers to the effective address of entry NOT
888 // the address contained by entry. This is because this is more natural
889 // for jumps/calls.
890 void call(AddressLiteral entry);
891
892 // Emit the CompiledIC call idiom
893 void ic_call(address entry, jint method_index = 0);
894
895 // Jumps
896
897 // NOTE: these jumps tranfer to the effective address of dst NOT
898 // the address contained by dst. This is because this is more natural
899 // for jumps/calls.
900 void jump(AddressLiteral dst);
901 void jump_cc(Condition cc, AddressLiteral dst);
902
903 // 32bit can do a case table jump in one instruction but we no longer allow the base
904 // to be installed in the Address class. This jump will tranfers to the address
905 // contained in the location described by entry (not the address of entry)
906 void jump(ArrayAddress entry);
907
908 // Floating
909
910 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
911 void andpd(XMMRegister dst, AddressLiteral src);
912 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
913
914 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
915 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
916 void andps(XMMRegister dst, AddressLiteral src);
917
918 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
919 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
920 void comiss(XMMRegister dst, AddressLiteral src);
921
922 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
923 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
924 void comisd(XMMRegister dst, AddressLiteral src);
925
926 void fadd_s(Address src) { Assembler::fadd_s(src); }
927 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
928
929 void fldcw(Address src) { Assembler::fldcw(src); }
930 void fldcw(AddressLiteral src);
931
932 void fld_s(int index) { Assembler::fld_s(index); }
933 void fld_s(Address src) { Assembler::fld_s(src); }
934 void fld_s(AddressLiteral src);
935
936 void fld_d(Address src) { Assembler::fld_d(src); }
937 void fld_d(AddressLiteral src);
938
939 void fld_x(Address src) { Assembler::fld_x(src); }
940 void fld_x(AddressLiteral src);
941
942 void fmul_s(Address src) { Assembler::fmul_s(src); }
943 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
944
945 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
946 void ldmxcsr(AddressLiteral src);
947
948 #ifdef _LP64
949 private:
950 void sha256_AVX2_one_round_compute(
951 Register reg_old_h,
952 Register reg_a,
953 Register reg_b,
954 Register reg_c,
955 Register reg_d,
956 Register reg_e,
957 Register reg_f,
958 Register reg_g,
959 Register reg_h,
960 int iter);
961 void sha256_AVX2_four_rounds_compute_first(int start);
962 void sha256_AVX2_four_rounds_compute_last(int start);
963 void sha256_AVX2_one_round_and_sched(
964 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
965 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
966 XMMRegister xmm_2, /* ymm6 */
967 XMMRegister xmm_3, /* ymm7 */
968 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
969 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
970 Register reg_c, /* edi */
971 Register reg_d, /* esi */
972 Register reg_e, /* r8d */
973 Register reg_f, /* r9d */
974 Register reg_g, /* r10d */
975 Register reg_h, /* r11d */
976 int iter);
977
978 void addm(int disp, Register r1, Register r2);
979
980 public:
981 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
982 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
983 Register buf, Register state, Register ofs, Register limit, Register rsp,
984 bool multi_block, XMMRegister shuf_mask);
985 #endif
986
987 #ifdef _LP64
988 private:
989 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
990 Register e, Register f, Register g, Register h, int iteration);
991
992 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
993 Register a, Register b, Register c, Register d, Register e, Register f,
994 Register g, Register h, int iteration);
995
996 void addmq(int disp, Register r1, Register r2);
997 public:
998 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
999 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1000 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1001 XMMRegister shuf_mask);
1002 #endif
1003
1004 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1005 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1006 Register buf, Register state, Register ofs, Register limit, Register rsp,
1007 bool multi_block);
1008
1009 #ifdef _LP64
1010 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1011 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1012 Register buf, Register state, Register ofs, Register limit, Register rsp,
1013 bool multi_block, XMMRegister shuf_mask);
1014 #else
1015 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1016 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1017 Register buf, Register state, Register ofs, Register limit, Register rsp,
1018 bool multi_block);
1019 #endif
1020
1021 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023 Register rax, Register rcx, Register rdx, Register tmp);
1024
1025 #ifdef _LP64
1026 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1027 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1028 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1029
1030 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1031 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1032 Register rax, Register rcx, Register rdx, Register r11);
1033
1034 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1035 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1036 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1037
1038 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1039 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1040 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1041 Register tmp3, Register tmp4);
1042
1043 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1044 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1045 Register rax, Register rcx, Register rdx, Register tmp1,
1046 Register tmp2, Register tmp3, Register tmp4);
1047 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1048 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1049 Register rax, Register rcx, Register rdx, Register tmp1,
1050 Register tmp2, Register tmp3, Register tmp4);
1051 #else
1052 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1053 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1054 Register rax, Register rcx, Register rdx, Register tmp1);
1055
1056 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1057 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1058 Register rax, Register rcx, Register rdx, Register tmp);
1059
1060 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1061 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1062 Register rdx, Register tmp);
1063
1064 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1065 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1066 Register rax, Register rbx, Register rdx);
1067
1068 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1069 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1070 Register rax, Register rcx, Register rdx, Register tmp);
1071
1072 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1073 Register edx, Register ebx, Register esi, Register edi,
1074 Register ebp, Register esp);
1075
1076 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1077 Register esi, Register edi, Register ebp, Register esp);
1078
1079 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1080 Register edx, Register ebx, Register esi, Register edi,
1081 Register ebp, Register esp);
1082
1083 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1084 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1085 Register rax, Register rcx, Register rdx, Register tmp);
1086 #endif
1087
1088 void increase_precision();
1089 void restore_precision();
1090
1091 private:
1092
1093 // these are private because users should be doing movflt/movdbl
1094
1095 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1096 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1097 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1098 void movss(XMMRegister dst, AddressLiteral src);
1099
1100 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1101 void movlpd(XMMRegister dst, AddressLiteral src);
1102
1103 public:
1104
1105 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1106 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1107 void addsd(XMMRegister dst, AddressLiteral src);
1108
1109 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1110 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1111 void addss(XMMRegister dst, AddressLiteral src);
1112
1113 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1114 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1115 void addpd(XMMRegister dst, AddressLiteral src);
1116
1117 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1118 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1119 void divsd(XMMRegister dst, AddressLiteral src);
1120
1121 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1122 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1123 void divss(XMMRegister dst, AddressLiteral src);
1124
1125 // Move Unaligned Double Quadword
1126 void movdqu(Address dst, XMMRegister src);
1127 void movdqu(XMMRegister dst, Address src);
1128 void movdqu(XMMRegister dst, XMMRegister src);
1129 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1130 // AVX Unaligned forms
1131 void vmovdqu(Address dst, XMMRegister src);
1132 void vmovdqu(XMMRegister dst, Address src);
1133 void vmovdqu(XMMRegister dst, XMMRegister src);
1134 void vmovdqu(XMMRegister dst, AddressLiteral src);
1135
1136 // Move Aligned Double Quadword
1137 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1138 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1139 void movdqa(XMMRegister dst, AddressLiteral src);
1140
1141 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1142 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1143 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1144 void movsd(XMMRegister dst, AddressLiteral src);
1145
1146 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1147 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1148 void mulpd(XMMRegister dst, AddressLiteral src);
1149
1150 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1151 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1152 void mulsd(XMMRegister dst, AddressLiteral src);
1153
1154 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1155 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1156 void mulss(XMMRegister dst, AddressLiteral src);
1157
1158 // Carry-Less Multiplication Quadword
1159 void pclmulldq(XMMRegister dst, XMMRegister src) {
1160 // 0x00 - multiply lower 64 bits [0:63]
1161 Assembler::pclmulqdq(dst, src, 0x00);
1162 }
1163 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1164 // 0x11 - multiply upper 64 bits [64:127]
1165 Assembler::pclmulqdq(dst, src, 0x11);
1166 }
1167
1168 void pcmpeqb(XMMRegister dst, XMMRegister src);
1169 void pcmpeqw(XMMRegister dst, XMMRegister src);
1170
1171 void pcmpestri(XMMRegister dst, Address src, int imm8);
1172 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1173
1174 void pmovzxbw(XMMRegister dst, XMMRegister src);
1175 void pmovzxbw(XMMRegister dst, Address src);
1176
1177 void pmovmskb(Register dst, XMMRegister src);
1178
1179 void ptest(XMMRegister dst, XMMRegister src);
1180
1181 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1182 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1183 void sqrtsd(XMMRegister dst, AddressLiteral src);
1184
1185 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1186 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1187 void sqrtss(XMMRegister dst, AddressLiteral src);
1188
1189 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1190 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1191 void subsd(XMMRegister dst, AddressLiteral src);
1192
1193 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1194 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1195 void subss(XMMRegister dst, AddressLiteral src);
1196
1197 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1198 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1199 void ucomiss(XMMRegister dst, AddressLiteral src);
1200
1201 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1202 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1203 void ucomisd(XMMRegister dst, AddressLiteral src);
1204
1205 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1206 void xorpd(XMMRegister dst, XMMRegister src);
1207 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1208 void xorpd(XMMRegister dst, AddressLiteral src);
1209
1210 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1211 void xorps(XMMRegister dst, XMMRegister src);
1212 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1213 void xorps(XMMRegister dst, AddressLiteral src);
1214
1215 // Shuffle Bytes
1216 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1217 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1218 void pshufb(XMMRegister dst, AddressLiteral src);
1219 // AVX 3-operands instructions
1220
1221 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1222 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1223 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1224
1225 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1226 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1227 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1228
1229 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1230 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1231
1232 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1233 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1234
1235 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1236 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1237
1238 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1239 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1240 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1241
1242 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1243
1244 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1245 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1246
1247 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1248 void vpmovmskb(Register dst, XMMRegister src);
1249
1250 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1251 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1252
1253 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1254 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1255
1256 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1257 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1258
1259 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1260 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1261
1262 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1263 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1264
1265 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1266 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1267
1268 void vptest(XMMRegister dst, XMMRegister src);
1269
1270 void punpcklbw(XMMRegister dst, XMMRegister src);
1271 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1272
1273 void pshufd(XMMRegister dst, Address src, int mode);
1274 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1275
1276 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1277 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1278
1279 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1280 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1281 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1282
1283 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1284 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1285 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1286
1287 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1288 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1289 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1290
1291 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1292 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1293 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1294
1295 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1296 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1297 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1298
1299 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1300 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1301 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1302
1303 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1304 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1305 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1306
1307 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1308 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1309 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1310
1311 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1312 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1313
1314 // AVX Vector instructions
1315
1316 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1317 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1318 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1319
1320 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1321 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1322 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1323
1324 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1325 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1326 Assembler::vpxor(dst, nds, src, vector_len);
1327 else
1328 Assembler::vxorpd(dst, nds, src, vector_len);
1329 }
1330 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1331 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1332 Assembler::vpxor(dst, nds, src, vector_len);
1333 else
1334 Assembler::vxorpd(dst, nds, src, vector_len);
1335 }
1336
1337 // Simple version for AVX2 256bit vectors
1338 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1339 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1340
1341 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1342 if (UseAVX > 2) {
1343 Assembler::vinserti32x4(dst, dst, src, imm8);
1344 } else if (UseAVX > 1) {
1345 // vinserti128 is available only in AVX2
1346 Assembler::vinserti128(dst, nds, src, imm8);
1347 } else {
1348 Assembler::vinsertf128(dst, nds, src, imm8);
1349 }
1350 }
1351
1352 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1353 if (UseAVX > 2) {
1354 Assembler::vinserti32x4(dst, dst, src, imm8);
1355 } else if (UseAVX > 1) {
1356 // vinserti128 is available only in AVX2
1357 Assembler::vinserti128(dst, nds, src, imm8);
1358 } else {
1359 Assembler::vinsertf128(dst, nds, src, imm8);
1360 }
1361 }
1362
1363 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1364 if (UseAVX > 2) {
1365 Assembler::vextracti32x4(dst, src, imm8);
1366 } else if (UseAVX > 1) {
1367 // vextracti128 is available only in AVX2
1368 Assembler::vextracti128(dst, src, imm8);
1369 } else {
1370 Assembler::vextractf128(dst, src, imm8);
1371 }
1372 }
1373
1374 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1375 if (UseAVX > 2) {
1376 Assembler::vextracti32x4(dst, src, imm8);
1377 } else if (UseAVX > 1) {
1378 // vextracti128 is available only in AVX2
1379 Assembler::vextracti128(dst, src, imm8);
1380 } else {
1381 Assembler::vextractf128(dst, src, imm8);
1382 }
1383 }
1384
1385 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1386 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1387 vinserti128(dst, dst, src, 1);
1388 }
1389 void vinserti128_high(XMMRegister dst, Address src) {
1390 vinserti128(dst, dst, src, 1);
1391 }
1392 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1393 vextracti128(dst, src, 1);
1394 }
1395 void vextracti128_high(Address dst, XMMRegister src) {
1396 vextracti128(dst, src, 1);
1397 }
1398
1399 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1400 if (UseAVX > 2) {
1401 Assembler::vinsertf32x4(dst, dst, src, 1);
1402 } else {
1403 Assembler::vinsertf128(dst, dst, src, 1);
1404 }
1405 }
1406
1407 void vinsertf128_high(XMMRegister dst, Address src) {
1408 if (UseAVX > 2) {
1409 Assembler::vinsertf32x4(dst, dst, src, 1);
1410 } else {
1411 Assembler::vinsertf128(dst, dst, src, 1);
1412 }
1413 }
1414
1415 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1416 if (UseAVX > 2) {
1417 Assembler::vextractf32x4(dst, src, 1);
1418 } else {
1419 Assembler::vextractf128(dst, src, 1);
1420 }
1421 }
1422
1423 void vextractf128_high(Address dst, XMMRegister src) {
1424 if (UseAVX > 2) {
1425 Assembler::vextractf32x4(dst, src, 1);
1426 } else {
1427 Assembler::vextractf128(dst, src, 1);
1428 }
1429 }
1430
1431 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1432 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1433 Assembler::vinserti64x4(dst, dst, src, 1);
1434 }
1435 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1436 Assembler::vinsertf64x4(dst, dst, src, 1);
1437 }
1438 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1439 Assembler::vextracti64x4(dst, src, 1);
1440 }
1441 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1442 Assembler::vextractf64x4(dst, src, 1);
1443 }
1444 void vextractf64x4_high(Address dst, XMMRegister src) {
1445 Assembler::vextractf64x4(dst, src, 1);
1446 }
1447 void vinsertf64x4_high(XMMRegister dst, Address src) {
1448 Assembler::vinsertf64x4(dst, dst, src, 1);
1449 }
1450
1451 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1452 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1453 vinserti128(dst, dst, src, 0);
1454 }
1455 void vinserti128_low(XMMRegister dst, Address src) {
1456 vinserti128(dst, dst, src, 0);
1457 }
1458 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1459 vextracti128(dst, src, 0);
1460 }
1461 void vextracti128_low(Address dst, XMMRegister src) {
1462 vextracti128(dst, src, 0);
1463 }
1464
1465 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1466 if (UseAVX > 2) {
1467 Assembler::vinsertf32x4(dst, dst, src, 0);
1468 } else {
1469 Assembler::vinsertf128(dst, dst, src, 0);
1470 }
1471 }
1472
1473 void vinsertf128_low(XMMRegister dst, Address src) {
1474 if (UseAVX > 2) {
1475 Assembler::vinsertf32x4(dst, dst, src, 0);
1476 } else {
1477 Assembler::vinsertf128(dst, dst, src, 0);
1478 }
1479 }
1480
1481 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1482 if (UseAVX > 2) {
1483 Assembler::vextractf32x4(dst, src, 0);
1484 } else {
1485 Assembler::vextractf128(dst, src, 0);
1486 }
1487 }
1488
1489 void vextractf128_low(Address dst, XMMRegister src) {
1490 if (UseAVX > 2) {
1491 Assembler::vextractf32x4(dst, src, 0);
1492 } else {
1493 Assembler::vextractf128(dst, src, 0);
1494 }
1495 }
1496
1497 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1498 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1499 Assembler::vinserti64x4(dst, dst, src, 0);
1500 }
1501 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1502 Assembler::vinsertf64x4(dst, dst, src, 0);
1503 }
1504 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1505 Assembler::vextracti64x4(dst, src, 0);
1506 }
1507 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1508 Assembler::vextractf64x4(dst, src, 0);
1509 }
1510 void vextractf64x4_low(Address dst, XMMRegister src) {
1511 Assembler::vextractf64x4(dst, src, 0);
1512 }
1513 void vinsertf64x4_low(XMMRegister dst, Address src) {
1514 Assembler::vinsertf64x4(dst, dst, src, 0);
1515 }
1516
1517 // Carry-Less Multiplication Quadword
1518 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1519 // 0x00 - multiply lower 64 bits [0:63]
1520 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1521 }
1522 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1523 // 0x11 - multiply upper 64 bits [64:127]
1524 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1525 }
1526
1527 // Data
1528
1529 void cmov32( Condition cc, Register dst, Address src);
1530 void cmov32( Condition cc, Register dst, Register src);
1531
1532 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1533
1534 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1535 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1536
1537 void movoop(Register dst, jobject obj);
1538 void movoop(Address dst, jobject obj);
1539
1540 void mov_metadata(Register dst, Metadata* obj);
1541 void mov_metadata(Address dst, Metadata* obj);
1542
1543 void movptr(ArrayAddress dst, Register src);
1544 // can this do an lea?
1545 void movptr(Register dst, ArrayAddress src);
1546
1547 void movptr(Register dst, Address src);
1548
1549 #ifdef _LP64
1550 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1551 #else
1552 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1553 #endif
1554
1555 void movptr(Register dst, intptr_t src);
1556 void movptr(Register dst, Register src);
1557 void movptr(Address dst, intptr_t src);
1558
1559 void movptr(Address dst, Register src);
1560
1561 void movptr(Register dst, RegisterOrConstant src) {
1562 if (src.is_constant()) movptr(dst, src.as_constant());
1563 else movptr(dst, src.as_register());
1564 }
1565
1566 #ifdef _LP64
1567 // Generally the next two are only used for moving NULL
1568 // Although there are situations in initializing the mark word where
1569 // they could be used. They are dangerous.
1570
1571 // They only exist on LP64 so that int32_t and intptr_t are not the same
1572 // and we have ambiguous declarations.
1573
1574 void movptr(Address dst, int32_t imm32);
1575 void movptr(Register dst, int32_t imm32);
1576 #endif // _LP64
1577
1578 // to avoid hiding movl
1579 void mov32(AddressLiteral dst, Register src);
1580 void mov32(Register dst, AddressLiteral src);
1581
1582 // to avoid hiding movb
1583 void movbyte(ArrayAddress dst, int src);
1584
1585 // Import other mov() methods from the parent class or else
1586 // they will be hidden by the following overriding declaration.
1587 using Assembler::movdl;
1588 using Assembler::movq;
1589 void movdl(XMMRegister dst, AddressLiteral src);
1590 void movq(XMMRegister dst, AddressLiteral src);
1591
1592 // Can push value or effective address
1593 void pushptr(AddressLiteral src);
1594
1595 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1596 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1597
1598 void pushoop(jobject obj);
1599 void pushklass(Metadata* obj);
1600
1601 // sign extend as need a l to ptr sized element
1602 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1603 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1604
1605 // C2 compiled method's prolog code.
1606 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1607
1608 // clear memory of size 'cnt' qwords, starting at 'base';
1609 // if 'is_large' is set, do not try to produce short loop
1610 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1611
1612 #ifdef COMPILER2
1613 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1614 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1615
1616 // IndexOf strings.
1617 // Small strings are loaded through stack if they cross page boundary.
1618 void string_indexof(Register str1, Register str2,
1619 Register cnt1, Register cnt2,
1620 int int_cnt2, Register result,
1621 XMMRegister vec, Register tmp,
1622 int ae);
1623
1624 // IndexOf for constant substrings with size >= 8 elements
1625 // which don't need to be loaded through stack.
1626 void string_indexofC8(Register str1, Register str2,
1627 Register cnt1, Register cnt2,
1628 int int_cnt2, Register result,
1629 XMMRegister vec, Register tmp,
1630 int ae);
1631
1632 // Smallest code: we don't need to load through stack,
1633 // check string tail.
1634
1635 // helper function for string_compare
1636 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1637 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1638 Address::ScaleFactor scale2, Register index, int ae);
1639 // Compare strings.
1640 void string_compare(Register str1, Register str2,
1641 Register cnt1, Register cnt2, Register result,
1642 XMMRegister vec1, int ae);
1643
1644 // Search for Non-ASCII character (Negative byte value) in a byte array,
1645 // return true if it has any and false otherwise.
1646 void has_negatives(Register ary1, Register len,
1647 Register result, Register tmp1,
1648 XMMRegister vec1, XMMRegister vec2);
1649
1650 // Compare char[] or byte[] arrays.
1651 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1652 Register limit, Register result, Register chr,
1653 XMMRegister vec1, XMMRegister vec2, bool is_char);
1654
1655 #endif
1656
1657 // Fill primitive arrays
1658 void generate_fill(BasicType t, bool aligned,
1659 Register to, Register value, Register count,
1660 Register rtmp, XMMRegister xtmp);
1661
1662 void encode_iso_array(Register src, Register dst, Register len,
1663 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1664 XMMRegister tmp4, Register tmp5, Register result);
1665
1666 #ifdef _LP64
1667 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1668 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1669 Register y, Register y_idx, Register z,
1670 Register carry, Register product,
1671 Register idx, Register kdx);
1672 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1673 Register yz_idx, Register idx,
1674 Register carry, Register product, int offset);
1675 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1676 Register carry, Register carry2,
1677 Register idx, Register jdx,
1678 Register yz_idx1, Register yz_idx2,
1679 Register tmp, Register tmp3, Register tmp4);
1680 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1681 Register yz_idx, Register idx, Register jdx,
1682 Register carry, Register product,
1683 Register carry2);
1684 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1685 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1686 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1687 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1688 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1689 Register tmp2);
1690 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1691 Register rdxReg, Register raxReg);
1692 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1693 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1694 Register tmp3, Register tmp4);
1695 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1696 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1697
1698 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1699 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1700 Register raxReg);
1701 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1702 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1703 Register raxReg);
1704 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1705 Register result, Register tmp1, Register tmp2,
1706 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1707 #endif
1708
1709 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1710 void update_byte_crc32(Register crc, Register val, Register table);
1711 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1712 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1713 // Note on a naming convention:
1714 // Prefix w = register only used on a Westmere+ architecture
1715 // Prefix n = register only used on a Nehalem architecture
1716 #ifdef _LP64
1717 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1718 Register tmp1, Register tmp2, Register tmp3);
1719 #else
1720 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1721 Register tmp1, Register tmp2, Register tmp3,
1722 XMMRegister xtmp1, XMMRegister xtmp2);
1723 #endif
1724 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1725 Register in_out,
1726 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1727 XMMRegister w_xtmp2,
1728 Register tmp1,
1729 Register n_tmp2, Register n_tmp3);
1730 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1731 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1732 Register tmp1, Register tmp2,
1733 Register n_tmp3);
1734 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1735 Register in_out1, Register in_out2, Register in_out3,
1736 Register tmp1, Register tmp2, Register tmp3,
1737 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1738 Register tmp4, Register tmp5,
1739 Register n_tmp6);
1740 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1741 Register tmp1, Register tmp2, Register tmp3,
1742 Register tmp4, Register tmp5, Register tmp6,
1743 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1744 bool is_pclmulqdq_supported);
1745 // Fold 128-bit data chunk
1746 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1747 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1748 // Fold 8-bit data
1749 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1750 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1751
1752 // Compress char[] array to byte[].
1753 void char_array_compress(Register src, Register dst, Register len,
1754 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1755 XMMRegister tmp4, Register tmp5, Register result);
1756
1757 // Inflate byte[] array to char[].
1758 void byte_array_inflate(Register src, Register dst, Register len,
1759 XMMRegister tmp1, Register tmp2);
1760
1761
1762 void save_vector_registers();
1763 void restore_vector_registers();
1764 };
1765
1766 /**
1767 * class SkipIfEqual:
1768 *
1769 * Instantiating this class will result in assembly code being output that will
1770 * jump around any code emitted between the creation of the instance and it's
1771 * automatic destruction at the end of a scope block, depending on the value of
1772 * the flag passed to the constructor, which will be checked at run-time.
1773 */
1774 class SkipIfEqual {
1775 private:
1776 MacroAssembler* _masm;
1777 Label _label;
1778
1779 public:
1780 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1781 ~SkipIfEqual();
1782 };
1783
1784 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP