1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 756 // we must set sp to zero to clear frame 757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 758 // must clear fp, so that compiled frames are not confused; it is 759 // possible that we need it only for debugging 760 if (clear_fp) { 761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 762 } 763 764 // Always clear the pc because it could have been set by make_walkable() 765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 766 } 767 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 769 Register last_java_fp, 770 address last_java_pc) { 771 // determine last_java_sp register 772 if (!last_java_sp->is_valid()) { 773 last_java_sp = rsp; 774 } 775 776 // last_java_fp is optional 777 if (last_java_fp->is_valid()) { 778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 779 last_java_fp); 780 } 781 782 // last_java_pc is optional 783 if (last_java_pc != NULL) { 784 Address java_pc(r15_thread, 785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 786 lea(rscratch1, InternalAddress(last_java_pc)); 787 movptr(java_pc, rscratch1); 788 } 789 790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 791 } 792 793 static void pass_arg0(MacroAssembler* masm, Register arg) { 794 if (c_rarg0 != arg ) { 795 masm->mov(c_rarg0, arg); 796 } 797 } 798 799 static void pass_arg1(MacroAssembler* masm, Register arg) { 800 if (c_rarg1 != arg ) { 801 masm->mov(c_rarg1, arg); 802 } 803 } 804 805 static void pass_arg2(MacroAssembler* masm, Register arg) { 806 if (c_rarg2 != arg ) { 807 masm->mov(c_rarg2, arg); 808 } 809 } 810 811 static void pass_arg3(MacroAssembler* masm, Register arg) { 812 if (c_rarg3 != arg ) { 813 masm->mov(c_rarg3, arg); 814 } 815 } 816 817 void MacroAssembler::stop(const char* msg) { 818 address rip = pc(); 819 pusha(); // get regs on stack 820 lea(c_rarg0, ExternalAddress((address) msg)); 821 lea(c_rarg1, InternalAddress(rip)); 822 movq(c_rarg2, rsp); // pass pointer to regs array 823 andq(rsp, -16); // align stack as required by ABI 824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 825 hlt(); 826 } 827 828 void MacroAssembler::warn(const char* msg) { 829 push(rbp); 830 movq(rbp, rsp); 831 andq(rsp, -16); // align stack as required by push_CPU_state and call 832 push_CPU_state(); // keeps alignment at 16 bytes 833 lea(c_rarg0, ExternalAddress((address) msg)); 834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 835 pop_CPU_state(); 836 mov(rsp, rbp); 837 pop(rbp); 838 } 839 840 void MacroAssembler::print_state() { 841 address rip = pc(); 842 pusha(); // get regs on stack 843 push(rbp); 844 movq(rbp, rsp); 845 andq(rsp, -16); // align stack as required by push_CPU_state and call 846 push_CPU_state(); // keeps alignment at 16 bytes 847 848 lea(c_rarg0, InternalAddress(rip)); 849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 851 852 pop_CPU_state(); 853 mov(rsp, rbp); 854 pop(rbp); 855 popa(); 856 } 857 858 #ifndef PRODUCT 859 extern "C" void findpc(intptr_t x); 860 #endif 861 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 863 // In order to get locks to work, we need to fake a in_VM state 864 if (ShowMessageBoxOnError) { 865 JavaThread* thread = JavaThread::current(); 866 JavaThreadState saved_state = thread->thread_state(); 867 thread->set_thread_state(_thread_in_vm); 868 #ifndef PRODUCT 869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 870 ttyLocker ttyl; 871 BytecodeCounter::print(); 872 } 873 #endif 874 // To see where a verify_oop failed, get $ebx+40/X for this frame. 875 // XXX correct this offset for amd64 876 // This is the value of eip which points to where verify_oop will return. 877 if (os::message_box(msg, "Execution stopped, print registers?")) { 878 print_state64(pc, regs); 879 BREAKPOINT; 880 assert(false, "start up GDB"); 881 } 882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 883 } else { 884 ttyLocker ttyl; 885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 886 msg); 887 assert(false, "DEBUG MESSAGE: %s", msg); 888 } 889 } 890 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 892 ttyLocker ttyl; 893 FlagSetting fs(Debugging, true); 894 tty->print_cr("rip = 0x%016lx", pc); 895 #ifndef PRODUCT 896 tty->cr(); 897 findpc(pc); 898 tty->cr(); 899 #endif 900 #define PRINT_REG(rax, value) \ 901 { tty->print("%s = ", #rax); os::print_location(tty, value); } 902 PRINT_REG(rax, regs[15]); 903 PRINT_REG(rbx, regs[12]); 904 PRINT_REG(rcx, regs[14]); 905 PRINT_REG(rdx, regs[13]); 906 PRINT_REG(rdi, regs[8]); 907 PRINT_REG(rsi, regs[9]); 908 PRINT_REG(rbp, regs[10]); 909 PRINT_REG(rsp, regs[11]); 910 PRINT_REG(r8 , regs[7]); 911 PRINT_REG(r9 , regs[6]); 912 PRINT_REG(r10, regs[5]); 913 PRINT_REG(r11, regs[4]); 914 PRINT_REG(r12, regs[3]); 915 PRINT_REG(r13, regs[2]); 916 PRINT_REG(r14, regs[1]); 917 PRINT_REG(r15, regs[0]); 918 #undef PRINT_REG 919 // Print some words near top of staack. 920 int64_t* rsp = (int64_t*) regs[11]; 921 int64_t* dump_sp = rsp; 922 for (int col1 = 0; col1 < 8; col1++) { 923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 924 os::print_location(tty, *dump_sp++); 925 } 926 for (int row = 0; row < 25; row++) { 927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 928 for (int col = 0; col < 4; col++) { 929 tty->print(" 0x%016lx", *dump_sp++); 930 } 931 tty->cr(); 932 } 933 // Print some instructions around pc: 934 Disassembler::decode((address)pc-64, (address)pc); 935 tty->print_cr("--------"); 936 Disassembler::decode((address)pc, (address)pc+32); 937 } 938 939 #endif // _LP64 940 941 // Now versions that are common to 32/64 bit 942 943 void MacroAssembler::addptr(Register dst, int32_t imm32) { 944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 945 } 946 947 void MacroAssembler::addptr(Register dst, Register src) { 948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 949 } 950 951 void MacroAssembler::addptr(Address dst, Register src) { 952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 953 } 954 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 956 if (reachable(src)) { 957 Assembler::addsd(dst, as_Address(src)); 958 } else { 959 lea(rscratch1, src); 960 Assembler::addsd(dst, Address(rscratch1, 0)); 961 } 962 } 963 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 965 if (reachable(src)) { 966 addss(dst, as_Address(src)); 967 } else { 968 lea(rscratch1, src); 969 addss(dst, Address(rscratch1, 0)); 970 } 971 } 972 973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 974 if (reachable(src)) { 975 Assembler::addpd(dst, as_Address(src)); 976 } else { 977 lea(rscratch1, src); 978 Assembler::addpd(dst, Address(rscratch1, 0)); 979 } 980 } 981 982 void MacroAssembler::align(int modulus) { 983 align(modulus, offset()); 984 } 985 986 void MacroAssembler::align(int modulus, int target) { 987 if (target % modulus != 0) { 988 nop(modulus - (target % modulus)); 989 } 990 } 991 992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 993 // Used in sign-masking with aligned address. 994 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 995 if (reachable(src)) { 996 Assembler::andpd(dst, as_Address(src)); 997 } else { 998 lea(rscratch1, src); 999 Assembler::andpd(dst, Address(rscratch1, 0)); 1000 } 1001 } 1002 1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1004 // Used in sign-masking with aligned address. 1005 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1006 if (reachable(src)) { 1007 Assembler::andps(dst, as_Address(src)); 1008 } else { 1009 lea(rscratch1, src); 1010 Assembler::andps(dst, Address(rscratch1, 0)); 1011 } 1012 } 1013 1014 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1015 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1016 } 1017 1018 void MacroAssembler::atomic_incl(Address counter_addr) { 1019 if (os::is_MP()) 1020 lock(); 1021 incrementl(counter_addr); 1022 } 1023 1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1025 if (reachable(counter_addr)) { 1026 atomic_incl(as_Address(counter_addr)); 1027 } else { 1028 lea(scr, counter_addr); 1029 atomic_incl(Address(scr, 0)); 1030 } 1031 } 1032 1033 #ifdef _LP64 1034 void MacroAssembler::atomic_incq(Address counter_addr) { 1035 if (os::is_MP()) 1036 lock(); 1037 incrementq(counter_addr); 1038 } 1039 1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1041 if (reachable(counter_addr)) { 1042 atomic_incq(as_Address(counter_addr)); 1043 } else { 1044 lea(scr, counter_addr); 1045 atomic_incq(Address(scr, 0)); 1046 } 1047 } 1048 #endif 1049 1050 // Writes to stack successive pages until offset reached to check for 1051 // stack overflow + shadow pages. This clobbers tmp. 1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1053 movptr(tmp, rsp); 1054 // Bang stack for total size given plus shadow page size. 1055 // Bang one page at a time because large size can bang beyond yellow and 1056 // red zones. 1057 Label loop; 1058 bind(loop); 1059 movl(Address(tmp, (-os::vm_page_size())), size ); 1060 subptr(tmp, os::vm_page_size()); 1061 subl(size, os::vm_page_size()); 1062 jcc(Assembler::greater, loop); 1063 1064 // Bang down shadow pages too. 1065 // At this point, (tmp-0) is the last address touched, so don't 1066 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1067 // was post-decremented.) Skip this address by starting at i=1, and 1068 // touch a few more pages below. N.B. It is important to touch all 1069 // the way down including all pages in the shadow zone. 1070 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1071 // this could be any sized move but this is can be a debugging crumb 1072 // so the bigger the better. 1073 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1074 } 1075 } 1076 1077 void MacroAssembler::reserved_stack_check() { 1078 // testing if reserved zone needs to be enabled 1079 Label no_reserved_zone_enabling; 1080 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1081 NOT_LP64(get_thread(rsi);) 1082 1083 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1084 jcc(Assembler::below, no_reserved_zone_enabling); 1085 1086 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1087 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1088 should_not_reach_here(); 1089 1090 bind(no_reserved_zone_enabling); 1091 } 1092 1093 int MacroAssembler::biased_locking_enter(Register lock_reg, 1094 Register obj_reg, 1095 Register swap_reg, 1096 Register tmp_reg, 1097 bool swap_reg_contains_mark, 1098 Label& done, 1099 Label* slow_case, 1100 BiasedLockingCounters* counters) { 1101 assert(UseBiasedLocking, "why call this otherwise?"); 1102 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1103 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1104 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1105 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1106 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1107 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1108 1109 if (PrintBiasedLockingStatistics && counters == NULL) { 1110 counters = BiasedLocking::counters(); 1111 } 1112 // Biased locking 1113 // See whether the lock is currently biased toward our thread and 1114 // whether the epoch is still valid 1115 // Note that the runtime guarantees sufficient alignment of JavaThread 1116 // pointers to allow age to be placed into low bits 1117 // First check to see whether biasing is even enabled for this object 1118 Label cas_label; 1119 int null_check_offset = -1; 1120 if (!swap_reg_contains_mark) { 1121 null_check_offset = offset(); 1122 movptr(swap_reg, mark_addr); 1123 } 1124 movptr(tmp_reg, swap_reg); 1125 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1126 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1127 jcc(Assembler::notEqual, cas_label); 1128 // The bias pattern is present in the object's header. Need to check 1129 // whether the bias owner and the epoch are both still current. 1130 #ifndef _LP64 1131 // Note that because there is no current thread register on x86_32 we 1132 // need to store off the mark word we read out of the object to 1133 // avoid reloading it and needing to recheck invariants below. This 1134 // store is unfortunate but it makes the overall code shorter and 1135 // simpler. 1136 movptr(saved_mark_addr, swap_reg); 1137 #endif 1138 if (swap_reg_contains_mark) { 1139 null_check_offset = offset(); 1140 } 1141 load_prototype_header(tmp_reg, obj_reg); 1142 #ifdef _LP64 1143 orptr(tmp_reg, r15_thread); 1144 xorptr(tmp_reg, swap_reg); 1145 Register header_reg = tmp_reg; 1146 #else 1147 xorptr(tmp_reg, swap_reg); 1148 get_thread(swap_reg); 1149 xorptr(swap_reg, tmp_reg); 1150 Register header_reg = swap_reg; 1151 #endif 1152 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1153 if (counters != NULL) { 1154 cond_inc32(Assembler::zero, 1155 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1156 } 1157 jcc(Assembler::equal, done); 1158 1159 Label try_revoke_bias; 1160 Label try_rebias; 1161 1162 // At this point we know that the header has the bias pattern and 1163 // that we are not the bias owner in the current epoch. We need to 1164 // figure out more details about the state of the header in order to 1165 // know what operations can be legally performed on the object's 1166 // header. 1167 1168 // If the low three bits in the xor result aren't clear, that means 1169 // the prototype header is no longer biased and we have to revoke 1170 // the bias on this object. 1171 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1172 jccb(Assembler::notZero, try_revoke_bias); 1173 1174 // Biasing is still enabled for this data type. See whether the 1175 // epoch of the current bias is still valid, meaning that the epoch 1176 // bits of the mark word are equal to the epoch bits of the 1177 // prototype header. (Note that the prototype header's epoch bits 1178 // only change at a safepoint.) If not, attempt to rebias the object 1179 // toward the current thread. Note that we must be absolutely sure 1180 // that the current epoch is invalid in order to do this because 1181 // otherwise the manipulations it performs on the mark word are 1182 // illegal. 1183 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1184 jccb(Assembler::notZero, try_rebias); 1185 1186 // The epoch of the current bias is still valid but we know nothing 1187 // about the owner; it might be set or it might be clear. Try to 1188 // acquire the bias of the object using an atomic operation. If this 1189 // fails we will go in to the runtime to revoke the object's bias. 1190 // Note that we first construct the presumed unbiased header so we 1191 // don't accidentally blow away another thread's valid bias. 1192 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1193 andptr(swap_reg, 1194 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1195 #ifdef _LP64 1196 movptr(tmp_reg, swap_reg); 1197 orptr(tmp_reg, r15_thread); 1198 #else 1199 get_thread(tmp_reg); 1200 orptr(tmp_reg, swap_reg); 1201 #endif 1202 if (os::is_MP()) { 1203 lock(); 1204 } 1205 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1206 // If the biasing toward our thread failed, this means that 1207 // another thread succeeded in biasing it toward itself and we 1208 // need to revoke that bias. The revocation will occur in the 1209 // interpreter runtime in the slow case. 1210 if (counters != NULL) { 1211 cond_inc32(Assembler::zero, 1212 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1213 } 1214 if (slow_case != NULL) { 1215 jcc(Assembler::notZero, *slow_case); 1216 } 1217 jmp(done); 1218 1219 bind(try_rebias); 1220 // At this point we know the epoch has expired, meaning that the 1221 // current "bias owner", if any, is actually invalid. Under these 1222 // circumstances _only_, we are allowed to use the current header's 1223 // value as the comparison value when doing the cas to acquire the 1224 // bias in the current epoch. In other words, we allow transfer of 1225 // the bias from one thread to another directly in this situation. 1226 // 1227 // FIXME: due to a lack of registers we currently blow away the age 1228 // bits in this situation. Should attempt to preserve them. 1229 load_prototype_header(tmp_reg, obj_reg); 1230 #ifdef _LP64 1231 orptr(tmp_reg, r15_thread); 1232 #else 1233 get_thread(swap_reg); 1234 orptr(tmp_reg, swap_reg); 1235 movptr(swap_reg, saved_mark_addr); 1236 #endif 1237 if (os::is_MP()) { 1238 lock(); 1239 } 1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1241 // If the biasing toward our thread failed, then another thread 1242 // succeeded in biasing it toward itself and we need to revoke that 1243 // bias. The revocation will occur in the runtime in the slow case. 1244 if (counters != NULL) { 1245 cond_inc32(Assembler::zero, 1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1247 } 1248 if (slow_case != NULL) { 1249 jcc(Assembler::notZero, *slow_case); 1250 } 1251 jmp(done); 1252 1253 bind(try_revoke_bias); 1254 // The prototype mark in the klass doesn't have the bias bit set any 1255 // more, indicating that objects of this data type are not supposed 1256 // to be biased any more. We are going to try to reset the mark of 1257 // this object to the prototype value and fall through to the 1258 // CAS-based locking scheme. Note that if our CAS fails, it means 1259 // that another thread raced us for the privilege of revoking the 1260 // bias of this particular object, so it's okay to continue in the 1261 // normal locking code. 1262 // 1263 // FIXME: due to a lack of registers we currently blow away the age 1264 // bits in this situation. Should attempt to preserve them. 1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1266 load_prototype_header(tmp_reg, obj_reg); 1267 if (os::is_MP()) { 1268 lock(); 1269 } 1270 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1271 // Fall through to the normal CAS-based lock, because no matter what 1272 // the result of the above CAS, some thread must have succeeded in 1273 // removing the bias bit from the object's header. 1274 if (counters != NULL) { 1275 cond_inc32(Assembler::zero, 1276 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1277 } 1278 1279 bind(cas_label); 1280 1281 return null_check_offset; 1282 } 1283 1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1285 assert(UseBiasedLocking, "why call this otherwise?"); 1286 1287 // Check for biased locking unlock case, which is a no-op 1288 // Note: we do not have to check the thread ID for two reasons. 1289 // First, the interpreter checks for IllegalMonitorStateException at 1290 // a higher level. Second, if the bias was revoked while we held the 1291 // lock, the object could not be rebiased toward another thread, so 1292 // the bias bit would be clear. 1293 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1294 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1295 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1296 jcc(Assembler::equal, done); 1297 } 1298 1299 #ifdef COMPILER2 1300 1301 #if INCLUDE_RTM_OPT 1302 1303 // Update rtm_counters based on abort status 1304 // input: abort_status 1305 // rtm_counters (RTMLockingCounters*) 1306 // flags are killed 1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1308 1309 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1310 if (PrintPreciseRTMLockingStatistics) { 1311 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1312 Label check_abort; 1313 testl(abort_status, (1<<i)); 1314 jccb(Assembler::equal, check_abort); 1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1316 bind(check_abort); 1317 } 1318 } 1319 } 1320 1321 // Branch if (random & (count-1) != 0), count is 2^n 1322 // tmp, scr and flags are killed 1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1324 assert(tmp == rax, ""); 1325 assert(scr == rdx, ""); 1326 rdtsc(); // modifies EDX:EAX 1327 andptr(tmp, count-1); 1328 jccb(Assembler::notZero, brLabel); 1329 } 1330 1331 // Perform abort ratio calculation, set no_rtm bit if high ratio 1332 // input: rtm_counters_Reg (RTMLockingCounters* address) 1333 // tmpReg, rtm_counters_Reg and flags are killed 1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1335 Register rtm_counters_Reg, 1336 RTMLockingCounters* rtm_counters, 1337 Metadata* method_data) { 1338 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1339 1340 if (RTMLockingCalculationDelay > 0) { 1341 // Delay calculation 1342 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1343 testptr(tmpReg, tmpReg); 1344 jccb(Assembler::equal, L_done); 1345 } 1346 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1347 // Aborted transactions = abort_count * 100 1348 // All transactions = total_count * RTMTotalCountIncrRate 1349 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1350 1351 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1352 cmpptr(tmpReg, RTMAbortThreshold); 1353 jccb(Assembler::below, L_check_always_rtm2); 1354 imulptr(tmpReg, tmpReg, 100); 1355 1356 Register scrReg = rtm_counters_Reg; 1357 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1358 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1359 imulptr(scrReg, scrReg, RTMAbortRatio); 1360 cmpptr(tmpReg, scrReg); 1361 jccb(Assembler::below, L_check_always_rtm1); 1362 if (method_data != NULL) { 1363 // set rtm_state to "no rtm" in MDO 1364 mov_metadata(tmpReg, method_data); 1365 if (os::is_MP()) { 1366 lock(); 1367 } 1368 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1369 } 1370 jmpb(L_done); 1371 bind(L_check_always_rtm1); 1372 // Reload RTMLockingCounters* address 1373 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1374 bind(L_check_always_rtm2); 1375 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1376 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1377 jccb(Assembler::below, L_done); 1378 if (method_data != NULL) { 1379 // set rtm_state to "always rtm" in MDO 1380 mov_metadata(tmpReg, method_data); 1381 if (os::is_MP()) { 1382 lock(); 1383 } 1384 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1385 } 1386 bind(L_done); 1387 } 1388 1389 // Update counters and perform abort ratio calculation 1390 // input: abort_status_Reg 1391 // rtm_counters_Reg, flags are killed 1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1393 Register rtm_counters_Reg, 1394 RTMLockingCounters* rtm_counters, 1395 Metadata* method_data, 1396 bool profile_rtm) { 1397 1398 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1399 // update rtm counters based on rax value at abort 1400 // reads abort_status_Reg, updates flags 1401 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1402 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1403 if (profile_rtm) { 1404 // Save abort status because abort_status_Reg is used by following code. 1405 if (RTMRetryCount > 0) { 1406 push(abort_status_Reg); 1407 } 1408 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1409 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1410 // restore abort status 1411 if (RTMRetryCount > 0) { 1412 pop(abort_status_Reg); 1413 } 1414 } 1415 } 1416 1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1418 // inputs: retry_count_Reg 1419 // : abort_status_Reg 1420 // output: retry_count_Reg decremented by 1 1421 // flags are killed 1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1423 Label doneRetry; 1424 assert(abort_status_Reg == rax, ""); 1425 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1426 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1427 // if reason is in 0x6 and retry count != 0 then retry 1428 andptr(abort_status_Reg, 0x6); 1429 jccb(Assembler::zero, doneRetry); 1430 testl(retry_count_Reg, retry_count_Reg); 1431 jccb(Assembler::zero, doneRetry); 1432 pause(); 1433 decrementl(retry_count_Reg); 1434 jmp(retryLabel); 1435 bind(doneRetry); 1436 } 1437 1438 // Spin and retry if lock is busy, 1439 // inputs: box_Reg (monitor address) 1440 // : retry_count_Reg 1441 // output: retry_count_Reg decremented by 1 1442 // : clear z flag if retry count exceeded 1443 // tmp_Reg, scr_Reg, flags are killed 1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1445 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1446 Label SpinLoop, SpinExit, doneRetry; 1447 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1448 1449 testl(retry_count_Reg, retry_count_Reg); 1450 jccb(Assembler::zero, doneRetry); 1451 decrementl(retry_count_Reg); 1452 movptr(scr_Reg, RTMSpinLoopCount); 1453 1454 bind(SpinLoop); 1455 pause(); 1456 decrementl(scr_Reg); 1457 jccb(Assembler::lessEqual, SpinExit); 1458 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1459 testptr(tmp_Reg, tmp_Reg); 1460 jccb(Assembler::notZero, SpinLoop); 1461 1462 bind(SpinExit); 1463 jmp(retryLabel); 1464 bind(doneRetry); 1465 incrementl(retry_count_Reg); // clear z flag 1466 } 1467 1468 // Use RTM for normal stack locks 1469 // Input: objReg (object to lock) 1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1471 Register retry_on_abort_count_Reg, 1472 RTMLockingCounters* stack_rtm_counters, 1473 Metadata* method_data, bool profile_rtm, 1474 Label& DONE_LABEL, Label& IsInflated) { 1475 assert(UseRTMForStackLocks, "why call this otherwise?"); 1476 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1477 assert(tmpReg == rax, ""); 1478 assert(scrReg == rdx, ""); 1479 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1480 1481 if (RTMRetryCount > 0) { 1482 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1483 bind(L_rtm_retry); 1484 } 1485 movptr(tmpReg, Address(objReg, 0)); 1486 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1487 jcc(Assembler::notZero, IsInflated); 1488 1489 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1490 Label L_noincrement; 1491 if (RTMTotalCountIncrRate > 1) { 1492 // tmpReg, scrReg and flags are killed 1493 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1494 } 1495 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1496 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1497 bind(L_noincrement); 1498 } 1499 xbegin(L_on_abort); 1500 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1501 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1502 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1503 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1504 1505 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1506 if (UseRTMXendForLockBusy) { 1507 xend(); 1508 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1509 jmp(L_decrement_retry); 1510 } 1511 else { 1512 xabort(0); 1513 } 1514 bind(L_on_abort); 1515 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1516 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1517 } 1518 bind(L_decrement_retry); 1519 if (RTMRetryCount > 0) { 1520 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1521 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1522 } 1523 } 1524 1525 // Use RTM for inflating locks 1526 // inputs: objReg (object to lock) 1527 // boxReg (on-stack box address (displaced header location) - KILLED) 1528 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1530 Register scrReg, Register retry_on_busy_count_Reg, 1531 Register retry_on_abort_count_Reg, 1532 RTMLockingCounters* rtm_counters, 1533 Metadata* method_data, bool profile_rtm, 1534 Label& DONE_LABEL) { 1535 assert(UseRTMLocking, "why call this otherwise?"); 1536 assert(tmpReg == rax, ""); 1537 assert(scrReg == rdx, ""); 1538 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1539 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1540 1541 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1542 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1543 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1544 1545 if (RTMRetryCount > 0) { 1546 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1547 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1548 bind(L_rtm_retry); 1549 } 1550 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1551 Label L_noincrement; 1552 if (RTMTotalCountIncrRate > 1) { 1553 // tmpReg, scrReg and flags are killed 1554 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1555 } 1556 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1557 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1558 bind(L_noincrement); 1559 } 1560 xbegin(L_on_abort); 1561 movptr(tmpReg, Address(objReg, 0)); 1562 movptr(tmpReg, Address(tmpReg, owner_offset)); 1563 testptr(tmpReg, tmpReg); 1564 jcc(Assembler::zero, DONE_LABEL); 1565 if (UseRTMXendForLockBusy) { 1566 xend(); 1567 jmp(L_decrement_retry); 1568 } 1569 else { 1570 xabort(0); 1571 } 1572 bind(L_on_abort); 1573 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1574 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1575 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1576 } 1577 if (RTMRetryCount > 0) { 1578 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1579 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1580 } 1581 1582 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1583 testptr(tmpReg, tmpReg) ; 1584 jccb(Assembler::notZero, L_decrement_retry) ; 1585 1586 // Appears unlocked - try to swing _owner from null to non-null. 1587 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1588 #ifdef _LP64 1589 Register threadReg = r15_thread; 1590 #else 1591 get_thread(scrReg); 1592 Register threadReg = scrReg; 1593 #endif 1594 if (os::is_MP()) { 1595 lock(); 1596 } 1597 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1598 1599 if (RTMRetryCount > 0) { 1600 // success done else retry 1601 jccb(Assembler::equal, DONE_LABEL) ; 1602 bind(L_decrement_retry); 1603 // Spin and retry if lock is busy. 1604 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1605 } 1606 else { 1607 bind(L_decrement_retry); 1608 } 1609 } 1610 1611 #endif // INCLUDE_RTM_OPT 1612 1613 // Fast_Lock and Fast_Unlock used by C2 1614 1615 // Because the transitions from emitted code to the runtime 1616 // monitorenter/exit helper stubs are so slow it's critical that 1617 // we inline both the stack-locking fast-path and the inflated fast path. 1618 // 1619 // See also: cmpFastLock and cmpFastUnlock. 1620 // 1621 // What follows is a specialized inline transliteration of the code 1622 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1623 // another option would be to emit TrySlowEnter and TrySlowExit methods 1624 // at startup-time. These methods would accept arguments as 1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1626 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1628 // In practice, however, the # of lock sites is bounded and is usually small. 1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1630 // if the processor uses simple bimodal branch predictors keyed by EIP 1631 // Since the helper routines would be called from multiple synchronization 1632 // sites. 1633 // 1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1636 // to those specialized methods. That'd give us a mostly platform-independent 1637 // implementation that the JITs could optimize and inline at their pleasure. 1638 // Done correctly, the only time we'd need to cross to native could would be 1639 // to park() or unpark() threads. We'd also need a few more unsafe operators 1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1641 // (b) explicit barriers or fence operations. 1642 // 1643 // TODO: 1644 // 1645 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1646 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1647 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1648 // the lock operators would typically be faster than reifying Self. 1649 // 1650 // * Ideally I'd define the primitives as: 1651 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1652 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1653 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1654 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1655 // Furthermore the register assignments are overconstrained, possibly resulting in 1656 // sub-optimal code near the synchronization site. 1657 // 1658 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1659 // Alternately, use a better sp-proximity test. 1660 // 1661 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1662 // Either one is sufficient to uniquely identify a thread. 1663 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1664 // 1665 // * Intrinsify notify() and notifyAll() for the common cases where the 1666 // object is locked by the calling thread but the waitlist is empty. 1667 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1668 // 1669 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1670 // But beware of excessive branch density on AMD Opterons. 1671 // 1672 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1673 // or failure of the fast-path. If the fast-path fails then we pass 1674 // control to the slow-path, typically in C. In Fast_Lock and 1675 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1676 // will emit a conditional branch immediately after the node. 1677 // So we have branches to branches and lots of ICC.ZF games. 1678 // Instead, it might be better to have C2 pass a "FailureLabel" 1679 // into Fast_Lock and Fast_Unlock. In the case of success, control 1680 // will drop through the node. ICC.ZF is undefined at exit. 1681 // In the case of failure, the node will branch directly to the 1682 // FailureLabel 1683 1684 1685 // obj: object to lock 1686 // box: on-stack box address (displaced header location) - KILLED 1687 // rax,: tmp -- KILLED 1688 // scr: tmp -- KILLED 1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1690 Register scrReg, Register cx1Reg, Register cx2Reg, 1691 BiasedLockingCounters* counters, 1692 RTMLockingCounters* rtm_counters, 1693 RTMLockingCounters* stack_rtm_counters, 1694 Metadata* method_data, 1695 bool use_rtm, bool profile_rtm) { 1696 // Ensure the register assignments are disjoint 1697 assert(tmpReg == rax, ""); 1698 1699 if (use_rtm) { 1700 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1701 } else { 1702 assert(cx1Reg == noreg, ""); 1703 assert(cx2Reg == noreg, ""); 1704 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1705 } 1706 1707 if (counters != NULL) { 1708 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1709 } 1710 if (EmitSync & 1) { 1711 // set box->dhw = markOopDesc::unused_mark() 1712 // Force all sync thru slow-path: slow_enter() and slow_exit() 1713 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1714 cmpptr (rsp, (int32_t)NULL_WORD); 1715 } else { 1716 // Possible cases that we'll encounter in fast_lock 1717 // ------------------------------------------------ 1718 // * Inflated 1719 // -- unlocked 1720 // -- Locked 1721 // = by self 1722 // = by other 1723 // * biased 1724 // -- by Self 1725 // -- by other 1726 // * neutral 1727 // * stack-locked 1728 // -- by self 1729 // = sp-proximity test hits 1730 // = sp-proximity test generates false-negative 1731 // -- by other 1732 // 1733 1734 Label IsInflated, DONE_LABEL; 1735 1736 // it's stack-locked, biased or neutral 1737 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1738 // order to reduce the number of conditional branches in the most common cases. 1739 // Beware -- there's a subtle invariant that fetch of the markword 1740 // at [FETCH], below, will never observe a biased encoding (*101b). 1741 // If this invariant is not held we risk exclusion (safety) failure. 1742 if (UseBiasedLocking && !UseOptoBiasInlining) { 1743 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1744 } 1745 1746 #if INCLUDE_RTM_OPT 1747 if (UseRTMForStackLocks && use_rtm) { 1748 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1749 stack_rtm_counters, method_data, profile_rtm, 1750 DONE_LABEL, IsInflated); 1751 } 1752 #endif // INCLUDE_RTM_OPT 1753 1754 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1755 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1756 jccb(Assembler::notZero, IsInflated); 1757 1758 // Attempt stack-locking ... 1759 orptr (tmpReg, markOopDesc::unlocked_value); 1760 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1761 if (os::is_MP()) { 1762 lock(); 1763 } 1764 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1765 if (counters != NULL) { 1766 cond_inc32(Assembler::equal, 1767 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1768 } 1769 jcc(Assembler::equal, DONE_LABEL); // Success 1770 1771 // Recursive locking. 1772 // The object is stack-locked: markword contains stack pointer to BasicLock. 1773 // Locked by current thread if difference with current SP is less than one page. 1774 subptr(tmpReg, rsp); 1775 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1776 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1777 movptr(Address(boxReg, 0), tmpReg); 1778 if (counters != NULL) { 1779 cond_inc32(Assembler::equal, 1780 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1781 } 1782 jmp(DONE_LABEL); 1783 1784 bind(IsInflated); 1785 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1786 1787 #if INCLUDE_RTM_OPT 1788 // Use the same RTM locking code in 32- and 64-bit VM. 1789 if (use_rtm) { 1790 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1791 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1792 } else { 1793 #endif // INCLUDE_RTM_OPT 1794 1795 #ifndef _LP64 1796 // The object is inflated. 1797 1798 // boxReg refers to the on-stack BasicLock in the current frame. 1799 // We'd like to write: 1800 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1801 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1802 // additional latency as we have another ST in the store buffer that must drain. 1803 1804 if (EmitSync & 8192) { 1805 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1806 get_thread (scrReg); 1807 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1808 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1809 if (os::is_MP()) { 1810 lock(); 1811 } 1812 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1813 } else 1814 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1815 // register juggle because we need tmpReg for cmpxchgptr below 1816 movptr(scrReg, boxReg); 1817 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1818 1819 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1820 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1821 // prefetchw [eax + Offset(_owner)-2] 1822 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1823 } 1824 1825 if ((EmitSync & 64) == 0) { 1826 // Optimistic form: consider XORL tmpReg,tmpReg 1827 movptr(tmpReg, NULL_WORD); 1828 } else { 1829 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1830 // Test-And-CAS instead of CAS 1831 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1832 testptr(tmpReg, tmpReg); // Locked ? 1833 jccb (Assembler::notZero, DONE_LABEL); 1834 } 1835 1836 // Appears unlocked - try to swing _owner from null to non-null. 1837 // Ideally, I'd manifest "Self" with get_thread and then attempt 1838 // to CAS the register containing Self into m->Owner. 1839 // But we don't have enough registers, so instead we can either try to CAS 1840 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1841 // we later store "Self" into m->Owner. Transiently storing a stack address 1842 // (rsp or the address of the box) into m->owner is harmless. 1843 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1844 if (os::is_MP()) { 1845 lock(); 1846 } 1847 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1848 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1849 // If we weren't able to swing _owner from NULL to the BasicLock 1850 // then take the slow path. 1851 jccb (Assembler::notZero, DONE_LABEL); 1852 // update _owner from BasicLock to thread 1853 get_thread (scrReg); // beware: clobbers ICCs 1854 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1855 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1856 1857 // If the CAS fails we can either retry or pass control to the slow-path. 1858 // We use the latter tactic. 1859 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1860 // If the CAS was successful ... 1861 // Self has acquired the lock 1862 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1863 // Intentional fall-through into DONE_LABEL ... 1864 } else { 1865 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1866 movptr(boxReg, tmpReg); 1867 1868 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1869 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1870 // prefetchw [eax + Offset(_owner)-2] 1871 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1872 } 1873 1874 if ((EmitSync & 64) == 0) { 1875 // Optimistic form 1876 xorptr (tmpReg, tmpReg); 1877 } else { 1878 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1879 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1880 testptr(tmpReg, tmpReg); // Locked ? 1881 jccb (Assembler::notZero, DONE_LABEL); 1882 } 1883 1884 // Appears unlocked - try to swing _owner from null to non-null. 1885 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1887 get_thread (scrReg); 1888 if (os::is_MP()) { 1889 lock(); 1890 } 1891 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1892 1893 // If the CAS fails we can either retry or pass control to the slow-path. 1894 // We use the latter tactic. 1895 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1896 // If the CAS was successful ... 1897 // Self has acquired the lock 1898 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1899 // Intentional fall-through into DONE_LABEL ... 1900 } 1901 #else // _LP64 1902 // It's inflated 1903 movq(scrReg, tmpReg); 1904 xorq(tmpReg, tmpReg); 1905 1906 if (os::is_MP()) { 1907 lock(); 1908 } 1909 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1910 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1911 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1912 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1913 // Intentional fall-through into DONE_LABEL ... 1914 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1915 #endif // _LP64 1916 #if INCLUDE_RTM_OPT 1917 } // use_rtm() 1918 #endif 1919 // DONE_LABEL is a hot target - we'd really like to place it at the 1920 // start of cache line by padding with NOPs. 1921 // See the AMD and Intel software optimization manuals for the 1922 // most efficient "long" NOP encodings. 1923 // Unfortunately none of our alignment mechanisms suffice. 1924 bind(DONE_LABEL); 1925 1926 // At DONE_LABEL the icc ZFlag is set as follows ... 1927 // Fast_Unlock uses the same protocol. 1928 // ZFlag == 1 -> Success 1929 // ZFlag == 0 -> Failure - force control through the slow-path 1930 } 1931 } 1932 1933 // obj: object to unlock 1934 // box: box address (displaced header location), killed. Must be EAX. 1935 // tmp: killed, cannot be obj nor box. 1936 // 1937 // Some commentary on balanced locking: 1938 // 1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1940 // Methods that don't have provably balanced locking are forced to run in the 1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1942 // The interpreter provides two properties: 1943 // I1: At return-time the interpreter automatically and quietly unlocks any 1944 // objects acquired the current activation (frame). Recall that the 1945 // interpreter maintains an on-stack list of locks currently held by 1946 // a frame. 1947 // I2: If a method attempts to unlock an object that is not held by the 1948 // the frame the interpreter throws IMSX. 1949 // 1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1951 // B() doesn't have provably balanced locking so it runs in the interpreter. 1952 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1953 // is still locked by A(). 1954 // 1955 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1957 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1959 // Arguably given that the spec legislates the JNI case as undefined our implementation 1960 // could reasonably *avoid* checking owner in Fast_Unlock(). 1961 // In the interest of performance we elide m->Owner==Self check in unlock. 1962 // A perfectly viable alternative is to elide the owner check except when 1963 // Xcheck:jni is enabled. 1964 1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1966 assert(boxReg == rax, ""); 1967 assert_different_registers(objReg, boxReg, tmpReg); 1968 1969 if (EmitSync & 4) { 1970 // Disable - inhibit all inlining. Force control through the slow-path 1971 cmpptr (rsp, 0); 1972 } else { 1973 Label DONE_LABEL, Stacked, CheckSucc; 1974 1975 // Critically, the biased locking test must have precedence over 1976 // and appear before the (box->dhw == 0) recursive stack-lock test. 1977 if (UseBiasedLocking && !UseOptoBiasInlining) { 1978 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1979 } 1980 1981 #if INCLUDE_RTM_OPT 1982 if (UseRTMForStackLocks && use_rtm) { 1983 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1984 Label L_regular_unlock; 1985 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1986 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1987 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1988 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1989 xend(); // otherwise end... 1990 jmp(DONE_LABEL); // ... and we're done 1991 bind(L_regular_unlock); 1992 } 1993 #endif 1994 1995 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1996 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1997 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1998 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1999 jccb (Assembler::zero, Stacked); 2000 2001 // It's inflated. 2002 #if INCLUDE_RTM_OPT 2003 if (use_rtm) { 2004 Label L_regular_inflated_unlock; 2005 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2006 movptr(boxReg, Address(tmpReg, owner_offset)); 2007 testptr(boxReg, boxReg); 2008 jccb(Assembler::notZero, L_regular_inflated_unlock); 2009 xend(); 2010 jmpb(DONE_LABEL); 2011 bind(L_regular_inflated_unlock); 2012 } 2013 #endif 2014 2015 // Despite our balanced locking property we still check that m->_owner == Self 2016 // as java routines or native JNI code called by this thread might 2017 // have released the lock. 2018 // Refer to the comments in synchronizer.cpp for how we might encode extra 2019 // state in _succ so we can avoid fetching EntryList|cxq. 2020 // 2021 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2022 // such as recursive enter and exit -- but we have to be wary of 2023 // I$ bloat, T$ effects and BP$ effects. 2024 // 2025 // If there's no contention try a 1-0 exit. That is, exit without 2026 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2027 // we detect and recover from the race that the 1-0 exit admits. 2028 // 2029 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2030 // before it STs null into _owner, releasing the lock. Updates 2031 // to data protected by the critical section must be visible before 2032 // we drop the lock (and thus before any other thread could acquire 2033 // the lock and observe the fields protected by the lock). 2034 // IA32's memory-model is SPO, so STs are ordered with respect to 2035 // each other and there's no need for an explicit barrier (fence). 2036 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2037 #ifndef _LP64 2038 get_thread (boxReg); 2039 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2040 // prefetchw [ebx + Offset(_owner)-2] 2041 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2042 } 2043 2044 // Note that we could employ various encoding schemes to reduce 2045 // the number of loads below (currently 4) to just 2 or 3. 2046 // Refer to the comments in synchronizer.cpp. 2047 // In practice the chain of fetches doesn't seem to impact performance, however. 2048 xorptr(boxReg, boxReg); 2049 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2050 // Attempt to reduce branch density - AMD's branch predictor. 2051 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2052 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2054 jccb (Assembler::notZero, DONE_LABEL); 2055 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2056 jmpb (DONE_LABEL); 2057 } else { 2058 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2059 jccb (Assembler::notZero, DONE_LABEL); 2060 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2062 jccb (Assembler::notZero, CheckSucc); 2063 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2064 jmpb (DONE_LABEL); 2065 } 2066 2067 // The Following code fragment (EmitSync & 65536) improves the performance of 2068 // contended applications and contended synchronization microbenchmarks. 2069 // Unfortunately the emission of the code - even though not executed - causes regressions 2070 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2071 // with an equal number of never-executed NOPs results in the same regression. 2072 // We leave it off by default. 2073 2074 if ((EmitSync & 65536) != 0) { 2075 Label LSuccess, LGoSlowPath ; 2076 2077 bind (CheckSucc); 2078 2079 // Optional pre-test ... it's safe to elide this 2080 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2081 jccb(Assembler::zero, LGoSlowPath); 2082 2083 // We have a classic Dekker-style idiom: 2084 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2085 // There are a number of ways to implement the barrier: 2086 // (1) lock:andl &m->_owner, 0 2087 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2088 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2089 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2090 // (2) If supported, an explicit MFENCE is appealing. 2091 // In older IA32 processors MFENCE is slower than lock:add or xchg 2092 // particularly if the write-buffer is full as might be the case if 2093 // if stores closely precede the fence or fence-equivalent instruction. 2094 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2095 // as the situation has changed with Nehalem and Shanghai. 2096 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2097 // The $lines underlying the top-of-stack should be in M-state. 2098 // The locked add instruction is serializing, of course. 2099 // (4) Use xchg, which is serializing 2100 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2101 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2102 // The integer condition codes will tell us if succ was 0. 2103 // Since _succ and _owner should reside in the same $line and 2104 // we just stored into _owner, it's likely that the $line 2105 // remains in M-state for the lock:orl. 2106 // 2107 // We currently use (3), although it's likely that switching to (2) 2108 // is correct for the future. 2109 2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2111 if (os::is_MP()) { 2112 lock(); addptr(Address(rsp, 0), 0); 2113 } 2114 // Ratify _succ remains non-null 2115 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2116 jccb (Assembler::notZero, LSuccess); 2117 2118 xorptr(boxReg, boxReg); // box is really EAX 2119 if (os::is_MP()) { lock(); } 2120 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2121 // There's no successor so we tried to regrab the lock with the 2122 // placeholder value. If that didn't work, then another thread 2123 // grabbed the lock so we're done (and exit was a success). 2124 jccb (Assembler::notEqual, LSuccess); 2125 // Since we're low on registers we installed rsp as a placeholding in _owner. 2126 // Now install Self over rsp. This is safe as we're transitioning from 2127 // non-null to non=null 2128 get_thread (boxReg); 2129 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2130 // Intentional fall-through into LGoSlowPath ... 2131 2132 bind (LGoSlowPath); 2133 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2134 jmpb (DONE_LABEL); 2135 2136 bind (LSuccess); 2137 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2138 jmpb (DONE_LABEL); 2139 } 2140 2141 bind (Stacked); 2142 // It's not inflated and it's not recursively stack-locked and it's not biased. 2143 // It must be stack-locked. 2144 // Try to reset the header to displaced header. 2145 // The "box" value on the stack is stable, so we can reload 2146 // and be assured we observe the same value as above. 2147 movptr(tmpReg, Address(boxReg, 0)); 2148 if (os::is_MP()) { 2149 lock(); 2150 } 2151 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2152 // Intention fall-thru into DONE_LABEL 2153 2154 // DONE_LABEL is a hot target - we'd really like to place it at the 2155 // start of cache line by padding with NOPs. 2156 // See the AMD and Intel software optimization manuals for the 2157 // most efficient "long" NOP encodings. 2158 // Unfortunately none of our alignment mechanisms suffice. 2159 if ((EmitSync & 65536) == 0) { 2160 bind (CheckSucc); 2161 } 2162 #else // _LP64 2163 // It's inflated 2164 if (EmitSync & 1024) { 2165 // Emit code to check that _owner == Self 2166 // We could fold the _owner test into subsequent code more efficiently 2167 // than using a stand-alone check, but since _owner checking is off by 2168 // default we don't bother. We also might consider predicating the 2169 // _owner==Self check on Xcheck:jni or running on a debug build. 2170 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2171 xorptr(boxReg, r15_thread); 2172 } else { 2173 xorptr(boxReg, boxReg); 2174 } 2175 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2176 jccb (Assembler::notZero, DONE_LABEL); 2177 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2179 jccb (Assembler::notZero, CheckSucc); 2180 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2181 jmpb (DONE_LABEL); 2182 2183 if ((EmitSync & 65536) == 0) { 2184 // Try to avoid passing control into the slow_path ... 2185 Label LSuccess, LGoSlowPath ; 2186 bind (CheckSucc); 2187 2188 // The following optional optimization can be elided if necessary 2189 // Effectively: if (succ == null) goto SlowPath 2190 // The code reduces the window for a race, however, 2191 // and thus benefits performance. 2192 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2193 jccb (Assembler::zero, LGoSlowPath); 2194 2195 xorptr(boxReg, boxReg); 2196 if ((EmitSync & 16) && os::is_MP()) { 2197 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2198 } else { 2199 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2200 if (os::is_MP()) { 2201 // Memory barrier/fence 2202 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2203 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2204 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2205 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2206 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2207 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2208 lock(); addl(Address(rsp, 0), 0); 2209 } 2210 } 2211 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2212 jccb (Assembler::notZero, LSuccess); 2213 2214 // Rare inopportune interleaving - race. 2215 // The successor vanished in the small window above. 2216 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2217 // We need to ensure progress and succession. 2218 // Try to reacquire the lock. 2219 // If that fails then the new owner is responsible for succession and this 2220 // thread needs to take no further action and can exit via the fast path (success). 2221 // If the re-acquire succeeds then pass control into the slow path. 2222 // As implemented, this latter mode is horrible because we generated more 2223 // coherence traffic on the lock *and* artifically extended the critical section 2224 // length while by virtue of passing control into the slow path. 2225 2226 // box is really RAX -- the following CMPXCHG depends on that binding 2227 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2228 if (os::is_MP()) { lock(); } 2229 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2230 // There's no successor so we tried to regrab the lock. 2231 // If that didn't work, then another thread grabbed the 2232 // lock so we're done (and exit was a success). 2233 jccb (Assembler::notEqual, LSuccess); 2234 // Intentional fall-through into slow-path 2235 2236 bind (LGoSlowPath); 2237 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2238 jmpb (DONE_LABEL); 2239 2240 bind (LSuccess); 2241 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2242 jmpb (DONE_LABEL); 2243 } 2244 2245 bind (Stacked); 2246 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2247 if (os::is_MP()) { lock(); } 2248 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2249 2250 if (EmitSync & 65536) { 2251 bind (CheckSucc); 2252 } 2253 #endif 2254 bind(DONE_LABEL); 2255 } 2256 } 2257 #endif // COMPILER2 2258 2259 void MacroAssembler::c2bool(Register x) { 2260 // implements x == 0 ? 0 : 1 2261 // note: must only look at least-significant byte of x 2262 // since C-style booleans are stored in one byte 2263 // only! (was bug) 2264 andl(x, 0xFF); 2265 setb(Assembler::notZero, x); 2266 } 2267 2268 // Wouldn't need if AddressLiteral version had new name 2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2270 Assembler::call(L, rtype); 2271 } 2272 2273 void MacroAssembler::call(Register entry) { 2274 Assembler::call(entry); 2275 } 2276 2277 void MacroAssembler::call(AddressLiteral entry) { 2278 if (reachable(entry)) { 2279 Assembler::call_literal(entry.target(), entry.rspec()); 2280 } else { 2281 lea(rscratch1, entry); 2282 Assembler::call(rscratch1); 2283 } 2284 } 2285 2286 void MacroAssembler::ic_call(address entry, jint method_index) { 2287 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2288 movptr(rax, (intptr_t)Universe::non_oop_word()); 2289 call(AddressLiteral(entry, rh)); 2290 } 2291 2292 // Implementation of call_VM versions 2293 2294 void MacroAssembler::call_VM(Register oop_result, 2295 address entry_point, 2296 bool check_exceptions) { 2297 Label C, E; 2298 call(C, relocInfo::none); 2299 jmp(E); 2300 2301 bind(C); 2302 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2303 ret(0); 2304 2305 bind(E); 2306 } 2307 2308 void MacroAssembler::call_VM(Register oop_result, 2309 address entry_point, 2310 Register arg_1, 2311 bool check_exceptions) { 2312 Label C, E; 2313 call(C, relocInfo::none); 2314 jmp(E); 2315 2316 bind(C); 2317 pass_arg1(this, arg_1); 2318 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2319 ret(0); 2320 2321 bind(E); 2322 } 2323 2324 void MacroAssembler::call_VM(Register oop_result, 2325 address entry_point, 2326 Register arg_1, 2327 Register arg_2, 2328 bool check_exceptions) { 2329 Label C, E; 2330 call(C, relocInfo::none); 2331 jmp(E); 2332 2333 bind(C); 2334 2335 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2336 2337 pass_arg2(this, arg_2); 2338 pass_arg1(this, arg_1); 2339 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2340 ret(0); 2341 2342 bind(E); 2343 } 2344 2345 void MacroAssembler::call_VM(Register oop_result, 2346 address entry_point, 2347 Register arg_1, 2348 Register arg_2, 2349 Register arg_3, 2350 bool check_exceptions) { 2351 Label C, E; 2352 call(C, relocInfo::none); 2353 jmp(E); 2354 2355 bind(C); 2356 2357 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2358 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2359 pass_arg3(this, arg_3); 2360 2361 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2362 pass_arg2(this, arg_2); 2363 2364 pass_arg1(this, arg_1); 2365 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2366 ret(0); 2367 2368 bind(E); 2369 } 2370 2371 void MacroAssembler::call_VM(Register oop_result, 2372 Register last_java_sp, 2373 address entry_point, 2374 int number_of_arguments, 2375 bool check_exceptions) { 2376 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2377 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2378 } 2379 2380 void MacroAssembler::call_VM(Register oop_result, 2381 Register last_java_sp, 2382 address entry_point, 2383 Register arg_1, 2384 bool check_exceptions) { 2385 pass_arg1(this, arg_1); 2386 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2387 } 2388 2389 void MacroAssembler::call_VM(Register oop_result, 2390 Register last_java_sp, 2391 address entry_point, 2392 Register arg_1, 2393 Register arg_2, 2394 bool check_exceptions) { 2395 2396 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2397 pass_arg2(this, arg_2); 2398 pass_arg1(this, arg_1); 2399 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2400 } 2401 2402 void MacroAssembler::call_VM(Register oop_result, 2403 Register last_java_sp, 2404 address entry_point, 2405 Register arg_1, 2406 Register arg_2, 2407 Register arg_3, 2408 bool check_exceptions) { 2409 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2410 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2411 pass_arg3(this, arg_3); 2412 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2413 pass_arg2(this, arg_2); 2414 pass_arg1(this, arg_1); 2415 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2416 } 2417 2418 void MacroAssembler::super_call_VM(Register oop_result, 2419 Register last_java_sp, 2420 address entry_point, 2421 int number_of_arguments, 2422 bool check_exceptions) { 2423 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2424 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2425 } 2426 2427 void MacroAssembler::super_call_VM(Register oop_result, 2428 Register last_java_sp, 2429 address entry_point, 2430 Register arg_1, 2431 bool check_exceptions) { 2432 pass_arg1(this, arg_1); 2433 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2434 } 2435 2436 void MacroAssembler::super_call_VM(Register oop_result, 2437 Register last_java_sp, 2438 address entry_point, 2439 Register arg_1, 2440 Register arg_2, 2441 bool check_exceptions) { 2442 2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2444 pass_arg2(this, arg_2); 2445 pass_arg1(this, arg_1); 2446 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2447 } 2448 2449 void MacroAssembler::super_call_VM(Register oop_result, 2450 Register last_java_sp, 2451 address entry_point, 2452 Register arg_1, 2453 Register arg_2, 2454 Register arg_3, 2455 bool check_exceptions) { 2456 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2457 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2458 pass_arg3(this, arg_3); 2459 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2460 pass_arg2(this, arg_2); 2461 pass_arg1(this, arg_1); 2462 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2463 } 2464 2465 void MacroAssembler::call_VM_base(Register oop_result, 2466 Register java_thread, 2467 Register last_java_sp, 2468 address entry_point, 2469 int number_of_arguments, 2470 bool check_exceptions) { 2471 // determine java_thread register 2472 if (!java_thread->is_valid()) { 2473 #ifdef _LP64 2474 java_thread = r15_thread; 2475 #else 2476 java_thread = rdi; 2477 get_thread(java_thread); 2478 #endif // LP64 2479 } 2480 // determine last_java_sp register 2481 if (!last_java_sp->is_valid()) { 2482 last_java_sp = rsp; 2483 } 2484 // debugging support 2485 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2486 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2487 #ifdef ASSERT 2488 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2489 // r12 is the heapbase. 2490 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2491 #endif // ASSERT 2492 2493 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2494 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2495 2496 // push java thread (becomes first argument of C function) 2497 2498 NOT_LP64(push(java_thread); number_of_arguments++); 2499 LP64_ONLY(mov(c_rarg0, r15_thread)); 2500 2501 // set last Java frame before call 2502 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2503 2504 // Only interpreter should have to set fp 2505 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2506 2507 // do the call, remove parameters 2508 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2509 2510 // restore the thread (cannot use the pushed argument since arguments 2511 // may be overwritten by C code generated by an optimizing compiler); 2512 // however can use the register value directly if it is callee saved. 2513 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2514 // rdi & rsi (also r15) are callee saved -> nothing to do 2515 #ifdef ASSERT 2516 guarantee(java_thread != rax, "change this code"); 2517 push(rax); 2518 { Label L; 2519 get_thread(rax); 2520 cmpptr(java_thread, rax); 2521 jcc(Assembler::equal, L); 2522 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2523 bind(L); 2524 } 2525 pop(rax); 2526 #endif 2527 } else { 2528 get_thread(java_thread); 2529 } 2530 // reset last Java frame 2531 // Only interpreter should have to clear fp 2532 reset_last_Java_frame(java_thread, true); 2533 2534 // C++ interp handles this in the interpreter 2535 check_and_handle_popframe(java_thread); 2536 check_and_handle_earlyret(java_thread); 2537 2538 if (check_exceptions) { 2539 // check for pending exceptions (java_thread is set upon return) 2540 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2541 #ifndef _LP64 2542 jump_cc(Assembler::notEqual, 2543 RuntimeAddress(StubRoutines::forward_exception_entry())); 2544 #else 2545 // This used to conditionally jump to forward_exception however it is 2546 // possible if we relocate that the branch will not reach. So we must jump 2547 // around so we can always reach 2548 2549 Label ok; 2550 jcc(Assembler::equal, ok); 2551 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2552 bind(ok); 2553 #endif // LP64 2554 } 2555 2556 // get oop result if there is one and reset the value in the thread 2557 if (oop_result->is_valid()) { 2558 get_vm_result(oop_result, java_thread); 2559 } 2560 } 2561 2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2563 2564 // Calculate the value for last_Java_sp 2565 // somewhat subtle. call_VM does an intermediate call 2566 // which places a return address on the stack just under the 2567 // stack pointer as the user finsihed with it. This allows 2568 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2569 // On 32bit we then have to push additional args on the stack to accomplish 2570 // the actual requested call. On 64bit call_VM only can use register args 2571 // so the only extra space is the return address that call_VM created. 2572 // This hopefully explains the calculations here. 2573 2574 #ifdef _LP64 2575 // We've pushed one address, correct last_Java_sp 2576 lea(rax, Address(rsp, wordSize)); 2577 #else 2578 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2579 #endif // LP64 2580 2581 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2582 2583 } 2584 2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2586 void MacroAssembler::call_VM_leaf0(address entry_point) { 2587 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2588 } 2589 2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2591 call_VM_leaf_base(entry_point, number_of_arguments); 2592 } 2593 2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2595 pass_arg0(this, arg_0); 2596 call_VM_leaf(entry_point, 1); 2597 } 2598 2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2600 2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2602 pass_arg1(this, arg_1); 2603 pass_arg0(this, arg_0); 2604 call_VM_leaf(entry_point, 2); 2605 } 2606 2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2608 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2609 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2610 pass_arg2(this, arg_2); 2611 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2612 pass_arg1(this, arg_1); 2613 pass_arg0(this, arg_0); 2614 call_VM_leaf(entry_point, 3); 2615 } 2616 2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2618 pass_arg0(this, arg_0); 2619 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2620 } 2621 2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2623 2624 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2625 pass_arg1(this, arg_1); 2626 pass_arg0(this, arg_0); 2627 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2628 } 2629 2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2631 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2632 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2633 pass_arg2(this, arg_2); 2634 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2635 pass_arg1(this, arg_1); 2636 pass_arg0(this, arg_0); 2637 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2638 } 2639 2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2641 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2642 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2643 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2644 pass_arg3(this, arg_3); 2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2647 pass_arg2(this, arg_2); 2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2649 pass_arg1(this, arg_1); 2650 pass_arg0(this, arg_0); 2651 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2652 } 2653 2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2655 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2656 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2657 verify_oop(oop_result, "broken oop in call_VM_base"); 2658 } 2659 2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2661 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2662 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2663 } 2664 2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2666 } 2667 2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2669 } 2670 2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2672 if (reachable(src1)) { 2673 cmpl(as_Address(src1), imm); 2674 } else { 2675 lea(rscratch1, src1); 2676 cmpl(Address(rscratch1, 0), imm); 2677 } 2678 } 2679 2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2681 assert(!src2.is_lval(), "use cmpptr"); 2682 if (reachable(src2)) { 2683 cmpl(src1, as_Address(src2)); 2684 } else { 2685 lea(rscratch1, src2); 2686 cmpl(src1, Address(rscratch1, 0)); 2687 } 2688 } 2689 2690 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2691 Assembler::cmpl(src1, imm); 2692 } 2693 2694 void MacroAssembler::cmp32(Register src1, Address src2) { 2695 Assembler::cmpl(src1, src2); 2696 } 2697 2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2699 ucomisd(opr1, opr2); 2700 2701 Label L; 2702 if (unordered_is_less) { 2703 movl(dst, -1); 2704 jcc(Assembler::parity, L); 2705 jcc(Assembler::below , L); 2706 movl(dst, 0); 2707 jcc(Assembler::equal , L); 2708 increment(dst); 2709 } else { // unordered is greater 2710 movl(dst, 1); 2711 jcc(Assembler::parity, L); 2712 jcc(Assembler::above , L); 2713 movl(dst, 0); 2714 jcc(Assembler::equal , L); 2715 decrementl(dst); 2716 } 2717 bind(L); 2718 } 2719 2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2721 ucomiss(opr1, opr2); 2722 2723 Label L; 2724 if (unordered_is_less) { 2725 movl(dst, -1); 2726 jcc(Assembler::parity, L); 2727 jcc(Assembler::below , L); 2728 movl(dst, 0); 2729 jcc(Assembler::equal , L); 2730 increment(dst); 2731 } else { // unordered is greater 2732 movl(dst, 1); 2733 jcc(Assembler::parity, L); 2734 jcc(Assembler::above , L); 2735 movl(dst, 0); 2736 jcc(Assembler::equal , L); 2737 decrementl(dst); 2738 } 2739 bind(L); 2740 } 2741 2742 2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2744 if (reachable(src1)) { 2745 cmpb(as_Address(src1), imm); 2746 } else { 2747 lea(rscratch1, src1); 2748 cmpb(Address(rscratch1, 0), imm); 2749 } 2750 } 2751 2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2753 #ifdef _LP64 2754 if (src2.is_lval()) { 2755 movptr(rscratch1, src2); 2756 Assembler::cmpq(src1, rscratch1); 2757 } else if (reachable(src2)) { 2758 cmpq(src1, as_Address(src2)); 2759 } else { 2760 lea(rscratch1, src2); 2761 Assembler::cmpq(src1, Address(rscratch1, 0)); 2762 } 2763 #else 2764 if (src2.is_lval()) { 2765 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2766 } else { 2767 cmpl(src1, as_Address(src2)); 2768 } 2769 #endif // _LP64 2770 } 2771 2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2773 assert(src2.is_lval(), "not a mem-mem compare"); 2774 #ifdef _LP64 2775 // moves src2's literal address 2776 movptr(rscratch1, src2); 2777 Assembler::cmpq(src1, rscratch1); 2778 #else 2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2780 #endif // _LP64 2781 } 2782 2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2784 if (reachable(adr)) { 2785 if (os::is_MP()) 2786 lock(); 2787 cmpxchgptr(reg, as_Address(adr)); 2788 } else { 2789 lea(rscratch1, adr); 2790 if (os::is_MP()) 2791 lock(); 2792 cmpxchgptr(reg, Address(rscratch1, 0)); 2793 } 2794 } 2795 2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2797 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2798 } 2799 2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2801 if (reachable(src)) { 2802 Assembler::comisd(dst, as_Address(src)); 2803 } else { 2804 lea(rscratch1, src); 2805 Assembler::comisd(dst, Address(rscratch1, 0)); 2806 } 2807 } 2808 2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2810 if (reachable(src)) { 2811 Assembler::comiss(dst, as_Address(src)); 2812 } else { 2813 lea(rscratch1, src); 2814 Assembler::comiss(dst, Address(rscratch1, 0)); 2815 } 2816 } 2817 2818 2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2820 Condition negated_cond = negate_condition(cond); 2821 Label L; 2822 jcc(negated_cond, L); 2823 pushf(); // Preserve flags 2824 atomic_incl(counter_addr); 2825 popf(); 2826 bind(L); 2827 } 2828 2829 int MacroAssembler::corrected_idivl(Register reg) { 2830 // Full implementation of Java idiv and irem; checks for 2831 // special case as described in JVM spec., p.243 & p.271. 2832 // The function returns the (pc) offset of the idivl 2833 // instruction - may be needed for implicit exceptions. 2834 // 2835 // normal case special case 2836 // 2837 // input : rax,: dividend min_int 2838 // reg: divisor (may not be rax,/rdx) -1 2839 // 2840 // output: rax,: quotient (= rax, idiv reg) min_int 2841 // rdx: remainder (= rax, irem reg) 0 2842 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2843 const int min_int = 0x80000000; 2844 Label normal_case, special_case; 2845 2846 // check for special case 2847 cmpl(rax, min_int); 2848 jcc(Assembler::notEqual, normal_case); 2849 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2850 cmpl(reg, -1); 2851 jcc(Assembler::equal, special_case); 2852 2853 // handle normal case 2854 bind(normal_case); 2855 cdql(); 2856 int idivl_offset = offset(); 2857 idivl(reg); 2858 2859 // normal and special case exit 2860 bind(special_case); 2861 2862 return idivl_offset; 2863 } 2864 2865 2866 2867 void MacroAssembler::decrementl(Register reg, int value) { 2868 if (value == min_jint) {subl(reg, value) ; return; } 2869 if (value < 0) { incrementl(reg, -value); return; } 2870 if (value == 0) { ; return; } 2871 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2872 /* else */ { subl(reg, value) ; return; } 2873 } 2874 2875 void MacroAssembler::decrementl(Address dst, int value) { 2876 if (value == min_jint) {subl(dst, value) ; return; } 2877 if (value < 0) { incrementl(dst, -value); return; } 2878 if (value == 0) { ; return; } 2879 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2880 /* else */ { subl(dst, value) ; return; } 2881 } 2882 2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2884 assert (shift_value > 0, "illegal shift value"); 2885 Label _is_positive; 2886 testl (reg, reg); 2887 jcc (Assembler::positive, _is_positive); 2888 int offset = (1 << shift_value) - 1 ; 2889 2890 if (offset == 1) { 2891 incrementl(reg); 2892 } else { 2893 addl(reg, offset); 2894 } 2895 2896 bind (_is_positive); 2897 sarl(reg, shift_value); 2898 } 2899 2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2901 if (reachable(src)) { 2902 Assembler::divsd(dst, as_Address(src)); 2903 } else { 2904 lea(rscratch1, src); 2905 Assembler::divsd(dst, Address(rscratch1, 0)); 2906 } 2907 } 2908 2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2910 if (reachable(src)) { 2911 Assembler::divss(dst, as_Address(src)); 2912 } else { 2913 lea(rscratch1, src); 2914 Assembler::divss(dst, Address(rscratch1, 0)); 2915 } 2916 } 2917 2918 // !defined(COMPILER2) is because of stupid core builds 2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2920 void MacroAssembler::empty_FPU_stack() { 2921 if (VM_Version::supports_mmx()) { 2922 emms(); 2923 } else { 2924 for (int i = 8; i-- > 0; ) ffree(i); 2925 } 2926 } 2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2928 2929 2930 // Defines obj, preserves var_size_in_bytes 2931 void MacroAssembler::eden_allocate(Register obj, 2932 Register var_size_in_bytes, 2933 int con_size_in_bytes, 2934 Register t1, 2935 Label& slow_case) { 2936 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2937 assert_different_registers(obj, var_size_in_bytes, t1); 2938 if (!Universe::heap()->supports_inline_contig_alloc()) { 2939 jmp(slow_case); 2940 } else { 2941 Register end = t1; 2942 Label retry; 2943 bind(retry); 2944 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2945 movptr(obj, heap_top); 2946 if (var_size_in_bytes == noreg) { 2947 lea(end, Address(obj, con_size_in_bytes)); 2948 } else { 2949 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2950 } 2951 // if end < obj then we wrapped around => object too long => slow case 2952 cmpptr(end, obj); 2953 jcc(Assembler::below, slow_case); 2954 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2955 jcc(Assembler::above, slow_case); 2956 // Compare obj with the top addr, and if still equal, store the new top addr in 2957 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2958 // it otherwise. Use lock prefix for atomicity on MPs. 2959 locked_cmpxchgptr(end, heap_top); 2960 jcc(Assembler::notEqual, retry); 2961 } 2962 } 2963 2964 void MacroAssembler::enter() { 2965 push(rbp); 2966 mov(rbp, rsp); 2967 } 2968 2969 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2970 void MacroAssembler::fat_nop() { 2971 if (UseAddressNop) { 2972 addr_nop_5(); 2973 } else { 2974 emit_int8(0x26); // es: 2975 emit_int8(0x2e); // cs: 2976 emit_int8(0x64); // fs: 2977 emit_int8(0x65); // gs: 2978 emit_int8((unsigned char)0x90); 2979 } 2980 } 2981 2982 void MacroAssembler::fcmp(Register tmp) { 2983 fcmp(tmp, 1, true, true); 2984 } 2985 2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2987 assert(!pop_right || pop_left, "usage error"); 2988 if (VM_Version::supports_cmov()) { 2989 assert(tmp == noreg, "unneeded temp"); 2990 if (pop_left) { 2991 fucomip(index); 2992 } else { 2993 fucomi(index); 2994 } 2995 if (pop_right) { 2996 fpop(); 2997 } 2998 } else { 2999 assert(tmp != noreg, "need temp"); 3000 if (pop_left) { 3001 if (pop_right) { 3002 fcompp(); 3003 } else { 3004 fcomp(index); 3005 } 3006 } else { 3007 fcom(index); 3008 } 3009 // convert FPU condition into eflags condition via rax, 3010 save_rax(tmp); 3011 fwait(); fnstsw_ax(); 3012 sahf(); 3013 restore_rax(tmp); 3014 } 3015 // condition codes set as follows: 3016 // 3017 // CF (corresponds to C0) if x < y 3018 // PF (corresponds to C2) if unordered 3019 // ZF (corresponds to C3) if x = y 3020 } 3021 3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3023 fcmp2int(dst, unordered_is_less, 1, true, true); 3024 } 3025 3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3027 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3028 Label L; 3029 if (unordered_is_less) { 3030 movl(dst, -1); 3031 jcc(Assembler::parity, L); 3032 jcc(Assembler::below , L); 3033 movl(dst, 0); 3034 jcc(Assembler::equal , L); 3035 increment(dst); 3036 } else { // unordered is greater 3037 movl(dst, 1); 3038 jcc(Assembler::parity, L); 3039 jcc(Assembler::above , L); 3040 movl(dst, 0); 3041 jcc(Assembler::equal , L); 3042 decrementl(dst); 3043 } 3044 bind(L); 3045 } 3046 3047 void MacroAssembler::fld_d(AddressLiteral src) { 3048 fld_d(as_Address(src)); 3049 } 3050 3051 void MacroAssembler::fld_s(AddressLiteral src) { 3052 fld_s(as_Address(src)); 3053 } 3054 3055 void MacroAssembler::fld_x(AddressLiteral src) { 3056 Assembler::fld_x(as_Address(src)); 3057 } 3058 3059 void MacroAssembler::fldcw(AddressLiteral src) { 3060 Assembler::fldcw(as_Address(src)); 3061 } 3062 3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3064 if (reachable(src)) { 3065 Assembler::mulpd(dst, as_Address(src)); 3066 } else { 3067 lea(rscratch1, src); 3068 Assembler::mulpd(dst, Address(rscratch1, 0)); 3069 } 3070 } 3071 3072 void MacroAssembler::increase_precision() { 3073 subptr(rsp, BytesPerWord); 3074 fnstcw(Address(rsp, 0)); 3075 movl(rax, Address(rsp, 0)); 3076 orl(rax, 0x300); 3077 push(rax); 3078 fldcw(Address(rsp, 0)); 3079 pop(rax); 3080 } 3081 3082 void MacroAssembler::restore_precision() { 3083 fldcw(Address(rsp, 0)); 3084 addptr(rsp, BytesPerWord); 3085 } 3086 3087 void MacroAssembler::fpop() { 3088 ffree(); 3089 fincstp(); 3090 } 3091 3092 void MacroAssembler::load_float(Address src) { 3093 if (UseSSE >= 1) { 3094 movflt(xmm0, src); 3095 } else { 3096 LP64_ONLY(ShouldNotReachHere()); 3097 NOT_LP64(fld_s(src)); 3098 } 3099 } 3100 3101 void MacroAssembler::store_float(Address dst) { 3102 if (UseSSE >= 1) { 3103 movflt(dst, xmm0); 3104 } else { 3105 LP64_ONLY(ShouldNotReachHere()); 3106 NOT_LP64(fstp_s(dst)); 3107 } 3108 } 3109 3110 void MacroAssembler::load_double(Address src) { 3111 if (UseSSE >= 2) { 3112 movdbl(xmm0, src); 3113 } else { 3114 LP64_ONLY(ShouldNotReachHere()); 3115 NOT_LP64(fld_d(src)); 3116 } 3117 } 3118 3119 void MacroAssembler::store_double(Address dst) { 3120 if (UseSSE >= 2) { 3121 movdbl(dst, xmm0); 3122 } else { 3123 LP64_ONLY(ShouldNotReachHere()); 3124 NOT_LP64(fstp_d(dst)); 3125 } 3126 } 3127 3128 void MacroAssembler::fremr(Register tmp) { 3129 save_rax(tmp); 3130 { Label L; 3131 bind(L); 3132 fprem(); 3133 fwait(); fnstsw_ax(); 3134 #ifdef _LP64 3135 testl(rax, 0x400); 3136 jcc(Assembler::notEqual, L); 3137 #else 3138 sahf(); 3139 jcc(Assembler::parity, L); 3140 #endif // _LP64 3141 } 3142 restore_rax(tmp); 3143 // Result is in ST0. 3144 // Note: fxch & fpop to get rid of ST1 3145 // (otherwise FPU stack could overflow eventually) 3146 fxch(1); 3147 fpop(); 3148 } 3149 3150 // dst = c = a * b + c 3151 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3152 Assembler::vfmadd231sd(c, a, b); 3153 if (dst != c) { 3154 movdbl(dst, c); 3155 } 3156 } 3157 3158 // dst = c = a * b + c 3159 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3160 Assembler::vfmadd231ss(c, a, b); 3161 if (dst != c) { 3162 movflt(dst, c); 3163 } 3164 } 3165 3166 3167 3168 3169 void MacroAssembler::incrementl(AddressLiteral dst) { 3170 if (reachable(dst)) { 3171 incrementl(as_Address(dst)); 3172 } else { 3173 lea(rscratch1, dst); 3174 incrementl(Address(rscratch1, 0)); 3175 } 3176 } 3177 3178 void MacroAssembler::incrementl(ArrayAddress dst) { 3179 incrementl(as_Address(dst)); 3180 } 3181 3182 void MacroAssembler::incrementl(Register reg, int value) { 3183 if (value == min_jint) {addl(reg, value) ; return; } 3184 if (value < 0) { decrementl(reg, -value); return; } 3185 if (value == 0) { ; return; } 3186 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3187 /* else */ { addl(reg, value) ; return; } 3188 } 3189 3190 void MacroAssembler::incrementl(Address dst, int value) { 3191 if (value == min_jint) {addl(dst, value) ; return; } 3192 if (value < 0) { decrementl(dst, -value); return; } 3193 if (value == 0) { ; return; } 3194 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3195 /* else */ { addl(dst, value) ; return; } 3196 } 3197 3198 void MacroAssembler::jump(AddressLiteral dst) { 3199 if (reachable(dst)) { 3200 jmp_literal(dst.target(), dst.rspec()); 3201 } else { 3202 lea(rscratch1, dst); 3203 jmp(rscratch1); 3204 } 3205 } 3206 3207 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3208 if (reachable(dst)) { 3209 InstructionMark im(this); 3210 relocate(dst.reloc()); 3211 const int short_size = 2; 3212 const int long_size = 6; 3213 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3214 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3215 // 0111 tttn #8-bit disp 3216 emit_int8(0x70 | cc); 3217 emit_int8((offs - short_size) & 0xFF); 3218 } else { 3219 // 0000 1111 1000 tttn #32-bit disp 3220 emit_int8(0x0F); 3221 emit_int8((unsigned char)(0x80 | cc)); 3222 emit_int32(offs - long_size); 3223 } 3224 } else { 3225 #ifdef ASSERT 3226 warning("reversing conditional branch"); 3227 #endif /* ASSERT */ 3228 Label skip; 3229 jccb(reverse[cc], skip); 3230 lea(rscratch1, dst); 3231 Assembler::jmp(rscratch1); 3232 bind(skip); 3233 } 3234 } 3235 3236 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3237 if (reachable(src)) { 3238 Assembler::ldmxcsr(as_Address(src)); 3239 } else { 3240 lea(rscratch1, src); 3241 Assembler::ldmxcsr(Address(rscratch1, 0)); 3242 } 3243 } 3244 3245 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3246 int off; 3247 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3248 off = offset(); 3249 movsbl(dst, src); // movsxb 3250 } else { 3251 off = load_unsigned_byte(dst, src); 3252 shll(dst, 24); 3253 sarl(dst, 24); 3254 } 3255 return off; 3256 } 3257 3258 // Note: load_signed_short used to be called load_signed_word. 3259 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3260 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3261 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3262 int MacroAssembler::load_signed_short(Register dst, Address src) { 3263 int off; 3264 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3265 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3266 // version but this is what 64bit has always done. This seems to imply 3267 // that users are only using 32bits worth. 3268 off = offset(); 3269 movswl(dst, src); // movsxw 3270 } else { 3271 off = load_unsigned_short(dst, src); 3272 shll(dst, 16); 3273 sarl(dst, 16); 3274 } 3275 return off; 3276 } 3277 3278 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3279 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3280 // and "3.9 Partial Register Penalties", p. 22). 3281 int off; 3282 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3283 off = offset(); 3284 movzbl(dst, src); // movzxb 3285 } else { 3286 xorl(dst, dst); 3287 off = offset(); 3288 movb(dst, src); 3289 } 3290 return off; 3291 } 3292 3293 // Note: load_unsigned_short used to be called load_unsigned_word. 3294 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3295 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3296 // and "3.9 Partial Register Penalties", p. 22). 3297 int off; 3298 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3299 off = offset(); 3300 movzwl(dst, src); // movzxw 3301 } else { 3302 xorl(dst, dst); 3303 off = offset(); 3304 movw(dst, src); 3305 } 3306 return off; 3307 } 3308 3309 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3310 switch (size_in_bytes) { 3311 #ifndef _LP64 3312 case 8: 3313 assert(dst2 != noreg, "second dest register required"); 3314 movl(dst, src); 3315 movl(dst2, src.plus_disp(BytesPerInt)); 3316 break; 3317 #else 3318 case 8: movq(dst, src); break; 3319 #endif 3320 case 4: movl(dst, src); break; 3321 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3322 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3323 default: ShouldNotReachHere(); 3324 } 3325 } 3326 3327 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3328 switch (size_in_bytes) { 3329 #ifndef _LP64 3330 case 8: 3331 assert(src2 != noreg, "second source register required"); 3332 movl(dst, src); 3333 movl(dst.plus_disp(BytesPerInt), src2); 3334 break; 3335 #else 3336 case 8: movq(dst, src); break; 3337 #endif 3338 case 4: movl(dst, src); break; 3339 case 2: movw(dst, src); break; 3340 case 1: movb(dst, src); break; 3341 default: ShouldNotReachHere(); 3342 } 3343 } 3344 3345 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3346 if (reachable(dst)) { 3347 movl(as_Address(dst), src); 3348 } else { 3349 lea(rscratch1, dst); 3350 movl(Address(rscratch1, 0), src); 3351 } 3352 } 3353 3354 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3355 if (reachable(src)) { 3356 movl(dst, as_Address(src)); 3357 } else { 3358 lea(rscratch1, src); 3359 movl(dst, Address(rscratch1, 0)); 3360 } 3361 } 3362 3363 // C++ bool manipulation 3364 3365 void MacroAssembler::movbool(Register dst, Address src) { 3366 if(sizeof(bool) == 1) 3367 movb(dst, src); 3368 else if(sizeof(bool) == 2) 3369 movw(dst, src); 3370 else if(sizeof(bool) == 4) 3371 movl(dst, src); 3372 else 3373 // unsupported 3374 ShouldNotReachHere(); 3375 } 3376 3377 void MacroAssembler::movbool(Address dst, bool boolconst) { 3378 if(sizeof(bool) == 1) 3379 movb(dst, (int) boolconst); 3380 else if(sizeof(bool) == 2) 3381 movw(dst, (int) boolconst); 3382 else if(sizeof(bool) == 4) 3383 movl(dst, (int) boolconst); 3384 else 3385 // unsupported 3386 ShouldNotReachHere(); 3387 } 3388 3389 void MacroAssembler::movbool(Address dst, Register src) { 3390 if(sizeof(bool) == 1) 3391 movb(dst, src); 3392 else if(sizeof(bool) == 2) 3393 movw(dst, src); 3394 else if(sizeof(bool) == 4) 3395 movl(dst, src); 3396 else 3397 // unsupported 3398 ShouldNotReachHere(); 3399 } 3400 3401 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3402 movb(as_Address(dst), src); 3403 } 3404 3405 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3406 if (reachable(src)) { 3407 movdl(dst, as_Address(src)); 3408 } else { 3409 lea(rscratch1, src); 3410 movdl(dst, Address(rscratch1, 0)); 3411 } 3412 } 3413 3414 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3415 if (reachable(src)) { 3416 movq(dst, as_Address(src)); 3417 } else { 3418 lea(rscratch1, src); 3419 movq(dst, Address(rscratch1, 0)); 3420 } 3421 } 3422 3423 void MacroAssembler::setvectmask(Register dst, Register src) { 3424 Assembler::movl(dst, 1); 3425 Assembler::shlxl(dst, dst, src); 3426 Assembler::decl(dst); 3427 Assembler::kmovdl(k1, dst); 3428 Assembler::movl(dst, src); 3429 } 3430 3431 void MacroAssembler::restorevectmask() { 3432 Assembler::knotwl(k1, k0); 3433 } 3434 3435 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3436 if (reachable(src)) { 3437 if (UseXmmLoadAndClearUpper) { 3438 movsd (dst, as_Address(src)); 3439 } else { 3440 movlpd(dst, as_Address(src)); 3441 } 3442 } else { 3443 lea(rscratch1, src); 3444 if (UseXmmLoadAndClearUpper) { 3445 movsd (dst, Address(rscratch1, 0)); 3446 } else { 3447 movlpd(dst, Address(rscratch1, 0)); 3448 } 3449 } 3450 } 3451 3452 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3453 if (reachable(src)) { 3454 movss(dst, as_Address(src)); 3455 } else { 3456 lea(rscratch1, src); 3457 movss(dst, Address(rscratch1, 0)); 3458 } 3459 } 3460 3461 void MacroAssembler::movptr(Register dst, Register src) { 3462 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3463 } 3464 3465 void MacroAssembler::movptr(Register dst, Address src) { 3466 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3467 } 3468 3469 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3470 void MacroAssembler::movptr(Register dst, intptr_t src) { 3471 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3472 } 3473 3474 void MacroAssembler::movptr(Address dst, Register src) { 3475 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3476 } 3477 3478 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3479 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3480 Assembler::vextractf32x4(dst, src, 0); 3481 } else { 3482 Assembler::movdqu(dst, src); 3483 } 3484 } 3485 3486 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3487 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3488 Assembler::vinsertf32x4(dst, dst, src, 0); 3489 } else { 3490 Assembler::movdqu(dst, src); 3491 } 3492 } 3493 3494 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3495 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3496 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3497 } else { 3498 Assembler::movdqu(dst, src); 3499 } 3500 } 3501 3502 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3503 if (reachable(src)) { 3504 movdqu(dst, as_Address(src)); 3505 } else { 3506 lea(rscratch1, src); 3507 movdqu(dst, Address(rscratch1, 0)); 3508 } 3509 } 3510 3511 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3512 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3513 vextractf64x4_low(dst, src); 3514 } else { 3515 Assembler::vmovdqu(dst, src); 3516 } 3517 } 3518 3519 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3520 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3521 vinsertf64x4_low(dst, src); 3522 } else { 3523 Assembler::vmovdqu(dst, src); 3524 } 3525 } 3526 3527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3528 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3529 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3530 } 3531 else { 3532 Assembler::vmovdqu(dst, src); 3533 } 3534 } 3535 3536 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3537 if (reachable(src)) { 3538 vmovdqu(dst, as_Address(src)); 3539 } 3540 else { 3541 lea(rscratch1, src); 3542 vmovdqu(dst, Address(rscratch1, 0)); 3543 } 3544 } 3545 3546 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3547 if (reachable(src)) { 3548 Assembler::movdqa(dst, as_Address(src)); 3549 } else { 3550 lea(rscratch1, src); 3551 Assembler::movdqa(dst, Address(rscratch1, 0)); 3552 } 3553 } 3554 3555 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3556 if (reachable(src)) { 3557 Assembler::movsd(dst, as_Address(src)); 3558 } else { 3559 lea(rscratch1, src); 3560 Assembler::movsd(dst, Address(rscratch1, 0)); 3561 } 3562 } 3563 3564 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3565 if (reachable(src)) { 3566 Assembler::movss(dst, as_Address(src)); 3567 } else { 3568 lea(rscratch1, src); 3569 Assembler::movss(dst, Address(rscratch1, 0)); 3570 } 3571 } 3572 3573 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3574 if (reachable(src)) { 3575 Assembler::mulsd(dst, as_Address(src)); 3576 } else { 3577 lea(rscratch1, src); 3578 Assembler::mulsd(dst, Address(rscratch1, 0)); 3579 } 3580 } 3581 3582 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3583 if (reachable(src)) { 3584 Assembler::mulss(dst, as_Address(src)); 3585 } else { 3586 lea(rscratch1, src); 3587 Assembler::mulss(dst, Address(rscratch1, 0)); 3588 } 3589 } 3590 3591 void MacroAssembler::null_check(Register reg, int offset) { 3592 if (needs_explicit_null_check(offset)) { 3593 // provoke OS NULL exception if reg = NULL by 3594 // accessing M[reg] w/o changing any (non-CC) registers 3595 // NOTE: cmpl is plenty here to provoke a segv 3596 cmpptr(rax, Address(reg, 0)); 3597 // Note: should probably use testl(rax, Address(reg, 0)); 3598 // may be shorter code (however, this version of 3599 // testl needs to be implemented first) 3600 } else { 3601 // nothing to do, (later) access of M[reg + offset] 3602 // will provoke OS NULL exception if reg = NULL 3603 } 3604 } 3605 3606 void MacroAssembler::os_breakpoint() { 3607 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3608 // (e.g., MSVC can't call ps() otherwise) 3609 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3610 } 3611 3612 #ifdef _LP64 3613 #define XSTATE_BV 0x200 3614 #endif 3615 3616 void MacroAssembler::pop_CPU_state() { 3617 pop_FPU_state(); 3618 pop_IU_state(); 3619 } 3620 3621 void MacroAssembler::pop_FPU_state() { 3622 #ifndef _LP64 3623 frstor(Address(rsp, 0)); 3624 #else 3625 fxrstor(Address(rsp, 0)); 3626 #endif 3627 addptr(rsp, FPUStateSizeInWords * wordSize); 3628 } 3629 3630 void MacroAssembler::pop_IU_state() { 3631 popa(); 3632 LP64_ONLY(addq(rsp, 8)); 3633 popf(); 3634 } 3635 3636 // Save Integer and Float state 3637 // Warning: Stack must be 16 byte aligned (64bit) 3638 void MacroAssembler::push_CPU_state() { 3639 push_IU_state(); 3640 push_FPU_state(); 3641 } 3642 3643 void MacroAssembler::push_FPU_state() { 3644 subptr(rsp, FPUStateSizeInWords * wordSize); 3645 #ifndef _LP64 3646 fnsave(Address(rsp, 0)); 3647 fwait(); 3648 #else 3649 fxsave(Address(rsp, 0)); 3650 #endif // LP64 3651 } 3652 3653 void MacroAssembler::push_IU_state() { 3654 // Push flags first because pusha kills them 3655 pushf(); 3656 // Make sure rsp stays 16-byte aligned 3657 LP64_ONLY(subq(rsp, 8)); 3658 pusha(); 3659 } 3660 3661 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3662 if (!java_thread->is_valid()) { 3663 java_thread = rdi; 3664 get_thread(java_thread); 3665 } 3666 // we must set sp to zero to clear frame 3667 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3668 if (clear_fp) { 3669 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3670 } 3671 3672 // Always clear the pc because it could have been set by make_walkable() 3673 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3674 3675 } 3676 3677 void MacroAssembler::restore_rax(Register tmp) { 3678 if (tmp == noreg) pop(rax); 3679 else if (tmp != rax) mov(rax, tmp); 3680 } 3681 3682 void MacroAssembler::round_to(Register reg, int modulus) { 3683 addptr(reg, modulus - 1); 3684 andptr(reg, -modulus); 3685 } 3686 3687 void MacroAssembler::save_rax(Register tmp) { 3688 if (tmp == noreg) push(rax); 3689 else if (tmp != rax) mov(tmp, rax); 3690 } 3691 3692 // Write serialization page so VM thread can do a pseudo remote membar. 3693 // We use the current thread pointer to calculate a thread specific 3694 // offset to write to within the page. This minimizes bus traffic 3695 // due to cache line collision. 3696 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3697 movl(tmp, thread); 3698 shrl(tmp, os::get_serialize_page_shift_count()); 3699 andl(tmp, (os::vm_page_size() - sizeof(int))); 3700 3701 Address index(noreg, tmp, Address::times_1); 3702 ExternalAddress page(os::get_memory_serialize_page()); 3703 3704 // Size of store must match masking code above 3705 movl(as_Address(ArrayAddress(page, index)), tmp); 3706 } 3707 3708 // Calls to C land 3709 // 3710 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3711 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3712 // has to be reset to 0. This is required to allow proper stack traversal. 3713 void MacroAssembler::set_last_Java_frame(Register java_thread, 3714 Register last_java_sp, 3715 Register last_java_fp, 3716 address last_java_pc) { 3717 // determine java_thread register 3718 if (!java_thread->is_valid()) { 3719 java_thread = rdi; 3720 get_thread(java_thread); 3721 } 3722 // determine last_java_sp register 3723 if (!last_java_sp->is_valid()) { 3724 last_java_sp = rsp; 3725 } 3726 3727 // last_java_fp is optional 3728 3729 if (last_java_fp->is_valid()) { 3730 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3731 } 3732 3733 // last_java_pc is optional 3734 3735 if (last_java_pc != NULL) { 3736 lea(Address(java_thread, 3737 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3738 InternalAddress(last_java_pc)); 3739 3740 } 3741 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3742 } 3743 3744 void MacroAssembler::shlptr(Register dst, int imm8) { 3745 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3746 } 3747 3748 void MacroAssembler::shrptr(Register dst, int imm8) { 3749 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3750 } 3751 3752 void MacroAssembler::sign_extend_byte(Register reg) { 3753 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3754 movsbl(reg, reg); // movsxb 3755 } else { 3756 shll(reg, 24); 3757 sarl(reg, 24); 3758 } 3759 } 3760 3761 void MacroAssembler::sign_extend_short(Register reg) { 3762 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3763 movswl(reg, reg); // movsxw 3764 } else { 3765 shll(reg, 16); 3766 sarl(reg, 16); 3767 } 3768 } 3769 3770 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3771 assert(reachable(src), "Address should be reachable"); 3772 testl(dst, as_Address(src)); 3773 } 3774 3775 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3776 int dst_enc = dst->encoding(); 3777 int src_enc = src->encoding(); 3778 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3779 Assembler::pcmpeqb(dst, src); 3780 } else if ((dst_enc < 16) && (src_enc < 16)) { 3781 Assembler::pcmpeqb(dst, src); 3782 } else if (src_enc < 16) { 3783 subptr(rsp, 64); 3784 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3785 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3786 Assembler::pcmpeqb(xmm0, src); 3787 movdqu(dst, xmm0); 3788 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3789 addptr(rsp, 64); 3790 } else if (dst_enc < 16) { 3791 subptr(rsp, 64); 3792 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3793 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3794 Assembler::pcmpeqb(dst, xmm0); 3795 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3796 addptr(rsp, 64); 3797 } else { 3798 subptr(rsp, 64); 3799 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3800 subptr(rsp, 64); 3801 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3802 movdqu(xmm0, src); 3803 movdqu(xmm1, dst); 3804 Assembler::pcmpeqb(xmm1, xmm0); 3805 movdqu(dst, xmm1); 3806 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3807 addptr(rsp, 64); 3808 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3809 addptr(rsp, 64); 3810 } 3811 } 3812 3813 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3814 int dst_enc = dst->encoding(); 3815 int src_enc = src->encoding(); 3816 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3817 Assembler::pcmpeqw(dst, src); 3818 } else if ((dst_enc < 16) && (src_enc < 16)) { 3819 Assembler::pcmpeqw(dst, src); 3820 } else if (src_enc < 16) { 3821 subptr(rsp, 64); 3822 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3823 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3824 Assembler::pcmpeqw(xmm0, src); 3825 movdqu(dst, xmm0); 3826 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3827 addptr(rsp, 64); 3828 } else if (dst_enc < 16) { 3829 subptr(rsp, 64); 3830 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3831 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3832 Assembler::pcmpeqw(dst, xmm0); 3833 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3834 addptr(rsp, 64); 3835 } else { 3836 subptr(rsp, 64); 3837 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3838 subptr(rsp, 64); 3839 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3840 movdqu(xmm0, src); 3841 movdqu(xmm1, dst); 3842 Assembler::pcmpeqw(xmm1, xmm0); 3843 movdqu(dst, xmm1); 3844 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3845 addptr(rsp, 64); 3846 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3847 addptr(rsp, 64); 3848 } 3849 } 3850 3851 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3852 int dst_enc = dst->encoding(); 3853 if (dst_enc < 16) { 3854 Assembler::pcmpestri(dst, src, imm8); 3855 } else { 3856 subptr(rsp, 64); 3857 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3858 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3859 Assembler::pcmpestri(xmm0, src, imm8); 3860 movdqu(dst, xmm0); 3861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3862 addptr(rsp, 64); 3863 } 3864 } 3865 3866 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3867 int dst_enc = dst->encoding(); 3868 int src_enc = src->encoding(); 3869 if ((dst_enc < 16) && (src_enc < 16)) { 3870 Assembler::pcmpestri(dst, src, imm8); 3871 } else if (src_enc < 16) { 3872 subptr(rsp, 64); 3873 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3874 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3875 Assembler::pcmpestri(xmm0, src, imm8); 3876 movdqu(dst, xmm0); 3877 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3878 addptr(rsp, 64); 3879 } else if (dst_enc < 16) { 3880 subptr(rsp, 64); 3881 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3882 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3883 Assembler::pcmpestri(dst, xmm0, imm8); 3884 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3885 addptr(rsp, 64); 3886 } else { 3887 subptr(rsp, 64); 3888 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3889 subptr(rsp, 64); 3890 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3891 movdqu(xmm0, src); 3892 movdqu(xmm1, dst); 3893 Assembler::pcmpestri(xmm1, xmm0, imm8); 3894 movdqu(dst, xmm1); 3895 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3896 addptr(rsp, 64); 3897 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3898 addptr(rsp, 64); 3899 } 3900 } 3901 3902 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3903 int dst_enc = dst->encoding(); 3904 int src_enc = src->encoding(); 3905 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3906 Assembler::pmovzxbw(dst, src); 3907 } else if ((dst_enc < 16) && (src_enc < 16)) { 3908 Assembler::pmovzxbw(dst, src); 3909 } else if (src_enc < 16) { 3910 subptr(rsp, 64); 3911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3912 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3913 Assembler::pmovzxbw(xmm0, src); 3914 movdqu(dst, xmm0); 3915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3916 addptr(rsp, 64); 3917 } else if (dst_enc < 16) { 3918 subptr(rsp, 64); 3919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3920 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3921 Assembler::pmovzxbw(dst, xmm0); 3922 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3923 addptr(rsp, 64); 3924 } else { 3925 subptr(rsp, 64); 3926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3927 subptr(rsp, 64); 3928 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3929 movdqu(xmm0, src); 3930 movdqu(xmm1, dst); 3931 Assembler::pmovzxbw(xmm1, xmm0); 3932 movdqu(dst, xmm1); 3933 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3934 addptr(rsp, 64); 3935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3936 addptr(rsp, 64); 3937 } 3938 } 3939 3940 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3941 int dst_enc = dst->encoding(); 3942 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3943 Assembler::pmovzxbw(dst, src); 3944 } else if (dst_enc < 16) { 3945 Assembler::pmovzxbw(dst, src); 3946 } else { 3947 subptr(rsp, 64); 3948 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3949 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3950 Assembler::pmovzxbw(xmm0, src); 3951 movdqu(dst, xmm0); 3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3953 addptr(rsp, 64); 3954 } 3955 } 3956 3957 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3958 int src_enc = src->encoding(); 3959 if (src_enc < 16) { 3960 Assembler::pmovmskb(dst, src); 3961 } else { 3962 subptr(rsp, 64); 3963 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3964 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3965 Assembler::pmovmskb(dst, xmm0); 3966 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3967 addptr(rsp, 64); 3968 } 3969 } 3970 3971 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3972 int dst_enc = dst->encoding(); 3973 int src_enc = src->encoding(); 3974 if ((dst_enc < 16) && (src_enc < 16)) { 3975 Assembler::ptest(dst, src); 3976 } else if (src_enc < 16) { 3977 subptr(rsp, 64); 3978 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3979 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3980 Assembler::ptest(xmm0, src); 3981 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3982 addptr(rsp, 64); 3983 } else if (dst_enc < 16) { 3984 subptr(rsp, 64); 3985 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3986 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3987 Assembler::ptest(dst, xmm0); 3988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3989 addptr(rsp, 64); 3990 } else { 3991 subptr(rsp, 64); 3992 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3993 subptr(rsp, 64); 3994 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3995 movdqu(xmm0, src); 3996 movdqu(xmm1, dst); 3997 Assembler::ptest(xmm1, xmm0); 3998 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3999 addptr(rsp, 64); 4000 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4001 addptr(rsp, 64); 4002 } 4003 } 4004 4005 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4006 if (reachable(src)) { 4007 Assembler::sqrtsd(dst, as_Address(src)); 4008 } else { 4009 lea(rscratch1, src); 4010 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4011 } 4012 } 4013 4014 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4015 if (reachable(src)) { 4016 Assembler::sqrtss(dst, as_Address(src)); 4017 } else { 4018 lea(rscratch1, src); 4019 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4020 } 4021 } 4022 4023 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4024 if (reachable(src)) { 4025 Assembler::subsd(dst, as_Address(src)); 4026 } else { 4027 lea(rscratch1, src); 4028 Assembler::subsd(dst, Address(rscratch1, 0)); 4029 } 4030 } 4031 4032 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4033 if (reachable(src)) { 4034 Assembler::subss(dst, as_Address(src)); 4035 } else { 4036 lea(rscratch1, src); 4037 Assembler::subss(dst, Address(rscratch1, 0)); 4038 } 4039 } 4040 4041 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4042 if (reachable(src)) { 4043 Assembler::ucomisd(dst, as_Address(src)); 4044 } else { 4045 lea(rscratch1, src); 4046 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4047 } 4048 } 4049 4050 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4051 if (reachable(src)) { 4052 Assembler::ucomiss(dst, as_Address(src)); 4053 } else { 4054 lea(rscratch1, src); 4055 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4056 } 4057 } 4058 4059 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4060 // Used in sign-bit flipping with aligned address. 4061 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4062 if (reachable(src)) { 4063 Assembler::xorpd(dst, as_Address(src)); 4064 } else { 4065 lea(rscratch1, src); 4066 Assembler::xorpd(dst, Address(rscratch1, 0)); 4067 } 4068 } 4069 4070 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4071 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4072 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4073 } 4074 else { 4075 Assembler::xorpd(dst, src); 4076 } 4077 } 4078 4079 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4080 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4081 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4082 } else { 4083 Assembler::xorps(dst, src); 4084 } 4085 } 4086 4087 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4088 // Used in sign-bit flipping with aligned address. 4089 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4090 if (reachable(src)) { 4091 Assembler::xorps(dst, as_Address(src)); 4092 } else { 4093 lea(rscratch1, src); 4094 Assembler::xorps(dst, Address(rscratch1, 0)); 4095 } 4096 } 4097 4098 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4099 // Used in sign-bit flipping with aligned address. 4100 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4101 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4102 if (reachable(src)) { 4103 Assembler::pshufb(dst, as_Address(src)); 4104 } else { 4105 lea(rscratch1, src); 4106 Assembler::pshufb(dst, Address(rscratch1, 0)); 4107 } 4108 } 4109 4110 // AVX 3-operands instructions 4111 4112 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4113 if (reachable(src)) { 4114 vaddsd(dst, nds, as_Address(src)); 4115 } else { 4116 lea(rscratch1, src); 4117 vaddsd(dst, nds, Address(rscratch1, 0)); 4118 } 4119 } 4120 4121 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4122 if (reachable(src)) { 4123 vaddss(dst, nds, as_Address(src)); 4124 } else { 4125 lea(rscratch1, src); 4126 vaddss(dst, nds, Address(rscratch1, 0)); 4127 } 4128 } 4129 4130 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4131 int dst_enc = dst->encoding(); 4132 int nds_enc = nds->encoding(); 4133 int src_enc = src->encoding(); 4134 if ((dst_enc < 16) && (nds_enc < 16)) { 4135 vandps(dst, nds, negate_field, vector_len); 4136 } else if ((src_enc < 16) && (dst_enc < 16)) { 4137 movss(src, nds); 4138 vandps(dst, src, negate_field, vector_len); 4139 } else if (src_enc < 16) { 4140 movss(src, nds); 4141 vandps(src, src, negate_field, vector_len); 4142 movss(dst, src); 4143 } else if (dst_enc < 16) { 4144 movdqu(src, xmm0); 4145 movss(xmm0, nds); 4146 vandps(dst, xmm0, negate_field, vector_len); 4147 movdqu(xmm0, src); 4148 } else if (nds_enc < 16) { 4149 movdqu(src, xmm0); 4150 vandps(xmm0, nds, negate_field, vector_len); 4151 movss(dst, xmm0); 4152 movdqu(xmm0, src); 4153 } else { 4154 movdqu(src, xmm0); 4155 movss(xmm0, nds); 4156 vandps(xmm0, xmm0, negate_field, vector_len); 4157 movss(dst, xmm0); 4158 movdqu(xmm0, src); 4159 } 4160 } 4161 4162 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4163 int dst_enc = dst->encoding(); 4164 int nds_enc = nds->encoding(); 4165 int src_enc = src->encoding(); 4166 if ((dst_enc < 16) && (nds_enc < 16)) { 4167 vandpd(dst, nds, negate_field, vector_len); 4168 } else if ((src_enc < 16) && (dst_enc < 16)) { 4169 movsd(src, nds); 4170 vandpd(dst, src, negate_field, vector_len); 4171 } else if (src_enc < 16) { 4172 movsd(src, nds); 4173 vandpd(src, src, negate_field, vector_len); 4174 movsd(dst, src); 4175 } else if (dst_enc < 16) { 4176 movdqu(src, xmm0); 4177 movsd(xmm0, nds); 4178 vandpd(dst, xmm0, negate_field, vector_len); 4179 movdqu(xmm0, src); 4180 } else if (nds_enc < 16) { 4181 movdqu(src, xmm0); 4182 vandpd(xmm0, nds, negate_field, vector_len); 4183 movsd(dst, xmm0); 4184 movdqu(xmm0, src); 4185 } else { 4186 movdqu(src, xmm0); 4187 movsd(xmm0, nds); 4188 vandpd(xmm0, xmm0, negate_field, vector_len); 4189 movsd(dst, xmm0); 4190 movdqu(xmm0, src); 4191 } 4192 } 4193 4194 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4195 int dst_enc = dst->encoding(); 4196 int nds_enc = nds->encoding(); 4197 int src_enc = src->encoding(); 4198 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4199 Assembler::vpaddb(dst, nds, src, vector_len); 4200 } else if ((dst_enc < 16) && (src_enc < 16)) { 4201 Assembler::vpaddb(dst, dst, src, vector_len); 4202 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4203 // use nds as scratch for src 4204 evmovdqul(nds, src, Assembler::AVX_512bit); 4205 Assembler::vpaddb(dst, dst, nds, vector_len); 4206 } else if ((src_enc < 16) && (nds_enc < 16)) { 4207 // use nds as scratch for dst 4208 evmovdqul(nds, dst, Assembler::AVX_512bit); 4209 Assembler::vpaddb(nds, nds, src, vector_len); 4210 evmovdqul(dst, nds, Assembler::AVX_512bit); 4211 } else if (dst_enc < 16) { 4212 // use nds as scatch for xmm0 to hold src 4213 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4214 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4215 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4216 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4217 } else { 4218 // worse case scenario, all regs are in the upper bank 4219 subptr(rsp, 64); 4220 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4221 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4222 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4223 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4224 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4225 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4226 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4227 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4228 addptr(rsp, 64); 4229 } 4230 } 4231 4232 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4233 int dst_enc = dst->encoding(); 4234 int nds_enc = nds->encoding(); 4235 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4236 Assembler::vpaddb(dst, nds, src, vector_len); 4237 } else if (dst_enc < 16) { 4238 Assembler::vpaddb(dst, dst, src, vector_len); 4239 } else if (nds_enc < 16) { 4240 // implies dst_enc in upper bank with src as scratch 4241 evmovdqul(nds, dst, Assembler::AVX_512bit); 4242 Assembler::vpaddb(nds, nds, src, vector_len); 4243 evmovdqul(dst, nds, Assembler::AVX_512bit); 4244 } else { 4245 // worse case scenario, all regs in upper bank 4246 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4247 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4248 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4249 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4250 } 4251 } 4252 4253 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4254 int dst_enc = dst->encoding(); 4255 int nds_enc = nds->encoding(); 4256 int src_enc = src->encoding(); 4257 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4258 Assembler::vpaddw(dst, nds, src, vector_len); 4259 } else if ((dst_enc < 16) && (src_enc < 16)) { 4260 Assembler::vpaddw(dst, dst, src, vector_len); 4261 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4262 // use nds as scratch for src 4263 evmovdqul(nds, src, Assembler::AVX_512bit); 4264 Assembler::vpaddw(dst, dst, nds, vector_len); 4265 } else if ((src_enc < 16) && (nds_enc < 16)) { 4266 // use nds as scratch for dst 4267 evmovdqul(nds, dst, Assembler::AVX_512bit); 4268 Assembler::vpaddw(nds, nds, src, vector_len); 4269 evmovdqul(dst, nds, Assembler::AVX_512bit); 4270 } else if (dst_enc < 16) { 4271 // use nds as scatch for xmm0 to hold src 4272 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4273 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4274 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4275 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4276 } else { 4277 // worse case scenario, all regs are in the upper bank 4278 subptr(rsp, 64); 4279 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4280 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4281 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4282 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4283 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4284 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4285 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4286 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4287 addptr(rsp, 64); 4288 } 4289 } 4290 4291 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4292 int dst_enc = dst->encoding(); 4293 int nds_enc = nds->encoding(); 4294 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4295 Assembler::vpaddw(dst, nds, src, vector_len); 4296 } else if (dst_enc < 16) { 4297 Assembler::vpaddw(dst, dst, src, vector_len); 4298 } else if (nds_enc < 16) { 4299 // implies dst_enc in upper bank with src as scratch 4300 evmovdqul(nds, dst, Assembler::AVX_512bit); 4301 Assembler::vpaddw(nds, nds, src, vector_len); 4302 evmovdqul(dst, nds, Assembler::AVX_512bit); 4303 } else { 4304 // worse case scenario, all regs in upper bank 4305 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4306 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4307 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4308 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4309 } 4310 } 4311 4312 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4313 int dst_enc = dst->encoding(); 4314 int src_enc = src->encoding(); 4315 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4316 Assembler::vpbroadcastw(dst, src); 4317 } else if ((dst_enc < 16) && (src_enc < 16)) { 4318 Assembler::vpbroadcastw(dst, src); 4319 } else if (src_enc < 16) { 4320 subptr(rsp, 64); 4321 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4322 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4323 Assembler::vpbroadcastw(xmm0, src); 4324 movdqu(dst, xmm0); 4325 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4326 addptr(rsp, 64); 4327 } else if (dst_enc < 16) { 4328 subptr(rsp, 64); 4329 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4330 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4331 Assembler::vpbroadcastw(dst, xmm0); 4332 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4333 addptr(rsp, 64); 4334 } else { 4335 subptr(rsp, 64); 4336 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4337 subptr(rsp, 64); 4338 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4339 movdqu(xmm0, src); 4340 movdqu(xmm1, dst); 4341 Assembler::vpbroadcastw(xmm1, xmm0); 4342 movdqu(dst, xmm1); 4343 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4344 addptr(rsp, 64); 4345 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4346 addptr(rsp, 64); 4347 } 4348 } 4349 4350 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4351 int dst_enc = dst->encoding(); 4352 int nds_enc = nds->encoding(); 4353 int src_enc = src->encoding(); 4354 assert(dst_enc == nds_enc, ""); 4355 if ((dst_enc < 16) && (src_enc < 16)) { 4356 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4357 } else if (src_enc < 16) { 4358 subptr(rsp, 64); 4359 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4360 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4361 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4362 movdqu(dst, xmm0); 4363 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4364 addptr(rsp, 64); 4365 } else if (dst_enc < 16) { 4366 subptr(rsp, 64); 4367 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4368 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4369 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4370 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4371 addptr(rsp, 64); 4372 } else { 4373 subptr(rsp, 64); 4374 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4375 subptr(rsp, 64); 4376 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4377 movdqu(xmm0, src); 4378 movdqu(xmm1, dst); 4379 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4380 movdqu(dst, xmm1); 4381 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4382 addptr(rsp, 64); 4383 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4384 addptr(rsp, 64); 4385 } 4386 } 4387 4388 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4389 int dst_enc = dst->encoding(); 4390 int nds_enc = nds->encoding(); 4391 int src_enc = src->encoding(); 4392 assert(dst_enc == nds_enc, ""); 4393 if ((dst_enc < 16) && (src_enc < 16)) { 4394 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4395 } else if (src_enc < 16) { 4396 subptr(rsp, 64); 4397 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4398 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4399 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4400 movdqu(dst, xmm0); 4401 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4402 addptr(rsp, 64); 4403 } else if (dst_enc < 16) { 4404 subptr(rsp, 64); 4405 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4406 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4407 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4408 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4409 addptr(rsp, 64); 4410 } else { 4411 subptr(rsp, 64); 4412 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4413 subptr(rsp, 64); 4414 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4415 movdqu(xmm0, src); 4416 movdqu(xmm1, dst); 4417 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4418 movdqu(dst, xmm1); 4419 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4420 addptr(rsp, 64); 4421 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4422 addptr(rsp, 64); 4423 } 4424 } 4425 4426 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4427 int dst_enc = dst->encoding(); 4428 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4429 Assembler::vpmovzxbw(dst, src, vector_len); 4430 } else if (dst_enc < 16) { 4431 Assembler::vpmovzxbw(dst, src, vector_len); 4432 } else { 4433 subptr(rsp, 64); 4434 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4435 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4436 Assembler::vpmovzxbw(xmm0, src, vector_len); 4437 movdqu(dst, xmm0); 4438 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4439 addptr(rsp, 64); 4440 } 4441 } 4442 4443 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4444 int src_enc = src->encoding(); 4445 if (src_enc < 16) { 4446 Assembler::vpmovmskb(dst, src); 4447 } else { 4448 subptr(rsp, 64); 4449 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4450 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4451 Assembler::vpmovmskb(dst, xmm0); 4452 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4453 addptr(rsp, 64); 4454 } 4455 } 4456 4457 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4458 int dst_enc = dst->encoding(); 4459 int nds_enc = nds->encoding(); 4460 int src_enc = src->encoding(); 4461 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4462 Assembler::vpmullw(dst, nds, src, vector_len); 4463 } else if ((dst_enc < 16) && (src_enc < 16)) { 4464 Assembler::vpmullw(dst, dst, src, vector_len); 4465 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4466 // use nds as scratch for src 4467 evmovdqul(nds, src, Assembler::AVX_512bit); 4468 Assembler::vpmullw(dst, dst, nds, vector_len); 4469 } else if ((src_enc < 16) && (nds_enc < 16)) { 4470 // use nds as scratch for dst 4471 evmovdqul(nds, dst, Assembler::AVX_512bit); 4472 Assembler::vpmullw(nds, nds, src, vector_len); 4473 evmovdqul(dst, nds, Assembler::AVX_512bit); 4474 } else if (dst_enc < 16) { 4475 // use nds as scatch for xmm0 to hold src 4476 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4477 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4478 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4479 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4480 } else { 4481 // worse case scenario, all regs are in the upper bank 4482 subptr(rsp, 64); 4483 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4484 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4485 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4486 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4487 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4488 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4489 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4490 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4491 addptr(rsp, 64); 4492 } 4493 } 4494 4495 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4496 int dst_enc = dst->encoding(); 4497 int nds_enc = nds->encoding(); 4498 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4499 Assembler::vpmullw(dst, nds, src, vector_len); 4500 } else if (dst_enc < 16) { 4501 Assembler::vpmullw(dst, dst, src, vector_len); 4502 } else if (nds_enc < 16) { 4503 // implies dst_enc in upper bank with src as scratch 4504 evmovdqul(nds, dst, Assembler::AVX_512bit); 4505 Assembler::vpmullw(nds, nds, src, vector_len); 4506 evmovdqul(dst, nds, Assembler::AVX_512bit); 4507 } else { 4508 // worse case scenario, all regs in upper bank 4509 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4510 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4511 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4512 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4513 } 4514 } 4515 4516 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4517 int dst_enc = dst->encoding(); 4518 int nds_enc = nds->encoding(); 4519 int src_enc = src->encoding(); 4520 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4521 Assembler::vpsubb(dst, nds, src, vector_len); 4522 } else if ((dst_enc < 16) && (src_enc < 16)) { 4523 Assembler::vpsubb(dst, dst, src, vector_len); 4524 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4525 // use nds as scratch for src 4526 evmovdqul(nds, src, Assembler::AVX_512bit); 4527 Assembler::vpsubb(dst, dst, nds, vector_len); 4528 } else if ((src_enc < 16) && (nds_enc < 16)) { 4529 // use nds as scratch for dst 4530 evmovdqul(nds, dst, Assembler::AVX_512bit); 4531 Assembler::vpsubb(nds, nds, src, vector_len); 4532 evmovdqul(dst, nds, Assembler::AVX_512bit); 4533 } else if (dst_enc < 16) { 4534 // use nds as scatch for xmm0 to hold src 4535 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4536 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4537 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4538 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4539 } else { 4540 // worse case scenario, all regs are in the upper bank 4541 subptr(rsp, 64); 4542 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4543 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4544 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4545 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4546 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4547 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4548 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4549 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4550 addptr(rsp, 64); 4551 } 4552 } 4553 4554 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4555 int dst_enc = dst->encoding(); 4556 int nds_enc = nds->encoding(); 4557 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4558 Assembler::vpsubb(dst, nds, src, vector_len); 4559 } else if (dst_enc < 16) { 4560 Assembler::vpsubb(dst, dst, src, vector_len); 4561 } else if (nds_enc < 16) { 4562 // implies dst_enc in upper bank with src as scratch 4563 evmovdqul(nds, dst, Assembler::AVX_512bit); 4564 Assembler::vpsubb(nds, nds, src, vector_len); 4565 evmovdqul(dst, nds, Assembler::AVX_512bit); 4566 } else { 4567 // worse case scenario, all regs in upper bank 4568 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4569 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4570 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4571 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4572 } 4573 } 4574 4575 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4576 int dst_enc = dst->encoding(); 4577 int nds_enc = nds->encoding(); 4578 int src_enc = src->encoding(); 4579 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4580 Assembler::vpsubw(dst, nds, src, vector_len); 4581 } else if ((dst_enc < 16) && (src_enc < 16)) { 4582 Assembler::vpsubw(dst, dst, src, vector_len); 4583 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4584 // use nds as scratch for src 4585 evmovdqul(nds, src, Assembler::AVX_512bit); 4586 Assembler::vpsubw(dst, dst, nds, vector_len); 4587 } else if ((src_enc < 16) && (nds_enc < 16)) { 4588 // use nds as scratch for dst 4589 evmovdqul(nds, dst, Assembler::AVX_512bit); 4590 Assembler::vpsubw(nds, nds, src, vector_len); 4591 evmovdqul(dst, nds, Assembler::AVX_512bit); 4592 } else if (dst_enc < 16) { 4593 // use nds as scatch for xmm0 to hold src 4594 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4595 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4596 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4597 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4598 } else { 4599 // worse case scenario, all regs are in the upper bank 4600 subptr(rsp, 64); 4601 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4602 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4603 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4604 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4605 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4606 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4607 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4608 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4609 addptr(rsp, 64); 4610 } 4611 } 4612 4613 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4614 int dst_enc = dst->encoding(); 4615 int nds_enc = nds->encoding(); 4616 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4617 Assembler::vpsubw(dst, nds, src, vector_len); 4618 } else if (dst_enc < 16) { 4619 Assembler::vpsubw(dst, dst, src, vector_len); 4620 } else if (nds_enc < 16) { 4621 // implies dst_enc in upper bank with src as scratch 4622 evmovdqul(nds, dst, Assembler::AVX_512bit); 4623 Assembler::vpsubw(nds, nds, src, vector_len); 4624 evmovdqul(dst, nds, Assembler::AVX_512bit); 4625 } else { 4626 // worse case scenario, all regs in upper bank 4627 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4628 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4629 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4630 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4631 } 4632 } 4633 4634 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4635 int dst_enc = dst->encoding(); 4636 int nds_enc = nds->encoding(); 4637 int shift_enc = shift->encoding(); 4638 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4639 Assembler::vpsraw(dst, nds, shift, vector_len); 4640 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4641 Assembler::vpsraw(dst, dst, shift, vector_len); 4642 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4643 // use nds_enc as scratch with shift 4644 evmovdqul(nds, shift, Assembler::AVX_512bit); 4645 Assembler::vpsraw(dst, dst, nds, vector_len); 4646 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4647 // use nds as scratch with dst 4648 evmovdqul(nds, dst, Assembler::AVX_512bit); 4649 Assembler::vpsraw(nds, nds, shift, vector_len); 4650 evmovdqul(dst, nds, Assembler::AVX_512bit); 4651 } else if (dst_enc < 16) { 4652 // use nds to save a copy of xmm0 and hold shift 4653 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4654 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4655 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4656 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4657 } else if (nds_enc < 16) { 4658 // use nds as dest as temps 4659 evmovdqul(nds, dst, Assembler::AVX_512bit); 4660 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4661 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4662 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4663 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4664 evmovdqul(dst, nds, Assembler::AVX_512bit); 4665 } else { 4666 // worse case scenario, all regs are in the upper bank 4667 subptr(rsp, 64); 4668 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4669 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4670 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4671 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4672 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4673 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4674 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4675 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4676 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4677 addptr(rsp, 64); 4678 } 4679 } 4680 4681 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4682 int dst_enc = dst->encoding(); 4683 int nds_enc = nds->encoding(); 4684 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4685 Assembler::vpsraw(dst, nds, shift, vector_len); 4686 } else if (dst_enc < 16) { 4687 Assembler::vpsraw(dst, dst, shift, vector_len); 4688 } else if (nds_enc < 16) { 4689 // use nds as scratch 4690 evmovdqul(nds, dst, Assembler::AVX_512bit); 4691 Assembler::vpsraw(nds, nds, shift, vector_len); 4692 evmovdqul(dst, nds, Assembler::AVX_512bit); 4693 } else { 4694 // use nds as scratch for xmm0 4695 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4696 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4697 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4698 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4699 } 4700 } 4701 4702 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4703 int dst_enc = dst->encoding(); 4704 int nds_enc = nds->encoding(); 4705 int shift_enc = shift->encoding(); 4706 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4707 Assembler::vpsrlw(dst, nds, shift, vector_len); 4708 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4709 Assembler::vpsrlw(dst, dst, shift, vector_len); 4710 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4711 // use nds_enc as scratch with shift 4712 evmovdqul(nds, shift, Assembler::AVX_512bit); 4713 Assembler::vpsrlw(dst, dst, nds, vector_len); 4714 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4715 // use nds as scratch with dst 4716 evmovdqul(nds, dst, Assembler::AVX_512bit); 4717 Assembler::vpsrlw(nds, nds, shift, vector_len); 4718 evmovdqul(dst, nds, Assembler::AVX_512bit); 4719 } else if (dst_enc < 16) { 4720 // use nds to save a copy of xmm0 and hold shift 4721 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4722 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4723 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4724 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4725 } else if (nds_enc < 16) { 4726 // use nds as dest as temps 4727 evmovdqul(nds, dst, Assembler::AVX_512bit); 4728 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4729 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4730 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4731 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4732 evmovdqul(dst, nds, Assembler::AVX_512bit); 4733 } else { 4734 // worse case scenario, all regs are in the upper bank 4735 subptr(rsp, 64); 4736 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4737 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4738 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4739 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4740 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4741 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4742 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4743 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4744 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4745 addptr(rsp, 64); 4746 } 4747 } 4748 4749 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4750 int dst_enc = dst->encoding(); 4751 int nds_enc = nds->encoding(); 4752 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4753 Assembler::vpsrlw(dst, nds, shift, vector_len); 4754 } else if (dst_enc < 16) { 4755 Assembler::vpsrlw(dst, dst, shift, vector_len); 4756 } else if (nds_enc < 16) { 4757 // use nds as scratch 4758 evmovdqul(nds, dst, Assembler::AVX_512bit); 4759 Assembler::vpsrlw(nds, nds, shift, vector_len); 4760 evmovdqul(dst, nds, Assembler::AVX_512bit); 4761 } else { 4762 // use nds as scratch for xmm0 4763 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4764 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4765 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4766 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4767 } 4768 } 4769 4770 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4771 int dst_enc = dst->encoding(); 4772 int nds_enc = nds->encoding(); 4773 int shift_enc = shift->encoding(); 4774 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4775 Assembler::vpsllw(dst, nds, shift, vector_len); 4776 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4777 Assembler::vpsllw(dst, dst, shift, vector_len); 4778 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4779 // use nds_enc as scratch with shift 4780 evmovdqul(nds, shift, Assembler::AVX_512bit); 4781 Assembler::vpsllw(dst, dst, nds, vector_len); 4782 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4783 // use nds as scratch with dst 4784 evmovdqul(nds, dst, Assembler::AVX_512bit); 4785 Assembler::vpsllw(nds, nds, shift, vector_len); 4786 evmovdqul(dst, nds, Assembler::AVX_512bit); 4787 } else if (dst_enc < 16) { 4788 // use nds to save a copy of xmm0 and hold shift 4789 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4790 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4791 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4792 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4793 } else if (nds_enc < 16) { 4794 // use nds as dest as temps 4795 evmovdqul(nds, dst, Assembler::AVX_512bit); 4796 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4797 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4798 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4799 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4800 evmovdqul(dst, nds, Assembler::AVX_512bit); 4801 } else { 4802 // worse case scenario, all regs are in the upper bank 4803 subptr(rsp, 64); 4804 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4805 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4806 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4807 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4808 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4809 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4810 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4811 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4812 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4813 addptr(rsp, 64); 4814 } 4815 } 4816 4817 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4818 int dst_enc = dst->encoding(); 4819 int nds_enc = nds->encoding(); 4820 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4821 Assembler::vpsllw(dst, nds, shift, vector_len); 4822 } else if (dst_enc < 16) { 4823 Assembler::vpsllw(dst, dst, shift, vector_len); 4824 } else if (nds_enc < 16) { 4825 // use nds as scratch 4826 evmovdqul(nds, dst, Assembler::AVX_512bit); 4827 Assembler::vpsllw(nds, nds, shift, vector_len); 4828 evmovdqul(dst, nds, Assembler::AVX_512bit); 4829 } else { 4830 // use nds as scratch for xmm0 4831 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4832 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4833 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4834 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4835 } 4836 } 4837 4838 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4839 int dst_enc = dst->encoding(); 4840 int src_enc = src->encoding(); 4841 if ((dst_enc < 16) && (src_enc < 16)) { 4842 Assembler::vptest(dst, src); 4843 } else if (src_enc < 16) { 4844 subptr(rsp, 64); 4845 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4846 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4847 Assembler::vptest(xmm0, src); 4848 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4849 addptr(rsp, 64); 4850 } else if (dst_enc < 16) { 4851 subptr(rsp, 64); 4852 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4853 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4854 Assembler::vptest(dst, xmm0); 4855 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4856 addptr(rsp, 64); 4857 } else { 4858 subptr(rsp, 64); 4859 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4860 subptr(rsp, 64); 4861 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4862 movdqu(xmm0, src); 4863 movdqu(xmm1, dst); 4864 Assembler::vptest(xmm1, xmm0); 4865 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4866 addptr(rsp, 64); 4867 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4868 addptr(rsp, 64); 4869 } 4870 } 4871 4872 // This instruction exists within macros, ergo we cannot control its input 4873 // when emitted through those patterns. 4874 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4875 if (VM_Version::supports_avx512nobw()) { 4876 int dst_enc = dst->encoding(); 4877 int src_enc = src->encoding(); 4878 if (dst_enc == src_enc) { 4879 if (dst_enc < 16) { 4880 Assembler::punpcklbw(dst, src); 4881 } else { 4882 subptr(rsp, 64); 4883 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4884 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4885 Assembler::punpcklbw(xmm0, xmm0); 4886 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4887 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4888 addptr(rsp, 64); 4889 } 4890 } else { 4891 if ((src_enc < 16) && (dst_enc < 16)) { 4892 Assembler::punpcklbw(dst, src); 4893 } else if (src_enc < 16) { 4894 subptr(rsp, 64); 4895 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4896 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4897 Assembler::punpcklbw(xmm0, src); 4898 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4899 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4900 addptr(rsp, 64); 4901 } else if (dst_enc < 16) { 4902 subptr(rsp, 64); 4903 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4904 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4905 Assembler::punpcklbw(dst, xmm0); 4906 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4907 addptr(rsp, 64); 4908 } else { 4909 subptr(rsp, 64); 4910 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4911 subptr(rsp, 64); 4912 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4913 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4914 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4915 Assembler::punpcklbw(xmm0, xmm1); 4916 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4917 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4918 addptr(rsp, 64); 4919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4920 addptr(rsp, 64); 4921 } 4922 } 4923 } else { 4924 Assembler::punpcklbw(dst, src); 4925 } 4926 } 4927 4928 // This instruction exists within macros, ergo we cannot control its input 4929 // when emitted through those patterns. 4930 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4931 if (VM_Version::supports_avx512nobw()) { 4932 int dst_enc = dst->encoding(); 4933 int src_enc = src->encoding(); 4934 if (dst_enc == src_enc) { 4935 if (dst_enc < 16) { 4936 Assembler::pshuflw(dst, src, mode); 4937 } else { 4938 subptr(rsp, 64); 4939 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4940 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4941 Assembler::pshuflw(xmm0, xmm0, mode); 4942 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4943 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4944 addptr(rsp, 64); 4945 } 4946 } else { 4947 if ((src_enc < 16) && (dst_enc < 16)) { 4948 Assembler::pshuflw(dst, src, mode); 4949 } else if (src_enc < 16) { 4950 subptr(rsp, 64); 4951 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4952 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4953 Assembler::pshuflw(xmm0, src, mode); 4954 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4955 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4956 addptr(rsp, 64); 4957 } else if (dst_enc < 16) { 4958 subptr(rsp, 64); 4959 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4960 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4961 Assembler::pshuflw(dst, xmm0, mode); 4962 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4963 addptr(rsp, 64); 4964 } else { 4965 subptr(rsp, 64); 4966 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4967 subptr(rsp, 64); 4968 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4969 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4970 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4971 Assembler::pshuflw(xmm0, xmm1, mode); 4972 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4973 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4974 addptr(rsp, 64); 4975 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4976 addptr(rsp, 64); 4977 } 4978 } 4979 } else { 4980 Assembler::pshuflw(dst, src, mode); 4981 } 4982 } 4983 4984 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4985 if (reachable(src)) { 4986 vandpd(dst, nds, as_Address(src), vector_len); 4987 } else { 4988 lea(rscratch1, src); 4989 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4990 } 4991 } 4992 4993 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4994 if (reachable(src)) { 4995 vandps(dst, nds, as_Address(src), vector_len); 4996 } else { 4997 lea(rscratch1, src); 4998 vandps(dst, nds, Address(rscratch1, 0), vector_len); 4999 } 5000 } 5001 5002 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5003 if (reachable(src)) { 5004 vdivsd(dst, nds, as_Address(src)); 5005 } else { 5006 lea(rscratch1, src); 5007 vdivsd(dst, nds, Address(rscratch1, 0)); 5008 } 5009 } 5010 5011 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5012 if (reachable(src)) { 5013 vdivss(dst, nds, as_Address(src)); 5014 } else { 5015 lea(rscratch1, src); 5016 vdivss(dst, nds, Address(rscratch1, 0)); 5017 } 5018 } 5019 5020 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5021 if (reachable(src)) { 5022 vmulsd(dst, nds, as_Address(src)); 5023 } else { 5024 lea(rscratch1, src); 5025 vmulsd(dst, nds, Address(rscratch1, 0)); 5026 } 5027 } 5028 5029 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5030 if (reachable(src)) { 5031 vmulss(dst, nds, as_Address(src)); 5032 } else { 5033 lea(rscratch1, src); 5034 vmulss(dst, nds, Address(rscratch1, 0)); 5035 } 5036 } 5037 5038 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5039 if (reachable(src)) { 5040 vsubsd(dst, nds, as_Address(src)); 5041 } else { 5042 lea(rscratch1, src); 5043 vsubsd(dst, nds, Address(rscratch1, 0)); 5044 } 5045 } 5046 5047 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5048 if (reachable(src)) { 5049 vsubss(dst, nds, as_Address(src)); 5050 } else { 5051 lea(rscratch1, src); 5052 vsubss(dst, nds, Address(rscratch1, 0)); 5053 } 5054 } 5055 5056 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5057 int nds_enc = nds->encoding(); 5058 int dst_enc = dst->encoding(); 5059 bool dst_upper_bank = (dst_enc > 15); 5060 bool nds_upper_bank = (nds_enc > 15); 5061 if (VM_Version::supports_avx512novl() && 5062 (nds_upper_bank || dst_upper_bank)) { 5063 if (dst_upper_bank) { 5064 subptr(rsp, 64); 5065 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5066 movflt(xmm0, nds); 5067 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5068 movflt(dst, xmm0); 5069 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5070 addptr(rsp, 64); 5071 } else { 5072 movflt(dst, nds); 5073 vxorps(dst, dst, src, Assembler::AVX_128bit); 5074 } 5075 } else { 5076 vxorps(dst, nds, src, Assembler::AVX_128bit); 5077 } 5078 } 5079 5080 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5081 int nds_enc = nds->encoding(); 5082 int dst_enc = dst->encoding(); 5083 bool dst_upper_bank = (dst_enc > 15); 5084 bool nds_upper_bank = (nds_enc > 15); 5085 if (VM_Version::supports_avx512novl() && 5086 (nds_upper_bank || dst_upper_bank)) { 5087 if (dst_upper_bank) { 5088 subptr(rsp, 64); 5089 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5090 movdbl(xmm0, nds); 5091 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5092 movdbl(dst, xmm0); 5093 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5094 addptr(rsp, 64); 5095 } else { 5096 movdbl(dst, nds); 5097 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5098 } 5099 } else { 5100 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5101 } 5102 } 5103 5104 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5105 if (reachable(src)) { 5106 vxorpd(dst, nds, as_Address(src), vector_len); 5107 } else { 5108 lea(rscratch1, src); 5109 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5110 } 5111 } 5112 5113 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5114 if (reachable(src)) { 5115 vxorps(dst, nds, as_Address(src), vector_len); 5116 } else { 5117 lea(rscratch1, src); 5118 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5119 } 5120 } 5121 5122 5123 ////////////////////////////////////////////////////////////////////////////////// 5124 #if INCLUDE_ALL_GCS 5125 5126 void MacroAssembler::g1_write_barrier_pre(Register obj, 5127 Register pre_val, 5128 Register thread, 5129 Register tmp, 5130 bool tosca_live, 5131 bool expand_call) { 5132 5133 // If expand_call is true then we expand the call_VM_leaf macro 5134 // directly to skip generating the check by 5135 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5136 5137 #ifdef _LP64 5138 assert(thread == r15_thread, "must be"); 5139 #endif // _LP64 5140 5141 Label done; 5142 Label runtime; 5143 5144 assert(pre_val != noreg, "check this code"); 5145 5146 if (obj != noreg) { 5147 assert_different_registers(obj, pre_val, tmp); 5148 assert(pre_val != rax, "check this code"); 5149 } 5150 5151 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5152 SATBMarkQueue::byte_offset_of_active())); 5153 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5154 SATBMarkQueue::byte_offset_of_index())); 5155 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5156 SATBMarkQueue::byte_offset_of_buf())); 5157 5158 5159 // Is marking active? 5160 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5161 cmpl(in_progress, 0); 5162 } else { 5163 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5164 cmpb(in_progress, 0); 5165 } 5166 jcc(Assembler::equal, done); 5167 5168 // Do we need to load the previous value? 5169 if (obj != noreg) { 5170 load_heap_oop(pre_val, Address(obj, 0)); 5171 } 5172 5173 // Is the previous value null? 5174 cmpptr(pre_val, (int32_t) NULL_WORD); 5175 jcc(Assembler::equal, done); 5176 5177 // Can we store original value in the thread's buffer? 5178 // Is index == 0? 5179 // (The index field is typed as size_t.) 5180 5181 movptr(tmp, index); // tmp := *index_adr 5182 cmpptr(tmp, 0); // tmp == 0? 5183 jcc(Assembler::equal, runtime); // If yes, goto runtime 5184 5185 subptr(tmp, wordSize); // tmp := tmp - wordSize 5186 movptr(index, tmp); // *index_adr := tmp 5187 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5188 5189 // Record the previous value 5190 movptr(Address(tmp, 0), pre_val); 5191 jmp(done); 5192 5193 bind(runtime); 5194 // save the live input values 5195 if(tosca_live) push(rax); 5196 5197 if (obj != noreg && obj != rax) 5198 push(obj); 5199 5200 if (pre_val != rax) 5201 push(pre_val); 5202 5203 // Calling the runtime using the regular call_VM_leaf mechanism generates 5204 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5205 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5206 // 5207 // If we care generating the pre-barrier without a frame (e.g. in the 5208 // intrinsified Reference.get() routine) then ebp might be pointing to 5209 // the caller frame and so this check will most likely fail at runtime. 5210 // 5211 // Expanding the call directly bypasses the generation of the check. 5212 // So when we do not have have a full interpreter frame on the stack 5213 // expand_call should be passed true. 5214 5215 NOT_LP64( push(thread); ) 5216 5217 if (expand_call) { 5218 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5219 pass_arg1(this, thread); 5220 pass_arg0(this, pre_val); 5221 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5222 } else { 5223 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5224 } 5225 5226 NOT_LP64( pop(thread); ) 5227 5228 // save the live input values 5229 if (pre_val != rax) 5230 pop(pre_val); 5231 5232 if (obj != noreg && obj != rax) 5233 pop(obj); 5234 5235 if(tosca_live) pop(rax); 5236 5237 bind(done); 5238 } 5239 5240 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5241 Register new_val, 5242 Register thread, 5243 Register tmp, 5244 Register tmp2) { 5245 #ifdef _LP64 5246 assert(thread == r15_thread, "must be"); 5247 #endif // _LP64 5248 5249 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5250 DirtyCardQueue::byte_offset_of_index())); 5251 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5252 DirtyCardQueue::byte_offset_of_buf())); 5253 5254 CardTableModRefBS* ct = 5255 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5256 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5257 5258 Label done; 5259 Label runtime; 5260 5261 // Does store cross heap regions? 5262 5263 movptr(tmp, store_addr); 5264 xorptr(tmp, new_val); 5265 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5266 jcc(Assembler::equal, done); 5267 5268 // crosses regions, storing NULL? 5269 5270 cmpptr(new_val, (int32_t) NULL_WORD); 5271 jcc(Assembler::equal, done); 5272 5273 // storing region crossing non-NULL, is card already dirty? 5274 5275 const Register card_addr = tmp; 5276 const Register cardtable = tmp2; 5277 5278 movptr(card_addr, store_addr); 5279 shrptr(card_addr, CardTableModRefBS::card_shift); 5280 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5281 // a valid address and therefore is not properly handled by the relocation code. 5282 movptr(cardtable, (intptr_t)ct->byte_map_base); 5283 addptr(card_addr, cardtable); 5284 5285 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5286 jcc(Assembler::equal, done); 5287 5288 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5289 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5290 jcc(Assembler::equal, done); 5291 5292 5293 // storing a region crossing, non-NULL oop, card is clean. 5294 // dirty card and log. 5295 5296 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5297 5298 cmpl(queue_index, 0); 5299 jcc(Assembler::equal, runtime); 5300 subl(queue_index, wordSize); 5301 movptr(tmp2, buffer); 5302 #ifdef _LP64 5303 movslq(rscratch1, queue_index); 5304 addq(tmp2, rscratch1); 5305 movq(Address(tmp2, 0), card_addr); 5306 #else 5307 addl(tmp2, queue_index); 5308 movl(Address(tmp2, 0), card_addr); 5309 #endif 5310 jmp(done); 5311 5312 bind(runtime); 5313 // save the live input values 5314 push(store_addr); 5315 push(new_val); 5316 #ifdef _LP64 5317 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5318 #else 5319 push(thread); 5320 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5321 pop(thread); 5322 #endif 5323 pop(new_val); 5324 pop(store_addr); 5325 5326 bind(done); 5327 } 5328 5329 #endif // INCLUDE_ALL_GCS 5330 ////////////////////////////////////////////////////////////////////////////////// 5331 5332 5333 void MacroAssembler::store_check(Register obj, Address dst) { 5334 store_check(obj); 5335 } 5336 5337 void MacroAssembler::store_check(Register obj) { 5338 // Does a store check for the oop in register obj. The content of 5339 // register obj is destroyed afterwards. 5340 BarrierSet* bs = Universe::heap()->barrier_set(); 5341 assert(bs->kind() == BarrierSet::CardTableForRS || 5342 bs->kind() == BarrierSet::CardTableExtension, 5343 "Wrong barrier set kind"); 5344 5345 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5346 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5347 5348 shrptr(obj, CardTableModRefBS::card_shift); 5349 5350 Address card_addr; 5351 5352 // The calculation for byte_map_base is as follows: 5353 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5354 // So this essentially converts an address to a displacement and it will 5355 // never need to be relocated. On 64bit however the value may be too 5356 // large for a 32bit displacement. 5357 intptr_t disp = (intptr_t) ct->byte_map_base; 5358 if (is_simm32(disp)) { 5359 card_addr = Address(noreg, obj, Address::times_1, disp); 5360 } else { 5361 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5362 // displacement and done in a single instruction given favorable mapping and a 5363 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5364 // entry and that entry is not properly handled by the relocation code. 5365 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5366 Address index(noreg, obj, Address::times_1); 5367 card_addr = as_Address(ArrayAddress(cardtable, index)); 5368 } 5369 5370 int dirty = CardTableModRefBS::dirty_card_val(); 5371 if (UseCondCardMark) { 5372 Label L_already_dirty; 5373 if (UseConcMarkSweepGC) { 5374 membar(Assembler::StoreLoad); 5375 } 5376 cmpb(card_addr, dirty); 5377 jcc(Assembler::equal, L_already_dirty); 5378 movb(card_addr, dirty); 5379 bind(L_already_dirty); 5380 } else { 5381 movb(card_addr, dirty); 5382 } 5383 } 5384 5385 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5386 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5387 } 5388 5389 // Force generation of a 4 byte immediate value even if it fits into 8bit 5390 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5391 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5392 } 5393 5394 void MacroAssembler::subptr(Register dst, Register src) { 5395 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5396 } 5397 5398 // C++ bool manipulation 5399 void MacroAssembler::testbool(Register dst) { 5400 if(sizeof(bool) == 1) 5401 testb(dst, 0xff); 5402 else if(sizeof(bool) == 2) { 5403 // testw implementation needed for two byte bools 5404 ShouldNotReachHere(); 5405 } else if(sizeof(bool) == 4) 5406 testl(dst, dst); 5407 else 5408 // unsupported 5409 ShouldNotReachHere(); 5410 } 5411 5412 void MacroAssembler::testptr(Register dst, Register src) { 5413 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5414 } 5415 5416 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5417 void MacroAssembler::tlab_allocate(Register obj, 5418 Register var_size_in_bytes, 5419 int con_size_in_bytes, 5420 Register t1, 5421 Register t2, 5422 Label& slow_case) { 5423 assert_different_registers(obj, t1, t2); 5424 assert_different_registers(obj, var_size_in_bytes, t1); 5425 Register end = t2; 5426 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5427 5428 verify_tlab(); 5429 5430 NOT_LP64(get_thread(thread)); 5431 5432 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5433 if (var_size_in_bytes == noreg) { 5434 lea(end, Address(obj, con_size_in_bytes)); 5435 } else { 5436 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5437 } 5438 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5439 jcc(Assembler::above, slow_case); 5440 5441 // update the tlab top pointer 5442 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5443 5444 // recover var_size_in_bytes if necessary 5445 if (var_size_in_bytes == end) { 5446 subptr(var_size_in_bytes, obj); 5447 } 5448 verify_tlab(); 5449 } 5450 5451 // Preserves rbx, and rdx. 5452 Register MacroAssembler::tlab_refill(Label& retry, 5453 Label& try_eden, 5454 Label& slow_case) { 5455 Register top = rax; 5456 Register t1 = rcx; // object size 5457 Register t2 = rsi; 5458 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5459 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5460 Label do_refill, discard_tlab; 5461 5462 if (!Universe::heap()->supports_inline_contig_alloc()) { 5463 // No allocation in the shared eden. 5464 jmp(slow_case); 5465 } 5466 5467 NOT_LP64(get_thread(thread_reg)); 5468 5469 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5470 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5471 5472 // calculate amount of free space 5473 subptr(t1, top); 5474 shrptr(t1, LogHeapWordSize); 5475 5476 // Retain tlab and allocate object in shared space if 5477 // the amount free in the tlab is too large to discard. 5478 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5479 jcc(Assembler::lessEqual, discard_tlab); 5480 5481 // Retain 5482 // %%% yuck as movptr... 5483 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5484 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5485 if (TLABStats) { 5486 // increment number of slow_allocations 5487 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5488 } 5489 jmp(try_eden); 5490 5491 bind(discard_tlab); 5492 if (TLABStats) { 5493 // increment number of refills 5494 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5495 // accumulate wastage -- t1 is amount free in tlab 5496 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5497 } 5498 5499 // if tlab is currently allocated (top or end != null) then 5500 // fill [top, end + alignment_reserve) with array object 5501 testptr(top, top); 5502 jcc(Assembler::zero, do_refill); 5503 5504 // set up the mark word 5505 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5506 // set the length to the remaining space 5507 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5508 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5509 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5510 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5511 // set klass to intArrayKlass 5512 // dubious reloc why not an oop reloc? 5513 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5514 // store klass last. concurrent gcs assumes klass length is valid if 5515 // klass field is not null. 5516 store_klass(top, t1); 5517 5518 movptr(t1, top); 5519 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5520 incr_allocated_bytes(thread_reg, t1, 0); 5521 5522 // refill the tlab with an eden allocation 5523 bind(do_refill); 5524 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5525 shlptr(t1, LogHeapWordSize); 5526 // allocate new tlab, address returned in top 5527 eden_allocate(top, t1, 0, t2, slow_case); 5528 5529 // Check that t1 was preserved in eden_allocate. 5530 #ifdef ASSERT 5531 if (UseTLAB) { 5532 Label ok; 5533 Register tsize = rsi; 5534 assert_different_registers(tsize, thread_reg, t1); 5535 push(tsize); 5536 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5537 shlptr(tsize, LogHeapWordSize); 5538 cmpptr(t1, tsize); 5539 jcc(Assembler::equal, ok); 5540 STOP("assert(t1 != tlab size)"); 5541 should_not_reach_here(); 5542 5543 bind(ok); 5544 pop(tsize); 5545 } 5546 #endif 5547 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5548 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5549 addptr(top, t1); 5550 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5551 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5552 5553 if (ZeroTLAB) { 5554 // This is a fast TLAB refill, therefore the GC is not notified of it. 5555 // So compiled code must fill the new TLAB with zeroes. 5556 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5557 zero_memory(top, t1, 0, t2); 5558 } 5559 5560 verify_tlab(); 5561 jmp(retry); 5562 5563 return thread_reg; // for use by caller 5564 } 5565 5566 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5567 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5568 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5569 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5570 Label done; 5571 5572 testptr(length_in_bytes, length_in_bytes); 5573 jcc(Assembler::zero, done); 5574 5575 // initialize topmost word, divide index by 2, check if odd and test if zero 5576 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5577 #ifdef ASSERT 5578 { 5579 Label L; 5580 testptr(length_in_bytes, BytesPerWord - 1); 5581 jcc(Assembler::zero, L); 5582 stop("length must be a multiple of BytesPerWord"); 5583 bind(L); 5584 } 5585 #endif 5586 Register index = length_in_bytes; 5587 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5588 if (UseIncDec) { 5589 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5590 } else { 5591 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5592 shrptr(index, 1); 5593 } 5594 #ifndef _LP64 5595 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5596 { 5597 Label even; 5598 // note: if index was a multiple of 8, then it cannot 5599 // be 0 now otherwise it must have been 0 before 5600 // => if it is even, we don't need to check for 0 again 5601 jcc(Assembler::carryClear, even); 5602 // clear topmost word (no jump would be needed if conditional assignment worked here) 5603 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5604 // index could be 0 now, must check again 5605 jcc(Assembler::zero, done); 5606 bind(even); 5607 } 5608 #endif // !_LP64 5609 // initialize remaining object fields: index is a multiple of 2 now 5610 { 5611 Label loop; 5612 bind(loop); 5613 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5614 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5615 decrement(index); 5616 jcc(Assembler::notZero, loop); 5617 } 5618 5619 bind(done); 5620 } 5621 5622 void MacroAssembler::incr_allocated_bytes(Register thread, 5623 Register var_size_in_bytes, 5624 int con_size_in_bytes, 5625 Register t1) { 5626 if (!thread->is_valid()) { 5627 #ifdef _LP64 5628 thread = r15_thread; 5629 #else 5630 assert(t1->is_valid(), "need temp reg"); 5631 thread = t1; 5632 get_thread(thread); 5633 #endif 5634 } 5635 5636 #ifdef _LP64 5637 if (var_size_in_bytes->is_valid()) { 5638 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5639 } else { 5640 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5641 } 5642 #else 5643 if (var_size_in_bytes->is_valid()) { 5644 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5645 } else { 5646 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5647 } 5648 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5649 #endif 5650 } 5651 5652 // Look up the method for a megamorphic invokeinterface call. 5653 // The target method is determined by <intf_klass, itable_index>. 5654 // The receiver klass is in recv_klass. 5655 // On success, the result will be in method_result, and execution falls through. 5656 // On failure, execution transfers to the given label. 5657 void MacroAssembler::lookup_interface_method(Register recv_klass, 5658 Register intf_klass, 5659 RegisterOrConstant itable_index, 5660 Register method_result, 5661 Register scan_temp, 5662 Label& L_no_such_interface) { 5663 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5664 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5665 "caller must use same register for non-constant itable index as for method"); 5666 5667 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5668 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5669 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5670 int scan_step = itableOffsetEntry::size() * wordSize; 5671 int vte_size = vtableEntry::size_in_bytes(); 5672 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5673 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5674 5675 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5676 5677 // %%% Could store the aligned, prescaled offset in the klassoop. 5678 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5679 5680 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5681 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5682 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5683 5684 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5685 // if (scan->interface() == intf) { 5686 // result = (klass + scan->offset() + itable_index); 5687 // } 5688 // } 5689 Label search, found_method; 5690 5691 for (int peel = 1; peel >= 0; peel--) { 5692 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5693 cmpptr(intf_klass, method_result); 5694 5695 if (peel) { 5696 jccb(Assembler::equal, found_method); 5697 } else { 5698 jccb(Assembler::notEqual, search); 5699 // (invert the test to fall through to found_method...) 5700 } 5701 5702 if (!peel) break; 5703 5704 bind(search); 5705 5706 // Check that the previous entry is non-null. A null entry means that 5707 // the receiver class doesn't implement the interface, and wasn't the 5708 // same as when the caller was compiled. 5709 testptr(method_result, method_result); 5710 jcc(Assembler::zero, L_no_such_interface); 5711 addptr(scan_temp, scan_step); 5712 } 5713 5714 bind(found_method); 5715 5716 // Got a hit. 5717 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5718 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5719 } 5720 5721 5722 // virtual method calling 5723 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5724 RegisterOrConstant vtable_index, 5725 Register method_result) { 5726 const int base = in_bytes(Klass::vtable_start_offset()); 5727 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5728 Address vtable_entry_addr(recv_klass, 5729 vtable_index, Address::times_ptr, 5730 base + vtableEntry::method_offset_in_bytes()); 5731 movptr(method_result, vtable_entry_addr); 5732 } 5733 5734 5735 void MacroAssembler::check_klass_subtype(Register sub_klass, 5736 Register super_klass, 5737 Register temp_reg, 5738 Label& L_success) { 5739 Label L_failure; 5740 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5741 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5742 bind(L_failure); 5743 } 5744 5745 5746 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5747 Register super_klass, 5748 Register temp_reg, 5749 Label* L_success, 5750 Label* L_failure, 5751 Label* L_slow_path, 5752 RegisterOrConstant super_check_offset) { 5753 assert_different_registers(sub_klass, super_klass, temp_reg); 5754 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5755 if (super_check_offset.is_register()) { 5756 assert_different_registers(sub_klass, super_klass, 5757 super_check_offset.as_register()); 5758 } else if (must_load_sco) { 5759 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5760 } 5761 5762 Label L_fallthrough; 5763 int label_nulls = 0; 5764 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5765 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5766 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5767 assert(label_nulls <= 1, "at most one NULL in the batch"); 5768 5769 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5770 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5771 Address super_check_offset_addr(super_klass, sco_offset); 5772 5773 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5774 // range of a jccb. If this routine grows larger, reconsider at 5775 // least some of these. 5776 #define local_jcc(assembler_cond, label) \ 5777 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5778 else jcc( assembler_cond, label) /*omit semi*/ 5779 5780 // Hacked jmp, which may only be used just before L_fallthrough. 5781 #define final_jmp(label) \ 5782 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5783 else jmp(label) /*omit semi*/ 5784 5785 // If the pointers are equal, we are done (e.g., String[] elements). 5786 // This self-check enables sharing of secondary supertype arrays among 5787 // non-primary types such as array-of-interface. Otherwise, each such 5788 // type would need its own customized SSA. 5789 // We move this check to the front of the fast path because many 5790 // type checks are in fact trivially successful in this manner, 5791 // so we get a nicely predicted branch right at the start of the check. 5792 cmpptr(sub_klass, super_klass); 5793 local_jcc(Assembler::equal, *L_success); 5794 5795 // Check the supertype display: 5796 if (must_load_sco) { 5797 // Positive movl does right thing on LP64. 5798 movl(temp_reg, super_check_offset_addr); 5799 super_check_offset = RegisterOrConstant(temp_reg); 5800 } 5801 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5802 cmpptr(super_klass, super_check_addr); // load displayed supertype 5803 5804 // This check has worked decisively for primary supers. 5805 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5806 // (Secondary supers are interfaces and very deeply nested subtypes.) 5807 // This works in the same check above because of a tricky aliasing 5808 // between the super_cache and the primary super display elements. 5809 // (The 'super_check_addr' can address either, as the case requires.) 5810 // Note that the cache is updated below if it does not help us find 5811 // what we need immediately. 5812 // So if it was a primary super, we can just fail immediately. 5813 // Otherwise, it's the slow path for us (no success at this point). 5814 5815 if (super_check_offset.is_register()) { 5816 local_jcc(Assembler::equal, *L_success); 5817 cmpl(super_check_offset.as_register(), sc_offset); 5818 if (L_failure == &L_fallthrough) { 5819 local_jcc(Assembler::equal, *L_slow_path); 5820 } else { 5821 local_jcc(Assembler::notEqual, *L_failure); 5822 final_jmp(*L_slow_path); 5823 } 5824 } else if (super_check_offset.as_constant() == sc_offset) { 5825 // Need a slow path; fast failure is impossible. 5826 if (L_slow_path == &L_fallthrough) { 5827 local_jcc(Assembler::equal, *L_success); 5828 } else { 5829 local_jcc(Assembler::notEqual, *L_slow_path); 5830 final_jmp(*L_success); 5831 } 5832 } else { 5833 // No slow path; it's a fast decision. 5834 if (L_failure == &L_fallthrough) { 5835 local_jcc(Assembler::equal, *L_success); 5836 } else { 5837 local_jcc(Assembler::notEqual, *L_failure); 5838 final_jmp(*L_success); 5839 } 5840 } 5841 5842 bind(L_fallthrough); 5843 5844 #undef local_jcc 5845 #undef final_jmp 5846 } 5847 5848 5849 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5850 Register super_klass, 5851 Register temp_reg, 5852 Register temp2_reg, 5853 Label* L_success, 5854 Label* L_failure, 5855 bool set_cond_codes) { 5856 assert_different_registers(sub_klass, super_klass, temp_reg); 5857 if (temp2_reg != noreg) 5858 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5859 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5860 5861 Label L_fallthrough; 5862 int label_nulls = 0; 5863 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5864 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5865 assert(label_nulls <= 1, "at most one NULL in the batch"); 5866 5867 // a couple of useful fields in sub_klass: 5868 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5869 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5870 Address secondary_supers_addr(sub_klass, ss_offset); 5871 Address super_cache_addr( sub_klass, sc_offset); 5872 5873 // Do a linear scan of the secondary super-klass chain. 5874 // This code is rarely used, so simplicity is a virtue here. 5875 // The repne_scan instruction uses fixed registers, which we must spill. 5876 // Don't worry too much about pre-existing connections with the input regs. 5877 5878 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5879 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5880 5881 // Get super_klass value into rax (even if it was in rdi or rcx). 5882 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5883 if (super_klass != rax || UseCompressedOops) { 5884 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5885 mov(rax, super_klass); 5886 } 5887 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5888 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5889 5890 #ifndef PRODUCT 5891 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5892 ExternalAddress pst_counter_addr((address) pst_counter); 5893 NOT_LP64( incrementl(pst_counter_addr) ); 5894 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5895 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5896 #endif //PRODUCT 5897 5898 // We will consult the secondary-super array. 5899 movptr(rdi, secondary_supers_addr); 5900 // Load the array length. (Positive movl does right thing on LP64.) 5901 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5902 // Skip to start of data. 5903 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5904 5905 // Scan RCX words at [RDI] for an occurrence of RAX. 5906 // Set NZ/Z based on last compare. 5907 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5908 // not change flags (only scas instruction which is repeated sets flags). 5909 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5910 5911 testptr(rax,rax); // Set Z = 0 5912 repne_scan(); 5913 5914 // Unspill the temp. registers: 5915 if (pushed_rdi) pop(rdi); 5916 if (pushed_rcx) pop(rcx); 5917 if (pushed_rax) pop(rax); 5918 5919 if (set_cond_codes) { 5920 // Special hack for the AD files: rdi is guaranteed non-zero. 5921 assert(!pushed_rdi, "rdi must be left non-NULL"); 5922 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5923 } 5924 5925 if (L_failure == &L_fallthrough) 5926 jccb(Assembler::notEqual, *L_failure); 5927 else jcc(Assembler::notEqual, *L_failure); 5928 5929 // Success. Cache the super we found and proceed in triumph. 5930 movptr(super_cache_addr, super_klass); 5931 5932 if (L_success != &L_fallthrough) { 5933 jmp(*L_success); 5934 } 5935 5936 #undef IS_A_TEMP 5937 5938 bind(L_fallthrough); 5939 } 5940 5941 5942 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5943 if (VM_Version::supports_cmov()) { 5944 cmovl(cc, dst, src); 5945 } else { 5946 Label L; 5947 jccb(negate_condition(cc), L); 5948 movl(dst, src); 5949 bind(L); 5950 } 5951 } 5952 5953 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5954 if (VM_Version::supports_cmov()) { 5955 cmovl(cc, dst, src); 5956 } else { 5957 Label L; 5958 jccb(negate_condition(cc), L); 5959 movl(dst, src); 5960 bind(L); 5961 } 5962 } 5963 5964 void MacroAssembler::verify_oop(Register reg, const char* s) { 5965 if (!VerifyOops) return; 5966 5967 // Pass register number to verify_oop_subroutine 5968 const char* b = NULL; 5969 { 5970 ResourceMark rm; 5971 stringStream ss; 5972 ss.print("verify_oop: %s: %s", reg->name(), s); 5973 b = code_string(ss.as_string()); 5974 } 5975 BLOCK_COMMENT("verify_oop {"); 5976 #ifdef _LP64 5977 push(rscratch1); // save r10, trashed by movptr() 5978 #endif 5979 push(rax); // save rax, 5980 push(reg); // pass register argument 5981 ExternalAddress buffer((address) b); 5982 // avoid using pushptr, as it modifies scratch registers 5983 // and our contract is not to modify anything 5984 movptr(rax, buffer.addr()); 5985 push(rax); 5986 // call indirectly to solve generation ordering problem 5987 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5988 call(rax); 5989 // Caller pops the arguments (oop, message) and restores rax, r10 5990 BLOCK_COMMENT("} verify_oop"); 5991 } 5992 5993 5994 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 5995 Register tmp, 5996 int offset) { 5997 intptr_t value = *delayed_value_addr; 5998 if (value != 0) 5999 return RegisterOrConstant(value + offset); 6000 6001 // load indirectly to solve generation ordering problem 6002 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6003 6004 #ifdef ASSERT 6005 { Label L; 6006 testptr(tmp, tmp); 6007 if (WizardMode) { 6008 const char* buf = NULL; 6009 { 6010 ResourceMark rm; 6011 stringStream ss; 6012 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6013 buf = code_string(ss.as_string()); 6014 } 6015 jcc(Assembler::notZero, L); 6016 STOP(buf); 6017 } else { 6018 jccb(Assembler::notZero, L); 6019 hlt(); 6020 } 6021 bind(L); 6022 } 6023 #endif 6024 6025 if (offset != 0) 6026 addptr(tmp, offset); 6027 6028 return RegisterOrConstant(tmp); 6029 } 6030 6031 6032 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6033 int extra_slot_offset) { 6034 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6035 int stackElementSize = Interpreter::stackElementSize; 6036 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6037 #ifdef ASSERT 6038 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6039 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6040 #endif 6041 Register scale_reg = noreg; 6042 Address::ScaleFactor scale_factor = Address::no_scale; 6043 if (arg_slot.is_constant()) { 6044 offset += arg_slot.as_constant() * stackElementSize; 6045 } else { 6046 scale_reg = arg_slot.as_register(); 6047 scale_factor = Address::times(stackElementSize); 6048 } 6049 offset += wordSize; // return PC is on stack 6050 return Address(rsp, scale_reg, scale_factor, offset); 6051 } 6052 6053 6054 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6055 if (!VerifyOops) return; 6056 6057 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6058 // Pass register number to verify_oop_subroutine 6059 const char* b = NULL; 6060 { 6061 ResourceMark rm; 6062 stringStream ss; 6063 ss.print("verify_oop_addr: %s", s); 6064 b = code_string(ss.as_string()); 6065 } 6066 #ifdef _LP64 6067 push(rscratch1); // save r10, trashed by movptr() 6068 #endif 6069 push(rax); // save rax, 6070 // addr may contain rsp so we will have to adjust it based on the push 6071 // we just did (and on 64 bit we do two pushes) 6072 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6073 // stores rax into addr which is backwards of what was intended. 6074 if (addr.uses(rsp)) { 6075 lea(rax, addr); 6076 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6077 } else { 6078 pushptr(addr); 6079 } 6080 6081 ExternalAddress buffer((address) b); 6082 // pass msg argument 6083 // avoid using pushptr, as it modifies scratch registers 6084 // and our contract is not to modify anything 6085 movptr(rax, buffer.addr()); 6086 push(rax); 6087 6088 // call indirectly to solve generation ordering problem 6089 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6090 call(rax); 6091 // Caller pops the arguments (addr, message) and restores rax, r10. 6092 } 6093 6094 void MacroAssembler::verify_tlab() { 6095 #ifdef ASSERT 6096 if (UseTLAB && VerifyOops) { 6097 Label next, ok; 6098 Register t1 = rsi; 6099 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6100 6101 push(t1); 6102 NOT_LP64(push(thread_reg)); 6103 NOT_LP64(get_thread(thread_reg)); 6104 6105 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6106 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6107 jcc(Assembler::aboveEqual, next); 6108 STOP("assert(top >= start)"); 6109 should_not_reach_here(); 6110 6111 bind(next); 6112 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6113 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6114 jcc(Assembler::aboveEqual, ok); 6115 STOP("assert(top <= end)"); 6116 should_not_reach_here(); 6117 6118 bind(ok); 6119 NOT_LP64(pop(thread_reg)); 6120 pop(t1); 6121 } 6122 #endif 6123 } 6124 6125 class ControlWord { 6126 public: 6127 int32_t _value; 6128 6129 int rounding_control() const { return (_value >> 10) & 3 ; } 6130 int precision_control() const { return (_value >> 8) & 3 ; } 6131 bool precision() const { return ((_value >> 5) & 1) != 0; } 6132 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6133 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6134 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6135 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6136 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6137 6138 void print() const { 6139 // rounding control 6140 const char* rc; 6141 switch (rounding_control()) { 6142 case 0: rc = "round near"; break; 6143 case 1: rc = "round down"; break; 6144 case 2: rc = "round up "; break; 6145 case 3: rc = "chop "; break; 6146 }; 6147 // precision control 6148 const char* pc; 6149 switch (precision_control()) { 6150 case 0: pc = "24 bits "; break; 6151 case 1: pc = "reserved"; break; 6152 case 2: pc = "53 bits "; break; 6153 case 3: pc = "64 bits "; break; 6154 }; 6155 // flags 6156 char f[9]; 6157 f[0] = ' '; 6158 f[1] = ' '; 6159 f[2] = (precision ()) ? 'P' : 'p'; 6160 f[3] = (underflow ()) ? 'U' : 'u'; 6161 f[4] = (overflow ()) ? 'O' : 'o'; 6162 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6163 f[6] = (denormalized()) ? 'D' : 'd'; 6164 f[7] = (invalid ()) ? 'I' : 'i'; 6165 f[8] = '\x0'; 6166 // output 6167 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6168 } 6169 6170 }; 6171 6172 class StatusWord { 6173 public: 6174 int32_t _value; 6175 6176 bool busy() const { return ((_value >> 15) & 1) != 0; } 6177 bool C3() const { return ((_value >> 14) & 1) != 0; } 6178 bool C2() const { return ((_value >> 10) & 1) != 0; } 6179 bool C1() const { return ((_value >> 9) & 1) != 0; } 6180 bool C0() const { return ((_value >> 8) & 1) != 0; } 6181 int top() const { return (_value >> 11) & 7 ; } 6182 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6183 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6184 bool precision() const { return ((_value >> 5) & 1) != 0; } 6185 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6186 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6187 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6188 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6189 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6190 6191 void print() const { 6192 // condition codes 6193 char c[5]; 6194 c[0] = (C3()) ? '3' : '-'; 6195 c[1] = (C2()) ? '2' : '-'; 6196 c[2] = (C1()) ? '1' : '-'; 6197 c[3] = (C0()) ? '0' : '-'; 6198 c[4] = '\x0'; 6199 // flags 6200 char f[9]; 6201 f[0] = (error_status()) ? 'E' : '-'; 6202 f[1] = (stack_fault ()) ? 'S' : '-'; 6203 f[2] = (precision ()) ? 'P' : '-'; 6204 f[3] = (underflow ()) ? 'U' : '-'; 6205 f[4] = (overflow ()) ? 'O' : '-'; 6206 f[5] = (zero_divide ()) ? 'Z' : '-'; 6207 f[6] = (denormalized()) ? 'D' : '-'; 6208 f[7] = (invalid ()) ? 'I' : '-'; 6209 f[8] = '\x0'; 6210 // output 6211 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6212 } 6213 6214 }; 6215 6216 class TagWord { 6217 public: 6218 int32_t _value; 6219 6220 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6221 6222 void print() const { 6223 printf("%04x", _value & 0xFFFF); 6224 } 6225 6226 }; 6227 6228 class FPU_Register { 6229 public: 6230 int32_t _m0; 6231 int32_t _m1; 6232 int16_t _ex; 6233 6234 bool is_indefinite() const { 6235 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6236 } 6237 6238 void print() const { 6239 char sign = (_ex < 0) ? '-' : '+'; 6240 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6241 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6242 }; 6243 6244 }; 6245 6246 class FPU_State { 6247 public: 6248 enum { 6249 register_size = 10, 6250 number_of_registers = 8, 6251 register_mask = 7 6252 }; 6253 6254 ControlWord _control_word; 6255 StatusWord _status_word; 6256 TagWord _tag_word; 6257 int32_t _error_offset; 6258 int32_t _error_selector; 6259 int32_t _data_offset; 6260 int32_t _data_selector; 6261 int8_t _register[register_size * number_of_registers]; 6262 6263 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6264 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6265 6266 const char* tag_as_string(int tag) const { 6267 switch (tag) { 6268 case 0: return "valid"; 6269 case 1: return "zero"; 6270 case 2: return "special"; 6271 case 3: return "empty"; 6272 } 6273 ShouldNotReachHere(); 6274 return NULL; 6275 } 6276 6277 void print() const { 6278 // print computation registers 6279 { int t = _status_word.top(); 6280 for (int i = 0; i < number_of_registers; i++) { 6281 int j = (i - t) & register_mask; 6282 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6283 st(j)->print(); 6284 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6285 } 6286 } 6287 printf("\n"); 6288 // print control registers 6289 printf("ctrl = "); _control_word.print(); printf("\n"); 6290 printf("stat = "); _status_word .print(); printf("\n"); 6291 printf("tags = "); _tag_word .print(); printf("\n"); 6292 } 6293 6294 }; 6295 6296 class Flag_Register { 6297 public: 6298 int32_t _value; 6299 6300 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6301 bool direction() const { return ((_value >> 10) & 1) != 0; } 6302 bool sign() const { return ((_value >> 7) & 1) != 0; } 6303 bool zero() const { return ((_value >> 6) & 1) != 0; } 6304 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6305 bool parity() const { return ((_value >> 2) & 1) != 0; } 6306 bool carry() const { return ((_value >> 0) & 1) != 0; } 6307 6308 void print() const { 6309 // flags 6310 char f[8]; 6311 f[0] = (overflow ()) ? 'O' : '-'; 6312 f[1] = (direction ()) ? 'D' : '-'; 6313 f[2] = (sign ()) ? 'S' : '-'; 6314 f[3] = (zero ()) ? 'Z' : '-'; 6315 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6316 f[5] = (parity ()) ? 'P' : '-'; 6317 f[6] = (carry ()) ? 'C' : '-'; 6318 f[7] = '\x0'; 6319 // output 6320 printf("%08x flags = %s", _value, f); 6321 } 6322 6323 }; 6324 6325 class IU_Register { 6326 public: 6327 int32_t _value; 6328 6329 void print() const { 6330 printf("%08x %11d", _value, _value); 6331 } 6332 6333 }; 6334 6335 class IU_State { 6336 public: 6337 Flag_Register _eflags; 6338 IU_Register _rdi; 6339 IU_Register _rsi; 6340 IU_Register _rbp; 6341 IU_Register _rsp; 6342 IU_Register _rbx; 6343 IU_Register _rdx; 6344 IU_Register _rcx; 6345 IU_Register _rax; 6346 6347 void print() const { 6348 // computation registers 6349 printf("rax, = "); _rax.print(); printf("\n"); 6350 printf("rbx, = "); _rbx.print(); printf("\n"); 6351 printf("rcx = "); _rcx.print(); printf("\n"); 6352 printf("rdx = "); _rdx.print(); printf("\n"); 6353 printf("rdi = "); _rdi.print(); printf("\n"); 6354 printf("rsi = "); _rsi.print(); printf("\n"); 6355 printf("rbp, = "); _rbp.print(); printf("\n"); 6356 printf("rsp = "); _rsp.print(); printf("\n"); 6357 printf("\n"); 6358 // control registers 6359 printf("flgs = "); _eflags.print(); printf("\n"); 6360 } 6361 }; 6362 6363 6364 class CPU_State { 6365 public: 6366 FPU_State _fpu_state; 6367 IU_State _iu_state; 6368 6369 void print() const { 6370 printf("--------------------------------------------------\n"); 6371 _iu_state .print(); 6372 printf("\n"); 6373 _fpu_state.print(); 6374 printf("--------------------------------------------------\n"); 6375 } 6376 6377 }; 6378 6379 6380 static void _print_CPU_state(CPU_State* state) { 6381 state->print(); 6382 }; 6383 6384 6385 void MacroAssembler::print_CPU_state() { 6386 push_CPU_state(); 6387 push(rsp); // pass CPU state 6388 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6389 addptr(rsp, wordSize); // discard argument 6390 pop_CPU_state(); 6391 } 6392 6393 6394 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6395 static int counter = 0; 6396 FPU_State* fs = &state->_fpu_state; 6397 counter++; 6398 // For leaf calls, only verify that the top few elements remain empty. 6399 // We only need 1 empty at the top for C2 code. 6400 if( stack_depth < 0 ) { 6401 if( fs->tag_for_st(7) != 3 ) { 6402 printf("FPR7 not empty\n"); 6403 state->print(); 6404 assert(false, "error"); 6405 return false; 6406 } 6407 return true; // All other stack states do not matter 6408 } 6409 6410 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6411 "bad FPU control word"); 6412 6413 // compute stack depth 6414 int i = 0; 6415 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6416 int d = i; 6417 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6418 // verify findings 6419 if (i != FPU_State::number_of_registers) { 6420 // stack not contiguous 6421 printf("%s: stack not contiguous at ST%d\n", s, i); 6422 state->print(); 6423 assert(false, "error"); 6424 return false; 6425 } 6426 // check if computed stack depth corresponds to expected stack depth 6427 if (stack_depth < 0) { 6428 // expected stack depth is -stack_depth or less 6429 if (d > -stack_depth) { 6430 // too many elements on the stack 6431 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6432 state->print(); 6433 assert(false, "error"); 6434 return false; 6435 } 6436 } else { 6437 // expected stack depth is stack_depth 6438 if (d != stack_depth) { 6439 // wrong stack depth 6440 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6441 state->print(); 6442 assert(false, "error"); 6443 return false; 6444 } 6445 } 6446 // everything is cool 6447 return true; 6448 } 6449 6450 6451 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6452 if (!VerifyFPU) return; 6453 push_CPU_state(); 6454 push(rsp); // pass CPU state 6455 ExternalAddress msg((address) s); 6456 // pass message string s 6457 pushptr(msg.addr()); 6458 push(stack_depth); // pass stack depth 6459 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6460 addptr(rsp, 3 * wordSize); // discard arguments 6461 // check for error 6462 { Label L; 6463 testl(rax, rax); 6464 jcc(Assembler::notZero, L); 6465 int3(); // break if error condition 6466 bind(L); 6467 } 6468 pop_CPU_state(); 6469 } 6470 6471 void MacroAssembler::restore_cpu_control_state_after_jni() { 6472 // Either restore the MXCSR register after returning from the JNI Call 6473 // or verify that it wasn't changed (with -Xcheck:jni flag). 6474 if (VM_Version::supports_sse()) { 6475 if (RestoreMXCSROnJNICalls) { 6476 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6477 } else if (CheckJNICalls) { 6478 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6479 } 6480 } 6481 if (VM_Version::supports_avx()) { 6482 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6483 vzeroupper(); 6484 } 6485 6486 #ifndef _LP64 6487 // Either restore the x87 floating pointer control word after returning 6488 // from the JNI call or verify that it wasn't changed. 6489 if (CheckJNICalls) { 6490 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6491 } 6492 #endif // _LP64 6493 } 6494 6495 void MacroAssembler::load_mirror(Register mirror, Register method) { 6496 // get mirror 6497 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6498 movptr(mirror, Address(method, Method::const_offset())); 6499 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6500 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6501 movptr(mirror, Address(mirror, mirror_offset)); 6502 } 6503 6504 void MacroAssembler::load_klass(Register dst, Register src) { 6505 #ifdef _LP64 6506 if (UseCompressedClassPointers) { 6507 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6508 decode_klass_not_null(dst); 6509 } else 6510 #endif 6511 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6512 } 6513 6514 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6515 load_klass(dst, src); 6516 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6517 } 6518 6519 void MacroAssembler::store_klass(Register dst, Register src) { 6520 #ifdef _LP64 6521 if (UseCompressedClassPointers) { 6522 encode_klass_not_null(src); 6523 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6524 } else 6525 #endif 6526 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6527 } 6528 6529 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6530 #ifdef _LP64 6531 // FIXME: Must change all places where we try to load the klass. 6532 if (UseCompressedOops) { 6533 movl(dst, src); 6534 decode_heap_oop(dst); 6535 } else 6536 #endif 6537 movptr(dst, src); 6538 } 6539 6540 // Doesn't do verfication, generates fixed size code 6541 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6542 #ifdef _LP64 6543 if (UseCompressedOops) { 6544 movl(dst, src); 6545 decode_heap_oop_not_null(dst); 6546 } else 6547 #endif 6548 movptr(dst, src); 6549 } 6550 6551 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6552 #ifdef _LP64 6553 if (UseCompressedOops) { 6554 assert(!dst.uses(src), "not enough registers"); 6555 encode_heap_oop(src); 6556 movl(dst, src); 6557 } else 6558 #endif 6559 movptr(dst, src); 6560 } 6561 6562 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6563 assert_different_registers(src1, tmp); 6564 #ifdef _LP64 6565 if (UseCompressedOops) { 6566 bool did_push = false; 6567 if (tmp == noreg) { 6568 tmp = rax; 6569 push(tmp); 6570 did_push = true; 6571 assert(!src2.uses(rsp), "can't push"); 6572 } 6573 load_heap_oop(tmp, src2); 6574 cmpptr(src1, tmp); 6575 if (did_push) pop(tmp); 6576 } else 6577 #endif 6578 cmpptr(src1, src2); 6579 } 6580 6581 // Used for storing NULLs. 6582 void MacroAssembler::store_heap_oop_null(Address dst) { 6583 #ifdef _LP64 6584 if (UseCompressedOops) { 6585 movl(dst, (int32_t)NULL_WORD); 6586 } else { 6587 movslq(dst, (int32_t)NULL_WORD); 6588 } 6589 #else 6590 movl(dst, (int32_t)NULL_WORD); 6591 #endif 6592 } 6593 6594 #ifdef _LP64 6595 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6596 if (UseCompressedClassPointers) { 6597 // Store to klass gap in destination 6598 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6599 } 6600 } 6601 6602 #ifdef ASSERT 6603 void MacroAssembler::verify_heapbase(const char* msg) { 6604 assert (UseCompressedOops, "should be compressed"); 6605 assert (Universe::heap() != NULL, "java heap should be initialized"); 6606 if (CheckCompressedOops) { 6607 Label ok; 6608 push(rscratch1); // cmpptr trashes rscratch1 6609 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6610 jcc(Assembler::equal, ok); 6611 STOP(msg); 6612 bind(ok); 6613 pop(rscratch1); 6614 } 6615 } 6616 #endif 6617 6618 // Algorithm must match oop.inline.hpp encode_heap_oop. 6619 void MacroAssembler::encode_heap_oop(Register r) { 6620 #ifdef ASSERT 6621 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6622 #endif 6623 verify_oop(r, "broken oop in encode_heap_oop"); 6624 if (Universe::narrow_oop_base() == NULL) { 6625 if (Universe::narrow_oop_shift() != 0) { 6626 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6627 shrq(r, LogMinObjAlignmentInBytes); 6628 } 6629 return; 6630 } 6631 testq(r, r); 6632 cmovq(Assembler::equal, r, r12_heapbase); 6633 subq(r, r12_heapbase); 6634 shrq(r, LogMinObjAlignmentInBytes); 6635 } 6636 6637 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6638 #ifdef ASSERT 6639 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6640 if (CheckCompressedOops) { 6641 Label ok; 6642 testq(r, r); 6643 jcc(Assembler::notEqual, ok); 6644 STOP("null oop passed to encode_heap_oop_not_null"); 6645 bind(ok); 6646 } 6647 #endif 6648 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6649 if (Universe::narrow_oop_base() != NULL) { 6650 subq(r, r12_heapbase); 6651 } 6652 if (Universe::narrow_oop_shift() != 0) { 6653 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6654 shrq(r, LogMinObjAlignmentInBytes); 6655 } 6656 } 6657 6658 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6659 #ifdef ASSERT 6660 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6661 if (CheckCompressedOops) { 6662 Label ok; 6663 testq(src, src); 6664 jcc(Assembler::notEqual, ok); 6665 STOP("null oop passed to encode_heap_oop_not_null2"); 6666 bind(ok); 6667 } 6668 #endif 6669 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6670 if (dst != src) { 6671 movq(dst, src); 6672 } 6673 if (Universe::narrow_oop_base() != NULL) { 6674 subq(dst, r12_heapbase); 6675 } 6676 if (Universe::narrow_oop_shift() != 0) { 6677 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6678 shrq(dst, LogMinObjAlignmentInBytes); 6679 } 6680 } 6681 6682 void MacroAssembler::decode_heap_oop(Register r) { 6683 #ifdef ASSERT 6684 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6685 #endif 6686 if (Universe::narrow_oop_base() == NULL) { 6687 if (Universe::narrow_oop_shift() != 0) { 6688 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6689 shlq(r, LogMinObjAlignmentInBytes); 6690 } 6691 } else { 6692 Label done; 6693 shlq(r, LogMinObjAlignmentInBytes); 6694 jccb(Assembler::equal, done); 6695 addq(r, r12_heapbase); 6696 bind(done); 6697 } 6698 verify_oop(r, "broken oop in decode_heap_oop"); 6699 } 6700 6701 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6702 // Note: it will change flags 6703 assert (UseCompressedOops, "should only be used for compressed headers"); 6704 assert (Universe::heap() != NULL, "java heap should be initialized"); 6705 // Cannot assert, unverified entry point counts instructions (see .ad file) 6706 // vtableStubs also counts instructions in pd_code_size_limit. 6707 // Also do not verify_oop as this is called by verify_oop. 6708 if (Universe::narrow_oop_shift() != 0) { 6709 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6710 shlq(r, LogMinObjAlignmentInBytes); 6711 if (Universe::narrow_oop_base() != NULL) { 6712 addq(r, r12_heapbase); 6713 } 6714 } else { 6715 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6716 } 6717 } 6718 6719 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6720 // Note: it will change flags 6721 assert (UseCompressedOops, "should only be used for compressed headers"); 6722 assert (Universe::heap() != NULL, "java heap should be initialized"); 6723 // Cannot assert, unverified entry point counts instructions (see .ad file) 6724 // vtableStubs also counts instructions in pd_code_size_limit. 6725 // Also do not verify_oop as this is called by verify_oop. 6726 if (Universe::narrow_oop_shift() != 0) { 6727 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6728 if (LogMinObjAlignmentInBytes == Address::times_8) { 6729 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6730 } else { 6731 if (dst != src) { 6732 movq(dst, src); 6733 } 6734 shlq(dst, LogMinObjAlignmentInBytes); 6735 if (Universe::narrow_oop_base() != NULL) { 6736 addq(dst, r12_heapbase); 6737 } 6738 } 6739 } else { 6740 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6741 if (dst != src) { 6742 movq(dst, src); 6743 } 6744 } 6745 } 6746 6747 void MacroAssembler::encode_klass_not_null(Register r) { 6748 if (Universe::narrow_klass_base() != NULL) { 6749 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6750 assert(r != r12_heapbase, "Encoding a klass in r12"); 6751 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6752 subq(r, r12_heapbase); 6753 } 6754 if (Universe::narrow_klass_shift() != 0) { 6755 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6756 shrq(r, LogKlassAlignmentInBytes); 6757 } 6758 if (Universe::narrow_klass_base() != NULL) { 6759 reinit_heapbase(); 6760 } 6761 } 6762 6763 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6764 if (dst == src) { 6765 encode_klass_not_null(src); 6766 } else { 6767 if (Universe::narrow_klass_base() != NULL) { 6768 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6769 negq(dst); 6770 addq(dst, src); 6771 } else { 6772 movptr(dst, src); 6773 } 6774 if (Universe::narrow_klass_shift() != 0) { 6775 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6776 shrq(dst, LogKlassAlignmentInBytes); 6777 } 6778 } 6779 } 6780 6781 // Function instr_size_for_decode_klass_not_null() counts the instructions 6782 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6783 // when (Universe::heap() != NULL). Hence, if the instructions they 6784 // generate change, then this method needs to be updated. 6785 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6786 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6787 if (Universe::narrow_klass_base() != NULL) { 6788 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6789 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6790 } else { 6791 // longest load decode klass function, mov64, leaq 6792 return 16; 6793 } 6794 } 6795 6796 // !!! If the instructions that get generated here change then function 6797 // instr_size_for_decode_klass_not_null() needs to get updated. 6798 void MacroAssembler::decode_klass_not_null(Register r) { 6799 // Note: it will change flags 6800 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6801 assert(r != r12_heapbase, "Decoding a klass in r12"); 6802 // Cannot assert, unverified entry point counts instructions (see .ad file) 6803 // vtableStubs also counts instructions in pd_code_size_limit. 6804 // Also do not verify_oop as this is called by verify_oop. 6805 if (Universe::narrow_klass_shift() != 0) { 6806 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6807 shlq(r, LogKlassAlignmentInBytes); 6808 } 6809 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6810 if (Universe::narrow_klass_base() != NULL) { 6811 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6812 addq(r, r12_heapbase); 6813 reinit_heapbase(); 6814 } 6815 } 6816 6817 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6818 // Note: it will change flags 6819 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6820 if (dst == src) { 6821 decode_klass_not_null(dst); 6822 } else { 6823 // Cannot assert, unverified entry point counts instructions (see .ad file) 6824 // vtableStubs also counts instructions in pd_code_size_limit. 6825 // Also do not verify_oop as this is called by verify_oop. 6826 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6827 if (Universe::narrow_klass_shift() != 0) { 6828 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6829 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6830 leaq(dst, Address(dst, src, Address::times_8, 0)); 6831 } else { 6832 addq(dst, src); 6833 } 6834 } 6835 } 6836 6837 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6838 assert (UseCompressedOops, "should only be used for compressed headers"); 6839 assert (Universe::heap() != NULL, "java heap should be initialized"); 6840 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6841 int oop_index = oop_recorder()->find_index(obj); 6842 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6843 mov_narrow_oop(dst, oop_index, rspec); 6844 } 6845 6846 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6847 assert (UseCompressedOops, "should only be used for compressed headers"); 6848 assert (Universe::heap() != NULL, "java heap should be initialized"); 6849 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6850 int oop_index = oop_recorder()->find_index(obj); 6851 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6852 mov_narrow_oop(dst, oop_index, rspec); 6853 } 6854 6855 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6856 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6857 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6858 int klass_index = oop_recorder()->find_index(k); 6859 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6860 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6861 } 6862 6863 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6864 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6865 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6866 int klass_index = oop_recorder()->find_index(k); 6867 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6868 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6869 } 6870 6871 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6872 assert (UseCompressedOops, "should only be used for compressed headers"); 6873 assert (Universe::heap() != NULL, "java heap should be initialized"); 6874 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6875 int oop_index = oop_recorder()->find_index(obj); 6876 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6877 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6878 } 6879 6880 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6881 assert (UseCompressedOops, "should only be used for compressed headers"); 6882 assert (Universe::heap() != NULL, "java heap should be initialized"); 6883 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6884 int oop_index = oop_recorder()->find_index(obj); 6885 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6886 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6887 } 6888 6889 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6890 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6891 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6892 int klass_index = oop_recorder()->find_index(k); 6893 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6894 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6895 } 6896 6897 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6898 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6899 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6900 int klass_index = oop_recorder()->find_index(k); 6901 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6902 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6903 } 6904 6905 void MacroAssembler::reinit_heapbase() { 6906 if (UseCompressedOops || UseCompressedClassPointers) { 6907 if (Universe::heap() != NULL) { 6908 if (Universe::narrow_oop_base() == NULL) { 6909 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6910 } else { 6911 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6912 } 6913 } else { 6914 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6915 } 6916 } 6917 } 6918 6919 #endif // _LP64 6920 6921 6922 // C2 compiled method's prolog code. 6923 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6924 6925 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6926 // NativeJump::patch_verified_entry will be able to patch out the entry 6927 // code safely. The push to verify stack depth is ok at 5 bytes, 6928 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6929 // stack bang then we must use the 6 byte frame allocation even if 6930 // we have no frame. :-( 6931 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6932 6933 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6934 // Remove word for return addr 6935 framesize -= wordSize; 6936 stack_bang_size -= wordSize; 6937 6938 // Calls to C2R adapters often do not accept exceptional returns. 6939 // We require that their callers must bang for them. But be careful, because 6940 // some VM calls (such as call site linkage) can use several kilobytes of 6941 // stack. But the stack safety zone should account for that. 6942 // See bugs 4446381, 4468289, 4497237. 6943 if (stack_bang_size > 0) { 6944 generate_stack_overflow_check(stack_bang_size); 6945 6946 // We always push rbp, so that on return to interpreter rbp, will be 6947 // restored correctly and we can correct the stack. 6948 push(rbp); 6949 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6950 if (PreserveFramePointer) { 6951 mov(rbp, rsp); 6952 } 6953 // Remove word for ebp 6954 framesize -= wordSize; 6955 6956 // Create frame 6957 if (framesize) { 6958 subptr(rsp, framesize); 6959 } 6960 } else { 6961 // Create frame (force generation of a 4 byte immediate value) 6962 subptr_imm32(rsp, framesize); 6963 6964 // Save RBP register now. 6965 framesize -= wordSize; 6966 movptr(Address(rsp, framesize), rbp); 6967 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6968 if (PreserveFramePointer) { 6969 movptr(rbp, rsp); 6970 if (framesize > 0) { 6971 addptr(rbp, framesize); 6972 } 6973 } 6974 } 6975 6976 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6977 framesize -= wordSize; 6978 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6979 } 6980 6981 #ifndef _LP64 6982 // If method sets FPU control word do it now 6983 if (fp_mode_24b) { 6984 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6985 } 6986 if (UseSSE >= 2 && VerifyFPU) { 6987 verify_FPU(0, "FPU stack must be clean on entry"); 6988 } 6989 #endif 6990 6991 #ifdef ASSERT 6992 if (VerifyStackAtCalls) { 6993 Label L; 6994 push(rax); 6995 mov(rax, rsp); 6996 andptr(rax, StackAlignmentInBytes-1); 6997 cmpptr(rax, StackAlignmentInBytes-wordSize); 6998 pop(rax); 6999 jcc(Assembler::equal, L); 7000 STOP("Stack is not properly aligned!"); 7001 bind(L); 7002 } 7003 #endif 7004 7005 } 7006 7007 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7008 // cnt - number of qwords (8-byte words). 7009 // base - start address, qword aligned. 7010 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7011 assert(base==rdi, "base register must be edi for rep stos"); 7012 assert(tmp==rax, "tmp register must be eax for rep stos"); 7013 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7014 assert(InitArrayShortSize % BytesPerLong == 0, 7015 "InitArrayShortSize should be the multiple of BytesPerLong"); 7016 7017 Label DONE; 7018 7019 xorptr(tmp, tmp); 7020 7021 if (!is_large) { 7022 Label LOOP, LONG; 7023 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7024 jccb(Assembler::greater, LONG); 7025 7026 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7027 7028 decrement(cnt); 7029 jccb(Assembler::negative, DONE); // Zero length 7030 7031 // Use individual pointer-sized stores for small counts: 7032 BIND(LOOP); 7033 movptr(Address(base, cnt, Address::times_ptr), tmp); 7034 decrement(cnt); 7035 jccb(Assembler::greaterEqual, LOOP); 7036 jmpb(DONE); 7037 7038 BIND(LONG); 7039 } 7040 7041 // Use longer rep-prefixed ops for non-small counts: 7042 if (UseFastStosb) { 7043 shlptr(cnt, 3); // convert to number of bytes 7044 rep_stosb(); 7045 } else { 7046 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7047 rep_stos(); 7048 } 7049 7050 BIND(DONE); 7051 } 7052 7053 #ifdef COMPILER2 7054 7055 // IndexOf for constant substrings with size >= 8 chars 7056 // which don't need to be loaded through stack. 7057 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7058 Register cnt1, Register cnt2, 7059 int int_cnt2, Register result, 7060 XMMRegister vec, Register tmp, 7061 int ae) { 7062 ShortBranchVerifier sbv(this); 7063 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7064 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7065 7066 // This method uses the pcmpestri instruction with bound registers 7067 // inputs: 7068 // xmm - substring 7069 // rax - substring length (elements count) 7070 // mem - scanned string 7071 // rdx - string length (elements count) 7072 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7073 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7074 // outputs: 7075 // rcx - matched index in string 7076 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7077 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7078 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7079 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7080 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7081 7082 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7083 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7084 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7085 7086 // Note, inline_string_indexOf() generates checks: 7087 // if (substr.count > string.count) return -1; 7088 // if (substr.count == 0) return 0; 7089 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7090 7091 // Load substring. 7092 if (ae == StrIntrinsicNode::UL) { 7093 pmovzxbw(vec, Address(str2, 0)); 7094 } else { 7095 movdqu(vec, Address(str2, 0)); 7096 } 7097 movl(cnt2, int_cnt2); 7098 movptr(result, str1); // string addr 7099 7100 if (int_cnt2 > stride) { 7101 jmpb(SCAN_TO_SUBSTR); 7102 7103 // Reload substr for rescan, this code 7104 // is executed only for large substrings (> 8 chars) 7105 bind(RELOAD_SUBSTR); 7106 if (ae == StrIntrinsicNode::UL) { 7107 pmovzxbw(vec, Address(str2, 0)); 7108 } else { 7109 movdqu(vec, Address(str2, 0)); 7110 } 7111 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7112 7113 bind(RELOAD_STR); 7114 // We came here after the beginning of the substring was 7115 // matched but the rest of it was not so we need to search 7116 // again. Start from the next element after the previous match. 7117 7118 // cnt2 is number of substring reminding elements and 7119 // cnt1 is number of string reminding elements when cmp failed. 7120 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7121 subl(cnt1, cnt2); 7122 addl(cnt1, int_cnt2); 7123 movl(cnt2, int_cnt2); // Now restore cnt2 7124 7125 decrementl(cnt1); // Shift to next element 7126 cmpl(cnt1, cnt2); 7127 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7128 7129 addptr(result, (1<<scale1)); 7130 7131 } // (int_cnt2 > 8) 7132 7133 // Scan string for start of substr in 16-byte vectors 7134 bind(SCAN_TO_SUBSTR); 7135 pcmpestri(vec, Address(result, 0), mode); 7136 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7137 subl(cnt1, stride); 7138 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7139 cmpl(cnt1, cnt2); 7140 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7141 addptr(result, 16); 7142 jmpb(SCAN_TO_SUBSTR); 7143 7144 // Found a potential substr 7145 bind(FOUND_CANDIDATE); 7146 // Matched whole vector if first element matched (tmp(rcx) == 0). 7147 if (int_cnt2 == stride) { 7148 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7149 } else { // int_cnt2 > 8 7150 jccb(Assembler::overflow, FOUND_SUBSTR); 7151 } 7152 // After pcmpestri tmp(rcx) contains matched element index 7153 // Compute start addr of substr 7154 lea(result, Address(result, tmp, scale1)); 7155 7156 // Make sure string is still long enough 7157 subl(cnt1, tmp); 7158 cmpl(cnt1, cnt2); 7159 if (int_cnt2 == stride) { 7160 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7161 } else { // int_cnt2 > 8 7162 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7163 } 7164 // Left less then substring. 7165 7166 bind(RET_NOT_FOUND); 7167 movl(result, -1); 7168 jmp(EXIT); 7169 7170 if (int_cnt2 > stride) { 7171 // This code is optimized for the case when whole substring 7172 // is matched if its head is matched. 7173 bind(MATCH_SUBSTR_HEAD); 7174 pcmpestri(vec, Address(result, 0), mode); 7175 // Reload only string if does not match 7176 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 7177 7178 Label CONT_SCAN_SUBSTR; 7179 // Compare the rest of substring (> 8 chars). 7180 bind(FOUND_SUBSTR); 7181 // First 8 chars are already matched. 7182 negptr(cnt2); 7183 addptr(cnt2, stride); 7184 7185 bind(SCAN_SUBSTR); 7186 subl(cnt1, stride); 7187 cmpl(cnt2, -stride); // Do not read beyond substring 7188 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7189 // Back-up strings to avoid reading beyond substring: 7190 // cnt1 = cnt1 - cnt2 + 8 7191 addl(cnt1, cnt2); // cnt2 is negative 7192 addl(cnt1, stride); 7193 movl(cnt2, stride); negptr(cnt2); 7194 bind(CONT_SCAN_SUBSTR); 7195 if (int_cnt2 < (int)G) { 7196 int tail_off1 = int_cnt2<<scale1; 7197 int tail_off2 = int_cnt2<<scale2; 7198 if (ae == StrIntrinsicNode::UL) { 7199 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7200 } else { 7201 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7202 } 7203 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7204 } else { 7205 // calculate index in register to avoid integer overflow (int_cnt2*2) 7206 movl(tmp, int_cnt2); 7207 addptr(tmp, cnt2); 7208 if (ae == StrIntrinsicNode::UL) { 7209 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7210 } else { 7211 movdqu(vec, Address(str2, tmp, scale2, 0)); 7212 } 7213 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7214 } 7215 // Need to reload strings pointers if not matched whole vector 7216 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7217 addptr(cnt2, stride); 7218 jcc(Assembler::negative, SCAN_SUBSTR); 7219 // Fall through if found full substring 7220 7221 } // (int_cnt2 > 8) 7222 7223 bind(RET_FOUND); 7224 // Found result if we matched full small substring. 7225 // Compute substr offset 7226 subptr(result, str1); 7227 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7228 shrl(result, 1); // index 7229 } 7230 bind(EXIT); 7231 7232 } // string_indexofC8 7233 7234 // Small strings are loaded through stack if they cross page boundary. 7235 void MacroAssembler::string_indexof(Register str1, Register str2, 7236 Register cnt1, Register cnt2, 7237 int int_cnt2, Register result, 7238 XMMRegister vec, Register tmp, 7239 int ae) { 7240 ShortBranchVerifier sbv(this); 7241 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7242 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7243 7244 // 7245 // int_cnt2 is length of small (< 8 chars) constant substring 7246 // or (-1) for non constant substring in which case its length 7247 // is in cnt2 register. 7248 // 7249 // Note, inline_string_indexOf() generates checks: 7250 // if (substr.count > string.count) return -1; 7251 // if (substr.count == 0) return 0; 7252 // 7253 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7254 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7255 // This method uses the pcmpestri instruction with bound registers 7256 // inputs: 7257 // xmm - substring 7258 // rax - substring length (elements count) 7259 // mem - scanned string 7260 // rdx - string length (elements count) 7261 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7262 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7263 // outputs: 7264 // rcx - matched index in string 7265 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7266 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7267 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7268 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7269 7270 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7271 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7272 FOUND_CANDIDATE; 7273 7274 { //======================================================== 7275 // We don't know where these strings are located 7276 // and we can't read beyond them. Load them through stack. 7277 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7278 7279 movptr(tmp, rsp); // save old SP 7280 7281 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7282 if (int_cnt2 == (1>>scale2)) { // One byte 7283 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7284 load_unsigned_byte(result, Address(str2, 0)); 7285 movdl(vec, result); // move 32 bits 7286 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7287 // Not enough header space in 32-bit VM: 12+3 = 15. 7288 movl(result, Address(str2, -1)); 7289 shrl(result, 8); 7290 movdl(vec, result); // move 32 bits 7291 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7292 load_unsigned_short(result, Address(str2, 0)); 7293 movdl(vec, result); // move 32 bits 7294 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7295 movdl(vec, Address(str2, 0)); // move 32 bits 7296 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7297 movq(vec, Address(str2, 0)); // move 64 bits 7298 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7299 // Array header size is 12 bytes in 32-bit VM 7300 // + 6 bytes for 3 chars == 18 bytes, 7301 // enough space to load vec and shift. 7302 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7303 if (ae == StrIntrinsicNode::UL) { 7304 int tail_off = int_cnt2-8; 7305 pmovzxbw(vec, Address(str2, tail_off)); 7306 psrldq(vec, -2*tail_off); 7307 } 7308 else { 7309 int tail_off = int_cnt2*(1<<scale2); 7310 movdqu(vec, Address(str2, tail_off-16)); 7311 psrldq(vec, 16-tail_off); 7312 } 7313 } 7314 } else { // not constant substring 7315 cmpl(cnt2, stride); 7316 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7317 7318 // We can read beyond string if srt+16 does not cross page boundary 7319 // since heaps are aligned and mapped by pages. 7320 assert(os::vm_page_size() < (int)G, "default page should be small"); 7321 movl(result, str2); // We need only low 32 bits 7322 andl(result, (os::vm_page_size()-1)); 7323 cmpl(result, (os::vm_page_size()-16)); 7324 jccb(Assembler::belowEqual, CHECK_STR); 7325 7326 // Move small strings to stack to allow load 16 bytes into vec. 7327 subptr(rsp, 16); 7328 int stk_offset = wordSize-(1<<scale2); 7329 push(cnt2); 7330 7331 bind(COPY_SUBSTR); 7332 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7333 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7334 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7335 } else if (ae == StrIntrinsicNode::UU) { 7336 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7337 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7338 } 7339 decrement(cnt2); 7340 jccb(Assembler::notZero, COPY_SUBSTR); 7341 7342 pop(cnt2); 7343 movptr(str2, rsp); // New substring address 7344 } // non constant 7345 7346 bind(CHECK_STR); 7347 cmpl(cnt1, stride); 7348 jccb(Assembler::aboveEqual, BIG_STRINGS); 7349 7350 // Check cross page boundary. 7351 movl(result, str1); // We need only low 32 bits 7352 andl(result, (os::vm_page_size()-1)); 7353 cmpl(result, (os::vm_page_size()-16)); 7354 jccb(Assembler::belowEqual, BIG_STRINGS); 7355 7356 subptr(rsp, 16); 7357 int stk_offset = -(1<<scale1); 7358 if (int_cnt2 < 0) { // not constant 7359 push(cnt2); 7360 stk_offset += wordSize; 7361 } 7362 movl(cnt2, cnt1); 7363 7364 bind(COPY_STR); 7365 if (ae == StrIntrinsicNode::LL) { 7366 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7367 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7368 } else { 7369 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7370 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7371 } 7372 decrement(cnt2); 7373 jccb(Assembler::notZero, COPY_STR); 7374 7375 if (int_cnt2 < 0) { // not constant 7376 pop(cnt2); 7377 } 7378 movptr(str1, rsp); // New string address 7379 7380 bind(BIG_STRINGS); 7381 // Load substring. 7382 if (int_cnt2 < 0) { // -1 7383 if (ae == StrIntrinsicNode::UL) { 7384 pmovzxbw(vec, Address(str2, 0)); 7385 } else { 7386 movdqu(vec, Address(str2, 0)); 7387 } 7388 push(cnt2); // substr count 7389 push(str2); // substr addr 7390 push(str1); // string addr 7391 } else { 7392 // Small (< 8 chars) constant substrings are loaded already. 7393 movl(cnt2, int_cnt2); 7394 } 7395 push(tmp); // original SP 7396 7397 } // Finished loading 7398 7399 //======================================================== 7400 // Start search 7401 // 7402 7403 movptr(result, str1); // string addr 7404 7405 if (int_cnt2 < 0) { // Only for non constant substring 7406 jmpb(SCAN_TO_SUBSTR); 7407 7408 // SP saved at sp+0 7409 // String saved at sp+1*wordSize 7410 // Substr saved at sp+2*wordSize 7411 // Substr count saved at sp+3*wordSize 7412 7413 // Reload substr for rescan, this code 7414 // is executed only for large substrings (> 8 chars) 7415 bind(RELOAD_SUBSTR); 7416 movptr(str2, Address(rsp, 2*wordSize)); 7417 movl(cnt2, Address(rsp, 3*wordSize)); 7418 if (ae == StrIntrinsicNode::UL) { 7419 pmovzxbw(vec, Address(str2, 0)); 7420 } else { 7421 movdqu(vec, Address(str2, 0)); 7422 } 7423 // We came here after the beginning of the substring was 7424 // matched but the rest of it was not so we need to search 7425 // again. Start from the next element after the previous match. 7426 subptr(str1, result); // Restore counter 7427 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7428 shrl(str1, 1); 7429 } 7430 addl(cnt1, str1); 7431 decrementl(cnt1); // Shift to next element 7432 cmpl(cnt1, cnt2); 7433 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7434 7435 addptr(result, (1<<scale1)); 7436 } // non constant 7437 7438 // Scan string for start of substr in 16-byte vectors 7439 bind(SCAN_TO_SUBSTR); 7440 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7441 pcmpestri(vec, Address(result, 0), mode); 7442 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7443 subl(cnt1, stride); 7444 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7445 cmpl(cnt1, cnt2); 7446 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7447 addptr(result, 16); 7448 7449 bind(ADJUST_STR); 7450 cmpl(cnt1, stride); // Do not read beyond string 7451 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7452 // Back-up string to avoid reading beyond string. 7453 lea(result, Address(result, cnt1, scale1, -16)); 7454 movl(cnt1, stride); 7455 jmpb(SCAN_TO_SUBSTR); 7456 7457 // Found a potential substr 7458 bind(FOUND_CANDIDATE); 7459 // After pcmpestri tmp(rcx) contains matched element index 7460 7461 // Make sure string is still long enough 7462 subl(cnt1, tmp); 7463 cmpl(cnt1, cnt2); 7464 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7465 // Left less then substring. 7466 7467 bind(RET_NOT_FOUND); 7468 movl(result, -1); 7469 jmpb(CLEANUP); 7470 7471 bind(FOUND_SUBSTR); 7472 // Compute start addr of substr 7473 lea(result, Address(result, tmp, scale1)); 7474 if (int_cnt2 > 0) { // Constant substring 7475 // Repeat search for small substring (< 8 chars) 7476 // from new point without reloading substring. 7477 // Have to check that we don't read beyond string. 7478 cmpl(tmp, stride-int_cnt2); 7479 jccb(Assembler::greater, ADJUST_STR); 7480 // Fall through if matched whole substring. 7481 } else { // non constant 7482 assert(int_cnt2 == -1, "should be != 0"); 7483 7484 addl(tmp, cnt2); 7485 // Found result if we matched whole substring. 7486 cmpl(tmp, stride); 7487 jccb(Assembler::lessEqual, RET_FOUND); 7488 7489 // Repeat search for small substring (<= 8 chars) 7490 // from new point 'str1' without reloading substring. 7491 cmpl(cnt2, stride); 7492 // Have to check that we don't read beyond string. 7493 jccb(Assembler::lessEqual, ADJUST_STR); 7494 7495 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7496 // Compare the rest of substring (> 8 chars). 7497 movptr(str1, result); 7498 7499 cmpl(tmp, cnt2); 7500 // First 8 chars are already matched. 7501 jccb(Assembler::equal, CHECK_NEXT); 7502 7503 bind(SCAN_SUBSTR); 7504 pcmpestri(vec, Address(str1, 0), mode); 7505 // Need to reload strings pointers if not matched whole vector 7506 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7507 7508 bind(CHECK_NEXT); 7509 subl(cnt2, stride); 7510 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7511 addptr(str1, 16); 7512 if (ae == StrIntrinsicNode::UL) { 7513 addptr(str2, 8); 7514 } else { 7515 addptr(str2, 16); 7516 } 7517 subl(cnt1, stride); 7518 cmpl(cnt2, stride); // Do not read beyond substring 7519 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7520 // Back-up strings to avoid reading beyond substring. 7521 7522 if (ae == StrIntrinsicNode::UL) { 7523 lea(str2, Address(str2, cnt2, scale2, -8)); 7524 lea(str1, Address(str1, cnt2, scale1, -16)); 7525 } else { 7526 lea(str2, Address(str2, cnt2, scale2, -16)); 7527 lea(str1, Address(str1, cnt2, scale1, -16)); 7528 } 7529 subl(cnt1, cnt2); 7530 movl(cnt2, stride); 7531 addl(cnt1, stride); 7532 bind(CONT_SCAN_SUBSTR); 7533 if (ae == StrIntrinsicNode::UL) { 7534 pmovzxbw(vec, Address(str2, 0)); 7535 } else { 7536 movdqu(vec, Address(str2, 0)); 7537 } 7538 jmp(SCAN_SUBSTR); 7539 7540 bind(RET_FOUND_LONG); 7541 movptr(str1, Address(rsp, wordSize)); 7542 } // non constant 7543 7544 bind(RET_FOUND); 7545 // Compute substr offset 7546 subptr(result, str1); 7547 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7548 shrl(result, 1); // index 7549 } 7550 bind(CLEANUP); 7551 pop(rsp); // restore SP 7552 7553 } // string_indexof 7554 7555 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7556 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7557 ShortBranchVerifier sbv(this); 7558 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7559 7560 int stride = 8; 7561 7562 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7563 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7564 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7565 FOUND_SEQ_CHAR, DONE_LABEL; 7566 7567 movptr(result, str1); 7568 if (UseAVX >= 2) { 7569 cmpl(cnt1, stride); 7570 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7571 cmpl(cnt1, 2*stride); 7572 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7573 movdl(vec1, ch); 7574 vpbroadcastw(vec1, vec1); 7575 vpxor(vec2, vec2); 7576 movl(tmp, cnt1); 7577 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7578 andl(cnt1,0x0000000F); //tail count (in chars) 7579 7580 bind(SCAN_TO_16_CHAR_LOOP); 7581 vmovdqu(vec3, Address(result, 0)); 7582 vpcmpeqw(vec3, vec3, vec1, 1); 7583 vptest(vec2, vec3); 7584 jcc(Assembler::carryClear, FOUND_CHAR); 7585 addptr(result, 32); 7586 subl(tmp, 2*stride); 7587 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7588 jmp(SCAN_TO_8_CHAR); 7589 bind(SCAN_TO_8_CHAR_INIT); 7590 movdl(vec1, ch); 7591 pshuflw(vec1, vec1, 0x00); 7592 pshufd(vec1, vec1, 0); 7593 pxor(vec2, vec2); 7594 } 7595 bind(SCAN_TO_8_CHAR); 7596 cmpl(cnt1, stride); 7597 if (UseAVX >= 2) { 7598 jcc(Assembler::less, SCAN_TO_CHAR); 7599 } else { 7600 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7601 movdl(vec1, ch); 7602 pshuflw(vec1, vec1, 0x00); 7603 pshufd(vec1, vec1, 0); 7604 pxor(vec2, vec2); 7605 } 7606 movl(tmp, cnt1); 7607 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7608 andl(cnt1,0x00000007); //tail count (in chars) 7609 7610 bind(SCAN_TO_8_CHAR_LOOP); 7611 movdqu(vec3, Address(result, 0)); 7612 pcmpeqw(vec3, vec1); 7613 ptest(vec2, vec3); 7614 jcc(Assembler::carryClear, FOUND_CHAR); 7615 addptr(result, 16); 7616 subl(tmp, stride); 7617 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7618 bind(SCAN_TO_CHAR); 7619 testl(cnt1, cnt1); 7620 jcc(Assembler::zero, RET_NOT_FOUND); 7621 bind(SCAN_TO_CHAR_LOOP); 7622 load_unsigned_short(tmp, Address(result, 0)); 7623 cmpl(ch, tmp); 7624 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7625 addptr(result, 2); 7626 subl(cnt1, 1); 7627 jccb(Assembler::zero, RET_NOT_FOUND); 7628 jmp(SCAN_TO_CHAR_LOOP); 7629 7630 bind(RET_NOT_FOUND); 7631 movl(result, -1); 7632 jmpb(DONE_LABEL); 7633 7634 bind(FOUND_CHAR); 7635 if (UseAVX >= 2) { 7636 vpmovmskb(tmp, vec3); 7637 } else { 7638 pmovmskb(tmp, vec3); 7639 } 7640 bsfl(ch, tmp); 7641 addl(result, ch); 7642 7643 bind(FOUND_SEQ_CHAR); 7644 subptr(result, str1); 7645 shrl(result, 1); 7646 7647 bind(DONE_LABEL); 7648 } // string_indexof_char 7649 7650 // helper function for string_compare 7651 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7652 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7653 Address::ScaleFactor scale2, Register index, int ae) { 7654 if (ae == StrIntrinsicNode::LL) { 7655 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7656 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7657 } else if (ae == StrIntrinsicNode::UU) { 7658 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7659 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7660 } else { 7661 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7662 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7663 } 7664 } 7665 7666 // Compare strings, used for char[] and byte[]. 7667 void MacroAssembler::string_compare(Register str1, Register str2, 7668 Register cnt1, Register cnt2, Register result, 7669 XMMRegister vec1, int ae) { 7670 ShortBranchVerifier sbv(this); 7671 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7672 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7673 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7674 int stride2x2 = 0x40; 7675 Address::ScaleFactor scale = Address::no_scale; 7676 Address::ScaleFactor scale1 = Address::no_scale; 7677 Address::ScaleFactor scale2 = Address::no_scale; 7678 7679 if (ae != StrIntrinsicNode::LL) { 7680 stride2x2 = 0x20; 7681 } 7682 7683 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7684 shrl(cnt2, 1); 7685 } 7686 // Compute the minimum of the string lengths and the 7687 // difference of the string lengths (stack). 7688 // Do the conditional move stuff 7689 movl(result, cnt1); 7690 subl(cnt1, cnt2); 7691 push(cnt1); 7692 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7693 7694 // Is the minimum length zero? 7695 testl(cnt2, cnt2); 7696 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7697 if (ae == StrIntrinsicNode::LL) { 7698 // Load first bytes 7699 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7700 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7701 } else if (ae == StrIntrinsicNode::UU) { 7702 // Load first characters 7703 load_unsigned_short(result, Address(str1, 0)); 7704 load_unsigned_short(cnt1, Address(str2, 0)); 7705 } else { 7706 load_unsigned_byte(result, Address(str1, 0)); 7707 load_unsigned_short(cnt1, Address(str2, 0)); 7708 } 7709 subl(result, cnt1); 7710 jcc(Assembler::notZero, POP_LABEL); 7711 7712 if (ae == StrIntrinsicNode::UU) { 7713 // Divide length by 2 to get number of chars 7714 shrl(cnt2, 1); 7715 } 7716 cmpl(cnt2, 1); 7717 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7718 7719 // Check if the strings start at the same location and setup scale and stride 7720 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7721 cmpptr(str1, str2); 7722 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7723 if (ae == StrIntrinsicNode::LL) { 7724 scale = Address::times_1; 7725 stride = 16; 7726 } else { 7727 scale = Address::times_2; 7728 stride = 8; 7729 } 7730 } else { 7731 scale1 = Address::times_1; 7732 scale2 = Address::times_2; 7733 // scale not used 7734 stride = 8; 7735 } 7736 7737 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7738 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7739 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7740 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7741 Label COMPARE_TAIL_LONG; 7742 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7743 7744 int pcmpmask = 0x19; 7745 if (ae == StrIntrinsicNode::LL) { 7746 pcmpmask &= ~0x01; 7747 } 7748 7749 // Setup to compare 16-chars (32-bytes) vectors, 7750 // start from first character again because it has aligned address. 7751 if (ae == StrIntrinsicNode::LL) { 7752 stride2 = 32; 7753 } else { 7754 stride2 = 16; 7755 } 7756 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7757 adr_stride = stride << scale; 7758 } else { 7759 adr_stride1 = 8; //stride << scale1; 7760 adr_stride2 = 16; //stride << scale2; 7761 } 7762 7763 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7764 // rax and rdx are used by pcmpestri as elements counters 7765 movl(result, cnt2); 7766 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7767 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7768 7769 // fast path : compare first 2 8-char vectors. 7770 bind(COMPARE_16_CHARS); 7771 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7772 movdqu(vec1, Address(str1, 0)); 7773 } else { 7774 pmovzxbw(vec1, Address(str1, 0)); 7775 } 7776 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7777 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7778 7779 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7780 movdqu(vec1, Address(str1, adr_stride)); 7781 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7782 } else { 7783 pmovzxbw(vec1, Address(str1, adr_stride1)); 7784 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7785 } 7786 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7787 addl(cnt1, stride); 7788 7789 // Compare the characters at index in cnt1 7790 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7791 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7792 subl(result, cnt2); 7793 jmp(POP_LABEL); 7794 7795 // Setup the registers to start vector comparison loop 7796 bind(COMPARE_WIDE_VECTORS); 7797 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7798 lea(str1, Address(str1, result, scale)); 7799 lea(str2, Address(str2, result, scale)); 7800 } else { 7801 lea(str1, Address(str1, result, scale1)); 7802 lea(str2, Address(str2, result, scale2)); 7803 } 7804 subl(result, stride2); 7805 subl(cnt2, stride2); 7806 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7807 negptr(result); 7808 7809 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7810 bind(COMPARE_WIDE_VECTORS_LOOP); 7811 7812 #ifdef _LP64 7813 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7814 cmpl(cnt2, stride2x2); 7815 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7816 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7817 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7818 7819 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7820 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7821 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7822 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7823 } else { 7824 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7825 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7826 } 7827 kortestql(k7, k7); 7828 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7829 addptr(result, stride2x2); // update since we already compared at this addr 7830 subl(cnt2, stride2x2); // and sub the size too 7831 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7832 7833 vpxor(vec1, vec1); 7834 jmpb(COMPARE_WIDE_TAIL); 7835 }//if (VM_Version::supports_avx512vlbw()) 7836 #endif // _LP64 7837 7838 7839 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7840 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7841 vmovdqu(vec1, Address(str1, result, scale)); 7842 vpxor(vec1, Address(str2, result, scale)); 7843 } else { 7844 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7845 vpxor(vec1, Address(str2, result, scale2)); 7846 } 7847 vptest(vec1, vec1); 7848 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7849 addptr(result, stride2); 7850 subl(cnt2, stride2); 7851 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7852 // clean upper bits of YMM registers 7853 vpxor(vec1, vec1); 7854 7855 // compare wide vectors tail 7856 bind(COMPARE_WIDE_TAIL); 7857 testptr(result, result); 7858 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7859 7860 movl(result, stride2); 7861 movl(cnt2, result); 7862 negptr(result); 7863 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7864 7865 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 7866 bind(VECTOR_NOT_EQUAL); 7867 // clean upper bits of YMM registers 7868 vpxor(vec1, vec1); 7869 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7870 lea(str1, Address(str1, result, scale)); 7871 lea(str2, Address(str2, result, scale)); 7872 } else { 7873 lea(str1, Address(str1, result, scale1)); 7874 lea(str2, Address(str2, result, scale2)); 7875 } 7876 jmp(COMPARE_16_CHARS); 7877 7878 // Compare tail chars, length between 1 to 15 chars 7879 bind(COMPARE_TAIL_LONG); 7880 movl(cnt2, result); 7881 cmpl(cnt2, stride); 7882 jcc(Assembler::less, COMPARE_SMALL_STR); 7883 7884 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7885 movdqu(vec1, Address(str1, 0)); 7886 } else { 7887 pmovzxbw(vec1, Address(str1, 0)); 7888 } 7889 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7890 jcc(Assembler::below, COMPARE_INDEX_CHAR); 7891 subptr(cnt2, stride); 7892 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7893 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7894 lea(str1, Address(str1, result, scale)); 7895 lea(str2, Address(str2, result, scale)); 7896 } else { 7897 lea(str1, Address(str1, result, scale1)); 7898 lea(str2, Address(str2, result, scale2)); 7899 } 7900 negptr(cnt2); 7901 jmpb(WHILE_HEAD_LABEL); 7902 7903 bind(COMPARE_SMALL_STR); 7904 } else if (UseSSE42Intrinsics) { 7905 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 7906 int pcmpmask = 0x19; 7907 // Setup to compare 8-char (16-byte) vectors, 7908 // start from first character again because it has aligned address. 7909 movl(result, cnt2); 7910 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 7911 if (ae == StrIntrinsicNode::LL) { 7912 pcmpmask &= ~0x01; 7913 } 7914 jcc(Assembler::zero, COMPARE_TAIL); 7915 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7916 lea(str1, Address(str1, result, scale)); 7917 lea(str2, Address(str2, result, scale)); 7918 } else { 7919 lea(str1, Address(str1, result, scale1)); 7920 lea(str2, Address(str2, result, scale2)); 7921 } 7922 negptr(result); 7923 7924 // pcmpestri 7925 // inputs: 7926 // vec1- substring 7927 // rax - negative string length (elements count) 7928 // mem - scanned string 7929 // rdx - string length (elements count) 7930 // pcmpmask - cmp mode: 11000 (string compare with negated result) 7931 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 7932 // outputs: 7933 // rcx - first mismatched element index 7934 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7935 7936 bind(COMPARE_WIDE_VECTORS); 7937 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7938 movdqu(vec1, Address(str1, result, scale)); 7939 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7940 } else { 7941 pmovzxbw(vec1, Address(str1, result, scale1)); 7942 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7943 } 7944 // After pcmpestri cnt1(rcx) contains mismatched element index 7945 7946 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 7947 addptr(result, stride); 7948 subptr(cnt2, stride); 7949 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 7950 7951 // compare wide vectors tail 7952 testptr(result, result); 7953 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7954 7955 movl(cnt2, stride); 7956 movl(result, stride); 7957 negptr(result); 7958 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7959 movdqu(vec1, Address(str1, result, scale)); 7960 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7961 } else { 7962 pmovzxbw(vec1, Address(str1, result, scale1)); 7963 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7964 } 7965 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 7966 7967 // Mismatched characters in the vectors 7968 bind(VECTOR_NOT_EQUAL); 7969 addptr(cnt1, result); 7970 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7971 subl(result, cnt2); 7972 jmpb(POP_LABEL); 7973 7974 bind(COMPARE_TAIL); // limit is zero 7975 movl(cnt2, result); 7976 // Fallthru to tail compare 7977 } 7978 // Shift str2 and str1 to the end of the arrays, negate min 7979 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7980 lea(str1, Address(str1, cnt2, scale)); 7981 lea(str2, Address(str2, cnt2, scale)); 7982 } else { 7983 lea(str1, Address(str1, cnt2, scale1)); 7984 lea(str2, Address(str2, cnt2, scale2)); 7985 } 7986 decrementl(cnt2); // first character was compared already 7987 negptr(cnt2); 7988 7989 // Compare the rest of the elements 7990 bind(WHILE_HEAD_LABEL); 7991 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 7992 subl(result, cnt1); 7993 jccb(Assembler::notZero, POP_LABEL); 7994 increment(cnt2); 7995 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 7996 7997 // Strings are equal up to min length. Return the length difference. 7998 bind(LENGTH_DIFF_LABEL); 7999 pop(result); 8000 if (ae == StrIntrinsicNode::UU) { 8001 // Divide diff by 2 to get number of chars 8002 sarl(result, 1); 8003 } 8004 jmpb(DONE_LABEL); 8005 8006 #ifdef _LP64 8007 if (VM_Version::supports_avx512vlbw()) { 8008 8009 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8010 8011 kmovql(cnt1, k7); 8012 notq(cnt1); 8013 bsfq(cnt2, cnt1); 8014 if (ae != StrIntrinsicNode::LL) { 8015 // Divide diff by 2 to get number of chars 8016 sarl(cnt2, 1); 8017 } 8018 addq(result, cnt2); 8019 if (ae == StrIntrinsicNode::LL) { 8020 load_unsigned_byte(cnt1, Address(str2, result)); 8021 load_unsigned_byte(result, Address(str1, result)); 8022 } else if (ae == StrIntrinsicNode::UU) { 8023 load_unsigned_short(cnt1, Address(str2, result, scale)); 8024 load_unsigned_short(result, Address(str1, result, scale)); 8025 } else { 8026 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8027 load_unsigned_byte(result, Address(str1, result, scale1)); 8028 } 8029 subl(result, cnt1); 8030 jmpb(POP_LABEL); 8031 }//if (VM_Version::supports_avx512vlbw()) 8032 #endif // _LP64 8033 8034 // Discard the stored length difference 8035 bind(POP_LABEL); 8036 pop(cnt1); 8037 8038 // That's it 8039 bind(DONE_LABEL); 8040 if(ae == StrIntrinsicNode::UL) { 8041 negl(result); 8042 } 8043 8044 } 8045 8046 // Search for Non-ASCII character (Negative byte value) in a byte array, 8047 // return true if it has any and false otherwise. 8048 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8049 // @HotSpotIntrinsicCandidate 8050 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8051 // for (int i = off; i < off + len; i++) { 8052 // if (ba[i] < 0) { 8053 // return true; 8054 // } 8055 // } 8056 // return false; 8057 // } 8058 void MacroAssembler::has_negatives(Register ary1, Register len, 8059 Register result, Register tmp1, 8060 XMMRegister vec1, XMMRegister vec2) { 8061 // rsi: byte array 8062 // rcx: len 8063 // rax: result 8064 ShortBranchVerifier sbv(this); 8065 assert_different_registers(ary1, len, result, tmp1); 8066 assert_different_registers(vec1, vec2); 8067 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8068 8069 // len == 0 8070 testl(len, len); 8071 jcc(Assembler::zero, FALSE_LABEL); 8072 8073 if ((UseAVX > 2) && // AVX512 8074 VM_Version::supports_avx512vlbw() && 8075 VM_Version::supports_bmi2()) { 8076 8077 set_vector_masking(); // opening of the stub context for programming mask registers 8078 8079 Label test_64_loop, test_tail; 8080 Register tmp3_aliased = len; 8081 8082 movl(tmp1, len); 8083 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8084 8085 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8086 andl(len, ~(64 - 1)); // vector count (in chars) 8087 jccb(Assembler::zero, test_tail); 8088 8089 lea(ary1, Address(ary1, len, Address::times_1)); 8090 negptr(len); 8091 8092 bind(test_64_loop); 8093 // Check whether our 64 elements of size byte contain negatives 8094 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8095 kortestql(k2, k2); 8096 jcc(Assembler::notZero, TRUE_LABEL); 8097 8098 addptr(len, 64); 8099 jccb(Assembler::notZero, test_64_loop); 8100 8101 8102 bind(test_tail); 8103 // bail out when there is nothing to be done 8104 testl(tmp1, -1); 8105 jcc(Assembler::zero, FALSE_LABEL); 8106 8107 // Save k1 8108 kmovql(k3, k1); 8109 8110 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8111 #ifdef _LP64 8112 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8113 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8114 notq(tmp3_aliased); 8115 kmovql(k1, tmp3_aliased); 8116 #else 8117 Label k_init; 8118 jmp(k_init); 8119 8120 // We could not read 64-bits from a general purpose register thus we move 8121 // data required to compose 64 1's to the instruction stream 8122 // We emit 64 byte wide series of elements from 0..63 which later on would 8123 // be used as a compare targets with tail count contained in tmp1 register. 8124 // Result would be a k1 register having tmp1 consecutive number or 1 8125 // counting from least significant bit. 8126 address tmp = pc(); 8127 emit_int64(0x0706050403020100); 8128 emit_int64(0x0F0E0D0C0B0A0908); 8129 emit_int64(0x1716151413121110); 8130 emit_int64(0x1F1E1D1C1B1A1918); 8131 emit_int64(0x2726252423222120); 8132 emit_int64(0x2F2E2D2C2B2A2928); 8133 emit_int64(0x3736353433323130); 8134 emit_int64(0x3F3E3D3C3B3A3938); 8135 8136 bind(k_init); 8137 lea(len, InternalAddress(tmp)); 8138 // create mask to test for negative byte inside a vector 8139 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8140 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8141 8142 #endif 8143 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8144 ktestq(k2, k1); 8145 // Restore k1 8146 kmovql(k1, k3); 8147 jcc(Assembler::notZero, TRUE_LABEL); 8148 8149 jmp(FALSE_LABEL); 8150 8151 clear_vector_masking(); // closing of the stub context for programming mask registers 8152 } else { 8153 movl(result, len); // copy 8154 8155 if (UseAVX == 2 && UseSSE >= 2) { 8156 // With AVX2, use 32-byte vector compare 8157 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8158 8159 // Compare 32-byte vectors 8160 andl(result, 0x0000001f); // tail count (in bytes) 8161 andl(len, 0xffffffe0); // vector count (in bytes) 8162 jccb(Assembler::zero, COMPARE_TAIL); 8163 8164 lea(ary1, Address(ary1, len, Address::times_1)); 8165 negptr(len); 8166 8167 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8168 movdl(vec2, tmp1); 8169 vpbroadcastd(vec2, vec2); 8170 8171 bind(COMPARE_WIDE_VECTORS); 8172 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8173 vptest(vec1, vec2); 8174 jccb(Assembler::notZero, TRUE_LABEL); 8175 addptr(len, 32); 8176 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8177 8178 testl(result, result); 8179 jccb(Assembler::zero, FALSE_LABEL); 8180 8181 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8182 vptest(vec1, vec2); 8183 jccb(Assembler::notZero, TRUE_LABEL); 8184 jmpb(FALSE_LABEL); 8185 8186 bind(COMPARE_TAIL); // len is zero 8187 movl(len, result); 8188 // Fallthru to tail compare 8189 } else if (UseSSE42Intrinsics) { 8190 // With SSE4.2, use double quad vector compare 8191 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8192 8193 // Compare 16-byte vectors 8194 andl(result, 0x0000000f); // tail count (in bytes) 8195 andl(len, 0xfffffff0); // vector count (in bytes) 8196 jccb(Assembler::zero, COMPARE_TAIL); 8197 8198 lea(ary1, Address(ary1, len, Address::times_1)); 8199 negptr(len); 8200 8201 movl(tmp1, 0x80808080); 8202 movdl(vec2, tmp1); 8203 pshufd(vec2, vec2, 0); 8204 8205 bind(COMPARE_WIDE_VECTORS); 8206 movdqu(vec1, Address(ary1, len, Address::times_1)); 8207 ptest(vec1, vec2); 8208 jccb(Assembler::notZero, TRUE_LABEL); 8209 addptr(len, 16); 8210 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8211 8212 testl(result, result); 8213 jccb(Assembler::zero, FALSE_LABEL); 8214 8215 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8216 ptest(vec1, vec2); 8217 jccb(Assembler::notZero, TRUE_LABEL); 8218 jmpb(FALSE_LABEL); 8219 8220 bind(COMPARE_TAIL); // len is zero 8221 movl(len, result); 8222 // Fallthru to tail compare 8223 } 8224 } 8225 // Compare 4-byte vectors 8226 andl(len, 0xfffffffc); // vector count (in bytes) 8227 jccb(Assembler::zero, COMPARE_CHAR); 8228 8229 lea(ary1, Address(ary1, len, Address::times_1)); 8230 negptr(len); 8231 8232 bind(COMPARE_VECTORS); 8233 movl(tmp1, Address(ary1, len, Address::times_1)); 8234 andl(tmp1, 0x80808080); 8235 jccb(Assembler::notZero, TRUE_LABEL); 8236 addptr(len, 4); 8237 jcc(Assembler::notZero, COMPARE_VECTORS); 8238 8239 // Compare trailing char (final 2 bytes), if any 8240 bind(COMPARE_CHAR); 8241 testl(result, 0x2); // tail char 8242 jccb(Assembler::zero, COMPARE_BYTE); 8243 load_unsigned_short(tmp1, Address(ary1, 0)); 8244 andl(tmp1, 0x00008080); 8245 jccb(Assembler::notZero, TRUE_LABEL); 8246 subptr(result, 2); 8247 lea(ary1, Address(ary1, 2)); 8248 8249 bind(COMPARE_BYTE); 8250 testl(result, 0x1); // tail byte 8251 jccb(Assembler::zero, FALSE_LABEL); 8252 load_unsigned_byte(tmp1, Address(ary1, 0)); 8253 andl(tmp1, 0x00000080); 8254 jccb(Assembler::notEqual, TRUE_LABEL); 8255 jmpb(FALSE_LABEL); 8256 8257 bind(TRUE_LABEL); 8258 movl(result, 1); // return true 8259 jmpb(DONE); 8260 8261 bind(FALSE_LABEL); 8262 xorl(result, result); // return false 8263 8264 // That's it 8265 bind(DONE); 8266 if (UseAVX >= 2 && UseSSE >= 2) { 8267 // clean upper bits of YMM registers 8268 vpxor(vec1, vec1); 8269 vpxor(vec2, vec2); 8270 } 8271 } 8272 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8273 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8274 Register limit, Register result, Register chr, 8275 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8276 ShortBranchVerifier sbv(this); 8277 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8278 8279 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8280 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8281 8282 if (is_array_equ) { 8283 // Check the input args 8284 cmpptr(ary1, ary2); 8285 jcc(Assembler::equal, TRUE_LABEL); 8286 8287 // Need additional checks for arrays_equals. 8288 testptr(ary1, ary1); 8289 jcc(Assembler::zero, FALSE_LABEL); 8290 testptr(ary2, ary2); 8291 jcc(Assembler::zero, FALSE_LABEL); 8292 8293 // Check the lengths 8294 movl(limit, Address(ary1, length_offset)); 8295 cmpl(limit, Address(ary2, length_offset)); 8296 jcc(Assembler::notEqual, FALSE_LABEL); 8297 } 8298 8299 // count == 0 8300 testl(limit, limit); 8301 jcc(Assembler::zero, TRUE_LABEL); 8302 8303 if (is_array_equ) { 8304 // Load array address 8305 lea(ary1, Address(ary1, base_offset)); 8306 lea(ary2, Address(ary2, base_offset)); 8307 } 8308 8309 if (is_array_equ && is_char) { 8310 // arrays_equals when used for char[]. 8311 shll(limit, 1); // byte count != 0 8312 } 8313 movl(result, limit); // copy 8314 8315 if (UseAVX >= 2) { 8316 // With AVX2, use 32-byte vector compare 8317 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8318 8319 // Compare 32-byte vectors 8320 andl(result, 0x0000001f); // tail count (in bytes) 8321 andl(limit, 0xffffffe0); // vector count (in bytes) 8322 jcc(Assembler::zero, COMPARE_TAIL); 8323 8324 lea(ary1, Address(ary1, limit, Address::times_1)); 8325 lea(ary2, Address(ary2, limit, Address::times_1)); 8326 negptr(limit); 8327 8328 bind(COMPARE_WIDE_VECTORS); 8329 8330 #ifdef _LP64 8331 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8332 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8333 8334 cmpl(limit, -64); 8335 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8336 8337 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8338 8339 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8340 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8341 kortestql(k7, k7); 8342 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8343 addptr(limit, 64); // update since we already compared at this addr 8344 cmpl(limit, -64); 8345 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8346 8347 // At this point we may still need to compare -limit+result bytes. 8348 // We could execute the next two instruction and just continue via non-wide path: 8349 // cmpl(limit, 0); 8350 // jcc(Assembler::equal, COMPARE_TAIL); // true 8351 // But since we stopped at the points ary{1,2}+limit which are 8352 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8353 // (|limit| <= 32 and result < 32), 8354 // we may just compare the last 64 bytes. 8355 // 8356 addptr(result, -64); // it is safe, bc we just came from this area 8357 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8358 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8359 kortestql(k7, k7); 8360 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8361 8362 jmp(TRUE_LABEL); 8363 8364 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8365 8366 }//if (VM_Version::supports_avx512vlbw()) 8367 #endif //_LP64 8368 8369 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8370 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8371 vpxor(vec1, vec2); 8372 8373 vptest(vec1, vec1); 8374 jcc(Assembler::notZero, FALSE_LABEL); 8375 addptr(limit, 32); 8376 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8377 8378 testl(result, result); 8379 jcc(Assembler::zero, TRUE_LABEL); 8380 8381 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8382 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8383 vpxor(vec1, vec2); 8384 8385 vptest(vec1, vec1); 8386 jccb(Assembler::notZero, FALSE_LABEL); 8387 jmpb(TRUE_LABEL); 8388 8389 bind(COMPARE_TAIL); // limit is zero 8390 movl(limit, result); 8391 // Fallthru to tail compare 8392 } else if (UseSSE42Intrinsics) { 8393 // With SSE4.2, use double quad vector compare 8394 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8395 8396 // Compare 16-byte vectors 8397 andl(result, 0x0000000f); // tail count (in bytes) 8398 andl(limit, 0xfffffff0); // vector count (in bytes) 8399 jcc(Assembler::zero, COMPARE_TAIL); 8400 8401 lea(ary1, Address(ary1, limit, Address::times_1)); 8402 lea(ary2, Address(ary2, limit, Address::times_1)); 8403 negptr(limit); 8404 8405 bind(COMPARE_WIDE_VECTORS); 8406 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8407 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8408 pxor(vec1, vec2); 8409 8410 ptest(vec1, vec1); 8411 jcc(Assembler::notZero, FALSE_LABEL); 8412 addptr(limit, 16); 8413 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8414 8415 testl(result, result); 8416 jcc(Assembler::zero, TRUE_LABEL); 8417 8418 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8419 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8420 pxor(vec1, vec2); 8421 8422 ptest(vec1, vec1); 8423 jccb(Assembler::notZero, FALSE_LABEL); 8424 jmpb(TRUE_LABEL); 8425 8426 bind(COMPARE_TAIL); // limit is zero 8427 movl(limit, result); 8428 // Fallthru to tail compare 8429 } 8430 8431 // Compare 4-byte vectors 8432 andl(limit, 0xfffffffc); // vector count (in bytes) 8433 jccb(Assembler::zero, COMPARE_CHAR); 8434 8435 lea(ary1, Address(ary1, limit, Address::times_1)); 8436 lea(ary2, Address(ary2, limit, Address::times_1)); 8437 negptr(limit); 8438 8439 bind(COMPARE_VECTORS); 8440 movl(chr, Address(ary1, limit, Address::times_1)); 8441 cmpl(chr, Address(ary2, limit, Address::times_1)); 8442 jccb(Assembler::notEqual, FALSE_LABEL); 8443 addptr(limit, 4); 8444 jcc(Assembler::notZero, COMPARE_VECTORS); 8445 8446 // Compare trailing char (final 2 bytes), if any 8447 bind(COMPARE_CHAR); 8448 testl(result, 0x2); // tail char 8449 jccb(Assembler::zero, COMPARE_BYTE); 8450 load_unsigned_short(chr, Address(ary1, 0)); 8451 load_unsigned_short(limit, Address(ary2, 0)); 8452 cmpl(chr, limit); 8453 jccb(Assembler::notEqual, FALSE_LABEL); 8454 8455 if (is_array_equ && is_char) { 8456 bind(COMPARE_BYTE); 8457 } else { 8458 lea(ary1, Address(ary1, 2)); 8459 lea(ary2, Address(ary2, 2)); 8460 8461 bind(COMPARE_BYTE); 8462 testl(result, 0x1); // tail byte 8463 jccb(Assembler::zero, TRUE_LABEL); 8464 load_unsigned_byte(chr, Address(ary1, 0)); 8465 load_unsigned_byte(limit, Address(ary2, 0)); 8466 cmpl(chr, limit); 8467 jccb(Assembler::notEqual, FALSE_LABEL); 8468 } 8469 bind(TRUE_LABEL); 8470 movl(result, 1); // return true 8471 jmpb(DONE); 8472 8473 bind(FALSE_LABEL); 8474 xorl(result, result); // return false 8475 8476 // That's it 8477 bind(DONE); 8478 if (UseAVX >= 2) { 8479 // clean upper bits of YMM registers 8480 vpxor(vec1, vec1); 8481 vpxor(vec2, vec2); 8482 } 8483 } 8484 8485 #endif 8486 8487 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8488 Register to, Register value, Register count, 8489 Register rtmp, XMMRegister xtmp) { 8490 ShortBranchVerifier sbv(this); 8491 assert_different_registers(to, value, count, rtmp); 8492 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8493 Label L_fill_2_bytes, L_fill_4_bytes; 8494 8495 int shift = -1; 8496 switch (t) { 8497 case T_BYTE: 8498 shift = 2; 8499 break; 8500 case T_SHORT: 8501 shift = 1; 8502 break; 8503 case T_INT: 8504 shift = 0; 8505 break; 8506 default: ShouldNotReachHere(); 8507 } 8508 8509 if (t == T_BYTE) { 8510 andl(value, 0xff); 8511 movl(rtmp, value); 8512 shll(rtmp, 8); 8513 orl(value, rtmp); 8514 } 8515 if (t == T_SHORT) { 8516 andl(value, 0xffff); 8517 } 8518 if (t == T_BYTE || t == T_SHORT) { 8519 movl(rtmp, value); 8520 shll(rtmp, 16); 8521 orl(value, rtmp); 8522 } 8523 8524 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8525 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8526 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8527 // align source address at 4 bytes address boundary 8528 if (t == T_BYTE) { 8529 // One byte misalignment happens only for byte arrays 8530 testptr(to, 1); 8531 jccb(Assembler::zero, L_skip_align1); 8532 movb(Address(to, 0), value); 8533 increment(to); 8534 decrement(count); 8535 BIND(L_skip_align1); 8536 } 8537 // Two bytes misalignment happens only for byte and short (char) arrays 8538 testptr(to, 2); 8539 jccb(Assembler::zero, L_skip_align2); 8540 movw(Address(to, 0), value); 8541 addptr(to, 2); 8542 subl(count, 1<<(shift-1)); 8543 BIND(L_skip_align2); 8544 } 8545 if (UseSSE < 2) { 8546 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8547 // Fill 32-byte chunks 8548 subl(count, 8 << shift); 8549 jcc(Assembler::less, L_check_fill_8_bytes); 8550 align(16); 8551 8552 BIND(L_fill_32_bytes_loop); 8553 8554 for (int i = 0; i < 32; i += 4) { 8555 movl(Address(to, i), value); 8556 } 8557 8558 addptr(to, 32); 8559 subl(count, 8 << shift); 8560 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8561 BIND(L_check_fill_8_bytes); 8562 addl(count, 8 << shift); 8563 jccb(Assembler::zero, L_exit); 8564 jmpb(L_fill_8_bytes); 8565 8566 // 8567 // length is too short, just fill qwords 8568 // 8569 BIND(L_fill_8_bytes_loop); 8570 movl(Address(to, 0), value); 8571 movl(Address(to, 4), value); 8572 addptr(to, 8); 8573 BIND(L_fill_8_bytes); 8574 subl(count, 1 << (shift + 1)); 8575 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8576 // fall through to fill 4 bytes 8577 } else { 8578 Label L_fill_32_bytes; 8579 if (!UseUnalignedLoadStores) { 8580 // align to 8 bytes, we know we are 4 byte aligned to start 8581 testptr(to, 4); 8582 jccb(Assembler::zero, L_fill_32_bytes); 8583 movl(Address(to, 0), value); 8584 addptr(to, 4); 8585 subl(count, 1<<shift); 8586 } 8587 BIND(L_fill_32_bytes); 8588 { 8589 assert( UseSSE >= 2, "supported cpu only" ); 8590 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8591 if (UseAVX > 2) { 8592 movl(rtmp, 0xffff); 8593 kmovwl(k1, rtmp); 8594 } 8595 movdl(xtmp, value); 8596 if (UseAVX > 2 && UseUnalignedLoadStores) { 8597 // Fill 64-byte chunks 8598 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8599 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8600 8601 subl(count, 16 << shift); 8602 jcc(Assembler::less, L_check_fill_32_bytes); 8603 align(16); 8604 8605 BIND(L_fill_64_bytes_loop); 8606 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8607 addptr(to, 64); 8608 subl(count, 16 << shift); 8609 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8610 8611 BIND(L_check_fill_32_bytes); 8612 addl(count, 8 << shift); 8613 jccb(Assembler::less, L_check_fill_8_bytes); 8614 vmovdqu(Address(to, 0), xtmp); 8615 addptr(to, 32); 8616 subl(count, 8 << shift); 8617 8618 BIND(L_check_fill_8_bytes); 8619 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8620 // Fill 64-byte chunks 8621 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8622 vpbroadcastd(xtmp, xtmp); 8623 8624 subl(count, 16 << shift); 8625 jcc(Assembler::less, L_check_fill_32_bytes); 8626 align(16); 8627 8628 BIND(L_fill_64_bytes_loop); 8629 vmovdqu(Address(to, 0), xtmp); 8630 vmovdqu(Address(to, 32), xtmp); 8631 addptr(to, 64); 8632 subl(count, 16 << shift); 8633 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8634 8635 BIND(L_check_fill_32_bytes); 8636 addl(count, 8 << shift); 8637 jccb(Assembler::less, L_check_fill_8_bytes); 8638 vmovdqu(Address(to, 0), xtmp); 8639 addptr(to, 32); 8640 subl(count, 8 << shift); 8641 8642 BIND(L_check_fill_8_bytes); 8643 // clean upper bits of YMM registers 8644 movdl(xtmp, value); 8645 pshufd(xtmp, xtmp, 0); 8646 } else { 8647 // Fill 32-byte chunks 8648 pshufd(xtmp, xtmp, 0); 8649 8650 subl(count, 8 << shift); 8651 jcc(Assembler::less, L_check_fill_8_bytes); 8652 align(16); 8653 8654 BIND(L_fill_32_bytes_loop); 8655 8656 if (UseUnalignedLoadStores) { 8657 movdqu(Address(to, 0), xtmp); 8658 movdqu(Address(to, 16), xtmp); 8659 } else { 8660 movq(Address(to, 0), xtmp); 8661 movq(Address(to, 8), xtmp); 8662 movq(Address(to, 16), xtmp); 8663 movq(Address(to, 24), xtmp); 8664 } 8665 8666 addptr(to, 32); 8667 subl(count, 8 << shift); 8668 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8669 8670 BIND(L_check_fill_8_bytes); 8671 } 8672 addl(count, 8 << shift); 8673 jccb(Assembler::zero, L_exit); 8674 jmpb(L_fill_8_bytes); 8675 8676 // 8677 // length is too short, just fill qwords 8678 // 8679 BIND(L_fill_8_bytes_loop); 8680 movq(Address(to, 0), xtmp); 8681 addptr(to, 8); 8682 BIND(L_fill_8_bytes); 8683 subl(count, 1 << (shift + 1)); 8684 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8685 } 8686 } 8687 // fill trailing 4 bytes 8688 BIND(L_fill_4_bytes); 8689 testl(count, 1<<shift); 8690 jccb(Assembler::zero, L_fill_2_bytes); 8691 movl(Address(to, 0), value); 8692 if (t == T_BYTE || t == T_SHORT) { 8693 addptr(to, 4); 8694 BIND(L_fill_2_bytes); 8695 // fill trailing 2 bytes 8696 testl(count, 1<<(shift-1)); 8697 jccb(Assembler::zero, L_fill_byte); 8698 movw(Address(to, 0), value); 8699 if (t == T_BYTE) { 8700 addptr(to, 2); 8701 BIND(L_fill_byte); 8702 // fill trailing byte 8703 testl(count, 1); 8704 jccb(Assembler::zero, L_exit); 8705 movb(Address(to, 0), value); 8706 } else { 8707 BIND(L_fill_byte); 8708 } 8709 } else { 8710 BIND(L_fill_2_bytes); 8711 } 8712 BIND(L_exit); 8713 } 8714 8715 // encode char[] to byte[] in ISO_8859_1 8716 //@HotSpotIntrinsicCandidate 8717 //private static int implEncodeISOArray(byte[] sa, int sp, 8718 //byte[] da, int dp, int len) { 8719 // int i = 0; 8720 // for (; i < len; i++) { 8721 // char c = StringUTF16.getChar(sa, sp++); 8722 // if (c > '\u00FF') 8723 // break; 8724 // da[dp++] = (byte)c; 8725 // } 8726 // return i; 8727 //} 8728 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8729 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8730 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8731 Register tmp5, Register result) { 8732 8733 // rsi: src 8734 // rdi: dst 8735 // rdx: len 8736 // rcx: tmp5 8737 // rax: result 8738 ShortBranchVerifier sbv(this); 8739 assert_different_registers(src, dst, len, tmp5, result); 8740 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8741 8742 // set result 8743 xorl(result, result); 8744 // check for zero length 8745 testl(len, len); 8746 jcc(Assembler::zero, L_done); 8747 8748 movl(result, len); 8749 8750 // Setup pointers 8751 lea(src, Address(src, len, Address::times_2)); // char[] 8752 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8753 negptr(len); 8754 8755 if (UseSSE42Intrinsics || UseAVX >= 2) { 8756 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8757 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8758 8759 if (UseAVX >= 2) { 8760 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8761 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8762 movdl(tmp1Reg, tmp5); 8763 vpbroadcastd(tmp1Reg, tmp1Reg); 8764 jmp(L_chars_32_check); 8765 8766 bind(L_copy_32_chars); 8767 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8768 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8769 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8770 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8771 jccb(Assembler::notZero, L_copy_32_chars_exit); 8772 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8773 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8774 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8775 8776 bind(L_chars_32_check); 8777 addptr(len, 32); 8778 jcc(Assembler::lessEqual, L_copy_32_chars); 8779 8780 bind(L_copy_32_chars_exit); 8781 subptr(len, 16); 8782 jccb(Assembler::greater, L_copy_16_chars_exit); 8783 8784 } else if (UseSSE42Intrinsics) { 8785 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8786 movdl(tmp1Reg, tmp5); 8787 pshufd(tmp1Reg, tmp1Reg, 0); 8788 jmpb(L_chars_16_check); 8789 } 8790 8791 bind(L_copy_16_chars); 8792 if (UseAVX >= 2) { 8793 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8794 vptest(tmp2Reg, tmp1Reg); 8795 jcc(Assembler::notZero, L_copy_16_chars_exit); 8796 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8797 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8798 } else { 8799 if (UseAVX > 0) { 8800 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8801 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8802 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8803 } else { 8804 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8805 por(tmp2Reg, tmp3Reg); 8806 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8807 por(tmp2Reg, tmp4Reg); 8808 } 8809 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8810 jccb(Assembler::notZero, L_copy_16_chars_exit); 8811 packuswb(tmp3Reg, tmp4Reg); 8812 } 8813 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8814 8815 bind(L_chars_16_check); 8816 addptr(len, 16); 8817 jcc(Assembler::lessEqual, L_copy_16_chars); 8818 8819 bind(L_copy_16_chars_exit); 8820 if (UseAVX >= 2) { 8821 // clean upper bits of YMM registers 8822 vpxor(tmp2Reg, tmp2Reg); 8823 vpxor(tmp3Reg, tmp3Reg); 8824 vpxor(tmp4Reg, tmp4Reg); 8825 movdl(tmp1Reg, tmp5); 8826 pshufd(tmp1Reg, tmp1Reg, 0); 8827 } 8828 subptr(len, 8); 8829 jccb(Assembler::greater, L_copy_8_chars_exit); 8830 8831 bind(L_copy_8_chars); 8832 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8833 ptest(tmp3Reg, tmp1Reg); 8834 jccb(Assembler::notZero, L_copy_8_chars_exit); 8835 packuswb(tmp3Reg, tmp1Reg); 8836 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8837 addptr(len, 8); 8838 jccb(Assembler::lessEqual, L_copy_8_chars); 8839 8840 bind(L_copy_8_chars_exit); 8841 subptr(len, 8); 8842 jccb(Assembler::zero, L_done); 8843 } 8844 8845 bind(L_copy_1_char); 8846 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8847 testl(tmp5, 0xff00); // check if Unicode char 8848 jccb(Assembler::notZero, L_copy_1_char_exit); 8849 movb(Address(dst, len, Address::times_1, 0), tmp5); 8850 addptr(len, 1); 8851 jccb(Assembler::less, L_copy_1_char); 8852 8853 bind(L_copy_1_char_exit); 8854 addptr(result, len); // len is negative count of not processed elements 8855 8856 bind(L_done); 8857 } 8858 8859 #ifdef _LP64 8860 /** 8861 * Helper for multiply_to_len(). 8862 */ 8863 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8864 addq(dest_lo, src1); 8865 adcq(dest_hi, 0); 8866 addq(dest_lo, src2); 8867 adcq(dest_hi, 0); 8868 } 8869 8870 /** 8871 * Multiply 64 bit by 64 bit first loop. 8872 */ 8873 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8874 Register y, Register y_idx, Register z, 8875 Register carry, Register product, 8876 Register idx, Register kdx) { 8877 // 8878 // jlong carry, x[], y[], z[]; 8879 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8880 // huge_128 product = y[idx] * x[xstart] + carry; 8881 // z[kdx] = (jlong)product; 8882 // carry = (jlong)(product >>> 64); 8883 // } 8884 // z[xstart] = carry; 8885 // 8886 8887 Label L_first_loop, L_first_loop_exit; 8888 Label L_one_x, L_one_y, L_multiply; 8889 8890 decrementl(xstart); 8891 jcc(Assembler::negative, L_one_x); 8892 8893 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8894 rorq(x_xstart, 32); // convert big-endian to little-endian 8895 8896 bind(L_first_loop); 8897 decrementl(idx); 8898 jcc(Assembler::negative, L_first_loop_exit); 8899 decrementl(idx); 8900 jcc(Assembler::negative, L_one_y); 8901 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8902 rorq(y_idx, 32); // convert big-endian to little-endian 8903 bind(L_multiply); 8904 movq(product, x_xstart); 8905 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 8906 addq(product, carry); 8907 adcq(rdx, 0); 8908 subl(kdx, 2); 8909 movl(Address(z, kdx, Address::times_4, 4), product); 8910 shrq(product, 32); 8911 movl(Address(z, kdx, Address::times_4, 0), product); 8912 movq(carry, rdx); 8913 jmp(L_first_loop); 8914 8915 bind(L_one_y); 8916 movl(y_idx, Address(y, 0)); 8917 jmp(L_multiply); 8918 8919 bind(L_one_x); 8920 movl(x_xstart, Address(x, 0)); 8921 jmp(L_first_loop); 8922 8923 bind(L_first_loop_exit); 8924 } 8925 8926 /** 8927 * Multiply 64 bit by 64 bit and add 128 bit. 8928 */ 8929 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 8930 Register yz_idx, Register idx, 8931 Register carry, Register product, int offset) { 8932 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 8933 // z[kdx] = (jlong)product; 8934 8935 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 8936 rorq(yz_idx, 32); // convert big-endian to little-endian 8937 movq(product, x_xstart); 8938 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 8939 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 8940 rorq(yz_idx, 32); // convert big-endian to little-endian 8941 8942 add2_with_carry(rdx, product, carry, yz_idx); 8943 8944 movl(Address(z, idx, Address::times_4, offset+4), product); 8945 shrq(product, 32); 8946 movl(Address(z, idx, Address::times_4, offset), product); 8947 8948 } 8949 8950 /** 8951 * Multiply 128 bit by 128 bit. Unrolled inner loop. 8952 */ 8953 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 8954 Register yz_idx, Register idx, Register jdx, 8955 Register carry, Register product, 8956 Register carry2) { 8957 // jlong carry, x[], y[], z[]; 8958 // int kdx = ystart+1; 8959 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 8960 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 8961 // z[kdx+idx+1] = (jlong)product; 8962 // jlong carry2 = (jlong)(product >>> 64); 8963 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 8964 // z[kdx+idx] = (jlong)product; 8965 // carry = (jlong)(product >>> 64); 8966 // } 8967 // idx += 2; 8968 // if (idx > 0) { 8969 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 8970 // z[kdx+idx] = (jlong)product; 8971 // carry = (jlong)(product >>> 64); 8972 // } 8973 // 8974 8975 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 8976 8977 movl(jdx, idx); 8978 andl(jdx, 0xFFFFFFFC); 8979 shrl(jdx, 2); 8980 8981 bind(L_third_loop); 8982 subl(jdx, 1); 8983 jcc(Assembler::negative, L_third_loop_exit); 8984 subl(idx, 4); 8985 8986 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 8987 movq(carry2, rdx); 8988 8989 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 8990 movq(carry, rdx); 8991 jmp(L_third_loop); 8992 8993 bind (L_third_loop_exit); 8994 8995 andl (idx, 0x3); 8996 jcc(Assembler::zero, L_post_third_loop_done); 8997 8998 Label L_check_1; 8999 subl(idx, 2); 9000 jcc(Assembler::negative, L_check_1); 9001 9002 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9003 movq(carry, rdx); 9004 9005 bind (L_check_1); 9006 addl (idx, 0x2); 9007 andl (idx, 0x1); 9008 subl(idx, 1); 9009 jcc(Assembler::negative, L_post_third_loop_done); 9010 9011 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9012 movq(product, x_xstart); 9013 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9014 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9015 9016 add2_with_carry(rdx, product, yz_idx, carry); 9017 9018 movl(Address(z, idx, Address::times_4, 0), product); 9019 shrq(product, 32); 9020 9021 shlq(rdx, 32); 9022 orq(product, rdx); 9023 movq(carry, product); 9024 9025 bind(L_post_third_loop_done); 9026 } 9027 9028 /** 9029 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9030 * 9031 */ 9032 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9033 Register carry, Register carry2, 9034 Register idx, Register jdx, 9035 Register yz_idx1, Register yz_idx2, 9036 Register tmp, Register tmp3, Register tmp4) { 9037 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9038 9039 // jlong carry, x[], y[], z[]; 9040 // int kdx = ystart+1; 9041 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9042 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9043 // jlong carry2 = (jlong)(tmp3 >>> 64); 9044 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9045 // carry = (jlong)(tmp4 >>> 64); 9046 // z[kdx+idx+1] = (jlong)tmp3; 9047 // z[kdx+idx] = (jlong)tmp4; 9048 // } 9049 // idx += 2; 9050 // if (idx > 0) { 9051 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9052 // z[kdx+idx] = (jlong)yz_idx1; 9053 // carry = (jlong)(yz_idx1 >>> 64); 9054 // } 9055 // 9056 9057 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9058 9059 movl(jdx, idx); 9060 andl(jdx, 0xFFFFFFFC); 9061 shrl(jdx, 2); 9062 9063 bind(L_third_loop); 9064 subl(jdx, 1); 9065 jcc(Assembler::negative, L_third_loop_exit); 9066 subl(idx, 4); 9067 9068 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9069 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9070 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9071 rorxq(yz_idx2, yz_idx2, 32); 9072 9073 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9074 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9075 9076 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9077 rorxq(yz_idx1, yz_idx1, 32); 9078 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9079 rorxq(yz_idx2, yz_idx2, 32); 9080 9081 if (VM_Version::supports_adx()) { 9082 adcxq(tmp3, carry); 9083 adoxq(tmp3, yz_idx1); 9084 9085 adcxq(tmp4, tmp); 9086 adoxq(tmp4, yz_idx2); 9087 9088 movl(carry, 0); // does not affect flags 9089 adcxq(carry2, carry); 9090 adoxq(carry2, carry); 9091 } else { 9092 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9093 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9094 } 9095 movq(carry, carry2); 9096 9097 movl(Address(z, idx, Address::times_4, 12), tmp3); 9098 shrq(tmp3, 32); 9099 movl(Address(z, idx, Address::times_4, 8), tmp3); 9100 9101 movl(Address(z, idx, Address::times_4, 4), tmp4); 9102 shrq(tmp4, 32); 9103 movl(Address(z, idx, Address::times_4, 0), tmp4); 9104 9105 jmp(L_third_loop); 9106 9107 bind (L_third_loop_exit); 9108 9109 andl (idx, 0x3); 9110 jcc(Assembler::zero, L_post_third_loop_done); 9111 9112 Label L_check_1; 9113 subl(idx, 2); 9114 jcc(Assembler::negative, L_check_1); 9115 9116 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9117 rorxq(yz_idx1, yz_idx1, 32); 9118 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9119 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9120 rorxq(yz_idx2, yz_idx2, 32); 9121 9122 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9123 9124 movl(Address(z, idx, Address::times_4, 4), tmp3); 9125 shrq(tmp3, 32); 9126 movl(Address(z, idx, Address::times_4, 0), tmp3); 9127 movq(carry, tmp4); 9128 9129 bind (L_check_1); 9130 addl (idx, 0x2); 9131 andl (idx, 0x1); 9132 subl(idx, 1); 9133 jcc(Assembler::negative, L_post_third_loop_done); 9134 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9135 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9136 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9137 9138 add2_with_carry(carry2, tmp3, tmp4, carry); 9139 9140 movl(Address(z, idx, Address::times_4, 0), tmp3); 9141 shrq(tmp3, 32); 9142 9143 shlq(carry2, 32); 9144 orq(tmp3, carry2); 9145 movq(carry, tmp3); 9146 9147 bind(L_post_third_loop_done); 9148 } 9149 9150 /** 9151 * Code for BigInteger::multiplyToLen() instrinsic. 9152 * 9153 * rdi: x 9154 * rax: xlen 9155 * rsi: y 9156 * rcx: ylen 9157 * r8: z 9158 * r11: zlen 9159 * r12: tmp1 9160 * r13: tmp2 9161 * r14: tmp3 9162 * r15: tmp4 9163 * rbx: tmp5 9164 * 9165 */ 9166 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9167 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9168 ShortBranchVerifier sbv(this); 9169 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9170 9171 push(tmp1); 9172 push(tmp2); 9173 push(tmp3); 9174 push(tmp4); 9175 push(tmp5); 9176 9177 push(xlen); 9178 push(zlen); 9179 9180 const Register idx = tmp1; 9181 const Register kdx = tmp2; 9182 const Register xstart = tmp3; 9183 9184 const Register y_idx = tmp4; 9185 const Register carry = tmp5; 9186 const Register product = xlen; 9187 const Register x_xstart = zlen; // reuse register 9188 9189 // First Loop. 9190 // 9191 // final static long LONG_MASK = 0xffffffffL; 9192 // int xstart = xlen - 1; 9193 // int ystart = ylen - 1; 9194 // long carry = 0; 9195 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9196 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9197 // z[kdx] = (int)product; 9198 // carry = product >>> 32; 9199 // } 9200 // z[xstart] = (int)carry; 9201 // 9202 9203 movl(idx, ylen); // idx = ylen; 9204 movl(kdx, zlen); // kdx = xlen+ylen; 9205 xorq(carry, carry); // carry = 0; 9206 9207 Label L_done; 9208 9209 movl(xstart, xlen); 9210 decrementl(xstart); 9211 jcc(Assembler::negative, L_done); 9212 9213 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9214 9215 Label L_second_loop; 9216 testl(kdx, kdx); 9217 jcc(Assembler::zero, L_second_loop); 9218 9219 Label L_carry; 9220 subl(kdx, 1); 9221 jcc(Assembler::zero, L_carry); 9222 9223 movl(Address(z, kdx, Address::times_4, 0), carry); 9224 shrq(carry, 32); 9225 subl(kdx, 1); 9226 9227 bind(L_carry); 9228 movl(Address(z, kdx, Address::times_4, 0), carry); 9229 9230 // Second and third (nested) loops. 9231 // 9232 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9233 // carry = 0; 9234 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9235 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9236 // (z[k] & LONG_MASK) + carry; 9237 // z[k] = (int)product; 9238 // carry = product >>> 32; 9239 // } 9240 // z[i] = (int)carry; 9241 // } 9242 // 9243 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9244 9245 const Register jdx = tmp1; 9246 9247 bind(L_second_loop); 9248 xorl(carry, carry); // carry = 0; 9249 movl(jdx, ylen); // j = ystart+1 9250 9251 subl(xstart, 1); // i = xstart-1; 9252 jcc(Assembler::negative, L_done); 9253 9254 push (z); 9255 9256 Label L_last_x; 9257 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9258 subl(xstart, 1); // i = xstart-1; 9259 jcc(Assembler::negative, L_last_x); 9260 9261 if (UseBMI2Instructions) { 9262 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9263 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9264 } else { 9265 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9266 rorq(x_xstart, 32); // convert big-endian to little-endian 9267 } 9268 9269 Label L_third_loop_prologue; 9270 bind(L_third_loop_prologue); 9271 9272 push (x); 9273 push (xstart); 9274 push (ylen); 9275 9276 9277 if (UseBMI2Instructions) { 9278 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9279 } else { // !UseBMI2Instructions 9280 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9281 } 9282 9283 pop(ylen); 9284 pop(xlen); 9285 pop(x); 9286 pop(z); 9287 9288 movl(tmp3, xlen); 9289 addl(tmp3, 1); 9290 movl(Address(z, tmp3, Address::times_4, 0), carry); 9291 subl(tmp3, 1); 9292 jccb(Assembler::negative, L_done); 9293 9294 shrq(carry, 32); 9295 movl(Address(z, tmp3, Address::times_4, 0), carry); 9296 jmp(L_second_loop); 9297 9298 // Next infrequent code is moved outside loops. 9299 bind(L_last_x); 9300 if (UseBMI2Instructions) { 9301 movl(rdx, Address(x, 0)); 9302 } else { 9303 movl(x_xstart, Address(x, 0)); 9304 } 9305 jmp(L_third_loop_prologue); 9306 9307 bind(L_done); 9308 9309 pop(zlen); 9310 pop(xlen); 9311 9312 pop(tmp5); 9313 pop(tmp4); 9314 pop(tmp3); 9315 pop(tmp2); 9316 pop(tmp1); 9317 } 9318 9319 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9320 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9321 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9322 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9323 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9324 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9325 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9326 Label SAME_TILL_END, DONE; 9327 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9328 9329 //scale is in rcx in both Win64 and Unix 9330 ShortBranchVerifier sbv(this); 9331 9332 shlq(length); 9333 xorq(result, result); 9334 9335 if ((UseAVX > 2) && 9336 VM_Version::supports_avx512vlbw()) { 9337 set_vector_masking(); // opening of the stub context for programming mask registers 9338 cmpq(length, 64); 9339 jcc(Assembler::less, VECTOR32_TAIL); 9340 movq(tmp1, length); 9341 andq(tmp1, 0x3F); // tail count 9342 andq(length, ~(0x3F)); //vector count 9343 9344 bind(VECTOR64_LOOP); 9345 // AVX512 code to compare 64 byte vectors. 9346 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9347 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9348 kortestql(k7, k7); 9349 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9350 addq(result, 64); 9351 subq(length, 64); 9352 jccb(Assembler::notZero, VECTOR64_LOOP); 9353 9354 //bind(VECTOR64_TAIL); 9355 testq(tmp1, tmp1); 9356 jcc(Assembler::zero, SAME_TILL_END); 9357 9358 bind(VECTOR64_TAIL); 9359 // AVX512 code to compare upto 63 byte vectors. 9360 // Save k1 9361 kmovql(k3, k1); 9362 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9363 shlxq(tmp2, tmp2, tmp1); 9364 notq(tmp2); 9365 kmovql(k1, tmp2); 9366 9367 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9368 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9369 9370 ktestql(k7, k1); 9371 // Restore k1 9372 kmovql(k1, k3); 9373 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9374 9375 bind(VECTOR64_NOT_EQUAL); 9376 kmovql(tmp1, k7); 9377 notq(tmp1); 9378 tzcntq(tmp1, tmp1); 9379 addq(result, tmp1); 9380 shrq(result); 9381 jmp(DONE); 9382 bind(VECTOR32_TAIL); 9383 clear_vector_masking(); // closing of the stub context for programming mask registers 9384 } 9385 9386 cmpq(length, 8); 9387 jcc(Assembler::equal, VECTOR8_LOOP); 9388 jcc(Assembler::less, VECTOR4_TAIL); 9389 9390 if (UseAVX >= 2) { 9391 9392 cmpq(length, 16); 9393 jcc(Assembler::equal, VECTOR16_LOOP); 9394 jcc(Assembler::less, VECTOR8_LOOP); 9395 9396 cmpq(length, 32); 9397 jccb(Assembler::less, VECTOR16_TAIL); 9398 9399 subq(length, 32); 9400 bind(VECTOR32_LOOP); 9401 vmovdqu(rymm0, Address(obja, result)); 9402 vmovdqu(rymm1, Address(objb, result)); 9403 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9404 vptest(rymm2, rymm2); 9405 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9406 addq(result, 32); 9407 subq(length, 32); 9408 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9409 addq(length, 32); 9410 jcc(Assembler::equal, SAME_TILL_END); 9411 //falling through if less than 32 bytes left //close the branch here. 9412 9413 bind(VECTOR16_TAIL); 9414 cmpq(length, 16); 9415 jccb(Assembler::less, VECTOR8_TAIL); 9416 bind(VECTOR16_LOOP); 9417 movdqu(rymm0, Address(obja, result)); 9418 movdqu(rymm1, Address(objb, result)); 9419 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9420 ptest(rymm2, rymm2); 9421 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9422 addq(result, 16); 9423 subq(length, 16); 9424 jcc(Assembler::equal, SAME_TILL_END); 9425 //falling through if less than 16 bytes left 9426 } else {//regular intrinsics 9427 9428 cmpq(length, 16); 9429 jccb(Assembler::less, VECTOR8_TAIL); 9430 9431 subq(length, 16); 9432 bind(VECTOR16_LOOP); 9433 movdqu(rymm0, Address(obja, result)); 9434 movdqu(rymm1, Address(objb, result)); 9435 pxor(rymm0, rymm1); 9436 ptest(rymm0, rymm0); 9437 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9438 addq(result, 16); 9439 subq(length, 16); 9440 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9441 addq(length, 16); 9442 jcc(Assembler::equal, SAME_TILL_END); 9443 //falling through if less than 16 bytes left 9444 } 9445 9446 bind(VECTOR8_TAIL); 9447 cmpq(length, 8); 9448 jccb(Assembler::less, VECTOR4_TAIL); 9449 bind(VECTOR8_LOOP); 9450 movq(tmp1, Address(obja, result)); 9451 movq(tmp2, Address(objb, result)); 9452 xorq(tmp1, tmp2); 9453 testq(tmp1, tmp1); 9454 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9455 addq(result, 8); 9456 subq(length, 8); 9457 jcc(Assembler::equal, SAME_TILL_END); 9458 //falling through if less than 8 bytes left 9459 9460 bind(VECTOR4_TAIL); 9461 cmpq(length, 4); 9462 jccb(Assembler::less, BYTES_TAIL); 9463 bind(VECTOR4_LOOP); 9464 movl(tmp1, Address(obja, result)); 9465 xorl(tmp1, Address(objb, result)); 9466 testl(tmp1, tmp1); 9467 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9468 addq(result, 4); 9469 subq(length, 4); 9470 jcc(Assembler::equal, SAME_TILL_END); 9471 //falling through if less than 4 bytes left 9472 9473 bind(BYTES_TAIL); 9474 bind(BYTES_LOOP); 9475 load_unsigned_byte(tmp1, Address(obja, result)); 9476 load_unsigned_byte(tmp2, Address(objb, result)); 9477 xorl(tmp1, tmp2); 9478 testl(tmp1, tmp1); 9479 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9480 decq(length); 9481 jccb(Assembler::zero, SAME_TILL_END); 9482 incq(result); 9483 load_unsigned_byte(tmp1, Address(obja, result)); 9484 load_unsigned_byte(tmp2, Address(objb, result)); 9485 xorl(tmp1, tmp2); 9486 testl(tmp1, tmp1); 9487 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9488 decq(length); 9489 jccb(Assembler::zero, SAME_TILL_END); 9490 incq(result); 9491 load_unsigned_byte(tmp1, Address(obja, result)); 9492 load_unsigned_byte(tmp2, Address(objb, result)); 9493 xorl(tmp1, tmp2); 9494 testl(tmp1, tmp1); 9495 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9496 jmpb(SAME_TILL_END); 9497 9498 if (UseAVX >= 2) { 9499 bind(VECTOR32_NOT_EQUAL); 9500 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9501 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9502 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9503 vpmovmskb(tmp1, rymm0); 9504 bsfq(tmp1, tmp1); 9505 addq(result, tmp1); 9506 shrq(result); 9507 jmpb(DONE); 9508 } 9509 9510 bind(VECTOR16_NOT_EQUAL); 9511 if (UseAVX >= 2) { 9512 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9513 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9514 pxor(rymm0, rymm2); 9515 } else { 9516 pcmpeqb(rymm2, rymm2); 9517 pxor(rymm0, rymm1); 9518 pcmpeqb(rymm0, rymm1); 9519 pxor(rymm0, rymm2); 9520 } 9521 pmovmskb(tmp1, rymm0); 9522 bsfq(tmp1, tmp1); 9523 addq(result, tmp1); 9524 shrq(result); 9525 jmpb(DONE); 9526 9527 bind(VECTOR8_NOT_EQUAL); 9528 bind(VECTOR4_NOT_EQUAL); 9529 bsfq(tmp1, tmp1); 9530 shrq(tmp1, 3); 9531 addq(result, tmp1); 9532 bind(BYTES_NOT_EQUAL); 9533 shrq(result); 9534 jmpb(DONE); 9535 9536 bind(SAME_TILL_END); 9537 mov64(result, -1); 9538 9539 bind(DONE); 9540 } 9541 9542 //Helper functions for square_to_len() 9543 9544 /** 9545 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9546 * Preserves x and z and modifies rest of the registers. 9547 */ 9548 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9549 // Perform square and right shift by 1 9550 // Handle odd xlen case first, then for even xlen do the following 9551 // jlong carry = 0; 9552 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9553 // huge_128 product = x[j:j+1] * x[j:j+1]; 9554 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9555 // z[i+2:i+3] = (jlong)(product >>> 1); 9556 // carry = (jlong)product; 9557 // } 9558 9559 xorq(tmp5, tmp5); // carry 9560 xorq(rdxReg, rdxReg); 9561 xorl(tmp1, tmp1); // index for x 9562 xorl(tmp4, tmp4); // index for z 9563 9564 Label L_first_loop, L_first_loop_exit; 9565 9566 testl(xlen, 1); 9567 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9568 9569 // Square and right shift by 1 the odd element using 32 bit multiply 9570 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9571 imulq(raxReg, raxReg); 9572 shrq(raxReg, 1); 9573 adcq(tmp5, 0); 9574 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9575 incrementl(tmp1); 9576 addl(tmp4, 2); 9577 9578 // Square and right shift by 1 the rest using 64 bit multiply 9579 bind(L_first_loop); 9580 cmpptr(tmp1, xlen); 9581 jccb(Assembler::equal, L_first_loop_exit); 9582 9583 // Square 9584 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9585 rorq(raxReg, 32); // convert big-endian to little-endian 9586 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9587 9588 // Right shift by 1 and save carry 9589 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9590 rcrq(rdxReg, 1); 9591 rcrq(raxReg, 1); 9592 adcq(tmp5, 0); 9593 9594 // Store result in z 9595 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9596 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9597 9598 // Update indices for x and z 9599 addl(tmp1, 2); 9600 addl(tmp4, 4); 9601 jmp(L_first_loop); 9602 9603 bind(L_first_loop_exit); 9604 } 9605 9606 9607 /** 9608 * Perform the following multiply add operation using BMI2 instructions 9609 * carry:sum = sum + op1*op2 + carry 9610 * op2 should be in rdx 9611 * op2 is preserved, all other registers are modified 9612 */ 9613 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9614 // assert op2 is rdx 9615 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9616 addq(sum, carry); 9617 adcq(tmp2, 0); 9618 addq(sum, op1); 9619 adcq(tmp2, 0); 9620 movq(carry, tmp2); 9621 } 9622 9623 /** 9624 * Perform the following multiply add operation: 9625 * carry:sum = sum + op1*op2 + carry 9626 * Preserves op1, op2 and modifies rest of registers 9627 */ 9628 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9629 // rdx:rax = op1 * op2 9630 movq(raxReg, op2); 9631 mulq(op1); 9632 9633 // rdx:rax = sum + carry + rdx:rax 9634 addq(sum, carry); 9635 adcq(rdxReg, 0); 9636 addq(sum, raxReg); 9637 adcq(rdxReg, 0); 9638 9639 // carry:sum = rdx:sum 9640 movq(carry, rdxReg); 9641 } 9642 9643 /** 9644 * Add 64 bit long carry into z[] with carry propogation. 9645 * Preserves z and carry register values and modifies rest of registers. 9646 * 9647 */ 9648 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9649 Label L_fourth_loop, L_fourth_loop_exit; 9650 9651 movl(tmp1, 1); 9652 subl(zlen, 2); 9653 addq(Address(z, zlen, Address::times_4, 0), carry); 9654 9655 bind(L_fourth_loop); 9656 jccb(Assembler::carryClear, L_fourth_loop_exit); 9657 subl(zlen, 2); 9658 jccb(Assembler::negative, L_fourth_loop_exit); 9659 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9660 jmp(L_fourth_loop); 9661 bind(L_fourth_loop_exit); 9662 } 9663 9664 /** 9665 * Shift z[] left by 1 bit. 9666 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9667 * 9668 */ 9669 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9670 9671 Label L_fifth_loop, L_fifth_loop_exit; 9672 9673 // Fifth loop 9674 // Perform primitiveLeftShift(z, zlen, 1) 9675 9676 const Register prev_carry = tmp1; 9677 const Register new_carry = tmp4; 9678 const Register value = tmp2; 9679 const Register zidx = tmp3; 9680 9681 // int zidx, carry; 9682 // long value; 9683 // carry = 0; 9684 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9685 // (carry:value) = (z[i] << 1) | carry ; 9686 // z[i] = value; 9687 // } 9688 9689 movl(zidx, zlen); 9690 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9691 9692 bind(L_fifth_loop); 9693 decl(zidx); // Use decl to preserve carry flag 9694 decl(zidx); 9695 jccb(Assembler::negative, L_fifth_loop_exit); 9696 9697 if (UseBMI2Instructions) { 9698 movq(value, Address(z, zidx, Address::times_4, 0)); 9699 rclq(value, 1); 9700 rorxq(value, value, 32); 9701 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9702 } 9703 else { 9704 // clear new_carry 9705 xorl(new_carry, new_carry); 9706 9707 // Shift z[i] by 1, or in previous carry and save new carry 9708 movq(value, Address(z, zidx, Address::times_4, 0)); 9709 shlq(value, 1); 9710 adcl(new_carry, 0); 9711 9712 orq(value, prev_carry); 9713 rorq(value, 0x20); 9714 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9715 9716 // Set previous carry = new carry 9717 movl(prev_carry, new_carry); 9718 } 9719 jmp(L_fifth_loop); 9720 9721 bind(L_fifth_loop_exit); 9722 } 9723 9724 9725 /** 9726 * Code for BigInteger::squareToLen() intrinsic 9727 * 9728 * rdi: x 9729 * rsi: len 9730 * r8: z 9731 * rcx: zlen 9732 * r12: tmp1 9733 * r13: tmp2 9734 * r14: tmp3 9735 * r15: tmp4 9736 * rbx: tmp5 9737 * 9738 */ 9739 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9740 9741 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9742 push(tmp1); 9743 push(tmp2); 9744 push(tmp3); 9745 push(tmp4); 9746 push(tmp5); 9747 9748 // First loop 9749 // Store the squares, right shifted one bit (i.e., divided by 2). 9750 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9751 9752 // Add in off-diagonal sums. 9753 // 9754 // Second, third (nested) and fourth loops. 9755 // zlen +=2; 9756 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9757 // carry = 0; 9758 // long op2 = x[xidx:xidx+1]; 9759 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9760 // k -= 2; 9761 // long op1 = x[j:j+1]; 9762 // long sum = z[k:k+1]; 9763 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9764 // z[k:k+1] = sum; 9765 // } 9766 // add_one_64(z, k, carry, tmp_regs); 9767 // } 9768 9769 const Register carry = tmp5; 9770 const Register sum = tmp3; 9771 const Register op1 = tmp4; 9772 Register op2 = tmp2; 9773 9774 push(zlen); 9775 push(len); 9776 addl(zlen,2); 9777 bind(L_second_loop); 9778 xorq(carry, carry); 9779 subl(zlen, 4); 9780 subl(len, 2); 9781 push(zlen); 9782 push(len); 9783 cmpl(len, 0); 9784 jccb(Assembler::lessEqual, L_second_loop_exit); 9785 9786 // Multiply an array by one 64 bit long. 9787 if (UseBMI2Instructions) { 9788 op2 = rdxReg; 9789 movq(op2, Address(x, len, Address::times_4, 0)); 9790 rorxq(op2, op2, 32); 9791 } 9792 else { 9793 movq(op2, Address(x, len, Address::times_4, 0)); 9794 rorq(op2, 32); 9795 } 9796 9797 bind(L_third_loop); 9798 decrementl(len); 9799 jccb(Assembler::negative, L_third_loop_exit); 9800 decrementl(len); 9801 jccb(Assembler::negative, L_last_x); 9802 9803 movq(op1, Address(x, len, Address::times_4, 0)); 9804 rorq(op1, 32); 9805 9806 bind(L_multiply); 9807 subl(zlen, 2); 9808 movq(sum, Address(z, zlen, Address::times_4, 0)); 9809 9810 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9811 if (UseBMI2Instructions) { 9812 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9813 } 9814 else { 9815 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9816 } 9817 9818 movq(Address(z, zlen, Address::times_4, 0), sum); 9819 9820 jmp(L_third_loop); 9821 bind(L_third_loop_exit); 9822 9823 // Fourth loop 9824 // Add 64 bit long carry into z with carry propogation. 9825 // Uses offsetted zlen. 9826 add_one_64(z, zlen, carry, tmp1); 9827 9828 pop(len); 9829 pop(zlen); 9830 jmp(L_second_loop); 9831 9832 // Next infrequent code is moved outside loops. 9833 bind(L_last_x); 9834 movl(op1, Address(x, 0)); 9835 jmp(L_multiply); 9836 9837 bind(L_second_loop_exit); 9838 pop(len); 9839 pop(zlen); 9840 pop(len); 9841 pop(zlen); 9842 9843 // Fifth loop 9844 // Shift z left 1 bit. 9845 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9846 9847 // z[zlen-1] |= x[len-1] & 1; 9848 movl(tmp3, Address(x, len, Address::times_4, -4)); 9849 andl(tmp3, 1); 9850 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9851 9852 pop(tmp5); 9853 pop(tmp4); 9854 pop(tmp3); 9855 pop(tmp2); 9856 pop(tmp1); 9857 } 9858 9859 /** 9860 * Helper function for mul_add() 9861 * Multiply the in[] by int k and add to out[] starting at offset offs using 9862 * 128 bit by 32 bit multiply and return the carry in tmp5. 9863 * Only quad int aligned length of in[] is operated on in this function. 9864 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9865 * This function preserves out, in and k registers. 9866 * len and offset point to the appropriate index in "in" & "out" correspondingly 9867 * tmp5 has the carry. 9868 * other registers are temporary and are modified. 9869 * 9870 */ 9871 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9872 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9873 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9874 9875 Label L_first_loop, L_first_loop_exit; 9876 9877 movl(tmp1, len); 9878 shrl(tmp1, 2); 9879 9880 bind(L_first_loop); 9881 subl(tmp1, 1); 9882 jccb(Assembler::negative, L_first_loop_exit); 9883 9884 subl(len, 4); 9885 subl(offset, 4); 9886 9887 Register op2 = tmp2; 9888 const Register sum = tmp3; 9889 const Register op1 = tmp4; 9890 const Register carry = tmp5; 9891 9892 if (UseBMI2Instructions) { 9893 op2 = rdxReg; 9894 } 9895 9896 movq(op1, Address(in, len, Address::times_4, 8)); 9897 rorq(op1, 32); 9898 movq(sum, Address(out, offset, Address::times_4, 8)); 9899 rorq(sum, 32); 9900 if (UseBMI2Instructions) { 9901 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9902 } 9903 else { 9904 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9905 } 9906 // Store back in big endian from little endian 9907 rorq(sum, 0x20); 9908 movq(Address(out, offset, Address::times_4, 8), sum); 9909 9910 movq(op1, Address(in, len, Address::times_4, 0)); 9911 rorq(op1, 32); 9912 movq(sum, Address(out, offset, Address::times_4, 0)); 9913 rorq(sum, 32); 9914 if (UseBMI2Instructions) { 9915 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9916 } 9917 else { 9918 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9919 } 9920 // Store back in big endian from little endian 9921 rorq(sum, 0x20); 9922 movq(Address(out, offset, Address::times_4, 0), sum); 9923 9924 jmp(L_first_loop); 9925 bind(L_first_loop_exit); 9926 } 9927 9928 /** 9929 * Code for BigInteger::mulAdd() intrinsic 9930 * 9931 * rdi: out 9932 * rsi: in 9933 * r11: offs (out.length - offset) 9934 * rcx: len 9935 * r8: k 9936 * r12: tmp1 9937 * r13: tmp2 9938 * r14: tmp3 9939 * r15: tmp4 9940 * rbx: tmp5 9941 * Multiply the in[] by word k and add to out[], return the carry in rax 9942 */ 9943 void MacroAssembler::mul_add(Register out, Register in, Register offs, 9944 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 9945 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9946 9947 Label L_carry, L_last_in, L_done; 9948 9949 // carry = 0; 9950 // for (int j=len-1; j >= 0; j--) { 9951 // long product = (in[j] & LONG_MASK) * kLong + 9952 // (out[offs] & LONG_MASK) + carry; 9953 // out[offs--] = (int)product; 9954 // carry = product >>> 32; 9955 // } 9956 // 9957 push(tmp1); 9958 push(tmp2); 9959 push(tmp3); 9960 push(tmp4); 9961 push(tmp5); 9962 9963 Register op2 = tmp2; 9964 const Register sum = tmp3; 9965 const Register op1 = tmp4; 9966 const Register carry = tmp5; 9967 9968 if (UseBMI2Instructions) { 9969 op2 = rdxReg; 9970 movl(op2, k); 9971 } 9972 else { 9973 movl(op2, k); 9974 } 9975 9976 xorq(carry, carry); 9977 9978 //First loop 9979 9980 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 9981 //The carry is in tmp5 9982 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 9983 9984 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 9985 decrementl(len); 9986 jccb(Assembler::negative, L_carry); 9987 decrementl(len); 9988 jccb(Assembler::negative, L_last_in); 9989 9990 movq(op1, Address(in, len, Address::times_4, 0)); 9991 rorq(op1, 32); 9992 9993 subl(offs, 2); 9994 movq(sum, Address(out, offs, Address::times_4, 0)); 9995 rorq(sum, 32); 9996 9997 if (UseBMI2Instructions) { 9998 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9999 } 10000 else { 10001 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10002 } 10003 10004 // Store back in big endian from little endian 10005 rorq(sum, 0x20); 10006 movq(Address(out, offs, Address::times_4, 0), sum); 10007 10008 testl(len, len); 10009 jccb(Assembler::zero, L_carry); 10010 10011 //Multiply the last in[] entry, if any 10012 bind(L_last_in); 10013 movl(op1, Address(in, 0)); 10014 movl(sum, Address(out, offs, Address::times_4, -4)); 10015 10016 movl(raxReg, k); 10017 mull(op1); //tmp4 * eax -> edx:eax 10018 addl(sum, carry); 10019 adcl(rdxReg, 0); 10020 addl(sum, raxReg); 10021 adcl(rdxReg, 0); 10022 movl(carry, rdxReg); 10023 10024 movl(Address(out, offs, Address::times_4, -4), sum); 10025 10026 bind(L_carry); 10027 //return tmp5/carry as carry in rax 10028 movl(rax, carry); 10029 10030 bind(L_done); 10031 pop(tmp5); 10032 pop(tmp4); 10033 pop(tmp3); 10034 pop(tmp2); 10035 pop(tmp1); 10036 } 10037 #endif 10038 10039 /** 10040 * Emits code to update CRC-32 with a byte value according to constants in table 10041 * 10042 * @param [in,out]crc Register containing the crc. 10043 * @param [in]val Register containing the byte to fold into the CRC. 10044 * @param [in]table Register containing the table of crc constants. 10045 * 10046 * uint32_t crc; 10047 * val = crc_table[(val ^ crc) & 0xFF]; 10048 * crc = val ^ (crc >> 8); 10049 * 10050 */ 10051 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10052 xorl(val, crc); 10053 andl(val, 0xFF); 10054 shrl(crc, 8); // unsigned shift 10055 xorl(crc, Address(table, val, Address::times_4, 0)); 10056 } 10057 10058 /** 10059 * Fold 128-bit data chunk 10060 */ 10061 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10062 if (UseAVX > 0) { 10063 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10064 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10065 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10066 pxor(xcrc, xtmp); 10067 } else { 10068 movdqa(xtmp, xcrc); 10069 pclmulhdq(xtmp, xK); // [123:64] 10070 pclmulldq(xcrc, xK); // [63:0] 10071 pxor(xcrc, xtmp); 10072 movdqu(xtmp, Address(buf, offset)); 10073 pxor(xcrc, xtmp); 10074 } 10075 } 10076 10077 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10078 if (UseAVX > 0) { 10079 vpclmulhdq(xtmp, xK, xcrc); 10080 vpclmulldq(xcrc, xK, xcrc); 10081 pxor(xcrc, xbuf); 10082 pxor(xcrc, xtmp); 10083 } else { 10084 movdqa(xtmp, xcrc); 10085 pclmulhdq(xtmp, xK); 10086 pclmulldq(xcrc, xK); 10087 pxor(xcrc, xbuf); 10088 pxor(xcrc, xtmp); 10089 } 10090 } 10091 10092 /** 10093 * 8-bit folds to compute 32-bit CRC 10094 * 10095 * uint64_t xcrc; 10096 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10097 */ 10098 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10099 movdl(tmp, xcrc); 10100 andl(tmp, 0xFF); 10101 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10102 psrldq(xcrc, 1); // unsigned shift one byte 10103 pxor(xcrc, xtmp); 10104 } 10105 10106 /** 10107 * uint32_t crc; 10108 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10109 */ 10110 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10111 movl(tmp, crc); 10112 andl(tmp, 0xFF); 10113 shrl(crc, 8); 10114 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10115 } 10116 10117 /** 10118 * @param crc register containing existing CRC (32-bit) 10119 * @param buf register pointing to input byte buffer (byte*) 10120 * @param len register containing number of bytes 10121 * @param table register that will contain address of CRC table 10122 * @param tmp scratch register 10123 */ 10124 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10125 assert_different_registers(crc, buf, len, table, tmp, rax); 10126 10127 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10128 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10129 10130 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10131 // context for the registers used, where all instructions below are using 128-bit mode 10132 // On EVEX without VL and BW, these instructions will all be AVX. 10133 if (VM_Version::supports_avx512vlbw()) { 10134 movl(tmp, 0xffff); 10135 kmovwl(k1, tmp); 10136 } 10137 10138 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10139 notl(crc); // ~crc 10140 cmpl(len, 16); 10141 jcc(Assembler::less, L_tail); 10142 10143 // Align buffer to 16 bytes 10144 movl(tmp, buf); 10145 andl(tmp, 0xF); 10146 jccb(Assembler::zero, L_aligned); 10147 subl(tmp, 16); 10148 addl(len, tmp); 10149 10150 align(4); 10151 BIND(L_align_loop); 10152 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10153 update_byte_crc32(crc, rax, table); 10154 increment(buf); 10155 incrementl(tmp); 10156 jccb(Assembler::less, L_align_loop); 10157 10158 BIND(L_aligned); 10159 movl(tmp, len); // save 10160 shrl(len, 4); 10161 jcc(Assembler::zero, L_tail_restore); 10162 10163 // Fold crc into first bytes of vector 10164 movdqa(xmm1, Address(buf, 0)); 10165 movdl(rax, xmm1); 10166 xorl(crc, rax); 10167 if (VM_Version::supports_sse4_1()) { 10168 pinsrd(xmm1, crc, 0); 10169 } else { 10170 pinsrw(xmm1, crc, 0); 10171 shrl(crc, 16); 10172 pinsrw(xmm1, crc, 1); 10173 } 10174 addptr(buf, 16); 10175 subl(len, 4); // len > 0 10176 jcc(Assembler::less, L_fold_tail); 10177 10178 movdqa(xmm2, Address(buf, 0)); 10179 movdqa(xmm3, Address(buf, 16)); 10180 movdqa(xmm4, Address(buf, 32)); 10181 addptr(buf, 48); 10182 subl(len, 3); 10183 jcc(Assembler::lessEqual, L_fold_512b); 10184 10185 // Fold total 512 bits of polynomial on each iteration, 10186 // 128 bits per each of 4 parallel streams. 10187 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10188 10189 align(32); 10190 BIND(L_fold_512b_loop); 10191 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10192 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10193 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10194 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10195 addptr(buf, 64); 10196 subl(len, 4); 10197 jcc(Assembler::greater, L_fold_512b_loop); 10198 10199 // Fold 512 bits to 128 bits. 10200 BIND(L_fold_512b); 10201 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10202 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10203 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10204 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10205 10206 // Fold the rest of 128 bits data chunks 10207 BIND(L_fold_tail); 10208 addl(len, 3); 10209 jccb(Assembler::lessEqual, L_fold_128b); 10210 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10211 10212 BIND(L_fold_tail_loop); 10213 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10214 addptr(buf, 16); 10215 decrementl(len); 10216 jccb(Assembler::greater, L_fold_tail_loop); 10217 10218 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10219 BIND(L_fold_128b); 10220 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10221 if (UseAVX > 0) { 10222 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10223 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10224 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10225 } else { 10226 movdqa(xmm2, xmm0); 10227 pclmulqdq(xmm2, xmm1, 0x1); 10228 movdqa(xmm3, xmm0); 10229 pand(xmm3, xmm2); 10230 pclmulqdq(xmm0, xmm3, 0x1); 10231 } 10232 psrldq(xmm1, 8); 10233 psrldq(xmm2, 4); 10234 pxor(xmm0, xmm1); 10235 pxor(xmm0, xmm2); 10236 10237 // 8 8-bit folds to compute 32-bit CRC. 10238 for (int j = 0; j < 4; j++) { 10239 fold_8bit_crc32(xmm0, table, xmm1, rax); 10240 } 10241 movdl(crc, xmm0); // mov 32 bits to general register 10242 for (int j = 0; j < 4; j++) { 10243 fold_8bit_crc32(crc, table, rax); 10244 } 10245 10246 BIND(L_tail_restore); 10247 movl(len, tmp); // restore 10248 BIND(L_tail); 10249 andl(len, 0xf); 10250 jccb(Assembler::zero, L_exit); 10251 10252 // Fold the rest of bytes 10253 align(4); 10254 BIND(L_tail_loop); 10255 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10256 update_byte_crc32(crc, rax, table); 10257 increment(buf); 10258 decrementl(len); 10259 jccb(Assembler::greater, L_tail_loop); 10260 10261 BIND(L_exit); 10262 notl(crc); // ~c 10263 } 10264 10265 #ifdef _LP64 10266 // S. Gueron / Information Processing Letters 112 (2012) 184 10267 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10268 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10269 // Output: the 64-bit carry-less product of B * CONST 10270 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10271 Register tmp1, Register tmp2, Register tmp3) { 10272 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10273 if (n > 0) { 10274 addq(tmp3, n * 256 * 8); 10275 } 10276 // Q1 = TABLEExt[n][B & 0xFF]; 10277 movl(tmp1, in); 10278 andl(tmp1, 0x000000FF); 10279 shll(tmp1, 3); 10280 addq(tmp1, tmp3); 10281 movq(tmp1, Address(tmp1, 0)); 10282 10283 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10284 movl(tmp2, in); 10285 shrl(tmp2, 8); 10286 andl(tmp2, 0x000000FF); 10287 shll(tmp2, 3); 10288 addq(tmp2, tmp3); 10289 movq(tmp2, Address(tmp2, 0)); 10290 10291 shlq(tmp2, 8); 10292 xorq(tmp1, tmp2); 10293 10294 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10295 movl(tmp2, in); 10296 shrl(tmp2, 16); 10297 andl(tmp2, 0x000000FF); 10298 shll(tmp2, 3); 10299 addq(tmp2, tmp3); 10300 movq(tmp2, Address(tmp2, 0)); 10301 10302 shlq(tmp2, 16); 10303 xorq(tmp1, tmp2); 10304 10305 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10306 shrl(in, 24); 10307 andl(in, 0x000000FF); 10308 shll(in, 3); 10309 addq(in, tmp3); 10310 movq(in, Address(in, 0)); 10311 10312 shlq(in, 24); 10313 xorq(in, tmp1); 10314 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10315 } 10316 10317 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10318 Register in_out, 10319 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10320 XMMRegister w_xtmp2, 10321 Register tmp1, 10322 Register n_tmp2, Register n_tmp3) { 10323 if (is_pclmulqdq_supported) { 10324 movdl(w_xtmp1, in_out); // modified blindly 10325 10326 movl(tmp1, const_or_pre_comp_const_index); 10327 movdl(w_xtmp2, tmp1); 10328 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10329 10330 movdq(in_out, w_xtmp1); 10331 } else { 10332 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10333 } 10334 } 10335 10336 // Recombination Alternative 2: No bit-reflections 10337 // T1 = (CRC_A * U1) << 1 10338 // T2 = (CRC_B * U2) << 1 10339 // C1 = T1 >> 32 10340 // C2 = T2 >> 32 10341 // T1 = T1 & 0xFFFFFFFF 10342 // T2 = T2 & 0xFFFFFFFF 10343 // T1 = CRC32(0, T1) 10344 // T2 = CRC32(0, T2) 10345 // C1 = C1 ^ T1 10346 // C2 = C2 ^ T2 10347 // CRC = C1 ^ C2 ^ CRC_C 10348 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10349 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10350 Register tmp1, Register tmp2, 10351 Register n_tmp3) { 10352 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10353 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10354 shlq(in_out, 1); 10355 movl(tmp1, in_out); 10356 shrq(in_out, 32); 10357 xorl(tmp2, tmp2); 10358 crc32(tmp2, tmp1, 4); 10359 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10360 shlq(in1, 1); 10361 movl(tmp1, in1); 10362 shrq(in1, 32); 10363 xorl(tmp2, tmp2); 10364 crc32(tmp2, tmp1, 4); 10365 xorl(in1, tmp2); 10366 xorl(in_out, in1); 10367 xorl(in_out, in2); 10368 } 10369 10370 // Set N to predefined value 10371 // Subtract from a lenght of a buffer 10372 // execute in a loop: 10373 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10374 // for i = 1 to N do 10375 // CRC_A = CRC32(CRC_A, A[i]) 10376 // CRC_B = CRC32(CRC_B, B[i]) 10377 // CRC_C = CRC32(CRC_C, C[i]) 10378 // end for 10379 // Recombine 10380 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10381 Register in_out1, Register in_out2, Register in_out3, 10382 Register tmp1, Register tmp2, Register tmp3, 10383 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10384 Register tmp4, Register tmp5, 10385 Register n_tmp6) { 10386 Label L_processPartitions; 10387 Label L_processPartition; 10388 Label L_exit; 10389 10390 bind(L_processPartitions); 10391 cmpl(in_out1, 3 * size); 10392 jcc(Assembler::less, L_exit); 10393 xorl(tmp1, tmp1); 10394 xorl(tmp2, tmp2); 10395 movq(tmp3, in_out2); 10396 addq(tmp3, size); 10397 10398 bind(L_processPartition); 10399 crc32(in_out3, Address(in_out2, 0), 8); 10400 crc32(tmp1, Address(in_out2, size), 8); 10401 crc32(tmp2, Address(in_out2, size * 2), 8); 10402 addq(in_out2, 8); 10403 cmpq(in_out2, tmp3); 10404 jcc(Assembler::less, L_processPartition); 10405 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10406 w_xtmp1, w_xtmp2, w_xtmp3, 10407 tmp4, tmp5, 10408 n_tmp6); 10409 addq(in_out2, 2 * size); 10410 subl(in_out1, 3 * size); 10411 jmp(L_processPartitions); 10412 10413 bind(L_exit); 10414 } 10415 #else 10416 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10417 Register tmp1, Register tmp2, Register tmp3, 10418 XMMRegister xtmp1, XMMRegister xtmp2) { 10419 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10420 if (n > 0) { 10421 addl(tmp3, n * 256 * 8); 10422 } 10423 // Q1 = TABLEExt[n][B & 0xFF]; 10424 movl(tmp1, in_out); 10425 andl(tmp1, 0x000000FF); 10426 shll(tmp1, 3); 10427 addl(tmp1, tmp3); 10428 movq(xtmp1, Address(tmp1, 0)); 10429 10430 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10431 movl(tmp2, in_out); 10432 shrl(tmp2, 8); 10433 andl(tmp2, 0x000000FF); 10434 shll(tmp2, 3); 10435 addl(tmp2, tmp3); 10436 movq(xtmp2, Address(tmp2, 0)); 10437 10438 psllq(xtmp2, 8); 10439 pxor(xtmp1, xtmp2); 10440 10441 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10442 movl(tmp2, in_out); 10443 shrl(tmp2, 16); 10444 andl(tmp2, 0x000000FF); 10445 shll(tmp2, 3); 10446 addl(tmp2, tmp3); 10447 movq(xtmp2, Address(tmp2, 0)); 10448 10449 psllq(xtmp2, 16); 10450 pxor(xtmp1, xtmp2); 10451 10452 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10453 shrl(in_out, 24); 10454 andl(in_out, 0x000000FF); 10455 shll(in_out, 3); 10456 addl(in_out, tmp3); 10457 movq(xtmp2, Address(in_out, 0)); 10458 10459 psllq(xtmp2, 24); 10460 pxor(xtmp1, xtmp2); // Result in CXMM 10461 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10462 } 10463 10464 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10465 Register in_out, 10466 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10467 XMMRegister w_xtmp2, 10468 Register tmp1, 10469 Register n_tmp2, Register n_tmp3) { 10470 if (is_pclmulqdq_supported) { 10471 movdl(w_xtmp1, in_out); 10472 10473 movl(tmp1, const_or_pre_comp_const_index); 10474 movdl(w_xtmp2, tmp1); 10475 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10476 // Keep result in XMM since GPR is 32 bit in length 10477 } else { 10478 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10479 } 10480 } 10481 10482 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10483 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10484 Register tmp1, Register tmp2, 10485 Register n_tmp3) { 10486 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10487 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10488 10489 psllq(w_xtmp1, 1); 10490 movdl(tmp1, w_xtmp1); 10491 psrlq(w_xtmp1, 32); 10492 movdl(in_out, w_xtmp1); 10493 10494 xorl(tmp2, tmp2); 10495 crc32(tmp2, tmp1, 4); 10496 xorl(in_out, tmp2); 10497 10498 psllq(w_xtmp2, 1); 10499 movdl(tmp1, w_xtmp2); 10500 psrlq(w_xtmp2, 32); 10501 movdl(in1, w_xtmp2); 10502 10503 xorl(tmp2, tmp2); 10504 crc32(tmp2, tmp1, 4); 10505 xorl(in1, tmp2); 10506 xorl(in_out, in1); 10507 xorl(in_out, in2); 10508 } 10509 10510 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10511 Register in_out1, Register in_out2, Register in_out3, 10512 Register tmp1, Register tmp2, Register tmp3, 10513 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10514 Register tmp4, Register tmp5, 10515 Register n_tmp6) { 10516 Label L_processPartitions; 10517 Label L_processPartition; 10518 Label L_exit; 10519 10520 bind(L_processPartitions); 10521 cmpl(in_out1, 3 * size); 10522 jcc(Assembler::less, L_exit); 10523 xorl(tmp1, tmp1); 10524 xorl(tmp2, tmp2); 10525 movl(tmp3, in_out2); 10526 addl(tmp3, size); 10527 10528 bind(L_processPartition); 10529 crc32(in_out3, Address(in_out2, 0), 4); 10530 crc32(tmp1, Address(in_out2, size), 4); 10531 crc32(tmp2, Address(in_out2, size*2), 4); 10532 crc32(in_out3, Address(in_out2, 0+4), 4); 10533 crc32(tmp1, Address(in_out2, size+4), 4); 10534 crc32(tmp2, Address(in_out2, size*2+4), 4); 10535 addl(in_out2, 8); 10536 cmpl(in_out2, tmp3); 10537 jcc(Assembler::less, L_processPartition); 10538 10539 push(tmp3); 10540 push(in_out1); 10541 push(in_out2); 10542 tmp4 = tmp3; 10543 tmp5 = in_out1; 10544 n_tmp6 = in_out2; 10545 10546 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10547 w_xtmp1, w_xtmp2, w_xtmp3, 10548 tmp4, tmp5, 10549 n_tmp6); 10550 10551 pop(in_out2); 10552 pop(in_out1); 10553 pop(tmp3); 10554 10555 addl(in_out2, 2 * size); 10556 subl(in_out1, 3 * size); 10557 jmp(L_processPartitions); 10558 10559 bind(L_exit); 10560 } 10561 #endif //LP64 10562 10563 #ifdef _LP64 10564 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10565 // Input: A buffer I of L bytes. 10566 // Output: the CRC32C value of the buffer. 10567 // Notations: 10568 // Write L = 24N + r, with N = floor (L/24). 10569 // r = L mod 24 (0 <= r < 24). 10570 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10571 // N quadwords, and R consists of r bytes. 10572 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10573 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10574 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10575 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10576 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10577 Register tmp1, Register tmp2, Register tmp3, 10578 Register tmp4, Register tmp5, Register tmp6, 10579 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10580 bool is_pclmulqdq_supported) { 10581 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10582 Label L_wordByWord; 10583 Label L_byteByByteProlog; 10584 Label L_byteByByte; 10585 Label L_exit; 10586 10587 if (is_pclmulqdq_supported ) { 10588 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10589 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10590 10591 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10592 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10593 10594 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10595 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10596 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10597 } else { 10598 const_or_pre_comp_const_index[0] = 1; 10599 const_or_pre_comp_const_index[1] = 0; 10600 10601 const_or_pre_comp_const_index[2] = 3; 10602 const_or_pre_comp_const_index[3] = 2; 10603 10604 const_or_pre_comp_const_index[4] = 5; 10605 const_or_pre_comp_const_index[5] = 4; 10606 } 10607 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10608 in2, in1, in_out, 10609 tmp1, tmp2, tmp3, 10610 w_xtmp1, w_xtmp2, w_xtmp3, 10611 tmp4, tmp5, 10612 tmp6); 10613 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10614 in2, in1, in_out, 10615 tmp1, tmp2, tmp3, 10616 w_xtmp1, w_xtmp2, w_xtmp3, 10617 tmp4, tmp5, 10618 tmp6); 10619 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10620 in2, in1, in_out, 10621 tmp1, tmp2, tmp3, 10622 w_xtmp1, w_xtmp2, w_xtmp3, 10623 tmp4, tmp5, 10624 tmp6); 10625 movl(tmp1, in2); 10626 andl(tmp1, 0x00000007); 10627 negl(tmp1); 10628 addl(tmp1, in2); 10629 addq(tmp1, in1); 10630 10631 BIND(L_wordByWord); 10632 cmpq(in1, tmp1); 10633 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10634 crc32(in_out, Address(in1, 0), 4); 10635 addq(in1, 4); 10636 jmp(L_wordByWord); 10637 10638 BIND(L_byteByByteProlog); 10639 andl(in2, 0x00000007); 10640 movl(tmp2, 1); 10641 10642 BIND(L_byteByByte); 10643 cmpl(tmp2, in2); 10644 jccb(Assembler::greater, L_exit); 10645 crc32(in_out, Address(in1, 0), 1); 10646 incq(in1); 10647 incl(tmp2); 10648 jmp(L_byteByByte); 10649 10650 BIND(L_exit); 10651 } 10652 #else 10653 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10654 Register tmp1, Register tmp2, Register tmp3, 10655 Register tmp4, Register tmp5, Register tmp6, 10656 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10657 bool is_pclmulqdq_supported) { 10658 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10659 Label L_wordByWord; 10660 Label L_byteByByteProlog; 10661 Label L_byteByByte; 10662 Label L_exit; 10663 10664 if (is_pclmulqdq_supported) { 10665 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10666 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10667 10668 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10669 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10670 10671 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10672 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10673 } else { 10674 const_or_pre_comp_const_index[0] = 1; 10675 const_or_pre_comp_const_index[1] = 0; 10676 10677 const_or_pre_comp_const_index[2] = 3; 10678 const_or_pre_comp_const_index[3] = 2; 10679 10680 const_or_pre_comp_const_index[4] = 5; 10681 const_or_pre_comp_const_index[5] = 4; 10682 } 10683 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10684 in2, in1, in_out, 10685 tmp1, tmp2, tmp3, 10686 w_xtmp1, w_xtmp2, w_xtmp3, 10687 tmp4, tmp5, 10688 tmp6); 10689 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10690 in2, in1, in_out, 10691 tmp1, tmp2, tmp3, 10692 w_xtmp1, w_xtmp2, w_xtmp3, 10693 tmp4, tmp5, 10694 tmp6); 10695 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10696 in2, in1, in_out, 10697 tmp1, tmp2, tmp3, 10698 w_xtmp1, w_xtmp2, w_xtmp3, 10699 tmp4, tmp5, 10700 tmp6); 10701 movl(tmp1, in2); 10702 andl(tmp1, 0x00000007); 10703 negl(tmp1); 10704 addl(tmp1, in2); 10705 addl(tmp1, in1); 10706 10707 BIND(L_wordByWord); 10708 cmpl(in1, tmp1); 10709 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10710 crc32(in_out, Address(in1,0), 4); 10711 addl(in1, 4); 10712 jmp(L_wordByWord); 10713 10714 BIND(L_byteByByteProlog); 10715 andl(in2, 0x00000007); 10716 movl(tmp2, 1); 10717 10718 BIND(L_byteByByte); 10719 cmpl(tmp2, in2); 10720 jccb(Assembler::greater, L_exit); 10721 movb(tmp1, Address(in1, 0)); 10722 crc32(in_out, tmp1, 1); 10723 incl(in1); 10724 incl(tmp2); 10725 jmp(L_byteByByte); 10726 10727 BIND(L_exit); 10728 } 10729 #endif // LP64 10730 #undef BIND 10731 #undef BLOCK_COMMENT 10732 10733 // Compress char[] array to byte[]. 10734 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10735 // @HotSpotIntrinsicCandidate 10736 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10737 // for (int i = 0; i < len; i++) { 10738 // int c = src[srcOff++]; 10739 // if (c >>> 8 != 0) { 10740 // return 0; 10741 // } 10742 // dst[dstOff++] = (byte)c; 10743 // } 10744 // return len; 10745 // } 10746 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10747 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10748 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10749 Register tmp5, Register result) { 10750 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10751 10752 // rsi: src 10753 // rdi: dst 10754 // rdx: len 10755 // rcx: tmp5 10756 // rax: result 10757 10758 // rsi holds start addr of source char[] to be compressed 10759 // rdi holds start addr of destination byte[] 10760 // rdx holds length 10761 10762 assert(len != result, ""); 10763 10764 // save length for return 10765 push(len); 10766 10767 // 8165287: EVEX version disabled for now, needs to be refactored as 10768 // it is returning incorrect results. 10769 if ((UseAVX > 2) && // AVX512 10770 0 && 10771 VM_Version::supports_avx512vlbw() && 10772 VM_Version::supports_bmi2()) { 10773 10774 set_vector_masking(); // opening of the stub context for programming mask registers 10775 10776 Label copy_32_loop, copy_loop_tail, copy_just_portion_of_candidates; 10777 10778 // alignement 10779 Label post_alignement; 10780 10781 // if length of the string is less than 16, handle it in an old fashioned 10782 // way 10783 testl(len, -32); 10784 jcc(Assembler::zero, below_threshold); 10785 10786 // First check whether a character is compressable ( <= 0xFF). 10787 // Create mask to test for Unicode chars inside zmm vector 10788 movl(result, 0x00FF); 10789 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10790 10791 testl(len, -64); 10792 jcc(Assembler::zero, post_alignement); 10793 10794 // Save k1 10795 kmovql(k3, k1); 10796 10797 movl(tmp5, dst); 10798 andl(tmp5, (64 - 1)); 10799 negl(tmp5); 10800 andl(tmp5, (64 - 1)); 10801 10802 // bail out when there is nothing to be done 10803 testl(tmp5, 0xFFFFFFFF); 10804 jcc(Assembler::zero, post_alignement); 10805 10806 // ~(~0 << len), where len is the # of remaining elements to process 10807 movl(result, 0xFFFFFFFF); 10808 shlxl(result, result, tmp5); 10809 notl(result); 10810 10811 kmovdl(k1, result); 10812 10813 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10814 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10815 ktestd(k2, k1); 10816 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10817 10818 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10819 10820 addptr(src, tmp5); 10821 addptr(src, tmp5); 10822 addptr(dst, tmp5); 10823 subl(len, tmp5); 10824 10825 bind(post_alignement); 10826 // end of alignement 10827 10828 movl(tmp5, len); 10829 andl(tmp5, (32 - 1)); // tail count (in chars) 10830 andl(len, ~(32 - 1)); // vector count (in chars) 10831 jcc(Assembler::zero, copy_loop_tail); 10832 10833 lea(src, Address(src, len, Address::times_2)); 10834 lea(dst, Address(dst, len, Address::times_1)); 10835 negptr(len); 10836 10837 bind(copy_32_loop); 10838 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10839 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10840 kortestdl(k2, k2); 10841 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10842 10843 // All elements in current processed chunk are valid candidates for 10844 // compression. Write a truncated byte elements to the memory. 10845 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10846 addptr(len, 32); 10847 jcc(Assembler::notZero, copy_32_loop); 10848 10849 bind(copy_loop_tail); 10850 // bail out when there is nothing to be done 10851 testl(tmp5, 0xFFFFFFFF); 10852 jcc(Assembler::zero, return_length); 10853 10854 // Save k1 10855 kmovql(k3, k1); 10856 10857 movl(len, tmp5); 10858 10859 // ~(~0 << len), where len is the # of remaining elements to process 10860 movl(result, 0xFFFFFFFF); 10861 shlxl(result, result, len); 10862 notl(result); 10863 10864 kmovdl(k1, result); 10865 10866 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10867 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10868 ktestd(k2, k1); 10869 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10870 10871 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10872 // Restore k1 10873 kmovql(k1, k3); 10874 10875 jmp(return_length); 10876 10877 bind(copy_just_portion_of_candidates); 10878 kmovdl(tmp5, k2); 10879 tzcntl(tmp5, tmp5); 10880 10881 // ~(~0 << tmp5), where tmp5 is a number of elements in an array from the 10882 // result to the first element larger than 0xFF 10883 movl(result, 0xFFFFFFFF); 10884 shlxl(result, result, tmp5); 10885 notl(result); 10886 10887 kmovdl(k1, result); 10888 10889 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10890 // Restore k1 10891 kmovql(k1, k3); 10892 10893 jmp(return_zero); 10894 10895 clear_vector_masking(); // closing of the stub context for programming mask registers 10896 } 10897 if (UseSSE42Intrinsics) { 10898 Label copy_32_loop, copy_16, copy_tail; 10899 10900 bind(below_threshold); 10901 10902 movl(result, len); 10903 10904 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10905 10906 // vectored compression 10907 andl(len, 0xfffffff0); // vector count (in chars) 10908 andl(result, 0x0000000f); // tail count (in chars) 10909 testl(len, len); 10910 jccb(Assembler::zero, copy_16); 10911 10912 // compress 16 chars per iter 10913 movdl(tmp1Reg, tmp5); 10914 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10915 pxor(tmp4Reg, tmp4Reg); 10916 10917 lea(src, Address(src, len, Address::times_2)); 10918 lea(dst, Address(dst, len, Address::times_1)); 10919 negptr(len); 10920 10921 bind(copy_32_loop); 10922 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 10923 por(tmp4Reg, tmp2Reg); 10924 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 10925 por(tmp4Reg, tmp3Reg); 10926 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 10927 jcc(Assembler::notZero, return_zero); 10928 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 10929 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 10930 addptr(len, 16); 10931 jcc(Assembler::notZero, copy_32_loop); 10932 10933 // compress next vector of 8 chars (if any) 10934 bind(copy_16); 10935 movl(len, result); 10936 andl(len, 0xfffffff8); // vector count (in chars) 10937 andl(result, 0x00000007); // tail count (in chars) 10938 testl(len, len); 10939 jccb(Assembler::zero, copy_tail); 10940 10941 movdl(tmp1Reg, tmp5); 10942 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10943 pxor(tmp3Reg, tmp3Reg); 10944 10945 movdqu(tmp2Reg, Address(src, 0)); 10946 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 10947 jccb(Assembler::notZero, return_zero); 10948 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 10949 movq(Address(dst, 0), tmp2Reg); 10950 addptr(src, 16); 10951 addptr(dst, 8); 10952 10953 bind(copy_tail); 10954 movl(len, result); 10955 } 10956 // compress 1 char per iter 10957 testl(len, len); 10958 jccb(Assembler::zero, return_length); 10959 lea(src, Address(src, len, Address::times_2)); 10960 lea(dst, Address(dst, len, Address::times_1)); 10961 negptr(len); 10962 10963 bind(copy_chars_loop); 10964 load_unsigned_short(result, Address(src, len, Address::times_2)); 10965 testl(result, 0xff00); // check if Unicode char 10966 jccb(Assembler::notZero, return_zero); 10967 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 10968 increment(len); 10969 jcc(Assembler::notZero, copy_chars_loop); 10970 10971 // if compression succeeded, return length 10972 bind(return_length); 10973 pop(result); 10974 jmpb(done); 10975 10976 // if compression failed, return 0 10977 bind(return_zero); 10978 xorl(result, result); 10979 addptr(rsp, wordSize); 10980 10981 bind(done); 10982 } 10983 10984 // Inflate byte[] array to char[]. 10985 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 10986 // @HotSpotIntrinsicCandidate 10987 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 10988 // for (int i = 0; i < len; i++) { 10989 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 10990 // } 10991 // } 10992 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 10993 XMMRegister tmp1, Register tmp2) { 10994 Label copy_chars_loop, done, below_threshold; 10995 // rsi: src 10996 // rdi: dst 10997 // rdx: len 10998 // rcx: tmp2 10999 11000 // rsi holds start addr of source byte[] to be inflated 11001 // rdi holds start addr of destination char[] 11002 // rdx holds length 11003 assert_different_registers(src, dst, len, tmp2); 11004 11005 if ((UseAVX > 2) && // AVX512 11006 VM_Version::supports_avx512vlbw() && 11007 VM_Version::supports_bmi2()) { 11008 11009 set_vector_masking(); // opening of the stub context for programming mask registers 11010 11011 Label copy_32_loop, copy_tail; 11012 Register tmp3_aliased = len; 11013 11014 // if length of the string is less than 16, handle it in an old fashioned 11015 // way 11016 testl(len, -16); 11017 jcc(Assembler::zero, below_threshold); 11018 11019 // In order to use only one arithmetic operation for the main loop we use 11020 // this pre-calculation 11021 movl(tmp2, len); 11022 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11023 andl(len, -32); // vector count 11024 jccb(Assembler::zero, copy_tail); 11025 11026 lea(src, Address(src, len, Address::times_1)); 11027 lea(dst, Address(dst, len, Address::times_2)); 11028 negptr(len); 11029 11030 11031 // inflate 32 chars per iter 11032 bind(copy_32_loop); 11033 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11034 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11035 addptr(len, 32); 11036 jcc(Assembler::notZero, copy_32_loop); 11037 11038 bind(copy_tail); 11039 // bail out when there is nothing to be done 11040 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11041 jcc(Assembler::zero, done); 11042 11043 // Save k1 11044 kmovql(k2, k1); 11045 11046 // ~(~0 << length), where length is the # of remaining elements to process 11047 movl(tmp3_aliased, -1); 11048 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11049 notl(tmp3_aliased); 11050 kmovdl(k1, tmp3_aliased); 11051 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11052 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11053 11054 // Restore k1 11055 kmovql(k1, k2); 11056 jmp(done); 11057 11058 clear_vector_masking(); // closing of the stub context for programming mask registers 11059 } 11060 if (UseSSE42Intrinsics) { 11061 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11062 11063 movl(tmp2, len); 11064 11065 if (UseAVX > 1) { 11066 andl(tmp2, (16 - 1)); 11067 andl(len, -16); 11068 jccb(Assembler::zero, copy_new_tail); 11069 } else { 11070 andl(tmp2, 0x00000007); // tail count (in chars) 11071 andl(len, 0xfffffff8); // vector count (in chars) 11072 jccb(Assembler::zero, copy_tail); 11073 } 11074 11075 // vectored inflation 11076 lea(src, Address(src, len, Address::times_1)); 11077 lea(dst, Address(dst, len, Address::times_2)); 11078 negptr(len); 11079 11080 if (UseAVX > 1) { 11081 bind(copy_16_loop); 11082 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11083 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11084 addptr(len, 16); 11085 jcc(Assembler::notZero, copy_16_loop); 11086 11087 bind(below_threshold); 11088 bind(copy_new_tail); 11089 if ((UseAVX > 2) && 11090 VM_Version::supports_avx512vlbw() && 11091 VM_Version::supports_bmi2()) { 11092 movl(tmp2, len); 11093 } else { 11094 movl(len, tmp2); 11095 } 11096 andl(tmp2, 0x00000007); 11097 andl(len, 0xFFFFFFF8); 11098 jccb(Assembler::zero, copy_tail); 11099 11100 pmovzxbw(tmp1, Address(src, 0)); 11101 movdqu(Address(dst, 0), tmp1); 11102 addptr(src, 8); 11103 addptr(dst, 2 * 8); 11104 11105 jmp(copy_tail, true); 11106 } 11107 11108 // inflate 8 chars per iter 11109 bind(copy_8_loop); 11110 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11111 movdqu(Address(dst, len, Address::times_2), tmp1); 11112 addptr(len, 8); 11113 jcc(Assembler::notZero, copy_8_loop); 11114 11115 bind(copy_tail); 11116 movl(len, tmp2); 11117 11118 cmpl(len, 4); 11119 jccb(Assembler::less, copy_bytes); 11120 11121 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11122 pmovzxbw(tmp1, tmp1); 11123 movq(Address(dst, 0), tmp1); 11124 subptr(len, 4); 11125 addptr(src, 4); 11126 addptr(dst, 8); 11127 11128 bind(copy_bytes); 11129 } 11130 testl(len, len); 11131 jccb(Assembler::zero, done); 11132 lea(src, Address(src, len, Address::times_1)); 11133 lea(dst, Address(dst, len, Address::times_2)); 11134 negptr(len); 11135 11136 // inflate 1 char per iter 11137 bind(copy_chars_loop); 11138 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11139 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11140 increment(len); 11141 jcc(Assembler::notZero, copy_chars_loop); 11142 11143 bind(done); 11144 } 11145 11146 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11147 switch (cond) { 11148 // Note some conditions are synonyms for others 11149 case Assembler::zero: return Assembler::notZero; 11150 case Assembler::notZero: return Assembler::zero; 11151 case Assembler::less: return Assembler::greaterEqual; 11152 case Assembler::lessEqual: return Assembler::greater; 11153 case Assembler::greater: return Assembler::lessEqual; 11154 case Assembler::greaterEqual: return Assembler::less; 11155 case Assembler::below: return Assembler::aboveEqual; 11156 case Assembler::belowEqual: return Assembler::above; 11157 case Assembler::above: return Assembler::belowEqual; 11158 case Assembler::aboveEqual: return Assembler::below; 11159 case Assembler::overflow: return Assembler::noOverflow; 11160 case Assembler::noOverflow: return Assembler::overflow; 11161 case Assembler::negative: return Assembler::positive; 11162 case Assembler::positive: return Assembler::negative; 11163 case Assembler::parity: return Assembler::noParity; 11164 case Assembler::noParity: return Assembler::parity; 11165 } 11166 ShouldNotReachHere(); return Assembler::overflow; 11167 } 11168 11169 SkipIfEqual::SkipIfEqual( 11170 MacroAssembler* masm, const bool* flag_addr, bool value) { 11171 _masm = masm; 11172 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11173 _masm->jcc(Assembler::equal, _label); 11174 } 11175 11176 SkipIfEqual::~SkipIfEqual() { 11177 _masm->bind(_label); 11178 } 11179 11180 // 32-bit Windows has its own fast-path implementation 11181 // of get_thread 11182 #if !defined(WIN32) || defined(_LP64) 11183 11184 // This is simply a call to Thread::current() 11185 void MacroAssembler::get_thread(Register thread) { 11186 if (thread != rax) { 11187 push(rax); 11188 } 11189 LP64_ONLY(push(rdi);) 11190 LP64_ONLY(push(rsi);) 11191 push(rdx); 11192 push(rcx); 11193 #ifdef _LP64 11194 push(r8); 11195 push(r9); 11196 push(r10); 11197 push(r11); 11198 #endif 11199 11200 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11201 11202 #ifdef _LP64 11203 pop(r11); 11204 pop(r10); 11205 pop(r9); 11206 pop(r8); 11207 #endif 11208 pop(rcx); 11209 pop(rdx); 11210 LP64_ONLY(pop(rsi);) 11211 LP64_ONLY(pop(rdi);) 11212 if (thread != rax) { 11213 mov(thread, rax); 11214 pop(rax); 11215 } 11216 } 11217 11218 #endif