1 /* 2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "vmreg_x86.inline.hpp" 42 43 44 // These masks are used to provide 128-bit aligned bitmasks to the XMM 45 // instructions, to allow sign-masking or sign-bit flipping. They allow 46 // fast versions of NegF/NegD and AbsF/AbsD. 47 48 // Note: 'double' and 'long long' have 32-bits alignment on x86. 49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 51 // of 128-bits operands for SSE instructions. 52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 53 // Store the value to a 128-bits operand. 54 operand[0] = lo; 55 operand[1] = hi; 56 return operand; 57 } 58 59 // Buffer for 128-bits masks used by SSE instructions. 60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 61 62 // Static initialization during VM startup. 63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 67 68 69 70 NEEDS_CLEANUP // remove this definitions ? 71 const Register IC_Klass = rax; // where the IC klass is cached 72 const Register SYNC_header = rax; // synchronization header 73 const Register SHIFT_count = rcx; // where count for shift operations must be 74 75 #define __ _masm-> 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2) { 82 if (tmp1 == preserve) { 83 assert_different_registers(tmp1, tmp2, extra); 84 tmp1 = extra; 85 } else if (tmp2 == preserve) { 86 assert_different_registers(tmp1, tmp2, extra); 87 tmp2 = extra; 88 } 89 assert_different_registers(preserve, tmp1, tmp2); 90 } 91 92 93 94 static void select_different_registers(Register preserve, 95 Register extra, 96 Register &tmp1, 97 Register &tmp2, 98 Register &tmp3) { 99 if (tmp1 == preserve) { 100 assert_different_registers(tmp1, tmp2, tmp3, extra); 101 tmp1 = extra; 102 } else if (tmp2 == preserve) { 103 assert_different_registers(tmp1, tmp2, tmp3, extra); 104 tmp2 = extra; 105 } else if (tmp3 == preserve) { 106 assert_different_registers(tmp1, tmp2, tmp3, extra); 107 tmp3 = extra; 108 } 109 assert_different_registers(preserve, tmp1, tmp2, tmp3); 110 } 111 112 113 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 115 if (opr->is_constant()) { 116 LIR_Const* constant = opr->as_constant_ptr(); 117 switch (constant->type()) { 118 case T_INT: { 119 return true; 120 } 121 122 default: 123 return false; 124 } 125 } 126 return false; 127 } 128 129 130 LIR_Opr LIR_Assembler::receiverOpr() { 131 return FrameMap::receiver_opr; 132 } 133 134 LIR_Opr LIR_Assembler::osrBufferPointer() { 135 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 136 } 137 138 //--------------fpu register translations----------------------- 139 140 141 address LIR_Assembler::float_constant(float f) { 142 address const_addr = __ float_constant(f); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 address LIR_Assembler::double_constant(double d) { 153 address const_addr = __ double_constant(d); 154 if (const_addr == NULL) { 155 bailout("const section overflow"); 156 return __ code()->consts()->start(); 157 } else { 158 return const_addr; 159 } 160 } 161 162 163 void LIR_Assembler::set_24bit_FPU() { 164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 165 } 166 167 void LIR_Assembler::reset_FPU() { 168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 169 } 170 171 void LIR_Assembler::fpop() { 172 __ fpop(); 173 } 174 175 void LIR_Assembler::fxch(int i) { 176 __ fxch(i); 177 } 178 179 void LIR_Assembler::fld(int i) { 180 __ fld_s(i); 181 } 182 183 void LIR_Assembler::ffree(int i) { 184 __ ffree(i); 185 } 186 187 void LIR_Assembler::breakpoint() { 188 __ int3(); 189 } 190 191 void LIR_Assembler::push(LIR_Opr opr) { 192 if (opr->is_single_cpu()) { 193 __ push_reg(opr->as_register()); 194 } else if (opr->is_double_cpu()) { 195 NOT_LP64(__ push_reg(opr->as_register_hi())); 196 __ push_reg(opr->as_register_lo()); 197 } else if (opr->is_stack()) { 198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 199 } else if (opr->is_constant()) { 200 LIR_Const* const_opr = opr->as_constant_ptr(); 201 if (const_opr->type() == T_OBJECT) { 202 __ push_oop(const_opr->as_jobject()); 203 } else if (const_opr->type() == T_INT) { 204 __ push_jint(const_opr->as_jint()); 205 } else { 206 ShouldNotReachHere(); 207 } 208 209 } else { 210 ShouldNotReachHere(); 211 } 212 } 213 214 void LIR_Assembler::pop(LIR_Opr opr) { 215 if (opr->is_single_cpu()) { 216 __ pop_reg(opr->as_register()); 217 } else { 218 ShouldNotReachHere(); 219 } 220 } 221 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 223 return addr->base()->is_illegal() && addr->index()->is_illegal(); 224 } 225 226 //------------------------------------------- 227 228 Address LIR_Assembler::as_Address(LIR_Address* addr) { 229 return as_Address(addr, rscratch1); 230 } 231 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 233 if (addr->base()->is_illegal()) { 234 assert(addr->index()->is_illegal(), "must be illegal too"); 235 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 236 if (! __ reachable(laddr)) { 237 __ movptr(tmp, laddr.addr()); 238 Address res(tmp, 0); 239 return res; 240 } else { 241 return __ as_Address(laddr); 242 } 243 } 244 245 Register base = addr->base()->as_pointer_register(); 246 247 if (addr->index()->is_illegal()) { 248 return Address( base, addr->disp()); 249 } else if (addr->index()->is_cpu_register()) { 250 Register index = addr->index()->as_pointer_register(); 251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 252 } else if (addr->index()->is_constant()) { 253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 254 assert(Assembler::is_simm32(addr_offset), "must be"); 255 256 return Address(base, addr_offset); 257 } else { 258 Unimplemented(); 259 return Address(); 260 } 261 } 262 263 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 265 Address base = as_Address(addr); 266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 267 } 268 269 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 271 return as_Address(addr); 272 } 273 274 275 void LIR_Assembler::osr_entry() { 276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 277 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 278 ValueStack* entry_state = osr_entry->state(); 279 int number_of_locks = entry_state->locks_size(); 280 281 // we jump here if osr happens with the interpreter 282 // state set up to continue at the beginning of the 283 // loop that triggered osr - in particular, we have 284 // the following registers setup: 285 // 286 // rcx: osr buffer 287 // 288 289 // build frame 290 ciMethod* m = compilation()->method(); 291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 292 293 // OSR buffer is 294 // 295 // locals[nlocals-1..0] 296 // monitors[0..number_of_locks] 297 // 298 // locals is a direct copy of the interpreter frame so in the osr buffer 299 // so first slot in the local array is the last local from the interpreter 300 // and last slot is local[0] (receiver) from the interpreter 301 // 302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 304 // in the interpreter frame (the method lock if a sync method) 305 306 // Initialize monitors in the compiled activation. 307 // rcx: pointer to osr buffer 308 // 309 // All other registers are dead at this point and the locals will be 310 // copied into place by code emitted in the IR. 311 312 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 314 int monitor_offset = BytesPerWord * method()->max_locals() + 315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 317 // the OSR buffer using 2 word entries: first the lock and then 318 // the oop. 319 for (int i = 0; i < number_of_locks; i++) { 320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 321 #ifdef ASSERT 322 // verify the interpreter's monitor has a non-null object 323 { 324 Label L; 325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 326 __ jcc(Assembler::notZero, L); 327 __ stop("locked object is NULL"); 328 __ bind(L); 329 } 330 #endif 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 334 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 335 } 336 } 337 } 338 339 340 // inline cache check; done before the frame is built. 341 int LIR_Assembler::check_icache() { 342 Register receiver = FrameMap::receiver_opr->as_register(); 343 Register ic_klass = IC_Klass; 344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 346 if (!do_post_padding) { 347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 349 } 350 int offset = __ offset(); 351 __ inline_cache_check(receiver, IC_Klass); 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353 if (do_post_padding) { 354 // force alignment after the cache check. 355 // It's been verified to be aligned if !VerifyOops 356 __ align(CodeEntryAlignment); 357 } 358 return offset; 359 } 360 361 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363 jobject o = NULL; 364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 365 __ movoop(reg, o); 366 patching_epilog(patch, lir_patch_normal, reg, info); 367 } 368 369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 370 Metadata* o = NULL; 371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 372 __ mov_metadata(reg, o); 373 patching_epilog(patch, lir_patch_normal, reg, info); 374 } 375 376 // This specifies the rsp decrement needed to build the frame 377 int LIR_Assembler::initial_frame_size_in_bytes() const { 378 // if rounding, must let FrameMap know! 379 380 // The frame_map records size in slots (32bit word) 381 382 // subtract two words to account for return address and link 383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 384 } 385 386 387 int LIR_Assembler::emit_exception_handler() { 388 // if the last instruction is a call (typically to do a throw which 389 // is coming at the end after block reordering) the return address 390 // must still point into the code area in order to avoid assertion 391 // failures when searching for the corresponding bci => add a nop 392 // (was bug 5/14/1999 - gri) 393 __ nop(); 394 395 // generate code for exception handler 396 address handler_base = __ start_a_stub(exception_handler_size()); 397 if (handler_base == NULL) { 398 // not enough space left for the handler 399 bailout("exception handler overflow"); 400 return -1; 401 } 402 403 int offset = code_offset(); 404 405 // the exception oop and pc are in rax, and rdx 406 // no other registers need to be preserved, so invalidate them 407 __ invalidate_registers(false, true, true, false, true, true); 408 409 // check that there is really an exception 410 __ verify_not_null_oop(rax); 411 412 // search an exception handler (rax: exception oop, rdx: throwing pc) 413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 414 __ should_not_reach_here(); 415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 416 __ end_a_stub(); 417 418 return offset; 419 } 420 421 422 // Emit the code to remove the frame from the stack in the exception 423 // unwind path. 424 int LIR_Assembler::emit_unwind_handler() { 425 #ifndef PRODUCT 426 if (CommentedAssembly) { 427 _masm->block_comment("Unwind handler"); 428 } 429 #endif 430 431 int offset = code_offset(); 432 433 // Fetch the exception from TLS and clear out exception related thread state 434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 435 NOT_LP64(__ get_thread(rsi)); 436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 439 440 __ bind(_unwind_handler_entry); 441 __ verify_not_null_oop(rax); 442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 444 } 445 446 // Preform needed unlocking 447 MonitorExitStub* stub = NULL; 448 if (method()->is_synchronized()) { 449 monitor_address(0, FrameMap::rax_opr); 450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 451 __ unlock_object(rdi, rsi, rax, *stub->entry()); 452 __ bind(*stub->continuation()); 453 } 454 455 if (compilation()->env()->dtrace_method_probes()) { 456 #ifdef _LP64 457 __ mov(rdi, r15_thread); 458 __ mov_metadata(rsi, method()->constant_encoding()); 459 #else 460 __ get_thread(rax); 461 __ movptr(Address(rsp, 0), rax); 462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 463 #endif 464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 465 } 466 467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 468 __ mov(rax, rbx); // Restore the exception 469 } 470 471 // remove the activation and dispatch to the unwind handler 472 __ remove_frame(initial_frame_size_in_bytes()); 473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 474 475 // Emit the slow path assembly 476 if (stub != NULL) { 477 stub->emit_code(this); 478 } 479 480 return offset; 481 } 482 483 484 int LIR_Assembler::emit_deopt_handler() { 485 // if the last instruction is a call (typically to do a throw which 486 // is coming at the end after block reordering) the return address 487 // must still point into the code area in order to avoid assertion 488 // failures when searching for the corresponding bci => add a nop 489 // (was bug 5/14/1999 - gri) 490 __ nop(); 491 492 // generate code for exception handler 493 address handler_base = __ start_a_stub(deopt_handler_size()); 494 if (handler_base == NULL) { 495 // not enough space left for the handler 496 bailout("deopt handler overflow"); 497 return -1; 498 } 499 500 int offset = code_offset(); 501 InternalAddress here(__ pc()); 502 503 __ pushptr(here.addr()); 504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 506 __ end_a_stub(); 507 508 return offset; 509 } 510 511 512 void LIR_Assembler::return_op(LIR_Opr result) { 513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 515 assert(result->fpu() == 0, "result must already be on TOS"); 516 } 517 518 // Pop the stack before the safepoint code 519 __ remove_frame(initial_frame_size_in_bytes()); 520 521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 522 __ reserved_stack_check(); 523 } 524 525 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 530 531 if (Assembler::is_polling_page_far()) { 532 __ lea(rscratch1, polling_page); 533 __ relocate(relocInfo::poll_return_type); 534 __ testl(rax, Address(rscratch1, 0)); 535 } else { 536 __ testl(rax, polling_page); 537 } 538 __ ret(0); 539 } 540 541 542 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 544 guarantee(info != NULL, "Shouldn't be NULL"); 545 int offset = __ offset(); 546 if (Assembler::is_polling_page_far()) { 547 __ lea(rscratch1, polling_page); 548 offset = __ offset(); 549 add_debug_info_for_branch(info); 550 __ relocate(relocInfo::poll_type); 551 __ testl(rax, Address(rscratch1, 0)); 552 } else { 553 add_debug_info_for_branch(info); 554 __ testl(rax, polling_page); 555 } 556 return offset; 557 } 558 559 560 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 561 if (from_reg != to_reg) __ mov(to_reg, from_reg); 562 } 563 564 void LIR_Assembler::swap_reg(Register a, Register b) { 565 __ xchgptr(a, b); 566 } 567 568 569 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 570 assert(src->is_constant(), "should not call otherwise"); 571 assert(dest->is_register(), "should not call otherwise"); 572 LIR_Const* c = src->as_constant_ptr(); 573 574 switch (c->type()) { 575 case T_INT: { 576 assert(patch_code == lir_patch_none, "no patching handled here"); 577 __ movl(dest->as_register(), c->as_jint()); 578 break; 579 } 580 581 case T_ADDRESS: { 582 assert(patch_code == lir_patch_none, "no patching handled here"); 583 __ movptr(dest->as_register(), c->as_jint()); 584 break; 585 } 586 587 case T_LONG: { 588 assert(patch_code == lir_patch_none, "no patching handled here"); 589 #ifdef _LP64 590 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 591 #else 592 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 593 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 594 #endif // _LP64 595 break; 596 } 597 598 case T_OBJECT: { 599 if (patch_code != lir_patch_none) { 600 jobject2reg_with_patching(dest->as_register(), info); 601 } else { 602 __ movoop(dest->as_register(), c->as_jobject()); 603 } 604 break; 605 } 606 607 case T_METADATA: { 608 if (patch_code != lir_patch_none) { 609 klass2reg_with_patching(dest->as_register(), info); 610 } else { 611 __ mov_metadata(dest->as_register(), c->as_metadata()); 612 } 613 break; 614 } 615 616 case T_FLOAT: { 617 if (dest->is_single_xmm()) { 618 if (c->is_zero_float()) { 619 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 620 } else { 621 __ movflt(dest->as_xmm_float_reg(), 622 InternalAddress(float_constant(c->as_jfloat()))); 623 } 624 } else { 625 assert(dest->is_single_fpu(), "must be"); 626 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 627 if (c->is_zero_float()) { 628 __ fldz(); 629 } else if (c->is_one_float()) { 630 __ fld1(); 631 } else { 632 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 633 } 634 } 635 break; 636 } 637 638 case T_DOUBLE: { 639 if (dest->is_double_xmm()) { 640 if (c->is_zero_double()) { 641 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 642 } else { 643 __ movdbl(dest->as_xmm_double_reg(), 644 InternalAddress(double_constant(c->as_jdouble()))); 645 } 646 } else { 647 assert(dest->is_double_fpu(), "must be"); 648 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 649 if (c->is_zero_double()) { 650 __ fldz(); 651 } else if (c->is_one_double()) { 652 __ fld1(); 653 } else { 654 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 655 } 656 } 657 break; 658 } 659 660 default: 661 ShouldNotReachHere(); 662 } 663 } 664 665 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 666 assert(src->is_constant(), "should not call otherwise"); 667 assert(dest->is_stack(), "should not call otherwise"); 668 LIR_Const* c = src->as_constant_ptr(); 669 670 switch (c->type()) { 671 case T_INT: // fall through 672 case T_FLOAT: 673 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 674 break; 675 676 case T_ADDRESS: 677 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 678 break; 679 680 case T_OBJECT: 681 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 682 break; 683 684 case T_LONG: // fall through 685 case T_DOUBLE: 686 #ifdef _LP64 687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 688 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 689 #else 690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 691 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 692 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 693 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 694 #endif // _LP64 695 break; 696 697 default: 698 ShouldNotReachHere(); 699 } 700 } 701 702 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 703 assert(src->is_constant(), "should not call otherwise"); 704 assert(dest->is_address(), "should not call otherwise"); 705 LIR_Const* c = src->as_constant_ptr(); 706 LIR_Address* addr = dest->as_address_ptr(); 707 708 int null_check_here = code_offset(); 709 switch (type) { 710 case T_INT: // fall through 711 case T_FLOAT: 712 __ movl(as_Address(addr), c->as_jint_bits()); 713 break; 714 715 case T_ADDRESS: 716 __ movptr(as_Address(addr), c->as_jint_bits()); 717 break; 718 719 case T_OBJECT: // fall through 720 case T_ARRAY: 721 if (c->as_jobject() == NULL) { 722 if (UseCompressedOops && !wide) { 723 __ movl(as_Address(addr), (int32_t)NULL_WORD); 724 } else { 725 #ifdef _LP64 726 __ xorptr(rscratch1, rscratch1); 727 null_check_here = code_offset(); 728 __ movptr(as_Address(addr), rscratch1); 729 #else 730 __ movptr(as_Address(addr), NULL_WORD); 731 #endif 732 } 733 } else { 734 if (is_literal_address(addr)) { 735 ShouldNotReachHere(); 736 __ movoop(as_Address(addr, noreg), c->as_jobject()); 737 } else { 738 #ifdef _LP64 739 __ movoop(rscratch1, c->as_jobject()); 740 if (UseCompressedOops && !wide) { 741 __ encode_heap_oop(rscratch1); 742 null_check_here = code_offset(); 743 __ movl(as_Address_lo(addr), rscratch1); 744 } else { 745 null_check_here = code_offset(); 746 __ movptr(as_Address_lo(addr), rscratch1); 747 } 748 #else 749 __ movoop(as_Address(addr), c->as_jobject()); 750 #endif 751 } 752 } 753 break; 754 755 case T_LONG: // fall through 756 case T_DOUBLE: 757 #ifdef _LP64 758 if (is_literal_address(addr)) { 759 ShouldNotReachHere(); 760 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 761 } else { 762 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 763 null_check_here = code_offset(); 764 __ movptr(as_Address_lo(addr), r10); 765 } 766 #else 767 // Always reachable in 32bit so this doesn't produce useless move literal 768 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 769 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 770 #endif // _LP64 771 break; 772 773 case T_BOOLEAN: // fall through 774 case T_BYTE: 775 __ movb(as_Address(addr), c->as_jint() & 0xFF); 776 break; 777 778 case T_CHAR: // fall through 779 case T_SHORT: 780 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 781 break; 782 783 default: 784 ShouldNotReachHere(); 785 }; 786 787 if (info != NULL) { 788 add_debug_info_for_null_check(null_check_here, info); 789 } 790 } 791 792 793 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 794 assert(src->is_register(), "should not call otherwise"); 795 assert(dest->is_register(), "should not call otherwise"); 796 797 // move between cpu-registers 798 if (dest->is_single_cpu()) { 799 #ifdef _LP64 800 if (src->type() == T_LONG) { 801 // Can do LONG -> OBJECT 802 move_regs(src->as_register_lo(), dest->as_register()); 803 return; 804 } 805 #endif 806 assert(src->is_single_cpu(), "must match"); 807 if (src->type() == T_OBJECT) { 808 __ verify_oop(src->as_register()); 809 } 810 move_regs(src->as_register(), dest->as_register()); 811 812 } else if (dest->is_double_cpu()) { 813 #ifdef _LP64 814 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 815 // Surprising to me but we can see move of a long to t_object 816 __ verify_oop(src->as_register()); 817 move_regs(src->as_register(), dest->as_register_lo()); 818 return; 819 } 820 #endif 821 assert(src->is_double_cpu(), "must match"); 822 Register f_lo = src->as_register_lo(); 823 Register f_hi = src->as_register_hi(); 824 Register t_lo = dest->as_register_lo(); 825 Register t_hi = dest->as_register_hi(); 826 #ifdef _LP64 827 assert(f_hi == f_lo, "must be same"); 828 assert(t_hi == t_lo, "must be same"); 829 move_regs(f_lo, t_lo); 830 #else 831 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 832 833 834 if (f_lo == t_hi && f_hi == t_lo) { 835 swap_reg(f_lo, f_hi); 836 } else if (f_hi == t_lo) { 837 assert(f_lo != t_hi, "overwriting register"); 838 move_regs(f_hi, t_hi); 839 move_regs(f_lo, t_lo); 840 } else { 841 assert(f_hi != t_lo, "overwriting register"); 842 move_regs(f_lo, t_lo); 843 move_regs(f_hi, t_hi); 844 } 845 #endif // LP64 846 847 // special moves from fpu-register to xmm-register 848 // necessary for method results 849 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 850 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 851 __ fld_s(Address(rsp, 0)); 852 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 853 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 854 __ fld_d(Address(rsp, 0)); 855 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 856 __ fstp_s(Address(rsp, 0)); 857 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 858 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 859 __ fstp_d(Address(rsp, 0)); 860 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 861 862 // move between xmm-registers 863 } else if (dest->is_single_xmm()) { 864 assert(src->is_single_xmm(), "must match"); 865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 866 } else if (dest->is_double_xmm()) { 867 assert(src->is_double_xmm(), "must match"); 868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 869 870 // move between fpu-registers (no instruction necessary because of fpu-stack) 871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 874 } else { 875 ShouldNotReachHere(); 876 } 877 } 878 879 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 880 assert(src->is_register(), "should not call otherwise"); 881 assert(dest->is_stack(), "should not call otherwise"); 882 883 if (src->is_single_cpu()) { 884 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 885 if (type == T_OBJECT || type == T_ARRAY) { 886 __ verify_oop(src->as_register()); 887 __ movptr (dst, src->as_register()); 888 } else if (type == T_METADATA) { 889 __ movptr (dst, src->as_register()); 890 } else { 891 __ movl (dst, src->as_register()); 892 } 893 894 } else if (src->is_double_cpu()) { 895 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 896 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 897 __ movptr (dstLO, src->as_register_lo()); 898 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 899 900 } else if (src->is_single_xmm()) { 901 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 902 __ movflt(dst_addr, src->as_xmm_float_reg()); 903 904 } else if (src->is_double_xmm()) { 905 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 906 __ movdbl(dst_addr, src->as_xmm_double_reg()); 907 908 } else if (src->is_single_fpu()) { 909 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 910 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 911 if (pop_fpu_stack) __ fstp_s (dst_addr); 912 else __ fst_s (dst_addr); 913 914 } else if (src->is_double_fpu()) { 915 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 916 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 917 if (pop_fpu_stack) __ fstp_d (dst_addr); 918 else __ fst_d (dst_addr); 919 920 } else { 921 ShouldNotReachHere(); 922 } 923 } 924 925 926 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 927 LIR_Address* to_addr = dest->as_address_ptr(); 928 PatchingStub* patch = NULL; 929 Register compressed_src = rscratch1; 930 931 if (type == T_ARRAY || type == T_OBJECT) { 932 __ verify_oop(src->as_register()); 933 __ shenandoah_store_addr_check(as_Address(to_addr)); 934 __ shenandoah_store_val_check(as_Address(to_addr), src->as_register()); 935 #ifdef _LP64 936 if (UseCompressedOops && !wide) { 937 __ movptr(compressed_src, src->as_register()); 938 __ encode_heap_oop(compressed_src); 939 if (patch_code != lir_patch_none) { 940 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 941 } 942 } 943 #endif 944 } else { 945 __ shenandoah_store_addr_check(to_addr->base()->as_pointer_register()); 946 } 947 948 if (patch_code != lir_patch_none) { 949 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 950 Address toa = as_Address(to_addr); 951 assert(toa.disp() != 0, "must have"); 952 } 953 954 int null_check_here = code_offset(); 955 switch (type) { 956 case T_FLOAT: { 957 if (src->is_single_xmm()) { 958 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 959 } else { 960 assert(src->is_single_fpu(), "must be"); 961 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 962 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 963 else __ fst_s (as_Address(to_addr)); 964 } 965 break; 966 } 967 968 case T_DOUBLE: { 969 if (src->is_double_xmm()) { 970 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 971 } else { 972 assert(src->is_double_fpu(), "must be"); 973 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 974 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 975 else __ fst_d (as_Address(to_addr)); 976 } 977 break; 978 } 979 980 case T_ARRAY: // fall through 981 case T_OBJECT: // fall through 982 if (UseCompressedOops && !wide) { 983 __ movl(as_Address(to_addr), compressed_src); 984 } else { 985 __ movptr(as_Address(to_addr), src->as_register()); 986 } 987 break; 988 case T_METADATA: 989 // We get here to store a method pointer to the stack to pass to 990 // a dtrace runtime call. This can't work on 64 bit with 991 // compressed klass ptrs: T_METADATA can be a compressed klass 992 // ptr or a 64 bit method pointer. 993 LP64_ONLY(ShouldNotReachHere()); 994 __ movptr(as_Address(to_addr), src->as_register()); 995 break; 996 case T_ADDRESS: 997 __ movptr(as_Address(to_addr), src->as_register()); 998 break; 999 case T_INT: 1000 __ movl(as_Address(to_addr), src->as_register()); 1001 break; 1002 1003 case T_LONG: { 1004 Register from_lo = src->as_register_lo(); 1005 Register from_hi = src->as_register_hi(); 1006 #ifdef _LP64 1007 __ movptr(as_Address_lo(to_addr), from_lo); 1008 #else 1009 Register base = to_addr->base()->as_register(); 1010 Register index = noreg; 1011 if (to_addr->index()->is_register()) { 1012 index = to_addr->index()->as_register(); 1013 } 1014 if (base == from_lo || index == from_lo) { 1015 assert(base != from_hi, "can't be"); 1016 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1017 __ movl(as_Address_hi(to_addr), from_hi); 1018 if (patch != NULL) { 1019 patching_epilog(patch, lir_patch_high, base, info); 1020 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1021 patch_code = lir_patch_low; 1022 } 1023 __ movl(as_Address_lo(to_addr), from_lo); 1024 } else { 1025 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1026 __ movl(as_Address_lo(to_addr), from_lo); 1027 if (patch != NULL) { 1028 patching_epilog(patch, lir_patch_low, base, info); 1029 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1030 patch_code = lir_patch_high; 1031 } 1032 __ movl(as_Address_hi(to_addr), from_hi); 1033 } 1034 #endif // _LP64 1035 break; 1036 } 1037 1038 case T_BYTE: // fall through 1039 case T_BOOLEAN: { 1040 Register src_reg = src->as_register(); 1041 Address dst_addr = as_Address(to_addr); 1042 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1043 __ movb(dst_addr, src_reg); 1044 break; 1045 } 1046 1047 case T_CHAR: // fall through 1048 case T_SHORT: 1049 __ movw(as_Address(to_addr), src->as_register()); 1050 break; 1051 1052 default: 1053 ShouldNotReachHere(); 1054 } 1055 if (info != NULL) { 1056 add_debug_info_for_null_check(null_check_here, info); 1057 } 1058 1059 if (patch_code != lir_patch_none) { 1060 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1061 } 1062 } 1063 1064 1065 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1066 assert(src->is_stack(), "should not call otherwise"); 1067 assert(dest->is_register(), "should not call otherwise"); 1068 1069 if (dest->is_single_cpu()) { 1070 if (type == T_ARRAY || type == T_OBJECT) { 1071 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1072 __ verify_oop(dest->as_register()); 1073 } else if (type == T_METADATA) { 1074 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1075 } else { 1076 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1077 } 1078 1079 } else if (dest->is_double_cpu()) { 1080 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1081 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1082 __ movptr(dest->as_register_lo(), src_addr_LO); 1083 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1084 1085 } else if (dest->is_single_xmm()) { 1086 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1087 __ movflt(dest->as_xmm_float_reg(), src_addr); 1088 1089 } else if (dest->is_double_xmm()) { 1090 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1091 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1092 1093 } else if (dest->is_single_fpu()) { 1094 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1095 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1096 __ fld_s(src_addr); 1097 1098 } else if (dest->is_double_fpu()) { 1099 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1100 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1101 __ fld_d(src_addr); 1102 1103 } else { 1104 ShouldNotReachHere(); 1105 } 1106 } 1107 1108 1109 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1110 if (src->is_single_stack()) { 1111 if (type == T_OBJECT || type == T_ARRAY) { 1112 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1113 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1114 } else { 1115 #ifndef _LP64 1116 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1117 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1118 #else 1119 //no pushl on 64bits 1120 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1121 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1122 #endif 1123 } 1124 1125 } else if (src->is_double_stack()) { 1126 #ifdef _LP64 1127 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1128 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1129 #else 1130 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1131 // push and pop the part at src + wordSize, adding wordSize for the previous push 1132 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1133 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1134 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1135 #endif // _LP64 1136 1137 } else { 1138 ShouldNotReachHere(); 1139 } 1140 } 1141 1142 1143 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1144 assert(src->is_address(), "should not call otherwise"); 1145 assert(dest->is_register(), "should not call otherwise"); 1146 1147 LIR_Address* addr = src->as_address_ptr(); 1148 Address from_addr = as_Address(addr); 1149 1150 if (addr->base()->type() == T_OBJECT) { 1151 __ verify_oop(addr->base()->as_pointer_register()); 1152 } 1153 1154 switch (type) { 1155 case T_BOOLEAN: // fall through 1156 case T_BYTE: // fall through 1157 case T_CHAR: // fall through 1158 case T_SHORT: 1159 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1160 // on pre P6 processors we may get partial register stalls 1161 // so blow away the value of to_rinfo before loading a 1162 // partial word into it. Do it here so that it precedes 1163 // the potential patch point below. 1164 __ xorptr(dest->as_register(), dest->as_register()); 1165 } 1166 break; 1167 default: 1168 break; 1169 } 1170 1171 PatchingStub* patch = NULL; 1172 if (patch_code != lir_patch_none) { 1173 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1174 assert(from_addr.disp() != 0, "must have"); 1175 } 1176 if (info != NULL) { 1177 add_debug_info_for_null_check_here(info); 1178 } 1179 1180 switch (type) { 1181 case T_FLOAT: { 1182 if (dest->is_single_xmm()) { 1183 __ movflt(dest->as_xmm_float_reg(), from_addr); 1184 } else { 1185 assert(dest->is_single_fpu(), "must be"); 1186 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1187 __ fld_s(from_addr); 1188 } 1189 break; 1190 } 1191 1192 case T_DOUBLE: { 1193 if (dest->is_double_xmm()) { 1194 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1195 } else { 1196 assert(dest->is_double_fpu(), "must be"); 1197 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1198 __ fld_d(from_addr); 1199 } 1200 break; 1201 } 1202 1203 case T_OBJECT: // fall through 1204 case T_ARRAY: // fall through 1205 if (UseCompressedOops && !wide) { 1206 __ movl(dest->as_register(), from_addr); 1207 } else { 1208 __ movptr(dest->as_register(), from_addr); 1209 } 1210 break; 1211 1212 case T_ADDRESS: 1213 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1214 __ movl(dest->as_register(), from_addr); 1215 } else { 1216 __ movptr(dest->as_register(), from_addr); 1217 } 1218 break; 1219 case T_INT: 1220 __ movl(dest->as_register(), from_addr); 1221 break; 1222 1223 case T_LONG: { 1224 Register to_lo = dest->as_register_lo(); 1225 Register to_hi = dest->as_register_hi(); 1226 #ifdef _LP64 1227 __ movptr(to_lo, as_Address_lo(addr)); 1228 #else 1229 Register base = addr->base()->as_register(); 1230 Register index = noreg; 1231 if (addr->index()->is_register()) { 1232 index = addr->index()->as_register(); 1233 } 1234 if ((base == to_lo && index == to_hi) || 1235 (base == to_hi && index == to_lo)) { 1236 // addresses with 2 registers are only formed as a result of 1237 // array access so this code will never have to deal with 1238 // patches or null checks. 1239 assert(info == NULL && patch == NULL, "must be"); 1240 __ lea(to_hi, as_Address(addr)); 1241 __ movl(to_lo, Address(to_hi, 0)); 1242 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1243 } else if (base == to_lo || index == to_lo) { 1244 assert(base != to_hi, "can't be"); 1245 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1246 __ movl(to_hi, as_Address_hi(addr)); 1247 if (patch != NULL) { 1248 patching_epilog(patch, lir_patch_high, base, info); 1249 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1250 patch_code = lir_patch_low; 1251 } 1252 __ movl(to_lo, as_Address_lo(addr)); 1253 } else { 1254 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1255 __ movl(to_lo, as_Address_lo(addr)); 1256 if (patch != NULL) { 1257 patching_epilog(patch, lir_patch_low, base, info); 1258 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1259 patch_code = lir_patch_high; 1260 } 1261 __ movl(to_hi, as_Address_hi(addr)); 1262 } 1263 #endif // _LP64 1264 break; 1265 } 1266 1267 case T_BOOLEAN: // fall through 1268 case T_BYTE: { 1269 Register dest_reg = dest->as_register(); 1270 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1271 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1272 __ movsbl(dest_reg, from_addr); 1273 } else { 1274 __ movb(dest_reg, from_addr); 1275 __ shll(dest_reg, 24); 1276 __ sarl(dest_reg, 24); 1277 } 1278 break; 1279 } 1280 1281 case T_CHAR: { 1282 Register dest_reg = dest->as_register(); 1283 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1284 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1285 __ movzwl(dest_reg, from_addr); 1286 } else { 1287 __ movw(dest_reg, from_addr); 1288 } 1289 break; 1290 } 1291 1292 case T_SHORT: { 1293 Register dest_reg = dest->as_register(); 1294 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1295 __ movswl(dest_reg, from_addr); 1296 } else { 1297 __ movw(dest_reg, from_addr); 1298 __ shll(dest_reg, 16); 1299 __ sarl(dest_reg, 16); 1300 } 1301 break; 1302 } 1303 1304 default: 1305 ShouldNotReachHere(); 1306 } 1307 1308 if (patch != NULL) { 1309 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1310 } 1311 1312 if (type == T_ARRAY || type == T_OBJECT) { 1313 #ifdef _LP64 1314 if (UseCompressedOops && !wide) { 1315 __ decode_heap_oop(dest->as_register()); 1316 } 1317 #endif 1318 __ verify_oop(dest->as_register()); 1319 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1320 #ifdef _LP64 1321 if (UseCompressedClassPointers) { 1322 __ decode_klass_not_null(dest->as_register()); 1323 } 1324 #endif 1325 } 1326 } 1327 1328 1329 NEEDS_CLEANUP; // This could be static? 1330 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1331 int elem_size = type2aelembytes(type); 1332 switch (elem_size) { 1333 case 1: return Address::times_1; 1334 case 2: return Address::times_2; 1335 case 4: return Address::times_4; 1336 case 8: return Address::times_8; 1337 } 1338 ShouldNotReachHere(); 1339 return Address::no_scale; 1340 } 1341 1342 1343 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1344 switch (op->code()) { 1345 case lir_idiv: 1346 case lir_irem: 1347 arithmetic_idiv(op->code(), 1348 op->in_opr1(), 1349 op->in_opr2(), 1350 op->in_opr3(), 1351 op->result_opr(), 1352 op->info()); 1353 break; 1354 case lir_fmad: 1355 __ fmad(op->result_opr()->as_xmm_double_reg(), 1356 op->in_opr1()->as_xmm_double_reg(), 1357 op->in_opr2()->as_xmm_double_reg(), 1358 op->in_opr3()->as_xmm_double_reg()); 1359 break; 1360 case lir_fmaf: 1361 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1362 op->in_opr1()->as_xmm_float_reg(), 1363 op->in_opr2()->as_xmm_float_reg(), 1364 op->in_opr3()->as_xmm_float_reg()); 1365 break; 1366 default: ShouldNotReachHere(); break; 1367 } 1368 } 1369 1370 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1371 #ifdef ASSERT 1372 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1373 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1374 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1375 #endif 1376 1377 if (op->cond() == lir_cond_always) { 1378 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1379 __ jmp (*(op->label())); 1380 } else { 1381 Assembler::Condition acond = Assembler::zero; 1382 if (op->code() == lir_cond_float_branch) { 1383 assert(op->ublock() != NULL, "must have unordered successor"); 1384 __ jcc(Assembler::parity, *(op->ublock()->label())); 1385 switch(op->cond()) { 1386 case lir_cond_equal: acond = Assembler::equal; break; 1387 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1388 case lir_cond_less: acond = Assembler::below; break; 1389 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1390 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1391 case lir_cond_greater: acond = Assembler::above; break; 1392 default: ShouldNotReachHere(); 1393 } 1394 } else { 1395 switch (op->cond()) { 1396 case lir_cond_equal: acond = Assembler::equal; break; 1397 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1398 case lir_cond_less: acond = Assembler::less; break; 1399 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1400 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1401 case lir_cond_greater: acond = Assembler::greater; break; 1402 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1403 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1404 default: ShouldNotReachHere(); 1405 } 1406 } 1407 __ jcc(acond,*(op->label())); 1408 } 1409 } 1410 1411 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) { 1412 Label done; 1413 Register obj = op->in_opr()->as_register(); 1414 Register res = op->result_opr()->as_register(); 1415 1416 if (res != obj) { 1417 __ mov(res, obj); 1418 } 1419 1420 // Check for null. 1421 if (op->need_null_check()) { 1422 __ testptr(res, res); 1423 __ jcc(Assembler::zero, done); 1424 } 1425 1426 __ shenandoah_write_barrier(res); 1427 1428 __ bind(done); 1429 1430 } 1431 1432 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1433 LIR_Opr src = op->in_opr(); 1434 LIR_Opr dest = op->result_opr(); 1435 1436 switch (op->bytecode()) { 1437 case Bytecodes::_i2l: 1438 #ifdef _LP64 1439 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1440 #else 1441 move_regs(src->as_register(), dest->as_register_lo()); 1442 move_regs(src->as_register(), dest->as_register_hi()); 1443 __ sarl(dest->as_register_hi(), 31); 1444 #endif // LP64 1445 break; 1446 1447 case Bytecodes::_l2i: 1448 #ifdef _LP64 1449 __ movl(dest->as_register(), src->as_register_lo()); 1450 #else 1451 move_regs(src->as_register_lo(), dest->as_register()); 1452 #endif 1453 break; 1454 1455 case Bytecodes::_i2b: 1456 move_regs(src->as_register(), dest->as_register()); 1457 __ sign_extend_byte(dest->as_register()); 1458 break; 1459 1460 case Bytecodes::_i2c: 1461 move_regs(src->as_register(), dest->as_register()); 1462 __ andl(dest->as_register(), 0xFFFF); 1463 break; 1464 1465 case Bytecodes::_i2s: 1466 move_regs(src->as_register(), dest->as_register()); 1467 __ sign_extend_short(dest->as_register()); 1468 break; 1469 1470 1471 case Bytecodes::_f2d: 1472 case Bytecodes::_d2f: 1473 if (dest->is_single_xmm()) { 1474 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1475 } else if (dest->is_double_xmm()) { 1476 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1477 } else { 1478 assert(src->fpu() == dest->fpu(), "register must be equal"); 1479 // do nothing (float result is rounded later through spilling) 1480 } 1481 break; 1482 1483 case Bytecodes::_i2f: 1484 case Bytecodes::_i2d: 1485 if (dest->is_single_xmm()) { 1486 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1487 } else if (dest->is_double_xmm()) { 1488 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1489 } else { 1490 assert(dest->fpu() == 0, "result must be on TOS"); 1491 __ movl(Address(rsp, 0), src->as_register()); 1492 __ fild_s(Address(rsp, 0)); 1493 } 1494 break; 1495 1496 case Bytecodes::_f2i: 1497 case Bytecodes::_d2i: 1498 if (src->is_single_xmm()) { 1499 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1500 } else if (src->is_double_xmm()) { 1501 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1502 } else { 1503 assert(src->fpu() == 0, "input must be on TOS"); 1504 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1505 __ fist_s(Address(rsp, 0)); 1506 __ movl(dest->as_register(), Address(rsp, 0)); 1507 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1508 } 1509 1510 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1511 assert(op->stub() != NULL, "stub required"); 1512 __ cmpl(dest->as_register(), 0x80000000); 1513 __ jcc(Assembler::equal, *op->stub()->entry()); 1514 __ bind(*op->stub()->continuation()); 1515 break; 1516 1517 case Bytecodes::_l2f: 1518 case Bytecodes::_l2d: 1519 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1520 assert(dest->fpu() == 0, "result must be on TOS"); 1521 1522 __ movptr(Address(rsp, 0), src->as_register_lo()); 1523 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1524 __ fild_d(Address(rsp, 0)); 1525 // float result is rounded later through spilling 1526 break; 1527 1528 case Bytecodes::_f2l: 1529 case Bytecodes::_d2l: 1530 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1531 assert(src->fpu() == 0, "input must be on TOS"); 1532 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1533 1534 // instruction sequence too long to inline it here 1535 { 1536 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1537 } 1538 break; 1539 1540 default: ShouldNotReachHere(); 1541 } 1542 } 1543 1544 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1545 if (op->init_check()) { 1546 __ cmpb(Address(op->klass()->as_register(), 1547 InstanceKlass::init_state_offset()), 1548 InstanceKlass::fully_initialized); 1549 add_debug_info_for_null_check_here(op->stub()->info()); 1550 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1551 } 1552 __ allocate_object(op->obj()->as_register(), 1553 op->tmp1()->as_register(), 1554 op->tmp2()->as_register(), 1555 op->header_size(), 1556 op->object_size(), 1557 op->klass()->as_register(), 1558 *op->stub()->entry()); 1559 __ bind(*op->stub()->continuation()); 1560 } 1561 1562 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1563 Register len = op->len()->as_register(); 1564 LP64_ONLY( __ movslq(len, len); ) 1565 1566 if (UseSlowPath || 1567 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1568 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1569 __ jmp(*op->stub()->entry()); 1570 } else { 1571 Register tmp1 = op->tmp1()->as_register(); 1572 Register tmp2 = op->tmp2()->as_register(); 1573 Register tmp3 = op->tmp3()->as_register(); 1574 if (len == tmp1) { 1575 tmp1 = tmp3; 1576 } else if (len == tmp2) { 1577 tmp2 = tmp3; 1578 } else if (len == tmp3) { 1579 // everything is ok 1580 } else { 1581 __ mov(tmp3, len); 1582 } 1583 __ allocate_array(op->obj()->as_register(), 1584 len, 1585 tmp1, 1586 tmp2, 1587 arrayOopDesc::header_size(op->type()), 1588 array_element_size(op->type()), 1589 op->klass()->as_register(), 1590 *op->stub()->entry()); 1591 } 1592 __ bind(*op->stub()->continuation()); 1593 } 1594 1595 void LIR_Assembler::type_profile_helper(Register mdo, 1596 ciMethodData *md, ciProfileData *data, 1597 Register recv, Label* update_done) { 1598 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1599 Label next_test; 1600 // See if the receiver is receiver[n]. 1601 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1602 __ jccb(Assembler::notEqual, next_test); 1603 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1604 __ addptr(data_addr, DataLayout::counter_increment); 1605 __ jmp(*update_done); 1606 __ bind(next_test); 1607 } 1608 1609 // Didn't find receiver; find next empty slot and fill it in 1610 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1611 Label next_test; 1612 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1613 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1614 __ jccb(Assembler::notEqual, next_test); 1615 __ movptr(recv_addr, recv); 1616 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1617 __ jmp(*update_done); 1618 __ bind(next_test); 1619 } 1620 } 1621 1622 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1623 // we always need a stub for the failure case. 1624 CodeStub* stub = op->stub(); 1625 Register obj = op->object()->as_register(); 1626 Register k_RInfo = op->tmp1()->as_register(); 1627 Register klass_RInfo = op->tmp2()->as_register(); 1628 Register dst = op->result_opr()->as_register(); 1629 ciKlass* k = op->klass(); 1630 Register Rtmp1 = noreg; 1631 1632 // check if it needs to be profiled 1633 ciMethodData* md = NULL; 1634 ciProfileData* data = NULL; 1635 1636 if (op->should_profile()) { 1637 ciMethod* method = op->profiled_method(); 1638 assert(method != NULL, "Should have method"); 1639 int bci = op->profiled_bci(); 1640 md = method->method_data_or_null(); 1641 assert(md != NULL, "Sanity"); 1642 data = md->bci_to_data(bci); 1643 assert(data != NULL, "need data for type check"); 1644 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1645 } 1646 Label profile_cast_success, profile_cast_failure; 1647 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1648 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1649 1650 if (obj == k_RInfo) { 1651 k_RInfo = dst; 1652 } else if (obj == klass_RInfo) { 1653 klass_RInfo = dst; 1654 } 1655 if (k->is_loaded() && !UseCompressedClassPointers) { 1656 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1657 } else { 1658 Rtmp1 = op->tmp3()->as_register(); 1659 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1660 } 1661 1662 assert_different_registers(obj, k_RInfo, klass_RInfo); 1663 1664 __ cmpptr(obj, (int32_t)NULL_WORD); 1665 if (op->should_profile()) { 1666 Label not_null; 1667 __ jccb(Assembler::notEqual, not_null); 1668 // Object is null; update MDO and exit 1669 Register mdo = klass_RInfo; 1670 __ mov_metadata(mdo, md->constant_encoding()); 1671 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1672 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1673 __ orl(data_addr, header_bits); 1674 __ jmp(*obj_is_null); 1675 __ bind(not_null); 1676 } else { 1677 __ jcc(Assembler::equal, *obj_is_null); 1678 } 1679 1680 if (!k->is_loaded()) { 1681 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1682 } else { 1683 #ifdef _LP64 1684 __ mov_metadata(k_RInfo, k->constant_encoding()); 1685 #endif // _LP64 1686 } 1687 __ verify_oop(obj); 1688 1689 if (op->fast_check()) { 1690 // get object class 1691 // not a safepoint as obj null check happens earlier 1692 #ifdef _LP64 1693 if (UseCompressedClassPointers) { 1694 __ load_klass(Rtmp1, obj); 1695 __ cmpptr(k_RInfo, Rtmp1); 1696 } else { 1697 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1698 } 1699 #else 1700 if (k->is_loaded()) { 1701 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1702 } else { 1703 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1704 } 1705 #endif 1706 __ jcc(Assembler::notEqual, *failure_target); 1707 // successful cast, fall through to profile or jump 1708 } else { 1709 // get object class 1710 // not a safepoint as obj null check happens earlier 1711 __ load_klass(klass_RInfo, obj); 1712 if (k->is_loaded()) { 1713 // See if we get an immediate positive hit 1714 #ifdef _LP64 1715 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1716 #else 1717 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1718 #endif // _LP64 1719 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1720 __ jcc(Assembler::notEqual, *failure_target); 1721 // successful cast, fall through to profile or jump 1722 } else { 1723 // See if we get an immediate positive hit 1724 __ jcc(Assembler::equal, *success_target); 1725 // check for self 1726 #ifdef _LP64 1727 __ cmpptr(klass_RInfo, k_RInfo); 1728 #else 1729 __ cmpklass(klass_RInfo, k->constant_encoding()); 1730 #endif // _LP64 1731 __ jcc(Assembler::equal, *success_target); 1732 1733 __ push(klass_RInfo); 1734 #ifdef _LP64 1735 __ push(k_RInfo); 1736 #else 1737 __ pushklass(k->constant_encoding()); 1738 #endif // _LP64 1739 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1740 __ pop(klass_RInfo); 1741 __ pop(klass_RInfo); 1742 // result is a boolean 1743 __ cmpl(klass_RInfo, 0); 1744 __ jcc(Assembler::equal, *failure_target); 1745 // successful cast, fall through to profile or jump 1746 } 1747 } else { 1748 // perform the fast part of the checking logic 1749 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1750 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1751 __ push(klass_RInfo); 1752 __ push(k_RInfo); 1753 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1754 __ pop(klass_RInfo); 1755 __ pop(k_RInfo); 1756 // result is a boolean 1757 __ cmpl(k_RInfo, 0); 1758 __ jcc(Assembler::equal, *failure_target); 1759 // successful cast, fall through to profile or jump 1760 } 1761 } 1762 if (op->should_profile()) { 1763 Register mdo = klass_RInfo, recv = k_RInfo; 1764 __ bind(profile_cast_success); 1765 __ mov_metadata(mdo, md->constant_encoding()); 1766 __ load_klass(recv, obj); 1767 Label update_done; 1768 type_profile_helper(mdo, md, data, recv, success); 1769 __ jmp(*success); 1770 1771 __ bind(profile_cast_failure); 1772 __ mov_metadata(mdo, md->constant_encoding()); 1773 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1774 __ subptr(counter_addr, DataLayout::counter_increment); 1775 __ jmp(*failure); 1776 } 1777 __ jmp(*success); 1778 } 1779 1780 1781 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1782 LIR_Code code = op->code(); 1783 if (code == lir_store_check) { 1784 Register value = op->object()->as_register(); 1785 Register array = op->array()->as_register(); 1786 Register k_RInfo = op->tmp1()->as_register(); 1787 Register klass_RInfo = op->tmp2()->as_register(); 1788 Register Rtmp1 = op->tmp3()->as_register(); 1789 1790 CodeStub* stub = op->stub(); 1791 1792 // check if it needs to be profiled 1793 ciMethodData* md = NULL; 1794 ciProfileData* data = NULL; 1795 1796 if (op->should_profile()) { 1797 ciMethod* method = op->profiled_method(); 1798 assert(method != NULL, "Should have method"); 1799 int bci = op->profiled_bci(); 1800 md = method->method_data_or_null(); 1801 assert(md != NULL, "Sanity"); 1802 data = md->bci_to_data(bci); 1803 assert(data != NULL, "need data for type check"); 1804 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1805 } 1806 Label profile_cast_success, profile_cast_failure, done; 1807 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1808 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1809 1810 __ cmpptr(value, (int32_t)NULL_WORD); 1811 if (op->should_profile()) { 1812 Label not_null; 1813 __ jccb(Assembler::notEqual, not_null); 1814 // Object is null; update MDO and exit 1815 Register mdo = klass_RInfo; 1816 __ mov_metadata(mdo, md->constant_encoding()); 1817 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1818 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1819 __ orl(data_addr, header_bits); 1820 __ jmp(done); 1821 __ bind(not_null); 1822 } else { 1823 __ jcc(Assembler::equal, done); 1824 } 1825 1826 add_debug_info_for_null_check_here(op->info_for_exception()); 1827 __ load_klass(k_RInfo, array); 1828 __ load_klass(klass_RInfo, value); 1829 1830 // get instance klass (it's already uncompressed) 1831 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1832 // perform the fast part of the checking logic 1833 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1834 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1835 __ push(klass_RInfo); 1836 __ push(k_RInfo); 1837 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1838 __ pop(klass_RInfo); 1839 __ pop(k_RInfo); 1840 // result is a boolean 1841 __ cmpl(k_RInfo, 0); 1842 __ jcc(Assembler::equal, *failure_target); 1843 // fall through to the success case 1844 1845 if (op->should_profile()) { 1846 Register mdo = klass_RInfo, recv = k_RInfo; 1847 __ bind(profile_cast_success); 1848 __ mov_metadata(mdo, md->constant_encoding()); 1849 __ load_klass(recv, value); 1850 Label update_done; 1851 type_profile_helper(mdo, md, data, recv, &done); 1852 __ jmpb(done); 1853 1854 __ bind(profile_cast_failure); 1855 __ mov_metadata(mdo, md->constant_encoding()); 1856 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1857 __ subptr(counter_addr, DataLayout::counter_increment); 1858 __ jmp(*stub->entry()); 1859 } 1860 1861 __ bind(done); 1862 } else 1863 if (code == lir_checkcast) { 1864 Register obj = op->object()->as_register(); 1865 Register dst = op->result_opr()->as_register(); 1866 Label success; 1867 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1868 __ bind(success); 1869 if (dst != obj) { 1870 __ mov(dst, obj); 1871 } 1872 } else 1873 if (code == lir_instanceof) { 1874 Register obj = op->object()->as_register(); 1875 Register dst = op->result_opr()->as_register(); 1876 Label success, failure, done; 1877 emit_typecheck_helper(op, &success, &failure, &failure); 1878 __ bind(failure); 1879 __ xorptr(dst, dst); 1880 __ jmpb(done); 1881 __ bind(success); 1882 __ movptr(dst, 1); 1883 __ bind(done); 1884 } else { 1885 ShouldNotReachHere(); 1886 } 1887 1888 } 1889 1890 1891 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1892 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1893 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1894 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1895 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1896 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1897 Register addr = op->addr()->as_register(); 1898 if (os::is_MP()) { 1899 __ lock(); 1900 } 1901 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1902 1903 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1904 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1905 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1906 Register newval = op->new_value()->as_register(); 1907 Register cmpval = op->cmp_value()->as_register(); 1908 assert(cmpval == rax, "wrong register"); 1909 assert(newval != NULL, "new val must be register"); 1910 assert(cmpval != newval, "cmp and new values must be in different registers"); 1911 assert(cmpval != addr, "cmp and addr must be in different registers"); 1912 assert(newval != addr, "new value and addr must be in different registers"); 1913 1914 if ( op->code() == lir_cas_obj) { 1915 #ifdef _LP64 1916 if (UseCompressedOops) { 1917 if (UseShenandoahGC && ShenandoahCASBarrier) { 1918 Register tmp1 = op->tmp1()->as_register(); 1919 Register tmp2 = op->tmp2()->as_register(); 1920 1921 __ encode_heap_oop(cmpval); 1922 __ mov(rscratch1, newval); 1923 __ encode_heap_oop(rscratch1); 1924 __ cmpxchg_oop_shenandoah(NULL, Address(addr, 0), cmpval, rscratch1, true, tmp1, tmp2); 1925 } else { 1926 __ encode_heap_oop(cmpval); 1927 __ mov(rscratch1, newval); 1928 __ encode_heap_oop(rscratch1); 1929 if (os::is_MP()) { 1930 __ lock(); 1931 } 1932 // cmpval (rax) is implicitly used by this instruction 1933 __ cmpxchgl(rscratch1, Address(addr, 0)); 1934 } 1935 } else 1936 #endif 1937 { 1938 if (UseShenandoahGC && ShenandoahCASBarrier) { 1939 Register tmp1 = op->tmp1()->as_register(); 1940 Register tmp2 = op->tmp2()->as_register(); 1941 __ cmpxchg_oop_shenandoah(NULL, Address(addr, 0), cmpval, newval, true, tmp1, tmp2); 1942 } else { 1943 if (os::is_MP()) { 1944 __ lock(); 1945 } 1946 __ cmpxchgptr(newval, Address(addr, 0)); 1947 } 1948 } 1949 } else { 1950 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1951 if (os::is_MP()) { 1952 __ lock(); 1953 } 1954 __ cmpxchgl(newval, Address(addr, 0)); 1955 } 1956 #ifdef _LP64 1957 } else if (op->code() == lir_cas_long) { 1958 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1959 Register newval = op->new_value()->as_register_lo(); 1960 Register cmpval = op->cmp_value()->as_register_lo(); 1961 assert(cmpval == rax, "wrong register"); 1962 assert(newval != NULL, "new val must be register"); 1963 assert(cmpval != newval, "cmp and new values must be in different registers"); 1964 assert(cmpval != addr, "cmp and addr must be in different registers"); 1965 assert(newval != addr, "new value and addr must be in different registers"); 1966 if (os::is_MP()) { 1967 __ lock(); 1968 } 1969 __ cmpxchgq(newval, Address(addr, 0)); 1970 #endif // _LP64 1971 } else { 1972 Unimplemented(); 1973 } 1974 } 1975 1976 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1977 Assembler::Condition acond, ncond; 1978 switch (condition) { 1979 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1980 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1981 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1982 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1983 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1984 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1985 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1986 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1987 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1988 ShouldNotReachHere(); 1989 } 1990 1991 if (opr1->is_cpu_register()) { 1992 reg2reg(opr1, result); 1993 } else if (opr1->is_stack()) { 1994 stack2reg(opr1, result, result->type()); 1995 } else if (opr1->is_constant()) { 1996 const2reg(opr1, result, lir_patch_none, NULL); 1997 } else { 1998 ShouldNotReachHere(); 1999 } 2000 2001 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2002 // optimized version that does not require a branch 2003 if (opr2->is_single_cpu()) { 2004 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2005 __ cmov(ncond, result->as_register(), opr2->as_register()); 2006 } else if (opr2->is_double_cpu()) { 2007 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2008 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2009 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2011 } else if (opr2->is_single_stack()) { 2012 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2013 } else if (opr2->is_double_stack()) { 2014 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2015 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2016 } else { 2017 ShouldNotReachHere(); 2018 } 2019 2020 } else { 2021 Label skip; 2022 __ jcc (acond, skip); 2023 if (opr2->is_cpu_register()) { 2024 reg2reg(opr2, result); 2025 } else if (opr2->is_stack()) { 2026 stack2reg(opr2, result, result->type()); 2027 } else if (opr2->is_constant()) { 2028 const2reg(opr2, result, lir_patch_none, NULL); 2029 } else { 2030 ShouldNotReachHere(); 2031 } 2032 __ bind(skip); 2033 } 2034 } 2035 2036 2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2038 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2039 2040 if (left->is_single_cpu()) { 2041 assert(left == dest, "left and dest must be equal"); 2042 Register lreg = left->as_register(); 2043 2044 if (right->is_single_cpu()) { 2045 // cpu register - cpu register 2046 Register rreg = right->as_register(); 2047 switch (code) { 2048 case lir_add: __ addl (lreg, rreg); break; 2049 case lir_sub: __ subl (lreg, rreg); break; 2050 case lir_mul: __ imull(lreg, rreg); break; 2051 default: ShouldNotReachHere(); 2052 } 2053 2054 } else if (right->is_stack()) { 2055 // cpu register - stack 2056 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2057 switch (code) { 2058 case lir_add: __ addl(lreg, raddr); break; 2059 case lir_sub: __ subl(lreg, raddr); break; 2060 default: ShouldNotReachHere(); 2061 } 2062 2063 } else if (right->is_constant()) { 2064 // cpu register - constant 2065 jint c = right->as_constant_ptr()->as_jint(); 2066 switch (code) { 2067 case lir_add: { 2068 __ incrementl(lreg, c); 2069 break; 2070 } 2071 case lir_sub: { 2072 __ decrementl(lreg, c); 2073 break; 2074 } 2075 default: ShouldNotReachHere(); 2076 } 2077 2078 } else { 2079 ShouldNotReachHere(); 2080 } 2081 2082 } else if (left->is_double_cpu()) { 2083 assert(left == dest, "left and dest must be equal"); 2084 Register lreg_lo = left->as_register_lo(); 2085 Register lreg_hi = left->as_register_hi(); 2086 2087 if (right->is_double_cpu()) { 2088 // cpu register - cpu register 2089 Register rreg_lo = right->as_register_lo(); 2090 Register rreg_hi = right->as_register_hi(); 2091 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2092 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2093 switch (code) { 2094 case lir_add: 2095 __ addptr(lreg_lo, rreg_lo); 2096 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2097 break; 2098 case lir_sub: 2099 __ subptr(lreg_lo, rreg_lo); 2100 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2101 break; 2102 case lir_mul: 2103 #ifdef _LP64 2104 __ imulq(lreg_lo, rreg_lo); 2105 #else 2106 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2107 __ imull(lreg_hi, rreg_lo); 2108 __ imull(rreg_hi, lreg_lo); 2109 __ addl (rreg_hi, lreg_hi); 2110 __ mull (rreg_lo); 2111 __ addl (lreg_hi, rreg_hi); 2112 #endif // _LP64 2113 break; 2114 default: 2115 ShouldNotReachHere(); 2116 } 2117 2118 } else if (right->is_constant()) { 2119 // cpu register - constant 2120 #ifdef _LP64 2121 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2122 __ movptr(r10, (intptr_t) c); 2123 switch (code) { 2124 case lir_add: 2125 __ addptr(lreg_lo, r10); 2126 break; 2127 case lir_sub: 2128 __ subptr(lreg_lo, r10); 2129 break; 2130 default: 2131 ShouldNotReachHere(); 2132 } 2133 #else 2134 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2135 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2136 switch (code) { 2137 case lir_add: 2138 __ addptr(lreg_lo, c_lo); 2139 __ adcl(lreg_hi, c_hi); 2140 break; 2141 case lir_sub: 2142 __ subptr(lreg_lo, c_lo); 2143 __ sbbl(lreg_hi, c_hi); 2144 break; 2145 default: 2146 ShouldNotReachHere(); 2147 } 2148 #endif // _LP64 2149 2150 } else { 2151 ShouldNotReachHere(); 2152 } 2153 2154 } else if (left->is_single_xmm()) { 2155 assert(left == dest, "left and dest must be equal"); 2156 XMMRegister lreg = left->as_xmm_float_reg(); 2157 2158 if (right->is_single_xmm()) { 2159 XMMRegister rreg = right->as_xmm_float_reg(); 2160 switch (code) { 2161 case lir_add: __ addss(lreg, rreg); break; 2162 case lir_sub: __ subss(lreg, rreg); break; 2163 case lir_mul_strictfp: // fall through 2164 case lir_mul: __ mulss(lreg, rreg); break; 2165 case lir_div_strictfp: // fall through 2166 case lir_div: __ divss(lreg, rreg); break; 2167 default: ShouldNotReachHere(); 2168 } 2169 } else { 2170 Address raddr; 2171 if (right->is_single_stack()) { 2172 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2173 } else if (right->is_constant()) { 2174 // hack for now 2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2176 } else { 2177 ShouldNotReachHere(); 2178 } 2179 switch (code) { 2180 case lir_add: __ addss(lreg, raddr); break; 2181 case lir_sub: __ subss(lreg, raddr); break; 2182 case lir_mul_strictfp: // fall through 2183 case lir_mul: __ mulss(lreg, raddr); break; 2184 case lir_div_strictfp: // fall through 2185 case lir_div: __ divss(lreg, raddr); break; 2186 default: ShouldNotReachHere(); 2187 } 2188 } 2189 2190 } else if (left->is_double_xmm()) { 2191 assert(left == dest, "left and dest must be equal"); 2192 2193 XMMRegister lreg = left->as_xmm_double_reg(); 2194 if (right->is_double_xmm()) { 2195 XMMRegister rreg = right->as_xmm_double_reg(); 2196 switch (code) { 2197 case lir_add: __ addsd(lreg, rreg); break; 2198 case lir_sub: __ subsd(lreg, rreg); break; 2199 case lir_mul_strictfp: // fall through 2200 case lir_mul: __ mulsd(lreg, rreg); break; 2201 case lir_div_strictfp: // fall through 2202 case lir_div: __ divsd(lreg, rreg); break; 2203 default: ShouldNotReachHere(); 2204 } 2205 } else { 2206 Address raddr; 2207 if (right->is_double_stack()) { 2208 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2209 } else if (right->is_constant()) { 2210 // hack for now 2211 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2212 } else { 2213 ShouldNotReachHere(); 2214 } 2215 switch (code) { 2216 case lir_add: __ addsd(lreg, raddr); break; 2217 case lir_sub: __ subsd(lreg, raddr); break; 2218 case lir_mul_strictfp: // fall through 2219 case lir_mul: __ mulsd(lreg, raddr); break; 2220 case lir_div_strictfp: // fall through 2221 case lir_div: __ divsd(lreg, raddr); break; 2222 default: ShouldNotReachHere(); 2223 } 2224 } 2225 2226 } else if (left->is_single_fpu()) { 2227 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2228 2229 if (right->is_single_fpu()) { 2230 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2231 2232 } else { 2233 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2234 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2235 2236 Address raddr; 2237 if (right->is_single_stack()) { 2238 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2239 } else if (right->is_constant()) { 2240 address const_addr = float_constant(right->as_jfloat()); 2241 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2242 // hack for now 2243 raddr = __ as_Address(InternalAddress(const_addr)); 2244 } else { 2245 ShouldNotReachHere(); 2246 } 2247 2248 switch (code) { 2249 case lir_add: __ fadd_s(raddr); break; 2250 case lir_sub: __ fsub_s(raddr); break; 2251 case lir_mul_strictfp: // fall through 2252 case lir_mul: __ fmul_s(raddr); break; 2253 case lir_div_strictfp: // fall through 2254 case lir_div: __ fdiv_s(raddr); break; 2255 default: ShouldNotReachHere(); 2256 } 2257 } 2258 2259 } else if (left->is_double_fpu()) { 2260 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2261 2262 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2263 // Double values require special handling for strictfp mul/div on x86 2264 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2265 __ fmulp(left->fpu_regnrLo() + 1); 2266 } 2267 2268 if (right->is_double_fpu()) { 2269 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2270 2271 } else { 2272 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2273 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2274 2275 Address raddr; 2276 if (right->is_double_stack()) { 2277 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2278 } else if (right->is_constant()) { 2279 // hack for now 2280 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2281 } else { 2282 ShouldNotReachHere(); 2283 } 2284 2285 switch (code) { 2286 case lir_add: __ fadd_d(raddr); break; 2287 case lir_sub: __ fsub_d(raddr); break; 2288 case lir_mul_strictfp: // fall through 2289 case lir_mul: __ fmul_d(raddr); break; 2290 case lir_div_strictfp: // fall through 2291 case lir_div: __ fdiv_d(raddr); break; 2292 default: ShouldNotReachHere(); 2293 } 2294 } 2295 2296 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2297 // Double values require special handling for strictfp mul/div on x86 2298 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2299 __ fmulp(dest->fpu_regnrLo() + 1); 2300 } 2301 2302 } else if (left->is_single_stack() || left->is_address()) { 2303 assert(left == dest, "left and dest must be equal"); 2304 2305 Address laddr; 2306 if (left->is_single_stack()) { 2307 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2308 } else if (left->is_address()) { 2309 laddr = as_Address(left->as_address_ptr()); 2310 } else { 2311 ShouldNotReachHere(); 2312 } 2313 2314 if (right->is_single_cpu()) { 2315 Register rreg = right->as_register(); 2316 switch (code) { 2317 case lir_add: __ addl(laddr, rreg); break; 2318 case lir_sub: __ subl(laddr, rreg); break; 2319 default: ShouldNotReachHere(); 2320 } 2321 } else if (right->is_constant()) { 2322 jint c = right->as_constant_ptr()->as_jint(); 2323 switch (code) { 2324 case lir_add: { 2325 __ incrementl(laddr, c); 2326 break; 2327 } 2328 case lir_sub: { 2329 __ decrementl(laddr, c); 2330 break; 2331 } 2332 default: ShouldNotReachHere(); 2333 } 2334 } else { 2335 ShouldNotReachHere(); 2336 } 2337 2338 } else { 2339 ShouldNotReachHere(); 2340 } 2341 } 2342 2343 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2344 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2345 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2346 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2347 2348 bool left_is_tos = (left_index == 0); 2349 bool dest_is_tos = (dest_index == 0); 2350 int non_tos_index = (left_is_tos ? right_index : left_index); 2351 2352 switch (code) { 2353 case lir_add: 2354 if (pop_fpu_stack) __ faddp(non_tos_index); 2355 else if (dest_is_tos) __ fadd (non_tos_index); 2356 else __ fadda(non_tos_index); 2357 break; 2358 2359 case lir_sub: 2360 if (left_is_tos) { 2361 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2362 else if (dest_is_tos) __ fsub (non_tos_index); 2363 else __ fsubra(non_tos_index); 2364 } else { 2365 if (pop_fpu_stack) __ fsubp (non_tos_index); 2366 else if (dest_is_tos) __ fsubr (non_tos_index); 2367 else __ fsuba (non_tos_index); 2368 } 2369 break; 2370 2371 case lir_mul_strictfp: // fall through 2372 case lir_mul: 2373 if (pop_fpu_stack) __ fmulp(non_tos_index); 2374 else if (dest_is_tos) __ fmul (non_tos_index); 2375 else __ fmula(non_tos_index); 2376 break; 2377 2378 case lir_div_strictfp: // fall through 2379 case lir_div: 2380 if (left_is_tos) { 2381 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2382 else if (dest_is_tos) __ fdiv (non_tos_index); 2383 else __ fdivra(non_tos_index); 2384 } else { 2385 if (pop_fpu_stack) __ fdivp (non_tos_index); 2386 else if (dest_is_tos) __ fdivr (non_tos_index); 2387 else __ fdiva (non_tos_index); 2388 } 2389 break; 2390 2391 case lir_rem: 2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2393 __ fremr(noreg); 2394 break; 2395 2396 default: 2397 ShouldNotReachHere(); 2398 } 2399 } 2400 2401 2402 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2403 if (value->is_double_xmm()) { 2404 switch(code) { 2405 case lir_abs : 2406 { 2407 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2408 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2409 } 2410 __ andpd(dest->as_xmm_double_reg(), 2411 ExternalAddress((address)double_signmask_pool)); 2412 } 2413 break; 2414 2415 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2416 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2417 default : ShouldNotReachHere(); 2418 } 2419 2420 } else if (value->is_double_fpu()) { 2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2422 switch(code) { 2423 case lir_abs : __ fabs() ; break; 2424 case lir_sqrt : __ fsqrt(); break; 2425 default : ShouldNotReachHere(); 2426 } 2427 } else { 2428 Unimplemented(); 2429 } 2430 } 2431 2432 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2433 // assert(left->destroys_register(), "check"); 2434 if (left->is_single_cpu()) { 2435 Register reg = left->as_register(); 2436 if (right->is_constant()) { 2437 int val = right->as_constant_ptr()->as_jint(); 2438 switch (code) { 2439 case lir_logic_and: __ andl (reg, val); break; 2440 case lir_logic_or: __ orl (reg, val); break; 2441 case lir_logic_xor: __ xorl (reg, val); break; 2442 default: ShouldNotReachHere(); 2443 } 2444 } else if (right->is_stack()) { 2445 // added support for stack operands 2446 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2447 switch (code) { 2448 case lir_logic_and: __ andl (reg, raddr); break; 2449 case lir_logic_or: __ orl (reg, raddr); break; 2450 case lir_logic_xor: __ xorl (reg, raddr); break; 2451 default: ShouldNotReachHere(); 2452 } 2453 } else { 2454 Register rright = right->as_register(); 2455 switch (code) { 2456 case lir_logic_and: __ andptr (reg, rright); break; 2457 case lir_logic_or : __ orptr (reg, rright); break; 2458 case lir_logic_xor: __ xorptr (reg, rright); break; 2459 default: ShouldNotReachHere(); 2460 } 2461 } 2462 move_regs(reg, dst->as_register()); 2463 } else { 2464 Register l_lo = left->as_register_lo(); 2465 Register l_hi = left->as_register_hi(); 2466 if (right->is_constant()) { 2467 #ifdef _LP64 2468 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2469 switch (code) { 2470 case lir_logic_and: 2471 __ andq(l_lo, rscratch1); 2472 break; 2473 case lir_logic_or: 2474 __ orq(l_lo, rscratch1); 2475 break; 2476 case lir_logic_xor: 2477 __ xorq(l_lo, rscratch1); 2478 break; 2479 default: ShouldNotReachHere(); 2480 } 2481 #else 2482 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2483 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2484 switch (code) { 2485 case lir_logic_and: 2486 __ andl(l_lo, r_lo); 2487 __ andl(l_hi, r_hi); 2488 break; 2489 case lir_logic_or: 2490 __ orl(l_lo, r_lo); 2491 __ orl(l_hi, r_hi); 2492 break; 2493 case lir_logic_xor: 2494 __ xorl(l_lo, r_lo); 2495 __ xorl(l_hi, r_hi); 2496 break; 2497 default: ShouldNotReachHere(); 2498 } 2499 #endif // _LP64 2500 } else { 2501 #ifdef _LP64 2502 Register r_lo; 2503 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2504 r_lo = right->as_register(); 2505 } else { 2506 r_lo = right->as_register_lo(); 2507 } 2508 #else 2509 Register r_lo = right->as_register_lo(); 2510 Register r_hi = right->as_register_hi(); 2511 assert(l_lo != r_hi, "overwriting registers"); 2512 #endif 2513 switch (code) { 2514 case lir_logic_and: 2515 __ andptr(l_lo, r_lo); 2516 NOT_LP64(__ andptr(l_hi, r_hi);) 2517 break; 2518 case lir_logic_or: 2519 __ orptr(l_lo, r_lo); 2520 NOT_LP64(__ orptr(l_hi, r_hi);) 2521 break; 2522 case lir_logic_xor: 2523 __ xorptr(l_lo, r_lo); 2524 NOT_LP64(__ xorptr(l_hi, r_hi);) 2525 break; 2526 default: ShouldNotReachHere(); 2527 } 2528 } 2529 2530 Register dst_lo = dst->as_register_lo(); 2531 Register dst_hi = dst->as_register_hi(); 2532 2533 #ifdef _LP64 2534 move_regs(l_lo, dst_lo); 2535 #else 2536 if (dst_lo == l_hi) { 2537 assert(dst_hi != l_lo, "overwriting registers"); 2538 move_regs(l_hi, dst_hi); 2539 move_regs(l_lo, dst_lo); 2540 } else { 2541 assert(dst_lo != l_hi, "overwriting registers"); 2542 move_regs(l_lo, dst_lo); 2543 move_regs(l_hi, dst_hi); 2544 } 2545 #endif // _LP64 2546 } 2547 } 2548 2549 2550 // we assume that rax, and rdx can be overwritten 2551 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2552 2553 assert(left->is_single_cpu(), "left must be register"); 2554 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2555 assert(result->is_single_cpu(), "result must be register"); 2556 2557 // assert(left->destroys_register(), "check"); 2558 // assert(right->destroys_register(), "check"); 2559 2560 Register lreg = left->as_register(); 2561 Register dreg = result->as_register(); 2562 2563 if (right->is_constant()) { 2564 int divisor = right->as_constant_ptr()->as_jint(); 2565 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2566 if (code == lir_idiv) { 2567 assert(lreg == rax, "must be rax,"); 2568 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2569 __ cdql(); // sign extend into rdx:rax 2570 if (divisor == 2) { 2571 __ subl(lreg, rdx); 2572 } else { 2573 __ andl(rdx, divisor - 1); 2574 __ addl(lreg, rdx); 2575 } 2576 __ sarl(lreg, log2_intptr(divisor)); 2577 move_regs(lreg, dreg); 2578 } else if (code == lir_irem) { 2579 Label done; 2580 __ mov(dreg, lreg); 2581 __ andl(dreg, 0x80000000 | (divisor - 1)); 2582 __ jcc(Assembler::positive, done); 2583 __ decrement(dreg); 2584 __ orl(dreg, ~(divisor - 1)); 2585 __ increment(dreg); 2586 __ bind(done); 2587 } else { 2588 ShouldNotReachHere(); 2589 } 2590 } else { 2591 Register rreg = right->as_register(); 2592 assert(lreg == rax, "left register must be rax,"); 2593 assert(rreg != rdx, "right register must not be rdx"); 2594 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2595 2596 move_regs(lreg, rax); 2597 2598 int idivl_offset = __ corrected_idivl(rreg); 2599 add_debug_info_for_div0(idivl_offset, info); 2600 if (code == lir_irem) { 2601 move_regs(rdx, dreg); // result is in rdx 2602 } else { 2603 move_regs(rax, dreg); 2604 } 2605 } 2606 } 2607 2608 2609 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2610 if (opr1->is_single_cpu()) { 2611 Register reg1 = opr1->as_register(); 2612 if (opr2->is_single_cpu()) { 2613 // cpu register - cpu register 2614 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2615 __ cmpptr(reg1, opr2->as_register()); 2616 oopDesc::bs()->asm_acmp_barrier(masm(), reg1, opr2->as_register()); 2617 } else { 2618 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2619 __ cmpl(reg1, opr2->as_register()); 2620 } 2621 } else if (opr2->is_stack()) { 2622 // cpu register - stack 2623 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2624 if (UseShenandoahGC && ShenandoahAcmpBarrier) { 2625 __ movptr(rscratch1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2626 __ cmpptr(reg1, rscratch1); 2627 oopDesc::bs()->asm_acmp_barrier(masm(), reg1, rscratch1); 2628 } else { 2629 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2630 } 2631 } else { 2632 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2633 } 2634 } else if (opr2->is_constant()) { 2635 // cpu register - constant 2636 LIR_Const* c = opr2->as_constant_ptr(); 2637 if (c->type() == T_INT) { 2638 __ cmpl(reg1, c->as_jint()); 2639 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2640 // In 64bit oops are single register 2641 jobject o = c->as_jobject(); 2642 if (o == NULL) { 2643 __ cmpptr(reg1, (int32_t)NULL_WORD); 2644 } else { 2645 #ifdef _LP64 2646 __ movoop(rscratch1, o); 2647 __ cmpptr(reg1, rscratch1); 2648 oopDesc::bs()->asm_acmp_barrier(masm(), reg1, rscratch1); 2649 #else 2650 __ cmpoop(reg1, c->as_jobject()); 2651 #endif // _LP64 2652 } 2653 } else { 2654 fatal("unexpected type: %s", basictype_to_str(c->type())); 2655 } 2656 // cpu register - address 2657 } else if (opr2->is_address()) { 2658 if (op->info() != NULL) { 2659 add_debug_info_for_null_check_here(op->info()); 2660 } 2661 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2662 } else { 2663 ShouldNotReachHere(); 2664 } 2665 2666 } else if(opr1->is_double_cpu()) { 2667 Register xlo = opr1->as_register_lo(); 2668 Register xhi = opr1->as_register_hi(); 2669 if (opr2->is_double_cpu()) { 2670 #ifdef _LP64 2671 __ cmpptr(xlo, opr2->as_register_lo()); 2672 #else 2673 // cpu register - cpu register 2674 Register ylo = opr2->as_register_lo(); 2675 Register yhi = opr2->as_register_hi(); 2676 __ subl(xlo, ylo); 2677 __ sbbl(xhi, yhi); 2678 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2679 __ orl(xhi, xlo); 2680 } 2681 #endif // _LP64 2682 } else if (opr2->is_constant()) { 2683 // cpu register - constant 0 2684 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2685 #ifdef _LP64 2686 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2687 #else 2688 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2689 __ orl(xhi, xlo); 2690 #endif // _LP64 2691 } else { 2692 ShouldNotReachHere(); 2693 } 2694 2695 } else if (opr1->is_single_xmm()) { 2696 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2697 if (opr2->is_single_xmm()) { 2698 // xmm register - xmm register 2699 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2700 } else if (opr2->is_stack()) { 2701 // xmm register - stack 2702 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2703 } else if (opr2->is_constant()) { 2704 // xmm register - constant 2705 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2706 } else if (opr2->is_address()) { 2707 // xmm register - address 2708 if (op->info() != NULL) { 2709 add_debug_info_for_null_check_here(op->info()); 2710 } 2711 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2712 } else { 2713 ShouldNotReachHere(); 2714 } 2715 2716 } else if (opr1->is_double_xmm()) { 2717 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2718 if (opr2->is_double_xmm()) { 2719 // xmm register - xmm register 2720 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2721 } else if (opr2->is_stack()) { 2722 // xmm register - stack 2723 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2724 } else if (opr2->is_constant()) { 2725 // xmm register - constant 2726 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2727 } else if (opr2->is_address()) { 2728 // xmm register - address 2729 if (op->info() != NULL) { 2730 add_debug_info_for_null_check_here(op->info()); 2731 } 2732 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2733 } else { 2734 ShouldNotReachHere(); 2735 } 2736 2737 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2738 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2739 assert(opr2->is_fpu_register(), "both must be registers"); 2740 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2741 2742 } else if (opr1->is_address() && opr2->is_constant()) { 2743 LIR_Const* c = opr2->as_constant_ptr(); 2744 #ifdef _LP64 2745 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2746 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2747 __ movoop(rscratch1, c->as_jobject()); 2748 } 2749 #endif // LP64 2750 if (op->info() != NULL) { 2751 add_debug_info_for_null_check_here(op->info()); 2752 } 2753 // special case: address - constant 2754 LIR_Address* addr = opr1->as_address_ptr(); 2755 if (c->type() == T_INT) { 2756 __ cmpl(as_Address(addr), c->as_jint()); 2757 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2758 #ifdef _LP64 2759 // %%% Make this explode if addr isn't reachable until we figure out a 2760 // better strategy by giving noreg as the temp for as_Address 2761 if (UseShenandoahGC && ShenandoahAcmpBarrier) { 2762 __ movptr(rscratch2, as_Address(addr, noreg)); 2763 __ cmpptr(rscratch1, rscratch2); 2764 oopDesc::bs()->asm_acmp_barrier(masm(), rscratch1, rscratch2); 2765 } else { 2766 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2767 } 2768 #else 2769 __ cmpoop(as_Address(addr), c->as_jobject()); 2770 #endif // _LP64 2771 } else { 2772 ShouldNotReachHere(); 2773 } 2774 2775 } else { 2776 ShouldNotReachHere(); 2777 } 2778 } 2779 2780 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2781 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2782 if (left->is_single_xmm()) { 2783 assert(right->is_single_xmm(), "must match"); 2784 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2785 } else if (left->is_double_xmm()) { 2786 assert(right->is_double_xmm(), "must match"); 2787 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2788 2789 } else { 2790 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2791 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2792 2793 assert(left->fpu() == 0, "left must be on TOS"); 2794 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2795 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2796 } 2797 } else { 2798 assert(code == lir_cmp_l2i, "check"); 2799 #ifdef _LP64 2800 Label done; 2801 Register dest = dst->as_register(); 2802 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2803 __ movl(dest, -1); 2804 __ jccb(Assembler::less, done); 2805 __ set_byte_if_not_zero(dest); 2806 __ movzbl(dest, dest); 2807 __ bind(done); 2808 #else 2809 __ lcmp2int(left->as_register_hi(), 2810 left->as_register_lo(), 2811 right->as_register_hi(), 2812 right->as_register_lo()); 2813 move_regs(left->as_register_hi(), dst->as_register()); 2814 #endif // _LP64 2815 } 2816 } 2817 2818 2819 void LIR_Assembler::align_call(LIR_Code code) { 2820 if (os::is_MP()) { 2821 // make sure that the displacement word of the call ends up word aligned 2822 int offset = __ offset(); 2823 switch (code) { 2824 case lir_static_call: 2825 case lir_optvirtual_call: 2826 case lir_dynamic_call: 2827 offset += NativeCall::displacement_offset; 2828 break; 2829 case lir_icvirtual_call: 2830 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2831 break; 2832 case lir_virtual_call: // currently, sparc-specific for niagara 2833 default: ShouldNotReachHere(); 2834 } 2835 __ align(BytesPerWord, offset); 2836 } 2837 } 2838 2839 2840 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2841 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2842 "must be aligned"); 2843 __ call(AddressLiteral(op->addr(), rtype)); 2844 add_call_info(code_offset(), op->info()); 2845 } 2846 2847 2848 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2849 __ ic_call(op->addr()); 2850 add_call_info(code_offset(), op->info()); 2851 assert(!os::is_MP() || 2852 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2853 "must be aligned"); 2854 } 2855 2856 2857 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2858 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2859 ShouldNotReachHere(); 2860 } 2861 2862 2863 void LIR_Assembler::emit_static_call_stub() { 2864 address call_pc = __ pc(); 2865 address stub = __ start_a_stub(call_stub_size()); 2866 if (stub == NULL) { 2867 bailout("static call stub overflow"); 2868 return; 2869 } 2870 2871 int start = __ offset(); 2872 if (os::is_MP()) { 2873 // make sure that the displacement word of the call ends up word aligned 2874 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2875 } 2876 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2877 __ mov_metadata(rbx, (Metadata*)NULL); 2878 // must be set to -1 at code generation time 2879 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2880 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2881 __ jump(RuntimeAddress(__ pc())); 2882 2883 if (UseAOT) { 2884 // Trampoline to aot code 2885 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2886 #ifdef _LP64 2887 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2888 #else 2889 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2890 #endif 2891 __ jmp(rax); 2892 } 2893 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2894 __ end_a_stub(); 2895 } 2896 2897 2898 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2899 assert(exceptionOop->as_register() == rax, "must match"); 2900 assert(exceptionPC->as_register() == rdx, "must match"); 2901 2902 // exception object is not added to oop map by LinearScan 2903 // (LinearScan assumes that no oops are in fixed registers) 2904 info->add_register_oop(exceptionOop); 2905 Runtime1::StubID unwind_id; 2906 2907 // get current pc information 2908 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2909 int pc_for_athrow_offset = __ offset(); 2910 InternalAddress pc_for_athrow(__ pc()); 2911 __ lea(exceptionPC->as_register(), pc_for_athrow); 2912 add_call_info(pc_for_athrow_offset, info); // for exception handler 2913 2914 __ verify_not_null_oop(rax); 2915 // search an exception handler (rax: exception oop, rdx: throwing pc) 2916 if (compilation()->has_fpu_code()) { 2917 unwind_id = Runtime1::handle_exception_id; 2918 } else { 2919 unwind_id = Runtime1::handle_exception_nofpu_id; 2920 } 2921 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2922 2923 // enough room for two byte trap 2924 __ nop(); 2925 } 2926 2927 2928 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2929 assert(exceptionOop->as_register() == rax, "must match"); 2930 2931 __ jmp(_unwind_handler_entry); 2932 } 2933 2934 2935 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2936 2937 // optimized version for linear scan: 2938 // * count must be already in ECX (guaranteed by LinearScan) 2939 // * left and dest must be equal 2940 // * tmp must be unused 2941 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2942 assert(left == dest, "left and dest must be equal"); 2943 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2944 2945 if (left->is_single_cpu()) { 2946 Register value = left->as_register(); 2947 assert(value != SHIFT_count, "left cannot be ECX"); 2948 2949 switch (code) { 2950 case lir_shl: __ shll(value); break; 2951 case lir_shr: __ sarl(value); break; 2952 case lir_ushr: __ shrl(value); break; 2953 default: ShouldNotReachHere(); 2954 } 2955 } else if (left->is_double_cpu()) { 2956 Register lo = left->as_register_lo(); 2957 Register hi = left->as_register_hi(); 2958 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2959 #ifdef _LP64 2960 switch (code) { 2961 case lir_shl: __ shlptr(lo); break; 2962 case lir_shr: __ sarptr(lo); break; 2963 case lir_ushr: __ shrptr(lo); break; 2964 default: ShouldNotReachHere(); 2965 } 2966 #else 2967 2968 switch (code) { 2969 case lir_shl: __ lshl(hi, lo); break; 2970 case lir_shr: __ lshr(hi, lo, true); break; 2971 case lir_ushr: __ lshr(hi, lo, false); break; 2972 default: ShouldNotReachHere(); 2973 } 2974 #endif // LP64 2975 } else { 2976 ShouldNotReachHere(); 2977 } 2978 } 2979 2980 2981 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2982 if (dest->is_single_cpu()) { 2983 // first move left into dest so that left is not destroyed by the shift 2984 Register value = dest->as_register(); 2985 count = count & 0x1F; // Java spec 2986 2987 move_regs(left->as_register(), value); 2988 switch (code) { 2989 case lir_shl: __ shll(value, count); break; 2990 case lir_shr: __ sarl(value, count); break; 2991 case lir_ushr: __ shrl(value, count); break; 2992 default: ShouldNotReachHere(); 2993 } 2994 } else if (dest->is_double_cpu()) { 2995 #ifndef _LP64 2996 Unimplemented(); 2997 #else 2998 // first move left into dest so that left is not destroyed by the shift 2999 Register value = dest->as_register_lo(); 3000 count = count & 0x1F; // Java spec 3001 3002 move_regs(left->as_register_lo(), value); 3003 switch (code) { 3004 case lir_shl: __ shlptr(value, count); break; 3005 case lir_shr: __ sarptr(value, count); break; 3006 case lir_ushr: __ shrptr(value, count); break; 3007 default: ShouldNotReachHere(); 3008 } 3009 #endif // _LP64 3010 } else { 3011 ShouldNotReachHere(); 3012 } 3013 } 3014 3015 3016 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3017 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3018 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3019 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3020 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3021 } 3022 3023 3024 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3025 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3026 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3027 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3028 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3029 } 3030 3031 3032 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3033 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3034 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3035 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3036 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3037 } 3038 3039 3040 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3041 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3042 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3043 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3044 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3045 } 3046 3047 3048 // This code replaces a call to arraycopy; no exception may 3049 // be thrown in this code, they must be thrown in the System.arraycopy 3050 // activation frame; we could save some checks if this would not be the case 3051 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3052 ciArrayKlass* default_type = op->expected_type(); 3053 Register src = op->src()->as_register(); 3054 Register dst = op->dst()->as_register(); 3055 Register src_pos = op->src_pos()->as_register(); 3056 Register dst_pos = op->dst_pos()->as_register(); 3057 Register length = op->length()->as_register(); 3058 Register tmp = op->tmp()->as_register(); 3059 3060 CodeStub* stub = op->stub(); 3061 int flags = op->flags(); 3062 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3063 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3064 3065 // if we don't know anything, just go through the generic arraycopy 3066 if (default_type == NULL) { 3067 Label done; 3068 // save outgoing arguments on stack in case call to System.arraycopy is needed 3069 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3070 // for interpreter calling conventions. Now we have to do it in new style conventions. 3071 // For the moment until C1 gets the new register allocator I just force all the 3072 // args to the right place (except the register args) and then on the back side 3073 // reload the register args properly if we go slow path. Yuck 3074 3075 // These are proper for the calling convention 3076 store_parameter(length, 2); 3077 store_parameter(dst_pos, 1); 3078 store_parameter(dst, 0); 3079 3080 // these are just temporary placements until we need to reload 3081 store_parameter(src_pos, 3); 3082 store_parameter(src, 4); 3083 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3084 3085 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3086 3087 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3088 3089 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3090 #ifdef _LP64 3091 // The arguments are in java calling convention so we can trivially shift them to C 3092 // convention 3093 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3094 __ mov(c_rarg0, j_rarg0); 3095 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3096 __ mov(c_rarg1, j_rarg1); 3097 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3098 __ mov(c_rarg2, j_rarg2); 3099 assert_different_registers(c_rarg3, j_rarg4); 3100 __ mov(c_rarg3, j_rarg3); 3101 #ifdef _WIN64 3102 // Allocate abi space for args but be sure to keep stack aligned 3103 __ subptr(rsp, 6*wordSize); 3104 store_parameter(j_rarg4, 4); 3105 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3106 __ call(RuntimeAddress(C_entry)); 3107 } else { 3108 #ifndef PRODUCT 3109 if (PrintC1Statistics) { 3110 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3111 } 3112 #endif 3113 __ call(RuntimeAddress(copyfunc_addr)); 3114 } 3115 __ addptr(rsp, 6*wordSize); 3116 #else 3117 __ mov(c_rarg4, j_rarg4); 3118 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3119 __ call(RuntimeAddress(C_entry)); 3120 } else { 3121 #ifndef PRODUCT 3122 if (PrintC1Statistics) { 3123 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3124 } 3125 #endif 3126 __ call(RuntimeAddress(copyfunc_addr)); 3127 } 3128 #endif // _WIN64 3129 #else 3130 __ push(length); 3131 __ push(dst_pos); 3132 __ push(dst); 3133 __ push(src_pos); 3134 __ push(src); 3135 3136 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3137 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3138 } else { 3139 #ifndef PRODUCT 3140 if (PrintC1Statistics) { 3141 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3142 } 3143 #endif 3144 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3145 } 3146 3147 #endif // _LP64 3148 3149 __ cmpl(rax, 0); 3150 __ jcc(Assembler::equal, *stub->continuation()); 3151 3152 if (copyfunc_addr != NULL) { 3153 __ mov(tmp, rax); 3154 __ xorl(tmp, -1); 3155 } 3156 3157 // Reload values from the stack so they are where the stub 3158 // expects them. 3159 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3160 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3161 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3162 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3163 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3164 3165 if (copyfunc_addr != NULL) { 3166 __ subl(length, tmp); 3167 __ addl(src_pos, tmp); 3168 __ addl(dst_pos, tmp); 3169 } 3170 __ jmp(*stub->entry()); 3171 3172 __ bind(*stub->continuation()); 3173 return; 3174 } 3175 3176 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3177 3178 int elem_size = type2aelembytes(basic_type); 3179 Address::ScaleFactor scale; 3180 3181 switch (elem_size) { 3182 case 1 : 3183 scale = Address::times_1; 3184 break; 3185 case 2 : 3186 scale = Address::times_2; 3187 break; 3188 case 4 : 3189 scale = Address::times_4; 3190 break; 3191 case 8 : 3192 scale = Address::times_8; 3193 break; 3194 default: 3195 scale = Address::no_scale; 3196 ShouldNotReachHere(); 3197 } 3198 3199 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3200 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3201 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3202 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3203 3204 // length and pos's are all sign extended at this point on 64bit 3205 3206 // test for NULL 3207 if (flags & LIR_OpArrayCopy::src_null_check) { 3208 __ testptr(src, src); 3209 __ jcc(Assembler::zero, *stub->entry()); 3210 } 3211 if (flags & LIR_OpArrayCopy::dst_null_check) { 3212 __ testptr(dst, dst); 3213 __ jcc(Assembler::zero, *stub->entry()); 3214 } 3215 3216 // If the compiler was not able to prove that exact type of the source or the destination 3217 // of the arraycopy is an array type, check at runtime if the source or the destination is 3218 // an instance type. 3219 if (flags & LIR_OpArrayCopy::type_check) { 3220 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3221 __ load_klass(tmp, dst); 3222 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3223 __ jcc(Assembler::greaterEqual, *stub->entry()); 3224 } 3225 3226 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3227 __ load_klass(tmp, src); 3228 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3229 __ jcc(Assembler::greaterEqual, *stub->entry()); 3230 } 3231 } 3232 3233 // check if negative 3234 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3235 __ testl(src_pos, src_pos); 3236 __ jcc(Assembler::less, *stub->entry()); 3237 } 3238 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3239 __ testl(dst_pos, dst_pos); 3240 __ jcc(Assembler::less, *stub->entry()); 3241 } 3242 3243 if (flags & LIR_OpArrayCopy::src_range_check) { 3244 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3245 __ cmpl(tmp, src_length_addr); 3246 __ jcc(Assembler::above, *stub->entry()); 3247 } 3248 if (flags & LIR_OpArrayCopy::dst_range_check) { 3249 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3250 __ cmpl(tmp, dst_length_addr); 3251 __ jcc(Assembler::above, *stub->entry()); 3252 } 3253 3254 if (flags & LIR_OpArrayCopy::length_positive_check) { 3255 __ testl(length, length); 3256 __ jcc(Assembler::less, *stub->entry()); 3257 } 3258 3259 #ifdef _LP64 3260 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3261 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3262 #endif 3263 3264 if (flags & LIR_OpArrayCopy::type_check) { 3265 // We don't know the array types are compatible 3266 if (basic_type != T_OBJECT) { 3267 // Simple test for basic type arrays 3268 if (UseCompressedClassPointers) { 3269 __ movl(tmp, src_klass_addr); 3270 __ cmpl(tmp, dst_klass_addr); 3271 } else { 3272 __ movptr(tmp, src_klass_addr); 3273 __ cmpptr(tmp, dst_klass_addr); 3274 } 3275 __ jcc(Assembler::notEqual, *stub->entry()); 3276 } else { 3277 // For object arrays, if src is a sub class of dst then we can 3278 // safely do the copy. 3279 Label cont, slow; 3280 3281 __ push(src); 3282 __ push(dst); 3283 3284 __ load_klass(src, src); 3285 __ load_klass(dst, dst); 3286 3287 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3288 3289 __ push(src); 3290 __ push(dst); 3291 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3292 __ pop(dst); 3293 __ pop(src); 3294 3295 __ cmpl(src, 0); 3296 __ jcc(Assembler::notEqual, cont); 3297 3298 __ bind(slow); 3299 __ pop(dst); 3300 __ pop(src); 3301 3302 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3303 if (copyfunc_addr != NULL) { // use stub if available 3304 // src is not a sub class of dst so we have to do a 3305 // per-element check. 3306 3307 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3308 if ((flags & mask) != mask) { 3309 // Check that at least both of them object arrays. 3310 assert(flags & mask, "one of the two should be known to be an object array"); 3311 3312 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3313 __ load_klass(tmp, src); 3314 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3315 __ load_klass(tmp, dst); 3316 } 3317 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3318 Address klass_lh_addr(tmp, lh_offset); 3319 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3320 __ cmpl(klass_lh_addr, objArray_lh); 3321 __ jcc(Assembler::notEqual, *stub->entry()); 3322 } 3323 3324 // Spill because stubs can use any register they like and it's 3325 // easier to restore just those that we care about. 3326 store_parameter(dst, 0); 3327 store_parameter(dst_pos, 1); 3328 store_parameter(length, 2); 3329 store_parameter(src_pos, 3); 3330 store_parameter(src, 4); 3331 3332 #ifndef _LP64 3333 __ movptr(tmp, dst_klass_addr); 3334 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3335 __ push(tmp); 3336 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3337 __ push(tmp); 3338 __ push(length); 3339 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3340 __ push(tmp); 3341 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3342 __ push(tmp); 3343 3344 __ call_VM_leaf(copyfunc_addr, 5); 3345 #else 3346 __ movl2ptr(length, length); //higher 32bits must be null 3347 3348 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3349 assert_different_registers(c_rarg0, dst, dst_pos, length); 3350 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3351 assert_different_registers(c_rarg1, dst, length); 3352 3353 __ mov(c_rarg2, length); 3354 assert_different_registers(c_rarg2, dst); 3355 3356 #ifdef _WIN64 3357 // Allocate abi space for args but be sure to keep stack aligned 3358 __ subptr(rsp, 6*wordSize); 3359 __ load_klass(c_rarg3, dst); 3360 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3361 store_parameter(c_rarg3, 4); 3362 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3363 __ call(RuntimeAddress(copyfunc_addr)); 3364 __ addptr(rsp, 6*wordSize); 3365 #else 3366 __ load_klass(c_rarg4, dst); 3367 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3368 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3369 __ call(RuntimeAddress(copyfunc_addr)); 3370 #endif 3371 3372 #endif 3373 3374 #ifndef PRODUCT 3375 if (PrintC1Statistics) { 3376 Label failed; 3377 __ testl(rax, rax); 3378 __ jcc(Assembler::notZero, failed); 3379 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3380 __ bind(failed); 3381 } 3382 #endif 3383 3384 __ testl(rax, rax); 3385 __ jcc(Assembler::zero, *stub->continuation()); 3386 3387 #ifndef PRODUCT 3388 if (PrintC1Statistics) { 3389 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3390 } 3391 #endif 3392 3393 __ mov(tmp, rax); 3394 3395 __ xorl(tmp, -1); 3396 3397 // Restore previously spilled arguments 3398 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3399 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3400 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3401 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3402 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3403 3404 3405 __ subl(length, tmp); 3406 __ addl(src_pos, tmp); 3407 __ addl(dst_pos, tmp); 3408 } 3409 3410 __ jmp(*stub->entry()); 3411 3412 __ bind(cont); 3413 __ pop(dst); 3414 __ pop(src); 3415 } 3416 } 3417 3418 #ifdef ASSERT 3419 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3420 // Sanity check the known type with the incoming class. For the 3421 // primitive case the types must match exactly with src.klass and 3422 // dst.klass each exactly matching the default type. For the 3423 // object array case, if no type check is needed then either the 3424 // dst type is exactly the expected type and the src type is a 3425 // subtype which we can't check or src is the same array as dst 3426 // but not necessarily exactly of type default_type. 3427 Label known_ok, halt; 3428 __ mov_metadata(tmp, default_type->constant_encoding()); 3429 #ifdef _LP64 3430 if (UseCompressedClassPointers) { 3431 __ encode_klass_not_null(tmp); 3432 } 3433 #endif 3434 3435 if (basic_type != T_OBJECT) { 3436 3437 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3438 else __ cmpptr(tmp, dst_klass_addr); 3439 __ jcc(Assembler::notEqual, halt); 3440 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3441 else __ cmpptr(tmp, src_klass_addr); 3442 __ jcc(Assembler::equal, known_ok); 3443 } else { 3444 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3445 else __ cmpptr(tmp, dst_klass_addr); 3446 __ jcc(Assembler::equal, known_ok); 3447 __ cmpptr(src, dst); 3448 __ jcc(Assembler::equal, known_ok); 3449 } 3450 __ bind(halt); 3451 __ stop("incorrect type information in arraycopy"); 3452 __ bind(known_ok); 3453 } 3454 #endif 3455 3456 #ifndef PRODUCT 3457 if (PrintC1Statistics) { 3458 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3459 } 3460 #endif 3461 3462 #ifdef _LP64 3463 assert_different_registers(c_rarg0, dst, dst_pos, length); 3464 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3465 assert_different_registers(c_rarg1, length); 3466 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3467 __ mov(c_rarg2, length); 3468 3469 #else 3470 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3471 store_parameter(tmp, 0); 3472 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3473 store_parameter(tmp, 1); 3474 store_parameter(length, 2); 3475 #endif // _LP64 3476 3477 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3478 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3479 const char *name; 3480 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3481 __ call_VM_leaf(entry, 0); 3482 3483 __ bind(*stub->continuation()); 3484 } 3485 3486 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3487 assert(op->crc()->is_single_cpu(), "crc must be register"); 3488 assert(op->val()->is_single_cpu(), "byte value must be register"); 3489 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3490 Register crc = op->crc()->as_register(); 3491 Register val = op->val()->as_register(); 3492 Register res = op->result_opr()->as_register(); 3493 3494 assert_different_registers(val, crc, res); 3495 3496 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3497 __ notl(crc); // ~crc 3498 __ update_byte_crc32(crc, val, res); 3499 __ notl(crc); // ~crc 3500 __ mov(res, crc); 3501 } 3502 3503 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3504 Register obj = op->obj_opr()->as_register(); // may not be an oop 3505 Register hdr = op->hdr_opr()->as_register(); 3506 Register lock = op->lock_opr()->as_register(); 3507 if (!UseFastLocking) { 3508 __ jmp(*op->stub()->entry()); 3509 } else if (op->code() == lir_lock) { 3510 Register scratch = noreg; 3511 if (UseBiasedLocking) { 3512 scratch = op->scratch_opr()->as_register(); 3513 } 3514 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3515 // add debug info for NullPointerException only if one is possible 3516 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3517 if (op->info() != NULL) { 3518 add_debug_info_for_null_check(null_check_offset, op->info()); 3519 } 3520 // done 3521 } else if (op->code() == lir_unlock) { 3522 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3523 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3524 } else { 3525 Unimplemented(); 3526 } 3527 __ bind(*op->stub()->continuation()); 3528 } 3529 3530 3531 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3532 ciMethod* method = op->profiled_method(); 3533 int bci = op->profiled_bci(); 3534 ciMethod* callee = op->profiled_callee(); 3535 3536 // Update counter for all call types 3537 ciMethodData* md = method->method_data_or_null(); 3538 assert(md != NULL, "Sanity"); 3539 ciProfileData* data = md->bci_to_data(bci); 3540 assert(data->is_CounterData(), "need CounterData for calls"); 3541 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3542 Register mdo = op->mdo()->as_register(); 3543 __ mov_metadata(mdo, md->constant_encoding()); 3544 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3545 Bytecodes::Code bc = method->java_code_at_bci(bci); 3546 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 3547 // Perform additional virtual call profiling for invokevirtual and 3548 // invokeinterface bytecodes 3549 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3550 !callee_is_static && // required for optimized MH invokes 3551 C1ProfileVirtualCalls) { 3552 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3553 Register recv = op->recv()->as_register(); 3554 assert_different_registers(mdo, recv); 3555 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3556 ciKlass* known_klass = op->known_holder(); 3557 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3558 // We know the type that will be seen at this call site; we can 3559 // statically update the MethodData* rather than needing to do 3560 // dynamic tests on the receiver type 3561 3562 // NOTE: we should probably put a lock around this search to 3563 // avoid collisions by concurrent compilations 3564 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3565 uint i; 3566 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3567 ciKlass* receiver = vc_data->receiver(i); 3568 if (known_klass->equals(receiver)) { 3569 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3570 __ addptr(data_addr, DataLayout::counter_increment); 3571 return; 3572 } 3573 } 3574 3575 // Receiver type not found in profile data; select an empty slot 3576 3577 // Note that this is less efficient than it should be because it 3578 // always does a write to the receiver part of the 3579 // VirtualCallData rather than just the first time 3580 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3581 ciKlass* receiver = vc_data->receiver(i); 3582 if (receiver == NULL) { 3583 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3584 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3585 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3586 __ addptr(data_addr, DataLayout::counter_increment); 3587 return; 3588 } 3589 } 3590 } else { 3591 __ load_klass(recv, recv); 3592 Label update_done; 3593 type_profile_helper(mdo, md, data, recv, &update_done); 3594 // Receiver did not match any saved receiver and there is no empty row for it. 3595 // Increment total counter to indicate polymorphic case. 3596 __ addptr(counter_addr, DataLayout::counter_increment); 3597 3598 __ bind(update_done); 3599 } 3600 } else { 3601 // Static call 3602 __ addptr(counter_addr, DataLayout::counter_increment); 3603 } 3604 } 3605 3606 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3607 Register obj = op->obj()->as_register(); 3608 Register tmp = op->tmp()->as_pointer_register(); 3609 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3610 ciKlass* exact_klass = op->exact_klass(); 3611 intptr_t current_klass = op->current_klass(); 3612 bool not_null = op->not_null(); 3613 bool no_conflict = op->no_conflict(); 3614 3615 Label update, next, none; 3616 3617 bool do_null = !not_null; 3618 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3619 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3620 3621 assert(do_null || do_update, "why are we here?"); 3622 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3623 3624 __ verify_oop(obj); 3625 3626 if (tmp != obj) { 3627 __ mov(tmp, obj); 3628 } 3629 if (do_null) { 3630 __ testptr(tmp, tmp); 3631 __ jccb(Assembler::notZero, update); 3632 if (!TypeEntries::was_null_seen(current_klass)) { 3633 __ orptr(mdo_addr, TypeEntries::null_seen); 3634 } 3635 if (do_update) { 3636 #ifndef ASSERT 3637 __ jmpb(next); 3638 } 3639 #else 3640 __ jmp(next); 3641 } 3642 } else { 3643 __ testptr(tmp, tmp); 3644 __ jccb(Assembler::notZero, update); 3645 __ stop("unexpect null obj"); 3646 #endif 3647 } 3648 3649 __ bind(update); 3650 3651 if (do_update) { 3652 #ifdef ASSERT 3653 if (exact_klass != NULL) { 3654 Label ok; 3655 __ load_klass(tmp, tmp); 3656 __ push(tmp); 3657 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3658 __ cmpptr(tmp, Address(rsp, 0)); 3659 __ jccb(Assembler::equal, ok); 3660 __ stop("exact klass and actual klass differ"); 3661 __ bind(ok); 3662 __ pop(tmp); 3663 } 3664 #endif 3665 if (!no_conflict) { 3666 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3667 if (exact_klass != NULL) { 3668 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3669 } else { 3670 __ load_klass(tmp, tmp); 3671 } 3672 3673 __ xorptr(tmp, mdo_addr); 3674 __ testptr(tmp, TypeEntries::type_klass_mask); 3675 // klass seen before, nothing to do. The unknown bit may have been 3676 // set already but no need to check. 3677 __ jccb(Assembler::zero, next); 3678 3679 __ testptr(tmp, TypeEntries::type_unknown); 3680 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3681 3682 if (TypeEntries::is_type_none(current_klass)) { 3683 __ cmpptr(mdo_addr, 0); 3684 __ jccb(Assembler::equal, none); 3685 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3686 __ jccb(Assembler::equal, none); 3687 // There is a chance that the checks above (re-reading profiling 3688 // data from memory) fail if another thread has just set the 3689 // profiling to this obj's klass 3690 __ xorptr(tmp, mdo_addr); 3691 __ testptr(tmp, TypeEntries::type_klass_mask); 3692 __ jccb(Assembler::zero, next); 3693 } 3694 } else { 3695 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3696 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3697 3698 __ movptr(tmp, mdo_addr); 3699 __ testptr(tmp, TypeEntries::type_unknown); 3700 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3701 } 3702 3703 // different than before. Cannot keep accurate profile. 3704 __ orptr(mdo_addr, TypeEntries::type_unknown); 3705 3706 if (TypeEntries::is_type_none(current_klass)) { 3707 __ jmpb(next); 3708 3709 __ bind(none); 3710 // first time here. Set profile type. 3711 __ movptr(mdo_addr, tmp); 3712 } 3713 } else { 3714 // There's a single possible klass at this profile point 3715 assert(exact_klass != NULL, "should be"); 3716 if (TypeEntries::is_type_none(current_klass)) { 3717 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3718 __ xorptr(tmp, mdo_addr); 3719 __ testptr(tmp, TypeEntries::type_klass_mask); 3720 #ifdef ASSERT 3721 __ jcc(Assembler::zero, next); 3722 3723 { 3724 Label ok; 3725 __ push(tmp); 3726 __ cmpptr(mdo_addr, 0); 3727 __ jcc(Assembler::equal, ok); 3728 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3729 __ jcc(Assembler::equal, ok); 3730 // may have been set by another thread 3731 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3732 __ xorptr(tmp, mdo_addr); 3733 __ testptr(tmp, TypeEntries::type_mask); 3734 __ jcc(Assembler::zero, ok); 3735 3736 __ stop("unexpected profiling mismatch"); 3737 __ bind(ok); 3738 __ pop(tmp); 3739 } 3740 #else 3741 __ jccb(Assembler::zero, next); 3742 #endif 3743 // first time here. Set profile type. 3744 __ movptr(mdo_addr, tmp); 3745 } else { 3746 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3747 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3748 3749 __ movptr(tmp, mdo_addr); 3750 __ testptr(tmp, TypeEntries::type_unknown); 3751 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3752 3753 __ orptr(mdo_addr, TypeEntries::type_unknown); 3754 } 3755 } 3756 3757 __ bind(next); 3758 } 3759 } 3760 3761 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3762 Unimplemented(); 3763 } 3764 3765 3766 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3767 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3768 } 3769 3770 3771 void LIR_Assembler::align_backward_branch_target() { 3772 __ align(BytesPerWord); 3773 } 3774 3775 3776 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3777 if (left->is_single_cpu()) { 3778 __ negl(left->as_register()); 3779 move_regs(left->as_register(), dest->as_register()); 3780 3781 } else if (left->is_double_cpu()) { 3782 Register lo = left->as_register_lo(); 3783 #ifdef _LP64 3784 Register dst = dest->as_register_lo(); 3785 __ movptr(dst, lo); 3786 __ negptr(dst); 3787 #else 3788 Register hi = left->as_register_hi(); 3789 __ lneg(hi, lo); 3790 if (dest->as_register_lo() == hi) { 3791 assert(dest->as_register_hi() != lo, "destroying register"); 3792 move_regs(hi, dest->as_register_hi()); 3793 move_regs(lo, dest->as_register_lo()); 3794 } else { 3795 move_regs(lo, dest->as_register_lo()); 3796 move_regs(hi, dest->as_register_hi()); 3797 } 3798 #endif // _LP64 3799 3800 } else if (dest->is_single_xmm()) { 3801 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3802 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3803 } 3804 if (UseAVX > 0) { 3805 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3806 ExternalAddress((address)float_signflip_pool)); 3807 } else { 3808 __ xorps(dest->as_xmm_float_reg(), 3809 ExternalAddress((address)float_signflip_pool)); 3810 } 3811 } else if (dest->is_double_xmm()) { 3812 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3813 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3814 } 3815 if (UseAVX > 0) { 3816 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3817 ExternalAddress((address)double_signflip_pool)); 3818 } else { 3819 __ xorpd(dest->as_xmm_double_reg(), 3820 ExternalAddress((address)double_signflip_pool)); 3821 } 3822 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3823 assert(left->fpu() == 0, "arg must be on TOS"); 3824 assert(dest->fpu() == 0, "dest must be TOS"); 3825 __ fchs(); 3826 3827 } else { 3828 ShouldNotReachHere(); 3829 } 3830 } 3831 3832 3833 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3834 assert(addr->is_address() && dest->is_register(), "check"); 3835 Register reg; 3836 reg = dest->as_pointer_register(); 3837 __ lea(reg, as_Address(addr->as_address_ptr())); 3838 } 3839 3840 3841 3842 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3843 assert(!tmp->is_valid(), "don't need temporary"); 3844 __ call(RuntimeAddress(dest)); 3845 if (info != NULL) { 3846 add_call_info_here(info); 3847 } 3848 } 3849 3850 3851 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3852 assert(type == T_LONG, "only for volatile long fields"); 3853 3854 if (info != NULL) { 3855 add_debug_info_for_null_check_here(info); 3856 } 3857 3858 if (src->is_double_xmm()) { 3859 if (dest->is_double_cpu()) { 3860 #ifdef _LP64 3861 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3862 #else 3863 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3864 __ psrlq(src->as_xmm_double_reg(), 32); 3865 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3866 #endif // _LP64 3867 } else if (dest->is_double_stack()) { 3868 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3869 } else if (dest->is_address()) { 3870 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3871 } else { 3872 ShouldNotReachHere(); 3873 } 3874 3875 } else if (dest->is_double_xmm()) { 3876 if (src->is_double_stack()) { 3877 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3878 } else if (src->is_address()) { 3879 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3880 } else { 3881 ShouldNotReachHere(); 3882 } 3883 3884 } else if (src->is_double_fpu()) { 3885 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3886 if (dest->is_double_stack()) { 3887 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3888 } else if (dest->is_address()) { 3889 __ fistp_d(as_Address(dest->as_address_ptr())); 3890 } else { 3891 ShouldNotReachHere(); 3892 } 3893 3894 } else if (dest->is_double_fpu()) { 3895 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3896 if (src->is_double_stack()) { 3897 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3898 } else if (src->is_address()) { 3899 __ fild_d(as_Address(src->as_address_ptr())); 3900 } else { 3901 ShouldNotReachHere(); 3902 } 3903 } else { 3904 ShouldNotReachHere(); 3905 } 3906 } 3907 3908 #ifdef ASSERT 3909 // emit run-time assertion 3910 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3911 assert(op->code() == lir_assert, "must be"); 3912 3913 if (op->in_opr1()->is_valid()) { 3914 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3915 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3916 } else { 3917 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3918 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3919 } 3920 3921 Label ok; 3922 if (op->condition() != lir_cond_always) { 3923 Assembler::Condition acond = Assembler::zero; 3924 switch (op->condition()) { 3925 case lir_cond_equal: acond = Assembler::equal; break; 3926 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3927 case lir_cond_less: acond = Assembler::less; break; 3928 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3929 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3930 case lir_cond_greater: acond = Assembler::greater; break; 3931 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3932 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3933 default: ShouldNotReachHere(); 3934 } 3935 __ jcc(acond, ok); 3936 } 3937 if (op->halt()) { 3938 const char* str = __ code_string(op->msg()); 3939 __ stop(str); 3940 } else { 3941 breakpoint(); 3942 } 3943 __ bind(ok); 3944 } 3945 #endif 3946 3947 void LIR_Assembler::membar() { 3948 // QQQ sparc TSO uses this, 3949 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3950 } 3951 3952 void LIR_Assembler::membar_acquire() { 3953 // No x86 machines currently require load fences 3954 } 3955 3956 void LIR_Assembler::membar_release() { 3957 // No x86 machines currently require store fences 3958 } 3959 3960 void LIR_Assembler::membar_loadload() { 3961 // no-op 3962 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3963 } 3964 3965 void LIR_Assembler::membar_storestore() { 3966 // no-op 3967 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3968 } 3969 3970 void LIR_Assembler::membar_loadstore() { 3971 // no-op 3972 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3973 } 3974 3975 void LIR_Assembler::membar_storeload() { 3976 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3977 } 3978 3979 void LIR_Assembler::on_spin_wait() { 3980 __ pause (); 3981 } 3982 3983 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3984 assert(result_reg->is_register(), "check"); 3985 #ifdef _LP64 3986 // __ get_thread(result_reg->as_register_lo()); 3987 __ mov(result_reg->as_register(), r15_thread); 3988 #else 3989 __ get_thread(result_reg->as_register()); 3990 #endif // _LP64 3991 } 3992 3993 3994 void LIR_Assembler::peephole(LIR_List*) { 3995 // do nothing for now 3996 } 3997 3998 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3999 assert(data == dest, "xchg/xadd uses only 2 operands"); 4000 4001 if (data->type() == T_INT) { 4002 if (code == lir_xadd) { 4003 if (os::is_MP()) { 4004 __ lock(); 4005 } 4006 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4007 } else { 4008 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4009 } 4010 } else if (data->is_oop()) { 4011 assert (code == lir_xchg, "xadd for oops"); 4012 Register obj = data->as_register(); 4013 #ifdef _LP64 4014 if (UseCompressedOops) { 4015 __ encode_heap_oop(obj); 4016 __ xchgl(obj, as_Address(src->as_address_ptr())); 4017 __ decode_heap_oop(obj); 4018 } else { 4019 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4020 } 4021 #else 4022 __ xchgl(obj, as_Address(src->as_address_ptr())); 4023 #endif 4024 } else if (data->type() == T_LONG) { 4025 #ifdef _LP64 4026 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4027 if (code == lir_xadd) { 4028 if (os::is_MP()) { 4029 __ lock(); 4030 } 4031 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4032 } else { 4033 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4034 } 4035 #else 4036 ShouldNotReachHere(); 4037 #endif 4038 } else { 4039 ShouldNotReachHere(); 4040 } 4041 } 4042 4043 #undef __