1 /*
2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
360
361
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
368
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
375
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() const {
378 // if rounding, must let FrameMap know!
379
380 // The frame_map records size in slots (32bit word)
381
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
385
386
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
394
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size());
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
402
403 int offset = code_offset();
404
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
408
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
411
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
435 NOT_LP64(__ get_thread(rsi));
436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
444 }
445
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rsi, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
454
455 if (compilation()->env()->dtrace_method_probes()) {
456 #ifdef _LP64
457 __ mov(rdi, r15_thread);
458 __ mov_metadata(rsi, method()->constant_encoding());
459 #else
460 __ get_thread(rax);
461 __ movptr(Address(rsp, 0), rax);
462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
463 #endif
464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
465 }
466
467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
468 __ mov(rax, rbx); // Restore the exception
469 }
470
471 // remove the activation and dispatch to the unwind handler
472 __ remove_frame(initial_frame_size_in_bytes());
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
474
475 // Emit the slow path assembly
476 if (stub != NULL) {
477 stub->emit_code(this);
478 }
479
480 return offset;
481 }
482
483
484 int LIR_Assembler::emit_deopt_handler() {
485 // if the last instruction is a call (typically to do a throw which
486 // is coming at the end after block reordering) the return address
487 // must still point into the code area in order to avoid assertion
488 // failures when searching for the corresponding bci => add a nop
489 // (was bug 5/14/1999 - gri)
490 __ nop();
491
492 // generate code for exception handler
493 address handler_base = __ start_a_stub(deopt_handler_size());
494 if (handler_base == NULL) {
495 // not enough space left for the handler
496 bailout("deopt handler overflow");
497 return -1;
498 }
499
500 int offset = code_offset();
501 InternalAddress here(__ pc());
502
503 __ pushptr(here.addr());
504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
506 __ end_a_stub();
507
508 return offset;
509 }
510
511
512 void LIR_Assembler::return_op(LIR_Opr result) {
513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
515 assert(result->fpu() == 0, "result must already be on TOS");
516 }
517
518 // Pop the stack before the safepoint code
519 __ remove_frame(initial_frame_size_in_bytes());
520
521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
522 __ reserved_stack_check();
523 }
524
525 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
530
531 if (Assembler::is_polling_page_far()) {
532 __ lea(rscratch1, polling_page);
533 __ relocate(relocInfo::poll_return_type);
534 __ testl(rax, Address(rscratch1, 0));
535 } else {
536 __ testl(rax, polling_page);
537 }
538 __ ret(0);
539 }
540
541
542 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
544 guarantee(info != NULL, "Shouldn't be NULL");
545 int offset = __ offset();
546 if (Assembler::is_polling_page_far()) {
547 __ lea(rscratch1, polling_page);
548 offset = __ offset();
549 add_debug_info_for_branch(info);
550 __ relocate(relocInfo::poll_type);
551 __ testl(rax, Address(rscratch1, 0));
552 } else {
553 add_debug_info_for_branch(info);
554 __ testl(rax, polling_page);
555 }
556 return offset;
557 }
558
559
560 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
561 if (from_reg != to_reg) __ mov(to_reg, from_reg);
562 }
563
564 void LIR_Assembler::swap_reg(Register a, Register b) {
565 __ xchgptr(a, b);
566 }
567
568
569 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
570 assert(src->is_constant(), "should not call otherwise");
571 assert(dest->is_register(), "should not call otherwise");
572 LIR_Const* c = src->as_constant_ptr();
573
574 switch (c->type()) {
575 case T_INT: {
576 assert(patch_code == lir_patch_none, "no patching handled here");
577 __ movl(dest->as_register(), c->as_jint());
578 break;
579 }
580
581 case T_ADDRESS: {
582 assert(patch_code == lir_patch_none, "no patching handled here");
583 __ movptr(dest->as_register(), c->as_jint());
584 break;
585 }
586
587 case T_LONG: {
588 assert(patch_code == lir_patch_none, "no patching handled here");
589 #ifdef _LP64
590 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
591 #else
592 __ movptr(dest->as_register_lo(), c->as_jint_lo());
593 __ movptr(dest->as_register_hi(), c->as_jint_hi());
594 #endif // _LP64
595 break;
596 }
597
598 case T_OBJECT: {
599 if (patch_code != lir_patch_none) {
600 jobject2reg_with_patching(dest->as_register(), info);
601 } else {
602 __ movoop(dest->as_register(), c->as_jobject());
603 }
604 break;
605 }
606
607 case T_METADATA: {
608 if (patch_code != lir_patch_none) {
609 klass2reg_with_patching(dest->as_register(), info);
610 } else {
611 __ mov_metadata(dest->as_register(), c->as_metadata());
612 }
613 break;
614 }
615
616 case T_FLOAT: {
617 if (dest->is_single_xmm()) {
618 if (c->is_zero_float()) {
619 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
620 } else {
621 __ movflt(dest->as_xmm_float_reg(),
622 InternalAddress(float_constant(c->as_jfloat())));
623 }
624 } else {
625 assert(dest->is_single_fpu(), "must be");
626 assert(dest->fpu_regnr() == 0, "dest must be TOS");
627 if (c->is_zero_float()) {
628 __ fldz();
629 } else if (c->is_one_float()) {
630 __ fld1();
631 } else {
632 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
633 }
634 }
635 break;
636 }
637
638 case T_DOUBLE: {
639 if (dest->is_double_xmm()) {
640 if (c->is_zero_double()) {
641 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
642 } else {
643 __ movdbl(dest->as_xmm_double_reg(),
644 InternalAddress(double_constant(c->as_jdouble())));
645 }
646 } else {
647 assert(dest->is_double_fpu(), "must be");
648 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
649 if (c->is_zero_double()) {
650 __ fldz();
651 } else if (c->is_one_double()) {
652 __ fld1();
653 } else {
654 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
655 }
656 }
657 break;
658 }
659
660 default:
661 ShouldNotReachHere();
662 }
663 }
664
665 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
666 assert(src->is_constant(), "should not call otherwise");
667 assert(dest->is_stack(), "should not call otherwise");
668 LIR_Const* c = src->as_constant_ptr();
669
670 switch (c->type()) {
671 case T_INT: // fall through
672 case T_FLOAT:
673 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
674 break;
675
676 case T_ADDRESS:
677 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
678 break;
679
680 case T_OBJECT:
681 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
682 break;
683
684 case T_LONG: // fall through
685 case T_DOUBLE:
686 #ifdef _LP64
687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
688 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
689 #else
690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
691 lo_word_offset_in_bytes), c->as_jint_lo_bits());
692 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
693 hi_word_offset_in_bytes), c->as_jint_hi_bits());
694 #endif // _LP64
695 break;
696
697 default:
698 ShouldNotReachHere();
699 }
700 }
701
702 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
703 assert(src->is_constant(), "should not call otherwise");
704 assert(dest->is_address(), "should not call otherwise");
705 LIR_Const* c = src->as_constant_ptr();
706 LIR_Address* addr = dest->as_address_ptr();
707
708 int null_check_here = code_offset();
709 switch (type) {
710 case T_INT: // fall through
711 case T_FLOAT:
712 __ movl(as_Address(addr), c->as_jint_bits());
713 break;
714
715 case T_ADDRESS:
716 __ movptr(as_Address(addr), c->as_jint_bits());
717 break;
718
719 case T_OBJECT: // fall through
720 case T_ARRAY:
721 if (c->as_jobject() == NULL) {
722 if (UseCompressedOops && !wide) {
723 __ movl(as_Address(addr), (int32_t)NULL_WORD);
724 } else {
725 #ifdef _LP64
726 __ xorptr(rscratch1, rscratch1);
727 null_check_here = code_offset();
728 __ movptr(as_Address(addr), rscratch1);
729 #else
730 __ movptr(as_Address(addr), NULL_WORD);
731 #endif
732 }
733 } else {
734 if (is_literal_address(addr)) {
735 ShouldNotReachHere();
736 __ movoop(as_Address(addr, noreg), c->as_jobject());
737 } else {
738 #ifdef _LP64
739 __ movoop(rscratch1, c->as_jobject());
740 if (UseCompressedOops && !wide) {
741 __ encode_heap_oop(rscratch1);
742 null_check_here = code_offset();
743 __ movl(as_Address_lo(addr), rscratch1);
744 } else {
745 null_check_here = code_offset();
746 __ movptr(as_Address_lo(addr), rscratch1);
747 }
748 #else
749 __ movoop(as_Address(addr), c->as_jobject());
750 #endif
751 }
752 }
753 break;
754
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 if (is_literal_address(addr)) {
759 ShouldNotReachHere();
760 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
761 } else {
762 __ movptr(r10, (intptr_t)c->as_jlong_bits());
763 null_check_here = code_offset();
764 __ movptr(as_Address_lo(addr), r10);
765 }
766 #else
767 // Always reachable in 32bit so this doesn't produce useless move literal
768 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
769 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
770 #endif // _LP64
771 break;
772
773 case T_BOOLEAN: // fall through
774 case T_BYTE:
775 __ movb(as_Address(addr), c->as_jint() & 0xFF);
776 break;
777
778 case T_CHAR: // fall through
779 case T_SHORT:
780 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
781 break;
782
783 default:
784 ShouldNotReachHere();
785 };
786
787 if (info != NULL) {
788 add_debug_info_for_null_check(null_check_here, info);
789 }
790 }
791
792
793 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
794 assert(src->is_register(), "should not call otherwise");
795 assert(dest->is_register(), "should not call otherwise");
796
797 // move between cpu-registers
798 if (dest->is_single_cpu()) {
799 #ifdef _LP64
800 if (src->type() == T_LONG) {
801 // Can do LONG -> OBJECT
802 move_regs(src->as_register_lo(), dest->as_register());
803 return;
804 }
805 #endif
806 assert(src->is_single_cpu(), "must match");
807 if (src->type() == T_OBJECT) {
808 __ verify_oop(src->as_register());
809 }
810 move_regs(src->as_register(), dest->as_register());
811
812 } else if (dest->is_double_cpu()) {
813 #ifdef _LP64
814 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
815 // Surprising to me but we can see move of a long to t_object
816 __ verify_oop(src->as_register());
817 move_regs(src->as_register(), dest->as_register_lo());
818 return;
819 }
820 #endif
821 assert(src->is_double_cpu(), "must match");
822 Register f_lo = src->as_register_lo();
823 Register f_hi = src->as_register_hi();
824 Register t_lo = dest->as_register_lo();
825 Register t_hi = dest->as_register_hi();
826 #ifdef _LP64
827 assert(f_hi == f_lo, "must be same");
828 assert(t_hi == t_lo, "must be same");
829 move_regs(f_lo, t_lo);
830 #else
831 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
832
833
834 if (f_lo == t_hi && f_hi == t_lo) {
835 swap_reg(f_lo, f_hi);
836 } else if (f_hi == t_lo) {
837 assert(f_lo != t_hi, "overwriting register");
838 move_regs(f_hi, t_hi);
839 move_regs(f_lo, t_lo);
840 } else {
841 assert(f_hi != t_lo, "overwriting register");
842 move_regs(f_lo, t_lo);
843 move_regs(f_hi, t_hi);
844 }
845 #endif // LP64
846
847 // special moves from fpu-register to xmm-register
848 // necessary for method results
849 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
850 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
851 __ fld_s(Address(rsp, 0));
852 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
853 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
854 __ fld_d(Address(rsp, 0));
855 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
856 __ fstp_s(Address(rsp, 0));
857 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
858 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
859 __ fstp_d(Address(rsp, 0));
860 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
861
862 // move between xmm-registers
863 } else if (dest->is_single_xmm()) {
864 assert(src->is_single_xmm(), "must match");
865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
866 } else if (dest->is_double_xmm()) {
867 assert(src->is_double_xmm(), "must match");
868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
869
870 // move between fpu-registers (no instruction necessary because of fpu-stack)
871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
874 } else {
875 ShouldNotReachHere();
876 }
877 }
878
879 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
880 assert(src->is_register(), "should not call otherwise");
881 assert(dest->is_stack(), "should not call otherwise");
882
883 if (src->is_single_cpu()) {
884 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
885 if (type == T_OBJECT || type == T_ARRAY) {
886 __ verify_oop(src->as_register());
887 __ movptr (dst, src->as_register());
888 } else if (type == T_METADATA) {
889 __ movptr (dst, src->as_register());
890 } else {
891 __ movl (dst, src->as_register());
892 }
893
894 } else if (src->is_double_cpu()) {
895 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
896 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
897 __ movptr (dstLO, src->as_register_lo());
898 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
899
900 } else if (src->is_single_xmm()) {
901 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
902 __ movflt(dst_addr, src->as_xmm_float_reg());
903
904 } else if (src->is_double_xmm()) {
905 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
906 __ movdbl(dst_addr, src->as_xmm_double_reg());
907
908 } else if (src->is_single_fpu()) {
909 assert(src->fpu_regnr() == 0, "argument must be on TOS");
910 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
911 if (pop_fpu_stack) __ fstp_s (dst_addr);
912 else __ fst_s (dst_addr);
913
914 } else if (src->is_double_fpu()) {
915 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
916 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
917 if (pop_fpu_stack) __ fstp_d (dst_addr);
918 else __ fst_d (dst_addr);
919
920 } else {
921 ShouldNotReachHere();
922 }
923 }
924
925
926 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
927 LIR_Address* to_addr = dest->as_address_ptr();
928 PatchingStub* patch = NULL;
929 Register compressed_src = rscratch1;
930
931 if (type == T_ARRAY || type == T_OBJECT) {
932 __ verify_oop(src->as_register());
933 __ shenandoah_store_addr_check(as_Address(to_addr));
934 __ shenandoah_store_val_check(as_Address(to_addr), src->as_register());
935 #ifdef _LP64
936 if (UseCompressedOops && !wide) {
937 __ movptr(compressed_src, src->as_register());
938 __ encode_heap_oop(compressed_src);
939 if (patch_code != lir_patch_none) {
940 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
941 }
942 }
943 #endif
944 } else {
945 __ shenandoah_store_addr_check(to_addr->base()->as_pointer_register());
946 }
947
948 if (patch_code != lir_patch_none) {
949 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
950 Address toa = as_Address(to_addr);
951 assert(toa.disp() != 0, "must have");
952 }
953
954 int null_check_here = code_offset();
955 switch (type) {
956 case T_FLOAT: {
957 if (src->is_single_xmm()) {
958 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
959 } else {
960 assert(src->is_single_fpu(), "must be");
961 assert(src->fpu_regnr() == 0, "argument must be on TOS");
962 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
963 else __ fst_s (as_Address(to_addr));
964 }
965 break;
966 }
967
968 case T_DOUBLE: {
969 if (src->is_double_xmm()) {
970 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
971 } else {
972 assert(src->is_double_fpu(), "must be");
973 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
974 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
975 else __ fst_d (as_Address(to_addr));
976 }
977 break;
978 }
979
980 case T_ARRAY: // fall through
981 case T_OBJECT: // fall through
982 if (UseCompressedOops && !wide) {
983 __ movl(as_Address(to_addr), compressed_src);
984 } else {
985 __ movptr(as_Address(to_addr), src->as_register());
986 }
987 break;
988 case T_METADATA:
989 // We get here to store a method pointer to the stack to pass to
990 // a dtrace runtime call. This can't work on 64 bit with
991 // compressed klass ptrs: T_METADATA can be a compressed klass
992 // ptr or a 64 bit method pointer.
993 LP64_ONLY(ShouldNotReachHere());
994 __ movptr(as_Address(to_addr), src->as_register());
995 break;
996 case T_ADDRESS:
997 __ movptr(as_Address(to_addr), src->as_register());
998 break;
999 case T_INT:
1000 __ movl(as_Address(to_addr), src->as_register());
1001 break;
1002
1003 case T_LONG: {
1004 Register from_lo = src->as_register_lo();
1005 Register from_hi = src->as_register_hi();
1006 #ifdef _LP64
1007 __ movptr(as_Address_lo(to_addr), from_lo);
1008 #else
1009 Register base = to_addr->base()->as_register();
1010 Register index = noreg;
1011 if (to_addr->index()->is_register()) {
1012 index = to_addr->index()->as_register();
1013 }
1014 if (base == from_lo || index == from_lo) {
1015 assert(base != from_hi, "can't be");
1016 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1017 __ movl(as_Address_hi(to_addr), from_hi);
1018 if (patch != NULL) {
1019 patching_epilog(patch, lir_patch_high, base, info);
1020 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1021 patch_code = lir_patch_low;
1022 }
1023 __ movl(as_Address_lo(to_addr), from_lo);
1024 } else {
1025 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1026 __ movl(as_Address_lo(to_addr), from_lo);
1027 if (patch != NULL) {
1028 patching_epilog(patch, lir_patch_low, base, info);
1029 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1030 patch_code = lir_patch_high;
1031 }
1032 __ movl(as_Address_hi(to_addr), from_hi);
1033 }
1034 #endif // _LP64
1035 break;
1036 }
1037
1038 case T_BYTE: // fall through
1039 case T_BOOLEAN: {
1040 Register src_reg = src->as_register();
1041 Address dst_addr = as_Address(to_addr);
1042 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1043 __ movb(dst_addr, src_reg);
1044 break;
1045 }
1046
1047 case T_CHAR: // fall through
1048 case T_SHORT:
1049 __ movw(as_Address(to_addr), src->as_register());
1050 break;
1051
1052 default:
1053 ShouldNotReachHere();
1054 }
1055 if (info != NULL) {
1056 add_debug_info_for_null_check(null_check_here, info);
1057 }
1058
1059 if (patch_code != lir_patch_none) {
1060 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1061 }
1062 }
1063
1064
1065 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1066 assert(src->is_stack(), "should not call otherwise");
1067 assert(dest->is_register(), "should not call otherwise");
1068
1069 if (dest->is_single_cpu()) {
1070 if (type == T_ARRAY || type == T_OBJECT) {
1071 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1072 __ verify_oop(dest->as_register());
1073 } else if (type == T_METADATA) {
1074 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1075 } else {
1076 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1077 }
1078
1079 } else if (dest->is_double_cpu()) {
1080 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1081 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1082 __ movptr(dest->as_register_lo(), src_addr_LO);
1083 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1084
1085 } else if (dest->is_single_xmm()) {
1086 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1087 __ movflt(dest->as_xmm_float_reg(), src_addr);
1088
1089 } else if (dest->is_double_xmm()) {
1090 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1091 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1092
1093 } else if (dest->is_single_fpu()) {
1094 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1095 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1096 __ fld_s(src_addr);
1097
1098 } else if (dest->is_double_fpu()) {
1099 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1100 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1101 __ fld_d(src_addr);
1102
1103 } else {
1104 ShouldNotReachHere();
1105 }
1106 }
1107
1108
1109 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1110 if (src->is_single_stack()) {
1111 if (type == T_OBJECT || type == T_ARRAY) {
1112 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1113 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1114 } else {
1115 #ifndef _LP64
1116 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1117 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1118 #else
1119 //no pushl on 64bits
1120 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1121 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1122 #endif
1123 }
1124
1125 } else if (src->is_double_stack()) {
1126 #ifdef _LP64
1127 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1128 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1129 #else
1130 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1131 // push and pop the part at src + wordSize, adding wordSize for the previous push
1132 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1133 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1134 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1135 #endif // _LP64
1136
1137 } else {
1138 ShouldNotReachHere();
1139 }
1140 }
1141
1142
1143 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1144 assert(src->is_address(), "should not call otherwise");
1145 assert(dest->is_register(), "should not call otherwise");
1146
1147 LIR_Address* addr = src->as_address_ptr();
1148 Address from_addr = as_Address(addr);
1149
1150 if (addr->base()->type() == T_OBJECT) {
1151 __ verify_oop(addr->base()->as_pointer_register());
1152 }
1153
1154 switch (type) {
1155 case T_BOOLEAN: // fall through
1156 case T_BYTE: // fall through
1157 case T_CHAR: // fall through
1158 case T_SHORT:
1159 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1160 // on pre P6 processors we may get partial register stalls
1161 // so blow away the value of to_rinfo before loading a
1162 // partial word into it. Do it here so that it precedes
1163 // the potential patch point below.
1164 __ xorptr(dest->as_register(), dest->as_register());
1165 }
1166 break;
1167 default:
1168 break;
1169 }
1170
1171 PatchingStub* patch = NULL;
1172 if (patch_code != lir_patch_none) {
1173 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1174 assert(from_addr.disp() != 0, "must have");
1175 }
1176 if (info != NULL) {
1177 add_debug_info_for_null_check_here(info);
1178 }
1179
1180 switch (type) {
1181 case T_FLOAT: {
1182 if (dest->is_single_xmm()) {
1183 __ movflt(dest->as_xmm_float_reg(), from_addr);
1184 } else {
1185 assert(dest->is_single_fpu(), "must be");
1186 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1187 __ fld_s(from_addr);
1188 }
1189 break;
1190 }
1191
1192 case T_DOUBLE: {
1193 if (dest->is_double_xmm()) {
1194 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1195 } else {
1196 assert(dest->is_double_fpu(), "must be");
1197 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1198 __ fld_d(from_addr);
1199 }
1200 break;
1201 }
1202
1203 case T_OBJECT: // fall through
1204 case T_ARRAY: // fall through
1205 if (UseCompressedOops && !wide) {
1206 __ movl(dest->as_register(), from_addr);
1207 } else {
1208 __ movptr(dest->as_register(), from_addr);
1209 }
1210 break;
1211
1212 case T_ADDRESS:
1213 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1214 __ movl(dest->as_register(), from_addr);
1215 } else {
1216 __ movptr(dest->as_register(), from_addr);
1217 }
1218 break;
1219 case T_INT:
1220 __ movl(dest->as_register(), from_addr);
1221 break;
1222
1223 case T_LONG: {
1224 Register to_lo = dest->as_register_lo();
1225 Register to_hi = dest->as_register_hi();
1226 #ifdef _LP64
1227 __ movptr(to_lo, as_Address_lo(addr));
1228 #else
1229 Register base = addr->base()->as_register();
1230 Register index = noreg;
1231 if (addr->index()->is_register()) {
1232 index = addr->index()->as_register();
1233 }
1234 if ((base == to_lo && index == to_hi) ||
1235 (base == to_hi && index == to_lo)) {
1236 // addresses with 2 registers are only formed as a result of
1237 // array access so this code will never have to deal with
1238 // patches or null checks.
1239 assert(info == NULL && patch == NULL, "must be");
1240 __ lea(to_hi, as_Address(addr));
1241 __ movl(to_lo, Address(to_hi, 0));
1242 __ movl(to_hi, Address(to_hi, BytesPerWord));
1243 } else if (base == to_lo || index == to_lo) {
1244 assert(base != to_hi, "can't be");
1245 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1246 __ movl(to_hi, as_Address_hi(addr));
1247 if (patch != NULL) {
1248 patching_epilog(patch, lir_patch_high, base, info);
1249 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1250 patch_code = lir_patch_low;
1251 }
1252 __ movl(to_lo, as_Address_lo(addr));
1253 } else {
1254 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1255 __ movl(to_lo, as_Address_lo(addr));
1256 if (patch != NULL) {
1257 patching_epilog(patch, lir_patch_low, base, info);
1258 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1259 patch_code = lir_patch_high;
1260 }
1261 __ movl(to_hi, as_Address_hi(addr));
1262 }
1263 #endif // _LP64
1264 break;
1265 }
1266
1267 case T_BOOLEAN: // fall through
1268 case T_BYTE: {
1269 Register dest_reg = dest->as_register();
1270 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1271 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1272 __ movsbl(dest_reg, from_addr);
1273 } else {
1274 __ movb(dest_reg, from_addr);
1275 __ shll(dest_reg, 24);
1276 __ sarl(dest_reg, 24);
1277 }
1278 break;
1279 }
1280
1281 case T_CHAR: {
1282 Register dest_reg = dest->as_register();
1283 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1284 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1285 __ movzwl(dest_reg, from_addr);
1286 } else {
1287 __ movw(dest_reg, from_addr);
1288 }
1289 break;
1290 }
1291
1292 case T_SHORT: {
1293 Register dest_reg = dest->as_register();
1294 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1295 __ movswl(dest_reg, from_addr);
1296 } else {
1297 __ movw(dest_reg, from_addr);
1298 __ shll(dest_reg, 16);
1299 __ sarl(dest_reg, 16);
1300 }
1301 break;
1302 }
1303
1304 default:
1305 ShouldNotReachHere();
1306 }
1307
1308 if (patch != NULL) {
1309 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1310 }
1311
1312 if (type == T_ARRAY || type == T_OBJECT) {
1313 #ifdef _LP64
1314 if (UseCompressedOops && !wide) {
1315 __ decode_heap_oop(dest->as_register());
1316 }
1317 #endif
1318 __ verify_oop(dest->as_register());
1319 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1320 #ifdef _LP64
1321 if (UseCompressedClassPointers) {
1322 __ decode_klass_not_null(dest->as_register());
1323 }
1324 #endif
1325 }
1326 }
1327
1328
1329 NEEDS_CLEANUP; // This could be static?
1330 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1331 int elem_size = type2aelembytes(type);
1332 switch (elem_size) {
1333 case 1: return Address::times_1;
1334 case 2: return Address::times_2;
1335 case 4: return Address::times_4;
1336 case 8: return Address::times_8;
1337 }
1338 ShouldNotReachHere();
1339 return Address::no_scale;
1340 }
1341
1342
1343 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1344 switch (op->code()) {
1345 case lir_idiv:
1346 case lir_irem:
1347 arithmetic_idiv(op->code(),
1348 op->in_opr1(),
1349 op->in_opr2(),
1350 op->in_opr3(),
1351 op->result_opr(),
1352 op->info());
1353 break;
1354 case lir_fmad:
1355 __ fmad(op->result_opr()->as_xmm_double_reg(),
1356 op->in_opr1()->as_xmm_double_reg(),
1357 op->in_opr2()->as_xmm_double_reg(),
1358 op->in_opr3()->as_xmm_double_reg());
1359 break;
1360 case lir_fmaf:
1361 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1362 op->in_opr1()->as_xmm_float_reg(),
1363 op->in_opr2()->as_xmm_float_reg(),
1364 op->in_opr3()->as_xmm_float_reg());
1365 break;
1366 default: ShouldNotReachHere(); break;
1367 }
1368 }
1369
1370 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1371 #ifdef ASSERT
1372 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1373 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1374 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1375 #endif
1376
1377 if (op->cond() == lir_cond_always) {
1378 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1379 __ jmp (*(op->label()));
1380 } else {
1381 Assembler::Condition acond = Assembler::zero;
1382 if (op->code() == lir_cond_float_branch) {
1383 assert(op->ublock() != NULL, "must have unordered successor");
1384 __ jcc(Assembler::parity, *(op->ublock()->label()));
1385 switch(op->cond()) {
1386 case lir_cond_equal: acond = Assembler::equal; break;
1387 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1388 case lir_cond_less: acond = Assembler::below; break;
1389 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1390 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1391 case lir_cond_greater: acond = Assembler::above; break;
1392 default: ShouldNotReachHere();
1393 }
1394 } else {
1395 switch (op->cond()) {
1396 case lir_cond_equal: acond = Assembler::equal; break;
1397 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1398 case lir_cond_less: acond = Assembler::less; break;
1399 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1400 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1401 case lir_cond_greater: acond = Assembler::greater; break;
1402 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1403 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1404 default: ShouldNotReachHere();
1405 }
1406 }
1407 __ jcc(acond,*(op->label()));
1408 }
1409 }
1410
1411 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
1412 Label done;
1413 Register obj = op->in_opr()->as_register();
1414 Register res = op->result_opr()->as_register();
1415
1416 if (res != obj) {
1417 __ mov(res, obj);
1418 }
1419
1420 // Check for null.
1421 if (op->need_null_check()) {
1422 __ testptr(res, res);
1423 __ jcc(Assembler::zero, done);
1424 }
1425
1426 __ shenandoah_write_barrier(res);
1427
1428 __ bind(done);
1429
1430 }
1431
1432 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1433 LIR_Opr src = op->in_opr();
1434 LIR_Opr dest = op->result_opr();
1435
1436 switch (op->bytecode()) {
1437 case Bytecodes::_i2l:
1438 #ifdef _LP64
1439 __ movl2ptr(dest->as_register_lo(), src->as_register());
1440 #else
1441 move_regs(src->as_register(), dest->as_register_lo());
1442 move_regs(src->as_register(), dest->as_register_hi());
1443 __ sarl(dest->as_register_hi(), 31);
1444 #endif // LP64
1445 break;
1446
1447 case Bytecodes::_l2i:
1448 #ifdef _LP64
1449 __ movl(dest->as_register(), src->as_register_lo());
1450 #else
1451 move_regs(src->as_register_lo(), dest->as_register());
1452 #endif
1453 break;
1454
1455 case Bytecodes::_i2b:
1456 move_regs(src->as_register(), dest->as_register());
1457 __ sign_extend_byte(dest->as_register());
1458 break;
1459
1460 case Bytecodes::_i2c:
1461 move_regs(src->as_register(), dest->as_register());
1462 __ andl(dest->as_register(), 0xFFFF);
1463 break;
1464
1465 case Bytecodes::_i2s:
1466 move_regs(src->as_register(), dest->as_register());
1467 __ sign_extend_short(dest->as_register());
1468 break;
1469
1470
1471 case Bytecodes::_f2d:
1472 case Bytecodes::_d2f:
1473 if (dest->is_single_xmm()) {
1474 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1475 } else if (dest->is_double_xmm()) {
1476 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1477 } else {
1478 assert(src->fpu() == dest->fpu(), "register must be equal");
1479 // do nothing (float result is rounded later through spilling)
1480 }
1481 break;
1482
1483 case Bytecodes::_i2f:
1484 case Bytecodes::_i2d:
1485 if (dest->is_single_xmm()) {
1486 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1487 } else if (dest->is_double_xmm()) {
1488 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1489 } else {
1490 assert(dest->fpu() == 0, "result must be on TOS");
1491 __ movl(Address(rsp, 0), src->as_register());
1492 __ fild_s(Address(rsp, 0));
1493 }
1494 break;
1495
1496 case Bytecodes::_f2i:
1497 case Bytecodes::_d2i:
1498 if (src->is_single_xmm()) {
1499 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1500 } else if (src->is_double_xmm()) {
1501 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1502 } else {
1503 assert(src->fpu() == 0, "input must be on TOS");
1504 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1505 __ fist_s(Address(rsp, 0));
1506 __ movl(dest->as_register(), Address(rsp, 0));
1507 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1508 }
1509
1510 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1511 assert(op->stub() != NULL, "stub required");
1512 __ cmpl(dest->as_register(), 0x80000000);
1513 __ jcc(Assembler::equal, *op->stub()->entry());
1514 __ bind(*op->stub()->continuation());
1515 break;
1516
1517 case Bytecodes::_l2f:
1518 case Bytecodes::_l2d:
1519 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1520 assert(dest->fpu() == 0, "result must be on TOS");
1521
1522 __ movptr(Address(rsp, 0), src->as_register_lo());
1523 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1524 __ fild_d(Address(rsp, 0));
1525 // float result is rounded later through spilling
1526 break;
1527
1528 case Bytecodes::_f2l:
1529 case Bytecodes::_d2l:
1530 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1531 assert(src->fpu() == 0, "input must be on TOS");
1532 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1533
1534 // instruction sequence too long to inline it here
1535 {
1536 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1537 }
1538 break;
1539
1540 default: ShouldNotReachHere();
1541 }
1542 }
1543
1544 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1545 if (op->init_check()) {
1546 __ cmpb(Address(op->klass()->as_register(),
1547 InstanceKlass::init_state_offset()),
1548 InstanceKlass::fully_initialized);
1549 add_debug_info_for_null_check_here(op->stub()->info());
1550 __ jcc(Assembler::notEqual, *op->stub()->entry());
1551 }
1552 __ allocate_object(op->obj()->as_register(),
1553 op->tmp1()->as_register(),
1554 op->tmp2()->as_register(),
1555 op->header_size(),
1556 op->object_size(),
1557 op->klass()->as_register(),
1558 *op->stub()->entry());
1559 __ bind(*op->stub()->continuation());
1560 }
1561
1562 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1563 Register len = op->len()->as_register();
1564 LP64_ONLY( __ movslq(len, len); )
1565
1566 if (UseSlowPath ||
1567 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1568 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1569 __ jmp(*op->stub()->entry());
1570 } else {
1571 Register tmp1 = op->tmp1()->as_register();
1572 Register tmp2 = op->tmp2()->as_register();
1573 Register tmp3 = op->tmp3()->as_register();
1574 if (len == tmp1) {
1575 tmp1 = tmp3;
1576 } else if (len == tmp2) {
1577 tmp2 = tmp3;
1578 } else if (len == tmp3) {
1579 // everything is ok
1580 } else {
1581 __ mov(tmp3, len);
1582 }
1583 __ allocate_array(op->obj()->as_register(),
1584 len,
1585 tmp1,
1586 tmp2,
1587 arrayOopDesc::header_size(op->type()),
1588 array_element_size(op->type()),
1589 op->klass()->as_register(),
1590 *op->stub()->entry());
1591 }
1592 __ bind(*op->stub()->continuation());
1593 }
1594
1595 void LIR_Assembler::type_profile_helper(Register mdo,
1596 ciMethodData *md, ciProfileData *data,
1597 Register recv, Label* update_done) {
1598 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1599 Label next_test;
1600 // See if the receiver is receiver[n].
1601 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1602 __ jccb(Assembler::notEqual, next_test);
1603 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1604 __ addptr(data_addr, DataLayout::counter_increment);
1605 __ jmp(*update_done);
1606 __ bind(next_test);
1607 }
1608
1609 // Didn't find receiver; find next empty slot and fill it in
1610 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1611 Label next_test;
1612 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1613 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1614 __ jccb(Assembler::notEqual, next_test);
1615 __ movptr(recv_addr, recv);
1616 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1617 __ jmp(*update_done);
1618 __ bind(next_test);
1619 }
1620 }
1621
1622 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1623 // we always need a stub for the failure case.
1624 CodeStub* stub = op->stub();
1625 Register obj = op->object()->as_register();
1626 Register k_RInfo = op->tmp1()->as_register();
1627 Register klass_RInfo = op->tmp2()->as_register();
1628 Register dst = op->result_opr()->as_register();
1629 ciKlass* k = op->klass();
1630 Register Rtmp1 = noreg;
1631
1632 // check if it needs to be profiled
1633 ciMethodData* md = NULL;
1634 ciProfileData* data = NULL;
1635
1636 if (op->should_profile()) {
1637 ciMethod* method = op->profiled_method();
1638 assert(method != NULL, "Should have method");
1639 int bci = op->profiled_bci();
1640 md = method->method_data_or_null();
1641 assert(md != NULL, "Sanity");
1642 data = md->bci_to_data(bci);
1643 assert(data != NULL, "need data for type check");
1644 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1645 }
1646 Label profile_cast_success, profile_cast_failure;
1647 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1648 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1649
1650 if (obj == k_RInfo) {
1651 k_RInfo = dst;
1652 } else if (obj == klass_RInfo) {
1653 klass_RInfo = dst;
1654 }
1655 if (k->is_loaded() && !UseCompressedClassPointers) {
1656 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1657 } else {
1658 Rtmp1 = op->tmp3()->as_register();
1659 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1660 }
1661
1662 assert_different_registers(obj, k_RInfo, klass_RInfo);
1663
1664 __ cmpptr(obj, (int32_t)NULL_WORD);
1665 if (op->should_profile()) {
1666 Label not_null;
1667 __ jccb(Assembler::notEqual, not_null);
1668 // Object is null; update MDO and exit
1669 Register mdo = klass_RInfo;
1670 __ mov_metadata(mdo, md->constant_encoding());
1671 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1672 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1673 __ orl(data_addr, header_bits);
1674 __ jmp(*obj_is_null);
1675 __ bind(not_null);
1676 } else {
1677 __ jcc(Assembler::equal, *obj_is_null);
1678 }
1679
1680 if (!k->is_loaded()) {
1681 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1682 } else {
1683 #ifdef _LP64
1684 __ mov_metadata(k_RInfo, k->constant_encoding());
1685 #endif // _LP64
1686 }
1687 __ verify_oop(obj);
1688
1689 if (op->fast_check()) {
1690 // get object class
1691 // not a safepoint as obj null check happens earlier
1692 #ifdef _LP64
1693 if (UseCompressedClassPointers) {
1694 __ load_klass(Rtmp1, obj);
1695 __ cmpptr(k_RInfo, Rtmp1);
1696 } else {
1697 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1698 }
1699 #else
1700 if (k->is_loaded()) {
1701 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1702 } else {
1703 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1704 }
1705 #endif
1706 __ jcc(Assembler::notEqual, *failure_target);
1707 // successful cast, fall through to profile or jump
1708 } else {
1709 // get object class
1710 // not a safepoint as obj null check happens earlier
1711 __ load_klass(klass_RInfo, obj);
1712 if (k->is_loaded()) {
1713 // See if we get an immediate positive hit
1714 #ifdef _LP64
1715 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1716 #else
1717 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1718 #endif // _LP64
1719 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1720 __ jcc(Assembler::notEqual, *failure_target);
1721 // successful cast, fall through to profile or jump
1722 } else {
1723 // See if we get an immediate positive hit
1724 __ jcc(Assembler::equal, *success_target);
1725 // check for self
1726 #ifdef _LP64
1727 __ cmpptr(klass_RInfo, k_RInfo);
1728 #else
1729 __ cmpklass(klass_RInfo, k->constant_encoding());
1730 #endif // _LP64
1731 __ jcc(Assembler::equal, *success_target);
1732
1733 __ push(klass_RInfo);
1734 #ifdef _LP64
1735 __ push(k_RInfo);
1736 #else
1737 __ pushklass(k->constant_encoding());
1738 #endif // _LP64
1739 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1740 __ pop(klass_RInfo);
1741 __ pop(klass_RInfo);
1742 // result is a boolean
1743 __ cmpl(klass_RInfo, 0);
1744 __ jcc(Assembler::equal, *failure_target);
1745 // successful cast, fall through to profile or jump
1746 }
1747 } else {
1748 // perform the fast part of the checking logic
1749 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1750 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1751 __ push(klass_RInfo);
1752 __ push(k_RInfo);
1753 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1754 __ pop(klass_RInfo);
1755 __ pop(k_RInfo);
1756 // result is a boolean
1757 __ cmpl(k_RInfo, 0);
1758 __ jcc(Assembler::equal, *failure_target);
1759 // successful cast, fall through to profile or jump
1760 }
1761 }
1762 if (op->should_profile()) {
1763 Register mdo = klass_RInfo, recv = k_RInfo;
1764 __ bind(profile_cast_success);
1765 __ mov_metadata(mdo, md->constant_encoding());
1766 __ load_klass(recv, obj);
1767 Label update_done;
1768 type_profile_helper(mdo, md, data, recv, success);
1769 __ jmp(*success);
1770
1771 __ bind(profile_cast_failure);
1772 __ mov_metadata(mdo, md->constant_encoding());
1773 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1774 __ subptr(counter_addr, DataLayout::counter_increment);
1775 __ jmp(*failure);
1776 }
1777 __ jmp(*success);
1778 }
1779
1780
1781 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1782 LIR_Code code = op->code();
1783 if (code == lir_store_check) {
1784 Register value = op->object()->as_register();
1785 Register array = op->array()->as_register();
1786 Register k_RInfo = op->tmp1()->as_register();
1787 Register klass_RInfo = op->tmp2()->as_register();
1788 Register Rtmp1 = op->tmp3()->as_register();
1789
1790 CodeStub* stub = op->stub();
1791
1792 // check if it needs to be profiled
1793 ciMethodData* md = NULL;
1794 ciProfileData* data = NULL;
1795
1796 if (op->should_profile()) {
1797 ciMethod* method = op->profiled_method();
1798 assert(method != NULL, "Should have method");
1799 int bci = op->profiled_bci();
1800 md = method->method_data_or_null();
1801 assert(md != NULL, "Sanity");
1802 data = md->bci_to_data(bci);
1803 assert(data != NULL, "need data for type check");
1804 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1805 }
1806 Label profile_cast_success, profile_cast_failure, done;
1807 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1808 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1809
1810 __ cmpptr(value, (int32_t)NULL_WORD);
1811 if (op->should_profile()) {
1812 Label not_null;
1813 __ jccb(Assembler::notEqual, not_null);
1814 // Object is null; update MDO and exit
1815 Register mdo = klass_RInfo;
1816 __ mov_metadata(mdo, md->constant_encoding());
1817 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1818 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1819 __ orl(data_addr, header_bits);
1820 __ jmp(done);
1821 __ bind(not_null);
1822 } else {
1823 __ jcc(Assembler::equal, done);
1824 }
1825
1826 add_debug_info_for_null_check_here(op->info_for_exception());
1827 __ load_klass(k_RInfo, array);
1828 __ load_klass(klass_RInfo, value);
1829
1830 // get instance klass (it's already uncompressed)
1831 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1832 // perform the fast part of the checking logic
1833 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1834 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1835 __ push(klass_RInfo);
1836 __ push(k_RInfo);
1837 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1838 __ pop(klass_RInfo);
1839 __ pop(k_RInfo);
1840 // result is a boolean
1841 __ cmpl(k_RInfo, 0);
1842 __ jcc(Assembler::equal, *failure_target);
1843 // fall through to the success case
1844
1845 if (op->should_profile()) {
1846 Register mdo = klass_RInfo, recv = k_RInfo;
1847 __ bind(profile_cast_success);
1848 __ mov_metadata(mdo, md->constant_encoding());
1849 __ load_klass(recv, value);
1850 Label update_done;
1851 type_profile_helper(mdo, md, data, recv, &done);
1852 __ jmpb(done);
1853
1854 __ bind(profile_cast_failure);
1855 __ mov_metadata(mdo, md->constant_encoding());
1856 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1857 __ subptr(counter_addr, DataLayout::counter_increment);
1858 __ jmp(*stub->entry());
1859 }
1860
1861 __ bind(done);
1862 } else
1863 if (code == lir_checkcast) {
1864 Register obj = op->object()->as_register();
1865 Register dst = op->result_opr()->as_register();
1866 Label success;
1867 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1868 __ bind(success);
1869 if (dst != obj) {
1870 __ mov(dst, obj);
1871 }
1872 } else
1873 if (code == lir_instanceof) {
1874 Register obj = op->object()->as_register();
1875 Register dst = op->result_opr()->as_register();
1876 Label success, failure, done;
1877 emit_typecheck_helper(op, &success, &failure, &failure);
1878 __ bind(failure);
1879 __ xorptr(dst, dst);
1880 __ jmpb(done);
1881 __ bind(success);
1882 __ movptr(dst, 1);
1883 __ bind(done);
1884 } else {
1885 ShouldNotReachHere();
1886 }
1887
1888 }
1889
1890
1891 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1892 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1893 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1894 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1895 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1896 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1897 Register addr = op->addr()->as_register();
1898 if (os::is_MP()) {
1899 __ lock();
1900 }
1901 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1902
1903 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1904 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1905 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1906 Register newval = op->new_value()->as_register();
1907 Register cmpval = op->cmp_value()->as_register();
1908 assert(cmpval == rax, "wrong register");
1909 assert(newval != NULL, "new val must be register");
1910 assert(cmpval != newval, "cmp and new values must be in different registers");
1911 assert(cmpval != addr, "cmp and addr must be in different registers");
1912 assert(newval != addr, "new value and addr must be in different registers");
1913
1914 if ( op->code() == lir_cas_obj) {
1915 #ifdef _LP64
1916 if (UseCompressedOops) {
1917 if (UseShenandoahGC && ShenandoahCASBarrier) {
1918 Register tmp1 = op->tmp1()->as_register();
1919 Register tmp2 = op->tmp2()->as_register();
1920
1921 __ encode_heap_oop(cmpval);
1922 __ mov(rscratch1, newval);
1923 __ encode_heap_oop(rscratch1);
1924 __ cmpxchg_oop_shenandoah(NULL, Address(addr, 0), cmpval, rscratch1, true, tmp1, tmp2);
1925 } else {
1926 __ encode_heap_oop(cmpval);
1927 __ mov(rscratch1, newval);
1928 __ encode_heap_oop(rscratch1);
1929 if (os::is_MP()) {
1930 __ lock();
1931 }
1932 // cmpval (rax) is implicitly used by this instruction
1933 __ cmpxchgl(rscratch1, Address(addr, 0));
1934 }
1935 } else
1936 #endif
1937 {
1938 if (UseShenandoahGC && ShenandoahCASBarrier) {
1939 Register tmp1 = op->tmp1()->as_register();
1940 Register tmp2 = op->tmp2()->as_register();
1941 __ cmpxchg_oop_shenandoah(NULL, Address(addr, 0), cmpval, newval, true, tmp1, tmp2);
1942 } else {
1943 if (os::is_MP()) {
1944 __ lock();
1945 }
1946 __ cmpxchgptr(newval, Address(addr, 0));
1947 }
1948 }
1949 } else {
1950 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1951 if (os::is_MP()) {
1952 __ lock();
1953 }
1954 __ cmpxchgl(newval, Address(addr, 0));
1955 }
1956 #ifdef _LP64
1957 } else if (op->code() == lir_cas_long) {
1958 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1959 Register newval = op->new_value()->as_register_lo();
1960 Register cmpval = op->cmp_value()->as_register_lo();
1961 assert(cmpval == rax, "wrong register");
1962 assert(newval != NULL, "new val must be register");
1963 assert(cmpval != newval, "cmp and new values must be in different registers");
1964 assert(cmpval != addr, "cmp and addr must be in different registers");
1965 assert(newval != addr, "new value and addr must be in different registers");
1966 if (os::is_MP()) {
1967 __ lock();
1968 }
1969 __ cmpxchgq(newval, Address(addr, 0));
1970 #endif // _LP64
1971 } else {
1972 Unimplemented();
1973 }
1974 }
1975
1976 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1977 Assembler::Condition acond, ncond;
1978 switch (condition) {
1979 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1980 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1981 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1982 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1983 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1984 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1985 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1986 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1987 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1988 ShouldNotReachHere();
1989 }
1990
1991 if (opr1->is_cpu_register()) {
1992 reg2reg(opr1, result);
1993 } else if (opr1->is_stack()) {
1994 stack2reg(opr1, result, result->type());
1995 } else if (opr1->is_constant()) {
1996 const2reg(opr1, result, lir_patch_none, NULL);
1997 } else {
1998 ShouldNotReachHere();
1999 }
2000
2001 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2002 // optimized version that does not require a branch
2003 if (opr2->is_single_cpu()) {
2004 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2005 __ cmov(ncond, result->as_register(), opr2->as_register());
2006 } else if (opr2->is_double_cpu()) {
2007 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2008 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2009 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2011 } else if (opr2->is_single_stack()) {
2012 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2013 } else if (opr2->is_double_stack()) {
2014 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2015 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2016 } else {
2017 ShouldNotReachHere();
2018 }
2019
2020 } else {
2021 Label skip;
2022 __ jcc (acond, skip);
2023 if (opr2->is_cpu_register()) {
2024 reg2reg(opr2, result);
2025 } else if (opr2->is_stack()) {
2026 stack2reg(opr2, result, result->type());
2027 } else if (opr2->is_constant()) {
2028 const2reg(opr2, result, lir_patch_none, NULL);
2029 } else {
2030 ShouldNotReachHere();
2031 }
2032 __ bind(skip);
2033 }
2034 }
2035
2036
2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2038 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2039
2040 if (left->is_single_cpu()) {
2041 assert(left == dest, "left and dest must be equal");
2042 Register lreg = left->as_register();
2043
2044 if (right->is_single_cpu()) {
2045 // cpu register - cpu register
2046 Register rreg = right->as_register();
2047 switch (code) {
2048 case lir_add: __ addl (lreg, rreg); break;
2049 case lir_sub: __ subl (lreg, rreg); break;
2050 case lir_mul: __ imull(lreg, rreg); break;
2051 default: ShouldNotReachHere();
2052 }
2053
2054 } else if (right->is_stack()) {
2055 // cpu register - stack
2056 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2057 switch (code) {
2058 case lir_add: __ addl(lreg, raddr); break;
2059 case lir_sub: __ subl(lreg, raddr); break;
2060 default: ShouldNotReachHere();
2061 }
2062
2063 } else if (right->is_constant()) {
2064 // cpu register - constant
2065 jint c = right->as_constant_ptr()->as_jint();
2066 switch (code) {
2067 case lir_add: {
2068 __ incrementl(lreg, c);
2069 break;
2070 }
2071 case lir_sub: {
2072 __ decrementl(lreg, c);
2073 break;
2074 }
2075 default: ShouldNotReachHere();
2076 }
2077
2078 } else {
2079 ShouldNotReachHere();
2080 }
2081
2082 } else if (left->is_double_cpu()) {
2083 assert(left == dest, "left and dest must be equal");
2084 Register lreg_lo = left->as_register_lo();
2085 Register lreg_hi = left->as_register_hi();
2086
2087 if (right->is_double_cpu()) {
2088 // cpu register - cpu register
2089 Register rreg_lo = right->as_register_lo();
2090 Register rreg_hi = right->as_register_hi();
2091 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2092 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2093 switch (code) {
2094 case lir_add:
2095 __ addptr(lreg_lo, rreg_lo);
2096 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2097 break;
2098 case lir_sub:
2099 __ subptr(lreg_lo, rreg_lo);
2100 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2101 break;
2102 case lir_mul:
2103 #ifdef _LP64
2104 __ imulq(lreg_lo, rreg_lo);
2105 #else
2106 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2107 __ imull(lreg_hi, rreg_lo);
2108 __ imull(rreg_hi, lreg_lo);
2109 __ addl (rreg_hi, lreg_hi);
2110 __ mull (rreg_lo);
2111 __ addl (lreg_hi, rreg_hi);
2112 #endif // _LP64
2113 break;
2114 default:
2115 ShouldNotReachHere();
2116 }
2117
2118 } else if (right->is_constant()) {
2119 // cpu register - constant
2120 #ifdef _LP64
2121 jlong c = right->as_constant_ptr()->as_jlong_bits();
2122 __ movptr(r10, (intptr_t) c);
2123 switch (code) {
2124 case lir_add:
2125 __ addptr(lreg_lo, r10);
2126 break;
2127 case lir_sub:
2128 __ subptr(lreg_lo, r10);
2129 break;
2130 default:
2131 ShouldNotReachHere();
2132 }
2133 #else
2134 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2135 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2136 switch (code) {
2137 case lir_add:
2138 __ addptr(lreg_lo, c_lo);
2139 __ adcl(lreg_hi, c_hi);
2140 break;
2141 case lir_sub:
2142 __ subptr(lreg_lo, c_lo);
2143 __ sbbl(lreg_hi, c_hi);
2144 break;
2145 default:
2146 ShouldNotReachHere();
2147 }
2148 #endif // _LP64
2149
2150 } else {
2151 ShouldNotReachHere();
2152 }
2153
2154 } else if (left->is_single_xmm()) {
2155 assert(left == dest, "left and dest must be equal");
2156 XMMRegister lreg = left->as_xmm_float_reg();
2157
2158 if (right->is_single_xmm()) {
2159 XMMRegister rreg = right->as_xmm_float_reg();
2160 switch (code) {
2161 case lir_add: __ addss(lreg, rreg); break;
2162 case lir_sub: __ subss(lreg, rreg); break;
2163 case lir_mul_strictfp: // fall through
2164 case lir_mul: __ mulss(lreg, rreg); break;
2165 case lir_div_strictfp: // fall through
2166 case lir_div: __ divss(lreg, rreg); break;
2167 default: ShouldNotReachHere();
2168 }
2169 } else {
2170 Address raddr;
2171 if (right->is_single_stack()) {
2172 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2173 } else if (right->is_constant()) {
2174 // hack for now
2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2176 } else {
2177 ShouldNotReachHere();
2178 }
2179 switch (code) {
2180 case lir_add: __ addss(lreg, raddr); break;
2181 case lir_sub: __ subss(lreg, raddr); break;
2182 case lir_mul_strictfp: // fall through
2183 case lir_mul: __ mulss(lreg, raddr); break;
2184 case lir_div_strictfp: // fall through
2185 case lir_div: __ divss(lreg, raddr); break;
2186 default: ShouldNotReachHere();
2187 }
2188 }
2189
2190 } else if (left->is_double_xmm()) {
2191 assert(left == dest, "left and dest must be equal");
2192
2193 XMMRegister lreg = left->as_xmm_double_reg();
2194 if (right->is_double_xmm()) {
2195 XMMRegister rreg = right->as_xmm_double_reg();
2196 switch (code) {
2197 case lir_add: __ addsd(lreg, rreg); break;
2198 case lir_sub: __ subsd(lreg, rreg); break;
2199 case lir_mul_strictfp: // fall through
2200 case lir_mul: __ mulsd(lreg, rreg); break;
2201 case lir_div_strictfp: // fall through
2202 case lir_div: __ divsd(lreg, rreg); break;
2203 default: ShouldNotReachHere();
2204 }
2205 } else {
2206 Address raddr;
2207 if (right->is_double_stack()) {
2208 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2209 } else if (right->is_constant()) {
2210 // hack for now
2211 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2212 } else {
2213 ShouldNotReachHere();
2214 }
2215 switch (code) {
2216 case lir_add: __ addsd(lreg, raddr); break;
2217 case lir_sub: __ subsd(lreg, raddr); break;
2218 case lir_mul_strictfp: // fall through
2219 case lir_mul: __ mulsd(lreg, raddr); break;
2220 case lir_div_strictfp: // fall through
2221 case lir_div: __ divsd(lreg, raddr); break;
2222 default: ShouldNotReachHere();
2223 }
2224 }
2225
2226 } else if (left->is_single_fpu()) {
2227 assert(dest->is_single_fpu(), "fpu stack allocation required");
2228
2229 if (right->is_single_fpu()) {
2230 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2231
2232 } else {
2233 assert(left->fpu_regnr() == 0, "left must be on TOS");
2234 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2235
2236 Address raddr;
2237 if (right->is_single_stack()) {
2238 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2239 } else if (right->is_constant()) {
2240 address const_addr = float_constant(right->as_jfloat());
2241 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2242 // hack for now
2243 raddr = __ as_Address(InternalAddress(const_addr));
2244 } else {
2245 ShouldNotReachHere();
2246 }
2247
2248 switch (code) {
2249 case lir_add: __ fadd_s(raddr); break;
2250 case lir_sub: __ fsub_s(raddr); break;
2251 case lir_mul_strictfp: // fall through
2252 case lir_mul: __ fmul_s(raddr); break;
2253 case lir_div_strictfp: // fall through
2254 case lir_div: __ fdiv_s(raddr); break;
2255 default: ShouldNotReachHere();
2256 }
2257 }
2258
2259 } else if (left->is_double_fpu()) {
2260 assert(dest->is_double_fpu(), "fpu stack allocation required");
2261
2262 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2263 // Double values require special handling for strictfp mul/div on x86
2264 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2265 __ fmulp(left->fpu_regnrLo() + 1);
2266 }
2267
2268 if (right->is_double_fpu()) {
2269 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2270
2271 } else {
2272 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2273 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2274
2275 Address raddr;
2276 if (right->is_double_stack()) {
2277 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2278 } else if (right->is_constant()) {
2279 // hack for now
2280 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2281 } else {
2282 ShouldNotReachHere();
2283 }
2284
2285 switch (code) {
2286 case lir_add: __ fadd_d(raddr); break;
2287 case lir_sub: __ fsub_d(raddr); break;
2288 case lir_mul_strictfp: // fall through
2289 case lir_mul: __ fmul_d(raddr); break;
2290 case lir_div_strictfp: // fall through
2291 case lir_div: __ fdiv_d(raddr); break;
2292 default: ShouldNotReachHere();
2293 }
2294 }
2295
2296 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2297 // Double values require special handling for strictfp mul/div on x86
2298 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2299 __ fmulp(dest->fpu_regnrLo() + 1);
2300 }
2301
2302 } else if (left->is_single_stack() || left->is_address()) {
2303 assert(left == dest, "left and dest must be equal");
2304
2305 Address laddr;
2306 if (left->is_single_stack()) {
2307 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2308 } else if (left->is_address()) {
2309 laddr = as_Address(left->as_address_ptr());
2310 } else {
2311 ShouldNotReachHere();
2312 }
2313
2314 if (right->is_single_cpu()) {
2315 Register rreg = right->as_register();
2316 switch (code) {
2317 case lir_add: __ addl(laddr, rreg); break;
2318 case lir_sub: __ subl(laddr, rreg); break;
2319 default: ShouldNotReachHere();
2320 }
2321 } else if (right->is_constant()) {
2322 jint c = right->as_constant_ptr()->as_jint();
2323 switch (code) {
2324 case lir_add: {
2325 __ incrementl(laddr, c);
2326 break;
2327 }
2328 case lir_sub: {
2329 __ decrementl(laddr, c);
2330 break;
2331 }
2332 default: ShouldNotReachHere();
2333 }
2334 } else {
2335 ShouldNotReachHere();
2336 }
2337
2338 } else {
2339 ShouldNotReachHere();
2340 }
2341 }
2342
2343 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2344 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2345 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2346 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2347
2348 bool left_is_tos = (left_index == 0);
2349 bool dest_is_tos = (dest_index == 0);
2350 int non_tos_index = (left_is_tos ? right_index : left_index);
2351
2352 switch (code) {
2353 case lir_add:
2354 if (pop_fpu_stack) __ faddp(non_tos_index);
2355 else if (dest_is_tos) __ fadd (non_tos_index);
2356 else __ fadda(non_tos_index);
2357 break;
2358
2359 case lir_sub:
2360 if (left_is_tos) {
2361 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2362 else if (dest_is_tos) __ fsub (non_tos_index);
2363 else __ fsubra(non_tos_index);
2364 } else {
2365 if (pop_fpu_stack) __ fsubp (non_tos_index);
2366 else if (dest_is_tos) __ fsubr (non_tos_index);
2367 else __ fsuba (non_tos_index);
2368 }
2369 break;
2370
2371 case lir_mul_strictfp: // fall through
2372 case lir_mul:
2373 if (pop_fpu_stack) __ fmulp(non_tos_index);
2374 else if (dest_is_tos) __ fmul (non_tos_index);
2375 else __ fmula(non_tos_index);
2376 break;
2377
2378 case lir_div_strictfp: // fall through
2379 case lir_div:
2380 if (left_is_tos) {
2381 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2382 else if (dest_is_tos) __ fdiv (non_tos_index);
2383 else __ fdivra(non_tos_index);
2384 } else {
2385 if (pop_fpu_stack) __ fdivp (non_tos_index);
2386 else if (dest_is_tos) __ fdivr (non_tos_index);
2387 else __ fdiva (non_tos_index);
2388 }
2389 break;
2390
2391 case lir_rem:
2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2393 __ fremr(noreg);
2394 break;
2395
2396 default:
2397 ShouldNotReachHere();
2398 }
2399 }
2400
2401
2402 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2403 if (value->is_double_xmm()) {
2404 switch(code) {
2405 case lir_abs :
2406 {
2407 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2408 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2409 }
2410 __ andpd(dest->as_xmm_double_reg(),
2411 ExternalAddress((address)double_signmask_pool));
2412 }
2413 break;
2414
2415 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2416 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2417 default : ShouldNotReachHere();
2418 }
2419
2420 } else if (value->is_double_fpu()) {
2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2422 switch(code) {
2423 case lir_abs : __ fabs() ; break;
2424 case lir_sqrt : __ fsqrt(); break;
2425 default : ShouldNotReachHere();
2426 }
2427 } else {
2428 Unimplemented();
2429 }
2430 }
2431
2432 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2433 // assert(left->destroys_register(), "check");
2434 if (left->is_single_cpu()) {
2435 Register reg = left->as_register();
2436 if (right->is_constant()) {
2437 int val = right->as_constant_ptr()->as_jint();
2438 switch (code) {
2439 case lir_logic_and: __ andl (reg, val); break;
2440 case lir_logic_or: __ orl (reg, val); break;
2441 case lir_logic_xor: __ xorl (reg, val); break;
2442 default: ShouldNotReachHere();
2443 }
2444 } else if (right->is_stack()) {
2445 // added support for stack operands
2446 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2447 switch (code) {
2448 case lir_logic_and: __ andl (reg, raddr); break;
2449 case lir_logic_or: __ orl (reg, raddr); break;
2450 case lir_logic_xor: __ xorl (reg, raddr); break;
2451 default: ShouldNotReachHere();
2452 }
2453 } else {
2454 Register rright = right->as_register();
2455 switch (code) {
2456 case lir_logic_and: __ andptr (reg, rright); break;
2457 case lir_logic_or : __ orptr (reg, rright); break;
2458 case lir_logic_xor: __ xorptr (reg, rright); break;
2459 default: ShouldNotReachHere();
2460 }
2461 }
2462 move_regs(reg, dst->as_register());
2463 } else {
2464 Register l_lo = left->as_register_lo();
2465 Register l_hi = left->as_register_hi();
2466 if (right->is_constant()) {
2467 #ifdef _LP64
2468 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2469 switch (code) {
2470 case lir_logic_and:
2471 __ andq(l_lo, rscratch1);
2472 break;
2473 case lir_logic_or:
2474 __ orq(l_lo, rscratch1);
2475 break;
2476 case lir_logic_xor:
2477 __ xorq(l_lo, rscratch1);
2478 break;
2479 default: ShouldNotReachHere();
2480 }
2481 #else
2482 int r_lo = right->as_constant_ptr()->as_jint_lo();
2483 int r_hi = right->as_constant_ptr()->as_jint_hi();
2484 switch (code) {
2485 case lir_logic_and:
2486 __ andl(l_lo, r_lo);
2487 __ andl(l_hi, r_hi);
2488 break;
2489 case lir_logic_or:
2490 __ orl(l_lo, r_lo);
2491 __ orl(l_hi, r_hi);
2492 break;
2493 case lir_logic_xor:
2494 __ xorl(l_lo, r_lo);
2495 __ xorl(l_hi, r_hi);
2496 break;
2497 default: ShouldNotReachHere();
2498 }
2499 #endif // _LP64
2500 } else {
2501 #ifdef _LP64
2502 Register r_lo;
2503 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2504 r_lo = right->as_register();
2505 } else {
2506 r_lo = right->as_register_lo();
2507 }
2508 #else
2509 Register r_lo = right->as_register_lo();
2510 Register r_hi = right->as_register_hi();
2511 assert(l_lo != r_hi, "overwriting registers");
2512 #endif
2513 switch (code) {
2514 case lir_logic_and:
2515 __ andptr(l_lo, r_lo);
2516 NOT_LP64(__ andptr(l_hi, r_hi);)
2517 break;
2518 case lir_logic_or:
2519 __ orptr(l_lo, r_lo);
2520 NOT_LP64(__ orptr(l_hi, r_hi);)
2521 break;
2522 case lir_logic_xor:
2523 __ xorptr(l_lo, r_lo);
2524 NOT_LP64(__ xorptr(l_hi, r_hi);)
2525 break;
2526 default: ShouldNotReachHere();
2527 }
2528 }
2529
2530 Register dst_lo = dst->as_register_lo();
2531 Register dst_hi = dst->as_register_hi();
2532
2533 #ifdef _LP64
2534 move_regs(l_lo, dst_lo);
2535 #else
2536 if (dst_lo == l_hi) {
2537 assert(dst_hi != l_lo, "overwriting registers");
2538 move_regs(l_hi, dst_hi);
2539 move_regs(l_lo, dst_lo);
2540 } else {
2541 assert(dst_lo != l_hi, "overwriting registers");
2542 move_regs(l_lo, dst_lo);
2543 move_regs(l_hi, dst_hi);
2544 }
2545 #endif // _LP64
2546 }
2547 }
2548
2549
2550 // we assume that rax, and rdx can be overwritten
2551 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2552
2553 assert(left->is_single_cpu(), "left must be register");
2554 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2555 assert(result->is_single_cpu(), "result must be register");
2556
2557 // assert(left->destroys_register(), "check");
2558 // assert(right->destroys_register(), "check");
2559
2560 Register lreg = left->as_register();
2561 Register dreg = result->as_register();
2562
2563 if (right->is_constant()) {
2564 int divisor = right->as_constant_ptr()->as_jint();
2565 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2566 if (code == lir_idiv) {
2567 assert(lreg == rax, "must be rax,");
2568 assert(temp->as_register() == rdx, "tmp register must be rdx");
2569 __ cdql(); // sign extend into rdx:rax
2570 if (divisor == 2) {
2571 __ subl(lreg, rdx);
2572 } else {
2573 __ andl(rdx, divisor - 1);
2574 __ addl(lreg, rdx);
2575 }
2576 __ sarl(lreg, log2_intptr(divisor));
2577 move_regs(lreg, dreg);
2578 } else if (code == lir_irem) {
2579 Label done;
2580 __ mov(dreg, lreg);
2581 __ andl(dreg, 0x80000000 | (divisor - 1));
2582 __ jcc(Assembler::positive, done);
2583 __ decrement(dreg);
2584 __ orl(dreg, ~(divisor - 1));
2585 __ increment(dreg);
2586 __ bind(done);
2587 } else {
2588 ShouldNotReachHere();
2589 }
2590 } else {
2591 Register rreg = right->as_register();
2592 assert(lreg == rax, "left register must be rax,");
2593 assert(rreg != rdx, "right register must not be rdx");
2594 assert(temp->as_register() == rdx, "tmp register must be rdx");
2595
2596 move_regs(lreg, rax);
2597
2598 int idivl_offset = __ corrected_idivl(rreg);
2599 add_debug_info_for_div0(idivl_offset, info);
2600 if (code == lir_irem) {
2601 move_regs(rdx, dreg); // result is in rdx
2602 } else {
2603 move_regs(rax, dreg);
2604 }
2605 }
2606 }
2607
2608
2609 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2610 if (opr1->is_single_cpu()) {
2611 Register reg1 = opr1->as_register();
2612 if (opr2->is_single_cpu()) {
2613 // cpu register - cpu register
2614 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2615 __ cmpoopptr(reg1, opr2->as_register());
2616 } else {
2617 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2618 __ cmpl(reg1, opr2->as_register());
2619 }
2620 } else if (opr2->is_stack()) {
2621 // cpu register - stack
2622 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2623 __ cmpoopptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2624 } else {
2625 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2626 }
2627 } else if (opr2->is_constant()) {
2628 // cpu register - constant
2629 LIR_Const* c = opr2->as_constant_ptr();
2630 if (c->type() == T_INT) {
2631 __ cmpl(reg1, c->as_jint());
2632 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2633 // In 64bit oops are single register
2634 jobject o = c->as_jobject();
2635 if (o == NULL) {
2636 __ cmpptr(reg1, (int32_t)NULL_WORD);
2637 } else {
2638 #ifdef _LP64
2639 __ movoop(rscratch1, o);
2640 __ cmpoopptr(reg1, rscratch1);
2641 #else
2642 __ cmpoop(reg1, c->as_jobject());
2643 #endif // _LP64
2644 }
2645 } else {
2646 fatal("unexpected type: %s", basictype_to_str(c->type()));
2647 }
2648 // cpu register - address
2649 } else if (opr2->is_address()) {
2650 if (op->info() != NULL) {
2651 add_debug_info_for_null_check_here(op->info());
2652 }
2653 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2654 } else {
2655 ShouldNotReachHere();
2656 }
2657
2658 } else if(opr1->is_double_cpu()) {
2659 Register xlo = opr1->as_register_lo();
2660 Register xhi = opr1->as_register_hi();
2661 if (opr2->is_double_cpu()) {
2662 #ifdef _LP64
2663 __ cmpptr(xlo, opr2->as_register_lo());
2664 #else
2665 // cpu register - cpu register
2666 Register ylo = opr2->as_register_lo();
2667 Register yhi = opr2->as_register_hi();
2668 __ subl(xlo, ylo);
2669 __ sbbl(xhi, yhi);
2670 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2671 __ orl(xhi, xlo);
2672 }
2673 #endif // _LP64
2674 } else if (opr2->is_constant()) {
2675 // cpu register - constant 0
2676 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2677 #ifdef _LP64
2678 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2679 #else
2680 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2681 __ orl(xhi, xlo);
2682 #endif // _LP64
2683 } else {
2684 ShouldNotReachHere();
2685 }
2686
2687 } else if (opr1->is_single_xmm()) {
2688 XMMRegister reg1 = opr1->as_xmm_float_reg();
2689 if (opr2->is_single_xmm()) {
2690 // xmm register - xmm register
2691 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2692 } else if (opr2->is_stack()) {
2693 // xmm register - stack
2694 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2695 } else if (opr2->is_constant()) {
2696 // xmm register - constant
2697 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2698 } else if (opr2->is_address()) {
2699 // xmm register - address
2700 if (op->info() != NULL) {
2701 add_debug_info_for_null_check_here(op->info());
2702 }
2703 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2704 } else {
2705 ShouldNotReachHere();
2706 }
2707
2708 } else if (opr1->is_double_xmm()) {
2709 XMMRegister reg1 = opr1->as_xmm_double_reg();
2710 if (opr2->is_double_xmm()) {
2711 // xmm register - xmm register
2712 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2713 } else if (opr2->is_stack()) {
2714 // xmm register - stack
2715 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2716 } else if (opr2->is_constant()) {
2717 // xmm register - constant
2718 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2719 } else if (opr2->is_address()) {
2720 // xmm register - address
2721 if (op->info() != NULL) {
2722 add_debug_info_for_null_check_here(op->info());
2723 }
2724 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2725 } else {
2726 ShouldNotReachHere();
2727 }
2728
2729 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2730 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2731 assert(opr2->is_fpu_register(), "both must be registers");
2732 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2733
2734 } else if (opr1->is_address() && opr2->is_constant()) {
2735 LIR_Const* c = opr2->as_constant_ptr();
2736 #ifdef _LP64
2737 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2738 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2739 __ movoop(rscratch1, c->as_jobject());
2740 }
2741 #endif // LP64
2742 if (op->info() != NULL) {
2743 add_debug_info_for_null_check_here(op->info());
2744 }
2745 // special case: address - constant
2746 LIR_Address* addr = opr1->as_address_ptr();
2747 if (c->type() == T_INT) {
2748 __ cmpl(as_Address(addr), c->as_jint());
2749 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2750 #ifdef _LP64
2751 // %%% Make this explode if addr isn't reachable until we figure out a
2752 // better strategy by giving noreg as the temp for as_Address
2753 __ cmpoopptr(rscratch1, as_Address(addr, noreg));
2754 #else
2755 __ cmpoop(as_Address(addr), c->as_jobject());
2756 #endif // _LP64
2757 } else {
2758 ShouldNotReachHere();
2759 }
2760
2761 } else {
2762 ShouldNotReachHere();
2763 }
2764 }
2765
2766 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2767 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2768 if (left->is_single_xmm()) {
2769 assert(right->is_single_xmm(), "must match");
2770 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2771 } else if (left->is_double_xmm()) {
2772 assert(right->is_double_xmm(), "must match");
2773 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2774
2775 } else {
2776 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2777 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2778
2779 assert(left->fpu() == 0, "left must be on TOS");
2780 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2781 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2782 }
2783 } else {
2784 assert(code == lir_cmp_l2i, "check");
2785 #ifdef _LP64
2786 Label done;
2787 Register dest = dst->as_register();
2788 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2789 __ movl(dest, -1);
2790 __ jccb(Assembler::less, done);
2791 __ set_byte_if_not_zero(dest);
2792 __ movzbl(dest, dest);
2793 __ bind(done);
2794 #else
2795 __ lcmp2int(left->as_register_hi(),
2796 left->as_register_lo(),
2797 right->as_register_hi(),
2798 right->as_register_lo());
2799 move_regs(left->as_register_hi(), dst->as_register());
2800 #endif // _LP64
2801 }
2802 }
2803
2804
2805 void LIR_Assembler::align_call(LIR_Code code) {
2806 if (os::is_MP()) {
2807 // make sure that the displacement word of the call ends up word aligned
2808 int offset = __ offset();
2809 switch (code) {
2810 case lir_static_call:
2811 case lir_optvirtual_call:
2812 case lir_dynamic_call:
2813 offset += NativeCall::displacement_offset;
2814 break;
2815 case lir_icvirtual_call:
2816 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2817 break;
2818 case lir_virtual_call: // currently, sparc-specific for niagara
2819 default: ShouldNotReachHere();
2820 }
2821 __ align(BytesPerWord, offset);
2822 }
2823 }
2824
2825
2826 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2827 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2828 "must be aligned");
2829 __ call(AddressLiteral(op->addr(), rtype));
2830 add_call_info(code_offset(), op->info());
2831 }
2832
2833
2834 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2835 __ ic_call(op->addr());
2836 add_call_info(code_offset(), op->info());
2837 assert(!os::is_MP() ||
2838 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2839 "must be aligned");
2840 }
2841
2842
2843 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2844 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2845 ShouldNotReachHere();
2846 }
2847
2848
2849 void LIR_Assembler::emit_static_call_stub() {
2850 address call_pc = __ pc();
2851 address stub = __ start_a_stub(call_stub_size());
2852 if (stub == NULL) {
2853 bailout("static call stub overflow");
2854 return;
2855 }
2856
2857 int start = __ offset();
2858 if (os::is_MP()) {
2859 // make sure that the displacement word of the call ends up word aligned
2860 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2861 }
2862 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2863 __ mov_metadata(rbx, (Metadata*)NULL);
2864 // must be set to -1 at code generation time
2865 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2866 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2867 __ jump(RuntimeAddress(__ pc()));
2868
2869 if (UseAOT) {
2870 // Trampoline to aot code
2871 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2872 #ifdef _LP64
2873 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2874 #else
2875 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2876 #endif
2877 __ jmp(rax);
2878 }
2879 assert(__ offset() - start <= call_stub_size(), "stub too big");
2880 __ end_a_stub();
2881 }
2882
2883
2884 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2885 assert(exceptionOop->as_register() == rax, "must match");
2886 assert(exceptionPC->as_register() == rdx, "must match");
2887
2888 // exception object is not added to oop map by LinearScan
2889 // (LinearScan assumes that no oops are in fixed registers)
2890 info->add_register_oop(exceptionOop);
2891 Runtime1::StubID unwind_id;
2892
2893 // get current pc information
2894 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2895 int pc_for_athrow_offset = __ offset();
2896 InternalAddress pc_for_athrow(__ pc());
2897 __ lea(exceptionPC->as_register(), pc_for_athrow);
2898 add_call_info(pc_for_athrow_offset, info); // for exception handler
2899
2900 __ verify_not_null_oop(rax);
2901 // search an exception handler (rax: exception oop, rdx: throwing pc)
2902 if (compilation()->has_fpu_code()) {
2903 unwind_id = Runtime1::handle_exception_id;
2904 } else {
2905 unwind_id = Runtime1::handle_exception_nofpu_id;
2906 }
2907 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2908
2909 // enough room for two byte trap
2910 __ nop();
2911 }
2912
2913
2914 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2915 assert(exceptionOop->as_register() == rax, "must match");
2916
2917 __ jmp(_unwind_handler_entry);
2918 }
2919
2920
2921 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2922
2923 // optimized version for linear scan:
2924 // * count must be already in ECX (guaranteed by LinearScan)
2925 // * left and dest must be equal
2926 // * tmp must be unused
2927 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2928 assert(left == dest, "left and dest must be equal");
2929 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2930
2931 if (left->is_single_cpu()) {
2932 Register value = left->as_register();
2933 assert(value != SHIFT_count, "left cannot be ECX");
2934
2935 switch (code) {
2936 case lir_shl: __ shll(value); break;
2937 case lir_shr: __ sarl(value); break;
2938 case lir_ushr: __ shrl(value); break;
2939 default: ShouldNotReachHere();
2940 }
2941 } else if (left->is_double_cpu()) {
2942 Register lo = left->as_register_lo();
2943 Register hi = left->as_register_hi();
2944 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2945 #ifdef _LP64
2946 switch (code) {
2947 case lir_shl: __ shlptr(lo); break;
2948 case lir_shr: __ sarptr(lo); break;
2949 case lir_ushr: __ shrptr(lo); break;
2950 default: ShouldNotReachHere();
2951 }
2952 #else
2953
2954 switch (code) {
2955 case lir_shl: __ lshl(hi, lo); break;
2956 case lir_shr: __ lshr(hi, lo, true); break;
2957 case lir_ushr: __ lshr(hi, lo, false); break;
2958 default: ShouldNotReachHere();
2959 }
2960 #endif // LP64
2961 } else {
2962 ShouldNotReachHere();
2963 }
2964 }
2965
2966
2967 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2968 if (dest->is_single_cpu()) {
2969 // first move left into dest so that left is not destroyed by the shift
2970 Register value = dest->as_register();
2971 count = count & 0x1F; // Java spec
2972
2973 move_regs(left->as_register(), value);
2974 switch (code) {
2975 case lir_shl: __ shll(value, count); break;
2976 case lir_shr: __ sarl(value, count); break;
2977 case lir_ushr: __ shrl(value, count); break;
2978 default: ShouldNotReachHere();
2979 }
2980 } else if (dest->is_double_cpu()) {
2981 #ifndef _LP64
2982 Unimplemented();
2983 #else
2984 // first move left into dest so that left is not destroyed by the shift
2985 Register value = dest->as_register_lo();
2986 count = count & 0x1F; // Java spec
2987
2988 move_regs(left->as_register_lo(), value);
2989 switch (code) {
2990 case lir_shl: __ shlptr(value, count); break;
2991 case lir_shr: __ sarptr(value, count); break;
2992 case lir_ushr: __ shrptr(value, count); break;
2993 default: ShouldNotReachHere();
2994 }
2995 #endif // _LP64
2996 } else {
2997 ShouldNotReachHere();
2998 }
2999 }
3000
3001
3002 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3003 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3004 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3005 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3006 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3007 }
3008
3009
3010 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3014 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3015 }
3016
3017
3018 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3019 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3020 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3021 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3022 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3023 }
3024
3025
3026 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3027 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3028 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3029 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3030 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3031 }
3032
3033
3034 // This code replaces a call to arraycopy; no exception may
3035 // be thrown in this code, they must be thrown in the System.arraycopy
3036 // activation frame; we could save some checks if this would not be the case
3037 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3038 ciArrayKlass* default_type = op->expected_type();
3039 Register src = op->src()->as_register();
3040 Register dst = op->dst()->as_register();
3041 Register src_pos = op->src_pos()->as_register();
3042 Register dst_pos = op->dst_pos()->as_register();
3043 Register length = op->length()->as_register();
3044 Register tmp = op->tmp()->as_register();
3045
3046 CodeStub* stub = op->stub();
3047 int flags = op->flags();
3048 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3049 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3050
3051 // if we don't know anything, just go through the generic arraycopy
3052 if (default_type == NULL) {
3053 Label done;
3054 // save outgoing arguments on stack in case call to System.arraycopy is needed
3055 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3056 // for interpreter calling conventions. Now we have to do it in new style conventions.
3057 // For the moment until C1 gets the new register allocator I just force all the
3058 // args to the right place (except the register args) and then on the back side
3059 // reload the register args properly if we go slow path. Yuck
3060
3061 // These are proper for the calling convention
3062 store_parameter(length, 2);
3063 store_parameter(dst_pos, 1);
3064 store_parameter(dst, 0);
3065
3066 // these are just temporary placements until we need to reload
3067 store_parameter(src_pos, 3);
3068 store_parameter(src, 4);
3069 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3070
3071 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3072
3073 address copyfunc_addr = StubRoutines::generic_arraycopy();
3074
3075 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3076 #ifdef _LP64
3077 // The arguments are in java calling convention so we can trivially shift them to C
3078 // convention
3079 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3080 __ mov(c_rarg0, j_rarg0);
3081 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3082 __ mov(c_rarg1, j_rarg1);
3083 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3084 __ mov(c_rarg2, j_rarg2);
3085 assert_different_registers(c_rarg3, j_rarg4);
3086 __ mov(c_rarg3, j_rarg3);
3087 #ifdef _WIN64
3088 // Allocate abi space for args but be sure to keep stack aligned
3089 __ subptr(rsp, 6*wordSize);
3090 store_parameter(j_rarg4, 4);
3091 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3092 __ call(RuntimeAddress(C_entry));
3093 } else {
3094 #ifndef PRODUCT
3095 if (PrintC1Statistics) {
3096 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3097 }
3098 #endif
3099 __ call(RuntimeAddress(copyfunc_addr));
3100 }
3101 __ addptr(rsp, 6*wordSize);
3102 #else
3103 __ mov(c_rarg4, j_rarg4);
3104 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3105 __ call(RuntimeAddress(C_entry));
3106 } else {
3107 #ifndef PRODUCT
3108 if (PrintC1Statistics) {
3109 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3110 }
3111 #endif
3112 __ call(RuntimeAddress(copyfunc_addr));
3113 }
3114 #endif // _WIN64
3115 #else
3116 __ push(length);
3117 __ push(dst_pos);
3118 __ push(dst);
3119 __ push(src_pos);
3120 __ push(src);
3121
3122 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3123 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3124 } else {
3125 #ifndef PRODUCT
3126 if (PrintC1Statistics) {
3127 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3128 }
3129 #endif
3130 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3131 }
3132
3133 #endif // _LP64
3134
3135 __ cmpl(rax, 0);
3136 __ jcc(Assembler::equal, *stub->continuation());
3137
3138 if (copyfunc_addr != NULL) {
3139 __ mov(tmp, rax);
3140 __ xorl(tmp, -1);
3141 }
3142
3143 // Reload values from the stack so they are where the stub
3144 // expects them.
3145 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3146 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3147 __ movptr (length, Address(rsp, 2*BytesPerWord));
3148 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3149 __ movptr (src, Address(rsp, 4*BytesPerWord));
3150
3151 if (copyfunc_addr != NULL) {
3152 __ subl(length, tmp);
3153 __ addl(src_pos, tmp);
3154 __ addl(dst_pos, tmp);
3155 }
3156 __ jmp(*stub->entry());
3157
3158 __ bind(*stub->continuation());
3159 return;
3160 }
3161
3162 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3163
3164 int elem_size = type2aelembytes(basic_type);
3165 Address::ScaleFactor scale;
3166
3167 switch (elem_size) {
3168 case 1 :
3169 scale = Address::times_1;
3170 break;
3171 case 2 :
3172 scale = Address::times_2;
3173 break;
3174 case 4 :
3175 scale = Address::times_4;
3176 break;
3177 case 8 :
3178 scale = Address::times_8;
3179 break;
3180 default:
3181 scale = Address::no_scale;
3182 ShouldNotReachHere();
3183 }
3184
3185 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3186 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3187 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3188 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3189
3190 // length and pos's are all sign extended at this point on 64bit
3191
3192 // test for NULL
3193 if (flags & LIR_OpArrayCopy::src_null_check) {
3194 __ testptr(src, src);
3195 __ jcc(Assembler::zero, *stub->entry());
3196 }
3197 if (flags & LIR_OpArrayCopy::dst_null_check) {
3198 __ testptr(dst, dst);
3199 __ jcc(Assembler::zero, *stub->entry());
3200 }
3201
3202 // If the compiler was not able to prove that exact type of the source or the destination
3203 // of the arraycopy is an array type, check at runtime if the source or the destination is
3204 // an instance type.
3205 if (flags & LIR_OpArrayCopy::type_check) {
3206 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3207 __ load_klass(tmp, dst);
3208 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3209 __ jcc(Assembler::greaterEqual, *stub->entry());
3210 }
3211
3212 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3213 __ load_klass(tmp, src);
3214 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3215 __ jcc(Assembler::greaterEqual, *stub->entry());
3216 }
3217 }
3218
3219 // check if negative
3220 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3221 __ testl(src_pos, src_pos);
3222 __ jcc(Assembler::less, *stub->entry());
3223 }
3224 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3225 __ testl(dst_pos, dst_pos);
3226 __ jcc(Assembler::less, *stub->entry());
3227 }
3228
3229 if (flags & LIR_OpArrayCopy::src_range_check) {
3230 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3231 __ cmpl(tmp, src_length_addr);
3232 __ jcc(Assembler::above, *stub->entry());
3233 }
3234 if (flags & LIR_OpArrayCopy::dst_range_check) {
3235 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3236 __ cmpl(tmp, dst_length_addr);
3237 __ jcc(Assembler::above, *stub->entry());
3238 }
3239
3240 if (flags & LIR_OpArrayCopy::length_positive_check) {
3241 __ testl(length, length);
3242 __ jcc(Assembler::less, *stub->entry());
3243 }
3244
3245 #ifdef _LP64
3246 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3247 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3248 #endif
3249
3250 if (flags & LIR_OpArrayCopy::type_check) {
3251 // We don't know the array types are compatible
3252 if (basic_type != T_OBJECT) {
3253 // Simple test for basic type arrays
3254 if (UseCompressedClassPointers) {
3255 __ movl(tmp, src_klass_addr);
3256 __ cmpl(tmp, dst_klass_addr);
3257 } else {
3258 __ movptr(tmp, src_klass_addr);
3259 __ cmpptr(tmp, dst_klass_addr);
3260 }
3261 __ jcc(Assembler::notEqual, *stub->entry());
3262 } else {
3263 // For object arrays, if src is a sub class of dst then we can
3264 // safely do the copy.
3265 Label cont, slow;
3266
3267 __ push(src);
3268 __ push(dst);
3269
3270 __ load_klass(src, src);
3271 __ load_klass(dst, dst);
3272
3273 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3274
3275 __ push(src);
3276 __ push(dst);
3277 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3278 __ pop(dst);
3279 __ pop(src);
3280
3281 __ cmpl(src, 0);
3282 __ jcc(Assembler::notEqual, cont);
3283
3284 __ bind(slow);
3285 __ pop(dst);
3286 __ pop(src);
3287
3288 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3289 if (copyfunc_addr != NULL) { // use stub if available
3290 // src is not a sub class of dst so we have to do a
3291 // per-element check.
3292
3293 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3294 if ((flags & mask) != mask) {
3295 // Check that at least both of them object arrays.
3296 assert(flags & mask, "one of the two should be known to be an object array");
3297
3298 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3299 __ load_klass(tmp, src);
3300 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3301 __ load_klass(tmp, dst);
3302 }
3303 int lh_offset = in_bytes(Klass::layout_helper_offset());
3304 Address klass_lh_addr(tmp, lh_offset);
3305 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3306 __ cmpl(klass_lh_addr, objArray_lh);
3307 __ jcc(Assembler::notEqual, *stub->entry());
3308 }
3309
3310 // Spill because stubs can use any register they like and it's
3311 // easier to restore just those that we care about.
3312 store_parameter(dst, 0);
3313 store_parameter(dst_pos, 1);
3314 store_parameter(length, 2);
3315 store_parameter(src_pos, 3);
3316 store_parameter(src, 4);
3317
3318 #ifndef _LP64
3319 __ movptr(tmp, dst_klass_addr);
3320 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3321 __ push(tmp);
3322 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3323 __ push(tmp);
3324 __ push(length);
3325 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3326 __ push(tmp);
3327 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3328 __ push(tmp);
3329
3330 __ call_VM_leaf(copyfunc_addr, 5);
3331 #else
3332 __ movl2ptr(length, length); //higher 32bits must be null
3333
3334 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3335 assert_different_registers(c_rarg0, dst, dst_pos, length);
3336 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3337 assert_different_registers(c_rarg1, dst, length);
3338
3339 __ mov(c_rarg2, length);
3340 assert_different_registers(c_rarg2, dst);
3341
3342 #ifdef _WIN64
3343 // Allocate abi space for args but be sure to keep stack aligned
3344 __ subptr(rsp, 6*wordSize);
3345 __ load_klass(c_rarg3, dst);
3346 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3347 store_parameter(c_rarg3, 4);
3348 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3349 __ call(RuntimeAddress(copyfunc_addr));
3350 __ addptr(rsp, 6*wordSize);
3351 #else
3352 __ load_klass(c_rarg4, dst);
3353 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3354 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3355 __ call(RuntimeAddress(copyfunc_addr));
3356 #endif
3357
3358 #endif
3359
3360 #ifndef PRODUCT
3361 if (PrintC1Statistics) {
3362 Label failed;
3363 __ testl(rax, rax);
3364 __ jcc(Assembler::notZero, failed);
3365 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3366 __ bind(failed);
3367 }
3368 #endif
3369
3370 __ testl(rax, rax);
3371 __ jcc(Assembler::zero, *stub->continuation());
3372
3373 #ifndef PRODUCT
3374 if (PrintC1Statistics) {
3375 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3376 }
3377 #endif
3378
3379 __ mov(tmp, rax);
3380
3381 __ xorl(tmp, -1);
3382
3383 // Restore previously spilled arguments
3384 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3385 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3386 __ movptr (length, Address(rsp, 2*BytesPerWord));
3387 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3388 __ movptr (src, Address(rsp, 4*BytesPerWord));
3389
3390
3391 __ subl(length, tmp);
3392 __ addl(src_pos, tmp);
3393 __ addl(dst_pos, tmp);
3394 }
3395
3396 __ jmp(*stub->entry());
3397
3398 __ bind(cont);
3399 __ pop(dst);
3400 __ pop(src);
3401 }
3402 }
3403
3404 #ifdef ASSERT
3405 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3406 // Sanity check the known type with the incoming class. For the
3407 // primitive case the types must match exactly with src.klass and
3408 // dst.klass each exactly matching the default type. For the
3409 // object array case, if no type check is needed then either the
3410 // dst type is exactly the expected type and the src type is a
3411 // subtype which we can't check or src is the same array as dst
3412 // but not necessarily exactly of type default_type.
3413 Label known_ok, halt;
3414 __ mov_metadata(tmp, default_type->constant_encoding());
3415 #ifdef _LP64
3416 if (UseCompressedClassPointers) {
3417 __ encode_klass_not_null(tmp);
3418 }
3419 #endif
3420
3421 if (basic_type != T_OBJECT) {
3422
3423 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3424 else __ cmpptr(tmp, dst_klass_addr);
3425 __ jcc(Assembler::notEqual, halt);
3426 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3427 else __ cmpptr(tmp, src_klass_addr);
3428 __ jcc(Assembler::equal, known_ok);
3429 } else {
3430 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3431 else __ cmpptr(tmp, dst_klass_addr);
3432 __ jcc(Assembler::equal, known_ok);
3433 __ cmpptr(src, dst);
3434 __ jcc(Assembler::equal, known_ok);
3435 }
3436 __ bind(halt);
3437 __ stop("incorrect type information in arraycopy");
3438 __ bind(known_ok);
3439 }
3440 #endif
3441
3442 #ifndef PRODUCT
3443 if (PrintC1Statistics) {
3444 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3445 }
3446 #endif
3447
3448 #ifdef _LP64
3449 assert_different_registers(c_rarg0, dst, dst_pos, length);
3450 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3451 assert_different_registers(c_rarg1, length);
3452 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3453 __ mov(c_rarg2, length);
3454
3455 #else
3456 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3457 store_parameter(tmp, 0);
3458 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3459 store_parameter(tmp, 1);
3460 store_parameter(length, 2);
3461 #endif // _LP64
3462
3463 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3464 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3465 const char *name;
3466 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3467 __ call_VM_leaf(entry, 0);
3468
3469 __ bind(*stub->continuation());
3470 }
3471
3472 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3473 assert(op->crc()->is_single_cpu(), "crc must be register");
3474 assert(op->val()->is_single_cpu(), "byte value must be register");
3475 assert(op->result_opr()->is_single_cpu(), "result must be register");
3476 Register crc = op->crc()->as_register();
3477 Register val = op->val()->as_register();
3478 Register res = op->result_opr()->as_register();
3479
3480 assert_different_registers(val, crc, res);
3481
3482 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3483 __ notl(crc); // ~crc
3484 __ update_byte_crc32(crc, val, res);
3485 __ notl(crc); // ~crc
3486 __ mov(res, crc);
3487 }
3488
3489 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3490 Register obj = op->obj_opr()->as_register(); // may not be an oop
3491 Register hdr = op->hdr_opr()->as_register();
3492 Register lock = op->lock_opr()->as_register();
3493 if (!UseFastLocking) {
3494 __ jmp(*op->stub()->entry());
3495 } else if (op->code() == lir_lock) {
3496 Register scratch = noreg;
3497 if (UseBiasedLocking) {
3498 scratch = op->scratch_opr()->as_register();
3499 }
3500 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3501 // add debug info for NullPointerException only if one is possible
3502 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3503 if (op->info() != NULL) {
3504 add_debug_info_for_null_check(null_check_offset, op->info());
3505 }
3506 // done
3507 } else if (op->code() == lir_unlock) {
3508 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3509 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3510 } else {
3511 Unimplemented();
3512 }
3513 __ bind(*op->stub()->continuation());
3514 }
3515
3516
3517 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3518 ciMethod* method = op->profiled_method();
3519 int bci = op->profiled_bci();
3520 ciMethod* callee = op->profiled_callee();
3521
3522 // Update counter for all call types
3523 ciMethodData* md = method->method_data_or_null();
3524 assert(md != NULL, "Sanity");
3525 ciProfileData* data = md->bci_to_data(bci);
3526 assert(data->is_CounterData(), "need CounterData for calls");
3527 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3528 Register mdo = op->mdo()->as_register();
3529 __ mov_metadata(mdo, md->constant_encoding());
3530 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3531 Bytecodes::Code bc = method->java_code_at_bci(bci);
3532 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3533 // Perform additional virtual call profiling for invokevirtual and
3534 // invokeinterface bytecodes
3535 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3536 !callee_is_static && // required for optimized MH invokes
3537 C1ProfileVirtualCalls) {
3538 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3539 Register recv = op->recv()->as_register();
3540 assert_different_registers(mdo, recv);
3541 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3542 ciKlass* known_klass = op->known_holder();
3543 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3544 // We know the type that will be seen at this call site; we can
3545 // statically update the MethodData* rather than needing to do
3546 // dynamic tests on the receiver type
3547
3548 // NOTE: we should probably put a lock around this search to
3549 // avoid collisions by concurrent compilations
3550 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3551 uint i;
3552 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3553 ciKlass* receiver = vc_data->receiver(i);
3554 if (known_klass->equals(receiver)) {
3555 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3556 __ addptr(data_addr, DataLayout::counter_increment);
3557 return;
3558 }
3559 }
3560
3561 // Receiver type not found in profile data; select an empty slot
3562
3563 // Note that this is less efficient than it should be because it
3564 // always does a write to the receiver part of the
3565 // VirtualCallData rather than just the first time
3566 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3567 ciKlass* receiver = vc_data->receiver(i);
3568 if (receiver == NULL) {
3569 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3570 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3571 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3572 __ addptr(data_addr, DataLayout::counter_increment);
3573 return;
3574 }
3575 }
3576 } else {
3577 __ load_klass(recv, recv);
3578 Label update_done;
3579 type_profile_helper(mdo, md, data, recv, &update_done);
3580 // Receiver did not match any saved receiver and there is no empty row for it.
3581 // Increment total counter to indicate polymorphic case.
3582 __ addptr(counter_addr, DataLayout::counter_increment);
3583
3584 __ bind(update_done);
3585 }
3586 } else {
3587 // Static call
3588 __ addptr(counter_addr, DataLayout::counter_increment);
3589 }
3590 }
3591
3592 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3593 Register obj = op->obj()->as_register();
3594 Register tmp = op->tmp()->as_pointer_register();
3595 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3596 ciKlass* exact_klass = op->exact_klass();
3597 intptr_t current_klass = op->current_klass();
3598 bool not_null = op->not_null();
3599 bool no_conflict = op->no_conflict();
3600
3601 Label update, next, none;
3602
3603 bool do_null = !not_null;
3604 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3605 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3606
3607 assert(do_null || do_update, "why are we here?");
3608 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3609
3610 __ verify_oop(obj);
3611
3612 if (tmp != obj) {
3613 __ mov(tmp, obj);
3614 }
3615 if (do_null) {
3616 __ testptr(tmp, tmp);
3617 __ jccb(Assembler::notZero, update);
3618 if (!TypeEntries::was_null_seen(current_klass)) {
3619 __ orptr(mdo_addr, TypeEntries::null_seen);
3620 }
3621 if (do_update) {
3622 #ifndef ASSERT
3623 __ jmpb(next);
3624 }
3625 #else
3626 __ jmp(next);
3627 }
3628 } else {
3629 __ testptr(tmp, tmp);
3630 __ jccb(Assembler::notZero, update);
3631 __ stop("unexpect null obj");
3632 #endif
3633 }
3634
3635 __ bind(update);
3636
3637 if (do_update) {
3638 #ifdef ASSERT
3639 if (exact_klass != NULL) {
3640 Label ok;
3641 __ load_klass(tmp, tmp);
3642 __ push(tmp);
3643 __ mov_metadata(tmp, exact_klass->constant_encoding());
3644 __ cmpptr(tmp, Address(rsp, 0));
3645 __ jccb(Assembler::equal, ok);
3646 __ stop("exact klass and actual klass differ");
3647 __ bind(ok);
3648 __ pop(tmp);
3649 }
3650 #endif
3651 if (!no_conflict) {
3652 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3653 if (exact_klass != NULL) {
3654 __ mov_metadata(tmp, exact_klass->constant_encoding());
3655 } else {
3656 __ load_klass(tmp, tmp);
3657 }
3658
3659 __ xorptr(tmp, mdo_addr);
3660 __ testptr(tmp, TypeEntries::type_klass_mask);
3661 // klass seen before, nothing to do. The unknown bit may have been
3662 // set already but no need to check.
3663 __ jccb(Assembler::zero, next);
3664
3665 __ testptr(tmp, TypeEntries::type_unknown);
3666 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3667
3668 if (TypeEntries::is_type_none(current_klass)) {
3669 __ cmpptr(mdo_addr, 0);
3670 __ jccb(Assembler::equal, none);
3671 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3672 __ jccb(Assembler::equal, none);
3673 // There is a chance that the checks above (re-reading profiling
3674 // data from memory) fail if another thread has just set the
3675 // profiling to this obj's klass
3676 __ xorptr(tmp, mdo_addr);
3677 __ testptr(tmp, TypeEntries::type_klass_mask);
3678 __ jccb(Assembler::zero, next);
3679 }
3680 } else {
3681 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3682 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3683
3684 __ movptr(tmp, mdo_addr);
3685 __ testptr(tmp, TypeEntries::type_unknown);
3686 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3687 }
3688
3689 // different than before. Cannot keep accurate profile.
3690 __ orptr(mdo_addr, TypeEntries::type_unknown);
3691
3692 if (TypeEntries::is_type_none(current_klass)) {
3693 __ jmpb(next);
3694
3695 __ bind(none);
3696 // first time here. Set profile type.
3697 __ movptr(mdo_addr, tmp);
3698 }
3699 } else {
3700 // There's a single possible klass at this profile point
3701 assert(exact_klass != NULL, "should be");
3702 if (TypeEntries::is_type_none(current_klass)) {
3703 __ mov_metadata(tmp, exact_klass->constant_encoding());
3704 __ xorptr(tmp, mdo_addr);
3705 __ testptr(tmp, TypeEntries::type_klass_mask);
3706 #ifdef ASSERT
3707 __ jcc(Assembler::zero, next);
3708
3709 {
3710 Label ok;
3711 __ push(tmp);
3712 __ cmpptr(mdo_addr, 0);
3713 __ jcc(Assembler::equal, ok);
3714 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3715 __ jcc(Assembler::equal, ok);
3716 // may have been set by another thread
3717 __ mov_metadata(tmp, exact_klass->constant_encoding());
3718 __ xorptr(tmp, mdo_addr);
3719 __ testptr(tmp, TypeEntries::type_mask);
3720 __ jcc(Assembler::zero, ok);
3721
3722 __ stop("unexpected profiling mismatch");
3723 __ bind(ok);
3724 __ pop(tmp);
3725 }
3726 #else
3727 __ jccb(Assembler::zero, next);
3728 #endif
3729 // first time here. Set profile type.
3730 __ movptr(mdo_addr, tmp);
3731 } else {
3732 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3733 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3734
3735 __ movptr(tmp, mdo_addr);
3736 __ testptr(tmp, TypeEntries::type_unknown);
3737 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3738
3739 __ orptr(mdo_addr, TypeEntries::type_unknown);
3740 }
3741 }
3742
3743 __ bind(next);
3744 }
3745 }
3746
3747 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3748 Unimplemented();
3749 }
3750
3751
3752 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3753 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3754 }
3755
3756
3757 void LIR_Assembler::align_backward_branch_target() {
3758 __ align(BytesPerWord);
3759 }
3760
3761
3762 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3763 if (left->is_single_cpu()) {
3764 __ negl(left->as_register());
3765 move_regs(left->as_register(), dest->as_register());
3766
3767 } else if (left->is_double_cpu()) {
3768 Register lo = left->as_register_lo();
3769 #ifdef _LP64
3770 Register dst = dest->as_register_lo();
3771 __ movptr(dst, lo);
3772 __ negptr(dst);
3773 #else
3774 Register hi = left->as_register_hi();
3775 __ lneg(hi, lo);
3776 if (dest->as_register_lo() == hi) {
3777 assert(dest->as_register_hi() != lo, "destroying register");
3778 move_regs(hi, dest->as_register_hi());
3779 move_regs(lo, dest->as_register_lo());
3780 } else {
3781 move_regs(lo, dest->as_register_lo());
3782 move_regs(hi, dest->as_register_hi());
3783 }
3784 #endif // _LP64
3785
3786 } else if (dest->is_single_xmm()) {
3787 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3788 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3789 }
3790 if (UseAVX > 0) {
3791 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3792 ExternalAddress((address)float_signflip_pool));
3793 } else {
3794 __ xorps(dest->as_xmm_float_reg(),
3795 ExternalAddress((address)float_signflip_pool));
3796 }
3797 } else if (dest->is_double_xmm()) {
3798 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3799 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3800 }
3801 if (UseAVX > 0) {
3802 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3803 ExternalAddress((address)double_signflip_pool));
3804 } else {
3805 __ xorpd(dest->as_xmm_double_reg(),
3806 ExternalAddress((address)double_signflip_pool));
3807 }
3808 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3809 assert(left->fpu() == 0, "arg must be on TOS");
3810 assert(dest->fpu() == 0, "dest must be TOS");
3811 __ fchs();
3812
3813 } else {
3814 ShouldNotReachHere();
3815 }
3816 }
3817
3818
3819 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3820 assert(addr->is_address() && dest->is_register(), "check");
3821 Register reg;
3822 reg = dest->as_pointer_register();
3823 __ lea(reg, as_Address(addr->as_address_ptr()));
3824 }
3825
3826
3827
3828 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3829 assert(!tmp->is_valid(), "don't need temporary");
3830 __ call(RuntimeAddress(dest));
3831 if (info != NULL) {
3832 add_call_info_here(info);
3833 }
3834 }
3835
3836
3837 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3838 assert(type == T_LONG, "only for volatile long fields");
3839
3840 if (info != NULL) {
3841 add_debug_info_for_null_check_here(info);
3842 }
3843
3844 if (src->is_double_xmm()) {
3845 if (dest->is_double_cpu()) {
3846 #ifdef _LP64
3847 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3848 #else
3849 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3850 __ psrlq(src->as_xmm_double_reg(), 32);
3851 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3852 #endif // _LP64
3853 } else if (dest->is_double_stack()) {
3854 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3855 } else if (dest->is_address()) {
3856 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3857 } else {
3858 ShouldNotReachHere();
3859 }
3860
3861 } else if (dest->is_double_xmm()) {
3862 if (src->is_double_stack()) {
3863 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3864 } else if (src->is_address()) {
3865 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3866 } else {
3867 ShouldNotReachHere();
3868 }
3869
3870 } else if (src->is_double_fpu()) {
3871 assert(src->fpu_regnrLo() == 0, "must be TOS");
3872 if (dest->is_double_stack()) {
3873 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3874 } else if (dest->is_address()) {
3875 __ fistp_d(as_Address(dest->as_address_ptr()));
3876 } else {
3877 ShouldNotReachHere();
3878 }
3879
3880 } else if (dest->is_double_fpu()) {
3881 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3882 if (src->is_double_stack()) {
3883 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3884 } else if (src->is_address()) {
3885 __ fild_d(as_Address(src->as_address_ptr()));
3886 } else {
3887 ShouldNotReachHere();
3888 }
3889 } else {
3890 ShouldNotReachHere();
3891 }
3892 }
3893
3894 #ifdef ASSERT
3895 // emit run-time assertion
3896 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3897 assert(op->code() == lir_assert, "must be");
3898
3899 if (op->in_opr1()->is_valid()) {
3900 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3901 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3902 } else {
3903 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3904 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3905 }
3906
3907 Label ok;
3908 if (op->condition() != lir_cond_always) {
3909 Assembler::Condition acond = Assembler::zero;
3910 switch (op->condition()) {
3911 case lir_cond_equal: acond = Assembler::equal; break;
3912 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3913 case lir_cond_less: acond = Assembler::less; break;
3914 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3915 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3916 case lir_cond_greater: acond = Assembler::greater; break;
3917 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3918 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3919 default: ShouldNotReachHere();
3920 }
3921 __ jcc(acond, ok);
3922 }
3923 if (op->halt()) {
3924 const char* str = __ code_string(op->msg());
3925 __ stop(str);
3926 } else {
3927 breakpoint();
3928 }
3929 __ bind(ok);
3930 }
3931 #endif
3932
3933 void LIR_Assembler::membar() {
3934 // QQQ sparc TSO uses this,
3935 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3936 }
3937
3938 void LIR_Assembler::membar_acquire() {
3939 // No x86 machines currently require load fences
3940 }
3941
3942 void LIR_Assembler::membar_release() {
3943 // No x86 machines currently require store fences
3944 }
3945
3946 void LIR_Assembler::membar_loadload() {
3947 // no-op
3948 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3949 }
3950
3951 void LIR_Assembler::membar_storestore() {
3952 // no-op
3953 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3954 }
3955
3956 void LIR_Assembler::membar_loadstore() {
3957 // no-op
3958 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3959 }
3960
3961 void LIR_Assembler::membar_storeload() {
3962 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3963 }
3964
3965 void LIR_Assembler::on_spin_wait() {
3966 __ pause ();
3967 }
3968
3969 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3970 assert(result_reg->is_register(), "check");
3971 #ifdef _LP64
3972 // __ get_thread(result_reg->as_register_lo());
3973 __ mov(result_reg->as_register(), r15_thread);
3974 #else
3975 __ get_thread(result_reg->as_register());
3976 #endif // _LP64
3977 }
3978
3979
3980 void LIR_Assembler::peephole(LIR_List*) {
3981 // do nothing for now
3982 }
3983
3984 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3985 assert(data == dest, "xchg/xadd uses only 2 operands");
3986
3987 if (data->type() == T_INT) {
3988 if (code == lir_xadd) {
3989 if (os::is_MP()) {
3990 __ lock();
3991 }
3992 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3993 } else {
3994 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3995 }
3996 } else if (data->is_oop()) {
3997 assert (code == lir_xchg, "xadd for oops");
3998 Register obj = data->as_register();
3999 #ifdef _LP64
4000 if (UseCompressedOops) {
4001 __ encode_heap_oop(obj);
4002 __ xchgl(obj, as_Address(src->as_address_ptr()));
4003 __ decode_heap_oop(obj);
4004 } else {
4005 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4006 }
4007 #else
4008 __ xchgl(obj, as_Address(src->as_address_ptr()));
4009 #endif
4010 } else if (data->type() == T_LONG) {
4011 #ifdef _LP64
4012 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4013 if (code == lir_xadd) {
4014 if (os::is_MP()) {
4015 __ lock();
4016 }
4017 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4018 } else {
4019 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4020 }
4021 #else
4022 ShouldNotReachHere();
4023 #endif
4024 } else {
4025 ShouldNotReachHere();
4026 }
4027 }
4028
4029 #undef __