769 void cmpklass(Register dst, Metadata* obj);
770 void cmpoop(Address dst, jobject obj);
771 void cmpoop(Register dst, jobject obj);
772 #endif // _LP64
773
774 // NOTE src2 must be the lval. This is NOT an mem-mem compare
775 void cmpptr(Address src1, AddressLiteral src2);
776
777 void cmpptr(Register src1, AddressLiteral src2);
778
779 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
780 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
781 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
782
783 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
784 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
785
786 // cmp64 to avoild hiding cmpq
787 void cmp64(Register src1, AddressLiteral src);
788
789 void cmpxchgptr(Register reg, Address adr);
790
791 // Special Shenandoah CAS implementation that handles false negatives
792 // due to concurrent evacuation.
793 void cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
794 bool exchange,
795 Register tmp1, Register tmp2);
796
797 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
798
799
800 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
801 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
802
803
804 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
805
806 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
807
808 void shlptr(Register dst, int32_t shift);
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769 void cmpklass(Register dst, Metadata* obj);
770 void cmpoop(Address dst, jobject obj);
771 void cmpoop(Register dst, jobject obj);
772 #endif // _LP64
773
774 // NOTE src2 must be the lval. This is NOT an mem-mem compare
775 void cmpptr(Address src1, AddressLiteral src2);
776
777 void cmpptr(Register src1, AddressLiteral src2);
778
779 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
780 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
781 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
782
783 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
784 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
785
786 // cmp64 to avoild hiding cmpq
787 void cmp64(Register src1, AddressLiteral src);
788
789 // Special cmp for heap objects, possibly inserting required barriers.
790 void cmpoopptr(Register src1, Register src2);
791 void cmpoopptr(Register src1, Address src2);
792
793 void cmpxchgptr(Register reg, Address adr);
794
795 // Special Shenandoah CAS implementation that handles false negatives
796 // due to concurrent evacuation.
797 void cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
798 bool exchange,
799 Register tmp1, Register tmp2);
800
801 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
802
803
804 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
805 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
806
807
808 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
809
810 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
811
812 void shlptr(Register dst, int32_t shift);
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