2595
2596 move_regs(lreg, rax);
2597
2598 int idivl_offset = __ corrected_idivl(rreg);
2599 add_debug_info_for_div0(idivl_offset, info);
2600 if (code == lir_irem) {
2601 move_regs(rdx, dreg); // result is in rdx
2602 } else {
2603 move_regs(rax, dreg);
2604 }
2605 }
2606 }
2607
2608
2609 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2610 if (opr1->is_single_cpu()) {
2611 Register reg1 = opr1->as_register();
2612 if (opr2->is_single_cpu()) {
2613 // cpu register - cpu register
2614 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2615 __ cmpoopptr(reg1, opr2->as_register());
2616 } else {
2617 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2618 __ cmpl(reg1, opr2->as_register());
2619 }
2620 } else if (opr2->is_stack()) {
2621 // cpu register - stack
2622 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2623 __ cmpoopptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2624 } else {
2625 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2626 }
2627 } else if (opr2->is_constant()) {
2628 // cpu register - constant
2629 LIR_Const* c = opr2->as_constant_ptr();
2630 if (c->type() == T_INT) {
2631 __ cmpl(reg1, c->as_jint());
2632 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2633 // In 64bit oops are single register
2634 jobject o = c->as_jobject();
2635 if (o == NULL) {
2636 __ cmpptr(reg1, (int32_t)NULL_WORD);
2637 } else {
2638 #ifdef _LP64
2639 __ movoop(rscratch1, o);
2640 __ cmpoopptr(reg1, rscratch1);
2641 #else
2642 __ cmpoop(reg1, c->as_jobject());
2643 #endif // _LP64
2644 }
2645 } else {
2646 fatal("unexpected type: %s", basictype_to_str(c->type()));
2647 }
2648 // cpu register - address
2649 } else if (opr2->is_address()) {
2650 if (op->info() != NULL) {
2651 add_debug_info_for_null_check_here(op->info());
2652 }
2653 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2654 } else {
2655 ShouldNotReachHere();
2656 }
2657
2658 } else if(opr1->is_double_cpu()) {
2659 Register xlo = opr1->as_register_lo();
2660 Register xhi = opr1->as_register_hi();
2733
2734 } else if (opr1->is_address() && opr2->is_constant()) {
2735 LIR_Const* c = opr2->as_constant_ptr();
2736 #ifdef _LP64
2737 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2738 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2739 __ movoop(rscratch1, c->as_jobject());
2740 }
2741 #endif // LP64
2742 if (op->info() != NULL) {
2743 add_debug_info_for_null_check_here(op->info());
2744 }
2745 // special case: address - constant
2746 LIR_Address* addr = opr1->as_address_ptr();
2747 if (c->type() == T_INT) {
2748 __ cmpl(as_Address(addr), c->as_jint());
2749 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2750 #ifdef _LP64
2751 // %%% Make this explode if addr isn't reachable until we figure out a
2752 // better strategy by giving noreg as the temp for as_Address
2753 __ cmpoopptr(rscratch1, as_Address(addr, noreg));
2754 #else
2755 __ cmpoop(as_Address(addr), c->as_jobject());
2756 #endif // _LP64
2757 } else {
2758 ShouldNotReachHere();
2759 }
2760
2761 } else {
2762 ShouldNotReachHere();
2763 }
2764 }
2765
2766 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2767 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2768 if (left->is_single_xmm()) {
2769 assert(right->is_single_xmm(), "must match");
2770 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2771 } else if (left->is_double_xmm()) {
2772 assert(right->is_double_xmm(), "must match");
2773 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
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2595
2596 move_regs(lreg, rax);
2597
2598 int idivl_offset = __ corrected_idivl(rreg);
2599 add_debug_info_for_div0(idivl_offset, info);
2600 if (code == lir_irem) {
2601 move_regs(rdx, dreg); // result is in rdx
2602 } else {
2603 move_regs(rax, dreg);
2604 }
2605 }
2606 }
2607
2608
2609 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2610 if (opr1->is_single_cpu()) {
2611 Register reg1 = opr1->as_register();
2612 if (opr2->is_single_cpu()) {
2613 // cpu register - cpu register
2614 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2615 __ cmpoops(reg1, opr2->as_register());
2616 } else {
2617 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2618 __ cmpl(reg1, opr2->as_register());
2619 }
2620 } else if (opr2->is_stack()) {
2621 // cpu register - stack
2622 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2623 __ cmpoops(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2624 } else {
2625 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2626 }
2627 } else if (opr2->is_constant()) {
2628 // cpu register - constant
2629 LIR_Const* c = opr2->as_constant_ptr();
2630 if (c->type() == T_INT) {
2631 __ cmpl(reg1, c->as_jint());
2632 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2633 // In 64bit oops are single register
2634 jobject o = c->as_jobject();
2635 if (o == NULL) {
2636 __ cmpptr(reg1, (int32_t)NULL_WORD);
2637 } else {
2638 #ifdef _LP64
2639 __ movoop(rscratch1, o);
2640 __ cmpoops(reg1, rscratch1);
2641 #else
2642 __ cmpoop(reg1, c->as_jobject());
2643 #endif // _LP64
2644 }
2645 } else {
2646 fatal("unexpected type: %s", basictype_to_str(c->type()));
2647 }
2648 // cpu register - address
2649 } else if (opr2->is_address()) {
2650 if (op->info() != NULL) {
2651 add_debug_info_for_null_check_here(op->info());
2652 }
2653 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2654 } else {
2655 ShouldNotReachHere();
2656 }
2657
2658 } else if(opr1->is_double_cpu()) {
2659 Register xlo = opr1->as_register_lo();
2660 Register xhi = opr1->as_register_hi();
2733
2734 } else if (opr1->is_address() && opr2->is_constant()) {
2735 LIR_Const* c = opr2->as_constant_ptr();
2736 #ifdef _LP64
2737 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2738 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2739 __ movoop(rscratch1, c->as_jobject());
2740 }
2741 #endif // LP64
2742 if (op->info() != NULL) {
2743 add_debug_info_for_null_check_here(op->info());
2744 }
2745 // special case: address - constant
2746 LIR_Address* addr = opr1->as_address_ptr();
2747 if (c->type() == T_INT) {
2748 __ cmpl(as_Address(addr), c->as_jint());
2749 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2750 #ifdef _LP64
2751 // %%% Make this explode if addr isn't reachable until we figure out a
2752 // better strategy by giving noreg as the temp for as_Address
2753 __ cmpoops(rscratch1, as_Address(addr, noreg));
2754 #else
2755 __ cmpoop(as_Address(addr), c->as_jobject());
2756 #endif // _LP64
2757 } else {
2758 ShouldNotReachHere();
2759 }
2760
2761 } else {
2762 ShouldNotReachHere();
2763 }
2764 }
2765
2766 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2767 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2768 if (left->is_single_xmm()) {
2769 assert(right->is_single_xmm(), "must match");
2770 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2771 } else if (left->is_double_xmm()) {
2772 assert(right->is_double_xmm(), "must match");
2773 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
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