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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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rev 52801 : Upstream/backport Shenandoah to JDK11u
* * *
[backport] 8237570: Shenandoah: cleanup uses of allocation/free threshold in static heuristics
Reviewed-by: rkennke


2798   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2799 
2800   if (left->is_single_cpu()) {
2801     assert(dest->is_single_cpu(), "expect single result reg");
2802     __ negw(dest->as_register(), left->as_register());
2803   } else if (left->is_double_cpu()) {
2804     assert(dest->is_double_cpu(), "expect double result reg");
2805     __ neg(dest->as_register_lo(), left->as_register_lo());
2806   } else if (left->is_single_fpu()) {
2807     assert(dest->is_single_fpu(), "expect single float result reg");
2808     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2809   } else {
2810     assert(left->is_double_fpu(), "expect double float operand reg");
2811     assert(dest->is_double_fpu(), "expect double float result reg");
2812     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2813   }
2814 }
2815 
2816 
2817 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2818   assert(patch_code == lir_patch_none, "Patch code not supported");




2819   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2820 }
2821 
2822 
2823 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2824   assert(!tmp->is_valid(), "don't need temporary");
2825 
2826   CodeBlob *cb = CodeCache::find_blob(dest);
2827   if (cb) {
2828     __ far_call(RuntimeAddress(dest));
2829   } else {
2830     __ mov(rscratch1, RuntimeAddress(dest));
2831     __ blr(rscratch1);
2832   }
2833 
2834   if (info != NULL) {
2835     add_call_info_here(info);
2836   }
2837   __ maybe_isb();
2838 }




2798   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2799 
2800   if (left->is_single_cpu()) {
2801     assert(dest->is_single_cpu(), "expect single result reg");
2802     __ negw(dest->as_register(), left->as_register());
2803   } else if (left->is_double_cpu()) {
2804     assert(dest->is_double_cpu(), "expect double result reg");
2805     __ neg(dest->as_register_lo(), left->as_register_lo());
2806   } else if (left->is_single_fpu()) {
2807     assert(dest->is_single_fpu(), "expect single float result reg");
2808     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2809   } else {
2810     assert(left->is_double_fpu(), "expect double float operand reg");
2811     assert(dest->is_double_fpu(), "expect double float result reg");
2812     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2813   }
2814 }
2815 
2816 
2817 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2818   if (patch_code != lir_patch_none) {
2819     deoptimize_trap(info);
2820     return;
2821   }
2822 
2823   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2824 }
2825 
2826 
2827 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2828   assert(!tmp->is_valid(), "don't need temporary");
2829 
2830   CodeBlob *cb = CodeCache::find_blob(dest);
2831   if (cb) {
2832     __ far_call(RuntimeAddress(dest));
2833   } else {
2834     __ mov(rscratch1, RuntimeAddress(dest));
2835     __ blr(rscratch1);
2836   }
2837 
2838   if (info != NULL) {
2839     add_call_info_here(info);
2840   }
2841   __ maybe_isb();
2842 }
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