1 /* 2 * Copyright (c) 2018, Red Hat, Inc. All rights reserved. 3 * 4 * This code is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 only, as 6 * published by the Free Software Foundation. 7 * 8 * This code is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 * version 2 for more details (a copy is included in the LICENSE file that 12 * accompanied this code). 13 * 14 * You should have received a copy of the GNU General Public License version 15 * 2 along with this work; if not, write to the Free Software Foundation, 16 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 19 * or visit www.oracle.com if you need additional information or have any 20 * questions. 21 * 22 */ 23 24 #include "precompiled.hpp" 25 #include "c1/c1_LIRAssembler.hpp" 26 #include "c1/c1_MacroAssembler.hpp" 27 #include "gc/shenandoah/shenandoahBarrierSet.hpp" 28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" 29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" 30 31 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { 32 Register addr = _addr->as_register_lo(); 33 Register newval = _new_value->as_register(); 34 Register cmpval = _cmp_value->as_register(); 35 Register tmp1 = _tmp1->as_register(); 36 Register tmp2 = _tmp2->as_register(); 37 assert(cmpval == rax, "wrong register"); 38 assert(newval != NULL, "new val must be register"); 39 assert(cmpval != newval, "cmp and new values must be in different registers"); 40 assert(cmpval != addr, "cmp and addr must be in different registers"); 41 assert(newval != addr, "new value and addr must be in different registers"); 42 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), NULL, Address(addr, 0), cmpval, newval, true, true, tmp1, tmp2); 43 } 44 45 #ifdef ASSERT 46 #define __ gen->lir(__FILE__, __LINE__)-> 47 #else 48 #define __ gen->lir()-> 49 #endif 50 51 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) { 52 53 if (access.is_oop()) { 54 LIRGenerator* gen = access.gen(); 55 if (ShenandoahSATBBarrier) { 56 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(), 57 LIR_OprFact::illegalOpr /* pre_val */); 58 } 59 if (ShenandoahCASBarrier) { 60 cmp_value.load_item_force(FrameMap::rax_oop_opr); 61 new_value.load_item(); 62 63 LIR_Opr t1 = gen->new_register(T_OBJECT); 64 LIR_Opr t2 = gen->new_register(T_OBJECT); 65 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); 66 67 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, LIR_OprFact::illegalOpr)); 68 69 LIR_Opr result = gen->new_register(T_INT); 70 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), 71 result, T_INT); 72 return result; 73 } 74 } 75 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); 76 } 77 78 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) { 79 LIRGenerator* gen = access.gen(); 80 BasicType type = access.type(); 81 82 LIR_Opr result = gen->new_register(type); 83 value.load_item(); 84 LIR_Opr value_opr = value.result(); 85 86 if (access.is_oop()) { 87 value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators()); 88 } 89 90 // Because we want a 2-arg form of xchg and xadd 91 __ move(value_opr, result); 92 93 assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type"); 94 __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr); 95 96 if (access.is_oop()) { 97 if (ShenandoahSATBBarrier) { 98 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, 99 result /* pre_val */); 100 } 101 } 102 103 return result; 104 }