1 /*
2 * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "nativeInst_x86.hpp"
32 #include "oops/compiledICHolder.hpp"
33 #include "oops/oop.inline.hpp"
34 #include "prims/jvmtiExport.hpp"
35 #include "register_x86.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/signature.hpp"
38 #include "runtime/vframeArray.hpp"
39 #include "utilities/macros.hpp"
40 #include "vmreg_x86.inline.hpp"
41 #if INCLUDE_ALL_GCS
42 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
43 #include "gc/shenandoah/shenandoahHeap.hpp"
44 #include "gc/shenandoah/shenandoahHeapRegion.hpp"
45 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
46 #endif
47
48
49 // Implementation of StubAssembler
50
51 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
52 // setup registers
53 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
54 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
55 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
56 assert(args_size >= 0, "illegal args_size");
57 bool align_stack = false;
58 #ifdef _LP64
59 // At a method handle call, the stack may not be properly aligned
60 // when returning with an exception.
61 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
62 #endif
63
64 #ifdef _LP64
65 mov(c_rarg0, thread);
66 set_num_rt_args(0); // Nothing on stack
67 #else
68 set_num_rt_args(1 + args_size);
69
70 // push java thread (becomes first argument of C function)
71 get_thread(thread);
72 push(thread);
73 #endif // _LP64
74
75 int call_offset;
76 if (!align_stack) {
77 set_last_Java_frame(thread, noreg, rbp, NULL);
78 } else {
79 address the_pc = pc();
80 call_offset = offset();
81 set_last_Java_frame(thread, noreg, rbp, the_pc);
82 andptr(rsp, -(StackAlignmentInBytes)); // Align stack
83 }
84
85 // do the call
86 call(RuntimeAddress(entry));
87 if (!align_stack) {
88 call_offset = offset();
89 }
90 // verify callee-saved register
91 #ifdef ASSERT
92 guarantee(thread != rax, "change this code");
93 push(rax);
94 { Label L;
95 get_thread(rax);
96 cmpptr(thread, rax);
97 jcc(Assembler::equal, L);
98 int3();
99 stop("StubAssembler::call_RT: rdi not callee saved?");
100 bind(L);
101 }
102 pop(rax);
103 #endif
104 reset_last_Java_frame(thread, true, align_stack);
105
106 // discard thread and arguments
107 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
108
109 // check for pending exceptions
110 { Label L;
111 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
112 jcc(Assembler::equal, L);
113 // exception pending => remove activation and forward to exception handler
114 movptr(rax, Address(thread, Thread::pending_exception_offset()));
115 // make sure that the vm_results are cleared
116 if (oop_result1->is_valid()) {
117 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
118 }
119 if (metadata_result->is_valid()) {
120 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
121 }
122 if (frame_size() == no_frame_size) {
123 leave();
124 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
125 } else if (_stub_id == Runtime1::forward_exception_id) {
126 should_not_reach_here();
127 } else {
128 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
129 }
130 bind(L);
131 }
132 // get oop results if there are any and reset the values in the thread
133 if (oop_result1->is_valid()) {
134 get_vm_result(oop_result1, thread);
135 }
136 if (metadata_result->is_valid()) {
137 get_vm_result_2(metadata_result, thread);
138 }
139 return call_offset;
140 }
141
142
143 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
144 #ifdef _LP64
145 mov(c_rarg1, arg1);
146 #else
147 push(arg1);
148 #endif // _LP64
149 return call_RT(oop_result1, metadata_result, entry, 1);
150 }
151
152
153 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
154 #ifdef _LP64
155 if (c_rarg1 == arg2) {
156 if (c_rarg2 == arg1) {
157 xchgq(arg1, arg2);
158 } else {
159 mov(c_rarg2, arg2);
160 mov(c_rarg1, arg1);
161 }
162 } else {
163 mov(c_rarg1, arg1);
164 mov(c_rarg2, arg2);
165 }
166 #else
167 push(arg2);
168 push(arg1);
169 #endif // _LP64
170 return call_RT(oop_result1, metadata_result, entry, 2);
171 }
172
173
174 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
175 #ifdef _LP64
176 // if there is any conflict use the stack
177 if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
178 arg2 == c_rarg1 || arg1 == c_rarg3 ||
179 arg3 == c_rarg1 || arg1 == c_rarg2) {
180 push(arg3);
181 push(arg2);
182 push(arg1);
183 pop(c_rarg1);
184 pop(c_rarg2);
185 pop(c_rarg3);
186 } else {
187 mov(c_rarg1, arg1);
188 mov(c_rarg2, arg2);
189 mov(c_rarg3, arg3);
190 }
191 #else
192 push(arg3);
193 push(arg2);
194 push(arg1);
195 #endif // _LP64
196 return call_RT(oop_result1, metadata_result, entry, 3);
197 }
198
199
200 // Implementation of StubFrame
201
202 class StubFrame: public StackObj {
203 private:
204 StubAssembler* _sasm;
205
206 public:
207 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
208 void load_argument(int offset_in_words, Register reg);
209
210 ~StubFrame();
211 };
212
213
214 #define __ _sasm->
215
216 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
217 _sasm = sasm;
218 __ set_info(name, must_gc_arguments);
219 __ enter();
220 }
221
222 // load parameters that were stored with LIR_Assembler::store_parameter
223 // Note: offsets for store_parameter and load_argument must match
224 void StubFrame::load_argument(int offset_in_words, Register reg) {
225 // rbp, + 0: link
226 // + 1: return address
227 // + 2: argument with offset 0
228 // + 3: argument with offset 1
229 // + 4: ...
230
231 __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
232 }
233
234
235 StubFrame::~StubFrame() {
236 __ leave();
237 __ ret(0);
238 }
239
240 #undef __
241
242
243 // Implementation of Runtime1
244
245 #define __ sasm->
246
247 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
248 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
249
250 // Stack layout for saving/restoring all the registers needed during a runtime
251 // call (this includes deoptimization)
252 // Note: note that users of this frame may well have arguments to some runtime
253 // while these values are on the stack. These positions neglect those arguments
254 // but the code in save_live_registers will take the argument count into
255 // account.
256 //
257 #ifdef _LP64
258 #define SLOT2(x) x,
259 #define SLOT_PER_WORD 2
260 #else
261 #define SLOT2(x)
262 #define SLOT_PER_WORD 1
263 #endif // _LP64
264
265 enum reg_save_layout {
266 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
267 // happen and will assert if the stack size we create is misaligned
268 #ifdef _LP64
269 align_dummy_0, align_dummy_1,
270 #endif // _LP64
271 #ifdef _WIN64
272 // Windows always allocates space for it's argument registers (see
273 // frame::arg_reg_save_area_bytes).
274 arg_reg_save_1, arg_reg_save_1H, // 0, 4
275 arg_reg_save_2, arg_reg_save_2H, // 8, 12
276 arg_reg_save_3, arg_reg_save_3H, // 16, 20
277 arg_reg_save_4, arg_reg_save_4H, // 24, 28
278 #endif // _WIN64
279 xmm_regs_as_doubles_off, // 32
280 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
281 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
282 // fpu_state_end_off is exclusive
283 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
284 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
285 extra_space_offset, // 360
286 #ifdef _LP64
287 r15_off = extra_space_offset, r15H_off, // 360, 364
288 r14_off, r14H_off, // 368, 372
289 r13_off, r13H_off, // 376, 380
290 r12_off, r12H_off, // 384, 388
291 r11_off, r11H_off, // 392, 396
292 r10_off, r10H_off, // 400, 404
293 r9_off, r9H_off, // 408, 412
294 r8_off, r8H_off, // 416, 420
295 rdi_off, rdiH_off, // 424, 428
296 #else
297 rdi_off = extra_space_offset,
298 #endif // _LP64
299 rsi_off, SLOT2(rsiH_off) // 432, 436
300 rbp_off, SLOT2(rbpH_off) // 440, 444
301 rsp_off, SLOT2(rspH_off) // 448, 452
302 rbx_off, SLOT2(rbxH_off) // 456, 460
303 rdx_off, SLOT2(rdxH_off) // 464, 468
304 rcx_off, SLOT2(rcxH_off) // 472, 476
305 rax_off, SLOT2(raxH_off) // 480, 484
306 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
307 return_off, SLOT2(returnH_off) // 496, 500
308 reg_save_frame_size // As noted: neglects any parameters to runtime // 504
309 };
310
311
312
313 // Save off registers which might be killed by calls into the runtime.
314 // Tries to smart of about FP registers. In particular we separate
315 // saving and describing the FPU registers for deoptimization since we
316 // have to save the FPU registers twice if we describe them and on P4
317 // saving FPU registers which don't contain anything appears
318 // expensive. The deopt blob is the only thing which needs to
319 // describe FPU registers. In all other cases it should be sufficient
320 // to simply save their current value.
321
322 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
323 bool save_fpu_registers = true) {
324
325 // In 64bit all the args are in regs so there are no additional stack slots
326 LP64_ONLY(num_rt_args = 0);
327 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
328 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
329 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
330
331 // record saved value locations in an OopMap
332 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
333 OopMap* map = new OopMap(frame_size_in_slots, 0);
334 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
335 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
336 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
337 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
338 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
339 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
340 #ifdef _LP64
341 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
342 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
343 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
344 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
345 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
346 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
347 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
348 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
349
350 // This is stupid but needed.
351 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
352 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
353 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
354 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
355 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
356 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
357
358 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
359 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
360 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
361 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
362 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
363 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
364 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
365 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
366 #endif // _LP64
367
368 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
369 #ifdef _LP64
370 if (UseAVX < 3) {
371 xmm_bypass_limit = xmm_bypass_limit / 2;
372 }
373 #endif
374
375 if (save_fpu_registers) {
376 if (UseSSE < 2) {
377 int fpu_off = float_regs_as_doubles_off;
378 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
379 VMReg fpu_name_0 = FrameMap::fpu_regname(n);
380 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
381 // %%% This is really a waste but we'll keep things as they were for now
382 if (true) {
383 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
384 }
385 fpu_off += 2;
386 }
387 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
388 }
389
390 if (UseSSE >= 2) {
391 int xmm_off = xmm_regs_as_doubles_off;
392 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
393 if (n < xmm_bypass_limit) {
394 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
395 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
396 // %%% This is really a waste but we'll keep things as they were for now
397 if (true) {
398 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
399 }
400 }
401 xmm_off += 2;
402 }
403 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
404
405 } else if (UseSSE == 1) {
406 int xmm_off = xmm_regs_as_doubles_off;
407 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
408 if (n < xmm_bypass_limit) {
409 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
410 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
411 }
412 xmm_off += 2;
413 }
414 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
415 }
416 }
417
418 return map;
419 }
420
421 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
422 bool save_fpu_registers = true) {
423 __ block_comment("save_live_registers");
424
425 __ pusha(); // integer registers
426
427 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
428 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
429
430 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
431
432 #ifdef ASSERT
433 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
434 #endif
435
436 if (save_fpu_registers) {
437 if (UseSSE < 2) {
438 // save FPU stack
439 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
440 __ fwait();
441
442 #ifdef ASSERT
443 Label ok;
444 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
445 __ jccb(Assembler::equal, ok);
446 __ stop("corrupted control word detected");
447 __ bind(ok);
448 #endif
449
450 // Reset the control word to guard against exceptions being unmasked
451 // since fstp_d can cause FPU stack underflow exceptions. Write it
452 // into the on stack copy and then reload that to make sure that the
453 // current and future values are correct.
454 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
455 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
456
457 // Save the FPU registers in de-opt-able form
458 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
459 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
460 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
461 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
462 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
463 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
464 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
465 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
466 }
467
468 if (UseSSE >= 2) {
469 // save XMM registers
470 // XMM registers can contain float or double values, but this is not known here,
471 // so always save them as doubles.
472 // note that float values are _not_ converted automatically, so for float values
473 // the second word contains only garbage data.
474 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
475 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
476 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
477 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
478 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
479 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
480 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
481 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
482 #ifdef _LP64
483 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
484 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
485 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
486 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
487 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
488 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
489 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
490 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
491 if (UseAVX > 2) {
492 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 128), xmm16);
493 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 136), xmm17);
494 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 144), xmm18);
495 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 152), xmm19);
496 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 160), xmm20);
497 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 168), xmm21);
498 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 176), xmm22);
499 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 184), xmm23);
500 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 192), xmm24);
501 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 200), xmm25);
502 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 208), xmm26);
503 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 216), xmm27);
504 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 224), xmm28);
505 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 232), xmm29);
506 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 240), xmm30);
507 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 248), xmm31);
508 }
509 #endif // _LP64
510 } else if (UseSSE == 1) {
511 // save XMM registers as float because double not supported without SSE2
512 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
513 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
514 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
515 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
516 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
517 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
518 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
519 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
520 }
521 }
522
523 // FPU stack must be empty now
524 __ verify_FPU(0, "save_live_registers");
525
526 return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
527 }
528
529
530 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
531 if (restore_fpu_registers) {
532 if (UseSSE >= 2) {
533 // restore XMM registers
534 __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
535 __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
536 __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
537 __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
538 __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
539 __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
540 __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
541 __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
542 #ifdef _LP64
543 __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
544 __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
545 __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
546 __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
547 __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
548 __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
549 __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
550 __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
551 if (UseAVX > 2) {
552 __ movdbl(xmm16, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 128));
553 __ movdbl(xmm17, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 136));
554 __ movdbl(xmm18, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 144));
555 __ movdbl(xmm19, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 152));
556 __ movdbl(xmm20, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 160));
557 __ movdbl(xmm21, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 168));
558 __ movdbl(xmm22, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 176));
559 __ movdbl(xmm23, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 184));
560 __ movdbl(xmm24, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 192));
561 __ movdbl(xmm25, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 200));
562 __ movdbl(xmm26, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 208));
563 __ movdbl(xmm27, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 216));
564 __ movdbl(xmm28, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 224));
565 __ movdbl(xmm29, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 232));
566 __ movdbl(xmm30, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 240));
567 __ movdbl(xmm31, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 248));
568 }
569 #endif // _LP64
570 } else if (UseSSE == 1) {
571 // restore XMM registers
572 __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
573 __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
574 __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
575 __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
576 __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
577 __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
578 __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
579 __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
580 }
581
582 if (UseSSE < 2) {
583 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
584 } else {
585 // check that FPU stack is really empty
586 __ verify_FPU(0, "restore_live_registers");
587 }
588
589 } else {
590 // check that FPU stack is really empty
591 __ verify_FPU(0, "restore_live_registers");
592 }
593
594 #ifdef ASSERT
595 {
596 Label ok;
597 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
598 __ jcc(Assembler::equal, ok);
599 __ stop("bad offsets in frame");
600 __ bind(ok);
601 }
602 #endif // ASSERT
603
604 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
605 }
606
607
608 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
609 __ block_comment("restore_live_registers");
610
611 restore_fpu(sasm, restore_fpu_registers);
612 __ popa();
613 }
614
615
616 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
617 __ block_comment("restore_live_registers_except_rax");
618
619 restore_fpu(sasm, restore_fpu_registers);
620
621 #ifdef _LP64
622 __ movptr(r15, Address(rsp, 0));
623 __ movptr(r14, Address(rsp, wordSize));
624 __ movptr(r13, Address(rsp, 2 * wordSize));
625 __ movptr(r12, Address(rsp, 3 * wordSize));
626 __ movptr(r11, Address(rsp, 4 * wordSize));
627 __ movptr(r10, Address(rsp, 5 * wordSize));
628 __ movptr(r9, Address(rsp, 6 * wordSize));
629 __ movptr(r8, Address(rsp, 7 * wordSize));
630 __ movptr(rdi, Address(rsp, 8 * wordSize));
631 __ movptr(rsi, Address(rsp, 9 * wordSize));
632 __ movptr(rbp, Address(rsp, 10 * wordSize));
633 // skip rsp
634 __ movptr(rbx, Address(rsp, 12 * wordSize));
635 __ movptr(rdx, Address(rsp, 13 * wordSize));
636 __ movptr(rcx, Address(rsp, 14 * wordSize));
637
638 __ addptr(rsp, 16 * wordSize);
639 #else
640
641 __ pop(rdi);
642 __ pop(rsi);
643 __ pop(rbp);
644 __ pop(rbx); // skip this value
645 __ pop(rbx);
646 __ pop(rdx);
647 __ pop(rcx);
648 __ addptr(rsp, BytesPerWord);
649 #endif // _LP64
650 }
651
652
653 void Runtime1::initialize_pd() {
654 // nothing to do
655 }
656
657
658 // target: the entry point of the method that creates and posts the exception oop
659 // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
660
661 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
662 // preserve all registers
663 int num_rt_args = has_argument ? 2 : 1;
664 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
665
666 // now all registers are saved and can be used freely
667 // verify that no old value is used accidentally
668 __ invalidate_registers(true, true, true, true, true, true);
669
670 // registers used by this stub
671 const Register temp_reg = rbx;
672
673 // load argument for exception that is passed as an argument into the stub
674 if (has_argument) {
675 #ifdef _LP64
676 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
677 #else
678 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
679 __ push(temp_reg);
680 #endif // _LP64
681 }
682 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
683
684 OopMapSet* oop_maps = new OopMapSet();
685 oop_maps->add_gc_map(call_offset, oop_map);
686
687 __ stop("should not reach here");
688
689 return oop_maps;
690 }
691
692
693 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
694 __ block_comment("generate_handle_exception");
695
696 // incoming parameters
697 const Register exception_oop = rax;
698 const Register exception_pc = rdx;
699 // other registers used in this stub
700 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
701
702 // Save registers, if required.
703 OopMapSet* oop_maps = new OopMapSet();
704 OopMap* oop_map = NULL;
705 switch (id) {
706 case forward_exception_id:
707 // We're handling an exception in the context of a compiled frame.
708 // The registers have been saved in the standard places. Perform
709 // an exception lookup in the caller and dispatch to the handler
710 // if found. Otherwise unwind and dispatch to the callers
711 // exception handler.
712 oop_map = generate_oop_map(sasm, 1 /*thread*/);
713
714 // load and clear pending exception oop into RAX
715 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
716 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
717
718 // load issuing PC (the return address for this stub) into rdx
719 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
720
721 // make sure that the vm_results are cleared (may be unnecessary)
722 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
723 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
724 break;
725 case handle_exception_nofpu_id:
726 case handle_exception_id:
727 // At this point all registers MAY be live.
728 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
729 break;
730 case handle_exception_from_callee_id: {
731 // At this point all registers except exception oop (RAX) and
732 // exception pc (RDX) are dead.
733 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
734 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
735 sasm->set_frame_size(frame_size);
736 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
737 break;
738 }
739 default: ShouldNotReachHere();
740 }
741
742 #ifdef TIERED
743 // C2 can leave the fpu stack dirty
744 if (UseSSE < 2) {
745 __ empty_FPU_stack();
746 }
747 #endif // TIERED
748
749 // verify that only rax, and rdx is valid at this time
750 __ invalidate_registers(false, true, true, false, true, true);
751 // verify that rax, contains a valid exception
752 __ verify_not_null_oop(exception_oop);
753
754 // load address of JavaThread object for thread-local data
755 NOT_LP64(__ get_thread(thread);)
756
757 #ifdef ASSERT
758 // check that fields in JavaThread for exception oop and issuing pc are
759 // empty before writing to them
760 Label oop_empty;
761 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
762 __ jcc(Assembler::equal, oop_empty);
763 __ stop("exception oop already set");
764 __ bind(oop_empty);
765
766 Label pc_empty;
767 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
768 __ jcc(Assembler::equal, pc_empty);
769 __ stop("exception pc already set");
770 __ bind(pc_empty);
771 #endif
772
773 // save exception oop and issuing pc into JavaThread
774 // (exception handler will load it from here)
775 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
776 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
777
778 // patch throwing pc into return address (has bci & oop map)
779 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
780
781 // compute the exception handler.
782 // the exception oop and the throwing pc are read from the fields in JavaThread
783 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
784 oop_maps->add_gc_map(call_offset, oop_map);
785
786 // rax: handler address
787 // will be the deopt blob if nmethod was deoptimized while we looked up
788 // handler regardless of whether handler existed in the nmethod.
789
790 // only rax, is valid at this time, all other registers have been destroyed by the runtime call
791 __ invalidate_registers(false, true, true, true, true, true);
792
793 // patch the return address, this stub will directly return to the exception handler
794 __ movptr(Address(rbp, 1*BytesPerWord), rax);
795
796 switch (id) {
797 case forward_exception_id:
798 case handle_exception_nofpu_id:
799 case handle_exception_id:
800 // Restore the registers that were saved at the beginning.
801 restore_live_registers(sasm, id != handle_exception_nofpu_id);
802 break;
803 case handle_exception_from_callee_id:
804 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
805 // since we do a leave anyway.
806
807 // Pop the return address.
808 __ leave();
809 __ pop(rcx);
810 __ jmp(rcx); // jump to exception handler
811 break;
812 default: ShouldNotReachHere();
813 }
814
815 return oop_maps;
816 }
817
818
819 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
820 // incoming parameters
821 const Register exception_oop = rax;
822 // callee-saved copy of exception_oop during runtime call
823 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
824 // other registers used in this stub
825 const Register exception_pc = rdx;
826 const Register handler_addr = rbx;
827 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
828
829 // verify that only rax, is valid at this time
830 __ invalidate_registers(false, true, true, true, true, true);
831
832 #ifdef ASSERT
833 // check that fields in JavaThread for exception oop and issuing pc are empty
834 NOT_LP64(__ get_thread(thread);)
835 Label oop_empty;
836 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
837 __ jcc(Assembler::equal, oop_empty);
838 __ stop("exception oop must be empty");
839 __ bind(oop_empty);
840
841 Label pc_empty;
842 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
843 __ jcc(Assembler::equal, pc_empty);
844 __ stop("exception pc must be empty");
845 __ bind(pc_empty);
846 #endif
847
848 // clear the FPU stack in case any FPU results are left behind
849 __ empty_FPU_stack();
850
851 // save exception_oop in callee-saved register to preserve it during runtime calls
852 __ verify_not_null_oop(exception_oop);
853 __ movptr(exception_oop_callee_saved, exception_oop);
854
855 NOT_LP64(__ get_thread(thread);)
856 // Get return address (is on top of stack after leave).
857 __ movptr(exception_pc, Address(rsp, 0));
858
859 // search the exception handler address of the caller (using the return address)
860 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
861 // rax: exception handler address of the caller
862
863 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
864 __ invalidate_registers(false, true, true, true, false, true);
865
866 // move result of call into correct register
867 __ movptr(handler_addr, rax);
868
869 // Restore exception oop to RAX (required convention of exception handler).
870 __ movptr(exception_oop, exception_oop_callee_saved);
871
872 // verify that there is really a valid exception in rax
873 __ verify_not_null_oop(exception_oop);
874
875 // get throwing pc (= return address).
876 // rdx has been destroyed by the call, so it must be set again
877 // the pop is also necessary to simulate the effect of a ret(0)
878 __ pop(exception_pc);
879
880 // continue at exception handler (return address removed)
881 // note: do *not* remove arguments when unwinding the
882 // activation since the caller assumes having
883 // all arguments on the stack when entering the
884 // runtime to determine the exception handler
885 // (GC happens at call site with arguments!)
886 // rax: exception oop
887 // rdx: throwing pc
888 // rbx: exception handler
889 __ jmp(handler_addr);
890 }
891
892
893 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
894 // use the maximum number of runtime-arguments here because it is difficult to
895 // distinguish each RT-Call.
896 // Note: This number affects also the RT-Call in generate_handle_exception because
897 // the oop-map is shared for all calls.
898 const int num_rt_args = 2; // thread + dummy
899
900 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
901 assert(deopt_blob != NULL, "deoptimization blob must have been created");
902
903 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
904
905 #ifdef _LP64
906 const Register thread = r15_thread;
907 // No need to worry about dummy
908 __ mov(c_rarg0, thread);
909 #else
910 __ push(rax); // push dummy
911
912 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
913 // push java thread (becomes first argument of C function)
914 __ get_thread(thread);
915 __ push(thread);
916 #endif // _LP64
917 __ set_last_Java_frame(thread, noreg, rbp, NULL);
918 // do the call
919 __ call(RuntimeAddress(target));
920 OopMapSet* oop_maps = new OopMapSet();
921 oop_maps->add_gc_map(__ offset(), oop_map);
922 // verify callee-saved register
923 #ifdef ASSERT
924 guarantee(thread != rax, "change this code");
925 __ push(rax);
926 { Label L;
927 __ get_thread(rax);
928 __ cmpptr(thread, rax);
929 __ jcc(Assembler::equal, L);
930 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
931 __ bind(L);
932 }
933 __ pop(rax);
934 #endif
935 __ reset_last_Java_frame(thread, true, false);
936 #ifndef _LP64
937 __ pop(rcx); // discard thread arg
938 __ pop(rcx); // discard dummy
939 #endif // _LP64
940
941 // check for pending exceptions
942 { Label L;
943 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
944 __ jcc(Assembler::equal, L);
945 // exception pending => remove activation and forward to exception handler
946
947 __ testptr(rax, rax); // have we deoptimized?
948 __ jump_cc(Assembler::equal,
949 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
950
951 // the deopt blob expects exceptions in the special fields of
952 // JavaThread, so copy and clear pending exception.
953
954 // load and clear pending exception
955 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
956 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
957
958 // check that there is really a valid exception
959 __ verify_not_null_oop(rax);
960
961 // load throwing pc: this is the return address of the stub
962 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
963
964 #ifdef ASSERT
965 // check that fields in JavaThread for exception oop and issuing pc are empty
966 Label oop_empty;
967 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
968 __ jcc(Assembler::equal, oop_empty);
969 __ stop("exception oop must be empty");
970 __ bind(oop_empty);
971
972 Label pc_empty;
973 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
974 __ jcc(Assembler::equal, pc_empty);
975 __ stop("exception pc must be empty");
976 __ bind(pc_empty);
977 #endif
978
979 // store exception oop and throwing pc to JavaThread
980 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
981 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
982
983 restore_live_registers(sasm);
984
985 __ leave();
986 __ addptr(rsp, BytesPerWord); // remove return address from stack
987
988 // Forward the exception directly to deopt blob. We can blow no
989 // registers and must leave throwing pc on the stack. A patch may
990 // have values live in registers so the entry point with the
991 // exception in tls.
992 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
993
994 __ bind(L);
995 }
996
997
998 // Runtime will return true if the nmethod has been deoptimized during
999 // the patching process. In that case we must do a deopt reexecute instead.
1000
1001 Label reexecuteEntry, cont;
1002
1003 __ testptr(rax, rax); // have we deoptimized?
1004 __ jcc(Assembler::equal, cont); // no
1005
1006 // Will reexecute. Proper return address is already on the stack we just restore
1007 // registers, pop all of our frame but the return address and jump to the deopt blob
1008 restore_live_registers(sasm);
1009 __ leave();
1010 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1011
1012 __ bind(cont);
1013 restore_live_registers(sasm);
1014 __ leave();
1015 __ ret(0);
1016
1017 return oop_maps;
1018 }
1019
1020
1021 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
1022
1023 // for better readability
1024 const bool must_gc_arguments = true;
1025 const bool dont_gc_arguments = false;
1026
1027 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
1028 bool save_fpu_registers = true;
1029
1030 // stub code & info for the different stubs
1031 OopMapSet* oop_maps = NULL;
1032 switch (id) {
1033 case forward_exception_id:
1034 {
1035 oop_maps = generate_handle_exception(id, sasm);
1036 __ leave();
1037 __ ret(0);
1038 }
1039 break;
1040
1041 case new_instance_id:
1042 case fast_new_instance_id:
1043 case fast_new_instance_init_check_id:
1044 {
1045 Register klass = rdx; // Incoming
1046 Register obj = rax; // Result
1047
1048 if (id == new_instance_id) {
1049 __ set_info("new_instance", dont_gc_arguments);
1050 } else if (id == fast_new_instance_id) {
1051 __ set_info("fast new_instance", dont_gc_arguments);
1052 } else {
1053 assert(id == fast_new_instance_init_check_id, "bad StubID");
1054 __ set_info("fast new_instance init check", dont_gc_arguments);
1055 }
1056
1057 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) &&
1058 UseTLAB && FastTLABRefill) {
1059 Label slow_path;
1060 Register obj_size = rcx;
1061 Register t1 = rbx;
1062 Register t2 = rsi;
1063 assert_different_registers(klass, obj, obj_size, t1, t2);
1064
1065 __ push(rdi);
1066 __ push(rbx);
1067
1068 if (id == fast_new_instance_init_check_id) {
1069 // make sure the klass is initialized
1070 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
1071 __ jcc(Assembler::notEqual, slow_path);
1072 }
1073
1074 #ifdef ASSERT
1075 // assert object can be fast path allocated
1076 {
1077 Label ok, not_ok;
1078 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1079 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0)
1080 __ jcc(Assembler::lessEqual, not_ok);
1081 __ testl(obj_size, Klass::_lh_instance_slow_path_bit);
1082 __ jcc(Assembler::zero, ok);
1083 __ bind(not_ok);
1084 __ stop("assert(can be fast path allocated)");
1085 __ should_not_reach_here();
1086 __ bind(ok);
1087 }
1088 #endif // ASSERT
1089
1090 // if we got here then the TLAB allocation failed, so try
1091 // refilling the TLAB or allocating directly from eden.
1092 Label retry_tlab, try_eden;
1093 const Register thread =
1094 __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy rdx (klass), returns rdi
1095
1096 __ bind(retry_tlab);
1097
1098 // get the instance size (size is postive so movl is fine for 64bit)
1099 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1100
1101 __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
1102
1103 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1104 __ verify_oop(obj);
1105 __ pop(rbx);
1106 __ pop(rdi);
1107 __ ret(0);
1108
1109 __ bind(try_eden);
1110 // get the instance size (size is postive so movl is fine for 64bit)
1111 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1112
1113 __ eden_allocate(obj, obj_size, 0, t1, slow_path);
1114 __ incr_allocated_bytes(thread, obj_size, 0);
1115
1116 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1117 __ verify_oop(obj);
1118 __ pop(rbx);
1119 __ pop(rdi);
1120 __ ret(0);
1121
1122 __ bind(slow_path);
1123 __ pop(rbx);
1124 __ pop(rdi);
1125 }
1126
1127 __ enter();
1128 OopMap* map = save_live_registers(sasm, 2);
1129 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1130 oop_maps = new OopMapSet();
1131 oop_maps->add_gc_map(call_offset, map);
1132 restore_live_registers_except_rax(sasm);
1133 __ verify_oop(obj);
1134 __ leave();
1135 __ ret(0);
1136
1137 // rax,: new instance
1138 }
1139
1140 break;
1141
1142 case counter_overflow_id:
1143 {
1144 Register bci = rax, method = rbx;
1145 __ enter();
1146 OopMap* map = save_live_registers(sasm, 3);
1147 // Retrieve bci
1148 __ movl(bci, Address(rbp, 2*BytesPerWord));
1149 // And a pointer to the Method*
1150 __ movptr(method, Address(rbp, 3*BytesPerWord));
1151 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1152 oop_maps = new OopMapSet();
1153 oop_maps->add_gc_map(call_offset, map);
1154 restore_live_registers(sasm);
1155 __ leave();
1156 __ ret(0);
1157 }
1158 break;
1159
1160 case new_type_array_id:
1161 case new_object_array_id:
1162 {
1163 Register length = rbx; // Incoming
1164 Register klass = rdx; // Incoming
1165 Register obj = rax; // Result
1166
1167 if (id == new_type_array_id) {
1168 __ set_info("new_type_array", dont_gc_arguments);
1169 } else {
1170 __ set_info("new_object_array", dont_gc_arguments);
1171 }
1172
1173 #ifdef ASSERT
1174 // assert object type is really an array of the proper kind
1175 {
1176 Label ok;
1177 Register t0 = obj;
1178 __ movl(t0, Address(klass, Klass::layout_helper_offset()));
1179 __ sarl(t0, Klass::_lh_array_tag_shift);
1180 int tag = ((id == new_type_array_id)
1181 ? Klass::_lh_array_tag_type_value
1182 : Klass::_lh_array_tag_obj_value);
1183 __ cmpl(t0, tag);
1184 __ jcc(Assembler::equal, ok);
1185 __ stop("assert(is an array klass)");
1186 __ should_not_reach_here();
1187 __ bind(ok);
1188 }
1189 #endif // ASSERT
1190
1191 if (UseTLAB && FastTLABRefill) {
1192 Register arr_size = rsi;
1193 Register t1 = rcx; // must be rcx for use as shift count
1194 Register t2 = rdi;
1195 Label slow_path;
1196 assert_different_registers(length, klass, obj, arr_size, t1, t2);
1197
1198 // check that array length is small enough for fast path.
1199 __ cmpl(length, C1_MacroAssembler::max_array_allocation_length);
1200 __ jcc(Assembler::above, slow_path);
1201
1202 // if we got here then the TLAB allocation failed, so try
1203 // refilling the TLAB or allocating directly from eden.
1204 Label retry_tlab, try_eden;
1205 const Register thread =
1206 __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves rbx & rdx, returns rdi
1207
1208 __ bind(retry_tlab);
1209
1210 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1211 // since size is positive movl does right thing on 64bit
1212 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1213 // since size is postive movl does right thing on 64bit
1214 __ movl(arr_size, length);
1215 assert(t1 == rcx, "fixed register usage");
1216 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1217 __ shrptr(t1, Klass::_lh_header_size_shift);
1218 __ andptr(t1, Klass::_lh_header_size_mask);
1219 __ addptr(arr_size, t1);
1220 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1221 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1222
1223 __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
1224
1225 __ initialize_header(obj, klass, length, t1, t2);
1226 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1227 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1228 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1229 __ andptr(t1, Klass::_lh_header_size_mask);
1230 __ subptr(arr_size, t1); // body length
1231 __ addptr(t1, obj); // body start
1232 __ initialize_body(t1, arr_size, 0, t2);
1233 __ verify_oop(obj);
1234 __ ret(0);
1235
1236 __ bind(try_eden);
1237 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1238 // since size is positive movl does right thing on 64bit
1239 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1240 // since size is postive movl does right thing on 64bit
1241 __ movl(arr_size, length);
1242 assert(t1 == rcx, "fixed register usage");
1243 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1244 __ shrptr(t1, Klass::_lh_header_size_shift);
1245 __ andptr(t1, Klass::_lh_header_size_mask);
1246 __ addptr(arr_size, t1);
1247 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1248 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1249
1250 __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
1251 __ incr_allocated_bytes(thread, arr_size, 0);
1252
1253 __ initialize_header(obj, klass, length, t1, t2);
1254 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1255 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1256 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1257 __ andptr(t1, Klass::_lh_header_size_mask);
1258 __ subptr(arr_size, t1); // body length
1259 __ addptr(t1, obj); // body start
1260 __ initialize_body(t1, arr_size, 0, t2);
1261 __ verify_oop(obj);
1262 __ ret(0);
1263
1264 __ bind(slow_path);
1265 }
1266
1267 __ enter();
1268 OopMap* map = save_live_registers(sasm, 3);
1269 int call_offset;
1270 if (id == new_type_array_id) {
1271 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1272 } else {
1273 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1274 }
1275
1276 oop_maps = new OopMapSet();
1277 oop_maps->add_gc_map(call_offset, map);
1278 restore_live_registers_except_rax(sasm);
1279
1280 __ verify_oop(obj);
1281 __ leave();
1282 __ ret(0);
1283
1284 // rax,: new array
1285 }
1286 break;
1287
1288 case new_multi_array_id:
1289 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1290 // rax,: klass
1291 // rbx,: rank
1292 // rcx: address of 1st dimension
1293 OopMap* map = save_live_registers(sasm, 4);
1294 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
1295
1296 oop_maps = new OopMapSet();
1297 oop_maps->add_gc_map(call_offset, map);
1298 restore_live_registers_except_rax(sasm);
1299
1300 // rax,: new multi array
1301 __ verify_oop(rax);
1302 }
1303 break;
1304
1305 case register_finalizer_id:
1306 {
1307 __ set_info("register_finalizer", dont_gc_arguments);
1308
1309 // This is called via call_runtime so the arguments
1310 // will be place in C abi locations
1311
1312 #ifdef _LP64
1313 __ verify_oop(c_rarg0);
1314 __ mov(rax, c_rarg0);
1315 #else
1316 // The object is passed on the stack and we haven't pushed a
1317 // frame yet so it's one work away from top of stack.
1318 __ movptr(rax, Address(rsp, 1 * BytesPerWord));
1319 __ verify_oop(rax);
1320 #endif // _LP64
1321
1322 // load the klass and check the has finalizer flag
1323 Label register_finalizer;
1324 Register t = rsi;
1325 __ load_klass(t, rax);
1326 __ movl(t, Address(t, Klass::access_flags_offset()));
1327 __ testl(t, JVM_ACC_HAS_FINALIZER);
1328 __ jcc(Assembler::notZero, register_finalizer);
1329 __ ret(0);
1330
1331 __ bind(register_finalizer);
1332 __ enter();
1333 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
1334 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
1335 oop_maps = new OopMapSet();
1336 oop_maps->add_gc_map(call_offset, oop_map);
1337
1338 // Now restore all the live registers
1339 restore_live_registers(sasm);
1340
1341 __ leave();
1342 __ ret(0);
1343 }
1344 break;
1345
1346 case throw_range_check_failed_id:
1347 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1348 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
1349 }
1350 break;
1351
1352 case throw_index_exception_id:
1353 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1354 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
1355 }
1356 break;
1357
1358 case throw_div0_exception_id:
1359 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1360 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
1361 }
1362 break;
1363
1364 case throw_null_pointer_exception_id:
1365 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1366 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
1367 }
1368 break;
1369
1370 case handle_exception_nofpu_id:
1371 case handle_exception_id:
1372 { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1373 oop_maps = generate_handle_exception(id, sasm);
1374 }
1375 break;
1376
1377 case handle_exception_from_callee_id:
1378 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1379 oop_maps = generate_handle_exception(id, sasm);
1380 }
1381 break;
1382
1383 case unwind_exception_id:
1384 { __ set_info("unwind_exception", dont_gc_arguments);
1385 // note: no stubframe since we are about to leave the current
1386 // activation and we are calling a leaf VM function only.
1387 generate_unwind_exception(sasm);
1388 }
1389 break;
1390
1391 case throw_array_store_exception_id:
1392 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1393 // tos + 0: link
1394 // + 1: return address
1395 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1396 }
1397 break;
1398
1399 case throw_class_cast_exception_id:
1400 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1401 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1402 }
1403 break;
1404
1405 case throw_incompatible_class_change_error_id:
1406 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
1407 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1408 }
1409 break;
1410
1411 case slow_subtype_check_id:
1412 {
1413 // Typical calling sequence:
1414 // __ push(klass_RInfo); // object klass or other subclass
1415 // __ push(sup_k_RInfo); // array element klass or other superclass
1416 // __ call(slow_subtype_check);
1417 // Note that the subclass is pushed first, and is therefore deepest.
1418 // Previous versions of this code reversed the names 'sub' and 'super'.
1419 // This was operationally harmless but made the code unreadable.
1420 enum layout {
1421 rax_off, SLOT2(raxH_off)
1422 rcx_off, SLOT2(rcxH_off)
1423 rsi_off, SLOT2(rsiH_off)
1424 rdi_off, SLOT2(rdiH_off)
1425 // saved_rbp_off, SLOT2(saved_rbpH_off)
1426 return_off, SLOT2(returnH_off)
1427 sup_k_off, SLOT2(sup_kH_off)
1428 klass_off, SLOT2(superH_off)
1429 framesize,
1430 result_off = klass_off // deepest argument is also the return value
1431 };
1432
1433 __ set_info("slow_subtype_check", dont_gc_arguments);
1434 __ push(rdi);
1435 __ push(rsi);
1436 __ push(rcx);
1437 __ push(rax);
1438
1439 // This is called by pushing args and not with C abi
1440 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
1441 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
1442
1443 Label miss;
1444 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss);
1445
1446 // fallthrough on success:
1447 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
1448 __ pop(rax);
1449 __ pop(rcx);
1450 __ pop(rsi);
1451 __ pop(rdi);
1452 __ ret(0);
1453
1454 __ bind(miss);
1455 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
1456 __ pop(rax);
1457 __ pop(rcx);
1458 __ pop(rsi);
1459 __ pop(rdi);
1460 __ ret(0);
1461 }
1462 break;
1463
1464 case monitorenter_nofpu_id:
1465 save_fpu_registers = false;
1466 // fall through
1467 case monitorenter_id:
1468 {
1469 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1470 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
1471
1472 // Called with store_parameter and not C abi
1473
1474 f.load_argument(1, rax); // rax,: object
1475 f.load_argument(0, rbx); // rbx,: lock address
1476
1477 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
1478
1479 oop_maps = new OopMapSet();
1480 oop_maps->add_gc_map(call_offset, map);
1481 restore_live_registers(sasm, save_fpu_registers);
1482 }
1483 break;
1484
1485 case monitorexit_nofpu_id:
1486 save_fpu_registers = false;
1487 // fall through
1488 case monitorexit_id:
1489 {
1490 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1491 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
1492
1493 // Called with store_parameter and not C abi
1494
1495 f.load_argument(0, rax); // rax,: lock address
1496
1497 // note: really a leaf routine but must setup last java sp
1498 // => use call_RT for now (speed can be improved by
1499 // doing last java sp setup manually)
1500 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
1501
1502 oop_maps = new OopMapSet();
1503 oop_maps->add_gc_map(call_offset, map);
1504 restore_live_registers(sasm, save_fpu_registers);
1505 }
1506 break;
1507
1508 case deoptimize_id:
1509 {
1510 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1511 const int num_rt_args = 2; // thread, trap_request
1512 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1513 f.load_argument(0, rax);
1514 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax);
1515 oop_maps = new OopMapSet();
1516 oop_maps->add_gc_map(call_offset, oop_map);
1517 restore_live_registers(sasm);
1518 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1519 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1520 __ leave();
1521 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1522 }
1523 break;
1524
1525 case access_field_patching_id:
1526 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1527 // we should set up register map
1528 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1529 }
1530 break;
1531
1532 case load_klass_patching_id:
1533 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1534 // we should set up register map
1535 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1536 }
1537 break;
1538
1539 case load_mirror_patching_id:
1540 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments);
1541 // we should set up register map
1542 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1543 }
1544 break;
1545
1546 case load_appendix_patching_id:
1547 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1548 // we should set up register map
1549 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1550 }
1551 break;
1552
1553 case dtrace_object_alloc_id:
1554 { // rax,: object
1555 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1556 // we can't gc here so skip the oopmap but make sure that all
1557 // the live registers get saved.
1558 save_live_registers(sasm, 1);
1559
1560 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
1561 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
1562 NOT_LP64(__ pop(rax));
1563
1564 restore_live_registers(sasm);
1565 }
1566 break;
1567
1568 case fpu2long_stub_id:
1569 {
1570 // rax, and rdx are destroyed, but should be free since the result is returned there
1571 // preserve rsi,ecx
1572 __ push(rsi);
1573 __ push(rcx);
1574 LP64_ONLY(__ push(rdx);)
1575
1576 // check for NaN
1577 Label return0, do_return, return_min_jlong, do_convert;
1578
1579 Address value_high_word(rsp, wordSize + 4);
1580 Address value_low_word(rsp, wordSize);
1581 Address result_high_word(rsp, 3*wordSize + 4);
1582 Address result_low_word(rsp, 3*wordSize);
1583
1584 __ subptr(rsp, 32); // more than enough on 32bit
1585 __ fst_d(value_low_word);
1586 __ movl(rax, value_high_word);
1587 __ andl(rax, 0x7ff00000);
1588 __ cmpl(rax, 0x7ff00000);
1589 __ jcc(Assembler::notEqual, do_convert);
1590 __ movl(rax, value_high_word);
1591 __ andl(rax, 0xfffff);
1592 __ orl(rax, value_low_word);
1593 __ jcc(Assembler::notZero, return0);
1594
1595 __ bind(do_convert);
1596 __ fnstcw(Address(rsp, 0));
1597 __ movzwl(rax, Address(rsp, 0));
1598 __ orl(rax, 0xc00);
1599 __ movw(Address(rsp, 2), rax);
1600 __ fldcw(Address(rsp, 2));
1601 __ fwait();
1602 __ fistp_d(result_low_word);
1603 __ fldcw(Address(rsp, 0));
1604 __ fwait();
1605 // This gets the entire long in rax on 64bit
1606 __ movptr(rax, result_low_word);
1607 // testing of high bits
1608 __ movl(rdx, result_high_word);
1609 __ mov(rcx, rax);
1610 // What the heck is the point of the next instruction???
1611 __ xorl(rcx, 0x0);
1612 __ movl(rsi, 0x80000000);
1613 __ xorl(rsi, rdx);
1614 __ orl(rcx, rsi);
1615 __ jcc(Assembler::notEqual, do_return);
1616 __ fldz();
1617 __ fcomp_d(value_low_word);
1618 __ fnstsw_ax();
1619 #ifdef _LP64
1620 __ testl(rax, 0x4100); // ZF & CF == 0
1621 __ jcc(Assembler::equal, return_min_jlong);
1622 #else
1623 __ sahf();
1624 __ jcc(Assembler::above, return_min_jlong);
1625 #endif // _LP64
1626 // return max_jlong
1627 #ifndef _LP64
1628 __ movl(rdx, 0x7fffffff);
1629 __ movl(rax, 0xffffffff);
1630 #else
1631 __ mov64(rax, CONST64(0x7fffffffffffffff));
1632 #endif // _LP64
1633 __ jmp(do_return);
1634
1635 __ bind(return_min_jlong);
1636 #ifndef _LP64
1637 __ movl(rdx, 0x80000000);
1638 __ xorl(rax, rax);
1639 #else
1640 __ mov64(rax, UCONST64(0x8000000000000000));
1641 #endif // _LP64
1642 __ jmp(do_return);
1643
1644 __ bind(return0);
1645 __ fpop();
1646 #ifndef _LP64
1647 __ xorptr(rdx,rdx);
1648 __ xorptr(rax,rax);
1649 #else
1650 __ xorptr(rax, rax);
1651 #endif // _LP64
1652
1653 __ bind(do_return);
1654 __ addptr(rsp, 32);
1655 LP64_ONLY(__ pop(rdx);)
1656 __ pop(rcx);
1657 __ pop(rsi);
1658 __ ret(0);
1659 }
1660 break;
1661
1662 #if INCLUDE_ALL_GCS
1663 case shenandoah_write_barrier_slow_id:
1664 {
1665 StubFrame f(sasm, "shenandoah_write_barrier", dont_gc_arguments);
1666
1667 save_live_registers(sasm, 1);
1668 __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahBarrierSet::resolve_and_maybe_copy_oop_c1), r15_thread, rax);
1669 restore_live_registers_except_rax(sasm);
1670 __ verify_oop(rax);
1671
1672 }
1673 break;
1674 case g1_pre_barrier_slow_id:
1675 {
1676 StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments);
1677 // arg0 : previous value of memory
1678
1679 BarrierSet* bs = Universe::heap()->barrier_set();
1680 if (bs->kind() != BarrierSet::G1SATBCTLogging && bs->kind() != BarrierSet::ShenandoahBarrierSet) {
1681 __ movptr(rax, (int)id);
1682 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1683 __ should_not_reach_here();
1684 break;
1685 }
1686 __ push(rax);
1687 __ push(rdx);
1688
1689 const Register pre_val = rax;
1690 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1691 const Register tmp = rdx;
1692
1693 NOT_LP64(__ get_thread(thread);)
1694
1695 Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1696 PtrQueue::byte_offset_of_index()));
1697 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1698 PtrQueue::byte_offset_of_buf()));
1699
1700 Label done;
1701 Label runtime;
1702
1703 // Can we store original value in the thread's buffer?
1704
1705 __ movptr(tmp, queue_index);
1706 __ testptr(tmp, tmp);
1707 __ jcc(Assembler::zero, runtime);
1708 __ subptr(tmp, wordSize);
1709 __ movptr(queue_index, tmp);
1710 __ addptr(tmp, buffer);
1711
1712 // prev_val (rax)
1713 f.load_argument(0, pre_val);
1714 __ movptr(Address(tmp, 0), pre_val);
1715 __ jmp(done);
1716
1717 __ bind(runtime);
1718 __ push(rcx);
1719 #ifdef _LP64
1720 __ push(r8);
1721 __ push(r9);
1722 __ push(r10);
1723 __ push(r11);
1724 # ifndef _WIN64
1725 __ push(rdi);
1726 __ push(rsi);
1727 # endif
1728 #endif
1729 // load the pre-value
1730 f.load_argument(0, rcx);
1731 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread);
1732 #ifdef _LP64
1733 # ifndef _WIN64
1734 __ pop(rsi);
1735 __ pop(rdi);
1736 # endif
1737 __ pop(r11);
1738 __ pop(r10);
1739 __ pop(r9);
1740 __ pop(r8);
1741 #endif
1742 __ pop(rcx);
1743 __ bind(done);
1744
1745 __ pop(rdx);
1746 __ pop(rax);
1747 }
1748 break;
1749
1750 case g1_post_barrier_slow_id:
1751 {
1752 StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments);
1753
1754
1755 // arg0: store_address
1756 Address store_addr(rbp, 2*BytesPerWord);
1757
1758 BarrierSet* bs = Universe::heap()->barrier_set();
1759 if (bs->kind() == BarrierSet::ShenandoahBarrierSet) {
1760 __ movptr(rax, (int)id);
1761 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1762 __ should_not_reach_here();
1763 break;
1764 }
1765 CardTableModRefBS* ct =
1766 barrier_set_cast<CardTableModRefBS>(bs);
1767 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1768
1769 Label done;
1770 Label enqueued;
1771 Label runtime;
1772
1773 // At this point we know new_value is non-NULL and the new_value crosses regions.
1774 // Must check to see if card is already dirty
1775
1776 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1777
1778 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1779 PtrQueue::byte_offset_of_index()));
1780 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1781 PtrQueue::byte_offset_of_buf()));
1782
1783 __ push(rax);
1784 __ push(rcx);
1785
1786 const Register cardtable = rax;
1787 const Register card_addr = rcx;
1788
1789 f.load_argument(0, card_addr);
1790 __ shrptr(card_addr, CardTableModRefBS::card_shift);
1791 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1792 // a valid address and therefore is not properly handled by the relocation code.
1793 __ movptr(cardtable, (intptr_t)ct->byte_map_base);
1794 __ addptr(card_addr, cardtable);
1795
1796 NOT_LP64(__ get_thread(thread);)
1797
1798 __ cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
1799 __ jcc(Assembler::equal, done);
1800
1801 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1802 __ cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1803 __ jcc(Assembler::equal, done);
1804
1805 // storing region crossing non-NULL, card is clean.
1806 // dirty card and log.
1807
1808 __ movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1809
1810 const Register tmp = rdx;
1811 __ push(rdx);
1812
1813 __ movptr(tmp, queue_index);
1814 __ testptr(tmp, tmp);
1815 __ jcc(Assembler::zero, runtime);
1816 __ subptr(tmp, wordSize);
1817 __ movptr(queue_index, tmp);
1818 __ addptr(tmp, buffer);
1819 __ movptr(Address(tmp, 0), card_addr);
1820 __ jmp(enqueued);
1821
1822 __ bind(runtime);
1823 #ifdef _LP64
1824 __ push(r8);
1825 __ push(r9);
1826 __ push(r10);
1827 __ push(r11);
1828 # ifndef _WIN64
1829 __ push(rdi);
1830 __ push(rsi);
1831 # endif
1832 #endif
1833 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1834 #ifdef _LP64
1835 # ifndef _WIN64
1836 __ pop(rsi);
1837 __ pop(rdi);
1838 # endif
1839 __ pop(r11);
1840 __ pop(r10);
1841 __ pop(r9);
1842 __ pop(r8);
1843 #endif
1844 __ bind(enqueued);
1845 __ pop(rdx);
1846
1847 __ bind(done);
1848 __ pop(rcx);
1849 __ pop(rax);
1850 }
1851 break;
1852 #endif // INCLUDE_ALL_GCS
1853
1854 case predicate_failed_trap_id:
1855 {
1856 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1857
1858 OopMap* map = save_live_registers(sasm, 1);
1859
1860 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1861 oop_maps = new OopMapSet();
1862 oop_maps->add_gc_map(call_offset, map);
1863 restore_live_registers(sasm);
1864 __ leave();
1865 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1866 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1867
1868 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1869 }
1870 break;
1871
1872 default:
1873 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1874 __ movptr(rax, (int)id);
1875 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1876 __ should_not_reach_here();
1877 }
1878 break;
1879 }
1880 return oop_maps;
1881 }
1882
1883 #undef __
1884
1885 const char *Runtime1::pd_name_for_address(address entry) {
1886 return "<unknown function>";
1887 }