1 /*
2 * Copyright (c) 2005, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_Instruction.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_LIRGenerator.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArray.hpp"
34 #include "ci/ciObjArrayKlass.hpp"
35 #include "ci/ciTypeArrayKlass.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "vmreg_x86.inline.hpp"
39
40 #ifdef ASSERT
41 #define __ gen()->lir(__FILE__, __LINE__)->
42 #else
43 #define __ gen()->lir()->
44 #endif
45
46 // Item will be loaded into a byte register; Intel only
47 void LIRItem::load_byte_item() {
48 load_item();
49 LIR_Opr res = result();
50
51 if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {
52 // make sure that it is a byte register
53 assert(!value()->type()->is_float() && !value()->type()->is_double(),
54 "can't load floats in byte register");
55 LIR_Opr reg = _gen->rlock_byte(T_BYTE);
56 __ move(res, reg);
57
58 _result = reg;
59 }
60 }
61
62
63 void LIRItem::load_nonconstant() {
64 LIR_Opr r = value()->operand();
65 if (r->is_constant()) {
66 _result = r;
67 } else {
68 load_item();
69 }
70 }
71
72 //--------------------------------------------------------------
73 // LIRGenerator
74 //--------------------------------------------------------------
75
76
77 LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::rax_oop_opr; }
78 LIR_Opr LIRGenerator::exceptionPcOpr() { return FrameMap::rdx_opr; }
79 LIR_Opr LIRGenerator::divInOpr() { return FrameMap::rax_opr; }
80 LIR_Opr LIRGenerator::divOutOpr() { return FrameMap::rax_opr; }
81 LIR_Opr LIRGenerator::remOutOpr() { return FrameMap::rdx_opr; }
82 LIR_Opr LIRGenerator::shiftCountOpr() { return FrameMap::rcx_opr; }
83 LIR_Opr LIRGenerator::syncTempOpr() { return FrameMap::rax_opr; }
84 LIR_Opr LIRGenerator::getThreadTemp() { return LIR_OprFact::illegalOpr; }
85
86
87 LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {
88 LIR_Opr opr;
89 switch (type->tag()) {
90 case intTag: opr = FrameMap::rax_opr; break;
91 case objectTag: opr = FrameMap::rax_oop_opr; break;
92 case longTag: opr = FrameMap::long0_opr; break;
93 case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break;
94 case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break;
95
96 case addressTag:
97 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
98 }
99
100 assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");
101 return opr;
102 }
103
104
105 LIR_Opr LIRGenerator::rlock_byte(BasicType type) {
106 LIR_Opr reg = new_register(T_INT);
107 set_vreg_flag(reg, LIRGenerator::byte_reg);
108 return reg;
109 }
110
111
112 //--------- loading items into registers --------------------------------
113
114
115 // i486 instructions can inline constants
116 bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {
117 if (type == T_SHORT || type == T_CHAR) {
118 // there is no immediate move of word values in asembler_i486.?pp
119 return false;
120 }
121 Constant* c = v->as_Constant();
122 if (c && c->state_before() == NULL) {
123 // constants of any type can be stored directly, except for
124 // unloaded object constants.
125 return true;
126 }
127 return false;
128 }
129
130
131 bool LIRGenerator::can_inline_as_constant(Value v) const {
132 if (v->type()->tag() == longTag) return false;
133 return v->type()->tag() != objectTag ||
134 (v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
135 }
136
137
138 bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
139 if (c->type() == T_LONG) return false;
140 return c->type() != T_OBJECT || c->as_jobject() == NULL;
141 }
142
143
144 LIR_Opr LIRGenerator::safepoint_poll_register() {
145 return LIR_OprFact::illegalOpr;
146 }
147
148
149 LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,
150 int shift, int disp, BasicType type) {
151 assert(base->is_register(), "must be");
152 if (index->is_constant()) {
153 return new LIR_Address(base,
154 (index->as_constant_ptr()->as_jint() << shift) + disp,
155 type);
156 } else {
157 return new LIR_Address(base, index, (LIR_Address::Scale)shift, disp, type);
158 }
159 }
160
161
162 LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,
163 BasicType type, bool needs_card_mark) {
164 int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);
165
166 LIR_Address* addr;
167 if (index_opr->is_constant()) {
168 int elem_size = type2aelembytes(type);
169 addr = new LIR_Address(array_opr,
170 offset_in_bytes + index_opr->as_jint() * elem_size, type);
171 } else {
172 #ifdef _LP64
173 if (index_opr->type() == T_INT) {
174 LIR_Opr tmp = new_register(T_LONG);
175 __ convert(Bytecodes::_i2l, index_opr, tmp);
176 index_opr = tmp;
177 }
178 #endif // _LP64
179 addr = new LIR_Address(array_opr,
180 index_opr,
181 LIR_Address::scale(type),
182 offset_in_bytes, type);
183 }
184 if (needs_card_mark) {
185 // This store will need a precise card mark, so go ahead and
186 // compute the full adddres instead of computing once for the
187 // store and again for the card mark.
188 LIR_Opr tmp = new_pointer_register();
189 __ leal(LIR_OprFact::address(addr), tmp);
190 return new LIR_Address(tmp, type);
191 } else {
192 return addr;
193 }
194 }
195
196
197 LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {
198 LIR_Opr r;
199 if (type == T_LONG) {
200 r = LIR_OprFact::longConst(x);
201 } else if (type == T_INT) {
202 r = LIR_OprFact::intConst(x);
203 } else {
204 ShouldNotReachHere();
205 }
206 return r;
207 }
208
209 void LIRGenerator::increment_counter(address counter, BasicType type, int step) {
210 LIR_Opr pointer = new_pointer_register();
211 __ move(LIR_OprFact::intptrConst(counter), pointer);
212 LIR_Address* addr = new LIR_Address(pointer, type);
213 increment_counter(addr, step);
214 }
215
216
217 void LIRGenerator::increment_counter(LIR_Address* addr, int step) {
218 __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr);
219 }
220
221 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
222 __ cmp_mem_int(condition, base, disp, c, info);
223 }
224
225
226 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {
227 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
228 }
229
230
231 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {
232 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
233 }
234
235
236 bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
237 if (tmp->is_valid()) {
238 if (is_power_of_2(c + 1)) {
239 __ move(left, tmp);
240 __ shift_left(left, log2_intptr(c + 1), left);
241 __ sub(left, tmp, result);
242 return true;
243 } else if (is_power_of_2(c - 1)) {
244 __ move(left, tmp);
245 __ shift_left(left, log2_intptr(c - 1), left);
246 __ add(left, tmp, result);
247 return true;
248 }
249 }
250 return false;
251 }
252
253
254 void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {
255 BasicType type = item->type();
256 __ store(item, new LIR_Address(FrameMap::rsp_opr, in_bytes(offset_from_sp), type));
257 }
258
259 //----------------------------------------------------------------------
260 // visitor functions
261 //----------------------------------------------------------------------
262
263
264 void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {
265 assert(x->is_pinned(),"");
266 bool needs_range_check = x->compute_needs_range_check();
267 bool use_length = x->length() != NULL;
268 bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;
269 bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||
270 !get_jobject_constant(x->value())->is_null_object() ||
271 x->should_profile());
272
273 LIRItem array(x->array(), this);
274 LIRItem index(x->index(), this);
275 LIRItem value(x->value(), this);
276 LIRItem length(this);
277
278 array.load_item();
279 index.load_nonconstant();
280
281 if (use_length && needs_range_check) {
282 length.set_instruction(x->length());
283 length.load_item();
284
285 }
286 if (needs_store_check) {
287 value.load_item();
288 } else {
289 value.load_for_store(x->elt_type());
290 }
291
292 set_no_result(x);
293
294 // the CodeEmitInfo must be duplicated for each different
295 // LIR-instruction because spilling can occur anywhere between two
296 // instructions and so the debug information must be different
297 CodeEmitInfo* range_check_info = state_for(x);
298 CodeEmitInfo* null_check_info = NULL;
299 if (x->needs_null_check()) {
300 null_check_info = new CodeEmitInfo(range_check_info);
301 }
302
303 LIR_Opr ary = array.result();
304 ary = shenandoah_write_barrier(ary, null_check_info, x->needs_null_check());
305 LIR_Opr val = value.result();
306 if (obj_store && UseShenandoahGC) {
307 if (! val->is_register()) {
308 assert(val->is_constant(), "expect constant");
309 } else {
310 val = shenandoah_read_barrier(val, NULL, true);
311 }
312 }
313
314 // emit array address setup early so it schedules better
315 LIR_Address* array_addr = emit_array_address(ary, index.result(), x->elt_type(), obj_store);
316
317 if (GenerateRangeChecks && needs_range_check) {
318 if (use_length) {
319 __ cmp(lir_cond_belowEqual, length.result(), index.result());
320 __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));
321 } else {
322 array_range_check(ary, index.result(), null_check_info, range_check_info);
323 // range_check also does the null check
324 null_check_info = NULL;
325 }
326 }
327
328 if (GenerateArrayStoreCheck && needs_store_check) {
329 LIR_Opr tmp1 = new_register(objectType);
330 LIR_Opr tmp2 = new_register(objectType);
331 LIR_Opr tmp3 = new_register(objectType);
332
333 CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);
334 __ store_check(val, ary, tmp1, tmp2, tmp3, store_check_info, x->profiled_method(), x->profiled_bci());
335 }
336
337 if (obj_store) {
338 // Needs GC write barriers.
339 pre_barrier(LIR_OprFact::address(array_addr), LIR_OprFact::illegalOpr /* pre_val */,
340 true /* do_load */, false /* patch */, NULL);
341 __ move(val, array_addr, null_check_info);
342 // Seems to be a precise
343 post_barrier(LIR_OprFact::address(array_addr), value.result());
344 } else {
345 __ move(val, array_addr, null_check_info);
346 }
347 }
348
349
350 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {
351 assert(x->is_pinned(),"");
352 LIRItem obj(x->obj(), this);
353 obj.load_item();
354
355 set_no_result(x);
356
357 // "lock" stores the address of the monitor stack slot, so this is not an oop
358 LIR_Opr lock = new_register(T_INT);
359 // Need a scratch register for biased locking on x86
360 LIR_Opr scratch = LIR_OprFact::illegalOpr;
361 if (UseBiasedLocking) {
362 scratch = new_register(T_INT);
363 }
364
365 CodeEmitInfo* info_for_exception = NULL;
366 if (x->needs_null_check()) {
367 info_for_exception = state_for(x);
368 }
369 // this CodeEmitInfo must not have the xhandlers because here the
370 // object is already locked (xhandlers expect object to be unlocked)
371 CodeEmitInfo* info = state_for(x, x->state(), true);
372 LIR_Opr obj_opr = obj.result();
373 obj_opr = shenandoah_write_barrier(obj_opr, state_for(x), x->needs_null_check());
374 monitor_enter(obj_opr, lock, syncTempOpr(), scratch,
375 x->monitor_no(), info_for_exception, info);
376 }
377
378
379 void LIRGenerator::do_MonitorExit(MonitorExit* x) {
380 assert(x->is_pinned(),"");
381
382 LIRItem obj(x->obj(), this);
383 obj.dont_load_item();
384
385 LIR_Opr lock = new_register(T_INT);
386 LIR_Opr obj_temp = new_register(T_INT);
387 set_no_result(x);
388 monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no());
389 }
390
391
392 // _ineg, _lneg, _fneg, _dneg
393 void LIRGenerator::do_NegateOp(NegateOp* x) {
394 LIRItem value(x->x(), this);
395 value.set_destroys_register();
396 value.load_item();
397 LIR_Opr reg = rlock(x);
398 __ negate(value.result(), reg);
399
400 set_result(x, round_item(reg));
401 }
402
403
404 // for _fadd, _fmul, _fsub, _fdiv, _frem
405 // _dadd, _dmul, _dsub, _ddiv, _drem
406 void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {
407 LIRItem left(x->x(), this);
408 LIRItem right(x->y(), this);
409 LIRItem* left_arg = &left;
410 LIRItem* right_arg = &right;
411 assert(!left.is_stack() || !right.is_stack(), "can't both be memory operands");
412 bool must_load_both = (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem);
413 if (left.is_register() || x->x()->type()->is_constant() || must_load_both) {
414 left.load_item();
415 } else {
416 left.dont_load_item();
417 }
418
419 // do not load right operand if it is a constant. only 0 and 1 are
420 // loaded because there are special instructions for loading them
421 // without memory access (not needed for SSE2 instructions)
422 bool must_load_right = false;
423 if (right.is_constant()) {
424 LIR_Const* c = right.result()->as_constant_ptr();
425 assert(c != NULL, "invalid constant");
426 assert(c->type() == T_FLOAT || c->type() == T_DOUBLE, "invalid type");
427
428 if (c->type() == T_FLOAT) {
429 must_load_right = UseSSE < 1 && (c->is_one_float() || c->is_zero_float());
430 } else {
431 must_load_right = UseSSE < 2 && (c->is_one_double() || c->is_zero_double());
432 }
433 }
434
435 if (must_load_both) {
436 // frem and drem destroy also right operand, so move it to a new register
437 right.set_destroys_register();
438 right.load_item();
439 } else if (right.is_register() || must_load_right) {
440 right.load_item();
441 } else {
442 right.dont_load_item();
443 }
444 LIR_Opr reg = rlock(x);
445 LIR_Opr tmp = LIR_OprFact::illegalOpr;
446 if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) {
447 tmp = new_register(T_DOUBLE);
448 }
449
450 if ((UseSSE >= 1 && x->op() == Bytecodes::_frem) || (UseSSE >= 2 && x->op() == Bytecodes::_drem)) {
451 // special handling for frem and drem: no SSE instruction, so must use FPU with temporary fpu stack slots
452 LIR_Opr fpu0, fpu1;
453 if (x->op() == Bytecodes::_frem) {
454 fpu0 = LIR_OprFact::single_fpu(0);
455 fpu1 = LIR_OprFact::single_fpu(1);
456 } else {
457 fpu0 = LIR_OprFact::double_fpu(0);
458 fpu1 = LIR_OprFact::double_fpu(1);
459 }
460 __ move(right.result(), fpu1); // order of left and right operand is important!
461 __ move(left.result(), fpu0);
462 __ rem (fpu0, fpu1, fpu0);
463 __ move(fpu0, reg);
464
465 } else {
466 arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp);
467 }
468
469 set_result(x, round_item(reg));
470 }
471
472
473 // for _ladd, _lmul, _lsub, _ldiv, _lrem
474 void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
475 if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem ) {
476 // long division is implemented as a direct call into the runtime
477 LIRItem left(x->x(), this);
478 LIRItem right(x->y(), this);
479
480 // the check for division by zero destroys the right operand
481 right.set_destroys_register();
482
483 BasicTypeList signature(2);
484 signature.append(T_LONG);
485 signature.append(T_LONG);
486 CallingConvention* cc = frame_map()->c_calling_convention(&signature);
487
488 // check for division by zero (destroys registers of right operand!)
489 CodeEmitInfo* info = state_for(x);
490
491 const LIR_Opr result_reg = result_register_for(x->type());
492 left.load_item_force(cc->at(1));
493 right.load_item();
494
495 __ move(right.result(), cc->at(0));
496
497 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));
498 __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));
499
500 address entry;
501 switch (x->op()) {
502 case Bytecodes::_lrem:
503 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem);
504 break; // check if dividend is 0 is done elsewhere
505 case Bytecodes::_ldiv:
506 entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv);
507 break; // check if dividend is 0 is done elsewhere
508 case Bytecodes::_lmul:
509 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul);
510 break;
511 default:
512 ShouldNotReachHere();
513 }
514
515 LIR_Opr result = rlock_result(x);
516 __ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args());
517 __ move(result_reg, result);
518 } else if (x->op() == Bytecodes::_lmul) {
519 // missing test if instr is commutative and if we should swap
520 LIRItem left(x->x(), this);
521 LIRItem right(x->y(), this);
522
523 // right register is destroyed by the long mul, so it must be
524 // copied to a new register.
525 right.set_destroys_register();
526
527 left.load_item();
528 right.load_item();
529
530 LIR_Opr reg = FrameMap::long0_opr;
531 arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
532 LIR_Opr result = rlock_result(x);
533 __ move(reg, result);
534 } else {
535 // missing test if instr is commutative and if we should swap
536 LIRItem left(x->x(), this);
537 LIRItem right(x->y(), this);
538
539 left.load_item();
540 // don't load constants to save register
541 right.load_nonconstant();
542 rlock_result(x);
543 arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);
544 }
545 }
546
547
548
549 // for: _iadd, _imul, _isub, _idiv, _irem
550 void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {
551 if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {
552 // The requirements for division and modulo
553 // input : rax,: dividend min_int
554 // reg: divisor (may not be rax,/rdx) -1
555 //
556 // output: rax,: quotient (= rax, idiv reg) min_int
557 // rdx: remainder (= rax, irem reg) 0
558
559 // rax, and rdx will be destroyed
560
561 // Note: does this invalidate the spec ???
562 LIRItem right(x->y(), this);
563 LIRItem left(x->x() , this); // visit left second, so that the is_register test is valid
564
565 // call state_for before load_item_force because state_for may
566 // force the evaluation of other instructions that are needed for
567 // correct debug info. Otherwise the live range of the fix
568 // register might be too long.
569 CodeEmitInfo* info = state_for(x);
570
571 left.load_item_force(divInOpr());
572
573 right.load_item();
574
575 LIR_Opr result = rlock_result(x);
576 LIR_Opr result_reg;
577 if (x->op() == Bytecodes::_idiv) {
578 result_reg = divOutOpr();
579 } else {
580 result_reg = remOutOpr();
581 }
582
583 if (!ImplicitDiv0Checks) {
584 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::intConst(0));
585 __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info));
586 }
587 LIR_Opr tmp = FrameMap::rdx_opr; // idiv and irem use rdx in their implementation
588 if (x->op() == Bytecodes::_irem) {
589 __ irem(left.result(), right.result(), result_reg, tmp, info);
590 } else if (x->op() == Bytecodes::_idiv) {
591 __ idiv(left.result(), right.result(), result_reg, tmp, info);
592 } else {
593 ShouldNotReachHere();
594 }
595
596 __ move(result_reg, result);
597 } else {
598 // missing test if instr is commutative and if we should swap
599 LIRItem left(x->x(), this);
600 LIRItem right(x->y(), this);
601 LIRItem* left_arg = &left;
602 LIRItem* right_arg = &right;
603 if (x->is_commutative() && left.is_stack() && right.is_register()) {
604 // swap them if left is real stack (or cached) and right is real register(not cached)
605 left_arg = &right;
606 right_arg = &left;
607 }
608
609 left_arg->load_item();
610
611 // do not need to load right, as we can handle stack and constants
612 if (x->op() == Bytecodes::_imul ) {
613 // check if we can use shift instead
614 bool use_constant = false;
615 bool use_tmp = false;
616 if (right_arg->is_constant()) {
617 int iconst = right_arg->get_jint_constant();
618 if (iconst > 0) {
619 if (is_power_of_2(iconst)) {
620 use_constant = true;
621 } else if (is_power_of_2(iconst - 1) || is_power_of_2(iconst + 1)) {
622 use_constant = true;
623 use_tmp = true;
624 }
625 }
626 }
627 if (use_constant) {
628 right_arg->dont_load_item();
629 } else {
630 right_arg->load_item();
631 }
632 LIR_Opr tmp = LIR_OprFact::illegalOpr;
633 if (use_tmp) {
634 tmp = new_register(T_INT);
635 }
636 rlock_result(x);
637
638 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
639 } else {
640 right_arg->dont_load_item();
641 rlock_result(x);
642 LIR_Opr tmp = LIR_OprFact::illegalOpr;
643 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
644 }
645 }
646 }
647
648
649 void LIRGenerator::do_ArithmeticOp(ArithmeticOp* x) {
650 // when an operand with use count 1 is the left operand, then it is
651 // likely that no move for 2-operand-LIR-form is necessary
652 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
653 x->swap_operands();
654 }
655
656 ValueTag tag = x->type()->tag();
657 assert(x->x()->type()->tag() == tag && x->y()->type()->tag() == tag, "wrong parameters");
658 switch (tag) {
659 case floatTag:
660 case doubleTag: do_ArithmeticOp_FPU(x); return;
661 case longTag: do_ArithmeticOp_Long(x); return;
662 case intTag: do_ArithmeticOp_Int(x); return;
663 }
664 ShouldNotReachHere();
665 }
666
667
668 // _ishl, _lshl, _ishr, _lshr, _iushr, _lushr
669 void LIRGenerator::do_ShiftOp(ShiftOp* x) {
670 // count must always be in rcx
671 LIRItem value(x->x(), this);
672 LIRItem count(x->y(), this);
673
674 ValueTag elemType = x->type()->tag();
675 bool must_load_count = !count.is_constant() || elemType == longTag;
676 if (must_load_count) {
677 // count for long must be in register
678 count.load_item_force(shiftCountOpr());
679 } else {
680 count.dont_load_item();
681 }
682 value.load_item();
683 LIR_Opr reg = rlock_result(x);
684
685 shift_op(x->op(), reg, value.result(), count.result(), LIR_OprFact::illegalOpr);
686 }
687
688
689 // _iand, _land, _ior, _lor, _ixor, _lxor
690 void LIRGenerator::do_LogicOp(LogicOp* x) {
691 // when an operand with use count 1 is the left operand, then it is
692 // likely that no move for 2-operand-LIR-form is necessary
693 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
694 x->swap_operands();
695 }
696
697 LIRItem left(x->x(), this);
698 LIRItem right(x->y(), this);
699
700 left.load_item();
701 right.load_nonconstant();
702 LIR_Opr reg = rlock_result(x);
703
704 logic_op(x->op(), reg, left.result(), right.result());
705 }
706
707
708
709 // _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg
710 void LIRGenerator::do_CompareOp(CompareOp* x) {
711 LIRItem left(x->x(), this);
712 LIRItem right(x->y(), this);
713 ValueTag tag = x->x()->type()->tag();
714 if (tag == longTag) {
715 left.set_destroys_register();
716 }
717 left.load_item();
718 right.load_item();
719 LIR_Opr reg = rlock_result(x);
720
721 if (x->x()->type()->is_float_kind()) {
722 Bytecodes::Code code = x->op();
723 __ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl));
724 } else if (x->x()->type()->tag() == longTag) {
725 __ lcmp2int(left.result(), right.result(), reg);
726 } else {
727 Unimplemented();
728 }
729 }
730
731
732 void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) {
733 assert(x->number_of_arguments() == 4, "wrong type");
734 LIRItem obj (x->argument_at(0), this); // object
735 LIRItem offset(x->argument_at(1), this); // offset of field
736 LIRItem cmp (x->argument_at(2), this); // value to compare with field
737 LIRItem val (x->argument_at(3), this); // replace field with val if matches cmp
738
739 assert(obj.type()->tag() == objectTag, "invalid type");
740
741 // In 64bit the type can be long, sparc doesn't have this assert
742 // assert(offset.type()->tag() == intTag, "invalid type");
743
744 assert(cmp.type()->tag() == type->tag(), "invalid type");
745 assert(val.type()->tag() == type->tag(), "invalid type");
746
747 // get address of field
748 obj.load_item();
749 offset.load_nonconstant();
750
751 if (type == objectType) {
752 cmp.load_item_force(FrameMap::rax_oop_opr);
753 val.load_item();
754 } else if (type == intType) {
755 cmp.load_item_force(FrameMap::rax_opr);
756 val.load_item();
757 } else if (type == longType) {
758 cmp.load_item_force(FrameMap::long0_opr);
759 val.load_item_force(FrameMap::long1_opr);
760 } else {
761 ShouldNotReachHere();
762 }
763
764 LIR_Opr addr = new_pointer_register();
765 LIR_Address* a;
766
767 LIR_Opr obj_op = obj.result();
768 obj_op = shenandoah_write_barrier(obj_op, NULL, false);
769
770 if(offset.result()->is_constant()) {
771 #ifdef _LP64
772 jlong c = offset.result()->as_jlong();
773 if ((jlong)((jint)c) == c) {
774 a = new LIR_Address(obj_op,
775 (jint)c,
776 as_BasicType(type));
777 } else {
778 LIR_Opr tmp = new_register(T_LONG);
779 __ move(offset.result(), tmp);
780 a = new LIR_Address(obj_op,
781 tmp,
782 as_BasicType(type));
783 }
784 #else
785 a = new LIR_Address(obj_op,
786 offset.result()->as_jint(),
787 as_BasicType(type));
788 #endif
789 } else {
790 a = new LIR_Address(obj_op,
791 offset.result(),
792 LIR_Address::times_1,
793 0,
794 as_BasicType(type));
795 }
796 __ leal(LIR_OprFact::address(a), addr);
797
798 if (type == objectType) { // Write-barrier needed for Object fields.
799 // Do the pre-write barrier, if any.
800 pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
801 true /* do_load */, false /* patch */, NULL);
802 }
803
804 LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience
805
806 LIR_Opr val_op = val.result();
807
808 if (type == objectType) {
809 val_op = shenandoah_read_barrier(val_op, NULL, true);
810 __ cas_obj(addr, cmp.result(), val_op, new_register(T_OBJECT), new_register(T_OBJECT));
811 }
812 else if (type == intType)
813 __ cas_int(addr, cmp.result(), val_op, ill, ill);
814 else if (type == longType)
815 __ cas_long(addr, cmp.result(), val_op, ill, ill);
816 else {
817 ShouldNotReachHere();
818 }
819
820 // generate conditional move of boolean result
821 LIR_Opr result = rlock_result(x);
822 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
823 result, as_BasicType(type));
824 if (type == objectType) { // Write-barrier needed for Object fields.
825 // Seems to be precise
826 post_barrier(addr, val_op);
827 }
828 }
829
830
831 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
832 assert(x->number_of_arguments() == 1 || (x->number_of_arguments() == 2 && x->id() == vmIntrinsics::_dpow), "wrong type");
833 LIRItem value(x->argument_at(0), this);
834
835 bool use_fpu = false;
836 if (UseSSE >= 2) {
837 switch(x->id()) {
838 case vmIntrinsics::_dsin:
839 case vmIntrinsics::_dcos:
840 case vmIntrinsics::_dtan:
841 case vmIntrinsics::_dlog:
842 case vmIntrinsics::_dlog10:
843 case vmIntrinsics::_dexp:
844 case vmIntrinsics::_dpow:
845 use_fpu = true;
846 }
847 } else {
848 value.set_destroys_register();
849 }
850
851 value.load_item();
852
853 LIR_Opr calc_input = value.result();
854 LIR_Opr calc_input2 = NULL;
855 if (x->id() == vmIntrinsics::_dpow) {
856 LIRItem extra_arg(x->argument_at(1), this);
857 if (UseSSE < 2) {
858 extra_arg.set_destroys_register();
859 }
860 extra_arg.load_item();
861 calc_input2 = extra_arg.result();
862 }
863 LIR_Opr calc_result = rlock_result(x);
864
865 // sin, cos, pow and exp need two free fpu stack slots, so register
866 // two temporary operands
867 LIR_Opr tmp1 = FrameMap::caller_save_fpu_reg_at(0);
868 LIR_Opr tmp2 = FrameMap::caller_save_fpu_reg_at(1);
869
870 if (use_fpu) {
871 LIR_Opr tmp = FrameMap::fpu0_double_opr;
872 int tmp_start = 1;
873 if (calc_input2 != NULL) {
874 __ move(calc_input2, tmp);
875 tmp_start = 2;
876 calc_input2 = tmp;
877 }
878 __ move(calc_input, tmp);
879
880 calc_input = tmp;
881 calc_result = tmp;
882
883 tmp1 = FrameMap::caller_save_fpu_reg_at(tmp_start);
884 tmp2 = FrameMap::caller_save_fpu_reg_at(tmp_start + 1);
885 }
886
887 switch(x->id()) {
888 case vmIntrinsics::_dabs: __ abs (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
889 case vmIntrinsics::_dsqrt: __ sqrt (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
890 case vmIntrinsics::_dsin: __ sin (calc_input, calc_result, tmp1, tmp2); break;
891 case vmIntrinsics::_dcos: __ cos (calc_input, calc_result, tmp1, tmp2); break;
892 case vmIntrinsics::_dtan: __ tan (calc_input, calc_result, tmp1, tmp2); break;
893 case vmIntrinsics::_dlog: __ log (calc_input, calc_result, tmp1); break;
894 case vmIntrinsics::_dlog10: __ log10(calc_input, calc_result, tmp1); break;
895 case vmIntrinsics::_dexp: __ exp (calc_input, calc_result, tmp1, tmp2, FrameMap::rax_opr, FrameMap::rcx_opr, FrameMap::rdx_opr); break;
896 case vmIntrinsics::_dpow: __ pow (calc_input, calc_input2, calc_result, tmp1, tmp2, FrameMap::rax_opr, FrameMap::rcx_opr, FrameMap::rdx_opr); break;
897 default: ShouldNotReachHere();
898 }
899
900 if (use_fpu) {
901 __ move(calc_result, x->operand());
902 }
903 }
904
905
906 void LIRGenerator::do_ArrayCopy(Intrinsic* x) {
907 assert(x->number_of_arguments() == 5, "wrong type");
908
909 // Make all state_for calls early since they can emit code
910 CodeEmitInfo* info = state_for(x, x->state());
911
912 LIRItem src(x->argument_at(0), this);
913 LIRItem src_pos(x->argument_at(1), this);
914 LIRItem dst(x->argument_at(2), this);
915 LIRItem dst_pos(x->argument_at(3), this);
916 LIRItem length(x->argument_at(4), this);
917
918 LIR_Opr dst_op = dst.result();
919 dst_op = shenandoah_write_barrier(dst_op, info, x->arg_needs_null_check(2));
920 LIR_Opr src_op = src.result();
921 src_op = shenandoah_read_barrier(src_op, info, x->arg_needs_null_check(0));
922
923 // operands for arraycopy must use fixed registers, otherwise
924 // LinearScan will fail allocation (because arraycopy always needs a
925 // call)
926
927 #ifndef _LP64
928 src_op = force_opr_to(src_op, FrameMap::rcx_oop_opr);
929 src_pos.load_item_force (FrameMap::rdx_opr);
930 dst_op = force_opr_to(dst_op, FrameMap::rax_oop_opr);
931 dst_pos.load_item_force (FrameMap::rbx_opr);
932 length.load_item_force (FrameMap::rdi_opr);
933 LIR_Opr tmp = (FrameMap::rsi_opr);
934 #else
935
936 // The java calling convention will give us enough registers
937 // so that on the stub side the args will be perfect already.
938 // On the other slow/special case side we call C and the arg
939 // positions are not similar enough to pick one as the best.
940 // Also because the java calling convention is a "shifted" version
941 // of the C convention we can process the java args trivially into C
942 // args without worry of overwriting during the xfer
943
944 src_op = force_opr_to(src_op, FrameMap::as_oop_opr(j_rarg0));
945 src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
946 dst_op = force_opr_to(dst_op, FrameMap::as_oop_opr(j_rarg2));
947 dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
948 length.load_item_force (FrameMap::as_opr(j_rarg4));
949
950 LIR_Opr tmp = FrameMap::as_opr(j_rarg5);
951 #endif // LP64
952
953 set_no_result(x);
954
955 int flags;
956 ciArrayKlass* expected_type;
957 arraycopy_helper(x, &flags, &expected_type);
958
959 __ arraycopy(src_op, src_pos.result(), dst_op, dst_pos.result(), length.result(), tmp, expected_type, flags, info); // does add_safepoint
960 }
961
962 void LIRGenerator::do_update_CRC32(Intrinsic* x) {
963 assert(UseCRC32Intrinsics, "need AVX and LCMUL instructions support");
964 // Make all state_for calls early since they can emit code
965 LIR_Opr result = rlock_result(x);
966 int flags = 0;
967 switch (x->id()) {
968 case vmIntrinsics::_updateCRC32: {
969 LIRItem crc(x->argument_at(0), this);
970 LIRItem val(x->argument_at(1), this);
971 // val is destroyed by update_crc32
972 val.set_destroys_register();
973 crc.load_item();
974 val.load_item();
975 __ update_crc32(crc.result(), val.result(), result);
976 break;
977 }
978 case vmIntrinsics::_updateBytesCRC32:
979 case vmIntrinsics::_updateByteBufferCRC32: {
980 bool is_updateBytes = (x->id() == vmIntrinsics::_updateBytesCRC32);
981
982 LIRItem crc(x->argument_at(0), this);
983 LIRItem buf(x->argument_at(1), this);
984 LIRItem off(x->argument_at(2), this);
985 LIRItem len(x->argument_at(3), this);
986 buf.load_item();
987 off.load_nonconstant();
988
989 LIR_Opr index = off.result();
990 int offset = is_updateBytes ? arrayOopDesc::base_offset_in_bytes(T_BYTE) : 0;
991 if(off.result()->is_constant()) {
992 index = LIR_OprFact::illegalOpr;
993 offset += off.result()->as_jint();
994 }
995 LIR_Opr base_op = buf.result();
996
997 #ifndef _LP64
998 if (!is_updateBytes) { // long b raw address
999 base_op = new_register(T_INT);
1000 __ convert(Bytecodes::_l2i, buf.result(), base_op);
1001 }
1002 #else
1003 if (index->is_valid()) {
1004 LIR_Opr tmp = new_register(T_LONG);
1005 __ convert(Bytecodes::_i2l, index, tmp);
1006 index = tmp;
1007 }
1008 #endif
1009
1010 if (is_updateBytes) {
1011 base_op = shenandoah_read_barrier(base_op, NULL, false);
1012 }
1013
1014 LIR_Address* a = new LIR_Address(base_op,
1015 index,
1016 LIR_Address::times_1,
1017 offset,
1018 T_BYTE);
1019 BasicTypeList signature(3);
1020 signature.append(T_INT);
1021 signature.append(T_ADDRESS);
1022 signature.append(T_INT);
1023 CallingConvention* cc = frame_map()->c_calling_convention(&signature);
1024 const LIR_Opr result_reg = result_register_for(x->type());
1025
1026 LIR_Opr addr = new_pointer_register();
1027 __ leal(LIR_OprFact::address(a), addr);
1028
1029 crc.load_item_force(cc->at(0));
1030 __ move(addr, cc->at(1));
1031 len.load_item_force(cc->at(2));
1032
1033 __ call_runtime_leaf(StubRoutines::updateBytesCRC32(), getThreadTemp(), result_reg, cc->args());
1034 __ move(result_reg, result);
1035
1036 break;
1037 }
1038 default: {
1039 ShouldNotReachHere();
1040 }
1041 }
1042 }
1043
1044 // _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
1045 // _i2b, _i2c, _i2s
1046 LIR_Opr fixed_register_for(BasicType type) {
1047 switch (type) {
1048 case T_FLOAT: return FrameMap::fpu0_float_opr;
1049 case T_DOUBLE: return FrameMap::fpu0_double_opr;
1050 case T_INT: return FrameMap::rax_opr;
1051 case T_LONG: return FrameMap::long0_opr;
1052 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
1053 }
1054 }
1055
1056 void LIRGenerator::do_Convert(Convert* x) {
1057 // flags that vary for the different operations and different SSE-settings
1058 bool fixed_input, fixed_result, round_result, needs_stub;
1059
1060 switch (x->op()) {
1061 case Bytecodes::_i2l: // fall through
1062 case Bytecodes::_l2i: // fall through
1063 case Bytecodes::_i2b: // fall through
1064 case Bytecodes::_i2c: // fall through
1065 case Bytecodes::_i2s: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
1066
1067 case Bytecodes::_f2d: fixed_input = UseSSE == 1; fixed_result = false; round_result = false; needs_stub = false; break;
1068 case Bytecodes::_d2f: fixed_input = false; fixed_result = UseSSE == 1; round_result = UseSSE < 1; needs_stub = false; break;
1069 case Bytecodes::_i2f: fixed_input = false; fixed_result = false; round_result = UseSSE < 1; needs_stub = false; break;
1070 case Bytecodes::_i2d: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
1071 case Bytecodes::_f2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
1072 case Bytecodes::_d2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
1073 case Bytecodes::_l2f: fixed_input = false; fixed_result = UseSSE >= 1; round_result = UseSSE < 1; needs_stub = false; break;
1074 case Bytecodes::_l2d: fixed_input = false; fixed_result = UseSSE >= 2; round_result = UseSSE < 2; needs_stub = false; break;
1075 case Bytecodes::_f2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
1076 case Bytecodes::_d2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
1077 default: ShouldNotReachHere();
1078 }
1079
1080 LIRItem value(x->value(), this);
1081 value.load_item();
1082 LIR_Opr input = value.result();
1083 LIR_Opr result = rlock(x);
1084
1085 // arguments of lir_convert
1086 LIR_Opr conv_input = input;
1087 LIR_Opr conv_result = result;
1088 ConversionStub* stub = NULL;
1089
1090 if (fixed_input) {
1091 conv_input = fixed_register_for(input->type());
1092 __ move(input, conv_input);
1093 }
1094
1095 assert(fixed_result == false || round_result == false, "cannot set both");
1096 if (fixed_result) {
1097 conv_result = fixed_register_for(result->type());
1098 } else if (round_result) {
1099 result = new_register(result->type());
1100 set_vreg_flag(result, must_start_in_memory);
1101 }
1102
1103 if (needs_stub) {
1104 stub = new ConversionStub(x->op(), conv_input, conv_result);
1105 }
1106
1107 __ convert(x->op(), conv_input, conv_result, stub);
1108
1109 if (result != conv_result) {
1110 __ move(conv_result, result);
1111 }
1112
1113 assert(result->is_virtual(), "result must be virtual register");
1114 set_result(x, result);
1115 }
1116
1117
1118 void LIRGenerator::do_NewInstance(NewInstance* x) {
1119 print_if_not_loaded(x);
1120
1121 CodeEmitInfo* info = state_for(x, x->state());
1122 LIR_Opr reg = result_register_for(x->type());
1123 new_instance(reg, x->klass(), x->is_unresolved(),
1124 FrameMap::rcx_oop_opr,
1125 FrameMap::rdi_oop_opr,
1126 FrameMap::rsi_oop_opr,
1127 LIR_OprFact::illegalOpr,
1128 FrameMap::rdx_metadata_opr, info);
1129 LIR_Opr result = rlock_result(x);
1130 __ move(reg, result);
1131 }
1132
1133
1134 void LIRGenerator::do_NewTypeArray(NewTypeArray* x) {
1135 CodeEmitInfo* info = state_for(x, x->state());
1136
1137 LIRItem length(x->length(), this);
1138 length.load_item_force(FrameMap::rbx_opr);
1139
1140 LIR_Opr reg = result_register_for(x->type());
1141 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1142 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1143 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1144 LIR_Opr tmp4 = reg;
1145 LIR_Opr klass_reg = FrameMap::rdx_metadata_opr;
1146 LIR_Opr len = length.result();
1147 BasicType elem_type = x->elt_type();
1148
1149 __ metadata2reg(ciTypeArrayKlass::make(elem_type)->constant_encoding(), klass_reg);
1150
1151 CodeStub* slow_path = new NewTypeArrayStub(klass_reg, len, reg, info);
1152 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, elem_type, klass_reg, slow_path);
1153
1154 LIR_Opr result = rlock_result(x);
1155 __ move(reg, result);
1156 }
1157
1158
1159 void LIRGenerator::do_NewObjectArray(NewObjectArray* x) {
1160 LIRItem length(x->length(), this);
1161 // in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction
1162 // and therefore provide the state before the parameters have been consumed
1163 CodeEmitInfo* patching_info = NULL;
1164 if (!x->klass()->is_loaded() || PatchALot) {
1165 patching_info = state_for(x, x->state_before());
1166 }
1167
1168 CodeEmitInfo* info = state_for(x, x->state());
1169
1170 const LIR_Opr reg = result_register_for(x->type());
1171 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1172 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1173 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1174 LIR_Opr tmp4 = reg;
1175 LIR_Opr klass_reg = FrameMap::rdx_metadata_opr;
1176
1177 length.load_item_force(FrameMap::rbx_opr);
1178 LIR_Opr len = length.result();
1179
1180 CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info);
1181 ciKlass* obj = (ciKlass*) ciObjArrayKlass::make(x->klass());
1182 if (obj == ciEnv::unloaded_ciobjarrayklass()) {
1183 BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
1184 }
1185 klass2reg_with_patching(klass_reg, obj, patching_info);
1186 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, T_OBJECT, klass_reg, slow_path);
1187
1188 LIR_Opr result = rlock_result(x);
1189 __ move(reg, result);
1190 }
1191
1192
1193 void LIRGenerator::do_NewMultiArray(NewMultiArray* x) {
1194 Values* dims = x->dims();
1195 int i = dims->length();
1196 LIRItemList* items = new LIRItemList(dims->length(), NULL);
1197 while (i-- > 0) {
1198 LIRItem* size = new LIRItem(dims->at(i), this);
1199 items->at_put(i, size);
1200 }
1201
1202 // Evaluate state_for early since it may emit code.
1203 CodeEmitInfo* patching_info = NULL;
1204 if (!x->klass()->is_loaded() || PatchALot) {
1205 patching_info = state_for(x, x->state_before());
1206
1207 // Cannot re-use same xhandlers for multiple CodeEmitInfos, so
1208 // clone all handlers (NOTE: Usually this is handled transparently
1209 // by the CodeEmitInfo cloning logic in CodeStub constructors but
1210 // is done explicitly here because a stub isn't being used).
1211 x->set_exception_handlers(new XHandlers(x->exception_handlers()));
1212 }
1213 CodeEmitInfo* info = state_for(x, x->state());
1214
1215 i = dims->length();
1216 while (i-- > 0) {
1217 LIRItem* size = items->at(i);
1218 size->load_nonconstant();
1219
1220 store_stack_parameter(size->result(), in_ByteSize(i*4));
1221 }
1222
1223 LIR_Opr klass_reg = FrameMap::rax_metadata_opr;
1224 klass2reg_with_patching(klass_reg, x->klass(), patching_info);
1225
1226 LIR_Opr rank = FrameMap::rbx_opr;
1227 __ move(LIR_OprFact::intConst(x->rank()), rank);
1228 LIR_Opr varargs = FrameMap::rcx_opr;
1229 __ move(FrameMap::rsp_opr, varargs);
1230 LIR_OprList* args = new LIR_OprList(3);
1231 args->append(klass_reg);
1232 args->append(rank);
1233 args->append(varargs);
1234 LIR_Opr reg = result_register_for(x->type());
1235 __ call_runtime(Runtime1::entry_for(Runtime1::new_multi_array_id),
1236 LIR_OprFact::illegalOpr,
1237 reg, args, info);
1238
1239 LIR_Opr result = rlock_result(x);
1240 __ move(reg, result);
1241 }
1242
1243
1244 void LIRGenerator::do_BlockBegin(BlockBegin* x) {
1245 // nothing to do for now
1246 }
1247
1248
1249 void LIRGenerator::do_CheckCast(CheckCast* x) {
1250 LIRItem obj(x->obj(), this);
1251
1252 CodeEmitInfo* patching_info = NULL;
1253 if (!x->klass()->is_loaded() || (PatchALot && !x->is_incompatible_class_change_check())) {
1254 // must do this before locking the destination register as an oop register,
1255 // and before the obj is loaded (the latter is for deoptimization)
1256 patching_info = state_for(x, x->state_before());
1257 }
1258 obj.load_item();
1259
1260 // info for exceptions
1261 CodeEmitInfo* info_for_exception = state_for(x);
1262
1263 CodeStub* stub;
1264 if (x->is_incompatible_class_change_check()) {
1265 assert(patching_info == NULL, "can't patch this");
1266 stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception);
1267 } else {
1268 stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception);
1269 }
1270 LIR_Opr reg = rlock_result(x);
1271 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1272 if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
1273 tmp3 = new_register(objectType);
1274 }
1275 __ checkcast(reg, obj.result(), x->klass(),
1276 new_register(objectType), new_register(objectType), tmp3,
1277 x->direct_compare(), info_for_exception, patching_info, stub,
1278 x->profiled_method(), x->profiled_bci());
1279 }
1280
1281
1282 void LIRGenerator::do_InstanceOf(InstanceOf* x) {
1283 LIRItem obj(x->obj(), this);
1284
1285 // result and test object may not be in same register
1286 LIR_Opr reg = rlock_result(x);
1287 CodeEmitInfo* patching_info = NULL;
1288 if ((!x->klass()->is_loaded() || PatchALot)) {
1289 // must do this before locking the destination register as an oop register
1290 patching_info = state_for(x, x->state_before());
1291 }
1292 obj.load_item();
1293 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1294 if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
1295 tmp3 = new_register(objectType);
1296 }
1297 __ instanceof(reg, obj.result(), x->klass(),
1298 new_register(objectType), new_register(objectType), tmp3,
1299 x->direct_compare(), patching_info, x->profiled_method(), x->profiled_bci());
1300 }
1301
1302
1303 void LIRGenerator::do_If(If* x) {
1304 assert(x->number_of_sux() == 2, "inconsistency");
1305 ValueTag tag = x->x()->type()->tag();
1306 bool is_safepoint = x->is_safepoint();
1307
1308 If::Condition cond = x->cond();
1309
1310 LIRItem xitem(x->x(), this);
1311 LIRItem yitem(x->y(), this);
1312 LIRItem* xin = &xitem;
1313 LIRItem* yin = &yitem;
1314
1315 if (tag == longTag) {
1316 // for longs, only conditions "eql", "neq", "lss", "geq" are valid;
1317 // mirror for other conditions
1318 if (cond == If::gtr || cond == If::leq) {
1319 cond = Instruction::mirror(cond);
1320 xin = &yitem;
1321 yin = &xitem;
1322 }
1323 xin->set_destroys_register();
1324 }
1325 xin->load_item();
1326 if (tag == longTag && yin->is_constant() && yin->get_jlong_constant() == 0 && (cond == If::eql || cond == If::neq)) {
1327 // inline long zero
1328 yin->dont_load_item();
1329 } else if (tag == longTag || tag == floatTag || tag == doubleTag) {
1330 // longs cannot handle constants at right side
1331 yin->load_item();
1332 } else {
1333 yin->dont_load_item();
1334 }
1335
1336 // add safepoint before generating condition code so it can be recomputed
1337 if (x->is_safepoint()) {
1338 // increment backedge counter if needed
1339 increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci());
1340 __ safepoint(LIR_OprFact::illegalOpr, state_for(x, x->state_before()));
1341 }
1342 set_no_result(x);
1343
1344 LIR_Opr left = xin->result();
1345 LIR_Opr right = yin->result();
1346 if (tag == objectTag && UseShenandoahGC && x->y()->type() != objectNull) { // Don't need to resolve for ifnull.
1347 left = shenandoah_write_barrier(left, NULL, true);
1348 right = shenandoah_read_barrier(right, NULL, true);
1349 }
1350 __ cmp(lir_cond(cond), left, right);
1351 // Generate branch profiling. Profiling code doesn't kill flags.
1352 profile_branch(x, cond);
1353 move_to_phi(x->state());
1354 if (x->x()->type()->is_float_kind()) {
1355 __ branch(lir_cond(cond), right->type(), x->tsux(), x->usux());
1356 } else {
1357 __ branch(lir_cond(cond), right->type(), x->tsux());
1358 }
1359 assert(x->default_sux() == x->fsux(), "wrong destination above");
1360 __ jump(x->default_sux());
1361 }
1362
1363
1364 LIR_Opr LIRGenerator::getThreadPointer() {
1365 #ifdef _LP64
1366 return FrameMap::as_pointer_opr(r15_thread);
1367 #else
1368 LIR_Opr result = new_register(T_INT);
1369 __ get_thread(result);
1370 return result;
1371 #endif //
1372 }
1373
1374 void LIRGenerator::trace_block_entry(BlockBegin* block) {
1375 store_stack_parameter(LIR_OprFact::intConst(block->block_id()), in_ByteSize(0));
1376 LIR_OprList* args = new LIR_OprList();
1377 address func = CAST_FROM_FN_PTR(address, Runtime1::trace_block_entry);
1378 __ call_runtime_leaf(func, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, args);
1379 }
1380
1381
1382 void LIRGenerator::volatile_field_store(LIR_Opr value, LIR_Address* address,
1383 CodeEmitInfo* info) {
1384 if (address->type() == T_LONG) {
1385 address = new LIR_Address(address->base(),
1386 address->index(), address->scale(),
1387 address->disp(), T_DOUBLE);
1388 // Transfer the value atomically by using FP moves. This means
1389 // the value has to be moved between CPU and FPU registers. It
1390 // always has to be moved through spill slot since there's no
1391 // quick way to pack the value into an SSE register.
1392 LIR_Opr temp_double = new_register(T_DOUBLE);
1393 LIR_Opr spill = new_register(T_LONG);
1394 set_vreg_flag(spill, must_start_in_memory);
1395 __ move(value, spill);
1396 __ volatile_move(spill, temp_double, T_LONG);
1397 __ volatile_move(temp_double, LIR_OprFact::address(address), T_LONG, info);
1398 } else {
1399 __ store(value, address, info);
1400 }
1401 }
1402
1403
1404
1405 void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
1406 CodeEmitInfo* info) {
1407 if (address->type() == T_LONG) {
1408 address = new LIR_Address(address->base(),
1409 address->index(), address->scale(),
1410 address->disp(), T_DOUBLE);
1411 // Transfer the value atomically by using FP moves. This means
1412 // the value has to be moved between CPU and FPU registers. In
1413 // SSE0 and SSE1 mode it has to be moved through spill slot but in
1414 // SSE2+ mode it can be moved directly.
1415 LIR_Opr temp_double = new_register(T_DOUBLE);
1416 __ volatile_move(LIR_OprFact::address(address), temp_double, T_LONG, info);
1417 __ volatile_move(temp_double, result, T_LONG);
1418 if (UseSSE < 2) {
1419 // no spill slot needed in SSE2 mode because xmm->cpu register move is possible
1420 set_vreg_flag(result, must_start_in_memory);
1421 }
1422 } else {
1423 __ load(address, result, info);
1424 }
1425 }
1426
1427 void LIRGenerator::get_Object_unsafe(LIR_Opr dst, LIR_Opr src, LIR_Opr offset,
1428 BasicType type, bool is_volatile) {
1429 src = shenandoah_read_barrier(src, NULL, false);
1430 if (is_volatile && type == T_LONG) {
1431 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1432 LIR_Opr tmp = new_register(T_DOUBLE);
1433 __ load(addr, tmp);
1434 LIR_Opr spill = new_register(T_LONG);
1435 set_vreg_flag(spill, must_start_in_memory);
1436 __ move(tmp, spill);
1437 __ move(spill, dst);
1438 } else {
1439 LIR_Address* addr = new LIR_Address(src, offset, type);
1440 __ load(addr, dst);
1441 }
1442 }
1443
1444
1445 void LIRGenerator::put_Object_unsafe(LIR_Opr src, LIR_Opr offset, LIR_Opr data,
1446 BasicType type, bool is_volatile) {
1447 src = shenandoah_write_barrier(src, NULL, false);
1448 if (is_volatile && type == T_LONG) {
1449 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1450 LIR_Opr tmp = new_register(T_DOUBLE);
1451 LIR_Opr spill = new_register(T_DOUBLE);
1452 set_vreg_flag(spill, must_start_in_memory);
1453 __ move(data, spill);
1454 __ move(spill, tmp);
1455 __ move(tmp, addr);
1456 } else {
1457 LIR_Address* addr = new LIR_Address(src, offset, type);
1458 bool is_obj = (type == T_ARRAY || type == T_OBJECT);
1459 if (is_obj) {
1460 // Do the pre-write barrier, if any.
1461 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1462 true /* do_load */, false /* patch */, NULL);
1463 data = shenandoah_read_barrier(data, NULL, true);
1464 __ move(data, addr);
1465 assert(src->is_register(), "must be register");
1466 // Seems to be a precise address
1467 post_barrier(LIR_OprFact::address(addr), data);
1468 } else {
1469 __ move(data, addr);
1470 }
1471 }
1472 }
1473
1474 void LIRGenerator::do_UnsafeGetAndSetObject(UnsafeGetAndSetObject* x) {
1475 BasicType type = x->basic_type();
1476 LIRItem src(x->object(), this);
1477 LIRItem off(x->offset(), this);
1478 LIRItem value(x->value(), this);
1479
1480 src.load_item();
1481 value.load_item();
1482 off.load_nonconstant();
1483
1484 LIR_Opr dst = rlock_result(x, type);
1485 LIR_Opr data = value.result();
1486 bool is_obj = (type == T_ARRAY || type == T_OBJECT);
1487 LIR_Opr offset = off.result();
1488
1489 assert (type == T_INT || (!x->is_add() && is_obj) LP64_ONLY( || type == T_LONG ), "unexpected type");
1490
1491 LIR_Opr src_op = src.result();
1492 src_op = shenandoah_write_barrier(src_op, NULL, false);
1493 if (is_obj) {
1494 data = shenandoah_read_barrier(data, NULL, true);
1495 }
1496
1497 LIR_Address* addr;
1498 if (offset->is_constant()) {
1499 #ifdef _LP64
1500 jlong c = offset->as_jlong();
1501 if ((jlong)((jint)c) == c) {
1502 addr = new LIR_Address(src_op, (jint)c, type);
1503 } else {
1504 LIR_Opr tmp = new_register(T_LONG);
1505 __ move(offset, tmp);
1506 addr = new LIR_Address(src_op, tmp, type);
1507 }
1508 #else
1509 addr = new LIR_Address(src_op, offset->as_jint(), type);
1510 #endif
1511 } else {
1512 addr = new LIR_Address(src_op, offset, type);
1513 }
1514
1515 // Because we want a 2-arg form of xchg and xadd
1516 __ move(data, dst);
1517
1518 if (x->is_add()) {
1519 __ xadd(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1520 } else {
1521 if (is_obj) {
1522 // Do the pre-write barrier, if any.
1523 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1524 true /* do_load */, false /* patch */, NULL);
1525 }
1526 __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1527 if (is_obj) {
1528 // Seems to be a precise address
1529 post_barrier(LIR_OprFact::address(addr), data);
1530 }
1531 }
1532 }