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src/cpu/x86/vm/templateTable_x86_32.cpp
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rev 11463 : Backport Traversal GC
@@ -34,10 +34,13 @@
#include "prims/methodHandles.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/synchronizer.hpp"
#include "utilities/macros.hpp"
+#if INCLUDE_ALL_GCS
+#include "shenandoahBarrierSetAssembler_x86.hpp"
+#endif
#ifndef CC_INTERP
#define __ _masm->
//----------------------------------------------------------------------------------------------------
@@ -127,11 +130,10 @@
assert(val == noreg || val == rax, "parameter is just for looks");
switch (barrier) {
#if INCLUDE_ALL_GCS
case BarrierSet::G1SATBCT:
case BarrierSet::G1SATBCTLogging:
- case BarrierSet::ShenandoahBarrierSet:
{
// flatten object address if needed
// We do it regardless of precise because we need the registers
if (obj.index() == noreg && obj.disp() == 0) {
if (obj.base() != rdx) {
@@ -164,10 +166,45 @@
}
__ restore_bcp();
}
break;
+ case BarrierSet::ShenandoahBarrierSet:
+ {
+ // flatten object address if needed
+ // We do it regardless of precise because we need the registers
+ if (obj.index() == noreg && obj.disp() == 0) {
+ if (obj.base() != rdx) {
+ __ movl(rdx, obj.base());
+ }
+ } else {
+ __ leal(rdx, obj);
+ }
+ __ get_thread(rcx);
+ __ save_bcp();
+ if (ShenandoahSATBBarrier) {
+ __ g1_write_barrier_pre(rdx /* obj */,
+ rbx /* pre_val */,
+ rcx /* thread */,
+ rsi /* tmp */,
+ val != noreg /* tosca_live */,
+ false /* expand_call */);
+ }
+
+ // Do the actual store
+ // noreg means NULL
+ if (val == noreg) {
+ __ movptr(Address(rdx, 0), NULL_WORD);
+ // No post barrier for NULL
+ } else {
+ ShenandoahBarrierSetAssembler::bsasm()->storeval_barrier(_masm, val, rsi);
+ __ movl(Address(rdx, 0), val);
+ }
+ __ restore_bcp();
+
+ }
+ break;
#endif // INCLUDE_ALL_GCS
case BarrierSet::CardTableModRef:
case BarrierSet::CardTableExtension:
{
if (val == noreg) {
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