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src/cpu/aarch64/vm/aarch64.ad
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rev 12152 : [mq]: verification.patch
*** 3744,3759 ****
rtype = MacroAssembler::ret_type_double;
break;
}
}
! #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
MacroAssembler _masm(&cbuf); \
{ \
guarantee(INDEX == -1, "mode not permitted for volatile"); \
guarantee(DISP == 0, "mode not permitted for volatile"); \
guarantee(SCALE == 0, "mode not permitted for volatile"); \
__ INSN(REG, as_Register(BASE)); \
}
typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
--- 3744,3760 ----
rtype = MacroAssembler::ret_type_double;
break;
}
}
! #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN, STORE) \
MacroAssembler _masm(&cbuf); \
{ \
guarantee(INDEX == -1, "mode not permitted for volatile"); \
guarantee(DISP == 0, "mode not permitted for volatile"); \
guarantee(SCALE == 0, "mode not permitted for volatile"); \
+ if (STORE) { __ shenandoah_store_addr_check(as_Register(BASE)); } \
__ INSN(REG, as_Register(BASE)); \
}
typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
*** 3761,3771 ****
MacroAssembler::SIMD_RegVariant T, const Address &adr);
// Used for all non-volatile memory accesses. The use of
// $mem->opcode() to discover whether this pattern uses sign-extended
// offsets is something of a kludge.
! static void loadStore(MacroAssembler masm, mem_insn insn,
Register reg, int opcode,
Register base, int index, int size, int disp)
{
Address::extend scale;
--- 3762,3772 ----
MacroAssembler::SIMD_RegVariant T, const Address &adr);
// Used for all non-volatile memory accesses. The use of
// $mem->opcode() to discover whether this pattern uses sign-extended
// offsets is something of a kludge.
! static void loadStore(MacroAssembler masm, mem_insn insn, bool store,
Register reg, int opcode,
Register base, int index, int size, int disp)
{
Address::extend scale;
*** 3781,3799 ****
break;
default:
scale = Address::lsl(size);
}
if (index == -1) {
(masm.*insn)(reg, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode: disp = %d", disp);
(masm.*insn)(reg, Address(base, as_Register(index), scale));
}
}
! static void loadStore(MacroAssembler masm, mem_float_insn insn,
FloatRegister reg, int opcode,
Register base, int index, int size, int disp)
{
Address::extend scale;
--- 3782,3801 ----
break;
default:
scale = Address::lsl(size);
}
+ if (store) masm.shenandoah_store_addr_check(base);
if (index == -1) {
(masm.*insn)(reg, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode: disp = %d", disp);
(masm.*insn)(reg, Address(base, as_Register(index), scale));
}
}
! static void loadStore(MacroAssembler masm, mem_float_insn insn, bool store,
FloatRegister reg, int opcode,
Register base, int index, int size, int disp)
{
Address::extend scale;
*** 3804,3825 ****
break;
default:
scale = Address::lsl(size);
}
if (index == -1) {
(masm.*insn)(reg, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode: disp = %d", disp);
(masm.*insn)(reg, Address(base, as_Register(index), scale));
}
}
! static void loadStore(MacroAssembler masm, mem_vector_insn insn,
FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
int opcode, Register base, int index, int size, int disp)
{
if (index == -1) {
(masm.*insn)(reg, T, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode");
(masm.*insn)(reg, T, Address(base, as_Register(index), Address::lsl(size)));
--- 3806,3829 ----
break;
default:
scale = Address::lsl(size);
}
+ if (store) masm.shenandoah_store_addr_check(base);
if (index == -1) {
(masm.*insn)(reg, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode: disp = %d", disp);
(masm.*insn)(reg, Address(base, as_Register(index), scale));
}
}
! static void loadStore(MacroAssembler masm, mem_vector_insn insn, bool store,
FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
int opcode, Register base, int index, int size, int disp)
{
+ if (store) masm.shenandoah_store_addr_check(base);
if (index == -1) {
(masm.*insn)(reg, T, Address(base, disp));
} else {
assert(disp == 0, "unsupported address mode");
(masm.*insn)(reg, T, Address(base, as_Register(index), Address::lsl(size)));
*** 3873,4022 ****
// BEGIN Non-volatile memory access
enc_class aarch64_enc_ldrsbw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsbw, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsb(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsb, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrb(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrb(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrshw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrshw, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsh(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsh, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrh(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrh(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrw(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsw(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsw, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldr(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrs(vRegF dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrd(vRegD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvS(vecD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvD(vecD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvQ(vecX dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strb, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb0_ordered(memory mem) %{
MacroAssembler _masm(&cbuf);
__ membar(Assembler::StoreStore);
! loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strh(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strh, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strh0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strh, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strw(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strw, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strw0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strw, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_str(iRegL src, memory mem) %{
Register src_reg = as_Register($src$$reg);
--- 3877,4026 ----
// BEGIN Non-volatile memory access
enc_class aarch64_enc_ldrsbw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsbw, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsb(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsb, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrb(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrb(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrshw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrshw, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsh(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsh, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrh(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrh(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrw(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrsw(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsw, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldr(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrs(vRegF dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrd(vRegD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, false, dst_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvS(vecD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, false, dst_reg, MacroAssembler::S,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvD(vecD dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, false, dst_reg, MacroAssembler::D,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_ldrvQ(vecX dst, memory mem) %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, false, dst_reg, MacroAssembler::Q,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strb, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strb, true, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strb0_ordered(memory mem) %{
MacroAssembler _masm(&cbuf);
__ membar(Assembler::StoreStore);
! loadStore(_masm, &MacroAssembler::strb, true, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strh(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strh, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strh0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strh, true, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strw(iRegI src, memory mem) %{
Register src_reg = as_Register($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strw, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strw0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::strw, true, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_str(iRegL src, memory mem) %{
Register src_reg = as_Register($src$$reg);
*** 4026,4167 ****
MacroAssembler _masm(&cbuf);
assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
__ mov(rscratch2, sp);
src_reg = rscratch2;
}
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_str0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::str, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strs(vRegF src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strs, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strd(vRegD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strd, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvS(vecD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::S,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvD(vecD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::D,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvQ(vecX src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::Q,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
// END Non-volatile memory access
// volatile loads and stores
enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrb);
%}
enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrh);
%}
enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrw);
%}
enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb);
__ sxtbw(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb);
__ sxtb(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb);
%}
enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb);
%}
enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh);
__ sxthw(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh);
__ sxth(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh);
%}
enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh);
%}
enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw);
%}
enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw);
%}
enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldar);
%}
enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw);
__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
%}
enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldar);
__ fmovd(as_FloatRegister($dst$$reg), rscratch1);
%}
enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
Register src_reg = as_Register($src$$reg);
--- 4030,4171 ----
MacroAssembler _masm(&cbuf);
assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
__ mov(rscratch2, sp);
src_reg = rscratch2;
}
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_str0(memory mem) %{
MacroAssembler _masm(&cbuf);
! loadStore(_masm, &MacroAssembler::str, true, zr, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strs(vRegF src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strs, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strd(vRegD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::strd, true, src_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvS(vecD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, true, src_reg, MacroAssembler::S,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvD(vecD src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, true, src_reg, MacroAssembler::D,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
enc_class aarch64_enc_strvQ(vecX src, memory mem) %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, true, src_reg, MacroAssembler::Q,
$mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
// END Non-volatile memory access
// volatile loads and stores
enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrb, true);
%}
enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrh, true);
%}
enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrw, true);
%}
enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb, false);
__ sxtbw(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb, false);
__ sxtb(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb, false);
%}
enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarb, false);
%}
enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh, false);
__ sxthw(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
Register dst_reg = as_Register($dst$$reg);
MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh, false);
__ sxth(dst_reg, dst_reg);
%}
enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh, false);
%}
enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarh, false);
%}
enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw, false);
%}
enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw, false);
%}
enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldar, false);
%}
enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldarw, false);
__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
%}
enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, ldar, false);
__ fmovd(as_FloatRegister($dst$$reg), rscratch1);
%}
enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
Register src_reg = as_Register($src$$reg);
*** 4172,4202 ****
assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
__ mov(rscratch2, sp);
src_reg = rscratch2;
}
MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlr);
%}
enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
{
MacroAssembler _masm(&cbuf);
FloatRegister src_reg = as_FloatRegister($src$$reg);
__ fmovs(rscratch2, src_reg);
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrw);
%}
enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
{
MacroAssembler _masm(&cbuf);
FloatRegister src_reg = as_FloatRegister($src$$reg);
__ fmovd(rscratch2, src_reg);
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlr);
%}
// synchronized read/update encodings
enc_class aarch64_enc_ldaxr(iRegL dst, memory mem) %{
--- 4176,4206 ----
assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
__ mov(rscratch2, sp);
src_reg = rscratch2;
}
MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlr, true);
%}
enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
{
MacroAssembler _masm(&cbuf);
FloatRegister src_reg = as_FloatRegister($src$$reg);
__ fmovs(rscratch2, src_reg);
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlrw, true);
%}
enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
{
MacroAssembler _masm(&cbuf);
FloatRegister src_reg = as_FloatRegister($src$$reg);
__ fmovd(rscratch2, src_reg);
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
! rscratch1, stlr, true);
%}
// synchronized read/update encodings
enc_class aarch64_enc_ldaxr(iRegL dst, memory mem) %{
*** 4259,4286 ****
--- 4263,4293 ----
%}
enc_class aarch64_enc_cmpxchg(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
+ __ shenandoah_store_addr_check($mem$$base$$Register);
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ false, /*release*/ true,
/*weak*/ false, noreg);
%}
enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
+ __ shenandoah_store_addr_check($mem$$base$$Register);
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
Assembler::word, /*acquire*/ false, /*release*/ true,
/*weak*/ false, noreg);
%}
enc_class aarch64_enc_cmpxchg_oop_shenandoah(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval, iRegP tmp) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
Register tmp = $tmp$$Register;
+ __ shenandoah_store_check($mem$$base$$Register, $newval$$Register);
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
__ cmpxchg_oop_shenandoah($res$$base$$Register, $mem$$base$$Register, tmp, $newval$$Register,
false, /*acquire*/ true, /*release*/ true);
%}
*** 4289,4316 ****
--- 4296,4326 ----
// CompareAndSwap sequence to serve as a barrier on acquiring a
// lock.
enc_class aarch64_enc_cmpxchg_acq(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
+ __ shenandoah_store_addr_check($mem$$base$$Register);
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ true, /*release*/ true,
/*weak*/ false, noreg);
%}
enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
+ __ shenandoah_store_addr_check($mem$$base$$Register);
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
Assembler::word, /*acquire*/ true, /*release*/ true,
/*weak*/ false, noreg);
%}
enc_class aarch64_enc_cmpxchg_acq_oop_shenandoah(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval, iRegP tmp) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
Register tmp = $tmp$$Register;
+ __ shenandoah_store_check($mem$$base$$Register, $newval$$Register);
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
__ cmpxchg_oop_shenandoah($res$$base$$Register, $mem$$base$$Register, tmp, $newval$$Register,
false, /*acquire*/ true, /*release*/ true);
%}
*** 4743,4752 ****
--- 4753,4764 ----
Label object_has_monitor;
Label cas_failed;
assert_different_registers(oop, box, tmp, disp_hdr);
+ __ shenandoah_store_addr_check(oop);
+
// Load markOop from object into displaced_header.
__ ldr(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
// Always do locking in runtime.
if (EmitSync & 0x01) {
*** 4901,4910 ****
--- 4913,4924 ----
Label object_has_monitor;
Label cas_failed;
assert_different_registers(oop, box, tmp, disp_hdr);
+ __ shenandoah_store_addr_check(oop);
+
// Always do locking in runtime.
if (EmitSync & 0x01) {
__ cmp(oop, zr); // Oop can't be 0 here => always false.
return;
}
*** 8481,8492 ****
__ lea(rscratch1, Address(base, disp));
adr = Address(rscratch1, as_Register(index), scale);
}
}
! if (reg != rscratch2)
! __ shenandoah_store_check(reg, adr);
__ str(reg, adr);
%}
ins_pipe(istore_reg_mem);
--- 8495,8505 ----
__ lea(rscratch1, Address(base, disp));
adr = Address(rscratch1, as_Register(index), scale);
}
}
! __ shenandoah_store_check(adr, reg);
__ str(reg, adr);
%}
ins_pipe(istore_reg_mem);
*** 9050,9060 ****
"cnt $tmp, $tmp\t# vector (8B)\n\t"
"addv $tmp, $tmp\t# vector (8B)\n\t"
"mov $dst, $tmp\t# vector (1D)" %}
ins_encode %{
FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, tmp_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
%}
--- 9063,9073 ----
"cnt $tmp, $tmp\t# vector (8B)\n\t"
"addv $tmp, $tmp\t# vector (8B)\n\t"
"mov $dst, $tmp\t# vector (1D)" %}
ins_encode %{
FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, false, tmp_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
%}
*** 9093,9103 ****
"cnt $tmp, $tmp\t# vector (8B)\n\t"
"addv $tmp, $tmp\t# vector (8B)\n\t"
"mov $dst, $tmp\t# vector (1D)" %}
ins_encode %{
FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, tmp_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
%}
--- 9106,9116 ----
"cnt $tmp, $tmp\t# vector (8B)\n\t"
"addv $tmp, $tmp\t# vector (8B)\n\t"
"mov $dst, $tmp\t# vector (1D)" %}
ins_encode %{
FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
! loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, false, tmp_reg, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
%}
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