1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 #ifdef ASSERT
32 #include "gc/shared/collectedHeap.hpp"
33 #endif
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42
43 public:
44 using Assembler::mov;
45 using Assembler::movi;
46
47 protected:
48
49 // Support for VM calls
50 //
51 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
52 // may customize this version by overriding it for its purposes (e.g., to save/restore
53 // additional registers when doing a VM call).
54 virtual void call_VM_leaf_base(
55 address entry_point, // the entry point
56 int number_of_arguments, // the number of arguments to pop after the call
57 Label *retaddr = NULL
58 );
59
60 virtual void call_VM_leaf_base(
61 address entry_point, // the entry point
62 int number_of_arguments, // the number of arguments to pop after the call
63 Label &retaddr) {
64 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
65 }
66
67 // This is the base routine called by the different versions of call_VM. The interpreter
68 // may customize this version by overriding it for its purposes (e.g., to save/restore
69 // additional registers when doing a VM call).
70 //
71 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
72 // returns the register which contains the thread upon return. If a thread register has been
73 // specified, the return value will correspond to that register. If no last_java_sp is specified
74 // (noreg) than rsp will be used instead.
75 virtual void call_VM_base( // returns the register containing the thread upon return
76 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
77 Register java_thread, // the thread if computed before ; use noreg otherwise
78 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
79 address entry_point, // the entry point
80 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
81 bool check_exceptions // whether to check for pending exceptions after return
82 );
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
91
92 // Maximum size of class area in Metaspace when compressed
93 uint64_t use_XOR_for_compressed_class_base;
94
95 public:
96 MacroAssembler(CodeBuffer* code) : Assembler(code) {
97 use_XOR_for_compressed_class_base
98 = (operand_valid_for_logical_immediate(false /*is32*/,
99 (uint64_t)Universe::narrow_klass_base())
100 && ((uint64_t)Universe::narrow_klass_base()
101 > (1u << log2_intptr(CompressedClassSpaceSize))));
102 }
103
104 // Biased locking support
105 // lock_reg and obj_reg must be loaded up with the appropriate values.
106 // swap_reg is killed.
107 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
108 // Optional slow case is for implementations (interpreter and C1) which branch to
109 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
110 // Returns offset of first potentially-faulting instruction for null
111 // check info (currently consumed only by C1). If
112 // swap_reg_contains_mark is true then returns -1 as it is assumed
113 // the calling code has already passed any potential faults.
114 int biased_locking_enter(Register lock_reg, Register obj_reg,
115 Register swap_reg, Register tmp_reg,
116 bool swap_reg_contains_mark,
117 Label& done, Label* slow_case = NULL,
118 BiasedLockingCounters* counters = NULL);
119 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
120
121
122 // Helper functions for statistics gathering.
123 // Unconditional atomic increment.
124 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
125 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
126 lea(tmp1, counter_addr);
127 atomic_incw(tmp1, tmp2, tmp3);
128 }
129 // Load Effective Address
130 void lea(Register r, const Address &a) {
131 InstructionMark im(this);
132 code_section()->relocate(inst_mark(), a.rspec());
133 a.lea(this, r);
134 }
135
136 void addmw(Address a, Register incr, Register scratch) {
137 ldrw(scratch, a);
138 addw(scratch, scratch, incr);
139 strw(scratch, a);
140 }
141
142 // Add constant to memory word
143 void addmw(Address a, int imm, Register scratch) {
144 ldrw(scratch, a);
145 if (imm > 0)
146 addw(scratch, scratch, (unsigned)imm);
147 else
148 subw(scratch, scratch, (unsigned)-imm);
149 strw(scratch, a);
150 }
151
152 void bind(Label& L) {
153 Assembler::bind(L);
154 code()->clear_last_membar();
155 }
156
157 void membar(Membar_mask_bits order_constraint);
158
159 // Frame creation and destruction shared between JITs.
160 void build_frame(int framesize);
161 void remove_frame(int framesize);
162
163 virtual void _call_Unimplemented(address call_site) {
164 mov(rscratch2, call_site);
165 haltsim();
166 }
167
168 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
169
170 virtual void notify(int type);
171
172 // aliases defined in AARCH64 spec
173
174 template<class T>
175 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
176 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
177
178 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
179 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
180
181 void cset(Register Rd, Assembler::Condition cond) {
182 csinc(Rd, zr, zr, ~cond);
183 }
184 void csetw(Register Rd, Assembler::Condition cond) {
185 csincw(Rd, zr, zr, ~cond);
186 }
187
188 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
189 csneg(Rd, Rn, Rn, ~cond);
190 }
191 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
192 csnegw(Rd, Rn, Rn, ~cond);
193 }
194
195 inline void movw(Register Rd, Register Rn) {
196 if (Rd == sp || Rn == sp) {
197 addw(Rd, Rn, 0U);
198 } else {
199 orrw(Rd, zr, Rn);
200 }
201 }
202 inline void mov(Register Rd, Register Rn) {
203 assert(Rd != r31_sp && Rn != r31_sp, "should be");
204 if (Rd == Rn) {
205 } else if (Rd == sp || Rn == sp) {
206 add(Rd, Rn, 0U);
207 } else {
208 orr(Rd, zr, Rn);
209 }
210 }
211
212 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
213 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
214
215 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
216 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
217
218 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
219 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
220
221 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
222 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
223 }
224 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
226 }
227
228 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 bfmw(Rd, Rn, lsb, (lsb + width - 1));
230 }
231 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfm(Rd, Rn, lsb , (lsb + width - 1));
233 }
234
235 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
237 }
238 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
240 }
241
242 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
244 }
245 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfm(Rd, Rn, lsb , (lsb + width - 1));
247 }
248
249 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
251 }
252 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
254 }
255
256 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
257 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
258 }
259 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfm(Rd, Rn, lsb , (lsb + width - 1));
261 }
262
263 inline void asrw(Register Rd, Register Rn, unsigned imm) {
264 sbfmw(Rd, Rn, imm, 31);
265 }
266
267 inline void asr(Register Rd, Register Rn, unsigned imm) {
268 sbfm(Rd, Rn, imm, 63);
269 }
270
271 inline void lslw(Register Rd, Register Rn, unsigned imm) {
272 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
273 }
274
275 inline void lsl(Register Rd, Register Rn, unsigned imm) {
276 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
277 }
278
279 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
280 ubfmw(Rd, Rn, imm, 31);
281 }
282
283 inline void lsr(Register Rd, Register Rn, unsigned imm) {
284 ubfm(Rd, Rn, imm, 63);
285 }
286
287 inline void rorw(Register Rd, Register Rn, unsigned imm) {
288 extrw(Rd, Rn, Rn, imm);
289 }
290
291 inline void ror(Register Rd, Register Rn, unsigned imm) {
292 extr(Rd, Rn, Rn, imm);
293 }
294
295 inline void sxtbw(Register Rd, Register Rn) {
296 sbfmw(Rd, Rn, 0, 7);
297 }
298 inline void sxthw(Register Rd, Register Rn) {
299 sbfmw(Rd, Rn, 0, 15);
300 }
301 inline void sxtb(Register Rd, Register Rn) {
302 sbfm(Rd, Rn, 0, 7);
303 }
304 inline void sxth(Register Rd, Register Rn) {
305 sbfm(Rd, Rn, 0, 15);
306 }
307 inline void sxtw(Register Rd, Register Rn) {
308 sbfm(Rd, Rn, 0, 31);
309 }
310
311 inline void uxtbw(Register Rd, Register Rn) {
312 ubfmw(Rd, Rn, 0, 7);
313 }
314 inline void uxthw(Register Rd, Register Rn) {
315 ubfmw(Rd, Rn, 0, 15);
316 }
317 inline void uxtb(Register Rd, Register Rn) {
318 ubfm(Rd, Rn, 0, 7);
319 }
320 inline void uxth(Register Rd, Register Rn) {
321 ubfm(Rd, Rn, 0, 15);
322 }
323 inline void uxtw(Register Rd, Register Rn) {
324 ubfm(Rd, Rn, 0, 31);
325 }
326
327 inline void cmnw(Register Rn, Register Rm) {
328 addsw(zr, Rn, Rm);
329 }
330 inline void cmn(Register Rn, Register Rm) {
331 adds(zr, Rn, Rm);
332 }
333
334 inline void cmpw(Register Rn, Register Rm) {
335 subsw(zr, Rn, Rm);
336 }
337 inline void cmp(Register Rn, Register Rm) {
338 subs(zr, Rn, Rm);
339 }
340
341 inline void negw(Register Rd, Register Rn) {
342 subw(Rd, zr, Rn);
343 }
344
345 inline void neg(Register Rd, Register Rn) {
346 sub(Rd, zr, Rn);
347 }
348
349 inline void negsw(Register Rd, Register Rn) {
350 subsw(Rd, zr, Rn);
351 }
352
353 inline void negs(Register Rd, Register Rn) {
354 subs(Rd, zr, Rn);
355 }
356
357 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
358 addsw(zr, Rn, Rm, kind, shift);
359 }
360 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 adds(zr, Rn, Rm, kind, shift);
362 }
363
364 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
365 subsw(zr, Rn, Rm, kind, shift);
366 }
367 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 subs(zr, Rn, Rm, kind, shift);
369 }
370
371 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
372 subw(Rd, zr, Rn, kind, shift);
373 }
374
375 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
376 sub(Rd, zr, Rn, kind, shift);
377 }
378
379 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
380 subsw(Rd, zr, Rn, kind, shift);
381 }
382
383 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
384 subs(Rd, zr, Rn, kind, shift);
385 }
386
387 inline void mnegw(Register Rd, Register Rn, Register Rm) {
388 msubw(Rd, Rn, Rm, zr);
389 }
390 inline void mneg(Register Rd, Register Rn, Register Rm) {
391 msub(Rd, Rn, Rm, zr);
392 }
393
394 inline void mulw(Register Rd, Register Rn, Register Rm) {
395 maddw(Rd, Rn, Rm, zr);
396 }
397 inline void mul(Register Rd, Register Rn, Register Rm) {
398 madd(Rd, Rn, Rm, zr);
399 }
400
401 inline void smnegl(Register Rd, Register Rn, Register Rm) {
402 smsubl(Rd, Rn, Rm, zr);
403 }
404 inline void smull(Register Rd, Register Rn, Register Rm) {
405 smaddl(Rd, Rn, Rm, zr);
406 }
407
408 inline void umnegl(Register Rd, Register Rn, Register Rm) {
409 umsubl(Rd, Rn, Rm, zr);
410 }
411 inline void umull(Register Rd, Register Rn, Register Rm) {
412 umaddl(Rd, Rn, Rm, zr);
413 }
414
415 #define WRAP(INSN) \
416 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
417 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
418 nop(); \
419 Assembler::INSN(Rd, Rn, Rm, Ra); \
420 }
421
422 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
423 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
424 #undef WRAP
425
426
427 // macro assembly operations needed for aarch64
428
429 // first two private routines for loading 32 bit or 64 bit constants
430 private:
431
432 void mov_immediate64(Register dst, u_int64_t imm64);
433 void mov_immediate32(Register dst, u_int32_t imm32);
434
435 int push(unsigned int bitset, Register stack);
436 int pop(unsigned int bitset, Register stack);
437
438 void mov(Register dst, Address a);
439
440 public:
441 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
442 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
443
444 // Push and pop everything that might be clobbered by a native
445 // runtime call except rscratch1 and rscratch2. (They are always
446 // scratch, so we don't have to protect them.) Only save the lower
447 // 64 bits of each vector register.
448 void push_call_clobbered_registers();
449 void pop_call_clobbered_registers();
450
451 // now mov instructions for loading absolute addresses and 32 or
452 // 64 bit integers
453
454 inline void mov(Register dst, address addr) {
455 assert(Universe::heap() == NULL
456 || !Universe::heap()->is_in(addr), "use movptr for oop pointers");
457 mov_immediate64(dst, (uintptr_t)addr);
458 }
459
460 inline void mov(Register dst, u_int64_t imm64)
461 {
462 mov_immediate64(dst, imm64);
463 }
464
465 inline void movw(Register dst, u_int32_t imm32)
466 {
467 mov_immediate32(dst, imm32);
468 }
469
470 inline void mov(Register dst, long l)
471 {
472 mov(dst, (u_int64_t)l);
473 }
474
475 inline void mov(Register dst, int i)
476 {
477 mov(dst, (long)i);
478 }
479
480 void mov(Register dst, RegisterOrConstant src) {
481 if (src.is_register())
482 mov(dst, src.as_register());
483 else
484 mov(dst, src.as_constant());
485 }
486
487 void movptr(Register r, uintptr_t imm64);
488
489 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
490
491 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
492 orr(Vd, T, Vn, Vn);
493 }
494
495 public:
496
497 // Generalized Test Bit And Branch, including a "far" variety which
498 // spans more than 32KiB.
499 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
500 assert(cond == EQ || cond == NE, "must be");
501
502 if (far)
503 cond = ~cond;
504
505 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
506 if (cond == Assembler::EQ)
507 branch = &Assembler::tbz;
508 else
509 branch = &Assembler::tbnz;
510
511 if (far) {
512 Label L;
513 (this->*branch)(Rt, bitpos, L);
514 b(dest);
515 bind(L);
516 } else {
517 (this->*branch)(Rt, bitpos, dest);
518 }
519 }
520
521 // macro instructions for accessing and updating floating point
522 // status register
523 //
524 // FPSR : op1 == 011
525 // CRn == 0100
526 // CRm == 0100
527 // op2 == 001
528
529 inline void get_fpsr(Register reg)
530 {
531 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
532 }
533
534 inline void set_fpsr(Register reg)
535 {
536 msr(0b011, 0b0100, 0b0100, 0b001, reg);
537 }
538
539 inline void clear_fpsr()
540 {
541 msr(0b011, 0b0100, 0b0100, 0b001, zr);
542 }
543
544 // DCZID_EL0: op1 == 011
545 // CRn == 0000
546 // CRm == 0000
547 // op2 == 111
548 inline void get_dczid_el0(Register reg)
549 {
550 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
551 }
552
553 // CTR_EL0: op1 == 011
554 // CRn == 0000
555 // CRm == 0000
556 // op2 == 001
557 inline void get_ctr_el0(Register reg)
558 {
559 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
560 }
561
562 // idiv variant which deals with MINLONG as dividend and -1 as divisor
563 int corrected_idivl(Register result, Register ra, Register rb,
564 bool want_remainder, Register tmp = rscratch1);
565 int corrected_idivq(Register result, Register ra, Register rb,
566 bool want_remainder, Register tmp = rscratch1);
567
568 // Support for NULL-checks
569 //
570 // Generates code that causes a NULL OS exception if the content of reg is NULL.
571 // If the accessed location is M[reg + offset] and the offset is known, provide the
572 // offset. No explicit code generation is needed if the offset is within a certain
573 // range (0 <= offset <= page_size).
574
575 virtual void null_check(Register reg, int offset = -1);
576 static bool needs_explicit_null_check(intptr_t offset);
577
578 static address target_addr_for_insn(address insn_addr, unsigned insn);
579 static address target_addr_for_insn(address insn_addr) {
580 unsigned insn = *(unsigned*)insn_addr;
581 return target_addr_for_insn(insn_addr, insn);
582 }
583
584 // Required platform-specific helpers for Label::patch_instructions.
585 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
586 static int pd_patch_instruction_size(address branch, address target);
587 static void pd_patch_instruction(address branch, address target) {
588 pd_patch_instruction_size(branch, target);
589 }
590 static address pd_call_destination(address branch) {
591 return target_addr_for_insn(branch);
592 }
593 #ifndef PRODUCT
594 static void pd_print_patched_instruction(address branch);
595 #endif
596
597 static int patch_oop(address insn_addr, address o);
598
599 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
600
601 // The following 4 methods return the offset of the appropriate move instruction
602
603 // Support for fast byte/short loading with zero extension (depending on particular CPU)
604 int load_unsigned_byte(Register dst, Address src);
605 int load_unsigned_short(Register dst, Address src);
606
607 // Support for fast byte/short loading with sign extension (depending on particular CPU)
608 int load_signed_byte(Register dst, Address src);
609 int load_signed_short(Register dst, Address src);
610
611 int load_signed_byte32(Register dst, Address src);
612 int load_signed_short32(Register dst, Address src);
613
614 // Support for sign-extension (hi:lo = extend_sign(lo))
615 void extend_sign(Register hi, Register lo);
616
617 // Load and store values by size and signed-ness
618 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
619 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
620
621 // Support for inc/dec with optimal instruction selection depending on value
622
623 // x86_64 aliases an unqualified register/address increment and
624 // decrement to call incrementq and decrementq but also supports
625 // explicitly sized calls to incrementq/decrementq or
626 // incrementl/decrementl
627
628 // for aarch64 the proper convention would be to use
629 // increment/decrement for 64 bit operatons and
630 // incrementw/decrementw for 32 bit operations. so when porting
631 // x86_64 code we can leave calls to increment/decrement as is,
632 // replace incrementq/decrementq with increment/decrement and
633 // replace incrementl/decrementl with incrementw/decrementw.
634
635 // n.b. increment/decrement calls with an Address destination will
636 // need to use a scratch register to load the value to be
637 // incremented. increment/decrement calls which add or subtract a
638 // constant value greater than 2^12 will need to use a 2nd scratch
639 // register to hold the constant. so, a register increment/decrement
640 // may trash rscratch2 and an address increment/decrement trash
641 // rscratch and rscratch2
642
643 void decrementw(Address dst, int value = 1);
644 void decrementw(Register reg, int value = 1);
645
646 void decrement(Register reg, int value = 1);
647 void decrement(Address dst, int value = 1);
648
649 void incrementw(Address dst, int value = 1);
650 void incrementw(Register reg, int value = 1);
651
652 void increment(Register reg, int value = 1);
653 void increment(Address dst, int value = 1);
654
655
656 // Alignment
657 void align(int modulus);
658
659 // Stack frame creation/removal
660 void enter()
661 {
662 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
663 mov(rfp, sp);
664 }
665 void leave()
666 {
667 mov(sp, rfp);
668 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
669 }
670
671 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
672 // The pointer will be loaded into the thread register.
673 void get_thread(Register thread);
674
675
676 // Support for VM calls
677 //
678 // It is imperative that all calls into the VM are handled via the call_VM macros.
679 // They make sure that the stack linkage is setup correctly. call_VM's correspond
680 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
681
682
683 void call_VM(Register oop_result,
684 address entry_point,
685 bool check_exceptions = true);
686 void call_VM(Register oop_result,
687 address entry_point,
688 Register arg_1,
689 bool check_exceptions = true);
690 void call_VM(Register oop_result,
691 address entry_point,
692 Register arg_1, Register arg_2,
693 bool check_exceptions = true);
694 void call_VM(Register oop_result,
695 address entry_point,
696 Register arg_1, Register arg_2, Register arg_3,
697 bool check_exceptions = true);
698
699 // Overloadings with last_Java_sp
700 void call_VM(Register oop_result,
701 Register last_java_sp,
702 address entry_point,
703 int number_of_arguments = 0,
704 bool check_exceptions = true);
705 void call_VM(Register oop_result,
706 Register last_java_sp,
707 address entry_point,
708 Register arg_1, bool
709 check_exceptions = true);
710 void call_VM(Register oop_result,
711 Register last_java_sp,
712 address entry_point,
713 Register arg_1, Register arg_2,
714 bool check_exceptions = true);
715 void call_VM(Register oop_result,
716 Register last_java_sp,
717 address entry_point,
718 Register arg_1, Register arg_2, Register arg_3,
719 bool check_exceptions = true);
720
721 void get_vm_result (Register oop_result, Register thread);
722 void get_vm_result_2(Register metadata_result, Register thread);
723
724 // These always tightly bind to MacroAssembler::call_VM_base
725 // bypassing the virtual implementation
726 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
727 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
728 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
729 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
730 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
731
732 void call_VM_leaf(address entry_point,
733 int number_of_arguments = 0);
734 void call_VM_leaf(address entry_point,
735 Register arg_1);
736 void call_VM_leaf(address entry_point,
737 Register arg_1, Register arg_2);
738 void call_VM_leaf(address entry_point,
739 Register arg_1, Register arg_2, Register arg_3);
740
741 // These always tightly bind to MacroAssembler::call_VM_leaf_base
742 // bypassing the virtual implementation
743 void super_call_VM_leaf(address entry_point);
744 void super_call_VM_leaf(address entry_point, Register arg_1);
745 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
746 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
747 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
748
749 // last Java Frame (fills frame anchor)
750 void set_last_Java_frame(Register last_java_sp,
751 Register last_java_fp,
752 address last_java_pc,
753 Register scratch);
754
755 void set_last_Java_frame(Register last_java_sp,
756 Register last_java_fp,
757 Label &last_java_pc,
758 Register scratch);
759
760 void set_last_Java_frame(Register last_java_sp,
761 Register last_java_fp,
762 Register last_java_pc,
763 Register scratch);
764
765 void reset_last_Java_frame(Register thread);
766
767 // thread in the default location (rthread)
768 void reset_last_Java_frame(bool clear_fp);
769
770 // Stores
771 void store_check(Register obj); // store check for obj - register is destroyed afterwards
772 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
773
774 #if INCLUDE_ALL_GCS
775
776 void g1_write_barrier_pre(Register obj,
777 Register pre_val,
778 Register thread,
779 Register tmp,
780 bool tosca_live,
781 bool expand_call);
782
783 void g1_write_barrier_post(Register store_addr,
784 Register new_val,
785 Register thread,
786 Register tmp,
787 Register tmp2);
788
789 #endif // INCLUDE_ALL_GCS
790
791 // oop manipulations
792 void load_klass(Register dst, Register src);
793 void store_klass(Register dst, Register src);
794 void cmp_klass(Register oop, Register trial_klass, Register tmp);
795
796 void load_mirror(Register dst, Register method);
797
798 void load_heap_oop(Register dst, Address src);
799
800 void load_heap_oop_not_null(Register dst, Address src);
801 void store_heap_oop(Address dst, Register src);
802
803 // currently unimplemented
804 // Used for storing NULL. All other oop constants should be
805 // stored using routines that take a jobject.
806 void store_heap_oop_null(Address dst);
807
808 void load_prototype_header(Register dst, Register src);
809
810 void store_klass_gap(Register dst, Register src);
811
812 // This dummy is to prevent a call to store_heap_oop from
813 // converting a zero (like NULL) into a Register by giving
814 // the compiler two choices it can't resolve
815
816 void store_heap_oop(Address dst, void* dummy);
817
818 void encode_heap_oop(Register d, Register s);
819 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
820 void decode_heap_oop(Register d, Register s);
821 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
822 void encode_heap_oop_not_null(Register r);
823 void decode_heap_oop_not_null(Register r);
824 void encode_heap_oop_not_null(Register dst, Register src);
825 void decode_heap_oop_not_null(Register dst, Register src);
826
827 void set_narrow_oop(Register dst, jobject obj);
828
829 void encode_klass_not_null(Register r);
830 void decode_klass_not_null(Register r);
831 void encode_klass_not_null(Register dst, Register src);
832 void decode_klass_not_null(Register dst, Register src);
833
834 void set_narrow_klass(Register dst, Klass* k);
835
836 // if heap base register is used - reinit it with the correct value
837 void reinit_heapbase();
838
839 DEBUG_ONLY(void verify_heapbase(const char* msg);)
840
841 void push_CPU_state(bool save_vectors = false);
842 void pop_CPU_state(bool restore_vectors = false) ;
843
844 // Round up to a power of two
845 void round_to(Register reg, int modulus);
846
847 // allocation
848 void eden_allocate(
849 Register obj, // result: pointer to object after successful allocation
850 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
851 int con_size_in_bytes, // object size in bytes if known at compile time
852 Register t1, // temp register
853 Label& slow_case // continuation point if fast allocation fails
854 );
855 void tlab_allocate(
856 Register obj, // result: pointer to object after successful allocation
857 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
858 int con_size_in_bytes, // object size in bytes if known at compile time
859 Register t1, // temp register
860 Register t2, // temp register
861 Label& slow_case // continuation point if fast allocation fails
862 );
863 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
864 void verify_tlab();
865
866 void incr_allocated_bytes(Register thread,
867 Register var_size_in_bytes, int con_size_in_bytes,
868 Register t1 = noreg);
869
870 // interface method calling
871 void lookup_interface_method(Register recv_klass,
872 Register intf_klass,
873 RegisterOrConstant itable_index,
874 Register method_result,
875 Register scan_temp,
876 Label& no_such_interface);
877
878 // virtual method calling
879 // n.b. x86 allows RegisterOrConstant for vtable_index
880 void lookup_virtual_method(Register recv_klass,
881 RegisterOrConstant vtable_index,
882 Register method_result);
883
884 // Test sub_klass against super_klass, with fast and slow paths.
885
886 // The fast path produces a tri-state answer: yes / no / maybe-slow.
887 // One of the three labels can be NULL, meaning take the fall-through.
888 // If super_check_offset is -1, the value is loaded up from super_klass.
889 // No registers are killed, except temp_reg.
890 void check_klass_subtype_fast_path(Register sub_klass,
891 Register super_klass,
892 Register temp_reg,
893 Label* L_success,
894 Label* L_failure,
895 Label* L_slow_path,
896 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
897
898 // The rest of the type check; must be wired to a corresponding fast path.
899 // It does not repeat the fast path logic, so don't use it standalone.
900 // The temp_reg and temp2_reg can be noreg, if no temps are available.
901 // Updates the sub's secondary super cache as necessary.
902 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
903 void check_klass_subtype_slow_path(Register sub_klass,
904 Register super_klass,
905 Register temp_reg,
906 Register temp2_reg,
907 Label* L_success,
908 Label* L_failure,
909 bool set_cond_codes = false);
910
911 // Simplified, combined version, good for typical uses.
912 // Falls through on failure.
913 void check_klass_subtype(Register sub_klass,
914 Register super_klass,
915 Register temp_reg,
916 Label& L_success);
917
918 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
919
920
921 // Debugging
922
923 // only if +VerifyOops
924 void verify_oop(Register reg, const char* s = "broken oop");
925 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
926
927 // TODO: verify method and klass metadata (compare against vptr?)
928 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
929 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
930
931 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
932 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
933
934 // only if +VerifyFPU
935 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
936
937 // prints msg, dumps registers and stops execution
938 void stop(const char* msg, Label *l = NULL);
939
940 // prints msg and continues
941 void warn(const char* msg);
942
943 static void debug64(char* msg, int64_t pc, int64_t regs[]);
944
945 void untested() { stop("untested"); }
946
947 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
948
949 void should_not_reach_here() { stop("should not reach here"); }
950
951 // Stack overflow checking
952 void bang_stack_with_offset(int offset) {
953 // stack grows down, caller passes positive offset
954 assert(offset > 0, "must bang with negative offset");
955 mov(rscratch2, -offset);
956 str(zr, Address(sp, rscratch2));
957 }
958
959 // Writes to stack successive pages until offset reached to check for
960 // stack overflow + shadow pages. Also, clobbers tmp
961 void bang_stack_size(Register size, Register tmp);
962
963 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
964 Register tmp,
965 int offset);
966
967 // Support for serializing memory accesses between threads
968 void serialize_memory(Register thread, Register tmp);
969
970 // Arithmetics
971
972 void addptr(const Address &dst, int32_t src);
973 void cmpptr(Register src1, Address src2);
974
975 // Various forms of CAS
976
977 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
978 Label &suceed, Label *fail);
979
980 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
981 Label &suceed, Label *fail);
982
983 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
984 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
985 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
986 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
987
988 void atomic_xchg(Register prev, Register newv, Register addr);
989 void atomic_xchgw(Register prev, Register newv, Register addr);
990 void atomic_xchgal(Register prev, Register newv, Register addr);
991 void atomic_xchgalw(Register prev, Register newv, Register addr);
992
993 void orptr(Address adr, RegisterOrConstant src) {
994 ldr(rscratch2, adr);
995 if (src.is_register())
996 orr(rscratch2, rscratch2, src.as_register());
997 else
998 orr(rscratch2, rscratch2, src.as_constant());
999 str(rscratch2, adr);
1000 }
1001
1002 // A generic CAS; success or failure is in the EQ flag.
1003 // Clobbers rscratch1
1004 void cmpxchg(Register addr, Register expected, Register new_val,
1005 enum operand_size size,
1006 bool acquire, bool release, bool weak,
1007 Register result);
1008
1009 void cmpxchg_oop_shenandoah(Register res, Register addr, Register expected, Register new_val,
1010 bool narrow,
1011 bool acquire, bool release,
1012 Register tmp1 = rscratch1, Register tmp2 = rscratch2);
1013 // Calls
1014
1015 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1016
1017 static bool far_branches() {
1018 return ReservedCodeCacheSize > branch_range;
1019 }
1020
1021 // Jumps that can reach anywhere in the code cache.
1022 // Trashes tmp.
1023 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1024 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1025
1026 static int far_branch_size() {
1027 if (far_branches()) {
1028 return 3 * 4; // adrp, add, br
1029 } else {
1030 return 4;
1031 }
1032 }
1033
1034 // Emit the CompiledIC call idiom
1035 address ic_call(address entry, jint method_index = 0);
1036
1037 public:
1038
1039 // Data
1040
1041 void mov_metadata(Register dst, Metadata* obj);
1042 Address allocate_metadata_address(Metadata* obj);
1043 Address constant_oop_address(jobject obj);
1044
1045 void movoop(Register dst, jobject obj, bool immediate = false);
1046
1047 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1048 void kernel_crc32(Register crc, Register buf, Register len,
1049 Register table0, Register table1, Register table2, Register table3,
1050 Register tmp, Register tmp2, Register tmp3);
1051 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1052 void kernel_crc32c(Register crc, Register buf, Register len,
1053 Register table0, Register table1, Register table2, Register table3,
1054 Register tmp, Register tmp2, Register tmp3);
1055
1056 // Stack push and pop individual 64 bit registers
1057 void push(Register src);
1058 void pop(Register dst);
1059
1060 // push all registers onto the stack
1061 void pusha();
1062 void popa();
1063
1064 void repne_scan(Register addr, Register value, Register count,
1065 Register scratch);
1066 void repne_scanw(Register addr, Register value, Register count,
1067 Register scratch);
1068
1069 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1070 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1071
1072 // If a constant does not fit in an immediate field, generate some
1073 // number of MOV instructions and then perform the operation
1074 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1075 add_sub_imm_insn insn1,
1076 add_sub_reg_insn insn2);
1077 // Seperate vsn which sets the flags
1078 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1079 add_sub_imm_insn insn1,
1080 add_sub_reg_insn insn2);
1081
1082 #define WRAP(INSN) \
1083 void INSN(Register Rd, Register Rn, unsigned imm) { \
1084 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1085 } \
1086 \
1087 void INSN(Register Rd, Register Rn, Register Rm, \
1088 enum shift_kind kind, unsigned shift = 0) { \
1089 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1090 } \
1091 \
1092 void INSN(Register Rd, Register Rn, Register Rm) { \
1093 Assembler::INSN(Rd, Rn, Rm); \
1094 } \
1095 \
1096 void INSN(Register Rd, Register Rn, Register Rm, \
1097 ext::operation option, int amount = 0) { \
1098 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1099 }
1100
1101 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1102
1103 #undef WRAP
1104 #define WRAP(INSN) \
1105 void INSN(Register Rd, Register Rn, unsigned imm) { \
1106 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1107 } \
1108 \
1109 void INSN(Register Rd, Register Rn, Register Rm, \
1110 enum shift_kind kind, unsigned shift = 0) { \
1111 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1112 } \
1113 \
1114 void INSN(Register Rd, Register Rn, Register Rm) { \
1115 Assembler::INSN(Rd, Rn, Rm); \
1116 } \
1117 \
1118 void INSN(Register Rd, Register Rn, Register Rm, \
1119 ext::operation option, int amount = 0) { \
1120 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1121 }
1122
1123 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1124
1125 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1126 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1127 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1128 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1129
1130 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1131
1132 void tableswitch(Register index, jint lowbound, jint highbound,
1133 Label &jumptable, Label &jumptable_end, int stride = 1) {
1134 adr(rscratch1, jumptable);
1135 subsw(rscratch2, index, lowbound);
1136 subsw(zr, rscratch2, highbound - lowbound);
1137 br(Assembler::HS, jumptable_end);
1138 add(rscratch1, rscratch1, rscratch2,
1139 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1140 br(rscratch1);
1141 }
1142
1143 // Form an address from base + offset in Rd. Rd may or may not
1144 // actually be used: you must use the Address that is returned. It
1145 // is up to you to ensure that the shift provided matches the size
1146 // of your data.
1147 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1148
1149 // Return true iff an address is within the 48-bit AArch64 address
1150 // space.
1151 bool is_valid_AArch64_address(address a) {
1152 return ((uint64_t)a >> 48) == 0;
1153 }
1154
1155 // Load the base of the cardtable byte map into reg.
1156 void load_byte_map_base(Register reg);
1157
1158 // Prolog generator routines to support switch between x86 code and
1159 // generated ARM code
1160
1161 // routine to generate an x86 prolog for a stub function which
1162 // bootstraps into the generated ARM code which directly follows the
1163 // stub
1164 //
1165
1166 public:
1167 // enum used for aarch64--x86 linkage to define return type of x86 function
1168 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1169
1170 #ifdef BUILTIN_SIM
1171 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1172 #else
1173 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1174 #endif
1175
1176 // special version of call_VM_leaf_base needed for aarch64 simulator
1177 // where we need to specify both the gp and fp arg counts and the
1178 // return type so that the linkage routine from aarch64 to x86 and
1179 // back knows which aarch64 registers to copy to x86 registers and
1180 // which x86 result register to copy back to an aarch64 register
1181
1182 void call_VM_leaf_base1(
1183 address entry_point, // the entry point
1184 int number_of_gp_arguments, // the number of gp reg arguments to pass
1185 int number_of_fp_arguments, // the number of fp reg arguments to pass
1186 ret_type type, // the return type for the call
1187 Label* retaddr = NULL
1188 );
1189
1190 void ldr_constant(Register dest, const Address &const_addr) {
1191 if (NearCpool) {
1192 ldr(dest, const_addr);
1193 } else {
1194 unsigned long offset;
1195 adrp(dest, InternalAddress(const_addr.target()), offset);
1196 ldr(dest, Address(dest, offset));
1197 }
1198 }
1199
1200 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1201 address read_polling_page(Register r, relocInfo::relocType rtype);
1202
1203 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1204 void update_byte_crc32(Register crc, Register val, Register table);
1205 void update_word_crc32(Register crc, Register v, Register tmp,
1206 Register table0, Register table1, Register table2, Register table3,
1207 bool upper = false);
1208
1209 void string_compare(Register str1, Register str2,
1210 Register cnt1, Register cnt2, Register result,
1211 Register tmp1,
1212 FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1213
1214 void arrays_equals(Register a1, Register a2,
1215 Register result, Register cnt1,
1216 int elem_size, bool is_string);
1217
1218 void fill_words(Register base, Register cnt, Register value);
1219 void zero_words(Register base, u_int64_t cnt);
1220 void zero_words(Register base, Register cnt);
1221 void block_zero(Register base, Register cnt, bool is_large = false);
1222
1223 void byte_array_inflate(Register src, Register dst, Register len,
1224 FloatRegister vtmp1, FloatRegister vtmp2,
1225 FloatRegister vtmp3, Register tmp4);
1226
1227 void char_array_compress(Register src, Register dst, Register len,
1228 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1229 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1230 Register result);
1231
1232 void encode_iso_array(Register src, Register dst,
1233 Register len, Register result,
1234 FloatRegister Vtmp1, FloatRegister Vtmp2,
1235 FloatRegister Vtmp3, FloatRegister Vtmp4);
1236 void string_indexof(Register str1, Register str2,
1237 Register cnt1, Register cnt2,
1238 Register tmp1, Register tmp2,
1239 Register tmp3, Register tmp4,
1240 int int_cnt1, Register result, int ae);
1241
1242 void in_heap_check(Register r, Label &nope);
1243 void shenandoah_store_check(Register r, Address addr);
1244 void shenandoah_store_check(Address addr);
1245 void shenandoah_store_check(Register addr);
1246
1247 private:
1248 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1249 Register src1, Register src2);
1250 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1251 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1252 }
1253 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1254 Register y, Register y_idx, Register z,
1255 Register carry, Register product,
1256 Register idx, Register kdx);
1257 void multiply_128_x_128_loop(Register y, Register z,
1258 Register carry, Register carry2,
1259 Register idx, Register jdx,
1260 Register yz_idx1, Register yz_idx2,
1261 Register tmp, Register tmp3, Register tmp4,
1262 Register tmp7, Register product_hi);
1263 public:
1264 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1265 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1266 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1267 // ISB may be needed because of a safepoint
1268 void maybe_isb() { isb(); }
1269
1270 private:
1271 // Return the effective address r + (r1 << ext) + offset.
1272 // Uses rscratch2.
1273 Address offsetted_address(Register r, Register r1, Address::extend ext,
1274 int offset, int size);
1275
1276 private:
1277 // Returns an address on the stack which is reachable with a ldr/str of size
1278 // Uses rscratch2 if the address is not directly reachable
1279 Address spill_address(int size, int offset, Register tmp=rscratch2);
1280
1281 public:
1282 void spill(Register Rx, bool is64, int offset) {
1283 if (is64) {
1284 str(Rx, spill_address(8, offset));
1285 } else {
1286 strw(Rx, spill_address(4, offset));
1287 }
1288 }
1289 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1290 str(Vx, T, spill_address(1 << (int)T, offset));
1291 }
1292 void unspill(Register Rx, bool is64, int offset) {
1293 if (is64) {
1294 ldr(Rx, spill_address(8, offset));
1295 } else {
1296 ldrw(Rx, spill_address(4, offset));
1297 }
1298 }
1299 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1300 ldr(Vx, T, spill_address(1 << (int)T, offset));
1301 }
1302 void spill_copy128(int src_offset, int dst_offset,
1303 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1304 if (src_offset < 512 && (src_offset & 7) == 0 &&
1305 dst_offset < 512 && (dst_offset & 7) == 0) {
1306 ldp(tmp1, tmp2, Address(sp, src_offset));
1307 stp(tmp1, tmp2, Address(sp, dst_offset));
1308 } else {
1309 unspill(tmp1, true, src_offset);
1310 spill(tmp1, true, dst_offset);
1311 unspill(tmp1, true, src_offset+8);
1312 spill(tmp1, true, dst_offset+8);
1313 }
1314 }
1315 };
1316
1317 #ifdef ASSERT
1318 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1319 #endif
1320
1321 /**
1322 * class SkipIfEqual:
1323 *
1324 * Instantiating this class will result in assembly code being output that will
1325 * jump around any code emitted between the creation of the instance and it's
1326 * automatic destruction at the end of a scope block, depending on the value of
1327 * the flag passed to the constructor, which will be checked at run-time.
1328 */
1329 class SkipIfEqual {
1330 private:
1331 MacroAssembler* _masm;
1332 Label _label;
1333
1334 public:
1335 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1336 ~SkipIfEqual();
1337 };
1338
1339 struct tableswitch {
1340 Register _reg;
1341 int _insn_index; jint _first_key; jint _last_key;
1342 Label _after;
1343 Label _branches;
1344 };
1345
1346 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP