916
917 } else if (src->is_double_fpu()) {
918 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
919 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
920 if (pop_fpu_stack) __ fstp_d (dst_addr);
921 else __ fst_d (dst_addr);
922
923 } else {
924 ShouldNotReachHere();
925 }
926 }
927
928
929 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
930 LIR_Address* to_addr = dest->as_address_ptr();
931 PatchingStub* patch = NULL;
932 Register compressed_src = rscratch1;
933
934 if (type == T_ARRAY || type == T_OBJECT) {
935 __ verify_oop(src->as_register());
936 #ifdef _LP64
937 if (UseCompressedOops && !wide) {
938 __ movptr(compressed_src, src->as_register());
939 __ encode_heap_oop(compressed_src);
940 if (patch_code != lir_patch_none) {
941 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
942 }
943 }
944 #endif
945 }
946
947 if (patch_code != lir_patch_none) {
948 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
949 Address toa = as_Address(to_addr);
950 assert(toa.disp() != 0, "must have");
951 }
952
953 int null_check_here = code_offset();
954 switch (type) {
955 case T_FLOAT: {
956 if (src->is_single_xmm()) {
957 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
958 } else {
959 assert(src->is_single_fpu(), "must be");
960 assert(src->fpu_regnr() == 0, "argument must be on TOS");
961 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
962 else __ fst_s (as_Address(to_addr));
963 }
964 break;
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916
917 } else if (src->is_double_fpu()) {
918 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
919 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
920 if (pop_fpu_stack) __ fstp_d (dst_addr);
921 else __ fst_d (dst_addr);
922
923 } else {
924 ShouldNotReachHere();
925 }
926 }
927
928
929 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
930 LIR_Address* to_addr = dest->as_address_ptr();
931 PatchingStub* patch = NULL;
932 Register compressed_src = rscratch1;
933
934 if (type == T_ARRAY || type == T_OBJECT) {
935 __ verify_oop(src->as_register());
936 __ shenandoah_store_check(as_Address(to_addr), src->as_register());
937 #ifdef _LP64
938 if (UseCompressedOops && !wide) {
939 __ movptr(compressed_src, src->as_register());
940 __ encode_heap_oop(compressed_src);
941 if (patch_code != lir_patch_none) {
942 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
943 }
944 }
945 #endif
946 } else {
947 __ shenandoah_store_addr_check(to_addr->base()->as_pointer_register());
948 }
949
950 if (patch_code != lir_patch_none) {
951 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
952 Address toa = as_Address(to_addr);
953 assert(toa.disp() != 0, "must have");
954 }
955
956 int null_check_here = code_offset();
957 switch (type) {
958 case T_FLOAT: {
959 if (src->is_single_xmm()) {
960 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
961 } else {
962 assert(src->is_single_fpu(), "must be");
963 assert(src->fpu_regnr() == 0, "argument must be on TOS");
964 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
965 else __ fst_s (as_Address(to_addr));
966 }
967 break;
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